## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Jul 08 02:23:56 Westeuropäische Sommerzeit 2006
##
vlib work
vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_types.vhdl"
vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_instr.vhdl"
vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/memory.vhdl"
vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx-behavior.vhdl"
vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen.vhdl"
vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/memory-preloaded.vhdl"
vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/clock_gen-behavior.vhdl"
vcom -explicit  -93 "E:/work/lib/HDL/Cores/CPUs/DLX/dlx_test-verifier.vhdl"
vsim -t 1ps   -lib work dlx_test
do {dlx_test.udo}
view wave
add wave *
view structure
view signals
run 1000ns