-- Xilinx Vhdl netlist produced by netgen application (version G.30)
-- Command       : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim vconfig.nga vconfig_timesim.vhd 
-- Input file    : vconfig.nga
-- Output file   : vconfig_timesim.vhd
-- Design name   : vconfig.nga
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : XC95288XL-6-TQ144 (Speed File: Version 3.0)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity vconfig is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RES : in STD_LOGIC := 'X'; 
    LOAD_PRESCALER : in STD_LOGIC := 'X'; 
    LOAD_SREG : in STD_LOGIC := 'X'; 
    DONE : in STD_LOGIC := 'X'; 
    nINIT_B : in STD_LOGIC := 'X'; 
    DOUT : out STD_LOGIC; 
    BUF_IS_EMPTY : out STD_LOGIC; 
    CCLK : out STD_LOGIC; 
    CCLK_PRESCALER : in STD_LOGIC_VECTOR ( 5 downto 0 ); 
    DIN : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
  );
end vconfig;

architecture Structure of vconfig is
  signal FCLKIO_0 : STD_LOGIC; 
  signal RES_IBUF : STD_LOGIC; 
  signal LOAD_PRESCALER_IBUF : STD_LOGIC; 
  signal LOAD_SREG_IBUF : STD_LOGIC; 
  signal CCLK_PRESCALER_0_IBUF : STD_LOGIC; 
  signal DIN_0_IBUF : STD_LOGIC; 
  signal DIN_1_IBUF : STD_LOGIC; 
  signal DIN_10_IBUF : STD_LOGIC; 
  signal DIN_11_IBUF : STD_LOGIC; 
  signal DIN_12_IBUF : STD_LOGIC; 
  signal DIN_13_IBUF : STD_LOGIC; 
  signal DIN_14_IBUF : STD_LOGIC; 
  signal DIN_15_IBUF : STD_LOGIC; 
  signal DIN_16_IBUF : STD_LOGIC; 
  signal DIN_17_IBUF : STD_LOGIC; 
  signal DIN_18_IBUF : STD_LOGIC; 
  signal DIN_19_IBUF : STD_LOGIC; 
  signal DIN_2_IBUF : STD_LOGIC; 
  signal DIN_20_IBUF : STD_LOGIC; 
  signal DIN_21_IBUF : STD_LOGIC; 
  signal DIN_22_IBUF : STD_LOGIC; 
  signal DIN_23_IBUF : STD_LOGIC; 
  signal DIN_24_IBUF : STD_LOGIC; 
  signal DIN_25_IBUF : STD_LOGIC; 
  signal DIN_26_IBUF : STD_LOGIC; 
  signal DIN_27_IBUF : STD_LOGIC; 
  signal DIN_28_IBUF : STD_LOGIC; 
  signal DIN_29_IBUF : STD_LOGIC; 
  signal DIN_3_IBUF : STD_LOGIC; 
  signal DIN_30_IBUF : STD_LOGIC; 
  signal DIN_31_IBUF : STD_LOGIC; 
  signal DIN_4_IBUF : STD_LOGIC; 
  signal DIN_5_IBUF : STD_LOGIC; 
  signal DIN_6_IBUF : STD_LOGIC; 
  signal DIN_7_IBUF : STD_LOGIC; 
  signal DIN_8_IBUF : STD_LOGIC; 
  signal DIN_9_IBUF : STD_LOGIC; 
  signal DONE_IBUF : STD_LOGIC; 
  signal nINIT_B_IBUF : STD_LOGIC; 
  signal CCLK_PRESCALER_1_IBUF : STD_LOGIC; 
  signal CCLK_PRESCALER_2_IBUF : STD_LOGIC; 
  signal CCLK_PRESCALER_3_IBUF : STD_LOGIC; 
  signal CCLK_PRESCALER_4_IBUF : STD_LOGIC; 
  signal CCLK_PRESCALER_5_IBUF : STD_LOGIC; 
  signal DOUT_OBUFE : STD_LOGIC; 
  signal DOUT_OBUFE_OE : STD_LOGIC; 
  signal BUF_IS_EMPTY_OBUF_Q : STD_LOGIC; 
  signal CCLK_OBUF : STD_LOGIC; 
  signal SCLK_Q : STD_LOGIC; 
  signal SCLK : STD_LOGIC; 
  signal SCLK_D : STD_LOGIC; 
  signal SCLK_tsimcreated_xor_Q : STD_LOGIC; 
  signal SCLK_SETF : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal SCLK_CE : STD_LOGIC; 
  signal SCLK_D1 : STD_LOGIC; 
  signal SCLK_D2 : STD_LOGIC; 
  signal readBufId_0_Q : STD_LOGIC; 
  signal readBufId_0_RSTF : STD_LOGIC; 
  signal readBufId_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal readBufId_0_D : STD_LOGIC; 
  signal readBufId_0_CLKF : STD_LOGIC; 
  signal Gnd : STD_LOGIC; 
  signal readBufId_0_CE : STD_LOGIC; 
  signal readBufId_0_D1 : STD_LOGIC; 
  signal readBufId_0_D2 : STD_LOGIC; 
  signal readBufId_0_D2_PT_0 : STD_LOGIC; 
  signal readBufId_0_D2_PT_1 : STD_LOGIC; 
  signal SHIFT_EN : STD_LOGIC; 
  signal buf_depth_0_Q : STD_LOGIC; 
  signal buf_depth_0_D : STD_LOGIC; 
  signal buf_depth_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal buf_depth_0_RSTF : STD_LOGIC; 
  signal buf_depth_0_SETF : STD_LOGIC; 
  signal buf_depth_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal buf_depth_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal buf_depth_0_CLKF : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal buf_depth_0_D1 : STD_LOGIC; 
  signal buf_depth_0_D2 : STD_LOGIC; 
  signal buf_depth_0_D2_PT_0 : STD_LOGIC; 
  signal buf_depth_0_D2_PT_1 : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_UIM : STD_LOGIC; 
  signal buf_depth_1_Q : STD_LOGIC; 
  signal buf_depth_1_D : STD_LOGIC; 
  signal buf_depth_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal buf_depth_1_RSTF : STD_LOGIC; 
  signal buf_depth_1_SETF : STD_LOGIC; 
  signal buf_depth_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal buf_depth_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal buf_depth_1_CLKF : STD_LOGIC; 
  signal buf_depth_1_D1 : STD_LOGIC; 
  signal buf_depth_1_D2 : STD_LOGIC; 
  signal buf_depth_1_D2_PT_0 : STD_LOGIC; 
  signal buf_depth_1_D2_PT_1 : STD_LOGIC; 
  signal buf_depth_1_buf_depth_1_RSTF_UIM : STD_LOGIC; 
  signal SHIFT_CNT_0_Q : STD_LOGIC; 
  signal SHIFT_CNT_0_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal SHIFT_CNT_0_EXP : STD_LOGIC; 
  signal SHIFT_CNT_0_D : STD_LOGIC; 
  signal SHIFT_CNT_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal SHIFT_CNT_0_RSTF : STD_LOGIC; 
  signal SHIFT_CNT_0_SETF : STD_LOGIC; 
  signal SHIFT_CNT_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SHIFT_CNT_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_CNT_0_CLKF : STD_LOGIC; 
  signal SHIFT_CNT_0_D1 : STD_LOGIC; 
  signal SHIFT_CNT_0_D2 : STD_LOGIC; 
  signal SHIFT_CNT_0_D2_PT_0 : STD_LOGIC; 
  signal EXP69_EXP : STD_LOGIC; 
  signal SHIFT_CNT_0_D2_PT_1 : STD_LOGIC; 
  signal count_0_Q : STD_LOGIC; 
  signal count_0_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal count_0_EXP : STD_LOGIC; 
  signal count_0_RSTF : STD_LOGIC; 
  signal count_0_SETF : STD_LOGIC; 
  signal count_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_0_D : STD_LOGIC; 
  signal count_0_D1 : STD_LOGIC; 
  signal count_0_D2 : STD_LOGIC; 
  signal EXP67_EXP : STD_LOGIC; 
  signal count_0_D2_PT_0 : STD_LOGIC; 
  signal count_0_D2_PT_1 : STD_LOGIC; 
  signal count_0_D2_PT_2 : STD_LOGIC; 
  signal count_4_Q : STD_LOGIC; 
  signal count_4_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal count_4_EXP : STD_LOGIC; 
  signal count_4_D : STD_LOGIC; 
  signal count_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_4_RSTF : STD_LOGIC; 
  signal count_4_SETF : STD_LOGIC; 
  signal count_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_4_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_4_D1 : STD_LOGIC; 
  signal count_4_D2 : STD_LOGIC; 
  signal CLK_SCALE_0_EXP : STD_LOGIC; 
  signal count_4_D2_PT_0 : STD_LOGIC; 
  signal count_4_D2_PT_1 : STD_LOGIC; 
  signal count_4_D2_PT_2 : STD_LOGIC; 
  signal SHIFT_CNT_1_Q : STD_LOGIC; 
  signal SHIFT_CNT_1_D : STD_LOGIC; 
  signal SHIFT_CNT_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal SHIFT_CNT_1_RSTF : STD_LOGIC; 
  signal SHIFT_CNT_1_SETF : STD_LOGIC; 
  signal SHIFT_CNT_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SHIFT_CNT_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_CNT_1_CLKF : STD_LOGIC; 
  signal SHIFT_CNT_1_D1 : STD_LOGIC; 
  signal SHIFT_CNT_1_D2 : STD_LOGIC; 
  signal SHIFT_CNT_1_D2_PT_0 : STD_LOGIC; 
  signal SHIFT_CNT_1_D2_PT_1 : STD_LOGIC; 
  signal SHIFT_CNT_2_EXP : STD_LOGIC; 
  signal SHIFT_CNT_1_D2_PT_2 : STD_LOGIC; 
  signal SHIFT_CNT_3_EXP : STD_LOGIC; 
  signal SHIFT_CNT_1_D2_PT_3 : STD_LOGIC; 
  signal SHIFT_CNT_2_Q : STD_LOGIC; 
  signal SHIFT_CNT_2_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal SHIFT_CNT_2_D : STD_LOGIC; 
  signal SHIFT_CNT_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal SHIFT_CNT_2_RSTF : STD_LOGIC; 
  signal SHIFT_CNT_2_SETF : STD_LOGIC; 
  signal SHIFT_CNT_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SHIFT_CNT_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_CNT_2_CLKF : STD_LOGIC; 
  signal SHIFT_CNT_2_D1 : STD_LOGIC; 
  signal SHIFT_CNT_2_D2 : STD_LOGIC; 
  signal SHIFT_CNT_2_D2_PT_0 : STD_LOGIC; 
  signal BUF_IS_EMPTY_OBUF_EXP : STD_LOGIC; 
  signal SHIFT_CNT_2_D2_PT_1 : STD_LOGIC; 
  signal SHIFT_CNT_3_Q : STD_LOGIC; 
  signal SHIFT_CNT_3_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal SHIFT_CNT_3_D : STD_LOGIC; 
  signal SHIFT_CNT_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal SHIFT_CNT_3_RSTF : STD_LOGIC; 
  signal SHIFT_CNT_3_SETF : STD_LOGIC; 
  signal SHIFT_CNT_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SHIFT_CNT_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_CNT_3_CLKF : STD_LOGIC; 
  signal SHIFT_CNT_3_D1 : STD_LOGIC; 
  signal SHIFT_CNT_3_D2 : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_EXP : STD_LOGIC; 
  signal SHIFT_CNT_3_D2_PT_0 : STD_LOGIC; 
  signal SHIFT_CNT_3_D2_PT_1 : STD_LOGIC; 
  signal count_1_Q : STD_LOGIC; 
  signal count_1_D : STD_LOGIC; 
  signal count_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_1_RSTF : STD_LOGIC; 
  signal count_1_SETF : STD_LOGIC; 
  signal count_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_1_D1 : STD_LOGIC; 
  signal count_1_D2 : STD_LOGIC; 
  signal CLK_SCALE_1_EXP : STD_LOGIC; 
  signal count_1_D2_PT_0 : STD_LOGIC; 
  signal count_1_D2_PT_1 : STD_LOGIC; 
  signal count_1_D2_PT_2 : STD_LOGIC; 
  signal count_1_D2_PT_3 : STD_LOGIC; 
  signal count_2_Q : STD_LOGIC; 
  signal count_2_D : STD_LOGIC; 
  signal count_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_2_RSTF : STD_LOGIC; 
  signal count_2_SETF : STD_LOGIC; 
  signal count_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_2_D1 : STD_LOGIC; 
  signal count_2_D2 : STD_LOGIC; 
  signal count_2_D2_PT_0 : STD_LOGIC; 
  signal count_2_D2_PT_1 : STD_LOGIC; 
  signal count_2_D2_PT_2 : STD_LOGIC; 
  signal count_2_D2_PT_3 : STD_LOGIC; 
  signal count_3_Q : STD_LOGIC; 
  signal count_3_D : STD_LOGIC; 
  signal count_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_3_RSTF : STD_LOGIC; 
  signal count_3_SETF : STD_LOGIC; 
  signal count_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_3_D1 : STD_LOGIC; 
  signal count_3_D2 : STD_LOGIC; 
  signal count_3_D2_PT_0 : STD_LOGIC; 
  signal count_3_D2_PT_1 : STD_LOGIC; 
  signal count_3_D2_PT_2 : STD_LOGIC; 
  signal count_3_D2_PT_3 : STD_LOGIC; 
  signal SHIFT_CNT_4_Q : STD_LOGIC; 
  signal SHIFT_CNT_4_D : STD_LOGIC; 
  signal SHIFT_CNT_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal SHIFT_CNT_4_RSTF : STD_LOGIC; 
  signal SHIFT_CNT_4_SETF : STD_LOGIC; 
  signal SHIFT_CNT_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SHIFT_CNT_4_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_CNT_4_CLKF : STD_LOGIC; 
  signal SHIFT_CNT_4_D1 : STD_LOGIC; 
  signal SHIFT_CNT_4_D2 : STD_LOGIC; 
  signal SHIFT_CNT_4_D2_PT_0 : STD_LOGIC; 
  signal SHIFT_CNT_4_D2_PT_1 : STD_LOGIC; 
  signal SHIFT_CNT_4_D2_PT_2 : STD_LOGIC; 
  signal count_5_Q : STD_LOGIC; 
  signal count_5_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal count_5_EXP : STD_LOGIC; 
  signal count_5_D : STD_LOGIC; 
  signal count_5_tsimcreated_xor_Q : STD_LOGIC; 
  signal count_5_RSTF : STD_LOGIC; 
  signal count_5_SETF : STD_LOGIC; 
  signal count_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal count_5_tsimcreated_prld_Q : STD_LOGIC; 
  signal count_5_D1 : STD_LOGIC; 
  signal count_5_D2 : STD_LOGIC; 
  signal CLK_SCALE_2_EXP : STD_LOGIC; 
  signal count_5_D2_PT_0 : STD_LOGIC; 
  signal count_5_D2_PT_1 : STD_LOGIC; 
  signal count_5_D2_PT_2 : STD_LOGIC; 
  signal writeBufId_0_Q : STD_LOGIC; 
  signal writeBufId_0_RSTF : STD_LOGIC; 
  signal writeBufId_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal writeBufId_0_D : STD_LOGIC; 
  signal writeBufId_0_CLKF : STD_LOGIC; 
  signal writeBufId_0_CE : STD_LOGIC; 
  signal writeBufId_0_D1 : STD_LOGIC; 
  signal writeBufId_0_D2 : STD_LOGIC; 
  signal writeBufId_0_D2_PT_0 : STD_LOGIC; 
  signal writeBufId_0_D2_PT_1 : STD_LOGIC; 
  signal CLK_SCALE_0_Q : STD_LOGIC; 
  signal CLK_SCALE_0_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal CLK_SCALE_0_D : STD_LOGIC; 
  signal CLK_SCALE_0_D1 : STD_LOGIC; 
  signal CLK_SCALE_0_D2 : STD_LOGIC; 
  signal CLK_SCALE_0_D2_PT_0 : STD_LOGIC; 
  signal CLK_SCALE_0_D2_PT_1 : STD_LOGIC; 
  signal CLK_SCALE_0_D2_PT_2 : STD_LOGIC; 
  signal CLK_SCALE_0_D2_PT_3 : STD_LOGIC; 
  signal CLK_SCALE_0_EXP_PT_0 : STD_LOGIC; 
  signal CLK_SCALE_0_EXP_PT_1 : STD_LOGIC; 
  signal REG_0_0_Q : STD_LOGIC; 
  signal REG_0_0 : STD_LOGIC; 
  signal REG_0_0_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_0_0_EXP : STD_LOGIC; 
  signal REG_0_0_D : STD_LOGIC; 
  signal REG_0_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_0_RSTF : STD_LOGIC; 
  signal REG_0_0_SETF : STD_LOGIC; 
  signal REG_0_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_0_CLKF : STD_LOGIC; 
  signal REG_0_0_D1 : STD_LOGIC; 
  signal REG_0_0_D2 : STD_LOGIC; 
  signal EXP22_EXP : STD_LOGIC; 
  signal REG_0_4 : STD_LOGIC; 
  signal REG_0_0_EXP_PT_0 : STD_LOGIC; 
  signal REG_0_0_EXP_PT_1 : STD_LOGIC; 
  signal REG_0_1_Q : STD_LOGIC; 
  signal REG_0_1 : STD_LOGIC; 
  signal REG_0_1_D : STD_LOGIC; 
  signal REG_0_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_1_RSTF : STD_LOGIC; 
  signal REG_0_1_SETF : STD_LOGIC; 
  signal REG_0_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_1_CLKF : STD_LOGIC; 
  signal REG_0_1_D1 : STD_LOGIC; 
  signal REG_0_1_D2 : STD_LOGIC; 
  signal EXP18_EXP : STD_LOGIC; 
  signal REG_0_1_D2_PT_0 : STD_LOGIC; 
  signal REG_0_1_D2_PT_1 : STD_LOGIC; 
  signal REG_0_1_D2_PT_2 : STD_LOGIC; 
  signal REG_0_10_Q : STD_LOGIC; 
  signal REG_0_10 : STD_LOGIC; 
  signal REG_0_10_D : STD_LOGIC; 
  signal REG_0_10_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_10_RSTF : STD_LOGIC; 
  signal REG_0_10_SETF : STD_LOGIC; 
  signal REG_0_10_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_10_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_10_CLKF : STD_LOGIC; 
  signal REG_0_10_D1 : STD_LOGIC; 
  signal REG_0_10_D2 : STD_LOGIC; 
  signal EXP65_EXP : STD_LOGIC; 
  signal REG_0_10_D2_PT_0 : STD_LOGIC; 
  signal REG_0_9 : STD_LOGIC; 
  signal REG_0_10_D2_PT_1 : STD_LOGIC; 
  signal REG_0_10_D2_PT_2 : STD_LOGIC; 
  signal REG_0_11_Q : STD_LOGIC; 
  signal REG_0_11 : STD_LOGIC; 
  signal REG_0_11_D : STD_LOGIC; 
  signal REG_0_11_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_11_RSTF : STD_LOGIC; 
  signal REG_0_11_SETF : STD_LOGIC; 
  signal REG_0_11_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_11_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_11_CLKF : STD_LOGIC; 
  signal REG_0_11_D1 : STD_LOGIC; 
  signal REG_0_11_D2 : STD_LOGIC; 
  signal SHIFT_EN_EXP : STD_LOGIC; 
  signal REG_0_11_D2_PT_0 : STD_LOGIC; 
  signal REG_0_11_D2_PT_1 : STD_LOGIC; 
  signal REG_0_11_D2_PT_2 : STD_LOGIC; 
  signal REG_0_12_Q : STD_LOGIC; 
  signal REG_0_12 : STD_LOGIC; 
  signal REG_0_12_D : STD_LOGIC; 
  signal REG_0_12_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_12_RSTF : STD_LOGIC; 
  signal REG_0_12_SETF : STD_LOGIC; 
  signal REG_0_12_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_12_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_12_CLKF : STD_LOGIC; 
  signal REG_0_12_D1 : STD_LOGIC; 
  signal REG_0_12_D2 : STD_LOGIC; 
  signal REG_0_13_EXP : STD_LOGIC; 
  signal REG_0_12_D2_PT_0 : STD_LOGIC; 
  signal REG_0_12_D2_PT_1 : STD_LOGIC; 
  signal REG_0_12_D2_PT_2 : STD_LOGIC; 
  signal REG_0_13_Q : STD_LOGIC; 
  signal REG_0_13 : STD_LOGIC; 
  signal REG_0_13_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_0_13_D : STD_LOGIC; 
  signal REG_0_13_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_13_RSTF : STD_LOGIC; 
  signal REG_0_13_SETF : STD_LOGIC; 
  signal REG_0_13_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_13_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_13_CLKF : STD_LOGIC; 
  signal REG_0_13_D1 : STD_LOGIC; 
  signal REG_0_13_D2 : STD_LOGIC; 
  signal CCLK_OBUF_EXP : STD_LOGIC; 
  signal REG_0_13_EXP_PT_0 : STD_LOGIC; 
  signal REG_0_13_EXP_PT_1 : STD_LOGIC; 
  signal REG_0_14_Q : STD_LOGIC; 
  signal REG_0_14 : STD_LOGIC; 
  signal REG_0_14_D : STD_LOGIC; 
  signal REG_0_14_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_14_RSTF : STD_LOGIC; 
  signal REG_0_14_SETF : STD_LOGIC; 
  signal REG_0_14_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_14_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_14_CLKF : STD_LOGIC; 
  signal REG_0_14_D1 : STD_LOGIC; 
  signal REG_0_14_D2 : STD_LOGIC; 
  signal EXP66_EXP : STD_LOGIC; 
  signal REG_0_14_D2_PT_0 : STD_LOGIC; 
  signal REG_0_14_D2_PT_1 : STD_LOGIC; 
  signal REG_0_14_D2_PT_2 : STD_LOGIC; 
  signal REG_0_15_Q : STD_LOGIC; 
  signal REG_0_15 : STD_LOGIC; 
  signal REG_0_15_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_0_15_EXP : STD_LOGIC; 
  signal REG_0_15_D : STD_LOGIC; 
  signal REG_0_15_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_15_RSTF : STD_LOGIC; 
  signal REG_0_15_SETF : STD_LOGIC; 
  signal REG_0_15_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_15_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_15_CLKF : STD_LOGIC; 
  signal REG_0_15_D1 : STD_LOGIC; 
  signal REG_0_15_D2 : STD_LOGIC; 
  signal EXP30_EXP : STD_LOGIC; 
  signal REG_0_15_D2_PT_0 : STD_LOGIC; 
  signal REG_0_15_D2_PT_1 : STD_LOGIC; 
  signal REG_0_16 : STD_LOGIC; 
  signal REG_0_16_Q : STD_LOGIC; 
  signal REG_0_16_D : STD_LOGIC; 
  signal REG_0_16_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_16_RSTF : STD_LOGIC; 
  signal REG_0_16_SETF : STD_LOGIC; 
  signal REG_0_16_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_16_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_16_CLKF : STD_LOGIC; 
  signal REG_0_16_D1 : STD_LOGIC; 
  signal REG_0_16_D2 : STD_LOGIC; 
  signal REG_0_16_D2_PT_0 : STD_LOGIC; 
  signal REG_0_17_EXP : STD_LOGIC; 
  signal REG_0_16_D2_PT_1 : STD_LOGIC; 
  signal REG_0_16_D2_PT_2 : STD_LOGIC; 
  signal REG_0_16_D2_PT_3 : STD_LOGIC; 
  signal REG_0_17_Q : STD_LOGIC; 
  signal REG_0_17 : STD_LOGIC; 
  signal REG_0_17_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_0_17_D : STD_LOGIC; 
  signal REG_0_17_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_17_RSTF : STD_LOGIC; 
  signal REG_0_17_SETF : STD_LOGIC; 
  signal REG_0_17_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_17_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_17_CLKF : STD_LOGIC; 
  signal REG_0_17_D1 : STD_LOGIC; 
  signal REG_0_17_D2 : STD_LOGIC; 
  signal EXP29_EXP : STD_LOGIC; 
  signal REG_0_17_D2_PT_0 : STD_LOGIC; 
  signal REG_0_17_D2_PT_1 : STD_LOGIC; 
  signal REG_0_18_Q : STD_LOGIC; 
  signal REG_0_18 : STD_LOGIC; 
  signal REG_0_18_D : STD_LOGIC; 
  signal REG_0_18_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_18_RSTF : STD_LOGIC; 
  signal REG_0_18_SETF : STD_LOGIC; 
  signal REG_0_18_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_18_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_18_CLKF : STD_LOGIC; 
  signal REG_0_18_D1 : STD_LOGIC; 
  signal REG_0_18_D2 : STD_LOGIC; 
  signal EXP32_EXP : STD_LOGIC; 
  signal REG_0_18_D2_PT_0 : STD_LOGIC; 
  signal REG_0_18_D2_PT_1 : STD_LOGIC; 
  signal REG_0_18_D2_PT_2 : STD_LOGIC; 
  signal REG_0_19_Q : STD_LOGIC; 
  signal REG_0_19 : STD_LOGIC; 
  signal REG_0_19_D : STD_LOGIC; 
  signal REG_0_19_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_19_RSTF : STD_LOGIC; 
  signal REG_0_19_SETF : STD_LOGIC; 
  signal REG_0_19_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_19_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_19_CLKF : STD_LOGIC; 
  signal REG_0_19_D1 : STD_LOGIC; 
  signal REG_0_19_D2 : STD_LOGIC; 
  signal state_0_EXP : STD_LOGIC; 
  signal REG_0_19_D2_PT_0 : STD_LOGIC; 
  signal REG_0_19_D2_PT_1 : STD_LOGIC; 
  signal REG_0_19_D2_PT_2 : STD_LOGIC; 
  signal REG_0_2_Q : STD_LOGIC; 
  signal REG_0_2 : STD_LOGIC; 
  signal REG_0_2_D : STD_LOGIC; 
  signal REG_0_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_2_RSTF : STD_LOGIC; 
  signal REG_0_2_SETF : STD_LOGIC; 
  signal REG_0_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_2_CLKF : STD_LOGIC; 
  signal REG_0_2_D1 : STD_LOGIC; 
  signal REG_0_2_D2 : STD_LOGIC; 
  signal REG_0_3_EXP : STD_LOGIC; 
  signal REG_0_2_D2_PT_0 : STD_LOGIC; 
  signal REG_0_2_D2_PT_1 : STD_LOGIC; 
  signal REG_0_2_D2_PT_2 : STD_LOGIC; 
  signal REG_0_20_Q : STD_LOGIC; 
  signal REG_0_20 : STD_LOGIC; 
  signal REG_0_20_D : STD_LOGIC; 
  signal REG_0_20_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_20_RSTF : STD_LOGIC; 
  signal REG_0_20_SETF : STD_LOGIC; 
  signal REG_0_20_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_20_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_20_CLKF : STD_LOGIC; 
  signal REG_0_20_D1 : STD_LOGIC; 
  signal REG_0_20_D2 : STD_LOGIC; 
  signal EXP31_EXP : STD_LOGIC; 
  signal REG_0_20_D2_PT_0 : STD_LOGIC; 
  signal REG_0_20_D2_PT_1 : STD_LOGIC; 
  signal REG_0_20_D2_PT_2 : STD_LOGIC; 
  signal REG_0_21_Q : STD_LOGIC; 
  signal REG_0_21 : STD_LOGIC; 
  signal REG_0_21_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_0_21_EXP : STD_LOGIC; 
  signal REG_0_21_D : STD_LOGIC; 
  signal REG_0_21_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_21_RSTF : STD_LOGIC; 
  signal REG_0_21_SETF : STD_LOGIC; 
  signal REG_0_21_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_21_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_21_CLKF : STD_LOGIC; 
  signal REG_0_21_D1 : STD_LOGIC; 
  signal REG_0_21_D2 : STD_LOGIC; 
  signal EXP34_EXP : STD_LOGIC; 
  signal REG_0_21_D2_PT_0 : STD_LOGIC; 
  signal REG_0_21_D2_PT_1 : STD_LOGIC; 
  signal REG_0_22 : STD_LOGIC; 
  signal REG_0_22_Q : STD_LOGIC; 
  signal REG_0_22_D : STD_LOGIC; 
  signal REG_0_22_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_22_RSTF : STD_LOGIC; 
  signal REG_0_22_SETF : STD_LOGIC; 
  signal REG_0_22_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_22_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_22_CLKF : STD_LOGIC; 
  signal REG_0_22_D1 : STD_LOGIC; 
  signal REG_0_22_D2 : STD_LOGIC; 
  signal REG_0_22_D2_PT_0 : STD_LOGIC; 
  signal REG_0_23_EXP : STD_LOGIC; 
  signal REG_0_22_D2_PT_1 : STD_LOGIC; 
  signal REG_0_22_D2_PT_2 : STD_LOGIC; 
  signal REG_0_22_D2_PT_3 : STD_LOGIC; 
  signal REG_0_23_Q : STD_LOGIC; 
  signal REG_0_23 : STD_LOGIC; 
  signal REG_0_23_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_0_23_D : STD_LOGIC; 
  signal REG_0_23_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_23_RSTF : STD_LOGIC; 
  signal REG_0_23_SETF : STD_LOGIC; 
  signal REG_0_23_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_23_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_23_CLKF : STD_LOGIC; 
  signal REG_0_23_D1 : STD_LOGIC; 
  signal REG_0_23_D2 : STD_LOGIC; 
  signal EXP33_EXP : STD_LOGIC; 
  signal REG_0_23_D2_PT_0 : STD_LOGIC; 
  signal REG_0_23_D2_PT_1 : STD_LOGIC; 
  signal REG_0_24_Q : STD_LOGIC; 
  signal REG_0_24 : STD_LOGIC; 
  signal REG_0_24_D : STD_LOGIC; 
  signal REG_0_24_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_24_RSTF : STD_LOGIC; 
  signal REG_0_24_SETF : STD_LOGIC; 
  signal REG_0_24_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_24_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_24_CLKF : STD_LOGIC; 
  signal REG_0_24_D1 : STD_LOGIC; 
  signal REG_0_24_D2 : STD_LOGIC; 
  signal EXP36_EXP : STD_LOGIC; 
  signal REG_0_24_D2_PT_0 : STD_LOGIC; 
  signal REG_0_24_D2_PT_1 : STD_LOGIC; 
  signal REG_0_24_D2_PT_2 : STD_LOGIC; 
  signal REG_0_25_Q : STD_LOGIC; 
  signal REG_0_25 : STD_LOGIC; 
  signal REG_0_25_D : STD_LOGIC; 
  signal REG_0_25_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_25_RSTF : STD_LOGIC; 
  signal REG_0_25_SETF : STD_LOGIC; 
  signal REG_0_25_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_25_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_25_CLKF : STD_LOGIC; 
  signal REG_0_25_D1 : STD_LOGIC; 
  signal REG_0_25_D2 : STD_LOGIC; 
  signal state_1_EXP : STD_LOGIC; 
  signal REG_0_25_D2_PT_0 : STD_LOGIC; 
  signal REG_0_25_D2_PT_1 : STD_LOGIC; 
  signal REG_0_25_D2_PT_2 : STD_LOGIC; 
  signal REG_0_26_Q : STD_LOGIC; 
  signal REG_0_26 : STD_LOGIC; 
  signal REG_0_26_D : STD_LOGIC; 
  signal REG_0_26_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_26_RSTF : STD_LOGIC; 
  signal REG_0_26_SETF : STD_LOGIC; 
  signal REG_0_26_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_26_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_26_CLKF : STD_LOGIC; 
  signal REG_0_26_D1 : STD_LOGIC; 
  signal REG_0_26_D2 : STD_LOGIC; 
  signal EXP35_EXP : STD_LOGIC; 
  signal REG_0_26_D2_PT_0 : STD_LOGIC; 
  signal REG_0_26_D2_PT_1 : STD_LOGIC; 
  signal REG_0_26_D2_PT_2 : STD_LOGIC; 
  signal REG_0_27_Q : STD_LOGIC; 
  signal REG_0_27 : STD_LOGIC; 
  signal REG_0_27_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_0_27_EXP : STD_LOGIC; 
  signal REG_0_27_D : STD_LOGIC; 
  signal REG_0_27_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_27_RSTF : STD_LOGIC; 
  signal REG_0_27_SETF : STD_LOGIC; 
  signal REG_0_27_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_27_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_27_CLKF : STD_LOGIC; 
  signal REG_0_27_D1 : STD_LOGIC; 
  signal REG_0_27_D2 : STD_LOGIC; 
  signal EXP39_EXP : STD_LOGIC; 
  signal REG_0_27_D2_PT_0 : STD_LOGIC; 
  signal REG_0_27_D2_PT_1 : STD_LOGIC; 
  signal REG_1_23 : STD_LOGIC; 
  signal REG_0_28_Q : STD_LOGIC; 
  signal REG_0_28 : STD_LOGIC; 
  signal REG_0_28_D : STD_LOGIC; 
  signal REG_0_28_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_28_RSTF : STD_LOGIC; 
  signal REG_0_28_SETF : STD_LOGIC; 
  signal REG_0_28_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_28_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_28_CLKF : STD_LOGIC; 
  signal REG_0_28_D1 : STD_LOGIC; 
  signal REG_0_28_D2 : STD_LOGIC; 
  signal EXP26_EXP : STD_LOGIC; 
  signal REG_0_28_D2_PT_0 : STD_LOGIC; 
  signal REG_0_28_D2_PT_1 : STD_LOGIC; 
  signal REG_0_28_D2_PT_2 : STD_LOGIC; 
  signal REG_0_29_Q : STD_LOGIC; 
  signal REG_0_29 : STD_LOGIC; 
  signal REG_0_29_D : STD_LOGIC; 
  signal REG_0_29_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_29_RSTF : STD_LOGIC; 
  signal REG_0_29_SETF : STD_LOGIC; 
  signal REG_0_29_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_29_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_29_CLKF : STD_LOGIC; 
  signal REG_0_29_D1 : STD_LOGIC; 
  signal REG_0_29_D2 : STD_LOGIC; 
  signal REG_0_30_EXP : STD_LOGIC; 
  signal REG_0_29_D2_PT_0 : STD_LOGIC; 
  signal REG_0_29_D2_PT_1 : STD_LOGIC; 
  signal REG_0_29_D2_PT_2 : STD_LOGIC; 
  signal REG_0_3_Q : STD_LOGIC; 
  signal REG_0_3 : STD_LOGIC; 
  signal REG_0_3_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_0_3_D : STD_LOGIC; 
  signal REG_0_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_3_RSTF : STD_LOGIC; 
  signal REG_0_3_SETF : STD_LOGIC; 
  signal REG_0_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_3_CLKF : STD_LOGIC; 
  signal REG_0_3_D1 : STD_LOGIC; 
  signal REG_0_3_D2 : STD_LOGIC; 
  signal EXP23_EXP : STD_LOGIC; 
  signal REG_0_3_EXP_PT_0 : STD_LOGIC; 
  signal REG_0_3_EXP_PT_1 : STD_LOGIC; 
  signal REG_0_30_Q : STD_LOGIC; 
  signal REG_0_30 : STD_LOGIC; 
  signal REG_0_30_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_0_30_D : STD_LOGIC; 
  signal REG_0_30_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_30_RSTF : STD_LOGIC; 
  signal REG_0_30_SETF : STD_LOGIC; 
  signal REG_0_30_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_30_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_30_CLKF : STD_LOGIC; 
  signal REG_0_30_D1 : STD_LOGIC; 
  signal REG_0_30_D2 : STD_LOGIC; 
  signal EXP25_EXP : STD_LOGIC; 
  signal REG_0_30_EXP_PT_0 : STD_LOGIC; 
  signal REG_0_30_EXP_PT_1 : STD_LOGIC; 
  signal REG_0_31_Q : STD_LOGIC; 
  signal REG_0_31 : STD_LOGIC; 
  signal REG_0_31_D : STD_LOGIC; 
  signal REG_0_31_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_31_RSTF : STD_LOGIC; 
  signal REG_0_31_SETF : STD_LOGIC; 
  signal REG_0_31_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_31_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_31_CLKF : STD_LOGIC; 
  signal REG_0_31_D1 : STD_LOGIC; 
  signal REG_0_31_D2 : STD_LOGIC; 
  signal EXP24_EXP : STD_LOGIC; 
  signal REG_0_31_D2_PT_0 : STD_LOGIC; 
  signal REG_0_31_D2_PT_1 : STD_LOGIC; 
  signal REG_0_31_D2_PT_2 : STD_LOGIC; 
  signal REG_0_4_Q : STD_LOGIC; 
  signal REG_0_4_D : STD_LOGIC; 
  signal REG_0_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_4_RSTF : STD_LOGIC; 
  signal REG_0_4_SETF : STD_LOGIC; 
  signal REG_0_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_4_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_4_CLKF : STD_LOGIC; 
  signal REG_0_4_D1 : STD_LOGIC; 
  signal REG_0_4_D2 : STD_LOGIC; 
  signal REG_0_4_D2_PT_0 : STD_LOGIC; 
  signal REG_0_4_D2_PT_1 : STD_LOGIC; 
  signal REG_0_4_D2_PT_2 : STD_LOGIC; 
  signal REG_0_5_Q : STD_LOGIC; 
  signal REG_0_5 : STD_LOGIC; 
  signal REG_0_5_D : STD_LOGIC; 
  signal REG_0_5_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_5_RSTF : STD_LOGIC; 
  signal REG_0_5_SETF : STD_LOGIC; 
  signal REG_0_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_5_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_5_CLKF : STD_LOGIC; 
  signal REG_0_5_D1 : STD_LOGIC; 
  signal REG_0_5_D2 : STD_LOGIC; 
  signal EXP19_EXP : STD_LOGIC; 
  signal REG_0_5_D2_PT_0 : STD_LOGIC; 
  signal REG_0_5_D2_PT_1 : STD_LOGIC; 
  signal REG_0_5_D2_PT_2 : STD_LOGIC; 
  signal REG_0_6_Q : STD_LOGIC; 
  signal REG_0_6 : STD_LOGIC; 
  signal REG_0_6_D : STD_LOGIC; 
  signal REG_0_6_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_6_RSTF : STD_LOGIC; 
  signal REG_0_6_SETF : STD_LOGIC; 
  signal REG_0_6_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_6_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_6_CLKF : STD_LOGIC; 
  signal REG_0_6_D1 : STD_LOGIC; 
  signal REG_0_6_D2 : STD_LOGIC; 
  signal EXP20_EXP : STD_LOGIC; 
  signal REG_0_6_D2_PT_0 : STD_LOGIC; 
  signal EXP21_EXP : STD_LOGIC; 
  signal REG_0_6_D2_PT_1 : STD_LOGIC; 
  signal REG_0_6_D2_PT_2 : STD_LOGIC; 
  signal REG_0_6_D2_PT_3 : STD_LOGIC; 
  signal REG_0_7_Q : STD_LOGIC; 
  signal REG_0_7 : STD_LOGIC; 
  signal REG_0_7_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_0_7_EXP : STD_LOGIC; 
  signal REG_0_7_D : STD_LOGIC; 
  signal REG_0_7_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_7_RSTF : STD_LOGIC; 
  signal REG_0_7_SETF : STD_LOGIC; 
  signal REG_0_7_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_7_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_7_CLKF : STD_LOGIC; 
  signal REG_0_7_D1 : STD_LOGIC; 
  signal REG_0_7_D2 : STD_LOGIC; 
  signal EXP46_EXP : STD_LOGIC; 
  signal REG_0_7_D2_PT_0 : STD_LOGIC; 
  signal REG_0_7_D2_PT_1 : STD_LOGIC; 
  signal REG_0_8 : STD_LOGIC; 
  signal REG_0_8_Q : STD_LOGIC; 
  signal REG_0_8_D : STD_LOGIC; 
  signal REG_0_8_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_8_RSTF : STD_LOGIC; 
  signal REG_0_8_SETF : STD_LOGIC; 
  signal REG_0_8_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_8_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_8_CLKF : STD_LOGIC; 
  signal REG_0_8_D1 : STD_LOGIC; 
  signal REG_0_8_D2 : STD_LOGIC; 
  signal REG_0_8_D2_PT_0 : STD_LOGIC; 
  signal REG_0_9_EXP : STD_LOGIC; 
  signal REG_0_8_D2_PT_1 : STD_LOGIC; 
  signal REG_0_8_D2_PT_2 : STD_LOGIC; 
  signal REG_0_8_D2_PT_3 : STD_LOGIC; 
  signal REG_0_9_Q : STD_LOGIC; 
  signal REG_0_9_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_0_9_D : STD_LOGIC; 
  signal REG_0_9_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_0_9_RSTF : STD_LOGIC; 
  signal REG_0_9_SETF : STD_LOGIC; 
  signal REG_0_9_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_0_9_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_0_9_CLKF : STD_LOGIC; 
  signal REG_0_9_D1 : STD_LOGIC; 
  signal REG_0_9_D2 : STD_LOGIC; 
  signal EXP45_EXP : STD_LOGIC; 
  signal REG_0_9_D2_PT_0 : STD_LOGIC; 
  signal REG_0_9_D2_PT_1 : STD_LOGIC; 
  signal REG_1_0_Q : STD_LOGIC; 
  signal REG_1_0 : STD_LOGIC; 
  signal REG_1_0_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_1_0_EXP : STD_LOGIC; 
  signal REG_1_0_D : STD_LOGIC; 
  signal REG_1_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_0_RSTF : STD_LOGIC; 
  signal REG_1_0_SETF : STD_LOGIC; 
  signal REG_1_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_0_CLKF : STD_LOGIC; 
  signal REG_1_0_D1 : STD_LOGIC; 
  signal REG_1_0_D2 : STD_LOGIC; 
  signal EXP52_EXP : STD_LOGIC; 
  signal REG_1_4 : STD_LOGIC; 
  signal REG_1_0_EXP_PT_0 : STD_LOGIC; 
  signal REG_1_0_EXP_PT_1 : STD_LOGIC; 
  signal REG_1_1_Q : STD_LOGIC; 
  signal REG_1_1 : STD_LOGIC; 
  signal REG_1_1_D : STD_LOGIC; 
  signal REG_1_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_1_RSTF : STD_LOGIC; 
  signal REG_1_1_SETF : STD_LOGIC; 
  signal REG_1_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_1_CLKF : STD_LOGIC; 
  signal REG_1_1_D1 : STD_LOGIC; 
  signal REG_1_1_D2 : STD_LOGIC; 
  signal EXP48_EXP : STD_LOGIC; 
  signal REG_1_1_D2_PT_0 : STD_LOGIC; 
  signal REG_1_1_D2_PT_1 : STD_LOGIC; 
  signal REG_1_1_D2_PT_2 : STD_LOGIC; 
  signal REG_1_10_Q : STD_LOGIC; 
  signal REG_1_10 : STD_LOGIC; 
  signal REG_1_10_D : STD_LOGIC; 
  signal REG_1_10_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_10_RSTF : STD_LOGIC; 
  signal REG_1_10_SETF : STD_LOGIC; 
  signal REG_1_10_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_10_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_10_CLKF : STD_LOGIC; 
  signal REG_1_10_D1 : STD_LOGIC; 
  signal REG_1_10_D2 : STD_LOGIC; 
  signal EXP43_EXP : STD_LOGIC; 
  signal REG_1_10_D2_PT_0 : STD_LOGIC; 
  signal REG_1_9 : STD_LOGIC; 
  signal REG_1_10_D2_PT_1 : STD_LOGIC; 
  signal REG_1_10_D2_PT_2 : STD_LOGIC; 
  signal REG_1_11_Q : STD_LOGIC; 
  signal REG_1_11 : STD_LOGIC; 
  signal REG_1_11_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_1_11_EXP : STD_LOGIC; 
  signal REG_1_11_D : STD_LOGIC; 
  signal REG_1_11_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_11_RSTF : STD_LOGIC; 
  signal REG_1_11_SETF : STD_LOGIC; 
  signal REG_1_11_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_11_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_11_CLKF : STD_LOGIC; 
  signal REG_1_11_D1 : STD_LOGIC; 
  signal REG_1_11_D2 : STD_LOGIC; 
  signal EXP56_EXP : STD_LOGIC; 
  signal REG_1_11_D2_PT_0 : STD_LOGIC; 
  signal REG_1_11_D2_PT_1 : STD_LOGIC; 
  signal REG_1_12 : STD_LOGIC; 
  signal REG_1_12_Q : STD_LOGIC; 
  signal REG_1_12_D : STD_LOGIC; 
  signal REG_1_12_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_12_RSTF : STD_LOGIC; 
  signal REG_1_12_SETF : STD_LOGIC; 
  signal REG_1_12_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_12_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_12_CLKF : STD_LOGIC; 
  signal REG_1_12_D1 : STD_LOGIC; 
  signal REG_1_12_D2 : STD_LOGIC; 
  signal REG_1_12_D2_PT_0 : STD_LOGIC; 
  signal REG_1_13_EXP : STD_LOGIC; 
  signal REG_1_12_D2_PT_1 : STD_LOGIC; 
  signal REG_1_12_D2_PT_2 : STD_LOGIC; 
  signal REG_1_12_D2_PT_3 : STD_LOGIC; 
  signal REG_1_13_Q : STD_LOGIC; 
  signal REG_1_13 : STD_LOGIC; 
  signal REG_1_13_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_1_13_D : STD_LOGIC; 
  signal REG_1_13_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_13_RSTF : STD_LOGIC; 
  signal REG_1_13_SETF : STD_LOGIC; 
  signal REG_1_13_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_13_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_13_CLKF : STD_LOGIC; 
  signal REG_1_13_D1 : STD_LOGIC; 
  signal REG_1_13_D2 : STD_LOGIC; 
  signal EXP55_EXP : STD_LOGIC; 
  signal REG_1_13_D2_PT_0 : STD_LOGIC; 
  signal REG_1_13_D2_PT_1 : STD_LOGIC; 
  signal REG_1_14_Q : STD_LOGIC; 
  signal REG_1_14 : STD_LOGIC; 
  signal REG_1_14_D : STD_LOGIC; 
  signal REG_1_14_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_14_RSTF : STD_LOGIC; 
  signal REG_1_14_SETF : STD_LOGIC; 
  signal REG_1_14_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_14_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_14_CLKF : STD_LOGIC; 
  signal REG_1_14_D1 : STD_LOGIC; 
  signal REG_1_14_D2 : STD_LOGIC; 
  signal EXP58_EXP : STD_LOGIC; 
  signal REG_1_14_D2_PT_0 : STD_LOGIC; 
  signal REG_1_14_D2_PT_1 : STD_LOGIC; 
  signal REG_1_14_D2_PT_2 : STD_LOGIC; 
  signal REG_1_15_Q : STD_LOGIC; 
  signal REG_1_15 : STD_LOGIC; 
  signal REG_1_15_D : STD_LOGIC; 
  signal REG_1_15_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_15_RSTF : STD_LOGIC; 
  signal REG_1_15_SETF : STD_LOGIC; 
  signal REG_1_15_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_15_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_15_CLKF : STD_LOGIC; 
  signal REG_1_15_D1 : STD_LOGIC; 
  signal REG_1_15_D2 : STD_LOGIC; 
  signal EXP57_EXP : STD_LOGIC; 
  signal REG_1_15_D2_PT_0 : STD_LOGIC; 
  signal REG_1_15_D2_PT_1 : STD_LOGIC; 
  signal REG_1_15_D2_PT_2 : STD_LOGIC; 
  signal REG_1_16_Q : STD_LOGIC; 
  signal REG_1_16 : STD_LOGIC; 
  signal REG_1_16_D : STD_LOGIC; 
  signal REG_1_16_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_16_RSTF : STD_LOGIC; 
  signal REG_1_16_SETF : STD_LOGIC; 
  signal REG_1_16_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_16_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_16_CLKF : STD_LOGIC; 
  signal REG_1_16_D1 : STD_LOGIC; 
  signal REG_1_16_D2 : STD_LOGIC; 
  signal EXP54_EXP : STD_LOGIC; 
  signal REG_1_16_D2_PT_0 : STD_LOGIC; 
  signal REG_1_16_D2_PT_1 : STD_LOGIC; 
  signal REG_1_16_D2_PT_2 : STD_LOGIC; 
  signal REG_1_17_Q : STD_LOGIC; 
  signal REG_1_17 : STD_LOGIC; 
  signal REG_1_17_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_1_17_EXP : STD_LOGIC; 
  signal REG_1_17_D : STD_LOGIC; 
  signal REG_1_17_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_17_RSTF : STD_LOGIC; 
  signal REG_1_17_SETF : STD_LOGIC; 
  signal REG_1_17_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_17_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_17_CLKF : STD_LOGIC; 
  signal REG_1_17_D1 : STD_LOGIC; 
  signal REG_1_17_D2 : STD_LOGIC; 
  signal EXP61_EXP : STD_LOGIC; 
  signal REG_1_17_D2_PT_0 : STD_LOGIC; 
  signal REG_1_17_D2_PT_1 : STD_LOGIC; 
  signal REG_1_18 : STD_LOGIC; 
  signal REG_1_18_Q : STD_LOGIC; 
  signal REG_1_18_D : STD_LOGIC; 
  signal REG_1_18_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_18_RSTF : STD_LOGIC; 
  signal REG_1_18_SETF : STD_LOGIC; 
  signal REG_1_18_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_18_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_18_CLKF : STD_LOGIC; 
  signal REG_1_18_D1 : STD_LOGIC; 
  signal REG_1_18_D2 : STD_LOGIC; 
  signal REG_1_18_D2_PT_0 : STD_LOGIC; 
  signal REG_1_19_EXP : STD_LOGIC; 
  signal REG_1_18_D2_PT_1 : STD_LOGIC; 
  signal REG_1_18_D2_PT_2 : STD_LOGIC; 
  signal REG_1_18_D2_PT_3 : STD_LOGIC; 
  signal REG_1_19_Q : STD_LOGIC; 
  signal REG_1_19 : STD_LOGIC; 
  signal REG_1_19_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_1_19_D : STD_LOGIC; 
  signal REG_1_19_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_19_RSTF : STD_LOGIC; 
  signal REG_1_19_SETF : STD_LOGIC; 
  signal REG_1_19_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_19_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_19_CLKF : STD_LOGIC; 
  signal REG_1_19_D1 : STD_LOGIC; 
  signal REG_1_19_D2 : STD_LOGIC; 
  signal EXP60_EXP : STD_LOGIC; 
  signal REG_1_19_D2_PT_0 : STD_LOGIC; 
  signal REG_1_19_D2_PT_1 : STD_LOGIC; 
  signal REG_1_2_Q : STD_LOGIC; 
  signal REG_1_2 : STD_LOGIC; 
  signal REG_1_2_D : STD_LOGIC; 
  signal REG_1_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_2_RSTF : STD_LOGIC; 
  signal REG_1_2_SETF : STD_LOGIC; 
  signal REG_1_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_2_CLKF : STD_LOGIC; 
  signal REG_1_2_D1 : STD_LOGIC; 
  signal REG_1_2_D2 : STD_LOGIC; 
  signal REG_1_3_EXP : STD_LOGIC; 
  signal REG_1_2_D2_PT_0 : STD_LOGIC; 
  signal REG_1_2_D2_PT_1 : STD_LOGIC; 
  signal REG_1_2_D2_PT_2 : STD_LOGIC; 
  signal REG_1_20_Q : STD_LOGIC; 
  signal REG_1_20 : STD_LOGIC; 
  signal REG_1_20_D : STD_LOGIC; 
  signal REG_1_20_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_20_RSTF : STD_LOGIC; 
  signal REG_1_20_SETF : STD_LOGIC; 
  signal REG_1_20_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_20_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_20_CLKF : STD_LOGIC; 
  signal REG_1_20_D1 : STD_LOGIC; 
  signal REG_1_20_D2 : STD_LOGIC; 
  signal EXP63_EXP : STD_LOGIC; 
  signal REG_1_20_D2_PT_0 : STD_LOGIC; 
  signal REG_1_20_D2_PT_1 : STD_LOGIC; 
  signal REG_1_20_D2_PT_2 : STD_LOGIC; 
  signal REG_1_21_Q : STD_LOGIC; 
  signal REG_1_21 : STD_LOGIC; 
  signal REG_1_21_D : STD_LOGIC; 
  signal REG_1_21_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_21_RSTF : STD_LOGIC; 
  signal REG_1_21_SETF : STD_LOGIC; 
  signal REG_1_21_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_21_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_21_CLKF : STD_LOGIC; 
  signal REG_1_21_D1 : STD_LOGIC; 
  signal REG_1_21_D2 : STD_LOGIC; 
  signal EXP62_EXP : STD_LOGIC; 
  signal REG_1_21_D2_PT_0 : STD_LOGIC; 
  signal REG_1_21_D2_PT_1 : STD_LOGIC; 
  signal REG_1_21_D2_PT_2 : STD_LOGIC; 
  signal REG_1_22_Q : STD_LOGIC; 
  signal REG_1_22 : STD_LOGIC; 
  signal REG_1_22_D : STD_LOGIC; 
  signal REG_1_22_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_22_RSTF : STD_LOGIC; 
  signal REG_1_22_SETF : STD_LOGIC; 
  signal REG_1_22_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_22_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_22_CLKF : STD_LOGIC; 
  signal REG_1_22_D1 : STD_LOGIC; 
  signal REG_1_22_D2 : STD_LOGIC; 
  signal EXP59_EXP : STD_LOGIC; 
  signal REG_1_22_D2_PT_0 : STD_LOGIC; 
  signal REG_1_22_D2_PT_1 : STD_LOGIC; 
  signal REG_1_22_D2_PT_2 : STD_LOGIC; 
  signal REG_1_23_Q : STD_LOGIC; 
  signal REG_1_23_D : STD_LOGIC; 
  signal REG_1_23_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_23_RSTF : STD_LOGIC; 
  signal REG_1_23_SETF : STD_LOGIC; 
  signal REG_1_23_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_23_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_23_CLKF : STD_LOGIC; 
  signal REG_1_23_D1 : STD_LOGIC; 
  signal REG_1_23_D2 : STD_LOGIC; 
  signal REG_1_23_D2_PT_0 : STD_LOGIC; 
  signal REG_1_24_EXP : STD_LOGIC; 
  signal REG_1_23_D2_PT_1 : STD_LOGIC; 
  signal REG_1_23_D2_PT_2 : STD_LOGIC; 
  signal REG_1_23_D2_PT_3 : STD_LOGIC; 
  signal REG_1_24_Q : STD_LOGIC; 
  signal REG_1_24 : STD_LOGIC; 
  signal REG_1_24_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_1_24_D : STD_LOGIC; 
  signal REG_1_24_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_24_RSTF : STD_LOGIC; 
  signal REG_1_24_SETF : STD_LOGIC; 
  signal REG_1_24_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_24_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_24_CLKF : STD_LOGIC; 
  signal REG_1_24_D1 : STD_LOGIC; 
  signal REG_1_24_D2 : STD_LOGIC; 
  signal EXP38_EXP : STD_LOGIC; 
  signal REG_1_24_D2_PT_0 : STD_LOGIC; 
  signal REG_1_24_D2_PT_1 : STD_LOGIC; 
  signal REG_1_25_Q : STD_LOGIC; 
  signal REG_1_25 : STD_LOGIC; 
  signal REG_1_25_D : STD_LOGIC; 
  signal REG_1_25_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_25_RSTF : STD_LOGIC; 
  signal REG_1_25_SETF : STD_LOGIC; 
  signal REG_1_25_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_25_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_25_CLKF : STD_LOGIC; 
  signal REG_1_25_D1 : STD_LOGIC; 
  signal REG_1_25_D2 : STD_LOGIC; 
  signal EXP41_EXP : STD_LOGIC; 
  signal REG_1_25_D2_PT_0 : STD_LOGIC; 
  signal REG_1_25_D2_PT_1 : STD_LOGIC; 
  signal REG_1_25_D2_PT_2 : STD_LOGIC; 
  signal REG_1_26_Q : STD_LOGIC; 
  signal REG_1_26 : STD_LOGIC; 
  signal REG_1_26_D : STD_LOGIC; 
  signal REG_1_26_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_26_RSTF : STD_LOGIC; 
  signal REG_1_26_SETF : STD_LOGIC; 
  signal REG_1_26_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_26_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_26_CLKF : STD_LOGIC; 
  signal REG_1_26_D1 : STD_LOGIC; 
  signal REG_1_26_D2 : STD_LOGIC; 
  signal EXP40_EXP : STD_LOGIC; 
  signal REG_1_26_D2_PT_0 : STD_LOGIC; 
  signal REG_1_26_D2_PT_1 : STD_LOGIC; 
  signal REG_1_26_D2_PT_2 : STD_LOGIC; 
  signal REG_1_27_Q : STD_LOGIC; 
  signal REG_1_27 : STD_LOGIC; 
  signal REG_1_27_D : STD_LOGIC; 
  signal REG_1_27_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_27_RSTF : STD_LOGIC; 
  signal REG_1_27_SETF : STD_LOGIC; 
  signal REG_1_27_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_27_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_27_CLKF : STD_LOGIC; 
  signal REG_1_27_D1 : STD_LOGIC; 
  signal REG_1_27_D2 : STD_LOGIC; 
  signal EXP37_EXP : STD_LOGIC; 
  signal REG_1_27_D2_PT_0 : STD_LOGIC; 
  signal REG_1_27_D2_PT_1 : STD_LOGIC; 
  signal REG_1_27_D2_PT_2 : STD_LOGIC; 
  signal REG_1_28_Q : STD_LOGIC; 
  signal REG_1_28 : STD_LOGIC; 
  signal REG_1_28_D : STD_LOGIC; 
  signal REG_1_28_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_28_RSTF : STD_LOGIC; 
  signal REG_1_28_SETF : STD_LOGIC; 
  signal REG_1_28_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_28_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_28_CLKF : STD_LOGIC; 
  signal REG_1_28_D1 : STD_LOGIC; 
  signal REG_1_28_D2 : STD_LOGIC; 
  signal EXP68_EXP : STD_LOGIC; 
  signal REG_1_28_D2_PT_0 : STD_LOGIC; 
  signal REG_1_28_D2_PT_1 : STD_LOGIC; 
  signal REG_1_28_D2_PT_2 : STD_LOGIC; 
  signal REG_1_29_Q : STD_LOGIC; 
  signal REG_1_29 : STD_LOGIC; 
  signal REG_1_29_D : STD_LOGIC; 
  signal REG_1_29_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_29_RSTF : STD_LOGIC; 
  signal REG_1_29_SETF : STD_LOGIC; 
  signal REG_1_29_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_29_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_29_CLKF : STD_LOGIC; 
  signal REG_1_29_D1 : STD_LOGIC; 
  signal REG_1_29_D2 : STD_LOGIC; 
  signal EXP28_EXP : STD_LOGIC; 
  signal REG_1_29_D2_PT_0 : STD_LOGIC; 
  signal REG_1_29_D2_PT_1 : STD_LOGIC; 
  signal REG_1_29_D2_PT_2 : STD_LOGIC; 
  signal REG_1_3_Q : STD_LOGIC; 
  signal REG_1_3 : STD_LOGIC; 
  signal REG_1_3_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal REG_1_3_D : STD_LOGIC; 
  signal REG_1_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_3_RSTF : STD_LOGIC; 
  signal REG_1_3_SETF : STD_LOGIC; 
  signal REG_1_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_3_CLKF : STD_LOGIC; 
  signal REG_1_3_D1 : STD_LOGIC; 
  signal REG_1_3_D2 : STD_LOGIC; 
  signal EXP53_EXP : STD_LOGIC; 
  signal REG_1_3_EXP_PT_0 : STD_LOGIC; 
  signal REG_1_3_EXP_PT_1 : STD_LOGIC; 
  signal REG_1_30_Q : STD_LOGIC; 
  signal REG_1_30 : STD_LOGIC; 
  signal REG_1_30_D : STD_LOGIC; 
  signal REG_1_30_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_30_RSTF : STD_LOGIC; 
  signal REG_1_30_SETF : STD_LOGIC; 
  signal REG_1_30_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_30_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_30_CLKF : STD_LOGIC; 
  signal REG_1_30_D1 : STD_LOGIC; 
  signal REG_1_30_D2 : STD_LOGIC; 
  signal DOUT_OBUFE_EXP : STD_LOGIC; 
  signal REG_1_30_D2_PT_0 : STD_LOGIC; 
  signal REG_1_30_D2_PT_1 : STD_LOGIC; 
  signal REG_1_30_D2_PT_2 : STD_LOGIC; 
  signal REG_1_31_Q : STD_LOGIC; 
  signal REG_1_31 : STD_LOGIC; 
  signal REG_1_31_D : STD_LOGIC; 
  signal REG_1_31_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_31_RSTF : STD_LOGIC; 
  signal REG_1_31_SETF : STD_LOGIC; 
  signal REG_1_31_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_31_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_31_CLKF : STD_LOGIC; 
  signal REG_1_31_D1 : STD_LOGIC; 
  signal REG_1_31_D2 : STD_LOGIC; 
  signal EXP27_EXP : STD_LOGIC; 
  signal REG_1_31_D2_PT_0 : STD_LOGIC; 
  signal REG_1_31_D2_PT_1 : STD_LOGIC; 
  signal REG_1_31_D2_PT_2 : STD_LOGIC; 
  signal REG_1_4_Q : STD_LOGIC; 
  signal REG_1_4_D : STD_LOGIC; 
  signal REG_1_4_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_4_RSTF : STD_LOGIC; 
  signal REG_1_4_SETF : STD_LOGIC; 
  signal REG_1_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_4_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_4_CLKF : STD_LOGIC; 
  signal REG_1_4_D1 : STD_LOGIC; 
  signal REG_1_4_D2 : STD_LOGIC; 
  signal REG_1_4_D2_PT_0 : STD_LOGIC; 
  signal REG_1_4_D2_PT_1 : STD_LOGIC; 
  signal REG_1_4_D2_PT_2 : STD_LOGIC; 
  signal REG_1_5_Q : STD_LOGIC; 
  signal REG_1_5 : STD_LOGIC; 
  signal REG_1_5_D : STD_LOGIC; 
  signal REG_1_5_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_5_RSTF : STD_LOGIC; 
  signal REG_1_5_SETF : STD_LOGIC; 
  signal REG_1_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_5_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_5_CLKF : STD_LOGIC; 
  signal REG_1_5_D1 : STD_LOGIC; 
  signal REG_1_5_D2 : STD_LOGIC; 
  signal EXP49_EXP : STD_LOGIC; 
  signal REG_1_5_D2_PT_0 : STD_LOGIC; 
  signal REG_1_5_D2_PT_1 : STD_LOGIC; 
  signal REG_1_5_D2_PT_2 : STD_LOGIC; 
  signal REG_1_6_Q : STD_LOGIC; 
  signal REG_1_6 : STD_LOGIC; 
  signal REG_1_6_D : STD_LOGIC; 
  signal REG_1_6_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_6_RSTF : STD_LOGIC; 
  signal REG_1_6_SETF : STD_LOGIC; 
  signal REG_1_6_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_6_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_6_CLKF : STD_LOGIC; 
  signal REG_1_6_D1 : STD_LOGIC; 
  signal REG_1_6_D2 : STD_LOGIC; 
  signal EXP50_EXP : STD_LOGIC; 
  signal REG_1_6_D2_PT_0 : STD_LOGIC; 
  signal EXP51_EXP : STD_LOGIC; 
  signal REG_1_6_D2_PT_1 : STD_LOGIC; 
  signal REG_1_6_D2_PT_2 : STD_LOGIC; 
  signal REG_1_6_D2_PT_3 : STD_LOGIC; 
  signal REG_1_7_Q : STD_LOGIC; 
  signal REG_1_7 : STD_LOGIC; 
  signal REG_1_7_D : STD_LOGIC; 
  signal REG_1_7_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_7_RSTF : STD_LOGIC; 
  signal REG_1_7_SETF : STD_LOGIC; 
  signal REG_1_7_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_7_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_7_CLKF : STD_LOGIC; 
  signal REG_1_7_D1 : STD_LOGIC; 
  signal REG_1_7_D2 : STD_LOGIC; 
  signal EXP42_EXP : STD_LOGIC; 
  signal REG_1_7_D2_PT_0 : STD_LOGIC; 
  signal REG_1_7_D2_PT_1 : STD_LOGIC; 
  signal REG_1_7_D2_PT_2 : STD_LOGIC; 
  signal REG_1_8_Q : STD_LOGIC; 
  signal REG_1_8 : STD_LOGIC; 
  signal REG_1_8_D : STD_LOGIC; 
  signal REG_1_8_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_8_RSTF : STD_LOGIC; 
  signal REG_1_8_SETF : STD_LOGIC; 
  signal REG_1_8_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_8_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_8_CLKF : STD_LOGIC; 
  signal REG_1_8_D1 : STD_LOGIC; 
  signal REG_1_8_D2 : STD_LOGIC; 
  signal EXP47_EXP : STD_LOGIC; 
  signal REG_1_8_D2_PT_0 : STD_LOGIC; 
  signal REG_1_8_D2_PT_1 : STD_LOGIC; 
  signal REG_1_8_D2_PT_2 : STD_LOGIC; 
  signal REG_1_9_Q : STD_LOGIC; 
  signal REG_1_9_D : STD_LOGIC; 
  signal REG_1_9_tsimcreated_xor_Q : STD_LOGIC; 
  signal REG_1_9_RSTF : STD_LOGIC; 
  signal REG_1_9_SETF : STD_LOGIC; 
  signal REG_1_9_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal REG_1_9_tsimcreated_prld_Q : STD_LOGIC; 
  signal REG_1_9_CLKF : STD_LOGIC; 
  signal REG_1_9_D1 : STD_LOGIC; 
  signal REG_1_9_D2 : STD_LOGIC; 
  signal EXP44_EXP : STD_LOGIC; 
  signal REG_1_9_D2_PT_0 : STD_LOGIC; 
  signal REG_1_9_D2_PT_1 : STD_LOGIC; 
  signal REG_1_9_D2_PT_2 : STD_LOGIC; 
  signal DOUT_OBUFE_Q : STD_LOGIC; 
  signal DOUT_OBUFE_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal DOUT_OBUFE_BUFOE_OUT : STD_LOGIC; 
  signal DOUT_OBUFE_TRST : STD_LOGIC; 
  signal DOUT_OBUFE_D : STD_LOGIC; 
  signal DOUT_OBUFE_D1 : STD_LOGIC; 
  signal DOUT_OBUFE_D2 : STD_LOGIC; 
  signal DOUT_OBUFE_D2_PT_0 : STD_LOGIC; 
  signal DOUT_OBUFE_D2_PT_1 : STD_LOGIC; 
  signal DOUT_OBUFE_EXP_PT_0 : STD_LOGIC; 
  signal DOUT_OBUFE_EXP_PT_1 : STD_LOGIC; 
  signal state_0_Q : STD_LOGIC; 
  signal state_0_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal state_0_RSTF : STD_LOGIC; 
  signal state_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal state_0_D : STD_LOGIC; 
  signal state_0_CLKF : STD_LOGIC; 
  signal state_0_D1 : STD_LOGIC; 
  signal state_0_D2 : STD_LOGIC; 
  signal state_0_EXP_PT_0 : STD_LOGIC; 
  signal state_0_EXP_PT_1 : STD_LOGIC; 
  signal state_1_Q : STD_LOGIC; 
  signal state_1_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal state_1_RSTF : STD_LOGIC; 
  signal state_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal state_1_D : STD_LOGIC; 
  signal state_1_CLKF : STD_LOGIC; 
  signal state_1_D1 : STD_LOGIC; 
  signal state_1_D2 : STD_LOGIC; 
  signal state_1_EXP_PT_0 : STD_LOGIC; 
  signal state_1_EXP_PT_1 : STD_LOGIC; 
  signal CLK_SCALE_1_Q : STD_LOGIC; 
  signal CLK_SCALE_1_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal CLK_SCALE_1_D : STD_LOGIC; 
  signal CLK_SCALE_1_D1 : STD_LOGIC; 
  signal CLK_SCALE_1_D2 : STD_LOGIC; 
  signal CLK_SCALE_1_D2_PT_0 : STD_LOGIC; 
  signal CLK_SCALE_1_D2_PT_1 : STD_LOGIC; 
  signal CLK_SCALE_1_D2_PT_2 : STD_LOGIC; 
  signal CLK_SCALE_2_Q : STD_LOGIC; 
  signal CLK_SCALE_2_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal CLK_SCALE_2_D : STD_LOGIC; 
  signal CLK_SCALE_2_D1 : STD_LOGIC; 
  signal CLK_SCALE_2_D2 : STD_LOGIC; 
  signal CLK_SCALE_2_D2_PT_0 : STD_LOGIC; 
  signal CLK_SCALE_2_D2_PT_1 : STD_LOGIC; 
  signal CLK_SCALE_2_D2_PT_2 : STD_LOGIC; 
  signal CLK_SCALE_2_EXP_PT_0 : STD_LOGIC; 
  signal CLK_SCALE_2_EXP_PT_1 : STD_LOGIC; 
  signal CLK_SCALE_3_Q : STD_LOGIC; 
  signal CLK_SCALE_3_D : STD_LOGIC; 
  signal CLK_SCALE_3_D1 : STD_LOGIC; 
  signal CLK_SCALE_3_D2 : STD_LOGIC; 
  signal CLK_SCALE_3_D2_PT_0 : STD_LOGIC; 
  signal CLK_SCALE_3_D2_PT_1 : STD_LOGIC; 
  signal CLK_SCALE_3_D2_PT_2 : STD_LOGIC; 
  signal CLK_SCALE_4_Q : STD_LOGIC; 
  signal CLK_SCALE_4_D : STD_LOGIC; 
  signal CLK_SCALE_4_D1 : STD_LOGIC; 
  signal CLK_SCALE_4_D2 : STD_LOGIC; 
  signal CLK_SCALE_4_D2_PT_0 : STD_LOGIC; 
  signal CLK_SCALE_4_D2_PT_1 : STD_LOGIC; 
  signal CLK_SCALE_4_D2_PT_2 : STD_LOGIC; 
  signal CLK_SCALE_5_Q : STD_LOGIC; 
  signal CLK_SCALE_5_D : STD_LOGIC; 
  signal CLK_SCALE_5_D1 : STD_LOGIC; 
  signal CLK_SCALE_5_D2 : STD_LOGIC; 
  signal CLK_SCALE_5_D2_PT_0 : STD_LOGIC; 
  signal CLK_SCALE_5_D2_PT_1 : STD_LOGIC; 
  signal CLK_SCALE_5_D2_PT_2 : STD_LOGIC; 
  signal tempID_0_Q : STD_LOGIC; 
  signal tempID_0_D : STD_LOGIC; 
  signal tempID_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal tempID_0_CLKF : STD_LOGIC; 
  signal tempID_0_D1 : STD_LOGIC; 
  signal tempID_0_D2 : STD_LOGIC; 
  signal tempID_0_D2_PT_0 : STD_LOGIC; 
  signal tempID_0_D2_PT_1 : STD_LOGIC; 
  signal tempID_0_D2_PT_2 : STD_LOGIC; 
  signal tempID_0_D2_PT_3 : STD_LOGIC; 
  signal BUF_IS_EMPTY_OBUF_Q_0 : STD_LOGIC; 
  signal BUF_IS_EMPTY_OBUF_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal BUF_IS_EMPTY_OBUF_D : STD_LOGIC; 
  signal BUF_IS_EMPTY_OBUF_D1 : STD_LOGIC; 
  signal BUF_IS_EMPTY_OBUF_D2 : STD_LOGIC; 
  signal BUF_IS_EMPTY_OBUF_EXP_PT_0 : STD_LOGIC; 
  signal BUF_IS_EMPTY_OBUF_EXP_PT_1 : STD_LOGIC; 
  signal BUF_IS_EMPTY_OBUF_EXP_PT_2 : STD_LOGIC; 
  signal BUF_IS_EMPTY_OBUF_EXP_PT_3 : STD_LOGIC; 
  signal SHIFT_EN_Q : STD_LOGIC; 
  signal SHIFT_EN_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal SHIFT_EN_RSTF : STD_LOGIC; 
  signal SHIFT_EN_SETF : STD_LOGIC; 
  signal SHIFT_EN_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal SHIFT_EN_tsimcreated_prld_Q : STD_LOGIC; 
  signal SHIFT_EN_D : STD_LOGIC; 
  signal SHIFT_EN_CLKF : STD_LOGIC; 
  signal SHIFT_EN_D1 : STD_LOGIC; 
  signal SHIFT_EN_D2 : STD_LOGIC; 
  signal SHIFT_EN_SHIFT_EN_RSTF_INT_UIM : STD_LOGIC; 
  signal SHIFT_EN_EXP_PT_0 : STD_LOGIC; 
  signal SHIFT_EN_EXP_PT_1 : STD_LOGIC; 
  signal next_state_0_Q : STD_LOGIC; 
  signal next_state_0_RSTF : STD_LOGIC; 
  signal next_state_0_SETF : STD_LOGIC; 
  signal next_state_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal next_state_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal next_state_0_D : STD_LOGIC; 
  signal next_state_0_CLKF : STD_LOGIC; 
  signal next_state_0_D1 : STD_LOGIC; 
  signal next_state_0_D2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_19_UIM : STD_LOGIC; 
  signal next_state_0_next_state_0_RSTF_UIM : STD_LOGIC; 
  signal next_state_1_Q : STD_LOGIC; 
  signal next_state_1_RSTF : STD_LOGIC; 
  signal next_state_1_SETF : STD_LOGIC; 
  signal next_state_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal next_state_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal next_state_1_D : STD_LOGIC; 
  signal next_state_1_CLKF : STD_LOGIC; 
  signal next_state_1_D1 : STD_LOGIC; 
  signal next_state_1_D2 : STD_LOGIC; 
  signal next_state_1_next_state_1_RSTF_UIM : STD_LOGIC; 
  signal CCLK_OBUF_Q : STD_LOGIC; 
  signal CCLK_OBUF_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal CCLK_OBUF_D : STD_LOGIC; 
  signal CCLK_OBUF_D1 : STD_LOGIC; 
  signal CCLK_OBUF_D2 : STD_LOGIC; 
  signal EXP64_EXP : STD_LOGIC; 
  signal CCLK_OBUF_D2_PT_0 : STD_LOGIC; 
  signal CCLK_OBUF_D2_PT_1 : STD_LOGIC; 
  signal CCLK_OBUF_EXP_PT_0 : STD_LOGIC; 
  signal CCLK_OBUF_EXP_PT_1 : STD_LOGIC; 
  signal CCLK_OBUF_EXP_PT_2 : STD_LOGIC; 
  signal CCLK_OBUF_EXP_PT_3 : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_Q : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_D : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_D1 : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_D2 : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_D2_PT_0 : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_D2_PT_1 : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_EXP_PT_0 : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_EXP_PT_1 : STD_LOGIC; 
  signal buf_depth_0_buf_depth_0_RSTF_EXP_PT_2 : STD_LOGIC; 
  signal buf_depth_1_buf_depth_1_RSTF_Q : STD_LOGIC; 
  signal buf_depth_1_buf_depth_1_RSTF_D : STD_LOGIC; 
  signal buf_depth_1_buf_depth_1_RSTF_D1 : STD_LOGIC; 
  signal buf_depth_1_buf_depth_1_RSTF_D2 : STD_LOGIC; 
  signal buf_depth_1_buf_depth_1_RSTF_D2_PT_0 : STD_LOGIC; 
  signal buf_depth_1_buf_depth_1_RSTF_D2_PT_1 : STD_LOGIC; 
  signal buf_depth_1_buf_depth_1_RSTF_D2_PT_2 : STD_LOGIC; 
  signal SHIFT_EN_SHIFT_EN_RSTF_INT_Q : STD_LOGIC; 
  signal SHIFT_EN_SHIFT_EN_RSTF_INT_D : STD_LOGIC; 
  signal SHIFT_EN_SHIFT_EN_RSTF_INT_D1 : STD_LOGIC; 
  signal SHIFT_EN_SHIFT_EN_RSTF_INT_D2 : STD_LOGIC; 
  signal SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0 : STD_LOGIC; 
  signal SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_19_Q : STD_LOGIC; 
  signal Q_OpTx_FX_DC_19_D : STD_LOGIC; 
  signal Q_OpTx_FX_DC_19_D1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_19_D2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_19_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_19_D2_PT_1 : STD_LOGIC; 
  signal next_state_0_next_state_0_RSTF_Q : STD_LOGIC; 
  signal next_state_0_next_state_0_RSTF_D : STD_LOGIC; 
  signal next_state_0_next_state_0_RSTF_D1 : STD_LOGIC; 
  signal next_state_0_next_state_0_RSTF_D2 : STD_LOGIC; 
  signal next_state_0_next_state_0_RSTF_D2_PT_0 : STD_LOGIC; 
  signal next_state_0_next_state_0_RSTF_D2_PT_1 : STD_LOGIC; 
  signal next_state_0_next_state_0_RSTF_D2_PT_2 : STD_LOGIC; 
  signal next_state_0_next_state_0_RSTF_D2_PT_3 : STD_LOGIC; 
  signal next_state_1_next_state_1_RSTF_Q : STD_LOGIC; 
  signal next_state_1_next_state_1_RSTF_D : STD_LOGIC; 
  signal next_state_1_next_state_1_RSTF_D1 : STD_LOGIC; 
  signal next_state_1_next_state_1_RSTF_D2 : STD_LOGIC; 
  signal next_state_1_next_state_1_RSTF_D2_PT_0 : STD_LOGIC; 
  signal next_state_1_next_state_1_RSTF_D2_PT_1 : STD_LOGIC; 
  signal next_state_1_next_state_1_RSTF_D2_PT_2 : STD_LOGIC; 
  signal next_state_1_next_state_1_RSTF_D2_PT_3 : STD_LOGIC; 
  signal next_state_1_next_state_1_RSTF_D2_PT_4 : STD_LOGIC; 
  signal EXP18_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP18_EXP_PT_0 : STD_LOGIC; 
  signal EXP18_EXP_PT_1 : STD_LOGIC; 
  signal EXP19_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP19_EXP_PT_0 : STD_LOGIC; 
  signal EXP19_EXP_PT_1 : STD_LOGIC; 
  signal EXP20_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP21_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP22_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP22_EXP_PT_0 : STD_LOGIC; 
  signal EXP22_EXP_PT_1 : STD_LOGIC; 
  signal EXP22_EXP_PT_2 : STD_LOGIC; 
  signal EXP23_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP23_EXP_PT_0 : STD_LOGIC; 
  signal EXP23_EXP_PT_1 : STD_LOGIC; 
  signal EXP23_EXP_PT_2 : STD_LOGIC; 
  signal EXP23_EXP_PT_3 : STD_LOGIC; 
  signal EXP24_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP24_EXP_PT_0 : STD_LOGIC; 
  signal EXP24_EXP_PT_1 : STD_LOGIC; 
  signal EXP25_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP25_EXP_PT_0 : STD_LOGIC; 
  signal EXP25_EXP_PT_1 : STD_LOGIC; 
  signal EXP25_EXP_PT_2 : STD_LOGIC; 
  signal EXP25_EXP_PT_3 : STD_LOGIC; 
  signal EXP26_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP26_EXP_PT_0 : STD_LOGIC; 
  signal EXP26_EXP_PT_1 : STD_LOGIC; 
  signal EXP27_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP27_EXP_PT_0 : STD_LOGIC; 
  signal EXP27_EXP_PT_1 : STD_LOGIC; 
  signal EXP28_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP28_EXP_PT_0 : STD_LOGIC; 
  signal EXP28_EXP_PT_1 : STD_LOGIC; 
  signal EXP29_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP29_EXP_PT_0 : STD_LOGIC; 
  signal EXP29_EXP_PT_1 : STD_LOGIC; 
  signal EXP29_EXP_PT_2 : STD_LOGIC; 
  signal EXP30_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP30_EXP_PT_0 : STD_LOGIC; 
  signal EXP30_EXP_PT_1 : STD_LOGIC; 
  signal EXP30_EXP_PT_2 : STD_LOGIC; 
  signal EXP31_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP31_EXP_PT_0 : STD_LOGIC; 
  signal EXP31_EXP_PT_1 : STD_LOGIC; 
  signal EXP32_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP32_EXP_PT_0 : STD_LOGIC; 
  signal EXP32_EXP_PT_1 : STD_LOGIC; 
  signal EXP33_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP33_EXP_PT_0 : STD_LOGIC; 
  signal EXP33_EXP_PT_1 : STD_LOGIC; 
  signal EXP33_EXP_PT_2 : STD_LOGIC; 
  signal EXP34_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP34_EXP_PT_0 : STD_LOGIC; 
  signal EXP34_EXP_PT_1 : STD_LOGIC; 
  signal EXP34_EXP_PT_2 : STD_LOGIC; 
  signal EXP35_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP35_EXP_PT_0 : STD_LOGIC; 
  signal EXP35_EXP_PT_1 : STD_LOGIC; 
  signal EXP36_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP36_EXP_PT_0 : STD_LOGIC; 
  signal EXP36_EXP_PT_1 : STD_LOGIC; 
  signal EXP37_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP37_EXP_PT_0 : STD_LOGIC; 
  signal EXP37_EXP_PT_1 : STD_LOGIC; 
  signal EXP38_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP38_EXP_PT_0 : STD_LOGIC; 
  signal EXP38_EXP_PT_1 : STD_LOGIC; 
  signal EXP38_EXP_PT_2 : STD_LOGIC; 
  signal EXP39_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP39_EXP_PT_0 : STD_LOGIC; 
  signal EXP39_EXP_PT_1 : STD_LOGIC; 
  signal EXP39_EXP_PT_2 : STD_LOGIC; 
  signal EXP40_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP40_EXP_PT_0 : STD_LOGIC; 
  signal EXP40_EXP_PT_1 : STD_LOGIC; 
  signal EXP41_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP41_EXP_PT_0 : STD_LOGIC; 
  signal EXP41_EXP_PT_1 : STD_LOGIC; 
  signal EXP42_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP42_EXP_PT_0 : STD_LOGIC; 
  signal EXP42_EXP_PT_1 : STD_LOGIC; 
  signal EXP43_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP43_EXP_PT_0 : STD_LOGIC; 
  signal EXP43_EXP_PT_1 : STD_LOGIC; 
  signal EXP44_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP44_EXP_PT_0 : STD_LOGIC; 
  signal EXP44_EXP_PT_1 : STD_LOGIC; 
  signal EXP45_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP45_EXP_PT_0 : STD_LOGIC; 
  signal EXP45_EXP_PT_1 : STD_LOGIC; 
  signal EXP45_EXP_PT_2 : STD_LOGIC; 
  signal EXP46_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP46_EXP_PT_0 : STD_LOGIC; 
  signal EXP46_EXP_PT_1 : STD_LOGIC; 
  signal EXP46_EXP_PT_2 : STD_LOGIC; 
  signal EXP47_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP47_EXP_PT_0 : STD_LOGIC; 
  signal EXP47_EXP_PT_1 : STD_LOGIC; 
  signal EXP48_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP48_EXP_PT_0 : STD_LOGIC; 
  signal EXP48_EXP_PT_1 : STD_LOGIC; 
  signal EXP49_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP49_EXP_PT_0 : STD_LOGIC; 
  signal EXP49_EXP_PT_1 : STD_LOGIC; 
  signal EXP50_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP51_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP52_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP52_EXP_PT_0 : STD_LOGIC; 
  signal EXP52_EXP_PT_1 : STD_LOGIC; 
  signal EXP52_EXP_PT_2 : STD_LOGIC; 
  signal EXP53_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP53_EXP_PT_0 : STD_LOGIC; 
  signal EXP53_EXP_PT_1 : STD_LOGIC; 
  signal EXP53_EXP_PT_2 : STD_LOGIC; 
  signal EXP53_EXP_PT_3 : STD_LOGIC; 
  signal EXP54_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP54_EXP_PT_0 : STD_LOGIC; 
  signal EXP54_EXP_PT_1 : STD_LOGIC; 
  signal EXP55_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP55_EXP_PT_0 : STD_LOGIC; 
  signal EXP55_EXP_PT_1 : STD_LOGIC; 
  signal EXP55_EXP_PT_2 : STD_LOGIC; 
  signal EXP56_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP56_EXP_PT_0 : STD_LOGIC; 
  signal EXP56_EXP_PT_1 : STD_LOGIC; 
  signal EXP56_EXP_PT_2 : STD_LOGIC; 
  signal EXP57_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP57_EXP_PT_0 : STD_LOGIC; 
  signal EXP57_EXP_PT_1 : STD_LOGIC; 
  signal EXP58_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP58_EXP_PT_0 : STD_LOGIC; 
  signal EXP58_EXP_PT_1 : STD_LOGIC; 
  signal EXP59_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP59_EXP_PT_0 : STD_LOGIC; 
  signal EXP59_EXP_PT_1 : STD_LOGIC; 
  signal EXP60_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP60_EXP_PT_0 : STD_LOGIC; 
  signal EXP60_EXP_PT_1 : STD_LOGIC; 
  signal EXP60_EXP_PT_2 : STD_LOGIC; 
  signal EXP61_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP61_EXP_PT_0 : STD_LOGIC; 
  signal EXP61_EXP_PT_1 : STD_LOGIC; 
  signal EXP61_EXP_PT_2 : STD_LOGIC; 
  signal EXP62_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP62_EXP_PT_0 : STD_LOGIC; 
  signal EXP62_EXP_PT_1 : STD_LOGIC; 
  signal EXP63_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP63_EXP_PT_0 : STD_LOGIC; 
  signal EXP63_EXP_PT_1 : STD_LOGIC; 
  signal EXP64_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP64_EXP_PT_0 : STD_LOGIC; 
  signal EXP64_EXP_PT_1 : STD_LOGIC; 
  signal EXP65_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP65_EXP_PT_0 : STD_LOGIC; 
  signal EXP65_EXP_PT_1 : STD_LOGIC; 
  signal EXP66_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP66_EXP_PT_0 : STD_LOGIC; 
  signal EXP66_EXP_PT_1 : STD_LOGIC; 
  signal EXP67_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP67_EXP_PT_0 : STD_LOGIC; 
  signal EXP67_EXP_PT_1 : STD_LOGIC; 
  signal EXP68_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP68_EXP_PT_0 : STD_LOGIC; 
  signal EXP68_EXP_PT_1 : STD_LOGIC; 
  signal EXP69_EXP_tsimrenamed_net_Q : STD_LOGIC; 
  signal EXP69_EXP_PT_0 : STD_LOGIC; 
  signal EXP69_EXP_PT_1 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK_CE_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK_CE_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK_CE_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK_CE_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK_CE_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SCLK_CE_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_readBufId_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_readBufId_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_readBufId_0_CE_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_readBufId_0_CE_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_readBufId_0_CE_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_readBufId_0_CE_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_readBufId_0_CE_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_readBufId_0_CE_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_SETF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_SETF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_1_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_3_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_count_1_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_count_2_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_count_3_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_CNT_4_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_writeBufId_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_writeBufId_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_writeBufId_0_CE_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_writeBufId_0_CE_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_writeBufId_0_CE_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_writeBufId_0_CE_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_writeBufId_0_CE_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_writeBufId_0_CE_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_0_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_1_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_10_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_11_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_12_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_13_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_14_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_16_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_18_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_19_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_2_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_20_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_22_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_24_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_25_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_26_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_28_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_29_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_3_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_30_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_31_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_4_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_5_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_6_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_8_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_0_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_0_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_0_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_0_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_0_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_1_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_1_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_1_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_1_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_1_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_1_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_1_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_10_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_10_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_10_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_10_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_10_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_10_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_10_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_10_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_10_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_10_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_11_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_11_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_11_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_11_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_11_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_11_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_11_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_12_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_12_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_12_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_12_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_12_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_12_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_12_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_12_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_12_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_12_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_13_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_13_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_13_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_13_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_13_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_13_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_13_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_14_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_14_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_14_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_14_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_14_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_14_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_14_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_14_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_14_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_14_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_15_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_15_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_15_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_15_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_15_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_15_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_15_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_15_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_15_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_15_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_16_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_16_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_16_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_16_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_16_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_16_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_16_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_16_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_16_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_16_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_17_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_17_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_17_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_17_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_17_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_17_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_17_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_18_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_18_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_18_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_18_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_18_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_18_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_18_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_18_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_18_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_18_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_19_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_19_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_19_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_19_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_19_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_19_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_19_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_2_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_2_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_2_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_2_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_2_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_2_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_2_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_2_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_20_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_20_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_20_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_20_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_20_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_20_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_20_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_20_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_20_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_20_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_21_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_21_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_21_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_21_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_21_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_21_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_21_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_21_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_21_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_21_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_22_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_22_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_22_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_22_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_22_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_22_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_22_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_22_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_22_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_22_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_23_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_23_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_23_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_23_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_23_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_23_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_23_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_23_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_23_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_23_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_24_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_24_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_24_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_24_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_24_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_24_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_24_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_25_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_25_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_25_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_25_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_25_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_25_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_25_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_25_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_25_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_25_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_26_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_26_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_26_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_26_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_26_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_26_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_26_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_26_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_26_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_26_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_27_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_27_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_27_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_27_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_27_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_27_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_27_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_27_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_27_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_27_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_28_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_28_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_28_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_28_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_28_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_28_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_28_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_28_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_28_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_28_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_29_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_29_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_29_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_29_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_29_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_29_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_29_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_29_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_29_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_29_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_3_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_3_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_3_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_3_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_3_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_3_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_3_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_30_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_30_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_30_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_30_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_30_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_30_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_30_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_30_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_30_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_30_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_31_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_31_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_31_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_31_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_31_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_31_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_31_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_31_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_31_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_31_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_4_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_4_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_4_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_4_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_4_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_4_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_4_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_4_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_5_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_5_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_5_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_5_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_5_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_5_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_5_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_5_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_5_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_6_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_6_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_6_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_6_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_6_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_6_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_6_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_6_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_6_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_6_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_7_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_7_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_7_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_7_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_7_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_7_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_7_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_7_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_7_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_7_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_8_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_8_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_8_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_8_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_8_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_8_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_8_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_8_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_8_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_8_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_9_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_9_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_9_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_9_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_9_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_9_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_9_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_9_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_9_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_REG_1_9_RSTF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DOUT_OBUFE_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DOUT_OBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_state_0_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_state_0_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_state_0_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_state_0_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_state_0_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_state_0_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_state_0_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_state_0_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_state_1_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_state_1_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_state_1_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_state_1_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_state_1_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_state_1_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_state_1_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_state_1_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_1_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_1_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_3_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_3_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_4_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_4_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_5_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CLK_SCALE_5_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_2_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_D2_PT_3_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tempID_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_SETF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_SETF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_SETF_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_SETF_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP18_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP19_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP22_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP23_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP24_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP25_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP26_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP27_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP27_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP27_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP27_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP28_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP28_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP28_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP28_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP29_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP30_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP31_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP32_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP33_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP34_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP35_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP36_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP36_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP36_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP36_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP36_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP36_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP36_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP36_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP37_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP37_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP37_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP37_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP38_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP38_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP38_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP38_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP38_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP38_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP38_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP39_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP40_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP40_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP40_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP40_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP41_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP41_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP41_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP41_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP42_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP42_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP42_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP42_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP43_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP43_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP43_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP43_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP44_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP44_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP44_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP44_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP45_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP46_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP47_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP47_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP47_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP47_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP48_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP48_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP48_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP48_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP49_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP49_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP49_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP49_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP52_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP52_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP52_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP52_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP52_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP52_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP53_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP53_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP53_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP53_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP53_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP53_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP53_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP53_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP53_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP53_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP54_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP54_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP54_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP54_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP55_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP55_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP55_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP55_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP55_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP55_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP55_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP56_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP56_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP56_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP56_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP56_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP56_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP56_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP57_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP57_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP57_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP57_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP58_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP58_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP58_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP58_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP59_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP59_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP59_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP59_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP60_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP60_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP60_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP60_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP60_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP60_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP60_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP61_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP61_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP61_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP61_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP61_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP61_EXP_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP61_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP62_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP62_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP62_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP62_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP63_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP63_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP63_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP63_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP64_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP64_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP64_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP65_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP65_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP65_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP65_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP65_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP65_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP65_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP65_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP66_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP66_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP66_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP66_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP66_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP66_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP66_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP66_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP67_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP67_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP67_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP68_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP68_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP68_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP68_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP69_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP69_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP69_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP69_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP69_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP69_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP69_EXP_PT_1_IN6 : STD_LOGIC; 
  signal count : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal readBufId : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal buf_depth : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal writeBufId : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal SHIFT_CNT : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal CLK_SCALE : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal tempID : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 ); 
begin
  FCLKIO_0_1 : X_BUF
    port map (
      I => CLK,
      O => FCLKIO_0
    );
  RES_IBUF_2 : X_BUF
    port map (
      I => RES,
      O => RES_IBUF
    );
  LOAD_PRESCALER_IBUF_3 : X_BUF
    port map (
      I => LOAD_PRESCALER,
      O => LOAD_PRESCALER_IBUF
    );
  LOAD_SREG_IBUF_4 : X_BUF
    port map (
      I => LOAD_SREG,
      O => LOAD_SREG_IBUF
    );
  CCLK_PRESCALER_0_IBUF_5 : X_BUF
    port map (
      I => CCLK_PRESCALER(0),
      O => CCLK_PRESCALER_0_IBUF
    );
  DIN_0_IBUF_6 : X_BUF
    port map (
      I => DIN(0),
      O => DIN_0_IBUF
    );
  DIN_1_IBUF_7 : X_BUF
    port map (
      I => DIN(1),
      O => DIN_1_IBUF
    );
  DIN_10_IBUF_8 : X_BUF
    port map (
      I => DIN(10),
      O => DIN_10_IBUF
    );
  DIN_11_IBUF_9 : X_BUF
    port map (
      I => DIN(11),
      O => DIN_11_IBUF
    );
  DIN_12_IBUF_10 : X_BUF
    port map (
      I => DIN(12),
      O => DIN_12_IBUF
    );
  DIN_13_IBUF_11 : X_BUF
    port map (
      I => DIN(13),
      O => DIN_13_IBUF
    );
  DIN_14_IBUF_12 : X_BUF
    port map (
      I => DIN(14),
      O => DIN_14_IBUF
    );
  DIN_15_IBUF_13 : X_BUF
    port map (
      I => DIN(15),
      O => DIN_15_IBUF
    );
  DIN_16_IBUF_14 : X_BUF
    port map (
      I => DIN(16),
      O => DIN_16_IBUF
    );
  DIN_17_IBUF_15 : X_BUF
    port map (
      I => DIN(17),
      O => DIN_17_IBUF
    );
  DIN_18_IBUF_16 : X_BUF
    port map (
      I => DIN(18),
      O => DIN_18_IBUF
    );
  DIN_19_IBUF_17 : X_BUF
    port map (
      I => DIN(19),
      O => DIN_19_IBUF
    );
  DIN_2_IBUF_18 : X_BUF
    port map (
      I => DIN(2),
      O => DIN_2_IBUF
    );
  DIN_20_IBUF_19 : X_BUF
    port map (
      I => DIN(20),
      O => DIN_20_IBUF
    );
  DIN_21_IBUF_20 : X_BUF
    port map (
      I => DIN(21),
      O => DIN_21_IBUF
    );
  DIN_22_IBUF_21 : X_BUF
    port map (
      I => DIN(22),
      O => DIN_22_IBUF
    );
  DIN_23_IBUF_22 : X_BUF
    port map (
      I => DIN(23),
      O => DIN_23_IBUF
    );
  DIN_24_IBUF_23 : X_BUF
    port map (
      I => DIN(24),
      O => DIN_24_IBUF
    );
  DIN_25_IBUF_24 : X_BUF
    port map (
      I => DIN(25),
      O => DIN_25_IBUF
    );
  DIN_26_IBUF_25 : X_BUF
    port map (
      I => DIN(26),
      O => DIN_26_IBUF
    );
  DIN_27_IBUF_26 : X_BUF
    port map (
      I => DIN(27),
      O => DIN_27_IBUF
    );
  DIN_28_IBUF_27 : X_BUF
    port map (
      I => DIN(28),
      O => DIN_28_IBUF
    );
  DIN_29_IBUF_28 : X_BUF
    port map (
      I => DIN(29),
      O => DIN_29_IBUF
    );
  DIN_3_IBUF_29 : X_BUF
    port map (
      I => DIN(3),
      O => DIN_3_IBUF
    );
  DIN_30_IBUF_30 : X_BUF
    port map (
      I => DIN(30),
      O => DIN_30_IBUF
    );
  DIN_31_IBUF_31 : X_BUF
    port map (
      I => DIN(31),
      O => DIN_31_IBUF
    );
  DIN_4_IBUF_32 : X_BUF
    port map (
      I => DIN(4),
      O => DIN_4_IBUF
    );
  DIN_5_IBUF_33 : X_BUF
    port map (
      I => DIN(5),
      O => DIN_5_IBUF
    );
  DIN_6_IBUF_34 : X_BUF
    port map (
      I => DIN(6),
      O => DIN_6_IBUF
    );
  DIN_7_IBUF_35 : X_BUF
    port map (
      I => DIN(7),
      O => DIN_7_IBUF
    );
  DIN_8_IBUF_36 : X_BUF
    port map (
      I => DIN(8),
      O => DIN_8_IBUF
    );
  DIN_9_IBUF_37 : X_BUF
    port map (
      I => DIN(9),
      O => DIN_9_IBUF
    );
  DONE_IBUF_38 : X_BUF
    port map (
      I => DONE,
      O => DONE_IBUF
    );
  nINIT_B_IBUF_39 : X_BUF
    port map (
      I => nINIT_B,
      O => nINIT_B_IBUF
    );
  CCLK_PRESCALER_1_IBUF_40 : X_BUF
    port map (
      I => CCLK_PRESCALER(1),
      O => CCLK_PRESCALER_1_IBUF
    );
  CCLK_PRESCALER_2_IBUF_41 : X_BUF
    port map (
      I => CCLK_PRESCALER(2),
      O => CCLK_PRESCALER_2_IBUF
    );
  CCLK_PRESCALER_3_IBUF_42 : X_BUF
    port map (
      I => CCLK_PRESCALER(3),
      O => CCLK_PRESCALER_3_IBUF
    );
  CCLK_PRESCALER_4_IBUF_43 : X_BUF
    port map (
      I => CCLK_PRESCALER(4),
      O => CCLK_PRESCALER_4_IBUF
    );
  CCLK_PRESCALER_5_IBUF_44 : X_BUF
    port map (
      I => CCLK_PRESCALER(5),
      O => CCLK_PRESCALER_5_IBUF
    );
  DOUT_45 : X_TRI
    port map (
      I => DOUT_OBUFE,
      CTL => DOUT_OBUFE_OE,
      O => DOUT
    );
  BUF_IS_EMPTY_46 : X_BUF
    port map (
      I => BUF_IS_EMPTY_OBUF_Q,
      O => BUF_IS_EMPTY
    );
  CCLK_47 : X_BUF
    port map (
      I => CCLK_OBUF,
      O => CCLK
    );
  SCLK_48 : X_BUF
    port map (
      I => SCLK_Q,
      O => SCLK
    );
  SCLK_tsimcreated_xor_Q_49 : X_XOR2
    port map (
      I0 => SCLK_D,
      I1 => SCLK_Q,
      O => SCLK_tsimcreated_xor_Q
    );
  SCLK_REG : X_FF
    port map (
      I => SCLK_tsimcreated_xor_Q,
      CE => SCLK_CE,
      CLK => FCLKIO_0,
      SET => SCLK_SETF,
      RST => PRLD,
      O => SCLK_Q
    );
  SCLK_D_50 : X_XOR2
    port map (
      I0 => SCLK_D1,
      I1 => SCLK_D2,
      O => SCLK_D
    );
  SCLK_D1_51 : X_ZERO
    port map (
      O => SCLK_D1
    );
  SCLK_D2_52 : X_ONE
    port map (
      O => SCLK_D2
    );
  SCLK_SETF_53 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => SCLK_SETF
    );
  SCLK_CE_54 : X_AND7
    port map (
      I0 => NlwInverterSignal_SCLK_CE_IN0,
      I1 => count(0),
      I2 => NlwInverterSignal_SCLK_CE_IN2,
      I3 => NlwInverterSignal_SCLK_CE_IN3,
      I4 => NlwInverterSignal_SCLK_CE_IN4,
      I5 => NlwInverterSignal_SCLK_CE_IN5,
      I6 => NlwInverterSignal_SCLK_CE_IN6,
      O => SCLK_CE
    );
  readBufId_0_Q_55 : X_BUF
    port map (
      I => readBufId_0_Q,
      O => readBufId(0)
    );
  readBufId_0_tsimcreated_prld_Q_56 : X_OR2
    port map (
      I0 => readBufId_0_RSTF,
      I1 => PRLD,
      O => readBufId_0_tsimcreated_prld_Q
    );
  readBufId_0_REG : X_FF
    port map (
      I => readBufId_0_D,
      CE => readBufId_0_CE,
      CLK => readBufId_0_CLKF,
      SET => Gnd,
      RST => readBufId_0_tsimcreated_prld_Q,
      O => readBufId_0_Q
    );
  Gnd_57 : X_ZERO
    port map (
      O => Gnd
    );
  readBufId_0_D_58 : X_XOR2
    port map (
      I0 => readBufId_0_D1,
      I1 => readBufId_0_D2,
      O => readBufId_0_D
    );
  readBufId_0_D1_59 : X_ZERO
    port map (
      O => readBufId_0_D1
    );
  readBufId_0_D2_PT_0_60 : X_AND2
    port map (
      I0 => buf_depth(0),
      I1 => writeBufId(0),
      O => readBufId_0_D2_PT_0
    );
  readBufId_0_D2_PT_1_61 : X_AND2
    port map (
      I0 => writeBufId(0),
      I1 => buf_depth(1),
      O => readBufId_0_D2_PT_1
    );
  readBufId_0_D2_62 : X_OR2
    port map (
      I0 => readBufId_0_D2_PT_0,
      I1 => readBufId_0_D2_PT_1,
      O => readBufId_0_D2
    );
  readBufId_0_CLKF_63 : X_AND2
    port map (
      I0 => NlwInverterSignal_readBufId_0_CLKF_IN0,
      I1 => NlwInverterSignal_readBufId_0_CLKF_IN1,
      O => readBufId_0_CLKF
    );
  readBufId_0_RSTF_64 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => readBufId_0_RSTF
    );
  readBufId_0_CE_65 : X_AND7
    port map (
      I0 => NlwInverterSignal_readBufId_0_CE_IN0,
      I1 => NlwInverterSignal_readBufId_0_CE_IN1,
      I2 => NlwInverterSignal_readBufId_0_CE_IN2,
      I3 => NlwInverterSignal_readBufId_0_CE_IN3,
      I4 => NlwInverterSignal_readBufId_0_CE_IN4,
      I5 => NlwInverterSignal_readBufId_0_CE_IN5,
      I6 => SHIFT_EN,
      O => readBufId_0_CE
    );
  buf_depth_0_Q_66 : X_BUF
    port map (
      I => buf_depth_0_Q,
      O => buf_depth(0)
    );
  buf_depth_0_tsimcreated_xor_Q_67 : X_XOR2
    port map (
      I0 => buf_depth_0_D,
      I1 => buf_depth_0_Q,
      O => buf_depth_0_tsimcreated_xor_Q
    );
  buf_depth_0_tsimcreated_set_and_noreset_Q_68 : X_AND2
    port map (
      I0 => NlwInverterSignal_buf_depth_0_tsimcreated_set_and_noreset_IN0,
      I1 => buf_depth_0_SETF,
      O => buf_depth_0_tsimcreated_set_and_noreset_Q
    );
  buf_depth_0_tsimcreated_prld_Q_69 : X_OR2
    port map (
      I0 => buf_depth_0_RSTF,
      I1 => PRLD,
      O => buf_depth_0_tsimcreated_prld_Q
    );
  buf_depth_0_REG : X_FF
    port map (
      I => buf_depth_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => buf_depth_0_CLKF,
      SET => buf_depth_0_tsimcreated_set_and_noreset_Q,
      RST => buf_depth_0_tsimcreated_prld_Q,
      O => buf_depth_0_Q
    );
  Vcc_70 : X_ONE
    port map (
      O => Vcc
    );
  buf_depth_0_D_71 : X_XOR2
    port map (
      I0 => buf_depth_0_D1,
      I1 => buf_depth_0_D2,
      O => buf_depth_0_D
    );
  buf_depth_0_D1_72 : X_ZERO
    port map (
      O => buf_depth_0_D1
    );
  buf_depth_0_D2_PT_0_73 : X_AND7
    port map (
      I0 => buf_depth(0),
      I1 => NlwInverterSignal_buf_depth_0_D2_PT_0_IN1,
      I2 => NlwInverterSignal_buf_depth_0_D2_PT_0_IN2,
      I3 => NlwInverterSignal_buf_depth_0_D2_PT_0_IN3,
      I4 => NlwInverterSignal_buf_depth_0_D2_PT_0_IN4,
      I5 => NlwInverterSignal_buf_depth_0_D2_PT_0_IN5,
      I6 => SHIFT_EN,
      O => buf_depth_0_D2_PT_0
    );
  buf_depth_0_D2_PT_1_74 : X_AND8
    port map (
      I0 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN0,
      I1 => buf_depth(1),
      I2 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN2,
      I3 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN3,
      I4 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN4,
      I5 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN5,
      I6 => NlwInverterSignal_buf_depth_0_D2_PT_1_IN6,
      I7 => SHIFT_EN,
      O => buf_depth_0_D2_PT_1
    );
  buf_depth_0_D2_75 : X_OR2
    port map (
      I0 => buf_depth_0_D2_PT_0,
      I1 => buf_depth_0_D2_PT_1,
      O => buf_depth_0_D2
    );
  buf_depth_0_CLKF_76 : X_AND2
    port map (
      I0 => NlwInverterSignal_buf_depth_0_CLKF_IN0,
      I1 => NlwInverterSignal_buf_depth_0_CLKF_IN1,
      O => buf_depth_0_CLKF
    );
  buf_depth_0_SETF_77 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_buf_depth_0_SETF_IN1,
      I2 => NlwInverterSignal_buf_depth_0_SETF_IN2,
      O => buf_depth_0_SETF
    );
  buf_depth_0_RSTF_78 : X_AND2
    port map (
      I0 => buf_depth_0_buf_depth_0_RSTF_UIM,
      I1 => buf_depth_0_buf_depth_0_RSTF_UIM,
      O => buf_depth_0_RSTF
    );
  buf_depth_1_Q_79 : X_BUF
    port map (
      I => buf_depth_1_Q,
      O => buf_depth(1)
    );
  buf_depth_1_tsimcreated_xor_Q_80 : X_XOR2
    port map (
      I0 => buf_depth_1_D,
      I1 => buf_depth_1_Q,
      O => buf_depth_1_tsimcreated_xor_Q
    );
  buf_depth_1_tsimcreated_set_and_noreset_Q_81 : X_AND2
    port map (
      I0 => NlwInverterSignal_buf_depth_1_tsimcreated_set_and_noreset_IN0,
      I1 => buf_depth_1_SETF,
      O => buf_depth_1_tsimcreated_set_and_noreset_Q
    );
  buf_depth_1_tsimcreated_prld_Q_82 : X_OR2
    port map (
      I0 => buf_depth_1_RSTF,
      I1 => PRLD,
      O => buf_depth_1_tsimcreated_prld_Q
    );
  buf_depth_1_REG : X_FF
    port map (
      I => buf_depth_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => buf_depth_1_CLKF,
      SET => buf_depth_1_tsimcreated_set_and_noreset_Q,
      RST => buf_depth_1_tsimcreated_prld_Q,
      O => buf_depth_1_Q
    );
  buf_depth_1_D_83 : X_XOR2
    port map (
      I0 => buf_depth_1_D1,
      I1 => buf_depth_1_D2,
      O => buf_depth_1_D
    );
  buf_depth_1_D1_84 : X_ZERO
    port map (
      O => buf_depth_1_D1
    );
  buf_depth_1_D2_PT_0_85 : X_AND8
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => buf_depth(0),
      I2 => NlwInverterSignal_buf_depth_1_D2_PT_0_IN2,
      I3 => NlwInverterSignal_buf_depth_1_D2_PT_0_IN3,
      I4 => NlwInverterSignal_buf_depth_1_D2_PT_0_IN4,
      I5 => NlwInverterSignal_buf_depth_1_D2_PT_0_IN5,
      I6 => NlwInverterSignal_buf_depth_1_D2_PT_0_IN6,
      I7 => SHIFT_EN,
      O => buf_depth_1_D2_PT_0
    );
  buf_depth_1_D2_PT_1_86 : X_AND16
    port map (
      I0 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN0,
      I1 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN1,
      I2 => buf_depth(1),
      I3 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN3,
      I4 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN4,
      I5 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN5,
      I6 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN6,
      I7 => NlwInverterSignal_buf_depth_1_D2_PT_1_IN7,
      I8 => SHIFT_EN,
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => buf_depth_1_D2_PT_1
    );
  buf_depth_1_D2_87 : X_OR2
    port map (
      I0 => buf_depth_1_D2_PT_0,
      I1 => buf_depth_1_D2_PT_1,
      O => buf_depth_1_D2
    );
  buf_depth_1_CLKF_88 : X_AND2
    port map (
      I0 => NlwInverterSignal_buf_depth_1_CLKF_IN0,
      I1 => NlwInverterSignal_buf_depth_1_CLKF_IN1,
      O => buf_depth_1_CLKF
    );
  buf_depth_1_SETF_89 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => buf_depth(0),
      I2 => NlwInverterSignal_buf_depth_1_SETF_IN2,
      O => buf_depth_1_SETF
    );
  buf_depth_1_RSTF_90 : X_AND2
    port map (
      I0 => buf_depth_1_buf_depth_1_RSTF_UIM,
      I1 => buf_depth_1_buf_depth_1_RSTF_UIM,
      O => buf_depth_1_RSTF
    );
  SHIFT_CNT_0_Q_91 : X_BUF
    port map (
      I => SHIFT_CNT_0_Q,
      O => SHIFT_CNT(0)
    );
  SHIFT_CNT_0_EXP_92 : X_BUF
    port map (
      I => SHIFT_CNT_0_EXP_tsimrenamed_net_Q,
      O => SHIFT_CNT_0_EXP
    );
  SHIFT_CNT_0_tsimcreated_xor_Q_93 : X_XOR2
    port map (
      I0 => SHIFT_CNT_0_D,
      I1 => SHIFT_CNT_0_Q,
      O => SHIFT_CNT_0_tsimcreated_xor_Q
    );
  SHIFT_CNT_0_tsimcreated_set_and_noreset_Q_94 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0,
      I1 => SHIFT_CNT_0_SETF,
      O => SHIFT_CNT_0_tsimcreated_set_and_noreset_Q
    );
  SHIFT_CNT_0_tsimcreated_prld_Q_95 : X_OR2
    port map (
      I0 => SHIFT_CNT_0_RSTF,
      I1 => PRLD,
      O => SHIFT_CNT_0_tsimcreated_prld_Q
    );
  SHIFT_CNT_0_REG : X_FF
    port map (
      I => SHIFT_CNT_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => SHIFT_CNT_0_CLKF,
      SET => SHIFT_CNT_0_tsimcreated_set_and_noreset_Q,
      RST => SHIFT_CNT_0_tsimcreated_prld_Q,
      O => SHIFT_CNT_0_Q
    );
  SHIFT_CNT_0_D_96 : X_XOR2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_0_D_IN0,
      I1 => SHIFT_CNT_0_D2,
      O => SHIFT_CNT_0_D
    );
  SHIFT_CNT_0_D1_97 : X_ZERO
    port map (
      O => SHIFT_CNT_0_D1
    );
  SHIFT_CNT_0_D2_PT_0_98 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN1,
      O => SHIFT_CNT_0_D2_PT_0
    );
  SHIFT_CNT_0_D2_PT_1_99 : X_AND2
    port map (
      I0 => EXP69_EXP,
      I1 => EXP69_EXP,
      O => SHIFT_CNT_0_D2_PT_1
    );
  SHIFT_CNT_0_D2_100 : X_OR2
    port map (
      I0 => SHIFT_CNT_0_D2_PT_0,
      I1 => SHIFT_CNT_0_D2_PT_1,
      O => SHIFT_CNT_0_D2
    );
  SHIFT_CNT_0_CLKF_101 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_0_CLKF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_0_CLKF_IN1,
      O => SHIFT_CNT_0_CLKF
    );
  SHIFT_CNT_0_SETF_102 : X_AND2
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_SHIFT_CNT_0_SETF_IN1,
      O => SHIFT_CNT_0_SETF
    );
  SHIFT_CNT_0_RSTF_103 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => SHIFT_CNT_0_RSTF
    );
  SHIFT_CNT_0_EXP_tsimrenamed_net_Q_104 : X_AND7
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN2,
      I3 => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN3,
      I4 => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN4,
      I5 => SHIFT_CNT(4),
      I6 => SHIFT_EN,
      O => SHIFT_CNT_0_EXP_tsimrenamed_net_Q
    );
  count_0_Q_105 : X_BUF
    port map (
      I => count_0_Q,
      O => count(0)
    );
  count_0_EXP_106 : X_BUF
    port map (
      I => count_0_EXP_tsimrenamed_net_Q,
      O => count_0_EXP
    );
  count_0_tsimcreated_set_and_noreset_Q_107 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0,
      I1 => count_0_SETF,
      O => count_0_tsimcreated_set_and_noreset_Q
    );
  count_0_tsimcreated_prld_Q_108 : X_OR2
    port map (
      I0 => count_0_RSTF,
      I1 => PRLD,
      O => count_0_tsimcreated_prld_Q
    );
  count_0_REG : X_FF
    port map (
      I => count_0_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_0_tsimcreated_set_and_noreset_Q,
      RST => count_0_tsimcreated_prld_Q,
      O => count_0_Q
    );
  count_0_D_109 : X_XOR2
    port map (
      I0 => count_0_D1,
      I1 => count_0_D2,
      O => count_0_D
    );
  count_0_D1_110 : X_ZERO
    port map (
      O => count_0_D1
    );
  count_0_D2_PT_0_111 : X_AND2
    port map (
      I0 => EXP67_EXP,
      I1 => EXP67_EXP,
      O => count_0_D2_PT_0
    );
  count_0_D2_PT_1_112 : X_AND3
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_0_D2_PT_1_IN1,
      I2 => CLK_SCALE(0),
      O => count_0_D2_PT_1
    );
  count_0_D2_PT_2_113 : X_AND7
    port map (
      I0 => NlwInverterSignal_count_0_D2_PT_2_IN0,
      I1 => NlwInverterSignal_count_0_D2_PT_2_IN1,
      I2 => NlwInverterSignal_count_0_D2_PT_2_IN2,
      I3 => NlwInverterSignal_count_0_D2_PT_2_IN3,
      I4 => NlwInverterSignal_count_0_D2_PT_2_IN4,
      I5 => NlwInverterSignal_count_0_D2_PT_2_IN5,
      I6 => CLK_SCALE(0),
      O => count_0_D2_PT_2
    );
  count_0_D2_114 : X_OR3
    port map (
      I0 => count_0_D2_PT_0,
      I1 => count_0_D2_PT_1,
      I2 => count_0_D2_PT_2,
      O => count_0_D2
    );
  count_0_SETF_115 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => CLK_SCALE(0),
      O => count_0_SETF
    );
  count_0_RSTF_116 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_0_RSTF_IN1,
      O => count_0_RSTF
    );
  count_0_EXP_tsimrenamed_net_Q_117 : X_AND4
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN1,
      I2 => count(2),
      I3 => NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN3,
      O => count_0_EXP_tsimrenamed_net_Q
    );
  count_4_Q_118 : X_BUF
    port map (
      I => count_4_Q,
      O => count(4)
    );
  count_4_EXP_119 : X_BUF
    port map (
      I => count_4_EXP_tsimrenamed_net_Q,
      O => count_4_EXP
    );
  count_4_tsimcreated_xor_Q_120 : X_XOR2
    port map (
      I0 => count_4_D,
      I1 => count_4_Q,
      O => count_4_tsimcreated_xor_Q
    );
  count_4_tsimcreated_set_and_noreset_Q_121 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0,
      I1 => count_4_SETF,
      O => count_4_tsimcreated_set_and_noreset_Q
    );
  count_4_tsimcreated_prld_Q_122 : X_OR2
    port map (
      I0 => count_4_RSTF,
      I1 => PRLD,
      O => count_4_tsimcreated_prld_Q
    );
  count_4_REG : X_FF
    port map (
      I => count_4_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_4_tsimcreated_set_and_noreset_Q,
      RST => count_4_tsimcreated_prld_Q,
      O => count_4_Q
    );
  count_4_D_123 : X_XOR2
    port map (
      I0 => count_4_D1,
      I1 => count_4_D2,
      O => count_4_D
    );
  count_4_D1_124 : X_ZERO
    port map (
      O => count_4_D1
    );
  count_4_D2_PT_0_125 : X_AND2
    port map (
      I0 => CLK_SCALE_0_EXP,
      I1 => CLK_SCALE_0_EXP,
      O => count_4_D2_PT_0
    );
  count_4_D2_PT_1_126 : X_AND6
    port map (
      I0 => NlwInverterSignal_count_4_D2_PT_1_IN0,
      I1 => NlwInverterSignal_count_4_D2_PT_1_IN1,
      I2 => NlwInverterSignal_count_4_D2_PT_1_IN2,
      I3 => NlwInverterSignal_count_4_D2_PT_1_IN3,
      I4 => NlwInverterSignal_count_4_D2_PT_1_IN4,
      I5 => NlwInverterSignal_count_4_D2_PT_1_IN5,
      O => count_4_D2_PT_1
    );
  count_4_D2_PT_2_127 : X_AND7
    port map (
      I0 => NlwInverterSignal_count_4_D2_PT_2_IN0,
      I1 => NlwInverterSignal_count_4_D2_PT_2_IN1,
      I2 => NlwInverterSignal_count_4_D2_PT_2_IN2,
      I3 => NlwInverterSignal_count_4_D2_PT_2_IN3,
      I4 => NlwInverterSignal_count_4_D2_PT_2_IN4,
      I5 => NlwInverterSignal_count_4_D2_PT_2_IN5,
      I6 => CLK_SCALE(4),
      O => count_4_D2_PT_2
    );
  count_4_D2_128 : X_OR3
    port map (
      I0 => count_4_D2_PT_0,
      I1 => count_4_D2_PT_1,
      I2 => count_4_D2_PT_2,
      O => count_4_D2
    );
  count_4_SETF_129 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => CLK_SCALE(4),
      O => count_4_SETF
    );
  count_4_RSTF_130 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_4_RSTF_IN1,
      O => count_4_RSTF
    );
  count_4_EXP_tsimrenamed_net_Q_131 : X_AND4
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1,
      I2 => count(3),
      I3 => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN3,
      O => count_4_EXP_tsimrenamed_net_Q
    );
  SHIFT_CNT_1_Q_132 : X_BUF
    port map (
      I => SHIFT_CNT_1_Q,
      O => SHIFT_CNT(1)
    );
  SHIFT_CNT_1_tsimcreated_xor_Q_133 : X_XOR2
    port map (
      I0 => SHIFT_CNT_1_D,
      I1 => SHIFT_CNT_1_Q,
      O => SHIFT_CNT_1_tsimcreated_xor_Q
    );
  SHIFT_CNT_1_tsimcreated_set_and_noreset_Q_134 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0,
      I1 => SHIFT_CNT_1_SETF,
      O => SHIFT_CNT_1_tsimcreated_set_and_noreset_Q
    );
  SHIFT_CNT_1_tsimcreated_prld_Q_135 : X_OR2
    port map (
      I0 => SHIFT_CNT_1_RSTF,
      I1 => PRLD,
      O => SHIFT_CNT_1_tsimcreated_prld_Q
    );
  SHIFT_CNT_1_REG : X_FF
    port map (
      I => SHIFT_CNT_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => SHIFT_CNT_1_CLKF,
      SET => SHIFT_CNT_1_tsimcreated_set_and_noreset_Q,
      RST => SHIFT_CNT_1_tsimcreated_prld_Q,
      O => SHIFT_CNT_1_Q
    );
  SHIFT_CNT_1_D_136 : X_XOR2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_1_D_IN0,
      I1 => SHIFT_CNT_1_D2,
      O => SHIFT_CNT_1_D
    );
  SHIFT_CNT_1_D1_137 : X_ZERO
    port map (
      O => SHIFT_CNT_1_D1
    );
  SHIFT_CNT_1_D2_PT_0_138 : X_AND2
    port map (
      I0 => SHIFT_CNT(0),
      I1 => SHIFT_CNT(0),
      O => SHIFT_CNT_1_D2_PT_0
    );
  SHIFT_CNT_1_D2_PT_1_139 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN1,
      O => SHIFT_CNT_1_D2_PT_1
    );
  SHIFT_CNT_1_D2_PT_2_140 : X_AND2
    port map (
      I0 => SHIFT_CNT_2_EXP,
      I1 => SHIFT_CNT_2_EXP,
      O => SHIFT_CNT_1_D2_PT_2
    );
  SHIFT_CNT_1_D2_PT_3_141 : X_AND2
    port map (
      I0 => SHIFT_CNT_3_EXP,
      I1 => SHIFT_CNT_3_EXP,
      O => SHIFT_CNT_1_D2_PT_3
    );
  SHIFT_CNT_1_D2_142 : X_OR4
    port map (
      I0 => SHIFT_CNT_1_D2_PT_0,
      I1 => SHIFT_CNT_1_D2_PT_1,
      I2 => SHIFT_CNT_1_D2_PT_2,
      I3 => SHIFT_CNT_1_D2_PT_3,
      O => SHIFT_CNT_1_D2
    );
  SHIFT_CNT_1_CLKF_143 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_1_CLKF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_1_CLKF_IN1,
      O => SHIFT_CNT_1_CLKF
    );
  SHIFT_CNT_1_SETF_144 : X_AND2
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_SHIFT_CNT_1_SETF_IN1,
      O => SHIFT_CNT_1_SETF
    );
  SHIFT_CNT_1_RSTF_145 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => SHIFT_CNT_1_RSTF
    );
  SHIFT_CNT_2_Q_146 : X_BUF
    port map (
      I => SHIFT_CNT_2_Q,
      O => SHIFT_CNT(2)
    );
  SHIFT_CNT_2_EXP_147 : X_BUF
    port map (
      I => SHIFT_CNT_2_EXP_tsimrenamed_net_Q,
      O => SHIFT_CNT_2_EXP
    );
  SHIFT_CNT_2_tsimcreated_xor_Q_148 : X_XOR2
    port map (
      I0 => SHIFT_CNT_2_D,
      I1 => SHIFT_CNT_2_Q,
      O => SHIFT_CNT_2_tsimcreated_xor_Q
    );
  SHIFT_CNT_2_tsimcreated_set_and_noreset_Q_149 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0,
      I1 => SHIFT_CNT_2_SETF,
      O => SHIFT_CNT_2_tsimcreated_set_and_noreset_Q
    );
  SHIFT_CNT_2_tsimcreated_prld_Q_150 : X_OR2
    port map (
      I0 => SHIFT_CNT_2_RSTF,
      I1 => PRLD,
      O => SHIFT_CNT_2_tsimcreated_prld_Q
    );
  SHIFT_CNT_2_REG : X_FF
    port map (
      I => SHIFT_CNT_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => SHIFT_CNT_2_CLKF,
      SET => SHIFT_CNT_2_tsimcreated_set_and_noreset_Q,
      RST => SHIFT_CNT_2_tsimcreated_prld_Q,
      O => SHIFT_CNT_2_Q
    );
  SHIFT_CNT_2_D_151 : X_XOR2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_2_D_IN0,
      I1 => SHIFT_CNT_2_D2,
      O => SHIFT_CNT_2_D
    );
  SHIFT_CNT_2_D1_152 : X_ZERO
    port map (
      O => SHIFT_CNT_2_D1
    );
  SHIFT_CNT_2_D2_PT_0_153 : X_AND2
    port map (
      I0 => SHIFT_CNT(0),
      I1 => SHIFT_CNT(0),
      O => SHIFT_CNT_2_D2_PT_0
    );
  SHIFT_CNT_2_D2_PT_1_154 : X_AND2
    port map (
      I0 => BUF_IS_EMPTY_OBUF_EXP,
      I1 => BUF_IS_EMPTY_OBUF_EXP,
      O => SHIFT_CNT_2_D2_PT_1
    );
  SHIFT_CNT_2_D2_155 : X_OR2
    port map (
      I0 => SHIFT_CNT_2_D2_PT_0,
      I1 => SHIFT_CNT_2_D2_PT_1,
      O => SHIFT_CNT_2_D2
    );
  SHIFT_CNT_2_CLKF_156 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_2_CLKF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_2_CLKF_IN1,
      O => SHIFT_CNT_2_CLKF
    );
  SHIFT_CNT_2_SETF_157 : X_AND2
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_SHIFT_CNT_2_SETF_IN1,
      O => SHIFT_CNT_2_SETF
    );
  SHIFT_CNT_2_RSTF_158 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => SHIFT_CNT_2_RSTF
    );
  SHIFT_CNT_2_EXP_tsimrenamed_net_Q_159 : X_AND6
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN2,
      I3 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN3,
      I4 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN4,
      I5 => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN5,
      O => SHIFT_CNT_2_EXP_tsimrenamed_net_Q
    );
  SHIFT_CNT_3_Q_160 : X_BUF
    port map (
      I => SHIFT_CNT_3_Q,
      O => SHIFT_CNT(3)
    );
  SHIFT_CNT_3_EXP_161 : X_BUF
    port map (
      I => SHIFT_CNT_3_EXP_tsimrenamed_net_Q,
      O => SHIFT_CNT_3_EXP
    );
  SHIFT_CNT_3_tsimcreated_xor_Q_162 : X_XOR2
    port map (
      I0 => SHIFT_CNT_3_D,
      I1 => SHIFT_CNT_3_Q,
      O => SHIFT_CNT_3_tsimcreated_xor_Q
    );
  SHIFT_CNT_3_tsimcreated_set_and_noreset_Q_163 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0,
      I1 => SHIFT_CNT_3_SETF,
      O => SHIFT_CNT_3_tsimcreated_set_and_noreset_Q
    );
  SHIFT_CNT_3_tsimcreated_prld_Q_164 : X_OR2
    port map (
      I0 => SHIFT_CNT_3_RSTF,
      I1 => PRLD,
      O => SHIFT_CNT_3_tsimcreated_prld_Q
    );
  SHIFT_CNT_3_REG : X_FF
    port map (
      I => SHIFT_CNT_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => SHIFT_CNT_3_CLKF,
      SET => SHIFT_CNT_3_tsimcreated_set_and_noreset_Q,
      RST => SHIFT_CNT_3_tsimcreated_prld_Q,
      O => SHIFT_CNT_3_Q
    );
  SHIFT_CNT_3_D_165 : X_XOR2
    port map (
      I0 => SHIFT_CNT_3_D1,
      I1 => SHIFT_CNT_3_D2,
      O => SHIFT_CNT_3_D
    );
  SHIFT_CNT_3_D1_166 : X_ZERO
    port map (
      O => SHIFT_CNT_3_D1
    );
  SHIFT_CNT_3_D2_PT_0_167 : X_AND2
    port map (
      I0 => buf_depth_0_buf_depth_0_RSTF_EXP,
      I1 => buf_depth_0_buf_depth_0_RSTF_EXP,
      O => SHIFT_CNT_3_D2_PT_0
    );
  SHIFT_CNT_3_D2_PT_1_168 : X_AND6
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN1,
      I2 => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN2,
      I3 => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN3,
      I4 => SHIFT_CNT(3),
      I5 => SHIFT_EN,
      O => SHIFT_CNT_3_D2_PT_1
    );
  SHIFT_CNT_3_D2_169 : X_OR2
    port map (
      I0 => SHIFT_CNT_3_D2_PT_0,
      I1 => SHIFT_CNT_3_D2_PT_1,
      O => SHIFT_CNT_3_D2
    );
  SHIFT_CNT_3_CLKF_170 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_3_CLKF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_3_CLKF_IN1,
      O => SHIFT_CNT_3_CLKF
    );
  SHIFT_CNT_3_SETF_171 : X_AND2
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_SHIFT_CNT_3_SETF_IN1,
      O => SHIFT_CNT_3_SETF
    );
  SHIFT_CNT_3_RSTF_172 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => SHIFT_CNT_3_RSTF
    );
  SHIFT_CNT_3_EXP_tsimrenamed_net_Q_173 : X_AND2
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => LOAD_SREG_IBUF,
      O => SHIFT_CNT_3_EXP_tsimrenamed_net_Q
    );
  count_1_Q_174 : X_BUF
    port map (
      I => count_1_Q,
      O => count(1)
    );
  count_1_tsimcreated_xor_Q_175 : X_XOR2
    port map (
      I0 => count_1_D,
      I1 => count_1_Q,
      O => count_1_tsimcreated_xor_Q
    );
  count_1_tsimcreated_set_and_noreset_Q_176 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0,
      I1 => count_1_SETF,
      O => count_1_tsimcreated_set_and_noreset_Q
    );
  count_1_tsimcreated_prld_Q_177 : X_OR2
    port map (
      I0 => count_1_RSTF,
      I1 => PRLD,
      O => count_1_tsimcreated_prld_Q
    );
  count_1_REG : X_FF
    port map (
      I => count_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_1_tsimcreated_set_and_noreset_Q,
      RST => count_1_tsimcreated_prld_Q,
      O => count_1_Q
    );
  count_1_D_178 : X_XOR2
    port map (
      I0 => count_1_D1,
      I1 => count_1_D2,
      O => count_1_D
    );
  count_1_D1_179 : X_ZERO
    port map (
      O => count_1_D1
    );
  count_1_D2_PT_0_180 : X_AND2
    port map (
      I0 => CLK_SCALE_1_EXP,
      I1 => CLK_SCALE_1_EXP,
      O => count_1_D2_PT_0
    );
  count_1_D2_PT_1_181 : X_AND3
    port map (
      I0 => NlwInverterSignal_count_1_D2_PT_1_IN0,
      I1 => NlwInverterSignal_count_1_D2_PT_1_IN1,
      I2 => NlwInverterSignal_count_1_D2_PT_1_IN2,
      O => count_1_D2_PT_1
    );
  count_1_D2_PT_2_182 : X_AND4
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_1_D2_PT_2_IN1,
      I2 => NlwInverterSignal_count_1_D2_PT_2_IN2,
      I3 => CLK_SCALE(1),
      O => count_1_D2_PT_2
    );
  count_1_D2_PT_3_183 : X_AND7
    port map (
      I0 => NlwInverterSignal_count_1_D2_PT_3_IN0,
      I1 => NlwInverterSignal_count_1_D2_PT_3_IN1,
      I2 => NlwInverterSignal_count_1_D2_PT_3_IN2,
      I3 => NlwInverterSignal_count_1_D2_PT_3_IN3,
      I4 => NlwInverterSignal_count_1_D2_PT_3_IN4,
      I5 => NlwInverterSignal_count_1_D2_PT_3_IN5,
      I6 => CLK_SCALE(1),
      O => count_1_D2_PT_3
    );
  count_1_D2_184 : X_OR4
    port map (
      I0 => count_1_D2_PT_0,
      I1 => count_1_D2_PT_1,
      I2 => count_1_D2_PT_2,
      I3 => count_1_D2_PT_3,
      O => count_1_D2
    );
  count_1_SETF_185 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => CLK_SCALE(1),
      O => count_1_SETF
    );
  count_1_RSTF_186 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_1_RSTF_IN1,
      O => count_1_RSTF
    );
  count_2_Q_187 : X_BUF
    port map (
      I => count_2_Q,
      O => count(2)
    );
  count_2_tsimcreated_xor_Q_188 : X_XOR2
    port map (
      I0 => count_2_D,
      I1 => count_2_Q,
      O => count_2_tsimcreated_xor_Q
    );
  count_2_tsimcreated_set_and_noreset_Q_189 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0,
      I1 => count_2_SETF,
      O => count_2_tsimcreated_set_and_noreset_Q
    );
  count_2_tsimcreated_prld_Q_190 : X_OR2
    port map (
      I0 => count_2_RSTF,
      I1 => PRLD,
      O => count_2_tsimcreated_prld_Q
    );
  count_2_REG : X_FF
    port map (
      I => count_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_2_tsimcreated_set_and_noreset_Q,
      RST => count_2_tsimcreated_prld_Q,
      O => count_2_Q
    );
  count_2_D_191 : X_XOR2
    port map (
      I0 => count_2_D1,
      I1 => count_2_D2,
      O => count_2_D
    );
  count_2_D1_192 : X_ZERO
    port map (
      O => count_2_D1
    );
  count_2_D2_PT_0_193 : X_AND2
    port map (
      I0 => count_0_EXP,
      I1 => count_0_EXP,
      O => count_2_D2_PT_0
    );
  count_2_D2_PT_1_194 : X_AND4
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_2_D2_PT_1_IN1,
      I2 => NlwInverterSignal_count_2_D2_PT_1_IN2,
      I3 => CLK_SCALE(2),
      O => count_2_D2_PT_1
    );
  count_2_D2_PT_2_195 : X_AND4
    port map (
      I0 => NlwInverterSignal_count_2_D2_PT_2_IN0,
      I1 => NlwInverterSignal_count_2_D2_PT_2_IN1,
      I2 => NlwInverterSignal_count_2_D2_PT_2_IN2,
      I3 => NlwInverterSignal_count_2_D2_PT_2_IN3,
      O => count_2_D2_PT_2
    );
  count_2_D2_PT_3_196 : X_AND7
    port map (
      I0 => NlwInverterSignal_count_2_D2_PT_3_IN0,
      I1 => NlwInverterSignal_count_2_D2_PT_3_IN1,
      I2 => NlwInverterSignal_count_2_D2_PT_3_IN2,
      I3 => NlwInverterSignal_count_2_D2_PT_3_IN3,
      I4 => NlwInverterSignal_count_2_D2_PT_3_IN4,
      I5 => NlwInverterSignal_count_2_D2_PT_3_IN5,
      I6 => CLK_SCALE(2),
      O => count_2_D2_PT_3
    );
  count_2_D2_197 : X_OR4
    port map (
      I0 => count_2_D2_PT_0,
      I1 => count_2_D2_PT_1,
      I2 => count_2_D2_PT_2,
      I3 => count_2_D2_PT_3,
      O => count_2_D2
    );
  count_2_SETF_198 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => CLK_SCALE(2),
      O => count_2_SETF
    );
  count_2_RSTF_199 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_2_RSTF_IN1,
      O => count_2_RSTF
    );
  count_3_Q_200 : X_BUF
    port map (
      I => count_3_Q,
      O => count(3)
    );
  count_3_tsimcreated_xor_Q_201 : X_XOR2
    port map (
      I0 => count_3_D,
      I1 => count_3_Q,
      O => count_3_tsimcreated_xor_Q
    );
  count_3_tsimcreated_set_and_noreset_Q_202 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0,
      I1 => count_3_SETF,
      O => count_3_tsimcreated_set_and_noreset_Q
    );
  count_3_tsimcreated_prld_Q_203 : X_OR2
    port map (
      I0 => count_3_RSTF,
      I1 => PRLD,
      O => count_3_tsimcreated_prld_Q
    );
  count_3_REG : X_FF
    port map (
      I => count_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_3_tsimcreated_set_and_noreset_Q,
      RST => count_3_tsimcreated_prld_Q,
      O => count_3_Q
    );
  count_3_D_204 : X_XOR2
    port map (
      I0 => count_3_D1,
      I1 => count_3_D2,
      O => count_3_D
    );
  count_3_D1_205 : X_ZERO
    port map (
      O => count_3_D1
    );
  count_3_D2_PT_0_206 : X_AND2
    port map (
      I0 => count_4_EXP,
      I1 => count_4_EXP,
      O => count_3_D2_PT_0
    );
  count_3_D2_PT_1_207 : X_AND4
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_3_D2_PT_1_IN1,
      I2 => NlwInverterSignal_count_3_D2_PT_1_IN2,
      I3 => CLK_SCALE(3),
      O => count_3_D2_PT_1
    );
  count_3_D2_PT_2_208 : X_AND5
    port map (
      I0 => NlwInverterSignal_count_3_D2_PT_2_IN0,
      I1 => NlwInverterSignal_count_3_D2_PT_2_IN1,
      I2 => NlwInverterSignal_count_3_D2_PT_2_IN2,
      I3 => NlwInverterSignal_count_3_D2_PT_2_IN3,
      I4 => NlwInverterSignal_count_3_D2_PT_2_IN4,
      O => count_3_D2_PT_2
    );
  count_3_D2_PT_3_209 : X_AND7
    port map (
      I0 => NlwInverterSignal_count_3_D2_PT_3_IN0,
      I1 => NlwInverterSignal_count_3_D2_PT_3_IN1,
      I2 => NlwInverterSignal_count_3_D2_PT_3_IN2,
      I3 => NlwInverterSignal_count_3_D2_PT_3_IN3,
      I4 => NlwInverterSignal_count_3_D2_PT_3_IN4,
      I5 => NlwInverterSignal_count_3_D2_PT_3_IN5,
      I6 => CLK_SCALE(3),
      O => count_3_D2_PT_3
    );
  count_3_D2_210 : X_OR4
    port map (
      I0 => count_3_D2_PT_0,
      I1 => count_3_D2_PT_1,
      I2 => count_3_D2_PT_2,
      I3 => count_3_D2_PT_3,
      O => count_3_D2
    );
  count_3_SETF_211 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => CLK_SCALE(3),
      O => count_3_SETF
    );
  count_3_RSTF_212 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_3_RSTF_IN1,
      O => count_3_RSTF
    );
  SHIFT_CNT_4_Q_213 : X_BUF
    port map (
      I => SHIFT_CNT_4_Q,
      O => SHIFT_CNT(4)
    );
  SHIFT_CNT_4_tsimcreated_xor_Q_214 : X_XOR2
    port map (
      I0 => SHIFT_CNT_4_D,
      I1 => SHIFT_CNT_4_Q,
      O => SHIFT_CNT_4_tsimcreated_xor_Q
    );
  SHIFT_CNT_4_tsimcreated_set_and_noreset_Q_215 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0,
      I1 => SHIFT_CNT_4_SETF,
      O => SHIFT_CNT_4_tsimcreated_set_and_noreset_Q
    );
  SHIFT_CNT_4_tsimcreated_prld_Q_216 : X_OR2
    port map (
      I0 => SHIFT_CNT_4_RSTF,
      I1 => PRLD,
      O => SHIFT_CNT_4_tsimcreated_prld_Q
    );
  SHIFT_CNT_4_REG : X_FF
    port map (
      I => SHIFT_CNT_4_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => SHIFT_CNT_4_CLKF,
      SET => SHIFT_CNT_4_tsimcreated_set_and_noreset_Q,
      RST => SHIFT_CNT_4_tsimcreated_prld_Q,
      O => SHIFT_CNT_4_Q
    );
  SHIFT_CNT_4_D_217 : X_XOR2
    port map (
      I0 => SHIFT_CNT_4_D1,
      I1 => SHIFT_CNT_4_D2,
      O => SHIFT_CNT_4_D
    );
  SHIFT_CNT_4_D1_218 : X_ZERO
    port map (
      O => SHIFT_CNT_4_D1
    );
  SHIFT_CNT_4_D2_PT_0_219 : X_AND2
    port map (
      I0 => SHIFT_CNT_0_EXP,
      I1 => SHIFT_CNT_0_EXP,
      O => SHIFT_CNT_4_D2_PT_0
    );
  SHIFT_CNT_4_D2_PT_1_220 : X_AND7
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN0,
      I1 => buf_depth(0),
      I2 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN2,
      I3 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN3,
      I4 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN4,
      I5 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN5,
      I6 => SHIFT_EN,
      O => SHIFT_CNT_4_D2_PT_1
    );
  SHIFT_CNT_4_D2_PT_2_221 : X_AND7
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN0,
      I1 => buf_depth(1),
      I2 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN2,
      I3 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN3,
      I4 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN4,
      I5 => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN5,
      I6 => SHIFT_EN,
      O => SHIFT_CNT_4_D2_PT_2
    );
  SHIFT_CNT_4_D2_222 : X_OR3
    port map (
      I0 => SHIFT_CNT_4_D2_PT_0,
      I1 => SHIFT_CNT_4_D2_PT_1,
      I2 => SHIFT_CNT_4_D2_PT_2,
      O => SHIFT_CNT_4_D2
    );
  SHIFT_CNT_4_CLKF_223 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_CNT_4_CLKF_IN0,
      I1 => NlwInverterSignal_SHIFT_CNT_4_CLKF_IN1,
      O => SHIFT_CNT_4_CLKF
    );
  SHIFT_CNT_4_SETF_224 : X_AND2
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_SHIFT_CNT_4_SETF_IN1,
      O => SHIFT_CNT_4_SETF
    );
  SHIFT_CNT_4_RSTF_225 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => SHIFT_CNT_4_RSTF
    );
  count_5_Q_226 : X_BUF
    port map (
      I => count_5_Q,
      O => count(5)
    );
  count_5_EXP_227 : X_BUF
    port map (
      I => count_5_EXP_tsimrenamed_net_Q,
      O => count_5_EXP
    );
  count_5_tsimcreated_xor_Q_228 : X_XOR2
    port map (
      I0 => count_5_D,
      I1 => count_5_Q,
      O => count_5_tsimcreated_xor_Q
    );
  count_5_tsimcreated_set_and_noreset_Q_229 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0,
      I1 => count_5_SETF,
      O => count_5_tsimcreated_set_and_noreset_Q
    );
  count_5_tsimcreated_prld_Q_230 : X_OR2
    port map (
      I0 => count_5_RSTF,
      I1 => PRLD,
      O => count_5_tsimcreated_prld_Q
    );
  count_5_REG : X_FF
    port map (
      I => count_5_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => count_5_tsimcreated_set_and_noreset_Q,
      RST => count_5_tsimcreated_prld_Q,
      O => count_5_Q
    );
  count_5_D_231 : X_XOR2
    port map (
      I0 => count_5_D1,
      I1 => count_5_D2,
      O => count_5_D
    );
  count_5_D1_232 : X_ZERO
    port map (
      O => count_5_D1
    );
  count_5_D2_PT_0_233 : X_AND2
    port map (
      I0 => CLK_SCALE_2_EXP,
      I1 => CLK_SCALE_2_EXP,
      O => count_5_D2_PT_0
    );
  count_5_D2_PT_1_234 : X_AND4
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_5_D2_PT_1_IN1,
      I2 => count(5),
      I3 => NlwInverterSignal_count_5_D2_PT_1_IN3,
      O => count_5_D2_PT_1
    );
  count_5_D2_PT_2_235 : X_AND4
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_5_D2_PT_2_IN1,
      I2 => NlwInverterSignal_count_5_D2_PT_2_IN2,
      I3 => CLK_SCALE(5),
      O => count_5_D2_PT_2
    );
  count_5_D2_236 : X_OR3
    port map (
      I0 => count_5_D2_PT_0,
      I1 => count_5_D2_PT_1,
      I2 => count_5_D2_PT_2,
      O => count_5_D2
    );
  count_5_SETF_237 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => CLK_SCALE(5),
      O => count_5_SETF
    );
  count_5_RSTF_238 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_count_5_RSTF_IN1,
      O => count_5_RSTF
    );
  count_5_EXP_tsimrenamed_net_Q_239 : X_AND2
    port map (
      I0 => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0,
      I1 => CLK_SCALE(0),
      O => count_5_EXP_tsimrenamed_net_Q
    );
  writeBufId_0_Q_240 : X_BUF
    port map (
      I => writeBufId_0_Q,
      O => writeBufId(0)
    );
  writeBufId_0_tsimcreated_prld_Q_241 : X_OR2
    port map (
      I0 => writeBufId_0_RSTF,
      I1 => PRLD,
      O => writeBufId_0_tsimcreated_prld_Q
    );
  writeBufId_0_REG : X_FF
    port map (
      I => writeBufId_0_D,
      CE => writeBufId_0_CE,
      CLK => writeBufId_0_CLKF,
      SET => Gnd,
      RST => writeBufId_0_tsimcreated_prld_Q,
      O => writeBufId_0_Q
    );
  writeBufId_0_D_242 : X_XOR2
    port map (
      I0 => writeBufId_0_D1,
      I1 => writeBufId_0_D2,
      O => writeBufId_0_D
    );
  writeBufId_0_D1_243 : X_ZERO
    port map (
      O => writeBufId_0_D1
    );
  writeBufId_0_D2_PT_0_244 : X_AND2
    port map (
      I0 => buf_depth(0),
      I1 => tempID(0),
      O => writeBufId_0_D2_PT_0
    );
  writeBufId_0_D2_PT_1_245 : X_AND2
    port map (
      I0 => buf_depth(1),
      I1 => tempID(0),
      O => writeBufId_0_D2_PT_1
    );
  writeBufId_0_D2_246 : X_OR2
    port map (
      I0 => writeBufId_0_D2_PT_0,
      I1 => writeBufId_0_D2_PT_1,
      O => writeBufId_0_D2
    );
  writeBufId_0_CLKF_247 : X_AND2
    port map (
      I0 => NlwInverterSignal_writeBufId_0_CLKF_IN0,
      I1 => NlwInverterSignal_writeBufId_0_CLKF_IN1,
      O => writeBufId_0_CLKF
    );
  writeBufId_0_RSTF_248 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => writeBufId_0_RSTF
    );
  writeBufId_0_CE_249 : X_AND7
    port map (
      I0 => NlwInverterSignal_writeBufId_0_CE_IN0,
      I1 => NlwInverterSignal_writeBufId_0_CE_IN1,
      I2 => NlwInverterSignal_writeBufId_0_CE_IN2,
      I3 => NlwInverterSignal_writeBufId_0_CE_IN3,
      I4 => NlwInverterSignal_writeBufId_0_CE_IN4,
      I5 => NlwInverterSignal_writeBufId_0_CE_IN5,
      I6 => SHIFT_EN,
      O => writeBufId_0_CE
    );
  CLK_SCALE_0_Q_250 : X_BUF
    port map (
      I => CLK_SCALE_0_Q,
      O => CLK_SCALE(0)
    );
  CLK_SCALE_0_EXP_251 : X_BUF
    port map (
      I => CLK_SCALE_0_EXP_tsimrenamed_net_Q,
      O => CLK_SCALE_0_EXP
    );
  CLK_SCALE_0_Q_252 : X_BUF
    port map (
      I => CLK_SCALE_0_D,
      O => CLK_SCALE_0_Q
    );
  CLK_SCALE_0_D_253 : X_XOR2
    port map (
      I0 => CLK_SCALE_0_D1,
      I1 => CLK_SCALE_0_D2,
      O => CLK_SCALE_0_D
    );
  CLK_SCALE_0_D1_254 : X_ZERO
    port map (
      O => CLK_SCALE_0_D1
    );
  CLK_SCALE_0_D2_PT_0_255 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => CLK_SCALE_0_D2_PT_0
    );
  CLK_SCALE_0_D2_PT_1_256 : X_AND2
    port map (
      I0 => count_5_EXP,
      I1 => count_5_EXP,
      O => CLK_SCALE_0_D2_PT_1
    );
  CLK_SCALE_0_D2_PT_2_257 : X_AND2
    port map (
      I0 => LOAD_PRESCALER_IBUF,
      I1 => CCLK_PRESCALER_0_IBUF,
      O => CLK_SCALE_0_D2_PT_2
    );
  CLK_SCALE_0_D2_PT_3_258 : X_AND2
    port map (
      I0 => CLK_SCALE(0),
      I1 => CCLK_PRESCALER_0_IBUF,
      O => CLK_SCALE_0_D2_PT_3
    );
  CLK_SCALE_0_D2_259 : X_OR4
    port map (
      I0 => CLK_SCALE_0_D2_PT_0,
      I1 => CLK_SCALE_0_D2_PT_1,
      I2 => CLK_SCALE_0_D2_PT_2,
      I3 => CLK_SCALE_0_D2_PT_3,
      O => CLK_SCALE_0_D2
    );
  CLK_SCALE_0_EXP_PT_0_260 : X_AND4
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN1,
      I2 => count(4),
      I3 => NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN3,
      O => CLK_SCALE_0_EXP_PT_0
    );
  CLK_SCALE_0_EXP_PT_1_261 : X_AND4
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN1,
      I2 => NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN2,
      I3 => CLK_SCALE(4),
      O => CLK_SCALE_0_EXP_PT_1
    );
  CLK_SCALE_0_EXP_tsimrenamed_net_Q_262 : X_OR2
    port map (
      I0 => CLK_SCALE_0_EXP_PT_0,
      I1 => CLK_SCALE_0_EXP_PT_1,
      O => CLK_SCALE_0_EXP_tsimrenamed_net_Q
    );
  REG_0_0_263 : X_BUF
    port map (
      I => REG_0_0_Q,
      O => REG_0_0
    );
  REG_0_0_EXP_264 : X_BUF
    port map (
      I => REG_0_0_EXP_tsimrenamed_net_Q,
      O => REG_0_0_EXP
    );
  REG_0_0_tsimcreated_xor_Q_265 : X_XOR2
    port map (
      I0 => REG_0_0_D,
      I1 => REG_0_0_Q,
      O => REG_0_0_tsimcreated_xor_Q
    );
  REG_0_0_tsimcreated_set_and_noreset_Q_266 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_0_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_0_SETF,
      O => REG_0_0_tsimcreated_set_and_noreset_Q
    );
  REG_0_0_tsimcreated_prld_Q_267 : X_OR2
    port map (
      I0 => REG_0_0_RSTF,
      I1 => PRLD,
      O => REG_0_0_tsimcreated_prld_Q
    );
  REG_0_0_REG : X_FF
    port map (
      I => REG_0_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_0_CLKF,
      SET => REG_0_0_tsimcreated_set_and_noreset_Q,
      RST => REG_0_0_tsimcreated_prld_Q,
      O => REG_0_0_Q
    );
  REG_0_0_D_268 : X_XOR2
    port map (
      I0 => REG_0_0_D1,
      I1 => REG_0_0_D2,
      O => REG_0_0_D
    );
  REG_0_0_D1_269 : X_ZERO
    port map (
      O => REG_0_0_D1
    );
  REG_0_0_D2_270 : X_AND2
    port map (
      I0 => EXP22_EXP,
      I1 => EXP22_EXP,
      O => REG_0_0_D2
    );
  REG_0_0_CLKF_271 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_0_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_0_CLKF_IN1,
      O => REG_0_0_CLKF
    );
  REG_0_0_SETF_272 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_0_SETF_IN1,
      I2 => DIN_0_IBUF,
      O => REG_0_0_SETF
    );
  REG_0_0_RSTF_273 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_0_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_0_RSTF_IN2,
      O => REG_0_0_RSTF
    );
  REG_0_0_EXP_PT_0_274 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_0_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_0_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_0_EXP_PT_0_IN4,
      I5 => REG_0_4,
      I6 => NlwInverterSignal_REG_0_0_EXP_PT_0_IN6,
      O => REG_0_0_EXP_PT_0
    );
  REG_0_0_EXP_PT_1_275 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_0_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_0_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_0_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_REG_0_0_EXP_PT_1_IN5,
      I6 => DIN_4_IBUF,
      O => REG_0_0_EXP_PT_1
    );
  REG_0_0_EXP_tsimrenamed_net_Q_276 : X_OR2
    port map (
      I0 => REG_0_0_EXP_PT_0,
      I1 => REG_0_0_EXP_PT_1,
      O => REG_0_0_EXP_tsimrenamed_net_Q
    );
  REG_0_1_277 : X_BUF
    port map (
      I => REG_0_1_Q,
      O => REG_0_1
    );
  REG_0_1_tsimcreated_xor_Q_278 : X_XOR2
    port map (
      I0 => REG_0_1_D,
      I1 => REG_0_1_Q,
      O => REG_0_1_tsimcreated_xor_Q
    );
  REG_0_1_tsimcreated_set_and_noreset_Q_279 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_1_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_1_SETF,
      O => REG_0_1_tsimcreated_set_and_noreset_Q
    );
  REG_0_1_tsimcreated_prld_Q_280 : X_OR2
    port map (
      I0 => REG_0_1_RSTF,
      I1 => PRLD,
      O => REG_0_1_tsimcreated_prld_Q
    );
  REG_0_1_REG : X_FF
    port map (
      I => REG_0_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_1_CLKF,
      SET => REG_0_1_tsimcreated_set_and_noreset_Q,
      RST => REG_0_1_tsimcreated_prld_Q,
      O => REG_0_1_Q
    );
  REG_0_1_D_281 : X_XOR2
    port map (
      I0 => REG_0_1_D1,
      I1 => REG_0_1_D2,
      O => REG_0_1_D
    );
  REG_0_1_D1_282 : X_ZERO
    port map (
      O => REG_0_1_D1
    );
  REG_0_1_D2_PT_0_283 : X_AND2
    port map (
      I0 => EXP18_EXP,
      I1 => EXP18_EXP,
      O => REG_0_1_D2_PT_0
    );
  REG_0_1_D2_PT_1_284 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_1_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_1_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_1_D2_PT_1_IN3,
      I4 => REG_0_0,
      I5 => NlwInverterSignal_REG_0_1_D2_PT_1_IN5,
      O => REG_0_1_D2_PT_1
    );
  REG_0_1_D2_PT_2_285 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_1_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_1_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_1_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_1_D2_PT_2_IN4,
      I5 => REG_0_1,
      O => REG_0_1_D2_PT_2
    );
  REG_0_1_D2_286 : X_OR3
    port map (
      I0 => REG_0_1_D2_PT_0,
      I1 => REG_0_1_D2_PT_1,
      I2 => REG_0_1_D2_PT_2,
      O => REG_0_1_D2
    );
  REG_0_1_CLKF_287 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_1_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_1_CLKF_IN1,
      O => REG_0_1_CLKF
    );
  REG_0_1_SETF_288 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_1_SETF_IN1,
      I2 => DIN_1_IBUF,
      O => REG_0_1_SETF
    );
  REG_0_1_RSTF_289 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_1_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_1_RSTF_IN2,
      O => REG_0_1_RSTF
    );
  REG_0_10_290 : X_BUF
    port map (
      I => REG_0_10_Q,
      O => REG_0_10
    );
  REG_0_10_tsimcreated_xor_Q_291 : X_XOR2
    port map (
      I0 => REG_0_10_D,
      I1 => REG_0_10_Q,
      O => REG_0_10_tsimcreated_xor_Q
    );
  REG_0_10_tsimcreated_set_and_noreset_Q_292 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_10_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_10_SETF,
      O => REG_0_10_tsimcreated_set_and_noreset_Q
    );
  REG_0_10_tsimcreated_prld_Q_293 : X_OR2
    port map (
      I0 => REG_0_10_RSTF,
      I1 => PRLD,
      O => REG_0_10_tsimcreated_prld_Q
    );
  REG_0_10_REG : X_FF
    port map (
      I => REG_0_10_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_10_CLKF,
      SET => REG_0_10_tsimcreated_set_and_noreset_Q,
      RST => REG_0_10_tsimcreated_prld_Q,
      O => REG_0_10_Q
    );
  REG_0_10_D_294 : X_XOR2
    port map (
      I0 => REG_0_10_D1,
      I1 => REG_0_10_D2,
      O => REG_0_10_D
    );
  REG_0_10_D1_295 : X_ZERO
    port map (
      O => REG_0_10_D1
    );
  REG_0_10_D2_PT_0_296 : X_AND2
    port map (
      I0 => EXP65_EXP,
      I1 => EXP65_EXP,
      O => REG_0_10_D2_PT_0
    );
  REG_0_10_D2_PT_1_297 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_10_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_10_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_10_D2_PT_1_IN3,
      I4 => REG_0_10,
      I5 => NlwInverterSignal_REG_0_10_D2_PT_1_IN5,
      O => REG_0_10_D2_PT_1
    );
  REG_0_10_D2_PT_2_298 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_10_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_10_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_10_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_10_D2_PT_2_IN4,
      I5 => REG_0_9,
      O => REG_0_10_D2_PT_2
    );
  REG_0_10_D2_299 : X_OR3
    port map (
      I0 => REG_0_10_D2_PT_0,
      I1 => REG_0_10_D2_PT_1,
      I2 => REG_0_10_D2_PT_2,
      O => REG_0_10_D2
    );
  REG_0_10_CLKF_300 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_10_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_10_CLKF_IN1,
      O => REG_0_10_CLKF
    );
  REG_0_10_SETF_301 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_10_SETF_IN1,
      I2 => DIN_10_IBUF,
      O => REG_0_10_SETF
    );
  REG_0_10_RSTF_302 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_10_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_10_RSTF_IN2,
      O => REG_0_10_RSTF
    );
  REG_0_11_303 : X_BUF
    port map (
      I => REG_0_11_Q,
      O => REG_0_11
    );
  REG_0_11_tsimcreated_xor_Q_304 : X_XOR2
    port map (
      I0 => REG_0_11_D,
      I1 => REG_0_11_Q,
      O => REG_0_11_tsimcreated_xor_Q
    );
  REG_0_11_tsimcreated_set_and_noreset_Q_305 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_11_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_11_SETF,
      O => REG_0_11_tsimcreated_set_and_noreset_Q
    );
  REG_0_11_tsimcreated_prld_Q_306 : X_OR2
    port map (
      I0 => REG_0_11_RSTF,
      I1 => PRLD,
      O => REG_0_11_tsimcreated_prld_Q
    );
  REG_0_11_REG : X_FF
    port map (
      I => REG_0_11_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_11_CLKF,
      SET => REG_0_11_tsimcreated_set_and_noreset_Q,
      RST => REG_0_11_tsimcreated_prld_Q,
      O => REG_0_11_Q
    );
  REG_0_11_D_307 : X_XOR2
    port map (
      I0 => REG_0_11_D1,
      I1 => REG_0_11_D2,
      O => REG_0_11_D
    );
  REG_0_11_D1_308 : X_ZERO
    port map (
      O => REG_0_11_D1
    );
  REG_0_11_D2_PT_0_309 : X_AND2
    port map (
      I0 => SHIFT_EN_EXP,
      I1 => SHIFT_EN_EXP,
      O => REG_0_11_D2_PT_0
    );
  REG_0_11_D2_PT_1_310 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_11_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_11_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_11_D2_PT_1_IN3,
      I4 => REG_0_10,
      I5 => NlwInverterSignal_REG_0_11_D2_PT_1_IN5,
      O => REG_0_11_D2_PT_1
    );
  REG_0_11_D2_PT_2_311 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_11_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_11_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_11_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_11_D2_PT_2_IN4,
      I5 => REG_0_11,
      O => REG_0_11_D2_PT_2
    );
  REG_0_11_D2_312 : X_OR3
    port map (
      I0 => REG_0_11_D2_PT_0,
      I1 => REG_0_11_D2_PT_1,
      I2 => REG_0_11_D2_PT_2,
      O => REG_0_11_D2
    );
  REG_0_11_CLKF_313 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_11_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_11_CLKF_IN1,
      O => REG_0_11_CLKF
    );
  REG_0_11_SETF_314 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_11_SETF_IN1,
      I2 => DIN_11_IBUF,
      O => REG_0_11_SETF
    );
  REG_0_11_RSTF_315 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_11_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_11_RSTF_IN2,
      O => REG_0_11_RSTF
    );
  REG_0_12_316 : X_BUF
    port map (
      I => REG_0_12_Q,
      O => REG_0_12
    );
  REG_0_12_tsimcreated_xor_Q_317 : X_XOR2
    port map (
      I0 => REG_0_12_D,
      I1 => REG_0_12_Q,
      O => REG_0_12_tsimcreated_xor_Q
    );
  REG_0_12_tsimcreated_set_and_noreset_Q_318 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_12_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_12_SETF,
      O => REG_0_12_tsimcreated_set_and_noreset_Q
    );
  REG_0_12_tsimcreated_prld_Q_319 : X_OR2
    port map (
      I0 => REG_0_12_RSTF,
      I1 => PRLD,
      O => REG_0_12_tsimcreated_prld_Q
    );
  REG_0_12_REG : X_FF
    port map (
      I => REG_0_12_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_12_CLKF,
      SET => REG_0_12_tsimcreated_set_and_noreset_Q,
      RST => REG_0_12_tsimcreated_prld_Q,
      O => REG_0_12_Q
    );
  REG_0_12_D_320 : X_XOR2
    port map (
      I0 => REG_0_12_D1,
      I1 => REG_0_12_D2,
      O => REG_0_12_D
    );
  REG_0_12_D1_321 : X_ZERO
    port map (
      O => REG_0_12_D1
    );
  REG_0_12_D2_PT_0_322 : X_AND2
    port map (
      I0 => REG_0_13_EXP,
      I1 => REG_0_13_EXP,
      O => REG_0_12_D2_PT_0
    );
  REG_0_12_D2_PT_1_323 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_12_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_12_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_12_D2_PT_1_IN3,
      I4 => REG_0_11,
      I5 => NlwInverterSignal_REG_0_12_D2_PT_1_IN5,
      O => REG_0_12_D2_PT_1
    );
  REG_0_12_D2_PT_2_324 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_12_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_12_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_12_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_12_D2_PT_2_IN4,
      I5 => REG_0_12,
      O => REG_0_12_D2_PT_2
    );
  REG_0_12_D2_325 : X_OR3
    port map (
      I0 => REG_0_12_D2_PT_0,
      I1 => REG_0_12_D2_PT_1,
      I2 => REG_0_12_D2_PT_2,
      O => REG_0_12_D2
    );
  REG_0_12_CLKF_326 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_12_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_12_CLKF_IN1,
      O => REG_0_12_CLKF
    );
  REG_0_12_SETF_327 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_12_SETF_IN1,
      I2 => DIN_12_IBUF,
      O => REG_0_12_SETF
    );
  REG_0_12_RSTF_328 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_12_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_12_RSTF_IN2,
      O => REG_0_12_RSTF
    );
  REG_0_13_329 : X_BUF
    port map (
      I => REG_0_13_Q,
      O => REG_0_13
    );
  REG_0_13_EXP_330 : X_BUF
    port map (
      I => REG_0_13_EXP_tsimrenamed_net_Q,
      O => REG_0_13_EXP
    );
  REG_0_13_tsimcreated_xor_Q_331 : X_XOR2
    port map (
      I0 => REG_0_13_D,
      I1 => REG_0_13_Q,
      O => REG_0_13_tsimcreated_xor_Q
    );
  REG_0_13_tsimcreated_set_and_noreset_Q_332 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_13_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_13_SETF,
      O => REG_0_13_tsimcreated_set_and_noreset_Q
    );
  REG_0_13_tsimcreated_prld_Q_333 : X_OR2
    port map (
      I0 => REG_0_13_RSTF,
      I1 => PRLD,
      O => REG_0_13_tsimcreated_prld_Q
    );
  REG_0_13_REG : X_FF
    port map (
      I => REG_0_13_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_13_CLKF,
      SET => REG_0_13_tsimcreated_set_and_noreset_Q,
      RST => REG_0_13_tsimcreated_prld_Q,
      O => REG_0_13_Q
    );
  REG_0_13_D_334 : X_XOR2
    port map (
      I0 => REG_0_13_D1,
      I1 => REG_0_13_D2,
      O => REG_0_13_D
    );
  REG_0_13_D1_335 : X_ZERO
    port map (
      O => REG_0_13_D1
    );
  REG_0_13_D2_336 : X_AND2
    port map (
      I0 => CCLK_OBUF_EXP,
      I1 => CCLK_OBUF_EXP,
      O => REG_0_13_D2
    );
  REG_0_13_CLKF_337 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_13_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_13_CLKF_IN1,
      O => REG_0_13_CLKF
    );
  REG_0_13_SETF_338 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_13_SETF_IN1,
      I2 => DIN_13_IBUF,
      O => REG_0_13_SETF
    );
  REG_0_13_RSTF_339 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_13_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_13_RSTF_IN2,
      O => REG_0_13_RSTF
    );
  REG_0_13_EXP_PT_0_340 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_13_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_13_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_13_EXP_PT_0_IN4,
      I5 => DIN_12_IBUF,
      I6 => NlwInverterSignal_REG_0_13_EXP_PT_0_IN6,
      O => REG_0_13_EXP_PT_0
    );
  REG_0_13_EXP_PT_1_341 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_13_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_13_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_13_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_REG_0_13_EXP_PT_1_IN5,
      I6 => REG_0_12,
      O => REG_0_13_EXP_PT_1
    );
  REG_0_13_EXP_tsimrenamed_net_Q_342 : X_OR2
    port map (
      I0 => REG_0_13_EXP_PT_0,
      I1 => REG_0_13_EXP_PT_1,
      O => REG_0_13_EXP_tsimrenamed_net_Q
    );
  REG_0_14_343 : X_BUF
    port map (
      I => REG_0_14_Q,
      O => REG_0_14
    );
  REG_0_14_tsimcreated_xor_Q_344 : X_XOR2
    port map (
      I0 => REG_0_14_D,
      I1 => REG_0_14_Q,
      O => REG_0_14_tsimcreated_xor_Q
    );
  REG_0_14_tsimcreated_set_and_noreset_Q_345 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_14_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_14_SETF,
      O => REG_0_14_tsimcreated_set_and_noreset_Q
    );
  REG_0_14_tsimcreated_prld_Q_346 : X_OR2
    port map (
      I0 => REG_0_14_RSTF,
      I1 => PRLD,
      O => REG_0_14_tsimcreated_prld_Q
    );
  REG_0_14_REG : X_FF
    port map (
      I => REG_0_14_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_14_CLKF,
      SET => REG_0_14_tsimcreated_set_and_noreset_Q,
      RST => REG_0_14_tsimcreated_prld_Q,
      O => REG_0_14_Q
    );
  REG_0_14_D_347 : X_XOR2
    port map (
      I0 => REG_0_14_D1,
      I1 => REG_0_14_D2,
      O => REG_0_14_D
    );
  REG_0_14_D1_348 : X_ZERO
    port map (
      O => REG_0_14_D1
    );
  REG_0_14_D2_PT_0_349 : X_AND2
    port map (
      I0 => EXP66_EXP,
      I1 => EXP66_EXP,
      O => REG_0_14_D2_PT_0
    );
  REG_0_14_D2_PT_1_350 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_14_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_14_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_14_D2_PT_1_IN3,
      I4 => REG_0_13,
      I5 => NlwInverterSignal_REG_0_14_D2_PT_1_IN5,
      O => REG_0_14_D2_PT_1
    );
  REG_0_14_D2_PT_2_351 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_14_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_14_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_14_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_14_D2_PT_2_IN4,
      I5 => REG_0_14,
      O => REG_0_14_D2_PT_2
    );
  REG_0_14_D2_352 : X_OR3
    port map (
      I0 => REG_0_14_D2_PT_0,
      I1 => REG_0_14_D2_PT_1,
      I2 => REG_0_14_D2_PT_2,
      O => REG_0_14_D2
    );
  REG_0_14_CLKF_353 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_14_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_14_CLKF_IN1,
      O => REG_0_14_CLKF
    );
  REG_0_14_SETF_354 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_14_SETF_IN1,
      I2 => DIN_14_IBUF,
      O => REG_0_14_SETF
    );
  REG_0_14_RSTF_355 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_14_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_14_RSTF_IN2,
      O => REG_0_14_RSTF
    );
  REG_0_15_356 : X_BUF
    port map (
      I => REG_0_15_Q,
      O => REG_0_15
    );
  REG_0_15_EXP_357 : X_BUF
    port map (
      I => REG_0_15_EXP_tsimrenamed_net_Q,
      O => REG_0_15_EXP
    );
  REG_0_15_tsimcreated_xor_Q_358 : X_XOR2
    port map (
      I0 => REG_0_15_D,
      I1 => REG_0_15_Q,
      O => REG_0_15_tsimcreated_xor_Q
    );
  REG_0_15_tsimcreated_set_and_noreset_Q_359 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_15_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_15_SETF,
      O => REG_0_15_tsimcreated_set_and_noreset_Q
    );
  REG_0_15_tsimcreated_prld_Q_360 : X_OR2
    port map (
      I0 => REG_0_15_RSTF,
      I1 => PRLD,
      O => REG_0_15_tsimcreated_prld_Q
    );
  REG_0_15_REG : X_FF
    port map (
      I => REG_0_15_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_15_CLKF,
      SET => REG_0_15_tsimcreated_set_and_noreset_Q,
      RST => REG_0_15_tsimcreated_prld_Q,
      O => REG_0_15_Q
    );
  REG_0_15_D_361 : X_XOR2
    port map (
      I0 => REG_0_15_D1,
      I1 => REG_0_15_D2,
      O => REG_0_15_D
    );
  REG_0_15_D1_362 : X_ZERO
    port map (
      O => REG_0_15_D1
    );
  REG_0_15_D2_PT_0_363 : X_AND2
    port map (
      I0 => EXP30_EXP,
      I1 => EXP30_EXP,
      O => REG_0_15_D2_PT_0
    );
  REG_0_15_D2_PT_1_364 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_15_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_15_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_15_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_0_15_D2_PT_1_IN4,
      I5 => REG_0_15,
      O => REG_0_15_D2_PT_1
    );
  REG_0_15_D2_365 : X_OR2
    port map (
      I0 => REG_0_15_D2_PT_0,
      I1 => REG_0_15_D2_PT_1,
      O => REG_0_15_D2
    );
  REG_0_15_CLKF_366 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_15_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_15_CLKF_IN1,
      O => REG_0_15_CLKF
    );
  REG_0_15_SETF_367 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_15_SETF_IN1,
      I2 => DIN_15_IBUF,
      O => REG_0_15_SETF
    );
  REG_0_15_RSTF_368 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_15_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_15_RSTF_IN2,
      O => REG_0_15_RSTF
    );
  REG_0_15_EXP_tsimrenamed_net_Q_369 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN4,
      I5 => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN5,
      I6 => DIN_16_IBUF,
      O => REG_0_15_EXP_tsimrenamed_net_Q
    );
  REG_0_16_370 : X_BUF
    port map (
      I => REG_0_16_Q,
      O => REG_0_16
    );
  REG_0_16_tsimcreated_xor_Q_371 : X_XOR2
    port map (
      I0 => REG_0_16_D,
      I1 => REG_0_16_Q,
      O => REG_0_16_tsimcreated_xor_Q
    );
  REG_0_16_tsimcreated_set_and_noreset_Q_372 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_16_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_16_SETF,
      O => REG_0_16_tsimcreated_set_and_noreset_Q
    );
  REG_0_16_tsimcreated_prld_Q_373 : X_OR2
    port map (
      I0 => REG_0_16_RSTF,
      I1 => PRLD,
      O => REG_0_16_tsimcreated_prld_Q
    );
  REG_0_16_REG : X_FF
    port map (
      I => REG_0_16_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_16_CLKF,
      SET => REG_0_16_tsimcreated_set_and_noreset_Q,
      RST => REG_0_16_tsimcreated_prld_Q,
      O => REG_0_16_Q
    );
  REG_0_16_D_374 : X_XOR2
    port map (
      I0 => REG_0_16_D1,
      I1 => REG_0_16_D2,
      O => REG_0_16_D
    );
  REG_0_16_D1_375 : X_ZERO
    port map (
      O => REG_0_16_D1
    );
  REG_0_16_D2_PT_0_376 : X_AND2
    port map (
      I0 => REG_0_15_EXP,
      I1 => REG_0_15_EXP,
      O => REG_0_16_D2_PT_0
    );
  REG_0_16_D2_PT_1_377 : X_AND2
    port map (
      I0 => REG_0_17_EXP,
      I1 => REG_0_17_EXP,
      O => REG_0_16_D2_PT_1
    );
  REG_0_16_D2_PT_2_378 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_16_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_16_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_16_D2_PT_2_IN3,
      I4 => REG_0_15,
      I5 => NlwInverterSignal_REG_0_16_D2_PT_2_IN5,
      O => REG_0_16_D2_PT_2
    );
  REG_0_16_D2_PT_3_379 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_16_D2_PT_3_IN0,
      I1 => NlwInverterSignal_REG_0_16_D2_PT_3_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_16_D2_PT_3_IN3,
      I4 => NlwInverterSignal_REG_0_16_D2_PT_3_IN4,
      I5 => REG_0_16,
      O => REG_0_16_D2_PT_3
    );
  REG_0_16_D2_380 : X_OR4
    port map (
      I0 => REG_0_16_D2_PT_0,
      I1 => REG_0_16_D2_PT_1,
      I2 => REG_0_16_D2_PT_2,
      I3 => REG_0_16_D2_PT_3,
      O => REG_0_16_D2
    );
  REG_0_16_CLKF_381 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_16_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_16_CLKF_IN1,
      O => REG_0_16_CLKF
    );
  REG_0_16_SETF_382 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_16_SETF_IN1,
      I2 => DIN_16_IBUF,
      O => REG_0_16_SETF
    );
  REG_0_16_RSTF_383 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_16_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_16_RSTF_IN2,
      O => REG_0_16_RSTF
    );
  REG_0_17_384 : X_BUF
    port map (
      I => REG_0_17_Q,
      O => REG_0_17
    );
  REG_0_17_EXP_385 : X_BUF
    port map (
      I => REG_0_17_EXP_tsimrenamed_net_Q,
      O => REG_0_17_EXP
    );
  REG_0_17_tsimcreated_xor_Q_386 : X_XOR2
    port map (
      I0 => REG_0_17_D,
      I1 => REG_0_17_Q,
      O => REG_0_17_tsimcreated_xor_Q
    );
  REG_0_17_tsimcreated_set_and_noreset_Q_387 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_17_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_17_SETF,
      O => REG_0_17_tsimcreated_set_and_noreset_Q
    );
  REG_0_17_tsimcreated_prld_Q_388 : X_OR2
    port map (
      I0 => REG_0_17_RSTF,
      I1 => PRLD,
      O => REG_0_17_tsimcreated_prld_Q
    );
  REG_0_17_REG : X_FF
    port map (
      I => REG_0_17_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_17_CLKF,
      SET => REG_0_17_tsimcreated_set_and_noreset_Q,
      RST => REG_0_17_tsimcreated_prld_Q,
      O => REG_0_17_Q
    );
  REG_0_17_D_389 : X_XOR2
    port map (
      I0 => REG_0_17_D1,
      I1 => REG_0_17_D2,
      O => REG_0_17_D
    );
  REG_0_17_D1_390 : X_ZERO
    port map (
      O => REG_0_17_D1
    );
  REG_0_17_D2_PT_0_391 : X_AND2
    port map (
      I0 => EXP29_EXP,
      I1 => EXP29_EXP,
      O => REG_0_17_D2_PT_0
    );
  REG_0_17_D2_PT_1_392 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_17_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_17_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_17_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_0_17_D2_PT_1_IN4,
      I5 => REG_0_17,
      O => REG_0_17_D2_PT_1
    );
  REG_0_17_D2_393 : X_OR2
    port map (
      I0 => REG_0_17_D2_PT_0,
      I1 => REG_0_17_D2_PT_1,
      O => REG_0_17_D2
    );
  REG_0_17_CLKF_394 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_17_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_17_CLKF_IN1,
      O => REG_0_17_CLKF
    );
  REG_0_17_SETF_395 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_17_SETF_IN1,
      I2 => DIN_17_IBUF,
      O => REG_0_17_SETF
    );
  REG_0_17_RSTF_396 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_17_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_17_RSTF_IN2,
      O => REG_0_17_RSTF
    );
  REG_0_17_EXP_tsimrenamed_net_Q_397 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN4,
      I5 => REG_0_16,
      I6 => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN6,
      O => REG_0_17_EXP_tsimrenamed_net_Q
    );
  REG_0_18_398 : X_BUF
    port map (
      I => REG_0_18_Q,
      O => REG_0_18
    );
  REG_0_18_tsimcreated_xor_Q_399 : X_XOR2
    port map (
      I0 => REG_0_18_D,
      I1 => REG_0_18_Q,
      O => REG_0_18_tsimcreated_xor_Q
    );
  REG_0_18_tsimcreated_set_and_noreset_Q_400 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_18_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_18_SETF,
      O => REG_0_18_tsimcreated_set_and_noreset_Q
    );
  REG_0_18_tsimcreated_prld_Q_401 : X_OR2
    port map (
      I0 => REG_0_18_RSTF,
      I1 => PRLD,
      O => REG_0_18_tsimcreated_prld_Q
    );
  REG_0_18_REG : X_FF
    port map (
      I => REG_0_18_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_18_CLKF,
      SET => REG_0_18_tsimcreated_set_and_noreset_Q,
      RST => REG_0_18_tsimcreated_prld_Q,
      O => REG_0_18_Q
    );
  REG_0_18_D_402 : X_XOR2
    port map (
      I0 => REG_0_18_D1,
      I1 => REG_0_18_D2,
      O => REG_0_18_D
    );
  REG_0_18_D1_403 : X_ZERO
    port map (
      O => REG_0_18_D1
    );
  REG_0_18_D2_PT_0_404 : X_AND2
    port map (
      I0 => EXP32_EXP,
      I1 => EXP32_EXP,
      O => REG_0_18_D2_PT_0
    );
  REG_0_18_D2_PT_1_405 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_18_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_18_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_18_D2_PT_1_IN3,
      I4 => REG_0_17,
      I5 => NlwInverterSignal_REG_0_18_D2_PT_1_IN5,
      O => REG_0_18_D2_PT_1
    );
  REG_0_18_D2_PT_2_406 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_18_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_18_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_18_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_18_D2_PT_2_IN4,
      I5 => REG_0_18,
      O => REG_0_18_D2_PT_2
    );
  REG_0_18_D2_407 : X_OR3
    port map (
      I0 => REG_0_18_D2_PT_0,
      I1 => REG_0_18_D2_PT_1,
      I2 => REG_0_18_D2_PT_2,
      O => REG_0_18_D2
    );
  REG_0_18_CLKF_408 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_18_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_18_CLKF_IN1,
      O => REG_0_18_CLKF
    );
  REG_0_18_SETF_409 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_18_SETF_IN1,
      I2 => DIN_18_IBUF,
      O => REG_0_18_SETF
    );
  REG_0_18_RSTF_410 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_18_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_18_RSTF_IN2,
      O => REG_0_18_RSTF
    );
  REG_0_19_411 : X_BUF
    port map (
      I => REG_0_19_Q,
      O => REG_0_19
    );
  REG_0_19_tsimcreated_xor_Q_412 : X_XOR2
    port map (
      I0 => REG_0_19_D,
      I1 => REG_0_19_Q,
      O => REG_0_19_tsimcreated_xor_Q
    );
  REG_0_19_tsimcreated_set_and_noreset_Q_413 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_19_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_19_SETF,
      O => REG_0_19_tsimcreated_set_and_noreset_Q
    );
  REG_0_19_tsimcreated_prld_Q_414 : X_OR2
    port map (
      I0 => REG_0_19_RSTF,
      I1 => PRLD,
      O => REG_0_19_tsimcreated_prld_Q
    );
  REG_0_19_REG : X_FF
    port map (
      I => REG_0_19_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_19_CLKF,
      SET => REG_0_19_tsimcreated_set_and_noreset_Q,
      RST => REG_0_19_tsimcreated_prld_Q,
      O => REG_0_19_Q
    );
  REG_0_19_D_415 : X_XOR2
    port map (
      I0 => REG_0_19_D1,
      I1 => REG_0_19_D2,
      O => REG_0_19_D
    );
  REG_0_19_D1_416 : X_ZERO
    port map (
      O => REG_0_19_D1
    );
  REG_0_19_D2_PT_0_417 : X_AND2
    port map (
      I0 => state_0_EXP,
      I1 => state_0_EXP,
      O => REG_0_19_D2_PT_0
    );
  REG_0_19_D2_PT_1_418 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_19_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_19_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_19_D2_PT_1_IN3,
      I4 => REG_0_18,
      I5 => NlwInverterSignal_REG_0_19_D2_PT_1_IN5,
      O => REG_0_19_D2_PT_1
    );
  REG_0_19_D2_PT_2_419 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_19_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_19_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_19_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_19_D2_PT_2_IN4,
      I5 => REG_0_19,
      O => REG_0_19_D2_PT_2
    );
  REG_0_19_D2_420 : X_OR3
    port map (
      I0 => REG_0_19_D2_PT_0,
      I1 => REG_0_19_D2_PT_1,
      I2 => REG_0_19_D2_PT_2,
      O => REG_0_19_D2
    );
  REG_0_19_CLKF_421 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_19_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_19_CLKF_IN1,
      O => REG_0_19_CLKF
    );
  REG_0_19_SETF_422 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_19_SETF_IN1,
      I2 => DIN_19_IBUF,
      O => REG_0_19_SETF
    );
  REG_0_19_RSTF_423 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_19_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_19_RSTF_IN2,
      O => REG_0_19_RSTF
    );
  REG_0_2_424 : X_BUF
    port map (
      I => REG_0_2_Q,
      O => REG_0_2
    );
  REG_0_2_tsimcreated_xor_Q_425 : X_XOR2
    port map (
      I0 => REG_0_2_D,
      I1 => REG_0_2_Q,
      O => REG_0_2_tsimcreated_xor_Q
    );
  REG_0_2_tsimcreated_set_and_noreset_Q_426 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_2_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_2_SETF,
      O => REG_0_2_tsimcreated_set_and_noreset_Q
    );
  REG_0_2_tsimcreated_prld_Q_427 : X_OR2
    port map (
      I0 => REG_0_2_RSTF,
      I1 => PRLD,
      O => REG_0_2_tsimcreated_prld_Q
    );
  REG_0_2_REG : X_FF
    port map (
      I => REG_0_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_2_CLKF,
      SET => REG_0_2_tsimcreated_set_and_noreset_Q,
      RST => REG_0_2_tsimcreated_prld_Q,
      O => REG_0_2_Q
    );
  REG_0_2_D_428 : X_XOR2
    port map (
      I0 => REG_0_2_D1,
      I1 => REG_0_2_D2,
      O => REG_0_2_D
    );
  REG_0_2_D1_429 : X_ZERO
    port map (
      O => REG_0_2_D1
    );
  REG_0_2_D2_PT_0_430 : X_AND2
    port map (
      I0 => REG_0_3_EXP,
      I1 => REG_0_3_EXP,
      O => REG_0_2_D2_PT_0
    );
  REG_0_2_D2_PT_1_431 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_2_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_2_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_2_D2_PT_1_IN3,
      I4 => REG_0_1,
      I5 => NlwInverterSignal_REG_0_2_D2_PT_1_IN5,
      O => REG_0_2_D2_PT_1
    );
  REG_0_2_D2_PT_2_432 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_2_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_2_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_2_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_2_D2_PT_2_IN4,
      I5 => REG_0_2,
      O => REG_0_2_D2_PT_2
    );
  REG_0_2_D2_433 : X_OR3
    port map (
      I0 => REG_0_2_D2_PT_0,
      I1 => REG_0_2_D2_PT_1,
      I2 => REG_0_2_D2_PT_2,
      O => REG_0_2_D2
    );
  REG_0_2_CLKF_434 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_2_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_2_CLKF_IN1,
      O => REG_0_2_CLKF
    );
  REG_0_2_SETF_435 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_2_SETF_IN1,
      I2 => DIN_2_IBUF,
      O => REG_0_2_SETF
    );
  REG_0_2_RSTF_436 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_2_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_2_RSTF_IN2,
      O => REG_0_2_RSTF
    );
  REG_0_20_437 : X_BUF
    port map (
      I => REG_0_20_Q,
      O => REG_0_20
    );
  REG_0_20_tsimcreated_xor_Q_438 : X_XOR2
    port map (
      I0 => REG_0_20_D,
      I1 => REG_0_20_Q,
      O => REG_0_20_tsimcreated_xor_Q
    );
  REG_0_20_tsimcreated_set_and_noreset_Q_439 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_20_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_20_SETF,
      O => REG_0_20_tsimcreated_set_and_noreset_Q
    );
  REG_0_20_tsimcreated_prld_Q_440 : X_OR2
    port map (
      I0 => REG_0_20_RSTF,
      I1 => PRLD,
      O => REG_0_20_tsimcreated_prld_Q
    );
  REG_0_20_REG : X_FF
    port map (
      I => REG_0_20_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_20_CLKF,
      SET => REG_0_20_tsimcreated_set_and_noreset_Q,
      RST => REG_0_20_tsimcreated_prld_Q,
      O => REG_0_20_Q
    );
  REG_0_20_D_441 : X_XOR2
    port map (
      I0 => REG_0_20_D1,
      I1 => REG_0_20_D2,
      O => REG_0_20_D
    );
  REG_0_20_D1_442 : X_ZERO
    port map (
      O => REG_0_20_D1
    );
  REG_0_20_D2_PT_0_443 : X_AND2
    port map (
      I0 => EXP31_EXP,
      I1 => EXP31_EXP,
      O => REG_0_20_D2_PT_0
    );
  REG_0_20_D2_PT_1_444 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_20_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_20_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_20_D2_PT_1_IN3,
      I4 => REG_0_19,
      I5 => NlwInverterSignal_REG_0_20_D2_PT_1_IN5,
      O => REG_0_20_D2_PT_1
    );
  REG_0_20_D2_PT_2_445 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_20_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_20_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_20_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_20_D2_PT_2_IN4,
      I5 => REG_0_20,
      O => REG_0_20_D2_PT_2
    );
  REG_0_20_D2_446 : X_OR3
    port map (
      I0 => REG_0_20_D2_PT_0,
      I1 => REG_0_20_D2_PT_1,
      I2 => REG_0_20_D2_PT_2,
      O => REG_0_20_D2
    );
  REG_0_20_CLKF_447 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_20_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_20_CLKF_IN1,
      O => REG_0_20_CLKF
    );
  REG_0_20_SETF_448 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_20_SETF_IN1,
      I2 => DIN_20_IBUF,
      O => REG_0_20_SETF
    );
  REG_0_20_RSTF_449 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_20_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_20_RSTF_IN2,
      O => REG_0_20_RSTF
    );
  REG_0_21_450 : X_BUF
    port map (
      I => REG_0_21_Q,
      O => REG_0_21
    );
  REG_0_21_EXP_451 : X_BUF
    port map (
      I => REG_0_21_EXP_tsimrenamed_net_Q,
      O => REG_0_21_EXP
    );
  REG_0_21_tsimcreated_xor_Q_452 : X_XOR2
    port map (
      I0 => REG_0_21_D,
      I1 => REG_0_21_Q,
      O => REG_0_21_tsimcreated_xor_Q
    );
  REG_0_21_tsimcreated_set_and_noreset_Q_453 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_21_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_21_SETF,
      O => REG_0_21_tsimcreated_set_and_noreset_Q
    );
  REG_0_21_tsimcreated_prld_Q_454 : X_OR2
    port map (
      I0 => REG_0_21_RSTF,
      I1 => PRLD,
      O => REG_0_21_tsimcreated_prld_Q
    );
  REG_0_21_REG : X_FF
    port map (
      I => REG_0_21_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_21_CLKF,
      SET => REG_0_21_tsimcreated_set_and_noreset_Q,
      RST => REG_0_21_tsimcreated_prld_Q,
      O => REG_0_21_Q
    );
  REG_0_21_D_455 : X_XOR2
    port map (
      I0 => REG_0_21_D1,
      I1 => REG_0_21_D2,
      O => REG_0_21_D
    );
  REG_0_21_D1_456 : X_ZERO
    port map (
      O => REG_0_21_D1
    );
  REG_0_21_D2_PT_0_457 : X_AND2
    port map (
      I0 => EXP34_EXP,
      I1 => EXP34_EXP,
      O => REG_0_21_D2_PT_0
    );
  REG_0_21_D2_PT_1_458 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_21_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_21_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_21_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_0_21_D2_PT_1_IN4,
      I5 => REG_0_21,
      O => REG_0_21_D2_PT_1
    );
  REG_0_21_D2_459 : X_OR2
    port map (
      I0 => REG_0_21_D2_PT_0,
      I1 => REG_0_21_D2_PT_1,
      O => REG_0_21_D2
    );
  REG_0_21_CLKF_460 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_21_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_21_CLKF_IN1,
      O => REG_0_21_CLKF
    );
  REG_0_21_SETF_461 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_21_SETF_IN1,
      I2 => DIN_21_IBUF,
      O => REG_0_21_SETF
    );
  REG_0_21_RSTF_462 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_21_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_21_RSTF_IN2,
      O => REG_0_21_RSTF
    );
  REG_0_21_EXP_tsimrenamed_net_Q_463 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN4,
      I5 => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN5,
      I6 => DIN_22_IBUF,
      O => REG_0_21_EXP_tsimrenamed_net_Q
    );
  REG_0_22_464 : X_BUF
    port map (
      I => REG_0_22_Q,
      O => REG_0_22
    );
  REG_0_22_tsimcreated_xor_Q_465 : X_XOR2
    port map (
      I0 => REG_0_22_D,
      I1 => REG_0_22_Q,
      O => REG_0_22_tsimcreated_xor_Q
    );
  REG_0_22_tsimcreated_set_and_noreset_Q_466 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_22_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_22_SETF,
      O => REG_0_22_tsimcreated_set_and_noreset_Q
    );
  REG_0_22_tsimcreated_prld_Q_467 : X_OR2
    port map (
      I0 => REG_0_22_RSTF,
      I1 => PRLD,
      O => REG_0_22_tsimcreated_prld_Q
    );
  REG_0_22_REG : X_FF
    port map (
      I => REG_0_22_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_22_CLKF,
      SET => REG_0_22_tsimcreated_set_and_noreset_Q,
      RST => REG_0_22_tsimcreated_prld_Q,
      O => REG_0_22_Q
    );
  REG_0_22_D_468 : X_XOR2
    port map (
      I0 => REG_0_22_D1,
      I1 => REG_0_22_D2,
      O => REG_0_22_D
    );
  REG_0_22_D1_469 : X_ZERO
    port map (
      O => REG_0_22_D1
    );
  REG_0_22_D2_PT_0_470 : X_AND2
    port map (
      I0 => REG_0_21_EXP,
      I1 => REG_0_21_EXP,
      O => REG_0_22_D2_PT_0
    );
  REG_0_22_D2_PT_1_471 : X_AND2
    port map (
      I0 => REG_0_23_EXP,
      I1 => REG_0_23_EXP,
      O => REG_0_22_D2_PT_1
    );
  REG_0_22_D2_PT_2_472 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_22_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_22_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_22_D2_PT_2_IN3,
      I4 => REG_0_21,
      I5 => NlwInverterSignal_REG_0_22_D2_PT_2_IN5,
      O => REG_0_22_D2_PT_2
    );
  REG_0_22_D2_PT_3_473 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_22_D2_PT_3_IN0,
      I1 => NlwInverterSignal_REG_0_22_D2_PT_3_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_22_D2_PT_3_IN3,
      I4 => NlwInverterSignal_REG_0_22_D2_PT_3_IN4,
      I5 => REG_0_22,
      O => REG_0_22_D2_PT_3
    );
  REG_0_22_D2_474 : X_OR4
    port map (
      I0 => REG_0_22_D2_PT_0,
      I1 => REG_0_22_D2_PT_1,
      I2 => REG_0_22_D2_PT_2,
      I3 => REG_0_22_D2_PT_3,
      O => REG_0_22_D2
    );
  REG_0_22_CLKF_475 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_22_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_22_CLKF_IN1,
      O => REG_0_22_CLKF
    );
  REG_0_22_SETF_476 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_22_SETF_IN1,
      I2 => DIN_22_IBUF,
      O => REG_0_22_SETF
    );
  REG_0_22_RSTF_477 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_22_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_22_RSTF_IN2,
      O => REG_0_22_RSTF
    );
  REG_0_23_478 : X_BUF
    port map (
      I => REG_0_23_Q,
      O => REG_0_23
    );
  REG_0_23_EXP_479 : X_BUF
    port map (
      I => REG_0_23_EXP_tsimrenamed_net_Q,
      O => REG_0_23_EXP
    );
  REG_0_23_tsimcreated_xor_Q_480 : X_XOR2
    port map (
      I0 => REG_0_23_D,
      I1 => REG_0_23_Q,
      O => REG_0_23_tsimcreated_xor_Q
    );
  REG_0_23_tsimcreated_set_and_noreset_Q_481 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_23_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_23_SETF,
      O => REG_0_23_tsimcreated_set_and_noreset_Q
    );
  REG_0_23_tsimcreated_prld_Q_482 : X_OR2
    port map (
      I0 => REG_0_23_RSTF,
      I1 => PRLD,
      O => REG_0_23_tsimcreated_prld_Q
    );
  REG_0_23_REG : X_FF
    port map (
      I => REG_0_23_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_23_CLKF,
      SET => REG_0_23_tsimcreated_set_and_noreset_Q,
      RST => REG_0_23_tsimcreated_prld_Q,
      O => REG_0_23_Q
    );
  REG_0_23_D_483 : X_XOR2
    port map (
      I0 => REG_0_23_D1,
      I1 => REG_0_23_D2,
      O => REG_0_23_D
    );
  REG_0_23_D1_484 : X_ZERO
    port map (
      O => REG_0_23_D1
    );
  REG_0_23_D2_PT_0_485 : X_AND2
    port map (
      I0 => EXP33_EXP,
      I1 => EXP33_EXP,
      O => REG_0_23_D2_PT_0
    );
  REG_0_23_D2_PT_1_486 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_23_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_23_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_23_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_0_23_D2_PT_1_IN4,
      I5 => REG_0_23,
      O => REG_0_23_D2_PT_1
    );
  REG_0_23_D2_487 : X_OR2
    port map (
      I0 => REG_0_23_D2_PT_0,
      I1 => REG_0_23_D2_PT_1,
      O => REG_0_23_D2
    );
  REG_0_23_CLKF_488 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_23_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_23_CLKF_IN1,
      O => REG_0_23_CLKF
    );
  REG_0_23_SETF_489 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_23_SETF_IN1,
      I2 => DIN_23_IBUF,
      O => REG_0_23_SETF
    );
  REG_0_23_RSTF_490 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_23_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_23_RSTF_IN2,
      O => REG_0_23_RSTF
    );
  REG_0_23_EXP_tsimrenamed_net_Q_491 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN4,
      I5 => REG_0_22,
      I6 => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN6,
      O => REG_0_23_EXP_tsimrenamed_net_Q
    );
  REG_0_24_492 : X_BUF
    port map (
      I => REG_0_24_Q,
      O => REG_0_24
    );
  REG_0_24_tsimcreated_xor_Q_493 : X_XOR2
    port map (
      I0 => REG_0_24_D,
      I1 => REG_0_24_Q,
      O => REG_0_24_tsimcreated_xor_Q
    );
  REG_0_24_tsimcreated_set_and_noreset_Q_494 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_24_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_24_SETF,
      O => REG_0_24_tsimcreated_set_and_noreset_Q
    );
  REG_0_24_tsimcreated_prld_Q_495 : X_OR2
    port map (
      I0 => REG_0_24_RSTF,
      I1 => PRLD,
      O => REG_0_24_tsimcreated_prld_Q
    );
  REG_0_24_REG : X_FF
    port map (
      I => REG_0_24_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_24_CLKF,
      SET => REG_0_24_tsimcreated_set_and_noreset_Q,
      RST => REG_0_24_tsimcreated_prld_Q,
      O => REG_0_24_Q
    );
  REG_0_24_D_496 : X_XOR2
    port map (
      I0 => REG_0_24_D1,
      I1 => REG_0_24_D2,
      O => REG_0_24_D
    );
  REG_0_24_D1_497 : X_ZERO
    port map (
      O => REG_0_24_D1
    );
  REG_0_24_D2_PT_0_498 : X_AND2
    port map (
      I0 => EXP36_EXP,
      I1 => EXP36_EXP,
      O => REG_0_24_D2_PT_0
    );
  REG_0_24_D2_PT_1_499 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_24_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_24_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_24_D2_PT_1_IN3,
      I4 => REG_0_23,
      I5 => NlwInverterSignal_REG_0_24_D2_PT_1_IN5,
      O => REG_0_24_D2_PT_1
    );
  REG_0_24_D2_PT_2_500 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_24_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_24_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_24_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_24_D2_PT_2_IN4,
      I5 => REG_0_24,
      O => REG_0_24_D2_PT_2
    );
  REG_0_24_D2_501 : X_OR3
    port map (
      I0 => REG_0_24_D2_PT_0,
      I1 => REG_0_24_D2_PT_1,
      I2 => REG_0_24_D2_PT_2,
      O => REG_0_24_D2
    );
  REG_0_24_CLKF_502 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_24_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_24_CLKF_IN1,
      O => REG_0_24_CLKF
    );
  REG_0_24_SETF_503 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_24_SETF_IN1,
      I2 => DIN_24_IBUF,
      O => REG_0_24_SETF
    );
  REG_0_24_RSTF_504 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_24_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_24_RSTF_IN2,
      O => REG_0_24_RSTF
    );
  REG_0_25_505 : X_BUF
    port map (
      I => REG_0_25_Q,
      O => REG_0_25
    );
  REG_0_25_tsimcreated_xor_Q_506 : X_XOR2
    port map (
      I0 => REG_0_25_D,
      I1 => REG_0_25_Q,
      O => REG_0_25_tsimcreated_xor_Q
    );
  REG_0_25_tsimcreated_set_and_noreset_Q_507 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_25_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_25_SETF,
      O => REG_0_25_tsimcreated_set_and_noreset_Q
    );
  REG_0_25_tsimcreated_prld_Q_508 : X_OR2
    port map (
      I0 => REG_0_25_RSTF,
      I1 => PRLD,
      O => REG_0_25_tsimcreated_prld_Q
    );
  REG_0_25_REG : X_FF
    port map (
      I => REG_0_25_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_25_CLKF,
      SET => REG_0_25_tsimcreated_set_and_noreset_Q,
      RST => REG_0_25_tsimcreated_prld_Q,
      O => REG_0_25_Q
    );
  REG_0_25_D_509 : X_XOR2
    port map (
      I0 => REG_0_25_D1,
      I1 => REG_0_25_D2,
      O => REG_0_25_D
    );
  REG_0_25_D1_510 : X_ZERO
    port map (
      O => REG_0_25_D1
    );
  REG_0_25_D2_PT_0_511 : X_AND2
    port map (
      I0 => state_1_EXP,
      I1 => state_1_EXP,
      O => REG_0_25_D2_PT_0
    );
  REG_0_25_D2_PT_1_512 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_25_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_25_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_25_D2_PT_1_IN3,
      I4 => REG_0_24,
      I5 => NlwInverterSignal_REG_0_25_D2_PT_1_IN5,
      O => REG_0_25_D2_PT_1
    );
  REG_0_25_D2_PT_2_513 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_25_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_25_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_25_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_25_D2_PT_2_IN4,
      I5 => REG_0_25,
      O => REG_0_25_D2_PT_2
    );
  REG_0_25_D2_514 : X_OR3
    port map (
      I0 => REG_0_25_D2_PT_0,
      I1 => REG_0_25_D2_PT_1,
      I2 => REG_0_25_D2_PT_2,
      O => REG_0_25_D2
    );
  REG_0_25_CLKF_515 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_25_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_25_CLKF_IN1,
      O => REG_0_25_CLKF
    );
  REG_0_25_SETF_516 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_25_SETF_IN1,
      I2 => DIN_25_IBUF,
      O => REG_0_25_SETF
    );
  REG_0_25_RSTF_517 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_25_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_25_RSTF_IN2,
      O => REG_0_25_RSTF
    );
  REG_0_26_518 : X_BUF
    port map (
      I => REG_0_26_Q,
      O => REG_0_26
    );
  REG_0_26_tsimcreated_xor_Q_519 : X_XOR2
    port map (
      I0 => REG_0_26_D,
      I1 => REG_0_26_Q,
      O => REG_0_26_tsimcreated_xor_Q
    );
  REG_0_26_tsimcreated_set_and_noreset_Q_520 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_26_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_26_SETF,
      O => REG_0_26_tsimcreated_set_and_noreset_Q
    );
  REG_0_26_tsimcreated_prld_Q_521 : X_OR2
    port map (
      I0 => REG_0_26_RSTF,
      I1 => PRLD,
      O => REG_0_26_tsimcreated_prld_Q
    );
  REG_0_26_REG : X_FF
    port map (
      I => REG_0_26_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_26_CLKF,
      SET => REG_0_26_tsimcreated_set_and_noreset_Q,
      RST => REG_0_26_tsimcreated_prld_Q,
      O => REG_0_26_Q
    );
  REG_0_26_D_522 : X_XOR2
    port map (
      I0 => REG_0_26_D1,
      I1 => REG_0_26_D2,
      O => REG_0_26_D
    );
  REG_0_26_D1_523 : X_ZERO
    port map (
      O => REG_0_26_D1
    );
  REG_0_26_D2_PT_0_524 : X_AND2
    port map (
      I0 => EXP35_EXP,
      I1 => EXP35_EXP,
      O => REG_0_26_D2_PT_0
    );
  REG_0_26_D2_PT_1_525 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_26_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_26_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_26_D2_PT_1_IN3,
      I4 => REG_0_25,
      I5 => NlwInverterSignal_REG_0_26_D2_PT_1_IN5,
      O => REG_0_26_D2_PT_1
    );
  REG_0_26_D2_PT_2_526 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_26_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_26_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_26_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_26_D2_PT_2_IN4,
      I5 => REG_0_26,
      O => REG_0_26_D2_PT_2
    );
  REG_0_26_D2_527 : X_OR3
    port map (
      I0 => REG_0_26_D2_PT_0,
      I1 => REG_0_26_D2_PT_1,
      I2 => REG_0_26_D2_PT_2,
      O => REG_0_26_D2
    );
  REG_0_26_CLKF_528 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_26_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_26_CLKF_IN1,
      O => REG_0_26_CLKF
    );
  REG_0_26_SETF_529 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_26_SETF_IN1,
      I2 => DIN_26_IBUF,
      O => REG_0_26_SETF
    );
  REG_0_26_RSTF_530 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_26_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_26_RSTF_IN2,
      O => REG_0_26_RSTF
    );
  REG_0_27_531 : X_BUF
    port map (
      I => REG_0_27_Q,
      O => REG_0_27
    );
  REG_0_27_EXP_532 : X_BUF
    port map (
      I => REG_0_27_EXP_tsimrenamed_net_Q,
      O => REG_0_27_EXP
    );
  REG_0_27_tsimcreated_xor_Q_533 : X_XOR2
    port map (
      I0 => REG_0_27_D,
      I1 => REG_0_27_Q,
      O => REG_0_27_tsimcreated_xor_Q
    );
  REG_0_27_tsimcreated_set_and_noreset_Q_534 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_27_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_27_SETF,
      O => REG_0_27_tsimcreated_set_and_noreset_Q
    );
  REG_0_27_tsimcreated_prld_Q_535 : X_OR2
    port map (
      I0 => REG_0_27_RSTF,
      I1 => PRLD,
      O => REG_0_27_tsimcreated_prld_Q
    );
  REG_0_27_REG : X_FF
    port map (
      I => REG_0_27_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_27_CLKF,
      SET => REG_0_27_tsimcreated_set_and_noreset_Q,
      RST => REG_0_27_tsimcreated_prld_Q,
      O => REG_0_27_Q
    );
  REG_0_27_D_536 : X_XOR2
    port map (
      I0 => REG_0_27_D1,
      I1 => REG_0_27_D2,
      O => REG_0_27_D
    );
  REG_0_27_D1_537 : X_ZERO
    port map (
      O => REG_0_27_D1
    );
  REG_0_27_D2_PT_0_538 : X_AND2
    port map (
      I0 => EXP39_EXP,
      I1 => EXP39_EXP,
      O => REG_0_27_D2_PT_0
    );
  REG_0_27_D2_PT_1_539 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_27_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_27_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_27_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_0_27_D2_PT_1_IN4,
      I5 => REG_0_27,
      O => REG_0_27_D2_PT_1
    );
  REG_0_27_D2_540 : X_OR2
    port map (
      I0 => REG_0_27_D2_PT_0,
      I1 => REG_0_27_D2_PT_1,
      O => REG_0_27_D2
    );
  REG_0_27_CLKF_541 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_27_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_27_CLKF_IN1,
      O => REG_0_27_CLKF
    );
  REG_0_27_SETF_542 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_27_SETF_IN1,
      I2 => DIN_27_IBUF,
      O => REG_0_27_SETF
    );
  REG_0_27_RSTF_543 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_27_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_27_RSTF_IN2,
      O => REG_0_27_RSTF
    );
  REG_0_27_EXP_tsimrenamed_net_Q_544 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_23_IBUF,
      I6 => NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN6,
      O => REG_0_27_EXP_tsimrenamed_net_Q
    );
  REG_0_28_545 : X_BUF
    port map (
      I => REG_0_28_Q,
      O => REG_0_28
    );
  REG_0_28_tsimcreated_xor_Q_546 : X_XOR2
    port map (
      I0 => REG_0_28_D,
      I1 => REG_0_28_Q,
      O => REG_0_28_tsimcreated_xor_Q
    );
  REG_0_28_tsimcreated_set_and_noreset_Q_547 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_28_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_28_SETF,
      O => REG_0_28_tsimcreated_set_and_noreset_Q
    );
  REG_0_28_tsimcreated_prld_Q_548 : X_OR2
    port map (
      I0 => REG_0_28_RSTF,
      I1 => PRLD,
      O => REG_0_28_tsimcreated_prld_Q
    );
  REG_0_28_REG : X_FF
    port map (
      I => REG_0_28_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_28_CLKF,
      SET => REG_0_28_tsimcreated_set_and_noreset_Q,
      RST => REG_0_28_tsimcreated_prld_Q,
      O => REG_0_28_Q
    );
  REG_0_28_D_549 : X_XOR2
    port map (
      I0 => REG_0_28_D1,
      I1 => REG_0_28_D2,
      O => REG_0_28_D
    );
  REG_0_28_D1_550 : X_ZERO
    port map (
      O => REG_0_28_D1
    );
  REG_0_28_D2_PT_0_551 : X_AND2
    port map (
      I0 => EXP26_EXP,
      I1 => EXP26_EXP,
      O => REG_0_28_D2_PT_0
    );
  REG_0_28_D2_PT_1_552 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_28_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_28_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_28_D2_PT_1_IN3,
      I4 => REG_0_27,
      I5 => NlwInverterSignal_REG_0_28_D2_PT_1_IN5,
      O => REG_0_28_D2_PT_1
    );
  REG_0_28_D2_PT_2_553 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_28_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_28_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_28_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_28_D2_PT_2_IN4,
      I5 => REG_0_28,
      O => REG_0_28_D2_PT_2
    );
  REG_0_28_D2_554 : X_OR3
    port map (
      I0 => REG_0_28_D2_PT_0,
      I1 => REG_0_28_D2_PT_1,
      I2 => REG_0_28_D2_PT_2,
      O => REG_0_28_D2
    );
  REG_0_28_CLKF_555 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_28_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_28_CLKF_IN1,
      O => REG_0_28_CLKF
    );
  REG_0_28_SETF_556 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_28_SETF_IN1,
      I2 => DIN_28_IBUF,
      O => REG_0_28_SETF
    );
  REG_0_28_RSTF_557 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_28_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_28_RSTF_IN2,
      O => REG_0_28_RSTF
    );
  REG_0_29_558 : X_BUF
    port map (
      I => REG_0_29_Q,
      O => REG_0_29
    );
  REG_0_29_tsimcreated_xor_Q_559 : X_XOR2
    port map (
      I0 => REG_0_29_D,
      I1 => REG_0_29_Q,
      O => REG_0_29_tsimcreated_xor_Q
    );
  REG_0_29_tsimcreated_set_and_noreset_Q_560 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_29_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_29_SETF,
      O => REG_0_29_tsimcreated_set_and_noreset_Q
    );
  REG_0_29_tsimcreated_prld_Q_561 : X_OR2
    port map (
      I0 => REG_0_29_RSTF,
      I1 => PRLD,
      O => REG_0_29_tsimcreated_prld_Q
    );
  REG_0_29_REG : X_FF
    port map (
      I => REG_0_29_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_29_CLKF,
      SET => REG_0_29_tsimcreated_set_and_noreset_Q,
      RST => REG_0_29_tsimcreated_prld_Q,
      O => REG_0_29_Q
    );
  REG_0_29_D_562 : X_XOR2
    port map (
      I0 => REG_0_29_D1,
      I1 => REG_0_29_D2,
      O => REG_0_29_D
    );
  REG_0_29_D1_563 : X_ZERO
    port map (
      O => REG_0_29_D1
    );
  REG_0_29_D2_PT_0_564 : X_AND2
    port map (
      I0 => REG_0_30_EXP,
      I1 => REG_0_30_EXP,
      O => REG_0_29_D2_PT_0
    );
  REG_0_29_D2_PT_1_565 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_29_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_29_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_29_D2_PT_1_IN3,
      I4 => REG_0_28,
      I5 => NlwInverterSignal_REG_0_29_D2_PT_1_IN5,
      O => REG_0_29_D2_PT_1
    );
  REG_0_29_D2_PT_2_566 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_29_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_29_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_29_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_29_D2_PT_2_IN4,
      I5 => REG_0_29,
      O => REG_0_29_D2_PT_2
    );
  REG_0_29_D2_567 : X_OR3
    port map (
      I0 => REG_0_29_D2_PT_0,
      I1 => REG_0_29_D2_PT_1,
      I2 => REG_0_29_D2_PT_2,
      O => REG_0_29_D2
    );
  REG_0_29_CLKF_568 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_29_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_29_CLKF_IN1,
      O => REG_0_29_CLKF
    );
  REG_0_29_SETF_569 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_29_SETF_IN1,
      I2 => DIN_29_IBUF,
      O => REG_0_29_SETF
    );
  REG_0_29_RSTF_570 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_29_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_29_RSTF_IN2,
      O => REG_0_29_RSTF
    );
  REG_0_3_571 : X_BUF
    port map (
      I => REG_0_3_Q,
      O => REG_0_3
    );
  REG_0_3_EXP_572 : X_BUF
    port map (
      I => REG_0_3_EXP_tsimrenamed_net_Q,
      O => REG_0_3_EXP
    );
  REG_0_3_tsimcreated_xor_Q_573 : X_XOR2
    port map (
      I0 => REG_0_3_D,
      I1 => REG_0_3_Q,
      O => REG_0_3_tsimcreated_xor_Q
    );
  REG_0_3_tsimcreated_set_and_noreset_Q_574 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_3_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_3_SETF,
      O => REG_0_3_tsimcreated_set_and_noreset_Q
    );
  REG_0_3_tsimcreated_prld_Q_575 : X_OR2
    port map (
      I0 => REG_0_3_RSTF,
      I1 => PRLD,
      O => REG_0_3_tsimcreated_prld_Q
    );
  REG_0_3_REG : X_FF
    port map (
      I => REG_0_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_3_CLKF,
      SET => REG_0_3_tsimcreated_set_and_noreset_Q,
      RST => REG_0_3_tsimcreated_prld_Q,
      O => REG_0_3_Q
    );
  REG_0_3_D_576 : X_XOR2
    port map (
      I0 => REG_0_3_D1,
      I1 => REG_0_3_D2,
      O => REG_0_3_D
    );
  REG_0_3_D1_577 : X_ZERO
    port map (
      O => REG_0_3_D1
    );
  REG_0_3_D2_578 : X_AND2
    port map (
      I0 => EXP23_EXP,
      I1 => EXP23_EXP,
      O => REG_0_3_D2
    );
  REG_0_3_CLKF_579 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_3_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_3_CLKF_IN1,
      O => REG_0_3_CLKF
    );
  REG_0_3_SETF_580 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_3_SETF_IN1,
      I2 => DIN_3_IBUF,
      O => REG_0_3_SETF
    );
  REG_0_3_RSTF_581 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_3_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_3_RSTF_IN2,
      O => REG_0_3_RSTF
    );
  REG_0_3_EXP_PT_0_582 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_3_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_3_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_3_EXP_PT_0_IN4,
      I5 => DIN_2_IBUF,
      I6 => NlwInverterSignal_REG_0_3_EXP_PT_0_IN6,
      O => REG_0_3_EXP_PT_0
    );
  REG_0_3_EXP_PT_1_583 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_3_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_3_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_3_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_REG_0_3_EXP_PT_1_IN5,
      I6 => REG_0_2,
      O => REG_0_3_EXP_PT_1
    );
  REG_0_3_EXP_tsimrenamed_net_Q_584 : X_OR2
    port map (
      I0 => REG_0_3_EXP_PT_0,
      I1 => REG_0_3_EXP_PT_1,
      O => REG_0_3_EXP_tsimrenamed_net_Q
    );
  REG_0_30_585 : X_BUF
    port map (
      I => REG_0_30_Q,
      O => REG_0_30
    );
  REG_0_30_EXP_586 : X_BUF
    port map (
      I => REG_0_30_EXP_tsimrenamed_net_Q,
      O => REG_0_30_EXP
    );
  REG_0_30_tsimcreated_xor_Q_587 : X_XOR2
    port map (
      I0 => REG_0_30_D,
      I1 => REG_0_30_Q,
      O => REG_0_30_tsimcreated_xor_Q
    );
  REG_0_30_tsimcreated_set_and_noreset_Q_588 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_30_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_30_SETF,
      O => REG_0_30_tsimcreated_set_and_noreset_Q
    );
  REG_0_30_tsimcreated_prld_Q_589 : X_OR2
    port map (
      I0 => REG_0_30_RSTF,
      I1 => PRLD,
      O => REG_0_30_tsimcreated_prld_Q
    );
  REG_0_30_REG : X_FF
    port map (
      I => REG_0_30_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_30_CLKF,
      SET => REG_0_30_tsimcreated_set_and_noreset_Q,
      RST => REG_0_30_tsimcreated_prld_Q,
      O => REG_0_30_Q
    );
  REG_0_30_D_590 : X_XOR2
    port map (
      I0 => REG_0_30_D1,
      I1 => REG_0_30_D2,
      O => REG_0_30_D
    );
  REG_0_30_D1_591 : X_ZERO
    port map (
      O => REG_0_30_D1
    );
  REG_0_30_D2_592 : X_AND2
    port map (
      I0 => EXP25_EXP,
      I1 => EXP25_EXP,
      O => REG_0_30_D2
    );
  REG_0_30_CLKF_593 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_30_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_30_CLKF_IN1,
      O => REG_0_30_CLKF
    );
  REG_0_30_SETF_594 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_30_SETF_IN1,
      I2 => DIN_30_IBUF,
      O => REG_0_30_SETF
    );
  REG_0_30_RSTF_595 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_30_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_30_RSTF_IN2,
      O => REG_0_30_RSTF
    );
  REG_0_30_EXP_PT_0_596 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_30_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_30_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_30_EXP_PT_0_IN4,
      I5 => DIN_29_IBUF,
      I6 => NlwInverterSignal_REG_0_30_EXP_PT_0_IN6,
      O => REG_0_30_EXP_PT_0
    );
  REG_0_30_EXP_PT_1_597 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_30_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_30_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_30_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_REG_0_30_EXP_PT_1_IN5,
      I6 => REG_0_29,
      O => REG_0_30_EXP_PT_1
    );
  REG_0_30_EXP_tsimrenamed_net_Q_598 : X_OR2
    port map (
      I0 => REG_0_30_EXP_PT_0,
      I1 => REG_0_30_EXP_PT_1,
      O => REG_0_30_EXP_tsimrenamed_net_Q
    );
  REG_0_31_599 : X_BUF
    port map (
      I => REG_0_31_Q,
      O => REG_0_31
    );
  REG_0_31_tsimcreated_xor_Q_600 : X_XOR2
    port map (
      I0 => REG_0_31_D,
      I1 => REG_0_31_Q,
      O => REG_0_31_tsimcreated_xor_Q
    );
  REG_0_31_tsimcreated_set_and_noreset_Q_601 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_31_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_31_SETF,
      O => REG_0_31_tsimcreated_set_and_noreset_Q
    );
  REG_0_31_tsimcreated_prld_Q_602 : X_OR2
    port map (
      I0 => REG_0_31_RSTF,
      I1 => PRLD,
      O => REG_0_31_tsimcreated_prld_Q
    );
  REG_0_31_REG : X_FF
    port map (
      I => REG_0_31_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_31_CLKF,
      SET => REG_0_31_tsimcreated_set_and_noreset_Q,
      RST => REG_0_31_tsimcreated_prld_Q,
      O => REG_0_31_Q
    );
  REG_0_31_D_603 : X_XOR2
    port map (
      I0 => REG_0_31_D1,
      I1 => REG_0_31_D2,
      O => REG_0_31_D
    );
  REG_0_31_D1_604 : X_ZERO
    port map (
      O => REG_0_31_D1
    );
  REG_0_31_D2_PT_0_605 : X_AND2
    port map (
      I0 => EXP24_EXP,
      I1 => EXP24_EXP,
      O => REG_0_31_D2_PT_0
    );
  REG_0_31_D2_PT_1_606 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_31_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_31_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_31_D2_PT_1_IN3,
      I4 => REG_0_30,
      I5 => NlwInverterSignal_REG_0_31_D2_PT_1_IN5,
      O => REG_0_31_D2_PT_1
    );
  REG_0_31_D2_PT_2_607 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_31_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_31_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_31_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_31_D2_PT_2_IN4,
      I5 => REG_0_31,
      O => REG_0_31_D2_PT_2
    );
  REG_0_31_D2_608 : X_OR3
    port map (
      I0 => REG_0_31_D2_PT_0,
      I1 => REG_0_31_D2_PT_1,
      I2 => REG_0_31_D2_PT_2,
      O => REG_0_31_D2
    );
  REG_0_31_CLKF_609 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_31_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_31_CLKF_IN1,
      O => REG_0_31_CLKF
    );
  REG_0_31_SETF_610 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_31_SETF_IN1,
      I2 => DIN_31_IBUF,
      O => REG_0_31_SETF
    );
  REG_0_31_RSTF_611 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_31_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_31_RSTF_IN2,
      O => REG_0_31_RSTF
    );
  REG_0_4_612 : X_BUF
    port map (
      I => REG_0_4_Q,
      O => REG_0_4
    );
  REG_0_4_tsimcreated_xor_Q_613 : X_XOR2
    port map (
      I0 => REG_0_4_D,
      I1 => REG_0_4_Q,
      O => REG_0_4_tsimcreated_xor_Q
    );
  REG_0_4_tsimcreated_set_and_noreset_Q_614 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_4_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_4_SETF,
      O => REG_0_4_tsimcreated_set_and_noreset_Q
    );
  REG_0_4_tsimcreated_prld_Q_615 : X_OR2
    port map (
      I0 => REG_0_4_RSTF,
      I1 => PRLD,
      O => REG_0_4_tsimcreated_prld_Q
    );
  REG_0_4_REG : X_FF
    port map (
      I => REG_0_4_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_4_CLKF,
      SET => REG_0_4_tsimcreated_set_and_noreset_Q,
      RST => REG_0_4_tsimcreated_prld_Q,
      O => REG_0_4_Q
    );
  REG_0_4_D_616 : X_XOR2
    port map (
      I0 => REG_0_4_D1,
      I1 => REG_0_4_D2,
      O => REG_0_4_D
    );
  REG_0_4_D1_617 : X_ZERO
    port map (
      O => REG_0_4_D1
    );
  REG_0_4_D2_PT_0_618 : X_AND2
    port map (
      I0 => REG_0_0_EXP,
      I1 => REG_0_0_EXP,
      O => REG_0_4_D2_PT_0
    );
  REG_0_4_D2_PT_1_619 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_4_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_4_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_4_D2_PT_1_IN3,
      I4 => REG_0_4,
      I5 => NlwInverterSignal_REG_0_4_D2_PT_1_IN5,
      O => REG_0_4_D2_PT_1
    );
  REG_0_4_D2_PT_2_620 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_4_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_4_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_4_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_4_D2_PT_2_IN4,
      I5 => REG_0_3,
      O => REG_0_4_D2_PT_2
    );
  REG_0_4_D2_621 : X_OR3
    port map (
      I0 => REG_0_4_D2_PT_0,
      I1 => REG_0_4_D2_PT_1,
      I2 => REG_0_4_D2_PT_2,
      O => REG_0_4_D2
    );
  REG_0_4_CLKF_622 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_4_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_4_CLKF_IN1,
      O => REG_0_4_CLKF
    );
  REG_0_4_SETF_623 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_4_SETF_IN1,
      I2 => DIN_4_IBUF,
      O => REG_0_4_SETF
    );
  REG_0_4_RSTF_624 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_4_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_4_RSTF_IN2,
      O => REG_0_4_RSTF
    );
  REG_0_5_625 : X_BUF
    port map (
      I => REG_0_5_Q,
      O => REG_0_5
    );
  REG_0_5_tsimcreated_xor_Q_626 : X_XOR2
    port map (
      I0 => REG_0_5_D,
      I1 => REG_0_5_Q,
      O => REG_0_5_tsimcreated_xor_Q
    );
  REG_0_5_tsimcreated_set_and_noreset_Q_627 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_5_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_5_SETF,
      O => REG_0_5_tsimcreated_set_and_noreset_Q
    );
  REG_0_5_tsimcreated_prld_Q_628 : X_OR2
    port map (
      I0 => REG_0_5_RSTF,
      I1 => PRLD,
      O => REG_0_5_tsimcreated_prld_Q
    );
  REG_0_5_REG : X_FF
    port map (
      I => REG_0_5_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_5_CLKF,
      SET => REG_0_5_tsimcreated_set_and_noreset_Q,
      RST => REG_0_5_tsimcreated_prld_Q,
      O => REG_0_5_Q
    );
  REG_0_5_D_629 : X_XOR2
    port map (
      I0 => REG_0_5_D1,
      I1 => REG_0_5_D2,
      O => REG_0_5_D
    );
  REG_0_5_D1_630 : X_ZERO
    port map (
      O => REG_0_5_D1
    );
  REG_0_5_D2_PT_0_631 : X_AND2
    port map (
      I0 => EXP19_EXP,
      I1 => EXP19_EXP,
      O => REG_0_5_D2_PT_0
    );
  REG_0_5_D2_PT_1_632 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_5_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_5_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_5_D2_PT_1_IN3,
      I4 => REG_0_4,
      I5 => NlwInverterSignal_REG_0_5_D2_PT_1_IN5,
      O => REG_0_5_D2_PT_1
    );
  REG_0_5_D2_PT_2_633 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_5_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_5_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_5_D2_PT_2_IN3,
      I4 => NlwInverterSignal_REG_0_5_D2_PT_2_IN4,
      I5 => REG_0_5,
      O => REG_0_5_D2_PT_2
    );
  REG_0_5_D2_634 : X_OR3
    port map (
      I0 => REG_0_5_D2_PT_0,
      I1 => REG_0_5_D2_PT_1,
      I2 => REG_0_5_D2_PT_2,
      O => REG_0_5_D2
    );
  REG_0_5_CLKF_635 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_5_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_5_CLKF_IN1,
      O => REG_0_5_CLKF
    );
  REG_0_5_SETF_636 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_5_SETF_IN1,
      I2 => DIN_5_IBUF,
      O => REG_0_5_SETF
    );
  REG_0_5_RSTF_637 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_5_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_5_RSTF_IN2,
      O => REG_0_5_RSTF
    );
  REG_0_6_638 : X_BUF
    port map (
      I => REG_0_6_Q,
      O => REG_0_6
    );
  REG_0_6_tsimcreated_xor_Q_639 : X_XOR2
    port map (
      I0 => REG_0_6_D,
      I1 => REG_0_6_Q,
      O => REG_0_6_tsimcreated_xor_Q
    );
  REG_0_6_tsimcreated_set_and_noreset_Q_640 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_6_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_6_SETF,
      O => REG_0_6_tsimcreated_set_and_noreset_Q
    );
  REG_0_6_tsimcreated_prld_Q_641 : X_OR2
    port map (
      I0 => REG_0_6_RSTF,
      I1 => PRLD,
      O => REG_0_6_tsimcreated_prld_Q
    );
  REG_0_6_REG : X_FF
    port map (
      I => REG_0_6_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_6_CLKF,
      SET => REG_0_6_tsimcreated_set_and_noreset_Q,
      RST => REG_0_6_tsimcreated_prld_Q,
      O => REG_0_6_Q
    );
  REG_0_6_D_642 : X_XOR2
    port map (
      I0 => REG_0_6_D1,
      I1 => REG_0_6_D2,
      O => REG_0_6_D
    );
  REG_0_6_D1_643 : X_ZERO
    port map (
      O => REG_0_6_D1
    );
  REG_0_6_D2_PT_0_644 : X_AND2
    port map (
      I0 => EXP20_EXP,
      I1 => EXP20_EXP,
      O => REG_0_6_D2_PT_0
    );
  REG_0_6_D2_PT_1_645 : X_AND2
    port map (
      I0 => EXP21_EXP,
      I1 => EXP21_EXP,
      O => REG_0_6_D2_PT_1
    );
  REG_0_6_D2_PT_2_646 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_6_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_6_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_6_D2_PT_2_IN3,
      I4 => REG_0_5,
      I5 => NlwInverterSignal_REG_0_6_D2_PT_2_IN5,
      O => REG_0_6_D2_PT_2
    );
  REG_0_6_D2_PT_3_647 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_6_D2_PT_3_IN0,
      I1 => NlwInverterSignal_REG_0_6_D2_PT_3_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_6_D2_PT_3_IN3,
      I4 => NlwInverterSignal_REG_0_6_D2_PT_3_IN4,
      I5 => REG_0_6,
      O => REG_0_6_D2_PT_3
    );
  REG_0_6_D2_648 : X_OR4
    port map (
      I0 => REG_0_6_D2_PT_0,
      I1 => REG_0_6_D2_PT_1,
      I2 => REG_0_6_D2_PT_2,
      I3 => REG_0_6_D2_PT_3,
      O => REG_0_6_D2
    );
  REG_0_6_CLKF_649 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_6_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_6_CLKF_IN1,
      O => REG_0_6_CLKF
    );
  REG_0_6_SETF_650 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_6_SETF_IN1,
      I2 => DIN_6_IBUF,
      O => REG_0_6_SETF
    );
  REG_0_6_RSTF_651 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_6_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_6_RSTF_IN2,
      O => REG_0_6_RSTF
    );
  REG_0_7_652 : X_BUF
    port map (
      I => REG_0_7_Q,
      O => REG_0_7
    );
  REG_0_7_EXP_653 : X_BUF
    port map (
      I => REG_0_7_EXP_tsimrenamed_net_Q,
      O => REG_0_7_EXP
    );
  REG_0_7_tsimcreated_xor_Q_654 : X_XOR2
    port map (
      I0 => REG_0_7_D,
      I1 => REG_0_7_Q,
      O => REG_0_7_tsimcreated_xor_Q
    );
  REG_0_7_tsimcreated_set_and_noreset_Q_655 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_7_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_7_SETF,
      O => REG_0_7_tsimcreated_set_and_noreset_Q
    );
  REG_0_7_tsimcreated_prld_Q_656 : X_OR2
    port map (
      I0 => REG_0_7_RSTF,
      I1 => PRLD,
      O => REG_0_7_tsimcreated_prld_Q
    );
  REG_0_7_REG : X_FF
    port map (
      I => REG_0_7_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_7_CLKF,
      SET => REG_0_7_tsimcreated_set_and_noreset_Q,
      RST => REG_0_7_tsimcreated_prld_Q,
      O => REG_0_7_Q
    );
  REG_0_7_D_657 : X_XOR2
    port map (
      I0 => REG_0_7_D1,
      I1 => REG_0_7_D2,
      O => REG_0_7_D
    );
  REG_0_7_D1_658 : X_ZERO
    port map (
      O => REG_0_7_D1
    );
  REG_0_7_D2_PT_0_659 : X_AND2
    port map (
      I0 => EXP46_EXP,
      I1 => EXP46_EXP,
      O => REG_0_7_D2_PT_0
    );
  REG_0_7_D2_PT_1_660 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_7_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_7_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_7_D2_PT_1_IN3,
      I4 => NlwInverterSignal_REG_0_7_D2_PT_1_IN4,
      I5 => REG_0_7,
      O => REG_0_7_D2_PT_1
    );
  REG_0_7_D2_661 : X_OR2
    port map (
      I0 => REG_0_7_D2_PT_0,
      I1 => REG_0_7_D2_PT_1,
      O => REG_0_7_D2
    );
  REG_0_7_CLKF_662 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_7_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_7_CLKF_IN1,
      O => REG_0_7_CLKF
    );
  REG_0_7_SETF_663 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_7_SETF_IN1,
      I2 => DIN_7_IBUF,
      O => REG_0_7_SETF
    );
  REG_0_7_RSTF_664 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_7_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_7_RSTF_IN2,
      O => REG_0_7_RSTF
    );
  REG_0_7_EXP_tsimrenamed_net_Q_665 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN4,
      I5 => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN5,
      I6 => DIN_8_IBUF,
      O => REG_0_7_EXP_tsimrenamed_net_Q
    );
  REG_0_8_666 : X_BUF
    port map (
      I => REG_0_8_Q,
      O => REG_0_8
    );
  REG_0_8_tsimcreated_xor_Q_667 : X_XOR2
    port map (
      I0 => REG_0_8_D,
      I1 => REG_0_8_Q,
      O => REG_0_8_tsimcreated_xor_Q
    );
  REG_0_8_tsimcreated_set_and_noreset_Q_668 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_8_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_8_SETF,
      O => REG_0_8_tsimcreated_set_and_noreset_Q
    );
  REG_0_8_tsimcreated_prld_Q_669 : X_OR2
    port map (
      I0 => REG_0_8_RSTF,
      I1 => PRLD,
      O => REG_0_8_tsimcreated_prld_Q
    );
  REG_0_8_REG : X_FF
    port map (
      I => REG_0_8_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_8_CLKF,
      SET => REG_0_8_tsimcreated_set_and_noreset_Q,
      RST => REG_0_8_tsimcreated_prld_Q,
      O => REG_0_8_Q
    );
  REG_0_8_D_670 : X_XOR2
    port map (
      I0 => REG_0_8_D1,
      I1 => REG_0_8_D2,
      O => REG_0_8_D
    );
  REG_0_8_D1_671 : X_ZERO
    port map (
      O => REG_0_8_D1
    );
  REG_0_8_D2_PT_0_672 : X_AND2
    port map (
      I0 => REG_0_7_EXP,
      I1 => REG_0_7_EXP,
      O => REG_0_8_D2_PT_0
    );
  REG_0_8_D2_PT_1_673 : X_AND2
    port map (
      I0 => REG_0_9_EXP,
      I1 => REG_0_9_EXP,
      O => REG_0_8_D2_PT_1
    );
  REG_0_8_D2_PT_2_674 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_8_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_0_8_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_8_D2_PT_2_IN3,
      I4 => REG_0_7,
      I5 => NlwInverterSignal_REG_0_8_D2_PT_2_IN5,
      O => REG_0_8_D2_PT_2
    );
  REG_0_8_D2_PT_3_675 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_8_D2_PT_3_IN0,
      I1 => NlwInverterSignal_REG_0_8_D2_PT_3_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_8_D2_PT_3_IN3,
      I4 => NlwInverterSignal_REG_0_8_D2_PT_3_IN4,
      I5 => REG_0_8,
      O => REG_0_8_D2_PT_3
    );
  REG_0_8_D2_676 : X_OR4
    port map (
      I0 => REG_0_8_D2_PT_0,
      I1 => REG_0_8_D2_PT_1,
      I2 => REG_0_8_D2_PT_2,
      I3 => REG_0_8_D2_PT_3,
      O => REG_0_8_D2
    );
  REG_0_8_CLKF_677 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_8_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_8_CLKF_IN1,
      O => REG_0_8_CLKF
    );
  REG_0_8_SETF_678 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_8_SETF_IN1,
      I2 => DIN_8_IBUF,
      O => REG_0_8_SETF
    );
  REG_0_8_RSTF_679 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_8_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_8_RSTF_IN2,
      O => REG_0_8_RSTF
    );
  REG_0_9_680 : X_BUF
    port map (
      I => REG_0_9_Q,
      O => REG_0_9
    );
  REG_0_9_EXP_681 : X_BUF
    port map (
      I => REG_0_9_EXP_tsimrenamed_net_Q,
      O => REG_0_9_EXP
    );
  REG_0_9_tsimcreated_xor_Q_682 : X_XOR2
    port map (
      I0 => REG_0_9_D,
      I1 => REG_0_9_Q,
      O => REG_0_9_tsimcreated_xor_Q
    );
  REG_0_9_tsimcreated_set_and_noreset_Q_683 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_9_tsimcreated_set_and_noreset_IN0,
      I1 => REG_0_9_SETF,
      O => REG_0_9_tsimcreated_set_and_noreset_Q
    );
  REG_0_9_tsimcreated_prld_Q_684 : X_OR2
    port map (
      I0 => REG_0_9_RSTF,
      I1 => PRLD,
      O => REG_0_9_tsimcreated_prld_Q
    );
  REG_0_9_REG : X_FF
    port map (
      I => REG_0_9_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_0_9_CLKF,
      SET => REG_0_9_tsimcreated_set_and_noreset_Q,
      RST => REG_0_9_tsimcreated_prld_Q,
      O => REG_0_9_Q
    );
  REG_0_9_D_685 : X_XOR2
    port map (
      I0 => REG_0_9_D1,
      I1 => REG_0_9_D2,
      O => REG_0_9_D
    );
  REG_0_9_D1_686 : X_ZERO
    port map (
      O => REG_0_9_D1
    );
  REG_0_9_D2_PT_0_687 : X_AND2
    port map (
      I0 => EXP45_EXP,
      I1 => EXP45_EXP,
      O => REG_0_9_D2_PT_0
    );
  REG_0_9_D2_PT_1_688 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_0_9_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_0_9_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_REG_0_9_D2_PT_1_IN3,
      I4 => REG_0_9,
      I5 => NlwInverterSignal_REG_0_9_D2_PT_1_IN5,
      O => REG_0_9_D2_PT_1
    );
  REG_0_9_D2_689 : X_OR2
    port map (
      I0 => REG_0_9_D2_PT_0,
      I1 => REG_0_9_D2_PT_1,
      O => REG_0_9_D2
    );
  REG_0_9_CLKF_690 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_0_9_CLKF_IN0,
      I1 => NlwInverterSignal_REG_0_9_CLKF_IN1,
      O => REG_0_9_CLKF
    );
  REG_0_9_SETF_691 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_9_SETF_IN1,
      I2 => DIN_9_IBUF,
      O => REG_0_9_SETF
    );
  REG_0_9_RSTF_692 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_REG_0_9_RSTF_IN1,
      I2 => NlwInverterSignal_REG_0_9_RSTF_IN2,
      O => REG_0_9_RSTF
    );
  REG_0_9_EXP_tsimrenamed_net_Q_693 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN4,
      I5 => REG_0_8,
      I6 => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN6,
      O => REG_0_9_EXP_tsimrenamed_net_Q
    );
  REG_1_0_694 : X_BUF
    port map (
      I => REG_1_0_Q,
      O => REG_1_0
    );
  REG_1_0_EXP_695 : X_BUF
    port map (
      I => REG_1_0_EXP_tsimrenamed_net_Q,
      O => REG_1_0_EXP
    );
  REG_1_0_tsimcreated_xor_Q_696 : X_XOR2
    port map (
      I0 => REG_1_0_D,
      I1 => REG_1_0_Q,
      O => REG_1_0_tsimcreated_xor_Q
    );
  REG_1_0_tsimcreated_set_and_noreset_Q_697 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_0_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_0_SETF,
      O => REG_1_0_tsimcreated_set_and_noreset_Q
    );
  REG_1_0_tsimcreated_prld_Q_698 : X_OR2
    port map (
      I0 => REG_1_0_RSTF,
      I1 => PRLD,
      O => REG_1_0_tsimcreated_prld_Q
    );
  REG_1_0_REG : X_FF
    port map (
      I => REG_1_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_0_CLKF,
      SET => REG_1_0_tsimcreated_set_and_noreset_Q,
      RST => REG_1_0_tsimcreated_prld_Q,
      O => REG_1_0_Q
    );
  REG_1_0_D_699 : X_XOR2
    port map (
      I0 => REG_1_0_D1,
      I1 => REG_1_0_D2,
      O => REG_1_0_D
    );
  REG_1_0_D1_700 : X_ZERO
    port map (
      O => REG_1_0_D1
    );
  REG_1_0_D2_701 : X_AND2
    port map (
      I0 => EXP52_EXP,
      I1 => EXP52_EXP,
      O => REG_1_0_D2
    );
  REG_1_0_CLKF_702 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_0_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_0_CLKF_IN1,
      O => REG_1_0_CLKF
    );
  REG_1_0_SETF_703 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_0_IBUF,
      O => REG_1_0_SETF
    );
  REG_1_0_RSTF_704 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_0_RSTF_IN2,
      O => REG_1_0_RSTF
    );
  REG_1_0_EXP_PT_0_705 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_1_0_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_4_IBUF,
      I6 => NlwInverterSignal_REG_1_0_EXP_PT_0_IN6,
      O => REG_1_0_EXP_PT_0
    );
  REG_1_0_EXP_PT_1_706 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_1_0_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_REG_1_0_EXP_PT_1_IN5,
      I6 => REG_1_4,
      O => REG_1_0_EXP_PT_1
    );
  REG_1_0_EXP_tsimrenamed_net_Q_707 : X_OR2
    port map (
      I0 => REG_1_0_EXP_PT_0,
      I1 => REG_1_0_EXP_PT_1,
      O => REG_1_0_EXP_tsimrenamed_net_Q
    );
  REG_1_1_708 : X_BUF
    port map (
      I => REG_1_1_Q,
      O => REG_1_1
    );
  REG_1_1_tsimcreated_xor_Q_709 : X_XOR2
    port map (
      I0 => REG_1_1_D,
      I1 => REG_1_1_Q,
      O => REG_1_1_tsimcreated_xor_Q
    );
  REG_1_1_tsimcreated_set_and_noreset_Q_710 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_1_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_1_SETF,
      O => REG_1_1_tsimcreated_set_and_noreset_Q
    );
  REG_1_1_tsimcreated_prld_Q_711 : X_OR2
    port map (
      I0 => REG_1_1_RSTF,
      I1 => PRLD,
      O => REG_1_1_tsimcreated_prld_Q
    );
  REG_1_1_REG : X_FF
    port map (
      I => REG_1_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_1_CLKF,
      SET => REG_1_1_tsimcreated_set_and_noreset_Q,
      RST => REG_1_1_tsimcreated_prld_Q,
      O => REG_1_1_Q
    );
  REG_1_1_D_712 : X_XOR2
    port map (
      I0 => REG_1_1_D1,
      I1 => REG_1_1_D2,
      O => REG_1_1_D
    );
  REG_1_1_D1_713 : X_ZERO
    port map (
      O => REG_1_1_D1
    );
  REG_1_1_D2_PT_0_714 : X_AND2
    port map (
      I0 => EXP48_EXP,
      I1 => EXP48_EXP,
      O => REG_1_1_D2_PT_0
    );
  REG_1_1_D2_PT_1_715 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_1_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_1_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_0,
      I5 => NlwInverterSignal_REG_1_1_D2_PT_1_IN5,
      O => REG_1_1_D2_PT_1
    );
  REG_1_1_D2_PT_2_716 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_1_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_1_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_1_D2_PT_2_IN4,
      I5 => REG_1_1,
      O => REG_1_1_D2_PT_2
    );
  REG_1_1_D2_717 : X_OR3
    port map (
      I0 => REG_1_1_D2_PT_0,
      I1 => REG_1_1_D2_PT_1,
      I2 => REG_1_1_D2_PT_2,
      O => REG_1_1_D2
    );
  REG_1_1_CLKF_718 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_1_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_1_CLKF_IN1,
      O => REG_1_1_CLKF
    );
  REG_1_1_SETF_719 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_1_IBUF,
      O => REG_1_1_SETF
    );
  REG_1_1_RSTF_720 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_1_RSTF_IN2,
      O => REG_1_1_RSTF
    );
  REG_1_10_721 : X_BUF
    port map (
      I => REG_1_10_Q,
      O => REG_1_10
    );
  REG_1_10_tsimcreated_xor_Q_722 : X_XOR2
    port map (
      I0 => REG_1_10_D,
      I1 => REG_1_10_Q,
      O => REG_1_10_tsimcreated_xor_Q
    );
  REG_1_10_tsimcreated_set_and_noreset_Q_723 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_10_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_10_SETF,
      O => REG_1_10_tsimcreated_set_and_noreset_Q
    );
  REG_1_10_tsimcreated_prld_Q_724 : X_OR2
    port map (
      I0 => REG_1_10_RSTF,
      I1 => PRLD,
      O => REG_1_10_tsimcreated_prld_Q
    );
  REG_1_10_REG : X_FF
    port map (
      I => REG_1_10_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_10_CLKF,
      SET => REG_1_10_tsimcreated_set_and_noreset_Q,
      RST => REG_1_10_tsimcreated_prld_Q,
      O => REG_1_10_Q
    );
  REG_1_10_D_725 : X_XOR2
    port map (
      I0 => REG_1_10_D1,
      I1 => REG_1_10_D2,
      O => REG_1_10_D
    );
  REG_1_10_D1_726 : X_ZERO
    port map (
      O => REG_1_10_D1
    );
  REG_1_10_D2_PT_0_727 : X_AND2
    port map (
      I0 => EXP43_EXP,
      I1 => EXP43_EXP,
      O => REG_1_10_D2_PT_0
    );
  REG_1_10_D2_PT_1_728 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_10_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_10_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_10,
      I5 => NlwInverterSignal_REG_1_10_D2_PT_1_IN5,
      O => REG_1_10_D2_PT_1
    );
  REG_1_10_D2_PT_2_729 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_10_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_10_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_10_D2_PT_2_IN4,
      I5 => REG_1_9,
      O => REG_1_10_D2_PT_2
    );
  REG_1_10_D2_730 : X_OR3
    port map (
      I0 => REG_1_10_D2_PT_0,
      I1 => REG_1_10_D2_PT_1,
      I2 => REG_1_10_D2_PT_2,
      O => REG_1_10_D2
    );
  REG_1_10_CLKF_731 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_10_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_10_CLKF_IN1,
      O => REG_1_10_CLKF
    );
  REG_1_10_SETF_732 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_10_IBUF,
      O => REG_1_10_SETF
    );
  REG_1_10_RSTF_733 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_10_RSTF_IN2,
      O => REG_1_10_RSTF
    );
  REG_1_11_734 : X_BUF
    port map (
      I => REG_1_11_Q,
      O => REG_1_11
    );
  REG_1_11_EXP_735 : X_BUF
    port map (
      I => REG_1_11_EXP_tsimrenamed_net_Q,
      O => REG_1_11_EXP
    );
  REG_1_11_tsimcreated_xor_Q_736 : X_XOR2
    port map (
      I0 => REG_1_11_D,
      I1 => REG_1_11_Q,
      O => REG_1_11_tsimcreated_xor_Q
    );
  REG_1_11_tsimcreated_set_and_noreset_Q_737 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_11_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_11_SETF,
      O => REG_1_11_tsimcreated_set_and_noreset_Q
    );
  REG_1_11_tsimcreated_prld_Q_738 : X_OR2
    port map (
      I0 => REG_1_11_RSTF,
      I1 => PRLD,
      O => REG_1_11_tsimcreated_prld_Q
    );
  REG_1_11_REG : X_FF
    port map (
      I => REG_1_11_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_11_CLKF,
      SET => REG_1_11_tsimcreated_set_and_noreset_Q,
      RST => REG_1_11_tsimcreated_prld_Q,
      O => REG_1_11_Q
    );
  REG_1_11_D_739 : X_XOR2
    port map (
      I0 => REG_1_11_D1,
      I1 => REG_1_11_D2,
      O => REG_1_11_D
    );
  REG_1_11_D1_740 : X_ZERO
    port map (
      O => REG_1_11_D1
    );
  REG_1_11_D2_PT_0_741 : X_AND2
    port map (
      I0 => EXP56_EXP,
      I1 => EXP56_EXP,
      O => REG_1_11_D2_PT_0
    );
  REG_1_11_D2_PT_1_742 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_11_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_11_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_11_D2_PT_1_IN4,
      I5 => REG_1_11,
      O => REG_1_11_D2_PT_1
    );
  REG_1_11_D2_743 : X_OR2
    port map (
      I0 => REG_1_11_D2_PT_0,
      I1 => REG_1_11_D2_PT_1,
      O => REG_1_11_D2
    );
  REG_1_11_CLKF_744 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_11_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_11_CLKF_IN1,
      O => REG_1_11_CLKF
    );
  REG_1_11_SETF_745 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_11_IBUF,
      O => REG_1_11_SETF
    );
  REG_1_11_RSTF_746 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_11_RSTF_IN2,
      O => REG_1_11_RSTF
    );
  REG_1_11_EXP_tsimrenamed_net_Q_747 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_12_IBUF,
      I6 => NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN6,
      O => REG_1_11_EXP_tsimrenamed_net_Q
    );
  REG_1_12_748 : X_BUF
    port map (
      I => REG_1_12_Q,
      O => REG_1_12
    );
  REG_1_12_tsimcreated_xor_Q_749 : X_XOR2
    port map (
      I0 => REG_1_12_D,
      I1 => REG_1_12_Q,
      O => REG_1_12_tsimcreated_xor_Q
    );
  REG_1_12_tsimcreated_set_and_noreset_Q_750 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_12_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_12_SETF,
      O => REG_1_12_tsimcreated_set_and_noreset_Q
    );
  REG_1_12_tsimcreated_prld_Q_751 : X_OR2
    port map (
      I0 => REG_1_12_RSTF,
      I1 => PRLD,
      O => REG_1_12_tsimcreated_prld_Q
    );
  REG_1_12_REG : X_FF
    port map (
      I => REG_1_12_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_12_CLKF,
      SET => REG_1_12_tsimcreated_set_and_noreset_Q,
      RST => REG_1_12_tsimcreated_prld_Q,
      O => REG_1_12_Q
    );
  REG_1_12_D_752 : X_XOR2
    port map (
      I0 => REG_1_12_D1,
      I1 => REG_1_12_D2,
      O => REG_1_12_D
    );
  REG_1_12_D1_753 : X_ZERO
    port map (
      O => REG_1_12_D1
    );
  REG_1_12_D2_PT_0_754 : X_AND2
    port map (
      I0 => REG_1_11_EXP,
      I1 => REG_1_11_EXP,
      O => REG_1_12_D2_PT_0
    );
  REG_1_12_D2_PT_1_755 : X_AND2
    port map (
      I0 => REG_1_13_EXP,
      I1 => REG_1_13_EXP,
      O => REG_1_12_D2_PT_1
    );
  REG_1_12_D2_PT_2_756 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_12_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_12_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_11,
      I5 => NlwInverterSignal_REG_1_12_D2_PT_2_IN5,
      O => REG_1_12_D2_PT_2
    );
  REG_1_12_D2_PT_3_757 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_12_D2_PT_3_IN0,
      I1 => NlwInverterSignal_REG_1_12_D2_PT_3_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_12_D2_PT_3_IN4,
      I5 => REG_1_12,
      O => REG_1_12_D2_PT_3
    );
  REG_1_12_D2_758 : X_OR4
    port map (
      I0 => REG_1_12_D2_PT_0,
      I1 => REG_1_12_D2_PT_1,
      I2 => REG_1_12_D2_PT_2,
      I3 => REG_1_12_D2_PT_3,
      O => REG_1_12_D2
    );
  REG_1_12_CLKF_759 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_12_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_12_CLKF_IN1,
      O => REG_1_12_CLKF
    );
  REG_1_12_SETF_760 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_12_IBUF,
      O => REG_1_12_SETF
    );
  REG_1_12_RSTF_761 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_12_RSTF_IN2,
      O => REG_1_12_RSTF
    );
  REG_1_13_762 : X_BUF
    port map (
      I => REG_1_13_Q,
      O => REG_1_13
    );
  REG_1_13_EXP_763 : X_BUF
    port map (
      I => REG_1_13_EXP_tsimrenamed_net_Q,
      O => REG_1_13_EXP
    );
  REG_1_13_tsimcreated_xor_Q_764 : X_XOR2
    port map (
      I0 => REG_1_13_D,
      I1 => REG_1_13_Q,
      O => REG_1_13_tsimcreated_xor_Q
    );
  REG_1_13_tsimcreated_set_and_noreset_Q_765 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_13_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_13_SETF,
      O => REG_1_13_tsimcreated_set_and_noreset_Q
    );
  REG_1_13_tsimcreated_prld_Q_766 : X_OR2
    port map (
      I0 => REG_1_13_RSTF,
      I1 => PRLD,
      O => REG_1_13_tsimcreated_prld_Q
    );
  REG_1_13_REG : X_FF
    port map (
      I => REG_1_13_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_13_CLKF,
      SET => REG_1_13_tsimcreated_set_and_noreset_Q,
      RST => REG_1_13_tsimcreated_prld_Q,
      O => REG_1_13_Q
    );
  REG_1_13_D_767 : X_XOR2
    port map (
      I0 => REG_1_13_D1,
      I1 => REG_1_13_D2,
      O => REG_1_13_D
    );
  REG_1_13_D1_768 : X_ZERO
    port map (
      O => REG_1_13_D1
    );
  REG_1_13_D2_PT_0_769 : X_AND2
    port map (
      I0 => EXP55_EXP,
      I1 => EXP55_EXP,
      O => REG_1_13_D2_PT_0
    );
  REG_1_13_D2_PT_1_770 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_13_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_13_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_13_D2_PT_1_IN4,
      I5 => REG_1_13,
      O => REG_1_13_D2_PT_1
    );
  REG_1_13_D2_771 : X_OR2
    port map (
      I0 => REG_1_13_D2_PT_0,
      I1 => REG_1_13_D2_PT_1,
      O => REG_1_13_D2
    );
  REG_1_13_CLKF_772 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_13_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_13_CLKF_IN1,
      O => REG_1_13_CLKF
    );
  REG_1_13_SETF_773 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_13_IBUF,
      O => REG_1_13_SETF
    );
  REG_1_13_RSTF_774 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_13_RSTF_IN2,
      O => REG_1_13_RSTF
    );
  REG_1_13_EXP_tsimrenamed_net_Q_775 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN5,
      I6 => REG_1_12,
      O => REG_1_13_EXP_tsimrenamed_net_Q
    );
  REG_1_14_776 : X_BUF
    port map (
      I => REG_1_14_Q,
      O => REG_1_14
    );
  REG_1_14_tsimcreated_xor_Q_777 : X_XOR2
    port map (
      I0 => REG_1_14_D,
      I1 => REG_1_14_Q,
      O => REG_1_14_tsimcreated_xor_Q
    );
  REG_1_14_tsimcreated_set_and_noreset_Q_778 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_14_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_14_SETF,
      O => REG_1_14_tsimcreated_set_and_noreset_Q
    );
  REG_1_14_tsimcreated_prld_Q_779 : X_OR2
    port map (
      I0 => REG_1_14_RSTF,
      I1 => PRLD,
      O => REG_1_14_tsimcreated_prld_Q
    );
  REG_1_14_REG : X_FF
    port map (
      I => REG_1_14_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_14_CLKF,
      SET => REG_1_14_tsimcreated_set_and_noreset_Q,
      RST => REG_1_14_tsimcreated_prld_Q,
      O => REG_1_14_Q
    );
  REG_1_14_D_780 : X_XOR2
    port map (
      I0 => REG_1_14_D1,
      I1 => REG_1_14_D2,
      O => REG_1_14_D
    );
  REG_1_14_D1_781 : X_ZERO
    port map (
      O => REG_1_14_D1
    );
  REG_1_14_D2_PT_0_782 : X_AND2
    port map (
      I0 => EXP58_EXP,
      I1 => EXP58_EXP,
      O => REG_1_14_D2_PT_0
    );
  REG_1_14_D2_PT_1_783 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_14_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_14_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_13,
      I5 => NlwInverterSignal_REG_1_14_D2_PT_1_IN5,
      O => REG_1_14_D2_PT_1
    );
  REG_1_14_D2_PT_2_784 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_14_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_14_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_14_D2_PT_2_IN4,
      I5 => REG_1_14,
      O => REG_1_14_D2_PT_2
    );
  REG_1_14_D2_785 : X_OR3
    port map (
      I0 => REG_1_14_D2_PT_0,
      I1 => REG_1_14_D2_PT_1,
      I2 => REG_1_14_D2_PT_2,
      O => REG_1_14_D2
    );
  REG_1_14_CLKF_786 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_14_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_14_CLKF_IN1,
      O => REG_1_14_CLKF
    );
  REG_1_14_SETF_787 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_14_IBUF,
      O => REG_1_14_SETF
    );
  REG_1_14_RSTF_788 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_14_RSTF_IN2,
      O => REG_1_14_RSTF
    );
  REG_1_15_789 : X_BUF
    port map (
      I => REG_1_15_Q,
      O => REG_1_15
    );
  REG_1_15_tsimcreated_xor_Q_790 : X_XOR2
    port map (
      I0 => REG_1_15_D,
      I1 => REG_1_15_Q,
      O => REG_1_15_tsimcreated_xor_Q
    );
  REG_1_15_tsimcreated_set_and_noreset_Q_791 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_15_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_15_SETF,
      O => REG_1_15_tsimcreated_set_and_noreset_Q
    );
  REG_1_15_tsimcreated_prld_Q_792 : X_OR2
    port map (
      I0 => REG_1_15_RSTF,
      I1 => PRLD,
      O => REG_1_15_tsimcreated_prld_Q
    );
  REG_1_15_REG : X_FF
    port map (
      I => REG_1_15_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_15_CLKF,
      SET => REG_1_15_tsimcreated_set_and_noreset_Q,
      RST => REG_1_15_tsimcreated_prld_Q,
      O => REG_1_15_Q
    );
  REG_1_15_D_793 : X_XOR2
    port map (
      I0 => REG_1_15_D1,
      I1 => REG_1_15_D2,
      O => REG_1_15_D
    );
  REG_1_15_D1_794 : X_ZERO
    port map (
      O => REG_1_15_D1
    );
  REG_1_15_D2_PT_0_795 : X_AND2
    port map (
      I0 => EXP57_EXP,
      I1 => EXP57_EXP,
      O => REG_1_15_D2_PT_0
    );
  REG_1_15_D2_PT_1_796 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_15_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_15_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_14,
      I5 => NlwInverterSignal_REG_1_15_D2_PT_1_IN5,
      O => REG_1_15_D2_PT_1
    );
  REG_1_15_D2_PT_2_797 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_15_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_15_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_15_D2_PT_2_IN4,
      I5 => REG_1_15,
      O => REG_1_15_D2_PT_2
    );
  REG_1_15_D2_798 : X_OR3
    port map (
      I0 => REG_1_15_D2_PT_0,
      I1 => REG_1_15_D2_PT_1,
      I2 => REG_1_15_D2_PT_2,
      O => REG_1_15_D2
    );
  REG_1_15_CLKF_799 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_15_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_15_CLKF_IN1,
      O => REG_1_15_CLKF
    );
  REG_1_15_SETF_800 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_15_IBUF,
      O => REG_1_15_SETF
    );
  REG_1_15_RSTF_801 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_15_RSTF_IN2,
      O => REG_1_15_RSTF
    );
  REG_1_16_802 : X_BUF
    port map (
      I => REG_1_16_Q,
      O => REG_1_16
    );
  REG_1_16_tsimcreated_xor_Q_803 : X_XOR2
    port map (
      I0 => REG_1_16_D,
      I1 => REG_1_16_Q,
      O => REG_1_16_tsimcreated_xor_Q
    );
  REG_1_16_tsimcreated_set_and_noreset_Q_804 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_16_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_16_SETF,
      O => REG_1_16_tsimcreated_set_and_noreset_Q
    );
  REG_1_16_tsimcreated_prld_Q_805 : X_OR2
    port map (
      I0 => REG_1_16_RSTF,
      I1 => PRLD,
      O => REG_1_16_tsimcreated_prld_Q
    );
  REG_1_16_REG : X_FF
    port map (
      I => REG_1_16_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_16_CLKF,
      SET => REG_1_16_tsimcreated_set_and_noreset_Q,
      RST => REG_1_16_tsimcreated_prld_Q,
      O => REG_1_16_Q
    );
  REG_1_16_D_806 : X_XOR2
    port map (
      I0 => REG_1_16_D1,
      I1 => REG_1_16_D2,
      O => REG_1_16_D
    );
  REG_1_16_D1_807 : X_ZERO
    port map (
      O => REG_1_16_D1
    );
  REG_1_16_D2_PT_0_808 : X_AND2
    port map (
      I0 => EXP54_EXP,
      I1 => EXP54_EXP,
      O => REG_1_16_D2_PT_0
    );
  REG_1_16_D2_PT_1_809 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_16_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_16_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_15,
      I5 => NlwInverterSignal_REG_1_16_D2_PT_1_IN5,
      O => REG_1_16_D2_PT_1
    );
  REG_1_16_D2_PT_2_810 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_16_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_16_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_16_D2_PT_2_IN4,
      I5 => REG_1_16,
      O => REG_1_16_D2_PT_2
    );
  REG_1_16_D2_811 : X_OR3
    port map (
      I0 => REG_1_16_D2_PT_0,
      I1 => REG_1_16_D2_PT_1,
      I2 => REG_1_16_D2_PT_2,
      O => REG_1_16_D2
    );
  REG_1_16_CLKF_812 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_16_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_16_CLKF_IN1,
      O => REG_1_16_CLKF
    );
  REG_1_16_SETF_813 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_16_IBUF,
      O => REG_1_16_SETF
    );
  REG_1_16_RSTF_814 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_16_RSTF_IN2,
      O => REG_1_16_RSTF
    );
  REG_1_17_815 : X_BUF
    port map (
      I => REG_1_17_Q,
      O => REG_1_17
    );
  REG_1_17_EXP_816 : X_BUF
    port map (
      I => REG_1_17_EXP_tsimrenamed_net_Q,
      O => REG_1_17_EXP
    );
  REG_1_17_tsimcreated_xor_Q_817 : X_XOR2
    port map (
      I0 => REG_1_17_D,
      I1 => REG_1_17_Q,
      O => REG_1_17_tsimcreated_xor_Q
    );
  REG_1_17_tsimcreated_set_and_noreset_Q_818 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_17_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_17_SETF,
      O => REG_1_17_tsimcreated_set_and_noreset_Q
    );
  REG_1_17_tsimcreated_prld_Q_819 : X_OR2
    port map (
      I0 => REG_1_17_RSTF,
      I1 => PRLD,
      O => REG_1_17_tsimcreated_prld_Q
    );
  REG_1_17_REG : X_FF
    port map (
      I => REG_1_17_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_17_CLKF,
      SET => REG_1_17_tsimcreated_set_and_noreset_Q,
      RST => REG_1_17_tsimcreated_prld_Q,
      O => REG_1_17_Q
    );
  REG_1_17_D_820 : X_XOR2
    port map (
      I0 => REG_1_17_D1,
      I1 => REG_1_17_D2,
      O => REG_1_17_D
    );
  REG_1_17_D1_821 : X_ZERO
    port map (
      O => REG_1_17_D1
    );
  REG_1_17_D2_PT_0_822 : X_AND2
    port map (
      I0 => EXP61_EXP,
      I1 => EXP61_EXP,
      O => REG_1_17_D2_PT_0
    );
  REG_1_17_D2_PT_1_823 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_17_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_17_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_17_D2_PT_1_IN4,
      I5 => REG_1_17,
      O => REG_1_17_D2_PT_1
    );
  REG_1_17_D2_824 : X_OR2
    port map (
      I0 => REG_1_17_D2_PT_0,
      I1 => REG_1_17_D2_PT_1,
      O => REG_1_17_D2
    );
  REG_1_17_CLKF_825 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_17_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_17_CLKF_IN1,
      O => REG_1_17_CLKF
    );
  REG_1_17_SETF_826 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_17_IBUF,
      O => REG_1_17_SETF
    );
  REG_1_17_RSTF_827 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_17_RSTF_IN2,
      O => REG_1_17_RSTF
    );
  REG_1_17_EXP_tsimrenamed_net_Q_828 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_18_IBUF,
      I6 => NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN6,
      O => REG_1_17_EXP_tsimrenamed_net_Q
    );
  REG_1_18_829 : X_BUF
    port map (
      I => REG_1_18_Q,
      O => REG_1_18
    );
  REG_1_18_tsimcreated_xor_Q_830 : X_XOR2
    port map (
      I0 => REG_1_18_D,
      I1 => REG_1_18_Q,
      O => REG_1_18_tsimcreated_xor_Q
    );
  REG_1_18_tsimcreated_set_and_noreset_Q_831 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_18_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_18_SETF,
      O => REG_1_18_tsimcreated_set_and_noreset_Q
    );
  REG_1_18_tsimcreated_prld_Q_832 : X_OR2
    port map (
      I0 => REG_1_18_RSTF,
      I1 => PRLD,
      O => REG_1_18_tsimcreated_prld_Q
    );
  REG_1_18_REG : X_FF
    port map (
      I => REG_1_18_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_18_CLKF,
      SET => REG_1_18_tsimcreated_set_and_noreset_Q,
      RST => REG_1_18_tsimcreated_prld_Q,
      O => REG_1_18_Q
    );
  REG_1_18_D_833 : X_XOR2
    port map (
      I0 => REG_1_18_D1,
      I1 => REG_1_18_D2,
      O => REG_1_18_D
    );
  REG_1_18_D1_834 : X_ZERO
    port map (
      O => REG_1_18_D1
    );
  REG_1_18_D2_PT_0_835 : X_AND2
    port map (
      I0 => REG_1_17_EXP,
      I1 => REG_1_17_EXP,
      O => REG_1_18_D2_PT_0
    );
  REG_1_18_D2_PT_1_836 : X_AND2
    port map (
      I0 => REG_1_19_EXP,
      I1 => REG_1_19_EXP,
      O => REG_1_18_D2_PT_1
    );
  REG_1_18_D2_PT_2_837 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_18_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_18_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_17,
      I5 => NlwInverterSignal_REG_1_18_D2_PT_2_IN5,
      O => REG_1_18_D2_PT_2
    );
  REG_1_18_D2_PT_3_838 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_18_D2_PT_3_IN0,
      I1 => NlwInverterSignal_REG_1_18_D2_PT_3_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_18_D2_PT_3_IN4,
      I5 => REG_1_18,
      O => REG_1_18_D2_PT_3
    );
  REG_1_18_D2_839 : X_OR4
    port map (
      I0 => REG_1_18_D2_PT_0,
      I1 => REG_1_18_D2_PT_1,
      I2 => REG_1_18_D2_PT_2,
      I3 => REG_1_18_D2_PT_3,
      O => REG_1_18_D2
    );
  REG_1_18_CLKF_840 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_18_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_18_CLKF_IN1,
      O => REG_1_18_CLKF
    );
  REG_1_18_SETF_841 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_18_IBUF,
      O => REG_1_18_SETF
    );
  REG_1_18_RSTF_842 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_18_RSTF_IN2,
      O => REG_1_18_RSTF
    );
  REG_1_19_843 : X_BUF
    port map (
      I => REG_1_19_Q,
      O => REG_1_19
    );
  REG_1_19_EXP_844 : X_BUF
    port map (
      I => REG_1_19_EXP_tsimrenamed_net_Q,
      O => REG_1_19_EXP
    );
  REG_1_19_tsimcreated_xor_Q_845 : X_XOR2
    port map (
      I0 => REG_1_19_D,
      I1 => REG_1_19_Q,
      O => REG_1_19_tsimcreated_xor_Q
    );
  REG_1_19_tsimcreated_set_and_noreset_Q_846 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_19_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_19_SETF,
      O => REG_1_19_tsimcreated_set_and_noreset_Q
    );
  REG_1_19_tsimcreated_prld_Q_847 : X_OR2
    port map (
      I0 => REG_1_19_RSTF,
      I1 => PRLD,
      O => REG_1_19_tsimcreated_prld_Q
    );
  REG_1_19_REG : X_FF
    port map (
      I => REG_1_19_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_19_CLKF,
      SET => REG_1_19_tsimcreated_set_and_noreset_Q,
      RST => REG_1_19_tsimcreated_prld_Q,
      O => REG_1_19_Q
    );
  REG_1_19_D_848 : X_XOR2
    port map (
      I0 => REG_1_19_D1,
      I1 => REG_1_19_D2,
      O => REG_1_19_D
    );
  REG_1_19_D1_849 : X_ZERO
    port map (
      O => REG_1_19_D1
    );
  REG_1_19_D2_PT_0_850 : X_AND2
    port map (
      I0 => EXP60_EXP,
      I1 => EXP60_EXP,
      O => REG_1_19_D2_PT_0
    );
  REG_1_19_D2_PT_1_851 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_19_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_19_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_19_D2_PT_1_IN4,
      I5 => REG_1_19,
      O => REG_1_19_D2_PT_1
    );
  REG_1_19_D2_852 : X_OR2
    port map (
      I0 => REG_1_19_D2_PT_0,
      I1 => REG_1_19_D2_PT_1,
      O => REG_1_19_D2
    );
  REG_1_19_CLKF_853 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_19_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_19_CLKF_IN1,
      O => REG_1_19_CLKF
    );
  REG_1_19_SETF_854 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_19_IBUF,
      O => REG_1_19_SETF
    );
  REG_1_19_RSTF_855 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_19_RSTF_IN2,
      O => REG_1_19_RSTF
    );
  REG_1_19_EXP_tsimrenamed_net_Q_856 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN5,
      I6 => REG_1_18,
      O => REG_1_19_EXP_tsimrenamed_net_Q
    );
  REG_1_2_857 : X_BUF
    port map (
      I => REG_1_2_Q,
      O => REG_1_2
    );
  REG_1_2_tsimcreated_xor_Q_858 : X_XOR2
    port map (
      I0 => REG_1_2_D,
      I1 => REG_1_2_Q,
      O => REG_1_2_tsimcreated_xor_Q
    );
  REG_1_2_tsimcreated_set_and_noreset_Q_859 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_2_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_2_SETF,
      O => REG_1_2_tsimcreated_set_and_noreset_Q
    );
  REG_1_2_tsimcreated_prld_Q_860 : X_OR2
    port map (
      I0 => REG_1_2_RSTF,
      I1 => PRLD,
      O => REG_1_2_tsimcreated_prld_Q
    );
  REG_1_2_REG : X_FF
    port map (
      I => REG_1_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_2_CLKF,
      SET => REG_1_2_tsimcreated_set_and_noreset_Q,
      RST => REG_1_2_tsimcreated_prld_Q,
      O => REG_1_2_Q
    );
  REG_1_2_D_861 : X_XOR2
    port map (
      I0 => REG_1_2_D1,
      I1 => REG_1_2_D2,
      O => REG_1_2_D
    );
  REG_1_2_D1_862 : X_ZERO
    port map (
      O => REG_1_2_D1
    );
  REG_1_2_D2_PT_0_863 : X_AND2
    port map (
      I0 => REG_1_3_EXP,
      I1 => REG_1_3_EXP,
      O => REG_1_2_D2_PT_0
    );
  REG_1_2_D2_PT_1_864 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_2_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_2_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_1,
      I5 => NlwInverterSignal_REG_1_2_D2_PT_1_IN5,
      O => REG_1_2_D2_PT_1
    );
  REG_1_2_D2_PT_2_865 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_2_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_2_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_2_D2_PT_2_IN4,
      I5 => REG_1_2,
      O => REG_1_2_D2_PT_2
    );
  REG_1_2_D2_866 : X_OR3
    port map (
      I0 => REG_1_2_D2_PT_0,
      I1 => REG_1_2_D2_PT_1,
      I2 => REG_1_2_D2_PT_2,
      O => REG_1_2_D2
    );
  REG_1_2_CLKF_867 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_2_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_2_CLKF_IN1,
      O => REG_1_2_CLKF
    );
  REG_1_2_SETF_868 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_2_IBUF,
      O => REG_1_2_SETF
    );
  REG_1_2_RSTF_869 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_2_RSTF_IN2,
      O => REG_1_2_RSTF
    );
  REG_1_20_870 : X_BUF
    port map (
      I => REG_1_20_Q,
      O => REG_1_20
    );
  REG_1_20_tsimcreated_xor_Q_871 : X_XOR2
    port map (
      I0 => REG_1_20_D,
      I1 => REG_1_20_Q,
      O => REG_1_20_tsimcreated_xor_Q
    );
  REG_1_20_tsimcreated_set_and_noreset_Q_872 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_20_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_20_SETF,
      O => REG_1_20_tsimcreated_set_and_noreset_Q
    );
  REG_1_20_tsimcreated_prld_Q_873 : X_OR2
    port map (
      I0 => REG_1_20_RSTF,
      I1 => PRLD,
      O => REG_1_20_tsimcreated_prld_Q
    );
  REG_1_20_REG : X_FF
    port map (
      I => REG_1_20_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_20_CLKF,
      SET => REG_1_20_tsimcreated_set_and_noreset_Q,
      RST => REG_1_20_tsimcreated_prld_Q,
      O => REG_1_20_Q
    );
  REG_1_20_D_874 : X_XOR2
    port map (
      I0 => REG_1_20_D1,
      I1 => REG_1_20_D2,
      O => REG_1_20_D
    );
  REG_1_20_D1_875 : X_ZERO
    port map (
      O => REG_1_20_D1
    );
  REG_1_20_D2_PT_0_876 : X_AND2
    port map (
      I0 => EXP63_EXP,
      I1 => EXP63_EXP,
      O => REG_1_20_D2_PT_0
    );
  REG_1_20_D2_PT_1_877 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_20_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_20_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_19,
      I5 => NlwInverterSignal_REG_1_20_D2_PT_1_IN5,
      O => REG_1_20_D2_PT_1
    );
  REG_1_20_D2_PT_2_878 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_20_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_20_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_20_D2_PT_2_IN4,
      I5 => REG_1_20,
      O => REG_1_20_D2_PT_2
    );
  REG_1_20_D2_879 : X_OR3
    port map (
      I0 => REG_1_20_D2_PT_0,
      I1 => REG_1_20_D2_PT_1,
      I2 => REG_1_20_D2_PT_2,
      O => REG_1_20_D2
    );
  REG_1_20_CLKF_880 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_20_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_20_CLKF_IN1,
      O => REG_1_20_CLKF
    );
  REG_1_20_SETF_881 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_20_IBUF,
      O => REG_1_20_SETF
    );
  REG_1_20_RSTF_882 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_20_RSTF_IN2,
      O => REG_1_20_RSTF
    );
  REG_1_21_883 : X_BUF
    port map (
      I => REG_1_21_Q,
      O => REG_1_21
    );
  REG_1_21_tsimcreated_xor_Q_884 : X_XOR2
    port map (
      I0 => REG_1_21_D,
      I1 => REG_1_21_Q,
      O => REG_1_21_tsimcreated_xor_Q
    );
  REG_1_21_tsimcreated_set_and_noreset_Q_885 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_21_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_21_SETF,
      O => REG_1_21_tsimcreated_set_and_noreset_Q
    );
  REG_1_21_tsimcreated_prld_Q_886 : X_OR2
    port map (
      I0 => REG_1_21_RSTF,
      I1 => PRLD,
      O => REG_1_21_tsimcreated_prld_Q
    );
  REG_1_21_REG : X_FF
    port map (
      I => REG_1_21_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_21_CLKF,
      SET => REG_1_21_tsimcreated_set_and_noreset_Q,
      RST => REG_1_21_tsimcreated_prld_Q,
      O => REG_1_21_Q
    );
  REG_1_21_D_887 : X_XOR2
    port map (
      I0 => REG_1_21_D1,
      I1 => REG_1_21_D2,
      O => REG_1_21_D
    );
  REG_1_21_D1_888 : X_ZERO
    port map (
      O => REG_1_21_D1
    );
  REG_1_21_D2_PT_0_889 : X_AND2
    port map (
      I0 => EXP62_EXP,
      I1 => EXP62_EXP,
      O => REG_1_21_D2_PT_0
    );
  REG_1_21_D2_PT_1_890 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_21_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_21_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_20,
      I5 => NlwInverterSignal_REG_1_21_D2_PT_1_IN5,
      O => REG_1_21_D2_PT_1
    );
  REG_1_21_D2_PT_2_891 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_21_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_21_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_21_D2_PT_2_IN4,
      I5 => REG_1_21,
      O => REG_1_21_D2_PT_2
    );
  REG_1_21_D2_892 : X_OR3
    port map (
      I0 => REG_1_21_D2_PT_0,
      I1 => REG_1_21_D2_PT_1,
      I2 => REG_1_21_D2_PT_2,
      O => REG_1_21_D2
    );
  REG_1_21_CLKF_893 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_21_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_21_CLKF_IN1,
      O => REG_1_21_CLKF
    );
  REG_1_21_SETF_894 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_21_IBUF,
      O => REG_1_21_SETF
    );
  REG_1_21_RSTF_895 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_21_RSTF_IN2,
      O => REG_1_21_RSTF
    );
  REG_1_22_896 : X_BUF
    port map (
      I => REG_1_22_Q,
      O => REG_1_22
    );
  REG_1_22_tsimcreated_xor_Q_897 : X_XOR2
    port map (
      I0 => REG_1_22_D,
      I1 => REG_1_22_Q,
      O => REG_1_22_tsimcreated_xor_Q
    );
  REG_1_22_tsimcreated_set_and_noreset_Q_898 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_22_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_22_SETF,
      O => REG_1_22_tsimcreated_set_and_noreset_Q
    );
  REG_1_22_tsimcreated_prld_Q_899 : X_OR2
    port map (
      I0 => REG_1_22_RSTF,
      I1 => PRLD,
      O => REG_1_22_tsimcreated_prld_Q
    );
  REG_1_22_REG : X_FF
    port map (
      I => REG_1_22_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_22_CLKF,
      SET => REG_1_22_tsimcreated_set_and_noreset_Q,
      RST => REG_1_22_tsimcreated_prld_Q,
      O => REG_1_22_Q
    );
  REG_1_22_D_900 : X_XOR2
    port map (
      I0 => REG_1_22_D1,
      I1 => REG_1_22_D2,
      O => REG_1_22_D
    );
  REG_1_22_D1_901 : X_ZERO
    port map (
      O => REG_1_22_D1
    );
  REG_1_22_D2_PT_0_902 : X_AND2
    port map (
      I0 => EXP59_EXP,
      I1 => EXP59_EXP,
      O => REG_1_22_D2_PT_0
    );
  REG_1_22_D2_PT_1_903 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_22_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_22_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_21,
      I5 => NlwInverterSignal_REG_1_22_D2_PT_1_IN5,
      O => REG_1_22_D2_PT_1
    );
  REG_1_22_D2_PT_2_904 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_22_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_22_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_22_D2_PT_2_IN4,
      I5 => REG_1_22,
      O => REG_1_22_D2_PT_2
    );
  REG_1_22_D2_905 : X_OR3
    port map (
      I0 => REG_1_22_D2_PT_0,
      I1 => REG_1_22_D2_PT_1,
      I2 => REG_1_22_D2_PT_2,
      O => REG_1_22_D2
    );
  REG_1_22_CLKF_906 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_22_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_22_CLKF_IN1,
      O => REG_1_22_CLKF
    );
  REG_1_22_SETF_907 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_22_IBUF,
      O => REG_1_22_SETF
    );
  REG_1_22_RSTF_908 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_22_RSTF_IN2,
      O => REG_1_22_RSTF
    );
  REG_1_23_909 : X_BUF
    port map (
      I => REG_1_23_Q,
      O => REG_1_23
    );
  REG_1_23_tsimcreated_xor_Q_910 : X_XOR2
    port map (
      I0 => REG_1_23_D,
      I1 => REG_1_23_Q,
      O => REG_1_23_tsimcreated_xor_Q
    );
  REG_1_23_tsimcreated_set_and_noreset_Q_911 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_23_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_23_SETF,
      O => REG_1_23_tsimcreated_set_and_noreset_Q
    );
  REG_1_23_tsimcreated_prld_Q_912 : X_OR2
    port map (
      I0 => REG_1_23_RSTF,
      I1 => PRLD,
      O => REG_1_23_tsimcreated_prld_Q
    );
  REG_1_23_REG : X_FF
    port map (
      I => REG_1_23_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_23_CLKF,
      SET => REG_1_23_tsimcreated_set_and_noreset_Q,
      RST => REG_1_23_tsimcreated_prld_Q,
      O => REG_1_23_Q
    );
  REG_1_23_D_913 : X_XOR2
    port map (
      I0 => REG_1_23_D1,
      I1 => REG_1_23_D2,
      O => REG_1_23_D
    );
  REG_1_23_D1_914 : X_ZERO
    port map (
      O => REG_1_23_D1
    );
  REG_1_23_D2_PT_0_915 : X_AND2
    port map (
      I0 => REG_0_27_EXP,
      I1 => REG_0_27_EXP,
      O => REG_1_23_D2_PT_0
    );
  REG_1_23_D2_PT_1_916 : X_AND2
    port map (
      I0 => REG_1_24_EXP,
      I1 => REG_1_24_EXP,
      O => REG_1_23_D2_PT_1
    );
  REG_1_23_D2_PT_2_917 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_23_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_23_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_23,
      I5 => NlwInverterSignal_REG_1_23_D2_PT_2_IN5,
      O => REG_1_23_D2_PT_2
    );
  REG_1_23_D2_PT_3_918 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_23_D2_PT_3_IN0,
      I1 => NlwInverterSignal_REG_1_23_D2_PT_3_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_23_D2_PT_3_IN4,
      I5 => REG_1_22,
      O => REG_1_23_D2_PT_3
    );
  REG_1_23_D2_919 : X_OR4
    port map (
      I0 => REG_1_23_D2_PT_0,
      I1 => REG_1_23_D2_PT_1,
      I2 => REG_1_23_D2_PT_2,
      I3 => REG_1_23_D2_PT_3,
      O => REG_1_23_D2
    );
  REG_1_23_CLKF_920 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_23_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_23_CLKF_IN1,
      O => REG_1_23_CLKF
    );
  REG_1_23_SETF_921 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_23_IBUF,
      O => REG_1_23_SETF
    );
  REG_1_23_RSTF_922 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_23_RSTF_IN2,
      O => REG_1_23_RSTF
    );
  REG_1_24_923 : X_BUF
    port map (
      I => REG_1_24_Q,
      O => REG_1_24
    );
  REG_1_24_EXP_924 : X_BUF
    port map (
      I => REG_1_24_EXP_tsimrenamed_net_Q,
      O => REG_1_24_EXP
    );
  REG_1_24_tsimcreated_xor_Q_925 : X_XOR2
    port map (
      I0 => REG_1_24_D,
      I1 => REG_1_24_Q,
      O => REG_1_24_tsimcreated_xor_Q
    );
  REG_1_24_tsimcreated_set_and_noreset_Q_926 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_24_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_24_SETF,
      O => REG_1_24_tsimcreated_set_and_noreset_Q
    );
  REG_1_24_tsimcreated_prld_Q_927 : X_OR2
    port map (
      I0 => REG_1_24_RSTF,
      I1 => PRLD,
      O => REG_1_24_tsimcreated_prld_Q
    );
  REG_1_24_REG : X_FF
    port map (
      I => REG_1_24_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_24_CLKF,
      SET => REG_1_24_tsimcreated_set_and_noreset_Q,
      RST => REG_1_24_tsimcreated_prld_Q,
      O => REG_1_24_Q
    );
  REG_1_24_D_928 : X_XOR2
    port map (
      I0 => REG_1_24_D1,
      I1 => REG_1_24_D2,
      O => REG_1_24_D
    );
  REG_1_24_D1_929 : X_ZERO
    port map (
      O => REG_1_24_D1
    );
  REG_1_24_D2_PT_0_930 : X_AND2
    port map (
      I0 => EXP38_EXP,
      I1 => EXP38_EXP,
      O => REG_1_24_D2_PT_0
    );
  REG_1_24_D2_PT_1_931 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_24_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_24_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_24_D2_PT_1_IN4,
      I5 => REG_1_24,
      O => REG_1_24_D2_PT_1
    );
  REG_1_24_D2_932 : X_OR2
    port map (
      I0 => REG_1_24_D2_PT_0,
      I1 => REG_1_24_D2_PT_1,
      O => REG_1_24_D2
    );
  REG_1_24_CLKF_933 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_24_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_24_CLKF_IN1,
      O => REG_1_24_CLKF
    );
  REG_1_24_SETF_934 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_24_IBUF,
      O => REG_1_24_SETF
    );
  REG_1_24_RSTF_935 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_24_RSTF_IN2,
      O => REG_1_24_RSTF
    );
  REG_1_24_EXP_tsimrenamed_net_Q_936 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN5,
      I6 => REG_1_23,
      O => REG_1_24_EXP_tsimrenamed_net_Q
    );
  REG_1_25_937 : X_BUF
    port map (
      I => REG_1_25_Q,
      O => REG_1_25
    );
  REG_1_25_tsimcreated_xor_Q_938 : X_XOR2
    port map (
      I0 => REG_1_25_D,
      I1 => REG_1_25_Q,
      O => REG_1_25_tsimcreated_xor_Q
    );
  REG_1_25_tsimcreated_set_and_noreset_Q_939 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_25_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_25_SETF,
      O => REG_1_25_tsimcreated_set_and_noreset_Q
    );
  REG_1_25_tsimcreated_prld_Q_940 : X_OR2
    port map (
      I0 => REG_1_25_RSTF,
      I1 => PRLD,
      O => REG_1_25_tsimcreated_prld_Q
    );
  REG_1_25_REG : X_FF
    port map (
      I => REG_1_25_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_25_CLKF,
      SET => REG_1_25_tsimcreated_set_and_noreset_Q,
      RST => REG_1_25_tsimcreated_prld_Q,
      O => REG_1_25_Q
    );
  REG_1_25_D_941 : X_XOR2
    port map (
      I0 => REG_1_25_D1,
      I1 => REG_1_25_D2,
      O => REG_1_25_D
    );
  REG_1_25_D1_942 : X_ZERO
    port map (
      O => REG_1_25_D1
    );
  REG_1_25_D2_PT_0_943 : X_AND2
    port map (
      I0 => EXP41_EXP,
      I1 => EXP41_EXP,
      O => REG_1_25_D2_PT_0
    );
  REG_1_25_D2_PT_1_944 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_25_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_25_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_24,
      I5 => NlwInverterSignal_REG_1_25_D2_PT_1_IN5,
      O => REG_1_25_D2_PT_1
    );
  REG_1_25_D2_PT_2_945 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_25_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_25_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_25_D2_PT_2_IN4,
      I5 => REG_1_25,
      O => REG_1_25_D2_PT_2
    );
  REG_1_25_D2_946 : X_OR3
    port map (
      I0 => REG_1_25_D2_PT_0,
      I1 => REG_1_25_D2_PT_1,
      I2 => REG_1_25_D2_PT_2,
      O => REG_1_25_D2
    );
  REG_1_25_CLKF_947 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_25_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_25_CLKF_IN1,
      O => REG_1_25_CLKF
    );
  REG_1_25_SETF_948 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_25_IBUF,
      O => REG_1_25_SETF
    );
  REG_1_25_RSTF_949 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_25_RSTF_IN2,
      O => REG_1_25_RSTF
    );
  REG_1_26_950 : X_BUF
    port map (
      I => REG_1_26_Q,
      O => REG_1_26
    );
  REG_1_26_tsimcreated_xor_Q_951 : X_XOR2
    port map (
      I0 => REG_1_26_D,
      I1 => REG_1_26_Q,
      O => REG_1_26_tsimcreated_xor_Q
    );
  REG_1_26_tsimcreated_set_and_noreset_Q_952 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_26_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_26_SETF,
      O => REG_1_26_tsimcreated_set_and_noreset_Q
    );
  REG_1_26_tsimcreated_prld_Q_953 : X_OR2
    port map (
      I0 => REG_1_26_RSTF,
      I1 => PRLD,
      O => REG_1_26_tsimcreated_prld_Q
    );
  REG_1_26_REG : X_FF
    port map (
      I => REG_1_26_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_26_CLKF,
      SET => REG_1_26_tsimcreated_set_and_noreset_Q,
      RST => REG_1_26_tsimcreated_prld_Q,
      O => REG_1_26_Q
    );
  REG_1_26_D_954 : X_XOR2
    port map (
      I0 => REG_1_26_D1,
      I1 => REG_1_26_D2,
      O => REG_1_26_D
    );
  REG_1_26_D1_955 : X_ZERO
    port map (
      O => REG_1_26_D1
    );
  REG_1_26_D2_PT_0_956 : X_AND2
    port map (
      I0 => EXP40_EXP,
      I1 => EXP40_EXP,
      O => REG_1_26_D2_PT_0
    );
  REG_1_26_D2_PT_1_957 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_26_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_26_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_25,
      I5 => NlwInverterSignal_REG_1_26_D2_PT_1_IN5,
      O => REG_1_26_D2_PT_1
    );
  REG_1_26_D2_PT_2_958 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_26_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_26_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_26_D2_PT_2_IN4,
      I5 => REG_1_26,
      O => REG_1_26_D2_PT_2
    );
  REG_1_26_D2_959 : X_OR3
    port map (
      I0 => REG_1_26_D2_PT_0,
      I1 => REG_1_26_D2_PT_1,
      I2 => REG_1_26_D2_PT_2,
      O => REG_1_26_D2
    );
  REG_1_26_CLKF_960 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_26_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_26_CLKF_IN1,
      O => REG_1_26_CLKF
    );
  REG_1_26_SETF_961 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_26_IBUF,
      O => REG_1_26_SETF
    );
  REG_1_26_RSTF_962 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_26_RSTF_IN2,
      O => REG_1_26_RSTF
    );
  REG_1_27_963 : X_BUF
    port map (
      I => REG_1_27_Q,
      O => REG_1_27
    );
  REG_1_27_tsimcreated_xor_Q_964 : X_XOR2
    port map (
      I0 => REG_1_27_D,
      I1 => REG_1_27_Q,
      O => REG_1_27_tsimcreated_xor_Q
    );
  REG_1_27_tsimcreated_set_and_noreset_Q_965 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_27_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_27_SETF,
      O => REG_1_27_tsimcreated_set_and_noreset_Q
    );
  REG_1_27_tsimcreated_prld_Q_966 : X_OR2
    port map (
      I0 => REG_1_27_RSTF,
      I1 => PRLD,
      O => REG_1_27_tsimcreated_prld_Q
    );
  REG_1_27_REG : X_FF
    port map (
      I => REG_1_27_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_27_CLKF,
      SET => REG_1_27_tsimcreated_set_and_noreset_Q,
      RST => REG_1_27_tsimcreated_prld_Q,
      O => REG_1_27_Q
    );
  REG_1_27_D_967 : X_XOR2
    port map (
      I0 => REG_1_27_D1,
      I1 => REG_1_27_D2,
      O => REG_1_27_D
    );
  REG_1_27_D1_968 : X_ZERO
    port map (
      O => REG_1_27_D1
    );
  REG_1_27_D2_PT_0_969 : X_AND2
    port map (
      I0 => EXP37_EXP,
      I1 => EXP37_EXP,
      O => REG_1_27_D2_PT_0
    );
  REG_1_27_D2_PT_1_970 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_27_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_27_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_26,
      I5 => NlwInverterSignal_REG_1_27_D2_PT_1_IN5,
      O => REG_1_27_D2_PT_1
    );
  REG_1_27_D2_PT_2_971 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_27_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_27_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_27_D2_PT_2_IN4,
      I5 => REG_1_27,
      O => REG_1_27_D2_PT_2
    );
  REG_1_27_D2_972 : X_OR3
    port map (
      I0 => REG_1_27_D2_PT_0,
      I1 => REG_1_27_D2_PT_1,
      I2 => REG_1_27_D2_PT_2,
      O => REG_1_27_D2
    );
  REG_1_27_CLKF_973 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_27_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_27_CLKF_IN1,
      O => REG_1_27_CLKF
    );
  REG_1_27_SETF_974 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_27_IBUF,
      O => REG_1_27_SETF
    );
  REG_1_27_RSTF_975 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_27_RSTF_IN2,
      O => REG_1_27_RSTF
    );
  REG_1_28_976 : X_BUF
    port map (
      I => REG_1_28_Q,
      O => REG_1_28
    );
  REG_1_28_tsimcreated_xor_Q_977 : X_XOR2
    port map (
      I0 => REG_1_28_D,
      I1 => REG_1_28_Q,
      O => REG_1_28_tsimcreated_xor_Q
    );
  REG_1_28_tsimcreated_set_and_noreset_Q_978 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_28_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_28_SETF,
      O => REG_1_28_tsimcreated_set_and_noreset_Q
    );
  REG_1_28_tsimcreated_prld_Q_979 : X_OR2
    port map (
      I0 => REG_1_28_RSTF,
      I1 => PRLD,
      O => REG_1_28_tsimcreated_prld_Q
    );
  REG_1_28_REG : X_FF
    port map (
      I => REG_1_28_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_28_CLKF,
      SET => REG_1_28_tsimcreated_set_and_noreset_Q,
      RST => REG_1_28_tsimcreated_prld_Q,
      O => REG_1_28_Q
    );
  REG_1_28_D_980 : X_XOR2
    port map (
      I0 => REG_1_28_D1,
      I1 => REG_1_28_D2,
      O => REG_1_28_D
    );
  REG_1_28_D1_981 : X_ZERO
    port map (
      O => REG_1_28_D1
    );
  REG_1_28_D2_PT_0_982 : X_AND2
    port map (
      I0 => EXP68_EXP,
      I1 => EXP68_EXP,
      O => REG_1_28_D2_PT_0
    );
  REG_1_28_D2_PT_1_983 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_28_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_28_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_27,
      I5 => NlwInverterSignal_REG_1_28_D2_PT_1_IN5,
      O => REG_1_28_D2_PT_1
    );
  REG_1_28_D2_PT_2_984 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_28_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_28_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_28_D2_PT_2_IN4,
      I5 => REG_1_28,
      O => REG_1_28_D2_PT_2
    );
  REG_1_28_D2_985 : X_OR3
    port map (
      I0 => REG_1_28_D2_PT_0,
      I1 => REG_1_28_D2_PT_1,
      I2 => REG_1_28_D2_PT_2,
      O => REG_1_28_D2
    );
  REG_1_28_CLKF_986 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_28_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_28_CLKF_IN1,
      O => REG_1_28_CLKF
    );
  REG_1_28_SETF_987 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_28_IBUF,
      O => REG_1_28_SETF
    );
  REG_1_28_RSTF_988 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_28_RSTF_IN2,
      O => REG_1_28_RSTF
    );
  REG_1_29_989 : X_BUF
    port map (
      I => REG_1_29_Q,
      O => REG_1_29
    );
  REG_1_29_tsimcreated_xor_Q_990 : X_XOR2
    port map (
      I0 => REG_1_29_D,
      I1 => REG_1_29_Q,
      O => REG_1_29_tsimcreated_xor_Q
    );
  REG_1_29_tsimcreated_set_and_noreset_Q_991 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_29_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_29_SETF,
      O => REG_1_29_tsimcreated_set_and_noreset_Q
    );
  REG_1_29_tsimcreated_prld_Q_992 : X_OR2
    port map (
      I0 => REG_1_29_RSTF,
      I1 => PRLD,
      O => REG_1_29_tsimcreated_prld_Q
    );
  REG_1_29_REG : X_FF
    port map (
      I => REG_1_29_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_29_CLKF,
      SET => REG_1_29_tsimcreated_set_and_noreset_Q,
      RST => REG_1_29_tsimcreated_prld_Q,
      O => REG_1_29_Q
    );
  REG_1_29_D_993 : X_XOR2
    port map (
      I0 => REG_1_29_D1,
      I1 => REG_1_29_D2,
      O => REG_1_29_D
    );
  REG_1_29_D1_994 : X_ZERO
    port map (
      O => REG_1_29_D1
    );
  REG_1_29_D2_PT_0_995 : X_AND2
    port map (
      I0 => EXP28_EXP,
      I1 => EXP28_EXP,
      O => REG_1_29_D2_PT_0
    );
  REG_1_29_D2_PT_1_996 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_29_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_29_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_28,
      I5 => NlwInverterSignal_REG_1_29_D2_PT_1_IN5,
      O => REG_1_29_D2_PT_1
    );
  REG_1_29_D2_PT_2_997 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_29_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_29_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_29_D2_PT_2_IN4,
      I5 => REG_1_29,
      O => REG_1_29_D2_PT_2
    );
  REG_1_29_D2_998 : X_OR3
    port map (
      I0 => REG_1_29_D2_PT_0,
      I1 => REG_1_29_D2_PT_1,
      I2 => REG_1_29_D2_PT_2,
      O => REG_1_29_D2
    );
  REG_1_29_CLKF_999 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_29_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_29_CLKF_IN1,
      O => REG_1_29_CLKF
    );
  REG_1_29_SETF_1000 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_29_IBUF,
      O => REG_1_29_SETF
    );
  REG_1_29_RSTF_1001 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_29_RSTF_IN2,
      O => REG_1_29_RSTF
    );
  REG_1_3_1002 : X_BUF
    port map (
      I => REG_1_3_Q,
      O => REG_1_3
    );
  REG_1_3_EXP_1003 : X_BUF
    port map (
      I => REG_1_3_EXP_tsimrenamed_net_Q,
      O => REG_1_3_EXP
    );
  REG_1_3_tsimcreated_xor_Q_1004 : X_XOR2
    port map (
      I0 => REG_1_3_D,
      I1 => REG_1_3_Q,
      O => REG_1_3_tsimcreated_xor_Q
    );
  REG_1_3_tsimcreated_set_and_noreset_Q_1005 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_3_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_3_SETF,
      O => REG_1_3_tsimcreated_set_and_noreset_Q
    );
  REG_1_3_tsimcreated_prld_Q_1006 : X_OR2
    port map (
      I0 => REG_1_3_RSTF,
      I1 => PRLD,
      O => REG_1_3_tsimcreated_prld_Q
    );
  REG_1_3_REG : X_FF
    port map (
      I => REG_1_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_3_CLKF,
      SET => REG_1_3_tsimcreated_set_and_noreset_Q,
      RST => REG_1_3_tsimcreated_prld_Q,
      O => REG_1_3_Q
    );
  REG_1_3_D_1007 : X_XOR2
    port map (
      I0 => REG_1_3_D1,
      I1 => REG_1_3_D2,
      O => REG_1_3_D
    );
  REG_1_3_D1_1008 : X_ZERO
    port map (
      O => REG_1_3_D1
    );
  REG_1_3_D2_1009 : X_AND2
    port map (
      I0 => EXP53_EXP,
      I1 => EXP53_EXP,
      O => REG_1_3_D2
    );
  REG_1_3_CLKF_1010 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_3_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_3_CLKF_IN1,
      O => REG_1_3_CLKF
    );
  REG_1_3_SETF_1011 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_3_IBUF,
      O => REG_1_3_SETF
    );
  REG_1_3_RSTF_1012 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_3_RSTF_IN2,
      O => REG_1_3_RSTF
    );
  REG_1_3_EXP_PT_0_1013 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_1_3_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_2_IBUF,
      I6 => NlwInverterSignal_REG_1_3_EXP_PT_0_IN6,
      O => REG_1_3_EXP_PT_0
    );
  REG_1_3_EXP_PT_1_1014 : X_AND7
    port map (
      I0 => NlwInverterSignal_REG_1_3_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_REG_1_3_EXP_PT_1_IN5,
      I6 => REG_1_2,
      O => REG_1_3_EXP_PT_1
    );
  REG_1_3_EXP_tsimrenamed_net_Q_1015 : X_OR2
    port map (
      I0 => REG_1_3_EXP_PT_0,
      I1 => REG_1_3_EXP_PT_1,
      O => REG_1_3_EXP_tsimrenamed_net_Q
    );
  REG_1_30_1016 : X_BUF
    port map (
      I => REG_1_30_Q,
      O => REG_1_30
    );
  REG_1_30_tsimcreated_xor_Q_1017 : X_XOR2
    port map (
      I0 => REG_1_30_D,
      I1 => REG_1_30_Q,
      O => REG_1_30_tsimcreated_xor_Q
    );
  REG_1_30_tsimcreated_set_and_noreset_Q_1018 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_30_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_30_SETF,
      O => REG_1_30_tsimcreated_set_and_noreset_Q
    );
  REG_1_30_tsimcreated_prld_Q_1019 : X_OR2
    port map (
      I0 => REG_1_30_RSTF,
      I1 => PRLD,
      O => REG_1_30_tsimcreated_prld_Q
    );
  REG_1_30_REG : X_FF
    port map (
      I => REG_1_30_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_30_CLKF,
      SET => REG_1_30_tsimcreated_set_and_noreset_Q,
      RST => REG_1_30_tsimcreated_prld_Q,
      O => REG_1_30_Q
    );
  REG_1_30_D_1020 : X_XOR2
    port map (
      I0 => REG_1_30_D1,
      I1 => REG_1_30_D2,
      O => REG_1_30_D
    );
  REG_1_30_D1_1021 : X_ZERO
    port map (
      O => REG_1_30_D1
    );
  REG_1_30_D2_PT_0_1022 : X_AND2
    port map (
      I0 => DOUT_OBUFE_EXP,
      I1 => DOUT_OBUFE_EXP,
      O => REG_1_30_D2_PT_0
    );
  REG_1_30_D2_PT_1_1023 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_30_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_30_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_29,
      I5 => NlwInverterSignal_REG_1_30_D2_PT_1_IN5,
      O => REG_1_30_D2_PT_1
    );
  REG_1_30_D2_PT_2_1024 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_30_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_30_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_30_D2_PT_2_IN4,
      I5 => REG_1_30,
      O => REG_1_30_D2_PT_2
    );
  REG_1_30_D2_1025 : X_OR3
    port map (
      I0 => REG_1_30_D2_PT_0,
      I1 => REG_1_30_D2_PT_1,
      I2 => REG_1_30_D2_PT_2,
      O => REG_1_30_D2
    );
  REG_1_30_CLKF_1026 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_30_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_30_CLKF_IN1,
      O => REG_1_30_CLKF
    );
  REG_1_30_SETF_1027 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_30_IBUF,
      O => REG_1_30_SETF
    );
  REG_1_30_RSTF_1028 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_30_RSTF_IN2,
      O => REG_1_30_RSTF
    );
  REG_1_31_1029 : X_BUF
    port map (
      I => REG_1_31_Q,
      O => REG_1_31
    );
  REG_1_31_tsimcreated_xor_Q_1030 : X_XOR2
    port map (
      I0 => REG_1_31_D,
      I1 => REG_1_31_Q,
      O => REG_1_31_tsimcreated_xor_Q
    );
  REG_1_31_tsimcreated_set_and_noreset_Q_1031 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_31_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_31_SETF,
      O => REG_1_31_tsimcreated_set_and_noreset_Q
    );
  REG_1_31_tsimcreated_prld_Q_1032 : X_OR2
    port map (
      I0 => REG_1_31_RSTF,
      I1 => PRLD,
      O => REG_1_31_tsimcreated_prld_Q
    );
  REG_1_31_REG : X_FF
    port map (
      I => REG_1_31_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_31_CLKF,
      SET => REG_1_31_tsimcreated_set_and_noreset_Q,
      RST => REG_1_31_tsimcreated_prld_Q,
      O => REG_1_31_Q
    );
  REG_1_31_D_1033 : X_XOR2
    port map (
      I0 => REG_1_31_D1,
      I1 => REG_1_31_D2,
      O => REG_1_31_D
    );
  REG_1_31_D1_1034 : X_ZERO
    port map (
      O => REG_1_31_D1
    );
  REG_1_31_D2_PT_0_1035 : X_AND2
    port map (
      I0 => EXP27_EXP,
      I1 => EXP27_EXP,
      O => REG_1_31_D2_PT_0
    );
  REG_1_31_D2_PT_1_1036 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_31_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_31_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_30,
      I5 => NlwInverterSignal_REG_1_31_D2_PT_1_IN5,
      O => REG_1_31_D2_PT_1
    );
  REG_1_31_D2_PT_2_1037 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_31_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_31_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_31_D2_PT_2_IN4,
      I5 => REG_1_31,
      O => REG_1_31_D2_PT_2
    );
  REG_1_31_D2_1038 : X_OR3
    port map (
      I0 => REG_1_31_D2_PT_0,
      I1 => REG_1_31_D2_PT_1,
      I2 => REG_1_31_D2_PT_2,
      O => REG_1_31_D2
    );
  REG_1_31_CLKF_1039 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_31_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_31_CLKF_IN1,
      O => REG_1_31_CLKF
    );
  REG_1_31_SETF_1040 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_31_IBUF,
      O => REG_1_31_SETF
    );
  REG_1_31_RSTF_1041 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_31_RSTF_IN2,
      O => REG_1_31_RSTF
    );
  REG_1_4_1042 : X_BUF
    port map (
      I => REG_1_4_Q,
      O => REG_1_4
    );
  REG_1_4_tsimcreated_xor_Q_1043 : X_XOR2
    port map (
      I0 => REG_1_4_D,
      I1 => REG_1_4_Q,
      O => REG_1_4_tsimcreated_xor_Q
    );
  REG_1_4_tsimcreated_set_and_noreset_Q_1044 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_4_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_4_SETF,
      O => REG_1_4_tsimcreated_set_and_noreset_Q
    );
  REG_1_4_tsimcreated_prld_Q_1045 : X_OR2
    port map (
      I0 => REG_1_4_RSTF,
      I1 => PRLD,
      O => REG_1_4_tsimcreated_prld_Q
    );
  REG_1_4_REG : X_FF
    port map (
      I => REG_1_4_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_4_CLKF,
      SET => REG_1_4_tsimcreated_set_and_noreset_Q,
      RST => REG_1_4_tsimcreated_prld_Q,
      O => REG_1_4_Q
    );
  REG_1_4_D_1046 : X_XOR2
    port map (
      I0 => REG_1_4_D1,
      I1 => REG_1_4_D2,
      O => REG_1_4_D
    );
  REG_1_4_D1_1047 : X_ZERO
    port map (
      O => REG_1_4_D1
    );
  REG_1_4_D2_PT_0_1048 : X_AND2
    port map (
      I0 => REG_1_0_EXP,
      I1 => REG_1_0_EXP,
      O => REG_1_4_D2_PT_0
    );
  REG_1_4_D2_PT_1_1049 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_4_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_4_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_4,
      I5 => NlwInverterSignal_REG_1_4_D2_PT_1_IN5,
      O => REG_1_4_D2_PT_1
    );
  REG_1_4_D2_PT_2_1050 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_4_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_4_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_4_D2_PT_2_IN4,
      I5 => REG_1_3,
      O => REG_1_4_D2_PT_2
    );
  REG_1_4_D2_1051 : X_OR3
    port map (
      I0 => REG_1_4_D2_PT_0,
      I1 => REG_1_4_D2_PT_1,
      I2 => REG_1_4_D2_PT_2,
      O => REG_1_4_D2
    );
  REG_1_4_CLKF_1052 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_4_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_4_CLKF_IN1,
      O => REG_1_4_CLKF
    );
  REG_1_4_SETF_1053 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_4_IBUF,
      O => REG_1_4_SETF
    );
  REG_1_4_RSTF_1054 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_4_RSTF_IN2,
      O => REG_1_4_RSTF
    );
  REG_1_5_1055 : X_BUF
    port map (
      I => REG_1_5_Q,
      O => REG_1_5
    );
  REG_1_5_tsimcreated_xor_Q_1056 : X_XOR2
    port map (
      I0 => REG_1_5_D,
      I1 => REG_1_5_Q,
      O => REG_1_5_tsimcreated_xor_Q
    );
  REG_1_5_tsimcreated_set_and_noreset_Q_1057 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_5_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_5_SETF,
      O => REG_1_5_tsimcreated_set_and_noreset_Q
    );
  REG_1_5_tsimcreated_prld_Q_1058 : X_OR2
    port map (
      I0 => REG_1_5_RSTF,
      I1 => PRLD,
      O => REG_1_5_tsimcreated_prld_Q
    );
  REG_1_5_REG : X_FF
    port map (
      I => REG_1_5_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_5_CLKF,
      SET => REG_1_5_tsimcreated_set_and_noreset_Q,
      RST => REG_1_5_tsimcreated_prld_Q,
      O => REG_1_5_Q
    );
  REG_1_5_D_1059 : X_XOR2
    port map (
      I0 => REG_1_5_D1,
      I1 => REG_1_5_D2,
      O => REG_1_5_D
    );
  REG_1_5_D1_1060 : X_ZERO
    port map (
      O => REG_1_5_D1
    );
  REG_1_5_D2_PT_0_1061 : X_AND2
    port map (
      I0 => EXP49_EXP,
      I1 => EXP49_EXP,
      O => REG_1_5_D2_PT_0
    );
  REG_1_5_D2_PT_1_1062 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_5_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_5_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_4,
      I5 => NlwInverterSignal_REG_1_5_D2_PT_1_IN5,
      O => REG_1_5_D2_PT_1
    );
  REG_1_5_D2_PT_2_1063 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_5_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_5_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_5_D2_PT_2_IN4,
      I5 => REG_1_5,
      O => REG_1_5_D2_PT_2
    );
  REG_1_5_D2_1064 : X_OR3
    port map (
      I0 => REG_1_5_D2_PT_0,
      I1 => REG_1_5_D2_PT_1,
      I2 => REG_1_5_D2_PT_2,
      O => REG_1_5_D2
    );
  REG_1_5_CLKF_1065 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_5_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_5_CLKF_IN1,
      O => REG_1_5_CLKF
    );
  REG_1_5_SETF_1066 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_5_IBUF,
      O => REG_1_5_SETF
    );
  REG_1_5_RSTF_1067 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_5_RSTF_IN2,
      O => REG_1_5_RSTF
    );
  REG_1_6_1068 : X_BUF
    port map (
      I => REG_1_6_Q,
      O => REG_1_6
    );
  REG_1_6_tsimcreated_xor_Q_1069 : X_XOR2
    port map (
      I0 => REG_1_6_D,
      I1 => REG_1_6_Q,
      O => REG_1_6_tsimcreated_xor_Q
    );
  REG_1_6_tsimcreated_set_and_noreset_Q_1070 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_6_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_6_SETF,
      O => REG_1_6_tsimcreated_set_and_noreset_Q
    );
  REG_1_6_tsimcreated_prld_Q_1071 : X_OR2
    port map (
      I0 => REG_1_6_RSTF,
      I1 => PRLD,
      O => REG_1_6_tsimcreated_prld_Q
    );
  REG_1_6_REG : X_FF
    port map (
      I => REG_1_6_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_6_CLKF,
      SET => REG_1_6_tsimcreated_set_and_noreset_Q,
      RST => REG_1_6_tsimcreated_prld_Q,
      O => REG_1_6_Q
    );
  REG_1_6_D_1072 : X_XOR2
    port map (
      I0 => REG_1_6_D1,
      I1 => REG_1_6_D2,
      O => REG_1_6_D
    );
  REG_1_6_D1_1073 : X_ZERO
    port map (
      O => REG_1_6_D1
    );
  REG_1_6_D2_PT_0_1074 : X_AND2
    port map (
      I0 => EXP50_EXP,
      I1 => EXP50_EXP,
      O => REG_1_6_D2_PT_0
    );
  REG_1_6_D2_PT_1_1075 : X_AND2
    port map (
      I0 => EXP51_EXP,
      I1 => EXP51_EXP,
      O => REG_1_6_D2_PT_1
    );
  REG_1_6_D2_PT_2_1076 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_6_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_6_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_5,
      I5 => NlwInverterSignal_REG_1_6_D2_PT_2_IN5,
      O => REG_1_6_D2_PT_2
    );
  REG_1_6_D2_PT_3_1077 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_6_D2_PT_3_IN0,
      I1 => NlwInverterSignal_REG_1_6_D2_PT_3_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_6_D2_PT_3_IN4,
      I5 => REG_1_6,
      O => REG_1_6_D2_PT_3
    );
  REG_1_6_D2_1078 : X_OR4
    port map (
      I0 => REG_1_6_D2_PT_0,
      I1 => REG_1_6_D2_PT_1,
      I2 => REG_1_6_D2_PT_2,
      I3 => REG_1_6_D2_PT_3,
      O => REG_1_6_D2
    );
  REG_1_6_CLKF_1079 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_6_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_6_CLKF_IN1,
      O => REG_1_6_CLKF
    );
  REG_1_6_SETF_1080 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_6_IBUF,
      O => REG_1_6_SETF
    );
  REG_1_6_RSTF_1081 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_6_RSTF_IN2,
      O => REG_1_6_RSTF
    );
  REG_1_7_1082 : X_BUF
    port map (
      I => REG_1_7_Q,
      O => REG_1_7
    );
  REG_1_7_tsimcreated_xor_Q_1083 : X_XOR2
    port map (
      I0 => REG_1_7_D,
      I1 => REG_1_7_Q,
      O => REG_1_7_tsimcreated_xor_Q
    );
  REG_1_7_tsimcreated_set_and_noreset_Q_1084 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_7_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_7_SETF,
      O => REG_1_7_tsimcreated_set_and_noreset_Q
    );
  REG_1_7_tsimcreated_prld_Q_1085 : X_OR2
    port map (
      I0 => REG_1_7_RSTF,
      I1 => PRLD,
      O => REG_1_7_tsimcreated_prld_Q
    );
  REG_1_7_REG : X_FF
    port map (
      I => REG_1_7_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_7_CLKF,
      SET => REG_1_7_tsimcreated_set_and_noreset_Q,
      RST => REG_1_7_tsimcreated_prld_Q,
      O => REG_1_7_Q
    );
  REG_1_7_D_1086 : X_XOR2
    port map (
      I0 => REG_1_7_D1,
      I1 => REG_1_7_D2,
      O => REG_1_7_D
    );
  REG_1_7_D1_1087 : X_ZERO
    port map (
      O => REG_1_7_D1
    );
  REG_1_7_D2_PT_0_1088 : X_AND2
    port map (
      I0 => EXP42_EXP,
      I1 => EXP42_EXP,
      O => REG_1_7_D2_PT_0
    );
  REG_1_7_D2_PT_1_1089 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_7_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_7_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_6,
      I5 => NlwInverterSignal_REG_1_7_D2_PT_1_IN5,
      O => REG_1_7_D2_PT_1
    );
  REG_1_7_D2_PT_2_1090 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_7_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_7_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_7_D2_PT_2_IN4,
      I5 => REG_1_7,
      O => REG_1_7_D2_PT_2
    );
  REG_1_7_D2_1091 : X_OR3
    port map (
      I0 => REG_1_7_D2_PT_0,
      I1 => REG_1_7_D2_PT_1,
      I2 => REG_1_7_D2_PT_2,
      O => REG_1_7_D2
    );
  REG_1_7_CLKF_1092 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_7_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_7_CLKF_IN1,
      O => REG_1_7_CLKF
    );
  REG_1_7_SETF_1093 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_7_IBUF,
      O => REG_1_7_SETF
    );
  REG_1_7_RSTF_1094 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_7_RSTF_IN2,
      O => REG_1_7_RSTF
    );
  REG_1_8_1095 : X_BUF
    port map (
      I => REG_1_8_Q,
      O => REG_1_8
    );
  REG_1_8_tsimcreated_xor_Q_1096 : X_XOR2
    port map (
      I0 => REG_1_8_D,
      I1 => REG_1_8_Q,
      O => REG_1_8_tsimcreated_xor_Q
    );
  REG_1_8_tsimcreated_set_and_noreset_Q_1097 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_8_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_8_SETF,
      O => REG_1_8_tsimcreated_set_and_noreset_Q
    );
  REG_1_8_tsimcreated_prld_Q_1098 : X_OR2
    port map (
      I0 => REG_1_8_RSTF,
      I1 => PRLD,
      O => REG_1_8_tsimcreated_prld_Q
    );
  REG_1_8_REG : X_FF
    port map (
      I => REG_1_8_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_8_CLKF,
      SET => REG_1_8_tsimcreated_set_and_noreset_Q,
      RST => REG_1_8_tsimcreated_prld_Q,
      O => REG_1_8_Q
    );
  REG_1_8_D_1099 : X_XOR2
    port map (
      I0 => REG_1_8_D1,
      I1 => REG_1_8_D2,
      O => REG_1_8_D
    );
  REG_1_8_D1_1100 : X_ZERO
    port map (
      O => REG_1_8_D1
    );
  REG_1_8_D2_PT_0_1101 : X_AND2
    port map (
      I0 => EXP47_EXP,
      I1 => EXP47_EXP,
      O => REG_1_8_D2_PT_0
    );
  REG_1_8_D2_PT_1_1102 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_8_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_8_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_7,
      I5 => NlwInverterSignal_REG_1_8_D2_PT_1_IN5,
      O => REG_1_8_D2_PT_1
    );
  REG_1_8_D2_PT_2_1103 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_8_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_8_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_8_D2_PT_2_IN4,
      I5 => REG_1_8,
      O => REG_1_8_D2_PT_2
    );
  REG_1_8_D2_1104 : X_OR3
    port map (
      I0 => REG_1_8_D2_PT_0,
      I1 => REG_1_8_D2_PT_1,
      I2 => REG_1_8_D2_PT_2,
      O => REG_1_8_D2
    );
  REG_1_8_CLKF_1105 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_8_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_8_CLKF_IN1,
      O => REG_1_8_CLKF
    );
  REG_1_8_SETF_1106 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_8_IBUF,
      O => REG_1_8_SETF
    );
  REG_1_8_RSTF_1107 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_8_RSTF_IN2,
      O => REG_1_8_RSTF
    );
  REG_1_9_1108 : X_BUF
    port map (
      I => REG_1_9_Q,
      O => REG_1_9
    );
  REG_1_9_tsimcreated_xor_Q_1109 : X_XOR2
    port map (
      I0 => REG_1_9_D,
      I1 => REG_1_9_Q,
      O => REG_1_9_tsimcreated_xor_Q
    );
  REG_1_9_tsimcreated_set_and_noreset_Q_1110 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_9_tsimcreated_set_and_noreset_IN0,
      I1 => REG_1_9_SETF,
      O => REG_1_9_tsimcreated_set_and_noreset_Q
    );
  REG_1_9_tsimcreated_prld_Q_1111 : X_OR2
    port map (
      I0 => REG_1_9_RSTF,
      I1 => PRLD,
      O => REG_1_9_tsimcreated_prld_Q
    );
  REG_1_9_REG : X_FF
    port map (
      I => REG_1_9_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => REG_1_9_CLKF,
      SET => REG_1_9_tsimcreated_set_and_noreset_Q,
      RST => REG_1_9_tsimcreated_prld_Q,
      O => REG_1_9_Q
    );
  REG_1_9_D_1112 : X_XOR2
    port map (
      I0 => REG_1_9_D1,
      I1 => REG_1_9_D2,
      O => REG_1_9_D
    );
  REG_1_9_D1_1113 : X_ZERO
    port map (
      O => REG_1_9_D1
    );
  REG_1_9_D2_PT_0_1114 : X_AND2
    port map (
      I0 => EXP44_EXP,
      I1 => EXP44_EXP,
      O => REG_1_9_D2_PT_0
    );
  REG_1_9_D2_PT_1_1115 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_9_D2_PT_1_IN0,
      I1 => NlwInverterSignal_REG_1_9_D2_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_9,
      I5 => NlwInverterSignal_REG_1_9_D2_PT_1_IN5,
      O => REG_1_9_D2_PT_1
    );
  REG_1_9_D2_PT_2_1116 : X_AND6
    port map (
      I0 => NlwInverterSignal_REG_1_9_D2_PT_2_IN0,
      I1 => NlwInverterSignal_REG_1_9_D2_PT_2_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_REG_1_9_D2_PT_2_IN4,
      I5 => REG_1_8,
      O => REG_1_9_D2_PT_2
    );
  REG_1_9_D2_1117 : X_OR3
    port map (
      I0 => REG_1_9_D2_PT_0,
      I1 => REG_1_9_D2_PT_1,
      I2 => REG_1_9_D2_PT_2,
      O => REG_1_9_D2
    );
  REG_1_9_CLKF_1118 : X_AND2
    port map (
      I0 => NlwInverterSignal_REG_1_9_CLKF_IN0,
      I1 => NlwInverterSignal_REG_1_9_CLKF_IN1,
      O => REG_1_9_CLKF
    );
  REG_1_9_SETF_1119 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => DIN_9_IBUF,
      O => REG_1_9_SETF
    );
  REG_1_9_RSTF_1120 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => writeBufId(0),
      I2 => NlwInverterSignal_REG_1_9_RSTF_IN2,
      O => REG_1_9_RSTF
    );
  DOUT_OBUFE_1121 : X_BUF
    port map (
      I => DOUT_OBUFE_Q,
      O => DOUT_OBUFE
    );
  DOUT_OBUFE_EXP_1122 : X_BUF
    port map (
      I => DOUT_OBUFE_EXP_tsimrenamed_net_Q,
      O => DOUT_OBUFE_EXP
    );
  DOUT_OBUFE_OE_1123 : X_BUF
    port map (
      I => DOUT_OBUFE_BUFOE_OUT,
      O => DOUT_OBUFE_OE
    );
  DOUT_OBUFE_BUFOE_OUT_1124 : X_BUF
    port map (
      I => DOUT_OBUFE_TRST,
      O => DOUT_OBUFE_BUFOE_OUT
    );
  DOUT_OBUFE_Q_1125 : X_BUF
    port map (
      I => DOUT_OBUFE_D,
      O => DOUT_OBUFE_Q
    );
  DOUT_OBUFE_D_1126 : X_XOR2
    port map (
      I0 => DOUT_OBUFE_D1,
      I1 => DOUT_OBUFE_D2,
      O => DOUT_OBUFE_D
    );
  DOUT_OBUFE_D1_1127 : X_ZERO
    port map (
      O => DOUT_OBUFE_D1
    );
  DOUT_OBUFE_D2_PT_0_1128 : X_AND2
    port map (
      I0 => readBufId(0),
      I1 => REG_1_31,
      O => DOUT_OBUFE_D2_PT_0
    );
  DOUT_OBUFE_D2_PT_1_1129 : X_AND2
    port map (
      I0 => NlwInverterSignal_DOUT_OBUFE_D2_PT_1_IN0,
      I1 => REG_0_31,
      O => DOUT_OBUFE_D2_PT_1
    );
  DOUT_OBUFE_D2_1130 : X_OR2
    port map (
      I0 => DOUT_OBUFE_D2_PT_0,
      I1 => DOUT_OBUFE_D2_PT_1,
      O => DOUT_OBUFE_D2
    );
  DOUT_OBUFE_TRST_1131 : X_AND2
    port map (
      I0 => NlwInverterSignal_DOUT_OBUFE_TRST_IN0,
      I1 => nINIT_B_IBUF,
      O => DOUT_OBUFE_TRST
    );
  DOUT_OBUFE_EXP_PT_0_1132 : X_AND7
    port map (
      I0 => NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_30_IBUF,
      I6 => NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN6,
      O => DOUT_OBUFE_EXP_PT_0
    );
  DOUT_OBUFE_EXP_PT_1_1133 : X_AND7
    port map (
      I0 => NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN5,
      I6 => REG_1_30,
      O => DOUT_OBUFE_EXP_PT_1
    );
  DOUT_OBUFE_EXP_tsimrenamed_net_Q_1134 : X_OR2
    port map (
      I0 => DOUT_OBUFE_EXP_PT_0,
      I1 => DOUT_OBUFE_EXP_PT_1,
      O => DOUT_OBUFE_EXP_tsimrenamed_net_Q
    );
  state_0_Q_1135 : X_BUF
    port map (
      I => state_0_Q,
      O => state(0)
    );
  state_0_EXP_1136 : X_BUF
    port map (
      I => state_0_EXP_tsimrenamed_net_Q,
      O => state_0_EXP
    );
  state_0_tsimcreated_prld_Q_1137 : X_OR2
    port map (
      I0 => state_0_RSTF,
      I1 => PRLD,
      O => state_0_tsimcreated_prld_Q
    );
  state_0_REG : X_FF
    port map (
      I => state_0_D,
      CE => Vcc,
      CLK => state_0_CLKF,
      SET => Gnd,
      RST => state_0_tsimcreated_prld_Q,
      O => state_0_Q
    );
  state_0_D_1138 : X_XOR2
    port map (
      I0 => state_0_D1,
      I1 => state_0_D2,
      O => state_0_D
    );
  state_0_D1_1139 : X_ZERO
    port map (
      O => state_0_D1
    );
  state_0_D2_1140 : X_AND2
    port map (
      I0 => next_state(0),
      I1 => next_state(0),
      O => state_0_D2
    );
  state_0_CLKF_1141 : X_AND2
    port map (
      I0 => SCLK,
      I1 => SCLK,
      O => state_0_CLKF
    );
  state_0_RSTF_1142 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => state_0_RSTF
    );
  state_0_EXP_PT_0_1143 : X_AND7
    port map (
      I0 => NlwInverterSignal_state_0_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_state_0_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_state_0_EXP_PT_0_IN4,
      I5 => DIN_19_IBUF,
      I6 => NlwInverterSignal_state_0_EXP_PT_0_IN6,
      O => state_0_EXP_PT_0
    );
  state_0_EXP_PT_1_1144 : X_AND7
    port map (
      I0 => NlwInverterSignal_state_0_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_state_0_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_state_0_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_state_0_EXP_PT_1_IN5,
      I6 => REG_0_19,
      O => state_0_EXP_PT_1
    );
  state_0_EXP_tsimrenamed_net_Q_1145 : X_OR2
    port map (
      I0 => state_0_EXP_PT_0,
      I1 => state_0_EXP_PT_1,
      O => state_0_EXP_tsimrenamed_net_Q
    );
  state_1_Q_1146 : X_BUF
    port map (
      I => state_1_Q,
      O => state(1)
    );
  state_1_EXP_1147 : X_BUF
    port map (
      I => state_1_EXP_tsimrenamed_net_Q,
      O => state_1_EXP
    );
  state_1_tsimcreated_prld_Q_1148 : X_OR2
    port map (
      I0 => state_1_RSTF,
      I1 => PRLD,
      O => state_1_tsimcreated_prld_Q
    );
  state_1_REG : X_FF
    port map (
      I => state_1_D,
      CE => Vcc,
      CLK => state_1_CLKF,
      SET => Gnd,
      RST => state_1_tsimcreated_prld_Q,
      O => state_1_Q
    );
  state_1_D_1149 : X_XOR2
    port map (
      I0 => state_1_D1,
      I1 => state_1_D2,
      O => state_1_D
    );
  state_1_D1_1150 : X_ZERO
    port map (
      O => state_1_D1
    );
  state_1_D2_1151 : X_AND2
    port map (
      I0 => next_state(1),
      I1 => next_state(1),
      O => state_1_D2
    );
  state_1_CLKF_1152 : X_AND2
    port map (
      I0 => SCLK,
      I1 => SCLK,
      O => state_1_CLKF
    );
  state_1_RSTF_1153 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => state_1_RSTF
    );
  state_1_EXP_PT_0_1154 : X_AND7
    port map (
      I0 => NlwInverterSignal_state_1_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_state_1_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_state_1_EXP_PT_0_IN4,
      I5 => DIN_25_IBUF,
      I6 => NlwInverterSignal_state_1_EXP_PT_0_IN6,
      O => state_1_EXP_PT_0
    );
  state_1_EXP_PT_1_1155 : X_AND7
    port map (
      I0 => NlwInverterSignal_state_1_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_state_1_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_state_1_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_state_1_EXP_PT_1_IN5,
      I6 => REG_0_25,
      O => state_1_EXP_PT_1
    );
  state_1_EXP_tsimrenamed_net_Q_1156 : X_OR2
    port map (
      I0 => state_1_EXP_PT_0,
      I1 => state_1_EXP_PT_1,
      O => state_1_EXP_tsimrenamed_net_Q
    );
  CLK_SCALE_1_Q_1157 : X_BUF
    port map (
      I => CLK_SCALE_1_Q,
      O => CLK_SCALE(1)
    );
  CLK_SCALE_1_EXP_1158 : X_BUF
    port map (
      I => CLK_SCALE_1_EXP_tsimrenamed_net_Q,
      O => CLK_SCALE_1_EXP
    );
  CLK_SCALE_1_Q_1159 : X_BUF
    port map (
      I => CLK_SCALE_1_D,
      O => CLK_SCALE_1_Q
    );
  CLK_SCALE_1_D_1160 : X_XOR2
    port map (
      I0 => CLK_SCALE_1_D1,
      I1 => CLK_SCALE_1_D2,
      O => CLK_SCALE_1_D
    );
  CLK_SCALE_1_D1_1161 : X_ZERO
    port map (
      O => CLK_SCALE_1_D1
    );
  CLK_SCALE_1_D2_PT_0_1162 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_1_D2_PT_0_IN0,
      I1 => LOAD_PRESCALER_IBUF,
      I2 => CCLK_PRESCALER_1_IBUF,
      O => CLK_SCALE_1_D2_PT_0
    );
  CLK_SCALE_1_D2_PT_1_1163 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN0,
      I1 => NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN1,
      I2 => CLK_SCALE(1),
      O => CLK_SCALE_1_D2_PT_1
    );
  CLK_SCALE_1_D2_PT_2_1164 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_1_D2_PT_2_IN0,
      I1 => CLK_SCALE(1),
      I2 => CCLK_PRESCALER_1_IBUF,
      O => CLK_SCALE_1_D2_PT_2
    );
  CLK_SCALE_1_D2_1165 : X_OR3
    port map (
      I0 => CLK_SCALE_1_D2_PT_0,
      I1 => CLK_SCALE_1_D2_PT_1,
      I2 => CLK_SCALE_1_D2_PT_2,
      O => CLK_SCALE_1_D2
    );
  CLK_SCALE_1_EXP_tsimrenamed_net_Q_1166 : X_AND4
    port map (
      I0 => RES_IBUF,
      I1 => NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN1,
      I2 => count(1),
      I3 => NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN3,
      O => CLK_SCALE_1_EXP_tsimrenamed_net_Q
    );
  CLK_SCALE_2_Q_1167 : X_BUF
    port map (
      I => CLK_SCALE_2_Q,
      O => CLK_SCALE(2)
    );
  CLK_SCALE_2_EXP_1168 : X_BUF
    port map (
      I => CLK_SCALE_2_EXP_tsimrenamed_net_Q,
      O => CLK_SCALE_2_EXP
    );
  CLK_SCALE_2_Q_1169 : X_BUF
    port map (
      I => CLK_SCALE_2_D,
      O => CLK_SCALE_2_Q
    );
  CLK_SCALE_2_D_1170 : X_XOR2
    port map (
      I0 => CLK_SCALE_2_D1,
      I1 => CLK_SCALE_2_D2,
      O => CLK_SCALE_2_D
    );
  CLK_SCALE_2_D1_1171 : X_ZERO
    port map (
      O => CLK_SCALE_2_D1
    );
  CLK_SCALE_2_D2_PT_0_1172 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_2_D2_PT_0_IN0,
      I1 => LOAD_PRESCALER_IBUF,
      I2 => CCLK_PRESCALER_2_IBUF,
      O => CLK_SCALE_2_D2_PT_0
    );
  CLK_SCALE_2_D2_PT_1_1173 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN0,
      I1 => NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN1,
      I2 => CLK_SCALE(2),
      O => CLK_SCALE_2_D2_PT_1
    );
  CLK_SCALE_2_D2_PT_2_1174 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_2_D2_PT_2_IN0,
      I1 => CLK_SCALE(2),
      I2 => CCLK_PRESCALER_2_IBUF,
      O => CLK_SCALE_2_D2_PT_2
    );
  CLK_SCALE_2_D2_1175 : X_OR3
    port map (
      I0 => CLK_SCALE_2_D2_PT_0,
      I1 => CLK_SCALE_2_D2_PT_1,
      I2 => CLK_SCALE_2_D2_PT_2,
      O => CLK_SCALE_2_D2
    );
  CLK_SCALE_2_EXP_PT_0_1176 : X_AND7
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN1,
      I2 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN2,
      I3 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN3,
      I4 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN4,
      I5 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN5,
      I6 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN6,
      O => CLK_SCALE_2_EXP_PT_0
    );
  CLK_SCALE_2_EXP_PT_1_1177 : X_AND7
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN1,
      I2 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN2,
      I3 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN5,
      I6 => CLK_SCALE(5),
      O => CLK_SCALE_2_EXP_PT_1
    );
  CLK_SCALE_2_EXP_tsimrenamed_net_Q_1178 : X_OR2
    port map (
      I0 => CLK_SCALE_2_EXP_PT_0,
      I1 => CLK_SCALE_2_EXP_PT_1,
      O => CLK_SCALE_2_EXP_tsimrenamed_net_Q
    );
  CLK_SCALE_3_Q_1179 : X_BUF
    port map (
      I => CLK_SCALE_3_Q,
      O => CLK_SCALE(3)
    );
  CLK_SCALE_3_Q_1180 : X_BUF
    port map (
      I => CLK_SCALE_3_D,
      O => CLK_SCALE_3_Q
    );
  CLK_SCALE_3_D_1181 : X_XOR2
    port map (
      I0 => CLK_SCALE_3_D1,
      I1 => CLK_SCALE_3_D2,
      O => CLK_SCALE_3_D
    );
  CLK_SCALE_3_D1_1182 : X_ZERO
    port map (
      O => CLK_SCALE_3_D1
    );
  CLK_SCALE_3_D2_PT_0_1183 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_3_D2_PT_0_IN0,
      I1 => LOAD_PRESCALER_IBUF,
      I2 => CCLK_PRESCALER_3_IBUF,
      O => CLK_SCALE_3_D2_PT_0
    );
  CLK_SCALE_3_D2_PT_1_1184 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN0,
      I1 => NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN1,
      I2 => CLK_SCALE(3),
      O => CLK_SCALE_3_D2_PT_1
    );
  CLK_SCALE_3_D2_PT_2_1185 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_3_D2_PT_2_IN0,
      I1 => CLK_SCALE(3),
      I2 => CCLK_PRESCALER_3_IBUF,
      O => CLK_SCALE_3_D2_PT_2
    );
  CLK_SCALE_3_D2_1186 : X_OR3
    port map (
      I0 => CLK_SCALE_3_D2_PT_0,
      I1 => CLK_SCALE_3_D2_PT_1,
      I2 => CLK_SCALE_3_D2_PT_2,
      O => CLK_SCALE_3_D2
    );
  CLK_SCALE_4_Q_1187 : X_BUF
    port map (
      I => CLK_SCALE_4_Q,
      O => CLK_SCALE(4)
    );
  CLK_SCALE_4_Q_1188 : X_BUF
    port map (
      I => CLK_SCALE_4_D,
      O => CLK_SCALE_4_Q
    );
  CLK_SCALE_4_D_1189 : X_XOR2
    port map (
      I0 => CLK_SCALE_4_D1,
      I1 => CLK_SCALE_4_D2,
      O => CLK_SCALE_4_D
    );
  CLK_SCALE_4_D1_1190 : X_ZERO
    port map (
      O => CLK_SCALE_4_D1
    );
  CLK_SCALE_4_D2_PT_0_1191 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_4_D2_PT_0_IN0,
      I1 => LOAD_PRESCALER_IBUF,
      I2 => CCLK_PRESCALER_4_IBUF,
      O => CLK_SCALE_4_D2_PT_0
    );
  CLK_SCALE_4_D2_PT_1_1192 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN0,
      I1 => NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN1,
      I2 => CLK_SCALE(4),
      O => CLK_SCALE_4_D2_PT_1
    );
  CLK_SCALE_4_D2_PT_2_1193 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_4_D2_PT_2_IN0,
      I1 => CLK_SCALE(4),
      I2 => CCLK_PRESCALER_4_IBUF,
      O => CLK_SCALE_4_D2_PT_2
    );
  CLK_SCALE_4_D2_1194 : X_OR3
    port map (
      I0 => CLK_SCALE_4_D2_PT_0,
      I1 => CLK_SCALE_4_D2_PT_1,
      I2 => CLK_SCALE_4_D2_PT_2,
      O => CLK_SCALE_4_D2
    );
  CLK_SCALE_5_Q_1195 : X_BUF
    port map (
      I => CLK_SCALE_5_Q,
      O => CLK_SCALE(5)
    );
  CLK_SCALE_5_Q_1196 : X_BUF
    port map (
      I => CLK_SCALE_5_D,
      O => CLK_SCALE_5_Q
    );
  CLK_SCALE_5_D_1197 : X_XOR2
    port map (
      I0 => CLK_SCALE_5_D1,
      I1 => CLK_SCALE_5_D2,
      O => CLK_SCALE_5_D
    );
  CLK_SCALE_5_D1_1198 : X_ZERO
    port map (
      O => CLK_SCALE_5_D1
    );
  CLK_SCALE_5_D2_PT_0_1199 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_5_D2_PT_0_IN0,
      I1 => LOAD_PRESCALER_IBUF,
      I2 => CCLK_PRESCALER_5_IBUF,
      O => CLK_SCALE_5_D2_PT_0
    );
  CLK_SCALE_5_D2_PT_1_1200 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN0,
      I1 => NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN1,
      I2 => CLK_SCALE(5),
      O => CLK_SCALE_5_D2_PT_1
    );
  CLK_SCALE_5_D2_PT_2_1201 : X_AND3
    port map (
      I0 => NlwInverterSignal_CLK_SCALE_5_D2_PT_2_IN0,
      I1 => CLK_SCALE(5),
      I2 => CCLK_PRESCALER_5_IBUF,
      O => CLK_SCALE_5_D2_PT_2
    );
  CLK_SCALE_5_D2_1202 : X_OR3
    port map (
      I0 => CLK_SCALE_5_D2_PT_0,
      I1 => CLK_SCALE_5_D2_PT_1,
      I2 => CLK_SCALE_5_D2_PT_2,
      O => CLK_SCALE_5_D2
    );
  tempID_0_Q_1203 : X_BUF
    port map (
      I => tempID_0_Q,
      O => tempID(0)
    );
  tempID_0_tsimcreated_xor_Q_1204 : X_XOR2
    port map (
      I0 => tempID_0_D,
      I1 => tempID_0_Q,
      O => tempID_0_tsimcreated_xor_Q
    );
  tempID_0_REG : X_FF
    port map (
      I => tempID_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => tempID_0_CLKF,
      SET => Gnd,
      RST => PRLD,
      O => tempID_0_Q
    );
  tempID_0_D_1205 : X_XOR2
    port map (
      I0 => tempID_0_D1,
      I1 => tempID_0_D2,
      O => tempID_0_D
    );
  tempID_0_D1_1206 : X_ZERO
    port map (
      O => tempID_0_D1
    );
  tempID_0_D2_PT_0_1207 : X_AND16
    port map (
      I0 => NlwInverterSignal_tempID_0_D2_PT_0_IN0,
      I1 => NlwInverterSignal_tempID_0_D2_PT_0_IN1,
      I2 => buf_depth(0),
      I3 => NlwInverterSignal_tempID_0_D2_PT_0_IN3,
      I4 => NlwInverterSignal_tempID_0_D2_PT_0_IN4,
      I5 => NlwInverterSignal_tempID_0_D2_PT_0_IN5,
      I6 => NlwInverterSignal_tempID_0_D2_PT_0_IN6,
      I7 => NlwInverterSignal_tempID_0_D2_PT_0_IN7,
      I8 => SHIFT_EN,
      I9 => readBufId(0),
      I10 => NlwInverterSignal_tempID_0_D2_PT_0_IN10,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => tempID_0_D2_PT_0
    );
  tempID_0_D2_PT_1_1208 : X_AND16
    port map (
      I0 => NlwInverterSignal_tempID_0_D2_PT_1_IN0,
      I1 => NlwInverterSignal_tempID_0_D2_PT_1_IN1,
      I2 => buf_depth(0),
      I3 => NlwInverterSignal_tempID_0_D2_PT_1_IN3,
      I4 => NlwInverterSignal_tempID_0_D2_PT_1_IN4,
      I5 => NlwInverterSignal_tempID_0_D2_PT_1_IN5,
      I6 => NlwInverterSignal_tempID_0_D2_PT_1_IN6,
      I7 => NlwInverterSignal_tempID_0_D2_PT_1_IN7,
      I8 => SHIFT_EN,
      I9 => NlwInverterSignal_tempID_0_D2_PT_1_IN9,
      I10 => tempID(0),
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => tempID_0_D2_PT_1
    );
  tempID_0_D2_PT_2_1209 : X_AND16
    port map (
      I0 => NlwInverterSignal_tempID_0_D2_PT_2_IN0,
      I1 => NlwInverterSignal_tempID_0_D2_PT_2_IN1,
      I2 => buf_depth(1),
      I3 => NlwInverterSignal_tempID_0_D2_PT_2_IN3,
      I4 => NlwInverterSignal_tempID_0_D2_PT_2_IN4,
      I5 => NlwInverterSignal_tempID_0_D2_PT_2_IN5,
      I6 => NlwInverterSignal_tempID_0_D2_PT_2_IN6,
      I7 => NlwInverterSignal_tempID_0_D2_PT_2_IN7,
      I8 => SHIFT_EN,
      I9 => readBufId(0),
      I10 => NlwInverterSignal_tempID_0_D2_PT_2_IN10,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => tempID_0_D2_PT_2
    );
  tempID_0_D2_PT_3_1210 : X_AND16
    port map (
      I0 => NlwInverterSignal_tempID_0_D2_PT_3_IN0,
      I1 => NlwInverterSignal_tempID_0_D2_PT_3_IN1,
      I2 => buf_depth(1),
      I3 => NlwInverterSignal_tempID_0_D2_PT_3_IN3,
      I4 => NlwInverterSignal_tempID_0_D2_PT_3_IN4,
      I5 => NlwInverterSignal_tempID_0_D2_PT_3_IN5,
      I6 => NlwInverterSignal_tempID_0_D2_PT_3_IN6,
      I7 => NlwInverterSignal_tempID_0_D2_PT_3_IN7,
      I8 => SHIFT_EN,
      I9 => NlwInverterSignal_tempID_0_D2_PT_3_IN9,
      I10 => tempID(0),
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => tempID_0_D2_PT_3
    );
  tempID_0_D2_1211 : X_OR4
    port map (
      I0 => tempID_0_D2_PT_0,
      I1 => tempID_0_D2_PT_1,
      I2 => tempID_0_D2_PT_2,
      I3 => tempID_0_D2_PT_3,
      O => tempID_0_D2
    );
  tempID_0_CLKF_1212 : X_AND2
    port map (
      I0 => NlwInverterSignal_tempID_0_CLKF_IN0,
      I1 => NlwInverterSignal_tempID_0_CLKF_IN1,
      O => tempID_0_CLKF
    );
  BUF_IS_EMPTY_OBUF_Q_1213 : X_BUF
    port map (
      I => BUF_IS_EMPTY_OBUF_Q_0,
      O => BUF_IS_EMPTY_OBUF_Q
    );
  BUF_IS_EMPTY_OBUF_EXP_1214 : X_BUF
    port map (
      I => BUF_IS_EMPTY_OBUF_EXP_tsimrenamed_net_Q,
      O => BUF_IS_EMPTY_OBUF_EXP
    );
  BUF_IS_EMPTY_OBUF_Q_1215 : X_BUF
    port map (
      I => BUF_IS_EMPTY_OBUF_D,
      O => BUF_IS_EMPTY_OBUF_Q_0
    );
  BUF_IS_EMPTY_OBUF_D_1216 : X_XOR2
    port map (
      I0 => BUF_IS_EMPTY_OBUF_D1,
      I1 => BUF_IS_EMPTY_OBUF_D2,
      O => BUF_IS_EMPTY_OBUF_D
    );
  BUF_IS_EMPTY_OBUF_D1_1217 : X_ZERO
    port map (
      O => BUF_IS_EMPTY_OBUF_D1
    );
  BUF_IS_EMPTY_OBUF_D2_1218 : X_AND7
    port map (
      I0 => buf_depth(0),
      I1 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN1,
      I2 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN2,
      I3 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN3,
      I4 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN4,
      I5 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN5,
      I6 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN6,
      O => BUF_IS_EMPTY_OBUF_D2
    );
  BUF_IS_EMPTY_OBUF_EXP_PT_0_1219 : X_AND2
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => LOAD_SREG_IBUF,
      O => BUF_IS_EMPTY_OBUF_EXP_PT_0
    );
  BUF_IS_EMPTY_OBUF_EXP_PT_1_1220 : X_AND2
    port map (
      I0 => SHIFT_CNT(1),
      I1 => SHIFT_CNT(1),
      O => BUF_IS_EMPTY_OBUF_EXP_PT_1
    );
  BUF_IS_EMPTY_OBUF_EXP_PT_2_1221 : X_AND2
    port map (
      I0 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN1,
      O => BUF_IS_EMPTY_OBUF_EXP_PT_2
    );
  BUF_IS_EMPTY_OBUF_EXP_PT_3_1222 : X_AND5
    port map (
      I0 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN0,
      I1 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN1,
      I2 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN2,
      I3 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN3,
      I4 => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN4,
      O => BUF_IS_EMPTY_OBUF_EXP_PT_3
    );
  BUF_IS_EMPTY_OBUF_EXP_tsimrenamed_net_Q_1223 : X_OR4
    port map (
      I0 => BUF_IS_EMPTY_OBUF_EXP_PT_0,
      I1 => BUF_IS_EMPTY_OBUF_EXP_PT_1,
      I2 => BUF_IS_EMPTY_OBUF_EXP_PT_2,
      I3 => BUF_IS_EMPTY_OBUF_EXP_PT_3,
      O => BUF_IS_EMPTY_OBUF_EXP_tsimrenamed_net_Q
    );
  SHIFT_EN_1224 : X_BUF
    port map (
      I => SHIFT_EN_Q,
      O => SHIFT_EN
    );
  SHIFT_EN_EXP_1225 : X_BUF
    port map (
      I => SHIFT_EN_EXP_tsimrenamed_net_Q,
      O => SHIFT_EN_EXP
    );
  SHIFT_EN_tsimcreated_set_and_noreset_Q_1226 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_EN_tsimcreated_set_and_noreset_IN0,
      I1 => SHIFT_EN_SETF,
      O => SHIFT_EN_tsimcreated_set_and_noreset_Q
    );
  SHIFT_EN_tsimcreated_prld_Q_1227 : X_OR2
    port map (
      I0 => SHIFT_EN_RSTF,
      I1 => PRLD,
      O => SHIFT_EN_tsimcreated_prld_Q
    );
  SHIFT_EN_REG : X_FF
    port map (
      I => SHIFT_EN_D,
      CE => Vcc,
      CLK => SHIFT_EN_CLKF,
      SET => SHIFT_EN_tsimcreated_set_and_noreset_Q,
      RST => SHIFT_EN_tsimcreated_prld_Q,
      O => SHIFT_EN_Q
    );
  SHIFT_EN_D_1228 : X_XOR2
    port map (
      I0 => SHIFT_EN_D1,
      I1 => SHIFT_EN_D2,
      O => SHIFT_EN_D
    );
  SHIFT_EN_D1_1229 : X_ZERO
    port map (
      O => SHIFT_EN_D1
    );
  SHIFT_EN_D2_1230 : X_ZERO
    port map (
      O => SHIFT_EN_D2
    );
  SHIFT_EN_CLKF_1231 : X_ZERO
    port map (
      O => SHIFT_EN_CLKF
    );
  SHIFT_EN_SETF_1232 : X_AND3
    port map (
      I0 => NlwInverterSignal_SHIFT_EN_SETF_IN0,
      I1 => NlwInverterSignal_SHIFT_EN_SETF_IN1,
      I2 => state(1),
      O => SHIFT_EN_SETF
    );
  SHIFT_EN_RSTF_1233 : X_AND2
    port map (
      I0 => NlwInverterSignal_SHIFT_EN_RSTF_IN0,
      I1 => NlwInverterSignal_SHIFT_EN_RSTF_IN1,
      O => SHIFT_EN_RSTF
    );
  SHIFT_EN_EXP_PT_0_1234 : X_AND7
    port map (
      I0 => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN4,
      I5 => DIN_11_IBUF,
      I6 => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN6,
      O => SHIFT_EN_EXP_PT_0
    );
  SHIFT_EN_EXP_PT_1_1235 : X_AND7
    port map (
      I0 => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN5,
      I6 => REG_0_11,
      O => SHIFT_EN_EXP_PT_1
    );
  SHIFT_EN_EXP_tsimrenamed_net_Q_1236 : X_OR2
    port map (
      I0 => SHIFT_EN_EXP_PT_0,
      I1 => SHIFT_EN_EXP_PT_1,
      O => SHIFT_EN_EXP_tsimrenamed_net_Q
    );
  next_state_0_Q_1237 : X_BUF
    port map (
      I => next_state_0_Q,
      O => next_state(0)
    );
  next_state_0_tsimcreated_set_and_noreset_Q_1238 : X_AND2
    port map (
      I0 => NlwInverterSignal_next_state_0_tsimcreated_set_and_noreset_IN0,
      I1 => next_state_0_SETF,
      O => next_state_0_tsimcreated_set_and_noreset_Q
    );
  next_state_0_tsimcreated_prld_Q_1239 : X_OR2
    port map (
      I0 => next_state_0_RSTF,
      I1 => PRLD,
      O => next_state_0_tsimcreated_prld_Q
    );
  next_state_0_REG : X_FF
    port map (
      I => next_state_0_D,
      CE => Vcc,
      CLK => next_state_0_CLKF,
      SET => next_state_0_tsimcreated_set_and_noreset_Q,
      RST => next_state_0_tsimcreated_prld_Q,
      O => next_state_0_Q
    );
  next_state_0_D_1240 : X_XOR2
    port map (
      I0 => next_state_0_D1,
      I1 => next_state_0_D2,
      O => next_state_0_D
    );
  next_state_0_D1_1241 : X_ZERO
    port map (
      O => next_state_0_D1
    );
  next_state_0_D2_1242 : X_ZERO
    port map (
      O => next_state_0_D2
    );
  next_state_0_CLKF_1243 : X_ZERO
    port map (
      O => next_state_0_CLKF
    );
  next_state_0_SETF_1244 : X_AND4
    port map (
      I0 => NlwInverterSignal_next_state_0_SETF_IN0,
      I1 => NlwInverterSignal_next_state_0_SETF_IN1,
      I2 => NlwInverterSignal_next_state_0_SETF_IN2,
      I3 => NlwInverterSignal_next_state_0_SETF_IN3,
      O => next_state_0_SETF
    );
  next_state_0_RSTF_1245 : X_AND2
    port map (
      I0 => next_state_0_next_state_0_RSTF_UIM,
      I1 => next_state_0_next_state_0_RSTF_UIM,
      O => next_state_0_RSTF
    );
  next_state_1_Q_1246 : X_BUF
    port map (
      I => next_state_1_Q,
      O => next_state(1)
    );
  next_state_1_tsimcreated_set_and_noreset_Q_1247 : X_AND2
    port map (
      I0 => NlwInverterSignal_next_state_1_tsimcreated_set_and_noreset_IN0,
      I1 => next_state_1_SETF,
      O => next_state_1_tsimcreated_set_and_noreset_Q
    );
  next_state_1_tsimcreated_prld_Q_1248 : X_OR2
    port map (
      I0 => next_state_1_RSTF,
      I1 => PRLD,
      O => next_state_1_tsimcreated_prld_Q
    );
  next_state_1_REG : X_FF
    port map (
      I => next_state_1_D,
      CE => Vcc,
      CLK => next_state_1_CLKF,
      SET => next_state_1_tsimcreated_set_and_noreset_Q,
      RST => next_state_1_tsimcreated_prld_Q,
      O => next_state_1_Q
    );
  next_state_1_D_1249 : X_XOR2
    port map (
      I0 => next_state_1_D1,
      I1 => next_state_1_D2,
      O => next_state_1_D
    );
  next_state_1_D1_1250 : X_ZERO
    port map (
      O => next_state_1_D1
    );
  next_state_1_D2_1251 : X_ZERO
    port map (
      O => next_state_1_D2
    );
  next_state_1_CLKF_1252 : X_ZERO
    port map (
      O => next_state_1_CLKF
    );
  next_state_1_SETF_1253 : X_AND2
    port map (
      I0 => SHIFT_EN_SHIFT_EN_RSTF_INT_UIM,
      I1 => NlwInverterSignal_next_state_1_SETF_IN1,
      O => next_state_1_SETF
    );
  next_state_1_RSTF_1254 : X_AND2
    port map (
      I0 => next_state_1_next_state_1_RSTF_UIM,
      I1 => next_state_1_next_state_1_RSTF_UIM,
      O => next_state_1_RSTF
    );
  CCLK_OBUF_1255 : X_BUF
    port map (
      I => CCLK_OBUF_Q,
      O => CCLK_OBUF
    );
  CCLK_OBUF_EXP_1256 : X_BUF
    port map (
      I => CCLK_OBUF_EXP_tsimrenamed_net_Q,
      O => CCLK_OBUF_EXP
    );
  CCLK_OBUF_Q_1257 : X_BUF
    port map (
      I => CCLK_OBUF_D,
      O => CCLK_OBUF_Q
    );
  CCLK_OBUF_D_1258 : X_XOR2
    port map (
      I0 => NlwInverterSignal_CCLK_OBUF_D_IN0,
      I1 => CCLK_OBUF_D2,
      O => CCLK_OBUF_D
    );
  CCLK_OBUF_D1_1259 : X_ZERO
    port map (
      O => CCLK_OBUF_D1
    );
  CCLK_OBUF_D2_PT_0_1260 : X_AND2
    port map (
      I0 => EXP64_EXP,
      I1 => EXP64_EXP,
      O => CCLK_OBUF_D2_PT_0
    );
  CCLK_OBUF_D2_PT_1_1261 : X_AND3
    port map (
      I0 => NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN0,
      I1 => NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN1,
      I2 => state(0),
      O => CCLK_OBUF_D2_PT_1
    );
  CCLK_OBUF_D2_1262 : X_OR2
    port map (
      I0 => CCLK_OBUF_D2_PT_0,
      I1 => CCLK_OBUF_D2_PT_1,
      O => CCLK_OBUF_D2
    );
  CCLK_OBUF_EXP_PT_0_1263 : X_AND6
    port map (
      I0 => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN3,
      I4 => REG_0_12,
      I5 => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN5,
      O => CCLK_OBUF_EXP_PT_0
    );
  CCLK_OBUF_EXP_PT_1_1264 : X_AND6
    port map (
      I0 => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN4,
      I5 => REG_0_13,
      O => CCLK_OBUF_EXP_PT_1
    );
  CCLK_OBUF_EXP_PT_2_1265 : X_AND7
    port map (
      I0 => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN4,
      I5 => DIN_13_IBUF,
      I6 => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN6,
      O => CCLK_OBUF_EXP_PT_2
    );
  CCLK_OBUF_EXP_PT_3_1266 : X_AND7
    port map (
      I0 => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN5,
      I6 => REG_0_13,
      O => CCLK_OBUF_EXP_PT_3
    );
  CCLK_OBUF_EXP_tsimrenamed_net_Q_1267 : X_OR4
    port map (
      I0 => CCLK_OBUF_EXP_PT_0,
      I1 => CCLK_OBUF_EXP_PT_1,
      I2 => CCLK_OBUF_EXP_PT_2,
      I3 => CCLK_OBUF_EXP_PT_3,
      O => CCLK_OBUF_EXP_tsimrenamed_net_Q
    );
  buf_depth_0_buf_depth_0_RSTF_UIM_1268 : X_BUF
    port map (
      I => buf_depth_0_buf_depth_0_RSTF_Q,
      O => buf_depth_0_buf_depth_0_RSTF_UIM
    );
  buf_depth_0_buf_depth_0_RSTF_EXP_1269 : X_BUF
    port map (
      I => buf_depth_0_buf_depth_0_RSTF_EXP_tsimrenamed_net_Q,
      O => buf_depth_0_buf_depth_0_RSTF_EXP
    );
  buf_depth_0_buf_depth_0_RSTF_Q_1270 : X_BUF
    port map (
      I => buf_depth_0_buf_depth_0_RSTF_D,
      O => buf_depth_0_buf_depth_0_RSTF_Q
    );
  buf_depth_0_buf_depth_0_RSTF_D_1271 : X_XOR2
    port map (
      I0 => buf_depth_0_buf_depth_0_RSTF_D1,
      I1 => buf_depth_0_buf_depth_0_RSTF_D2,
      O => buf_depth_0_buf_depth_0_RSTF_D
    );
  buf_depth_0_buf_depth_0_RSTF_D1_1272 : X_ZERO
    port map (
      O => buf_depth_0_buf_depth_0_RSTF_D1
    );
  buf_depth_0_buf_depth_0_RSTF_D2_PT_0_1273 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => buf_depth_0_buf_depth_0_RSTF_D2_PT_0
    );
  buf_depth_0_buf_depth_0_RSTF_D2_PT_1_1274 : X_AND2
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => buf_depth(0),
      O => buf_depth_0_buf_depth_0_RSTF_D2_PT_1
    );
  buf_depth_0_buf_depth_0_RSTF_D2_1275 : X_OR2
    port map (
      I0 => buf_depth_0_buf_depth_0_RSTF_D2_PT_0,
      I1 => buf_depth_0_buf_depth_0_RSTF_D2_PT_1,
      O => buf_depth_0_buf_depth_0_RSTF_D2
    );
  buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_1276 : X_AND6
    port map (
      I0 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN0,
      I1 => buf_depth(0),
      I2 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN2,
      I3 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN3,
      I4 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN4,
      I5 => SHIFT_EN,
      O => buf_depth_0_buf_depth_0_RSTF_EXP_PT_0
    );
  buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_1277 : X_AND6
    port map (
      I0 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN0,
      I1 => buf_depth(1),
      I2 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN2,
      I3 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN4,
      I5 => SHIFT_EN,
      O => buf_depth_0_buf_depth_0_RSTF_EXP_PT_1
    );
  buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_1278 : X_AND6
    port map (
      I0 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN0,
      I1 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN1,
      I2 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN2,
      I3 => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN3,
      I4 => SHIFT_CNT(4),
      I5 => SHIFT_EN,
      O => buf_depth_0_buf_depth_0_RSTF_EXP_PT_2
    );
  buf_depth_0_buf_depth_0_RSTF_EXP_tsimrenamed_net_Q_1279 : X_OR3
    port map (
      I0 => buf_depth_0_buf_depth_0_RSTF_EXP_PT_0,
      I1 => buf_depth_0_buf_depth_0_RSTF_EXP_PT_1,
      I2 => buf_depth_0_buf_depth_0_RSTF_EXP_PT_2,
      O => buf_depth_0_buf_depth_0_RSTF_EXP_tsimrenamed_net_Q
    );
  buf_depth_1_buf_depth_1_RSTF_UIM_1280 : X_BUF
    port map (
      I => buf_depth_1_buf_depth_1_RSTF_Q,
      O => buf_depth_1_buf_depth_1_RSTF_UIM
    );
  buf_depth_1_buf_depth_1_RSTF_Q_1281 : X_BUF
    port map (
      I => buf_depth_1_buf_depth_1_RSTF_D,
      O => buf_depth_1_buf_depth_1_RSTF_Q
    );
  buf_depth_1_buf_depth_1_RSTF_D_1282 : X_XOR2
    port map (
      I0 => buf_depth_1_buf_depth_1_RSTF_D1,
      I1 => buf_depth_1_buf_depth_1_RSTF_D2,
      O => buf_depth_1_buf_depth_1_RSTF_D
    );
  buf_depth_1_buf_depth_1_RSTF_D1_1283 : X_ZERO
    port map (
      O => buf_depth_1_buf_depth_1_RSTF_D1
    );
  buf_depth_1_buf_depth_1_RSTF_D2_PT_0_1284 : X_AND2
    port map (
      I0 => RES_IBUF,
      I1 => RES_IBUF,
      O => buf_depth_1_buf_depth_1_RSTF_D2_PT_0
    );
  buf_depth_1_buf_depth_1_RSTF_D2_PT_1_1285 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => buf_depth(0),
      I2 => buf_depth(1),
      O => buf_depth_1_buf_depth_1_RSTF_D2_PT_1
    );
  buf_depth_1_buf_depth_1_RSTF_D2_PT_2_1286 : X_AND3
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN1,
      I2 => NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN2,
      O => buf_depth_1_buf_depth_1_RSTF_D2_PT_2
    );
  buf_depth_1_buf_depth_1_RSTF_D2_1287 : X_OR3
    port map (
      I0 => buf_depth_1_buf_depth_1_RSTF_D2_PT_0,
      I1 => buf_depth_1_buf_depth_1_RSTF_D2_PT_1,
      I2 => buf_depth_1_buf_depth_1_RSTF_D2_PT_2,
      O => buf_depth_1_buf_depth_1_RSTF_D2
    );
  SHIFT_EN_SHIFT_EN_RSTF_INT_UIM_1288 : X_BUF
    port map (
      I => SHIFT_EN_SHIFT_EN_RSTF_INT_Q,
      O => SHIFT_EN_SHIFT_EN_RSTF_INT_UIM
    );
  SHIFT_EN_SHIFT_EN_RSTF_INT_Q_1289 : X_BUF
    port map (
      I => SHIFT_EN_SHIFT_EN_RSTF_INT_D,
      O => SHIFT_EN_SHIFT_EN_RSTF_INT_Q
    );
  SHIFT_EN_SHIFT_EN_RSTF_INT_D_1290 : X_XOR2
    port map (
      I0 => SHIFT_EN_SHIFT_EN_RSTF_INT_D1,
      I1 => SHIFT_EN_SHIFT_EN_RSTF_INT_D2,
      O => SHIFT_EN_SHIFT_EN_RSTF_INT_D
    );
  SHIFT_EN_SHIFT_EN_RSTF_INT_D1_1291 : X_ZERO
    port map (
      O => SHIFT_EN_SHIFT_EN_RSTF_INT_D1
    );
  SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_1292 : X_AND3
    port map (
      I0 => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN0,
      I1 => state(0),
      I2 => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN2,
      O => SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0
    );
  SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_1293 : X_AND3
    port map (
      I0 => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN0,
      I1 => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN1,
      I2 => state(1),
      O => SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1
    );
  SHIFT_EN_SHIFT_EN_RSTF_INT_D2_1294 : X_OR2
    port map (
      I0 => SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0,
      I1 => SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1,
      O => SHIFT_EN_SHIFT_EN_RSTF_INT_D2
    );
  Q_OpTx_FX_DC_19_UIM_1295 : X_BUF
    port map (
      I => Q_OpTx_FX_DC_19_Q,
      O => Q_OpTx_FX_DC_19_UIM
    );
  Q_OpTx_FX_DC_19_Q_1296 : X_BUF
    port map (
      I => Q_OpTx_FX_DC_19_D,
      O => Q_OpTx_FX_DC_19_Q
    );
  Q_OpTx_FX_DC_19_D_1297 : X_XOR2
    port map (
      I0 => Q_OpTx_FX_DC_19_D1,
      I1 => Q_OpTx_FX_DC_19_D2,
      O => Q_OpTx_FX_DC_19_D
    );
  Q_OpTx_FX_DC_19_D1_1298 : X_ZERO
    port map (
      O => Q_OpTx_FX_DC_19_D1
    );
  Q_OpTx_FX_DC_19_D2_PT_0_1299 : X_AND2
    port map (
      I0 => DONE_IBUF,
      I1 => DONE_IBUF,
      O => Q_OpTx_FX_DC_19_D2_PT_0
    );
  Q_OpTx_FX_DC_19_D2_PT_1_1300 : X_AND7
    port map (
      I0 => buf_depth(0),
      I1 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN1,
      I2 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN2,
      I3 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN3,
      I4 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN4,
      I5 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN5,
      I6 => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN6,
      O => Q_OpTx_FX_DC_19_D2_PT_1
    );
  Q_OpTx_FX_DC_19_D2_1301 : X_OR2
    port map (
      I0 => Q_OpTx_FX_DC_19_D2_PT_0,
      I1 => Q_OpTx_FX_DC_19_D2_PT_1,
      O => Q_OpTx_FX_DC_19_D2
    );
  next_state_0_next_state_0_RSTF_UIM_1302 : X_BUF
    port map (
      I => next_state_0_next_state_0_RSTF_Q,
      O => next_state_0_next_state_0_RSTF_UIM
    );
  next_state_0_next_state_0_RSTF_Q_1303 : X_BUF
    port map (
      I => next_state_0_next_state_0_RSTF_D,
      O => next_state_0_next_state_0_RSTF_Q
    );
  next_state_0_next_state_0_RSTF_D_1304 : X_XOR2
    port map (
      I0 => next_state_0_next_state_0_RSTF_D1,
      I1 => next_state_0_next_state_0_RSTF_D2,
      O => next_state_0_next_state_0_RSTF_D
    );
  next_state_0_next_state_0_RSTF_D1_1305 : X_ZERO
    port map (
      O => next_state_0_next_state_0_RSTF_D1
    );
  next_state_0_next_state_0_RSTF_D2_PT_0_1306 : X_AND2
    port map (
      I0 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_0_IN0,
      I1 => DONE_IBUF,
      O => next_state_0_next_state_0_RSTF_D2_PT_0
    );
  next_state_0_next_state_0_RSTF_D2_PT_1_1307 : X_AND2
    port map (
      I0 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_1_IN0,
      I1 => state(0),
      O => next_state_0_next_state_0_RSTF_D2_PT_1
    );
  next_state_0_next_state_0_RSTF_D2_PT_2_1308 : X_AND2
    port map (
      I0 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_2_IN0,
      I1 => state(1),
      O => next_state_0_next_state_0_RSTF_D2_PT_2
    );
  next_state_0_next_state_0_RSTF_D2_PT_3_1309 : X_AND8
    port map (
      I0 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN0,
      I1 => buf_depth(0),
      I2 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN2,
      I3 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN3,
      I4 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN4,
      I5 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN5,
      I6 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN6,
      I7 => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN7,
      O => next_state_0_next_state_0_RSTF_D2_PT_3
    );
  next_state_0_next_state_0_RSTF_D2_1310 : X_OR4
    port map (
      I0 => next_state_0_next_state_0_RSTF_D2_PT_0,
      I1 => next_state_0_next_state_0_RSTF_D2_PT_1,
      I2 => next_state_0_next_state_0_RSTF_D2_PT_2,
      I3 => next_state_0_next_state_0_RSTF_D2_PT_3,
      O => next_state_0_next_state_0_RSTF_D2
    );
  next_state_1_next_state_1_RSTF_UIM_1311 : X_BUF
    port map (
      I => next_state_1_next_state_1_RSTF_Q,
      O => next_state_1_next_state_1_RSTF_UIM
    );
  next_state_1_next_state_1_RSTF_Q_1312 : X_BUF
    port map (
      I => next_state_1_next_state_1_RSTF_D,
      O => next_state_1_next_state_1_RSTF_Q
    );
  next_state_1_next_state_1_RSTF_D_1313 : X_XOR2
    port map (
      I0 => next_state_1_next_state_1_RSTF_D1,
      I1 => next_state_1_next_state_1_RSTF_D2,
      O => next_state_1_next_state_1_RSTF_D
    );
  next_state_1_next_state_1_RSTF_D1_1314 : X_ZERO
    port map (
      O => next_state_1_next_state_1_RSTF_D1
    );
  next_state_1_next_state_1_RSTF_D2_PT_0_1315 : X_AND3
    port map (
      I0 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_0_IN0,
      I1 => DONE_IBUF,
      I2 => state(1),
      O => next_state_1_next_state_1_RSTF_D2_PT_0
    );
  next_state_1_next_state_1_RSTF_D2_PT_1_1316 : X_AND3
    port map (
      I0 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN0,
      I1 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN1,
      I2 => state(1),
      O => next_state_1_next_state_1_RSTF_D2_PT_1
    );
  next_state_1_next_state_1_RSTF_D2_PT_2_1317 : X_AND3
    port map (
      I0 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_2_IN0,
      I1 => state(0),
      I2 => state(1),
      O => next_state_1_next_state_1_RSTF_D2_PT_2
    );
  next_state_1_next_state_1_RSTF_D2_PT_3_1318 : X_AND3
    port map (
      I0 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN0,
      I1 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN1,
      I2 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN2,
      O => next_state_1_next_state_1_RSTF_D2_PT_3
    );
  next_state_1_next_state_1_RSTF_D2_PT_4_1319 : X_AND16
    port map (
      I0 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN0,
      I1 => buf_depth(0),
      I2 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN2,
      I3 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN3,
      I4 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN4,
      I5 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN5,
      I6 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN6,
      I7 => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN7,
      I8 => state(1),
      I9 => Vcc,
      I10 => Vcc,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => next_state_1_next_state_1_RSTF_D2_PT_4
    );
  next_state_1_next_state_1_RSTF_D2_1320 : X_OR5
    port map (
      I0 => next_state_1_next_state_1_RSTF_D2_PT_0,
      I1 => next_state_1_next_state_1_RSTF_D2_PT_1,
      I2 => next_state_1_next_state_1_RSTF_D2_PT_2,
      I3 => next_state_1_next_state_1_RSTF_D2_PT_3,
      I4 => next_state_1_next_state_1_RSTF_D2_PT_4,
      O => next_state_1_next_state_1_RSTF_D2
    );
  EXP18_EXP_1321 : X_BUF
    port map (
      I => EXP18_EXP_tsimrenamed_net_Q,
      O => EXP18_EXP
    );
  EXP18_EXP_PT_0_1322 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP18_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP18_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP18_EXP_PT_0_IN4,
      I5 => DIN_1_IBUF,
      I6 => NlwInverterSignal_EXP18_EXP_PT_0_IN6,
      O => EXP18_EXP_PT_0
    );
  EXP18_EXP_PT_1_1323 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP18_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP18_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP18_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP18_EXP_PT_1_IN5,
      I6 => REG_0_1,
      O => EXP18_EXP_PT_1
    );
  EXP18_EXP_tsimrenamed_net_Q_1324 : X_OR2
    port map (
      I0 => EXP18_EXP_PT_0,
      I1 => EXP18_EXP_PT_1,
      O => EXP18_EXP_tsimrenamed_net_Q
    );
  EXP19_EXP_1325 : X_BUF
    port map (
      I => EXP19_EXP_tsimrenamed_net_Q,
      O => EXP19_EXP
    );
  EXP19_EXP_PT_0_1326 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP19_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP19_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP19_EXP_PT_0_IN4,
      I5 => DIN_5_IBUF,
      I6 => NlwInverterSignal_EXP19_EXP_PT_0_IN6,
      O => EXP19_EXP_PT_0
    );
  EXP19_EXP_PT_1_1327 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP19_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP19_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP19_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP19_EXP_PT_1_IN5,
      I6 => REG_0_5,
      O => EXP19_EXP_PT_1
    );
  EXP19_EXP_tsimrenamed_net_Q_1328 : X_OR2
    port map (
      I0 => EXP19_EXP_PT_0,
      I1 => EXP19_EXP_PT_1,
      O => EXP19_EXP_tsimrenamed_net_Q
    );
  EXP20_EXP_1329 : X_BUF
    port map (
      I => EXP20_EXP_tsimrenamed_net_Q,
      O => EXP20_EXP
    );
  EXP20_EXP_tsimrenamed_net_Q_1330 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN4,
      I5 => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN5,
      I6 => REG_0_6,
      O => EXP20_EXP_tsimrenamed_net_Q
    );
  EXP21_EXP_1331 : X_BUF
    port map (
      I => EXP21_EXP_tsimrenamed_net_Q,
      O => EXP21_EXP
    );
  EXP21_EXP_tsimrenamed_net_Q_1332 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN4,
      I5 => DIN_6_IBUF,
      I6 => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN6,
      O => EXP21_EXP_tsimrenamed_net_Q
    );
  EXP22_EXP_1333 : X_BUF
    port map (
      I => EXP22_EXP_tsimrenamed_net_Q,
      O => EXP22_EXP
    );
  EXP22_EXP_PT_0_1334 : X_AND5
    port map (
      I0 => NlwInverterSignal_EXP22_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP22_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP22_EXP_PT_0_IN3,
      I4 => REG_0_0,
      O => EXP22_EXP_PT_0
    );
  EXP22_EXP_PT_1_1335 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP22_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP22_EXP_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP22_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_EXP22_EXP_PT_1_IN4,
      I5 => REG_0_0,
      O => EXP22_EXP_PT_1
    );
  EXP22_EXP_PT_2_1336 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP22_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP22_EXP_PT_2_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP22_EXP_PT_2_IN4,
      I5 => DIN_0_IBUF,
      I6 => NlwInverterSignal_EXP22_EXP_PT_2_IN6,
      O => EXP22_EXP_PT_2
    );
  EXP22_EXP_tsimrenamed_net_Q_1337 : X_OR3
    port map (
      I0 => EXP22_EXP_PT_0,
      I1 => EXP22_EXP_PT_1,
      I2 => EXP22_EXP_PT_2,
      O => EXP22_EXP_tsimrenamed_net_Q
    );
  EXP23_EXP_1338 : X_BUF
    port map (
      I => EXP23_EXP_tsimrenamed_net_Q,
      O => EXP23_EXP
    );
  EXP23_EXP_PT_0_1339 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP23_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP23_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP23_EXP_PT_0_IN3,
      I4 => REG_0_2,
      I5 => NlwInverterSignal_EXP23_EXP_PT_0_IN5,
      O => EXP23_EXP_PT_0
    );
  EXP23_EXP_PT_1_1340 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP23_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP23_EXP_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP23_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_EXP23_EXP_PT_1_IN4,
      I5 => REG_0_3,
      O => EXP23_EXP_PT_1
    );
  EXP23_EXP_PT_2_1341 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP23_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP23_EXP_PT_2_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP23_EXP_PT_2_IN4,
      I5 => DIN_3_IBUF,
      I6 => NlwInverterSignal_EXP23_EXP_PT_2_IN6,
      O => EXP23_EXP_PT_2
    );
  EXP23_EXP_PT_3_1342 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP23_EXP_PT_3_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP23_EXP_PT_3_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP23_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_EXP23_EXP_PT_3_IN5,
      I6 => REG_0_3,
      O => EXP23_EXP_PT_3
    );
  EXP23_EXP_tsimrenamed_net_Q_1343 : X_OR4
    port map (
      I0 => EXP23_EXP_PT_0,
      I1 => EXP23_EXP_PT_1,
      I2 => EXP23_EXP_PT_2,
      I3 => EXP23_EXP_PT_3,
      O => EXP23_EXP_tsimrenamed_net_Q
    );
  EXP24_EXP_1344 : X_BUF
    port map (
      I => EXP24_EXP_tsimrenamed_net_Q,
      O => EXP24_EXP
    );
  EXP24_EXP_PT_0_1345 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP24_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP24_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP24_EXP_PT_0_IN4,
      I5 => DIN_31_IBUF,
      I6 => NlwInverterSignal_EXP24_EXP_PT_0_IN6,
      O => EXP24_EXP_PT_0
    );
  EXP24_EXP_PT_1_1346 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP24_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP24_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP24_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP24_EXP_PT_1_IN5,
      I6 => REG_0_31,
      O => EXP24_EXP_PT_1
    );
  EXP24_EXP_tsimrenamed_net_Q_1347 : X_OR2
    port map (
      I0 => EXP24_EXP_PT_0,
      I1 => EXP24_EXP_PT_1,
      O => EXP24_EXP_tsimrenamed_net_Q
    );
  EXP25_EXP_1348 : X_BUF
    port map (
      I => EXP25_EXP_tsimrenamed_net_Q,
      O => EXP25_EXP
    );
  EXP25_EXP_PT_0_1349 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP25_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP25_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP25_EXP_PT_0_IN3,
      I4 => REG_0_29,
      I5 => NlwInverterSignal_EXP25_EXP_PT_0_IN5,
      O => EXP25_EXP_PT_0
    );
  EXP25_EXP_PT_1_1350 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP25_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP25_EXP_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP25_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_EXP25_EXP_PT_1_IN4,
      I5 => REG_0_30,
      O => EXP25_EXP_PT_1
    );
  EXP25_EXP_PT_2_1351 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP25_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP25_EXP_PT_2_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP25_EXP_PT_2_IN4,
      I5 => DIN_30_IBUF,
      I6 => NlwInverterSignal_EXP25_EXP_PT_2_IN6,
      O => EXP25_EXP_PT_2
    );
  EXP25_EXP_PT_3_1352 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP25_EXP_PT_3_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP25_EXP_PT_3_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP25_EXP_PT_3_IN4,
      I5 => NlwInverterSignal_EXP25_EXP_PT_3_IN5,
      I6 => REG_0_30,
      O => EXP25_EXP_PT_3
    );
  EXP25_EXP_tsimrenamed_net_Q_1353 : X_OR4
    port map (
      I0 => EXP25_EXP_PT_0,
      I1 => EXP25_EXP_PT_1,
      I2 => EXP25_EXP_PT_2,
      I3 => EXP25_EXP_PT_3,
      O => EXP25_EXP_tsimrenamed_net_Q
    );
  EXP26_EXP_1354 : X_BUF
    port map (
      I => EXP26_EXP_tsimrenamed_net_Q,
      O => EXP26_EXP
    );
  EXP26_EXP_PT_0_1355 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP26_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP26_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP26_EXP_PT_0_IN4,
      I5 => DIN_28_IBUF,
      I6 => NlwInverterSignal_EXP26_EXP_PT_0_IN6,
      O => EXP26_EXP_PT_0
    );
  EXP26_EXP_PT_1_1356 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP26_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP26_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP26_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP26_EXP_PT_1_IN5,
      I6 => REG_0_28,
      O => EXP26_EXP_PT_1
    );
  EXP26_EXP_tsimrenamed_net_Q_1357 : X_OR2
    port map (
      I0 => EXP26_EXP_PT_0,
      I1 => EXP26_EXP_PT_1,
      O => EXP26_EXP_tsimrenamed_net_Q
    );
  EXP27_EXP_1358 : X_BUF
    port map (
      I => EXP27_EXP_tsimrenamed_net_Q,
      O => EXP27_EXP
    );
  EXP27_EXP_PT_0_1359 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP27_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_31_IBUF,
      I6 => NlwInverterSignal_EXP27_EXP_PT_0_IN6,
      O => EXP27_EXP_PT_0
    );
  EXP27_EXP_PT_1_1360 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP27_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP27_EXP_PT_1_IN5,
      I6 => REG_1_31,
      O => EXP27_EXP_PT_1
    );
  EXP27_EXP_tsimrenamed_net_Q_1361 : X_OR2
    port map (
      I0 => EXP27_EXP_PT_0,
      I1 => EXP27_EXP_PT_1,
      O => EXP27_EXP_tsimrenamed_net_Q
    );
  EXP28_EXP_1362 : X_BUF
    port map (
      I => EXP28_EXP_tsimrenamed_net_Q,
      O => EXP28_EXP
    );
  EXP28_EXP_PT_0_1363 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP28_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_29_IBUF,
      I6 => NlwInverterSignal_EXP28_EXP_PT_0_IN6,
      O => EXP28_EXP_PT_0
    );
  EXP28_EXP_PT_1_1364 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP28_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP28_EXP_PT_1_IN5,
      I6 => REG_1_29,
      O => EXP28_EXP_PT_1
    );
  EXP28_EXP_tsimrenamed_net_Q_1365 : X_OR2
    port map (
      I0 => EXP28_EXP_PT_0,
      I1 => EXP28_EXP_PT_1,
      O => EXP28_EXP_tsimrenamed_net_Q
    );
  EXP29_EXP_1366 : X_BUF
    port map (
      I => EXP29_EXP_tsimrenamed_net_Q,
      O => EXP29_EXP
    );
  EXP29_EXP_PT_0_1367 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP29_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP29_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP29_EXP_PT_0_IN3,
      I4 => REG_0_16,
      I5 => NlwInverterSignal_EXP29_EXP_PT_0_IN5,
      O => EXP29_EXP_PT_0
    );
  EXP29_EXP_PT_1_1368 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP29_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP29_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP29_EXP_PT_1_IN4,
      I5 => DIN_17_IBUF,
      I6 => NlwInverterSignal_EXP29_EXP_PT_1_IN6,
      O => EXP29_EXP_PT_1
    );
  EXP29_EXP_PT_2_1369 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP29_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP29_EXP_PT_2_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP29_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP29_EXP_PT_2_IN5,
      I6 => REG_0_17,
      O => EXP29_EXP_PT_2
    );
  EXP29_EXP_tsimrenamed_net_Q_1370 : X_OR3
    port map (
      I0 => EXP29_EXP_PT_0,
      I1 => EXP29_EXP_PT_1,
      I2 => EXP29_EXP_PT_2,
      O => EXP29_EXP_tsimrenamed_net_Q
    );
  EXP30_EXP_1371 : X_BUF
    port map (
      I => EXP30_EXP_tsimrenamed_net_Q,
      O => EXP30_EXP
    );
  EXP30_EXP_PT_0_1372 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP30_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP30_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP30_EXP_PT_0_IN3,
      I4 => REG_0_14,
      I5 => NlwInverterSignal_EXP30_EXP_PT_0_IN5,
      O => EXP30_EXP_PT_0
    );
  EXP30_EXP_PT_1_1373 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP30_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP30_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP30_EXP_PT_1_IN4,
      I5 => DIN_15_IBUF,
      I6 => NlwInverterSignal_EXP30_EXP_PT_1_IN6,
      O => EXP30_EXP_PT_1
    );
  EXP30_EXP_PT_2_1374 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP30_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP30_EXP_PT_2_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP30_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP30_EXP_PT_2_IN5,
      I6 => REG_0_15,
      O => EXP30_EXP_PT_2
    );
  EXP30_EXP_tsimrenamed_net_Q_1375 : X_OR3
    port map (
      I0 => EXP30_EXP_PT_0,
      I1 => EXP30_EXP_PT_1,
      I2 => EXP30_EXP_PT_2,
      O => EXP30_EXP_tsimrenamed_net_Q
    );
  EXP31_EXP_1376 : X_BUF
    port map (
      I => EXP31_EXP_tsimrenamed_net_Q,
      O => EXP31_EXP
    );
  EXP31_EXP_PT_0_1377 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP31_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP31_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP31_EXP_PT_0_IN4,
      I5 => DIN_20_IBUF,
      I6 => NlwInverterSignal_EXP31_EXP_PT_0_IN6,
      O => EXP31_EXP_PT_0
    );
  EXP31_EXP_PT_1_1378 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP31_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP31_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP31_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP31_EXP_PT_1_IN5,
      I6 => REG_0_20,
      O => EXP31_EXP_PT_1
    );
  EXP31_EXP_tsimrenamed_net_Q_1379 : X_OR2
    port map (
      I0 => EXP31_EXP_PT_0,
      I1 => EXP31_EXP_PT_1,
      O => EXP31_EXP_tsimrenamed_net_Q
    );
  EXP32_EXP_1380 : X_BUF
    port map (
      I => EXP32_EXP_tsimrenamed_net_Q,
      O => EXP32_EXP
    );
  EXP32_EXP_PT_0_1381 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP32_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP32_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP32_EXP_PT_0_IN4,
      I5 => DIN_18_IBUF,
      I6 => NlwInverterSignal_EXP32_EXP_PT_0_IN6,
      O => EXP32_EXP_PT_0
    );
  EXP32_EXP_PT_1_1382 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP32_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP32_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP32_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP32_EXP_PT_1_IN5,
      I6 => REG_0_18,
      O => EXP32_EXP_PT_1
    );
  EXP32_EXP_tsimrenamed_net_Q_1383 : X_OR2
    port map (
      I0 => EXP32_EXP_PT_0,
      I1 => EXP32_EXP_PT_1,
      O => EXP32_EXP_tsimrenamed_net_Q
    );
  EXP33_EXP_1384 : X_BUF
    port map (
      I => EXP33_EXP_tsimrenamed_net_Q,
      O => EXP33_EXP
    );
  EXP33_EXP_PT_0_1385 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP33_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP33_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP33_EXP_PT_0_IN3,
      I4 => REG_0_22,
      I5 => NlwInverterSignal_EXP33_EXP_PT_0_IN5,
      O => EXP33_EXP_PT_0
    );
  EXP33_EXP_PT_1_1386 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP33_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP33_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP33_EXP_PT_1_IN4,
      I5 => DIN_23_IBUF,
      I6 => NlwInverterSignal_EXP33_EXP_PT_1_IN6,
      O => EXP33_EXP_PT_1
    );
  EXP33_EXP_PT_2_1387 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP33_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP33_EXP_PT_2_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP33_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP33_EXP_PT_2_IN5,
      I6 => REG_0_23,
      O => EXP33_EXP_PT_2
    );
  EXP33_EXP_tsimrenamed_net_Q_1388 : X_OR3
    port map (
      I0 => EXP33_EXP_PT_0,
      I1 => EXP33_EXP_PT_1,
      I2 => EXP33_EXP_PT_2,
      O => EXP33_EXP_tsimrenamed_net_Q
    );
  EXP34_EXP_1389 : X_BUF
    port map (
      I => EXP34_EXP_tsimrenamed_net_Q,
      O => EXP34_EXP
    );
  EXP34_EXP_PT_0_1390 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP34_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP34_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP34_EXP_PT_0_IN3,
      I4 => REG_0_20,
      I5 => NlwInverterSignal_EXP34_EXP_PT_0_IN5,
      O => EXP34_EXP_PT_0
    );
  EXP34_EXP_PT_1_1391 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP34_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP34_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP34_EXP_PT_1_IN4,
      I5 => DIN_21_IBUF,
      I6 => NlwInverterSignal_EXP34_EXP_PT_1_IN6,
      O => EXP34_EXP_PT_1
    );
  EXP34_EXP_PT_2_1392 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP34_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP34_EXP_PT_2_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP34_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP34_EXP_PT_2_IN5,
      I6 => REG_0_21,
      O => EXP34_EXP_PT_2
    );
  EXP34_EXP_tsimrenamed_net_Q_1393 : X_OR3
    port map (
      I0 => EXP34_EXP_PT_0,
      I1 => EXP34_EXP_PT_1,
      I2 => EXP34_EXP_PT_2,
      O => EXP34_EXP_tsimrenamed_net_Q
    );
  EXP35_EXP_1394 : X_BUF
    port map (
      I => EXP35_EXP_tsimrenamed_net_Q,
      O => EXP35_EXP
    );
  EXP35_EXP_PT_0_1395 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP35_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP35_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP35_EXP_PT_0_IN4,
      I5 => DIN_26_IBUF,
      I6 => NlwInverterSignal_EXP35_EXP_PT_0_IN6,
      O => EXP35_EXP_PT_0
    );
  EXP35_EXP_PT_1_1396 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP35_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP35_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP35_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP35_EXP_PT_1_IN5,
      I6 => REG_0_26,
      O => EXP35_EXP_PT_1
    );
  EXP35_EXP_tsimrenamed_net_Q_1397 : X_OR2
    port map (
      I0 => EXP35_EXP_PT_0,
      I1 => EXP35_EXP_PT_1,
      O => EXP35_EXP_tsimrenamed_net_Q
    );
  EXP36_EXP_1398 : X_BUF
    port map (
      I => EXP36_EXP_tsimrenamed_net_Q,
      O => EXP36_EXP
    );
  EXP36_EXP_PT_0_1399 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP36_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP36_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP36_EXP_PT_0_IN4,
      I5 => DIN_24_IBUF,
      I6 => NlwInverterSignal_EXP36_EXP_PT_0_IN6,
      O => EXP36_EXP_PT_0
    );
  EXP36_EXP_PT_1_1400 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP36_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP36_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP36_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP36_EXP_PT_1_IN5,
      I6 => REG_0_24,
      O => EXP36_EXP_PT_1
    );
  EXP36_EXP_tsimrenamed_net_Q_1401 : X_OR2
    port map (
      I0 => EXP36_EXP_PT_0,
      I1 => EXP36_EXP_PT_1,
      O => EXP36_EXP_tsimrenamed_net_Q
    );
  EXP37_EXP_1402 : X_BUF
    port map (
      I => EXP37_EXP_tsimrenamed_net_Q,
      O => EXP37_EXP
    );
  EXP37_EXP_PT_0_1403 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP37_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_27_IBUF,
      I6 => NlwInverterSignal_EXP37_EXP_PT_0_IN6,
      O => EXP37_EXP_PT_0
    );
  EXP37_EXP_PT_1_1404 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP37_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP37_EXP_PT_1_IN5,
      I6 => REG_1_27,
      O => EXP37_EXP_PT_1
    );
  EXP37_EXP_tsimrenamed_net_Q_1405 : X_OR2
    port map (
      I0 => EXP37_EXP_PT_0,
      I1 => EXP37_EXP_PT_1,
      O => EXP37_EXP_tsimrenamed_net_Q
    );
  EXP38_EXP_1406 : X_BUF
    port map (
      I => EXP38_EXP_tsimrenamed_net_Q,
      O => EXP38_EXP
    );
  EXP38_EXP_PT_0_1407 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP38_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP38_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_23,
      I5 => NlwInverterSignal_EXP38_EXP_PT_0_IN5,
      O => EXP38_EXP_PT_0
    );
  EXP38_EXP_PT_1_1408 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP38_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_24_IBUF,
      I6 => NlwInverterSignal_EXP38_EXP_PT_1_IN6,
      O => EXP38_EXP_PT_1
    );
  EXP38_EXP_PT_2_1409 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP38_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP38_EXP_PT_2_IN5,
      I6 => REG_1_24,
      O => EXP38_EXP_PT_2
    );
  EXP38_EXP_tsimrenamed_net_Q_1410 : X_OR3
    port map (
      I0 => EXP38_EXP_PT_0,
      I1 => EXP38_EXP_PT_1,
      I2 => EXP38_EXP_PT_2,
      O => EXP38_EXP_tsimrenamed_net_Q
    );
  EXP39_EXP_1411 : X_BUF
    port map (
      I => EXP39_EXP_tsimrenamed_net_Q,
      O => EXP39_EXP
    );
  EXP39_EXP_PT_0_1412 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP39_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP39_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP39_EXP_PT_0_IN3,
      I4 => REG_0_26,
      I5 => NlwInverterSignal_EXP39_EXP_PT_0_IN5,
      O => EXP39_EXP_PT_0
    );
  EXP39_EXP_PT_1_1413 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP39_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP39_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP39_EXP_PT_1_IN4,
      I5 => DIN_27_IBUF,
      I6 => NlwInverterSignal_EXP39_EXP_PT_1_IN6,
      O => EXP39_EXP_PT_1
    );
  EXP39_EXP_PT_2_1414 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP39_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP39_EXP_PT_2_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP39_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP39_EXP_PT_2_IN5,
      I6 => REG_0_27,
      O => EXP39_EXP_PT_2
    );
  EXP39_EXP_tsimrenamed_net_Q_1415 : X_OR3
    port map (
      I0 => EXP39_EXP_PT_0,
      I1 => EXP39_EXP_PT_1,
      I2 => EXP39_EXP_PT_2,
      O => EXP39_EXP_tsimrenamed_net_Q
    );
  EXP40_EXP_1416 : X_BUF
    port map (
      I => EXP40_EXP_tsimrenamed_net_Q,
      O => EXP40_EXP
    );
  EXP40_EXP_PT_0_1417 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP40_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_26_IBUF,
      I6 => NlwInverterSignal_EXP40_EXP_PT_0_IN6,
      O => EXP40_EXP_PT_0
    );
  EXP40_EXP_PT_1_1418 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP40_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP40_EXP_PT_1_IN5,
      I6 => REG_1_26,
      O => EXP40_EXP_PT_1
    );
  EXP40_EXP_tsimrenamed_net_Q_1419 : X_OR2
    port map (
      I0 => EXP40_EXP_PT_0,
      I1 => EXP40_EXP_PT_1,
      O => EXP40_EXP_tsimrenamed_net_Q
    );
  EXP41_EXP_1420 : X_BUF
    port map (
      I => EXP41_EXP_tsimrenamed_net_Q,
      O => EXP41_EXP
    );
  EXP41_EXP_PT_0_1421 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP41_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_25_IBUF,
      I6 => NlwInverterSignal_EXP41_EXP_PT_0_IN6,
      O => EXP41_EXP_PT_0
    );
  EXP41_EXP_PT_1_1422 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP41_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP41_EXP_PT_1_IN5,
      I6 => REG_1_25,
      O => EXP41_EXP_PT_1
    );
  EXP41_EXP_tsimrenamed_net_Q_1423 : X_OR2
    port map (
      I0 => EXP41_EXP_PT_0,
      I1 => EXP41_EXP_PT_1,
      O => EXP41_EXP_tsimrenamed_net_Q
    );
  EXP42_EXP_1424 : X_BUF
    port map (
      I => EXP42_EXP_tsimrenamed_net_Q,
      O => EXP42_EXP
    );
  EXP42_EXP_PT_0_1425 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP42_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_7_IBUF,
      I6 => NlwInverterSignal_EXP42_EXP_PT_0_IN6,
      O => EXP42_EXP_PT_0
    );
  EXP42_EXP_PT_1_1426 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP42_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP42_EXP_PT_1_IN5,
      I6 => REG_1_7,
      O => EXP42_EXP_PT_1
    );
  EXP42_EXP_tsimrenamed_net_Q_1427 : X_OR2
    port map (
      I0 => EXP42_EXP_PT_0,
      I1 => EXP42_EXP_PT_1,
      O => EXP42_EXP_tsimrenamed_net_Q
    );
  EXP43_EXP_1428 : X_BUF
    port map (
      I => EXP43_EXP_tsimrenamed_net_Q,
      O => EXP43_EXP
    );
  EXP43_EXP_PT_0_1429 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP43_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_10_IBUF,
      I6 => NlwInverterSignal_EXP43_EXP_PT_0_IN6,
      O => EXP43_EXP_PT_0
    );
  EXP43_EXP_PT_1_1430 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP43_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP43_EXP_PT_1_IN5,
      I6 => REG_1_10,
      O => EXP43_EXP_PT_1
    );
  EXP43_EXP_tsimrenamed_net_Q_1431 : X_OR2
    port map (
      I0 => EXP43_EXP_PT_0,
      I1 => EXP43_EXP_PT_1,
      O => EXP43_EXP_tsimrenamed_net_Q
    );
  EXP44_EXP_1432 : X_BUF
    port map (
      I => EXP44_EXP_tsimrenamed_net_Q,
      O => EXP44_EXP
    );
  EXP44_EXP_PT_0_1433 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP44_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_9_IBUF,
      I6 => NlwInverterSignal_EXP44_EXP_PT_0_IN6,
      O => EXP44_EXP_PT_0
    );
  EXP44_EXP_PT_1_1434 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP44_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP44_EXP_PT_1_IN5,
      I6 => REG_1_9,
      O => EXP44_EXP_PT_1
    );
  EXP44_EXP_tsimrenamed_net_Q_1435 : X_OR2
    port map (
      I0 => EXP44_EXP_PT_0,
      I1 => EXP44_EXP_PT_1,
      O => EXP44_EXP_tsimrenamed_net_Q
    );
  EXP45_EXP_1436 : X_BUF
    port map (
      I => EXP45_EXP_tsimrenamed_net_Q,
      O => EXP45_EXP
    );
  EXP45_EXP_PT_0_1437 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP45_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP45_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP45_EXP_PT_0_IN3,
      I4 => NlwInverterSignal_EXP45_EXP_PT_0_IN4,
      I5 => REG_0_8,
      O => EXP45_EXP_PT_0
    );
  EXP45_EXP_PT_1_1438 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP45_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP45_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP45_EXP_PT_1_IN4,
      I5 => REG_0_9,
      I6 => NlwInverterSignal_EXP45_EXP_PT_1_IN6,
      O => EXP45_EXP_PT_1
    );
  EXP45_EXP_PT_2_1439 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP45_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP45_EXP_PT_2_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP45_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP45_EXP_PT_2_IN5,
      I6 => DIN_9_IBUF,
      O => EXP45_EXP_PT_2
    );
  EXP45_EXP_tsimrenamed_net_Q_1440 : X_OR3
    port map (
      I0 => EXP45_EXP_PT_0,
      I1 => EXP45_EXP_PT_1,
      I2 => EXP45_EXP_PT_2,
      O => EXP45_EXP_tsimrenamed_net_Q
    );
  EXP46_EXP_1441 : X_BUF
    port map (
      I => EXP46_EXP_tsimrenamed_net_Q,
      O => EXP46_EXP
    );
  EXP46_EXP_PT_0_1442 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP46_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP46_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => NlwInverterSignal_EXP46_EXP_PT_0_IN3,
      I4 => REG_0_6,
      I5 => NlwInverterSignal_EXP46_EXP_PT_0_IN5,
      O => EXP46_EXP_PT_0
    );
  EXP46_EXP_PT_1_1443 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP46_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP46_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP46_EXP_PT_1_IN4,
      I5 => DIN_7_IBUF,
      I6 => NlwInverterSignal_EXP46_EXP_PT_1_IN6,
      O => EXP46_EXP_PT_1
    );
  EXP46_EXP_PT_2_1444 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP46_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP46_EXP_PT_2_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP46_EXP_PT_2_IN4,
      I5 => NlwInverterSignal_EXP46_EXP_PT_2_IN5,
      I6 => REG_0_7,
      O => EXP46_EXP_PT_2
    );
  EXP46_EXP_tsimrenamed_net_Q_1445 : X_OR3
    port map (
      I0 => EXP46_EXP_PT_0,
      I1 => EXP46_EXP_PT_1,
      I2 => EXP46_EXP_PT_2,
      O => EXP46_EXP_tsimrenamed_net_Q
    );
  EXP47_EXP_1446 : X_BUF
    port map (
      I => EXP47_EXP_tsimrenamed_net_Q,
      O => EXP47_EXP
    );
  EXP47_EXP_PT_0_1447 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP47_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_8_IBUF,
      I6 => NlwInverterSignal_EXP47_EXP_PT_0_IN6,
      O => EXP47_EXP_PT_0
    );
  EXP47_EXP_PT_1_1448 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP47_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP47_EXP_PT_1_IN5,
      I6 => REG_1_8,
      O => EXP47_EXP_PT_1
    );
  EXP47_EXP_tsimrenamed_net_Q_1449 : X_OR2
    port map (
      I0 => EXP47_EXP_PT_0,
      I1 => EXP47_EXP_PT_1,
      O => EXP47_EXP_tsimrenamed_net_Q
    );
  EXP48_EXP_1450 : X_BUF
    port map (
      I => EXP48_EXP_tsimrenamed_net_Q,
      O => EXP48_EXP
    );
  EXP48_EXP_PT_0_1451 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP48_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_1_IBUF,
      I6 => NlwInverterSignal_EXP48_EXP_PT_0_IN6,
      O => EXP48_EXP_PT_0
    );
  EXP48_EXP_PT_1_1452 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP48_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP48_EXP_PT_1_IN5,
      I6 => REG_1_1,
      O => EXP48_EXP_PT_1
    );
  EXP48_EXP_tsimrenamed_net_Q_1453 : X_OR2
    port map (
      I0 => EXP48_EXP_PT_0,
      I1 => EXP48_EXP_PT_1,
      O => EXP48_EXP_tsimrenamed_net_Q
    );
  EXP49_EXP_1454 : X_BUF
    port map (
      I => EXP49_EXP_tsimrenamed_net_Q,
      O => EXP49_EXP
    );
  EXP49_EXP_PT_0_1455 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP49_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_5_IBUF,
      I6 => NlwInverterSignal_EXP49_EXP_PT_0_IN6,
      O => EXP49_EXP_PT_0
    );
  EXP49_EXP_PT_1_1456 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP49_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP49_EXP_PT_1_IN5,
      I6 => REG_1_5,
      O => EXP49_EXP_PT_1
    );
  EXP49_EXP_tsimrenamed_net_Q_1457 : X_OR2
    port map (
      I0 => EXP49_EXP_PT_0,
      I1 => EXP49_EXP_PT_1,
      O => EXP49_EXP_tsimrenamed_net_Q
    );
  EXP50_EXP_1458 : X_BUF
    port map (
      I => EXP50_EXP_tsimrenamed_net_Q,
      O => EXP50_EXP
    );
  EXP50_EXP_tsimrenamed_net_Q_1459 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN5,
      I6 => REG_1_6,
      O => EXP50_EXP_tsimrenamed_net_Q
    );
  EXP51_EXP_1460 : X_BUF
    port map (
      I => EXP51_EXP_tsimrenamed_net_Q,
      O => EXP51_EXP
    );
  EXP51_EXP_tsimrenamed_net_Q_1461 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_6_IBUF,
      I6 => NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN6,
      O => EXP51_EXP_tsimrenamed_net_Q
    );
  EXP52_EXP_1462 : X_BUF
    port map (
      I => EXP52_EXP_tsimrenamed_net_Q,
      O => EXP52_EXP
    );
  EXP52_EXP_PT_0_1463 : X_AND5
    port map (
      I0 => NlwInverterSignal_EXP52_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP52_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_0,
      O => EXP52_EXP_PT_0
    );
  EXP52_EXP_PT_1_1464 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP52_EXP_PT_1_IN0,
      I1 => writeBufId(0),
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_EXP52_EXP_PT_1_IN4,
      I5 => REG_1_0,
      O => EXP52_EXP_PT_1
    );
  EXP52_EXP_PT_2_1465 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP52_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_0_IBUF,
      I6 => NlwInverterSignal_EXP52_EXP_PT_2_IN6,
      O => EXP52_EXP_PT_2
    );
  EXP52_EXP_tsimrenamed_net_Q_1466 : X_OR3
    port map (
      I0 => EXP52_EXP_PT_0,
      I1 => EXP52_EXP_PT_1,
      I2 => EXP52_EXP_PT_2,
      O => EXP52_EXP_tsimrenamed_net_Q
    );
  EXP53_EXP_1467 : X_BUF
    port map (
      I => EXP53_EXP_tsimrenamed_net_Q,
      O => EXP53_EXP
    );
  EXP53_EXP_PT_0_1468 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP53_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP53_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_2,
      I5 => NlwInverterSignal_EXP53_EXP_PT_0_IN5,
      O => EXP53_EXP_PT_0
    );
  EXP53_EXP_PT_1_1469 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP53_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP53_EXP_PT_1_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => NlwInverterSignal_EXP53_EXP_PT_1_IN4,
      I5 => REG_1_3,
      O => EXP53_EXP_PT_1
    );
  EXP53_EXP_PT_2_1470 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP53_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_3_IBUF,
      I6 => NlwInverterSignal_EXP53_EXP_PT_2_IN6,
      O => EXP53_EXP_PT_2
    );
  EXP53_EXP_PT_3_1471 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP53_EXP_PT_3_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP53_EXP_PT_3_IN5,
      I6 => REG_1_3,
      O => EXP53_EXP_PT_3
    );
  EXP53_EXP_tsimrenamed_net_Q_1472 : X_OR4
    port map (
      I0 => EXP53_EXP_PT_0,
      I1 => EXP53_EXP_PT_1,
      I2 => EXP53_EXP_PT_2,
      I3 => EXP53_EXP_PT_3,
      O => EXP53_EXP_tsimrenamed_net_Q
    );
  EXP54_EXP_1473 : X_BUF
    port map (
      I => EXP54_EXP_tsimrenamed_net_Q,
      O => EXP54_EXP
    );
  EXP54_EXP_PT_0_1474 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP54_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_16_IBUF,
      I6 => NlwInverterSignal_EXP54_EXP_PT_0_IN6,
      O => EXP54_EXP_PT_0
    );
  EXP54_EXP_PT_1_1475 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP54_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP54_EXP_PT_1_IN5,
      I6 => REG_1_16,
      O => EXP54_EXP_PT_1
    );
  EXP54_EXP_tsimrenamed_net_Q_1476 : X_OR2
    port map (
      I0 => EXP54_EXP_PT_0,
      I1 => EXP54_EXP_PT_1,
      O => EXP54_EXP_tsimrenamed_net_Q
    );
  EXP55_EXP_1477 : X_BUF
    port map (
      I => EXP55_EXP_tsimrenamed_net_Q,
      O => EXP55_EXP
    );
  EXP55_EXP_PT_0_1478 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP55_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP55_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_12,
      I5 => NlwInverterSignal_EXP55_EXP_PT_0_IN5,
      O => EXP55_EXP_PT_0
    );
  EXP55_EXP_PT_1_1479 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP55_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_13_IBUF,
      I6 => NlwInverterSignal_EXP55_EXP_PT_1_IN6,
      O => EXP55_EXP_PT_1
    );
  EXP55_EXP_PT_2_1480 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP55_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP55_EXP_PT_2_IN5,
      I6 => REG_1_13,
      O => EXP55_EXP_PT_2
    );
  EXP55_EXP_tsimrenamed_net_Q_1481 : X_OR3
    port map (
      I0 => EXP55_EXP_PT_0,
      I1 => EXP55_EXP_PT_1,
      I2 => EXP55_EXP_PT_2,
      O => EXP55_EXP_tsimrenamed_net_Q
    );
  EXP56_EXP_1482 : X_BUF
    port map (
      I => EXP56_EXP_tsimrenamed_net_Q,
      O => EXP56_EXP
    );
  EXP56_EXP_PT_0_1483 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP56_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP56_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_10,
      I5 => NlwInverterSignal_EXP56_EXP_PT_0_IN5,
      O => EXP56_EXP_PT_0
    );
  EXP56_EXP_PT_1_1484 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP56_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_11_IBUF,
      I6 => NlwInverterSignal_EXP56_EXP_PT_1_IN6,
      O => EXP56_EXP_PT_1
    );
  EXP56_EXP_PT_2_1485 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP56_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP56_EXP_PT_2_IN5,
      I6 => REG_1_11,
      O => EXP56_EXP_PT_2
    );
  EXP56_EXP_tsimrenamed_net_Q_1486 : X_OR3
    port map (
      I0 => EXP56_EXP_PT_0,
      I1 => EXP56_EXP_PT_1,
      I2 => EXP56_EXP_PT_2,
      O => EXP56_EXP_tsimrenamed_net_Q
    );
  EXP57_EXP_1487 : X_BUF
    port map (
      I => EXP57_EXP_tsimrenamed_net_Q,
      O => EXP57_EXP
    );
  EXP57_EXP_PT_0_1488 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP57_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_15_IBUF,
      I6 => NlwInverterSignal_EXP57_EXP_PT_0_IN6,
      O => EXP57_EXP_PT_0
    );
  EXP57_EXP_PT_1_1489 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP57_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP57_EXP_PT_1_IN5,
      I6 => REG_1_15,
      O => EXP57_EXP_PT_1
    );
  EXP57_EXP_tsimrenamed_net_Q_1490 : X_OR2
    port map (
      I0 => EXP57_EXP_PT_0,
      I1 => EXP57_EXP_PT_1,
      O => EXP57_EXP_tsimrenamed_net_Q
    );
  EXP58_EXP_1491 : X_BUF
    port map (
      I => EXP58_EXP_tsimrenamed_net_Q,
      O => EXP58_EXP
    );
  EXP58_EXP_PT_0_1492 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP58_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_14_IBUF,
      I6 => NlwInverterSignal_EXP58_EXP_PT_0_IN6,
      O => EXP58_EXP_PT_0
    );
  EXP58_EXP_PT_1_1493 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP58_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP58_EXP_PT_1_IN5,
      I6 => REG_1_14,
      O => EXP58_EXP_PT_1
    );
  EXP58_EXP_tsimrenamed_net_Q_1494 : X_OR2
    port map (
      I0 => EXP58_EXP_PT_0,
      I1 => EXP58_EXP_PT_1,
      O => EXP58_EXP_tsimrenamed_net_Q
    );
  EXP59_EXP_1495 : X_BUF
    port map (
      I => EXP59_EXP_tsimrenamed_net_Q,
      O => EXP59_EXP
    );
  EXP59_EXP_PT_0_1496 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP59_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_22_IBUF,
      I6 => NlwInverterSignal_EXP59_EXP_PT_0_IN6,
      O => EXP59_EXP_PT_0
    );
  EXP59_EXP_PT_1_1497 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP59_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP59_EXP_PT_1_IN5,
      I6 => REG_1_22,
      O => EXP59_EXP_PT_1
    );
  EXP59_EXP_tsimrenamed_net_Q_1498 : X_OR2
    port map (
      I0 => EXP59_EXP_PT_0,
      I1 => EXP59_EXP_PT_1,
      O => EXP59_EXP_tsimrenamed_net_Q
    );
  EXP60_EXP_1499 : X_BUF
    port map (
      I => EXP60_EXP_tsimrenamed_net_Q,
      O => EXP60_EXP
    );
  EXP60_EXP_PT_0_1500 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP60_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP60_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_18,
      I5 => NlwInverterSignal_EXP60_EXP_PT_0_IN5,
      O => EXP60_EXP_PT_0
    );
  EXP60_EXP_PT_1_1501 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP60_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_19_IBUF,
      I6 => NlwInverterSignal_EXP60_EXP_PT_1_IN6,
      O => EXP60_EXP_PT_1
    );
  EXP60_EXP_PT_2_1502 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP60_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP60_EXP_PT_2_IN5,
      I6 => REG_1_19,
      O => EXP60_EXP_PT_2
    );
  EXP60_EXP_tsimrenamed_net_Q_1503 : X_OR3
    port map (
      I0 => EXP60_EXP_PT_0,
      I1 => EXP60_EXP_PT_1,
      I2 => EXP60_EXP_PT_2,
      O => EXP60_EXP_tsimrenamed_net_Q
    );
  EXP61_EXP_1504 : X_BUF
    port map (
      I => EXP61_EXP_tsimrenamed_net_Q,
      O => EXP61_EXP
    );
  EXP61_EXP_PT_0_1505 : X_AND6
    port map (
      I0 => NlwInverterSignal_EXP61_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP61_EXP_PT_0_IN1,
      I2 => SHIFT_EN,
      I3 => readBufId(0),
      I4 => REG_1_16,
      I5 => NlwInverterSignal_EXP61_EXP_PT_0_IN5,
      O => EXP61_EXP_PT_0
    );
  EXP61_EXP_PT_1_1506 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP61_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_17_IBUF,
      I6 => NlwInverterSignal_EXP61_EXP_PT_1_IN6,
      O => EXP61_EXP_PT_1
    );
  EXP61_EXP_PT_2_1507 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP61_EXP_PT_2_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP61_EXP_PT_2_IN5,
      I6 => REG_1_17,
      O => EXP61_EXP_PT_2
    );
  EXP61_EXP_tsimrenamed_net_Q_1508 : X_OR3
    port map (
      I0 => EXP61_EXP_PT_0,
      I1 => EXP61_EXP_PT_1,
      I2 => EXP61_EXP_PT_2,
      O => EXP61_EXP_tsimrenamed_net_Q
    );
  EXP62_EXP_1509 : X_BUF
    port map (
      I => EXP62_EXP_tsimrenamed_net_Q,
      O => EXP62_EXP
    );
  EXP62_EXP_PT_0_1510 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP62_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_21_IBUF,
      I6 => NlwInverterSignal_EXP62_EXP_PT_0_IN6,
      O => EXP62_EXP_PT_0
    );
  EXP62_EXP_PT_1_1511 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP62_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP62_EXP_PT_1_IN5,
      I6 => REG_1_21,
      O => EXP62_EXP_PT_1
    );
  EXP62_EXP_tsimrenamed_net_Q_1512 : X_OR2
    port map (
      I0 => EXP62_EXP_PT_0,
      I1 => EXP62_EXP_PT_1,
      O => EXP62_EXP_tsimrenamed_net_Q
    );
  EXP63_EXP_1513 : X_BUF
    port map (
      I => EXP63_EXP_tsimrenamed_net_Q,
      O => EXP63_EXP
    );
  EXP63_EXP_PT_0_1514 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP63_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_20_IBUF,
      I6 => NlwInverterSignal_EXP63_EXP_PT_0_IN6,
      O => EXP63_EXP_PT_0
    );
  EXP63_EXP_PT_1_1515 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP63_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP63_EXP_PT_1_IN5,
      I6 => REG_1_20,
      O => EXP63_EXP_PT_1
    );
  EXP63_EXP_tsimrenamed_net_Q_1516 : X_OR2
    port map (
      I0 => EXP63_EXP_PT_0,
      I1 => EXP63_EXP_PT_1,
      O => EXP63_EXP_tsimrenamed_net_Q
    );
  EXP64_EXP_1517 : X_BUF
    port map (
      I => EXP64_EXP_tsimrenamed_net_Q,
      O => EXP64_EXP
    );
  EXP64_EXP_PT_0_1518 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP64_EXP_PT_0_IN0,
      I1 => NlwInverterSignal_EXP64_EXP_PT_0_IN1,
      I2 => state(1),
      O => EXP64_EXP_PT_0
    );
  EXP64_EXP_PT_1_1519 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP64_EXP_PT_1_IN0,
      I1 => state(0),
      I2 => state(1),
      O => EXP64_EXP_PT_1
    );
  EXP64_EXP_tsimrenamed_net_Q_1520 : X_OR2
    port map (
      I0 => EXP64_EXP_PT_0,
      I1 => EXP64_EXP_PT_1,
      O => EXP64_EXP_tsimrenamed_net_Q
    );
  EXP65_EXP_1521 : X_BUF
    port map (
      I => EXP65_EXP_tsimrenamed_net_Q,
      O => EXP65_EXP
    );
  EXP65_EXP_PT_0_1522 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP65_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP65_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP65_EXP_PT_0_IN4,
      I5 => DIN_10_IBUF,
      I6 => NlwInverterSignal_EXP65_EXP_PT_0_IN6,
      O => EXP65_EXP_PT_0
    );
  EXP65_EXP_PT_1_1523 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP65_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP65_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP65_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP65_EXP_PT_1_IN5,
      I6 => REG_0_10,
      O => EXP65_EXP_PT_1
    );
  EXP65_EXP_tsimrenamed_net_Q_1524 : X_OR2
    port map (
      I0 => EXP65_EXP_PT_0,
      I1 => EXP65_EXP_PT_1,
      O => EXP65_EXP_tsimrenamed_net_Q
    );
  EXP66_EXP_1525 : X_BUF
    port map (
      I => EXP66_EXP_tsimrenamed_net_Q,
      O => EXP66_EXP
    );
  EXP66_EXP_PT_0_1526 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP66_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP66_EXP_PT_0_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP66_EXP_PT_0_IN4,
      I5 => DIN_14_IBUF,
      I6 => NlwInverterSignal_EXP66_EXP_PT_0_IN6,
      O => EXP66_EXP_PT_0
    );
  EXP66_EXP_PT_1_1527 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP66_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => NlwInverterSignal_EXP66_EXP_PT_1_IN2,
      I3 => SHIFT_EN,
      I4 => NlwInverterSignal_EXP66_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP66_EXP_PT_1_IN5,
      I6 => REG_0_14,
      O => EXP66_EXP_PT_1
    );
  EXP66_EXP_tsimrenamed_net_Q_1528 : X_OR2
    port map (
      I0 => EXP66_EXP_PT_0,
      I1 => EXP66_EXP_PT_1,
      O => EXP66_EXP_tsimrenamed_net_Q
    );
  EXP67_EXP_1529 : X_BUF
    port map (
      I => EXP67_EXP_tsimrenamed_net_Q,
      O => EXP67_EXP
    );
  EXP67_EXP_PT_0_1530 : X_AND2
    port map (
      I0 => LOAD_PRESCALER_IBUF,
      I1 => count(0),
      O => EXP67_EXP_PT_0
    );
  EXP67_EXP_PT_1_1531 : X_AND3
    port map (
      I0 => NlwInverterSignal_EXP67_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP67_EXP_PT_1_IN1,
      I2 => NlwInverterSignal_EXP67_EXP_PT_1_IN2,
      O => EXP67_EXP_PT_1
    );
  EXP67_EXP_tsimrenamed_net_Q_1532 : X_OR2
    port map (
      I0 => EXP67_EXP_PT_0,
      I1 => EXP67_EXP_PT_1,
      O => EXP67_EXP_tsimrenamed_net_Q
    );
  EXP68_EXP_1533 : X_BUF
    port map (
      I => EXP68_EXP_tsimrenamed_net_Q,
      O => EXP68_EXP
    );
  EXP68_EXP_PT_0_1534 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP68_EXP_PT_0_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => DIN_28_IBUF,
      I6 => NlwInverterSignal_EXP68_EXP_PT_0_IN6,
      O => EXP68_EXP_PT_0
    );
  EXP68_EXP_PT_1_1535 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP68_EXP_PT_1_IN0,
      I1 => LOAD_SREG_IBUF,
      I2 => writeBufId(0),
      I3 => SHIFT_EN,
      I4 => readBufId(0),
      I5 => NlwInverterSignal_EXP68_EXP_PT_1_IN5,
      I6 => REG_1_28,
      O => EXP68_EXP_PT_1
    );
  EXP68_EXP_tsimrenamed_net_Q_1536 : X_OR2
    port map (
      I0 => EXP68_EXP_PT_0,
      I1 => EXP68_EXP_PT_1,
      O => EXP68_EXP_tsimrenamed_net_Q
    );
  EXP69_EXP_1537 : X_BUF
    port map (
      I => EXP69_EXP_tsimrenamed_net_Q,
      O => EXP69_EXP
    );
  EXP69_EXP_PT_0_1538 : X_AND2
    port map (
      I0 => LOAD_SREG_IBUF,
      I1 => LOAD_SREG_IBUF,
      O => EXP69_EXP_PT_0
    );
  EXP69_EXP_PT_1_1539 : X_AND7
    port map (
      I0 => NlwInverterSignal_EXP69_EXP_PT_1_IN0,
      I1 => NlwInverterSignal_EXP69_EXP_PT_1_IN1,
      I2 => NlwInverterSignal_EXP69_EXP_PT_1_IN2,
      I3 => NlwInverterSignal_EXP69_EXP_PT_1_IN3,
      I4 => NlwInverterSignal_EXP69_EXP_PT_1_IN4,
      I5 => NlwInverterSignal_EXP69_EXP_PT_1_IN5,
      I6 => NlwInverterSignal_EXP69_EXP_PT_1_IN6,
      O => EXP69_EXP_PT_1
    );
  EXP69_EXP_tsimrenamed_net_Q_1540 : X_OR2
    port map (
      I0 => EXP69_EXP_PT_0,
      I1 => EXP69_EXP_PT_1,
      O => EXP69_EXP_tsimrenamed_net_Q
    );
  NlwInverterBlock_SCLK_CE_IN0 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_SCLK_CE_IN0
    );
  NlwInverterBlock_SCLK_CE_IN2 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_SCLK_CE_IN2
    );
  NlwInverterBlock_SCLK_CE_IN3 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_SCLK_CE_IN3
    );
  NlwInverterBlock_SCLK_CE_IN4 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_SCLK_CE_IN4
    );
  NlwInverterBlock_SCLK_CE_IN5 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_SCLK_CE_IN5
    );
  NlwInverterBlock_SCLK_CE_IN6 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_SCLK_CE_IN6
    );
  NlwInverterBlock_readBufId_0_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_readBufId_0_CLKF_IN0
    );
  NlwInverterBlock_readBufId_0_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_readBufId_0_CLKF_IN1
    );
  NlwInverterBlock_readBufId_0_CE_IN0 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_readBufId_0_CE_IN0
    );
  NlwInverterBlock_readBufId_0_CE_IN1 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_readBufId_0_CE_IN1
    );
  NlwInverterBlock_readBufId_0_CE_IN2 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_readBufId_0_CE_IN2
    );
  NlwInverterBlock_readBufId_0_CE_IN3 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_readBufId_0_CE_IN3
    );
  NlwInverterBlock_readBufId_0_CE_IN4 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_readBufId_0_CE_IN4
    );
  NlwInverterBlock_readBufId_0_CE_IN5 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_readBufId_0_CE_IN5
    );
  NlwInverterBlock_buf_depth_0_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => buf_depth_0_RSTF,
      O => NlwInverterSignal_buf_depth_0_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_buf_depth_0_D2_PT_0_IN1 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_buf_depth_0_D2_PT_0_IN1
    );
  NlwInverterBlock_buf_depth_0_D2_PT_0_IN2 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_buf_depth_0_D2_PT_0_IN2
    );
  NlwInverterBlock_buf_depth_0_D2_PT_0_IN3 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_buf_depth_0_D2_PT_0_IN3
    );
  NlwInverterBlock_buf_depth_0_D2_PT_0_IN4 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_buf_depth_0_D2_PT_0_IN4
    );
  NlwInverterBlock_buf_depth_0_D2_PT_0_IN5 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_buf_depth_0_D2_PT_0_IN5
    );
  NlwInverterBlock_buf_depth_0_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN0
    );
  NlwInverterBlock_buf_depth_0_D2_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN2
    );
  NlwInverterBlock_buf_depth_0_D2_PT_1_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN3
    );
  NlwInverterBlock_buf_depth_0_D2_PT_1_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN4
    );
  NlwInverterBlock_buf_depth_0_D2_PT_1_IN5 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN5
    );
  NlwInverterBlock_buf_depth_0_D2_PT_1_IN6 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_buf_depth_0_D2_PT_1_IN6
    );
  NlwInverterBlock_buf_depth_0_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_buf_depth_0_CLKF_IN0
    );
  NlwInverterBlock_buf_depth_0_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_buf_depth_0_CLKF_IN1
    );
  NlwInverterBlock_buf_depth_0_SETF_IN1 : X_INV
    port map (
      I => buf_depth(0),
      O => NlwInverterSignal_buf_depth_0_SETF_IN1
    );
  NlwInverterBlock_buf_depth_0_SETF_IN2 : X_INV
    port map (
      I => buf_depth(1),
      O => NlwInverterSignal_buf_depth_0_SETF_IN2
    );
  NlwInverterBlock_buf_depth_1_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => buf_depth_1_RSTF,
      O => NlwInverterSignal_buf_depth_1_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_buf_depth_1_D2_PT_0_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_buf_depth_1_D2_PT_0_IN2
    );
  NlwInverterBlock_buf_depth_1_D2_PT_0_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_buf_depth_1_D2_PT_0_IN3
    );
  NlwInverterBlock_buf_depth_1_D2_PT_0_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_buf_depth_1_D2_PT_0_IN4
    );
  NlwInverterBlock_buf_depth_1_D2_PT_0_IN5 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_buf_depth_1_D2_PT_0_IN5
    );
  NlwInverterBlock_buf_depth_1_D2_PT_0_IN6 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_buf_depth_1_D2_PT_0_IN6
    );
  NlwInverterBlock_buf_depth_1_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN0
    );
  NlwInverterBlock_buf_depth_1_D2_PT_1_IN1 : X_INV
    port map (
      I => buf_depth(0),
      O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN1
    );
  NlwInverterBlock_buf_depth_1_D2_PT_1_IN3 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN3
    );
  NlwInverterBlock_buf_depth_1_D2_PT_1_IN4 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN4
    );
  NlwInverterBlock_buf_depth_1_D2_PT_1_IN5 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN5
    );
  NlwInverterBlock_buf_depth_1_D2_PT_1_IN6 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN6
    );
  NlwInverterBlock_buf_depth_1_D2_PT_1_IN7 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_buf_depth_1_D2_PT_1_IN7
    );
  NlwInverterBlock_buf_depth_1_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_buf_depth_1_CLKF_IN0
    );
  NlwInverterBlock_buf_depth_1_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_buf_depth_1_CLKF_IN1
    );
  NlwInverterBlock_buf_depth_1_SETF_IN2 : X_INV
    port map (
      I => buf_depth(1),
      O => NlwInverterSignal_buf_depth_1_SETF_IN2
    );
  NlwInverterBlock_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SHIFT_CNT_0_RSTF,
      O => NlwInverterSignal_SHIFT_CNT_0_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SHIFT_CNT_0_D_IN0 : X_INV
    port map (
      I => SHIFT_CNT_0_D1,
      O => NlwInverterSignal_SHIFT_CNT_0_D_IN0
    );
  NlwInverterBlock_SHIFT_CNT_0_D2_PT_0_IN0 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN0
    );
  NlwInverterBlock_SHIFT_CNT_0_D2_PT_0_IN1 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_0_D2_PT_0_IN1
    );
  NlwInverterBlock_SHIFT_CNT_0_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_CNT_0_CLKF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_0_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_CNT_0_CLKF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_0_SETF_IN1 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_0_SETF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_0_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_SHIFT_CNT_0_EXP_tsimrenamed_net_IN1 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN1
    );
  NlwInverterBlock_SHIFT_CNT_0_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_SHIFT_CNT_0_EXP_tsimrenamed_net_IN3 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN3
    );
  NlwInverterBlock_SHIFT_CNT_0_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_SHIFT_CNT_0_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_count_0_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_0_RSTF,
      O => NlwInverterSignal_count_0_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_0_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_0_D2_PT_1_IN1
    );
  NlwInverterBlock_count_0_D2_PT_2_IN0 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_0_D2_PT_2_IN0
    );
  NlwInverterBlock_count_0_D2_PT_2_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_0_D2_PT_2_IN1
    );
  NlwInverterBlock_count_0_D2_PT_2_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_0_D2_PT_2_IN2
    );
  NlwInverterBlock_count_0_D2_PT_2_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_0_D2_PT_2_IN3
    );
  NlwInverterBlock_count_0_D2_PT_2_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_0_D2_PT_2_IN4
    );
  NlwInverterBlock_count_0_D2_PT_2_IN5 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_0_D2_PT_2_IN5
    );
  NlwInverterBlock_count_0_RSTF_IN1 : X_INV
    port map (
      I => CLK_SCALE(0),
      O => NlwInverterSignal_count_0_RSTF_IN1
    );
  NlwInverterBlock_count_0_EXP_tsimrenamed_net_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN1
    );
  NlwInverterBlock_count_0_EXP_tsimrenamed_net_IN3 : X_INV
    port map (
      I => CLK_SCALE(2),
      O => NlwInverterSignal_count_0_EXP_tsimrenamed_net_IN3
    );
  NlwInverterBlock_count_4_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_4_RSTF,
      O => NlwInverterSignal_count_4_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_4_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_4_D2_PT_1_IN0
    );
  NlwInverterBlock_count_4_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_4_D2_PT_1_IN1
    );
  NlwInverterBlock_count_4_D2_PT_1_IN2 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_4_D2_PT_1_IN2
    );
  NlwInverterBlock_count_4_D2_PT_1_IN3 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_4_D2_PT_1_IN3
    );
  NlwInverterBlock_count_4_D2_PT_1_IN4 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_4_D2_PT_1_IN4
    );
  NlwInverterBlock_count_4_D2_PT_1_IN5 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_4_D2_PT_1_IN5
    );
  NlwInverterBlock_count_4_D2_PT_2_IN0 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_4_D2_PT_2_IN0
    );
  NlwInverterBlock_count_4_D2_PT_2_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_4_D2_PT_2_IN1
    );
  NlwInverterBlock_count_4_D2_PT_2_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_4_D2_PT_2_IN2
    );
  NlwInverterBlock_count_4_D2_PT_2_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_4_D2_PT_2_IN3
    );
  NlwInverterBlock_count_4_D2_PT_2_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_4_D2_PT_2_IN4
    );
  NlwInverterBlock_count_4_D2_PT_2_IN5 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_4_D2_PT_2_IN5
    );
  NlwInverterBlock_count_4_RSTF_IN1 : X_INV
    port map (
      I => CLK_SCALE(4),
      O => NlwInverterSignal_count_4_RSTF_IN1
    );
  NlwInverterBlock_count_4_EXP_tsimrenamed_net_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN1
    );
  NlwInverterBlock_count_4_EXP_tsimrenamed_net_IN3 : X_INV
    port map (
      I => CLK_SCALE(3),
      O => NlwInverterSignal_count_4_EXP_tsimrenamed_net_IN3
    );
  NlwInverterBlock_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SHIFT_CNT_1_RSTF,
      O => NlwInverterSignal_SHIFT_CNT_1_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SHIFT_CNT_1_D_IN0 : X_INV
    port map (
      I => SHIFT_CNT_1_D1,
      O => NlwInverterSignal_SHIFT_CNT_1_D_IN0
    );
  NlwInverterBlock_SHIFT_CNT_1_D2_PT_1_IN0 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN0
    );
  NlwInverterBlock_SHIFT_CNT_1_D2_PT_1_IN1 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_1_D2_PT_1_IN1
    );
  NlwInverterBlock_SHIFT_CNT_1_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_CNT_1_CLKF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_1_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_CNT_1_CLKF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_1_SETF_IN1 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_1_SETF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SHIFT_CNT_2_RSTF,
      O => NlwInverterSignal_SHIFT_CNT_2_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SHIFT_CNT_2_D_IN0 : X_INV
    port map (
      I => SHIFT_CNT_2_D1,
      O => NlwInverterSignal_SHIFT_CNT_2_D_IN0
    );
  NlwInverterBlock_SHIFT_CNT_2_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_CNT_2_CLKF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_2_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_CNT_2_CLKF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_2_SETF_IN1 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_2_SETF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => buf_depth(0),
      O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN1 : X_INV
    port map (
      I => buf_depth(1),
      O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN1
    );
  NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN3 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN3
    );
  NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_SHIFT_CNT_2_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_SHIFT_CNT_2_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SHIFT_CNT_3_RSTF,
      O => NlwInverterSignal_SHIFT_CNT_3_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SHIFT_CNT_3_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN0
    );
  NlwInverterBlock_SHIFT_CNT_3_D2_PT_1_IN1 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN1
    );
  NlwInverterBlock_SHIFT_CNT_3_D2_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN2
    );
  NlwInverterBlock_SHIFT_CNT_3_D2_PT_1_IN3 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SHIFT_CNT_3_D2_PT_1_IN3
    );
  NlwInverterBlock_SHIFT_CNT_3_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_CNT_3_CLKF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_3_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_CNT_3_CLKF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_3_SETF_IN1 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_3_SETF_IN1
    );
  NlwInverterBlock_count_1_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_1_RSTF,
      O => NlwInverterSignal_count_1_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_1_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_1_D2_PT_1_IN0
    );
  NlwInverterBlock_count_1_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_1_D2_PT_1_IN1
    );
  NlwInverterBlock_count_1_D2_PT_1_IN2 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_1_D2_PT_1_IN2
    );
  NlwInverterBlock_count_1_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_1_D2_PT_2_IN1
    );
  NlwInverterBlock_count_1_D2_PT_2_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_1_D2_PT_2_IN2
    );
  NlwInverterBlock_count_1_D2_PT_3_IN0 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_1_D2_PT_3_IN0
    );
  NlwInverterBlock_count_1_D2_PT_3_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_1_D2_PT_3_IN1
    );
  NlwInverterBlock_count_1_D2_PT_3_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_1_D2_PT_3_IN2
    );
  NlwInverterBlock_count_1_D2_PT_3_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_1_D2_PT_3_IN3
    );
  NlwInverterBlock_count_1_D2_PT_3_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_1_D2_PT_3_IN4
    );
  NlwInverterBlock_count_1_D2_PT_3_IN5 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_1_D2_PT_3_IN5
    );
  NlwInverterBlock_count_1_RSTF_IN1 : X_INV
    port map (
      I => CLK_SCALE(1),
      O => NlwInverterSignal_count_1_RSTF_IN1
    );
  NlwInverterBlock_count_2_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_2_RSTF,
      O => NlwInverterSignal_count_2_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_2_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_2_D2_PT_1_IN1
    );
  NlwInverterBlock_count_2_D2_PT_1_IN2 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_2_D2_PT_1_IN2
    );
  NlwInverterBlock_count_2_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_2_D2_PT_2_IN0
    );
  NlwInverterBlock_count_2_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_2_D2_PT_2_IN1
    );
  NlwInverterBlock_count_2_D2_PT_2_IN2 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_2_D2_PT_2_IN2
    );
  NlwInverterBlock_count_2_D2_PT_2_IN3 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_2_D2_PT_2_IN3
    );
  NlwInverterBlock_count_2_D2_PT_3_IN0 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_2_D2_PT_3_IN0
    );
  NlwInverterBlock_count_2_D2_PT_3_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_2_D2_PT_3_IN1
    );
  NlwInverterBlock_count_2_D2_PT_3_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_2_D2_PT_3_IN2
    );
  NlwInverterBlock_count_2_D2_PT_3_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_2_D2_PT_3_IN3
    );
  NlwInverterBlock_count_2_D2_PT_3_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_2_D2_PT_3_IN4
    );
  NlwInverterBlock_count_2_D2_PT_3_IN5 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_2_D2_PT_3_IN5
    );
  NlwInverterBlock_count_2_RSTF_IN1 : X_INV
    port map (
      I => CLK_SCALE(2),
      O => NlwInverterSignal_count_2_RSTF_IN1
    );
  NlwInverterBlock_count_3_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_3_RSTF,
      O => NlwInverterSignal_count_3_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_3_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_3_D2_PT_1_IN1
    );
  NlwInverterBlock_count_3_D2_PT_1_IN2 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_3_D2_PT_1_IN2
    );
  NlwInverterBlock_count_3_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_count_3_D2_PT_2_IN0
    );
  NlwInverterBlock_count_3_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_3_D2_PT_2_IN1
    );
  NlwInverterBlock_count_3_D2_PT_2_IN2 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_count_3_D2_PT_2_IN2
    );
  NlwInverterBlock_count_3_D2_PT_2_IN3 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_3_D2_PT_2_IN3
    );
  NlwInverterBlock_count_3_D2_PT_2_IN4 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_3_D2_PT_2_IN4
    );
  NlwInverterBlock_count_3_D2_PT_3_IN0 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_3_D2_PT_3_IN0
    );
  NlwInverterBlock_count_3_D2_PT_3_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_count_3_D2_PT_3_IN1
    );
  NlwInverterBlock_count_3_D2_PT_3_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_count_3_D2_PT_3_IN2
    );
  NlwInverterBlock_count_3_D2_PT_3_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_count_3_D2_PT_3_IN3
    );
  NlwInverterBlock_count_3_D2_PT_3_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_count_3_D2_PT_3_IN4
    );
  NlwInverterBlock_count_3_D2_PT_3_IN5 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_3_D2_PT_3_IN5
    );
  NlwInverterBlock_count_3_RSTF_IN1 : X_INV
    port map (
      I => CLK_SCALE(3),
      O => NlwInverterSignal_count_3_RSTF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SHIFT_CNT_4_RSTF,
      O => NlwInverterSignal_SHIFT_CNT_4_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SHIFT_CNT_4_D2_PT_1_IN0 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN0
    );
  NlwInverterBlock_SHIFT_CNT_4_D2_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN2
    );
  NlwInverterBlock_SHIFT_CNT_4_D2_PT_1_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN3
    );
  NlwInverterBlock_SHIFT_CNT_4_D2_PT_1_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN4
    );
  NlwInverterBlock_SHIFT_CNT_4_D2_PT_1_IN5 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_1_IN5
    );
  NlwInverterBlock_SHIFT_CNT_4_D2_PT_2_IN0 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN0
    );
  NlwInverterBlock_SHIFT_CNT_4_D2_PT_2_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN2
    );
  NlwInverterBlock_SHIFT_CNT_4_D2_PT_2_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN3
    );
  NlwInverterBlock_SHIFT_CNT_4_D2_PT_2_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN4
    );
  NlwInverterBlock_SHIFT_CNT_4_D2_PT_2_IN5 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_SHIFT_CNT_4_D2_PT_2_IN5
    );
  NlwInverterBlock_SHIFT_CNT_4_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_CNT_4_CLKF_IN0
    );
  NlwInverterBlock_SHIFT_CNT_4_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_SHIFT_CNT_4_CLKF_IN1
    );
  NlwInverterBlock_SHIFT_CNT_4_SETF_IN1 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_SHIFT_CNT_4_SETF_IN1
    );
  NlwInverterBlock_count_5_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => count_5_RSTF,
      O => NlwInverterSignal_count_5_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_count_5_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_5_D2_PT_1_IN1
    );
  NlwInverterBlock_count_5_D2_PT_1_IN3 : X_INV
    port map (
      I => CLK_SCALE(5),
      O => NlwInverterSignal_count_5_D2_PT_1_IN3
    );
  NlwInverterBlock_count_5_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_5_D2_PT_2_IN1
    );
  NlwInverterBlock_count_5_D2_PT_2_IN2 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_count_5_D2_PT_2_IN2
    );
  NlwInverterBlock_count_5_RSTF_IN1 : X_INV
    port map (
      I => CLK_SCALE(5),
      O => NlwInverterSignal_count_5_RSTF_IN1
    );
  NlwInverterBlock_count_5_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_count_5_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_writeBufId_0_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_writeBufId_0_CLKF_IN0
    );
  NlwInverterBlock_writeBufId_0_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_writeBufId_0_CLKF_IN1
    );
  NlwInverterBlock_writeBufId_0_CE_IN0 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_writeBufId_0_CE_IN0
    );
  NlwInverterBlock_writeBufId_0_CE_IN1 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_writeBufId_0_CE_IN1
    );
  NlwInverterBlock_writeBufId_0_CE_IN2 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_writeBufId_0_CE_IN2
    );
  NlwInverterBlock_writeBufId_0_CE_IN3 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_writeBufId_0_CE_IN3
    );
  NlwInverterBlock_writeBufId_0_CE_IN4 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_writeBufId_0_CE_IN4
    );
  NlwInverterBlock_writeBufId_0_CE_IN5 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_writeBufId_0_CE_IN5
    );
  NlwInverterBlock_CLK_SCALE_0_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN1
    );
  NlwInverterBlock_CLK_SCALE_0_EXP_PT_0_IN3 : X_INV
    port map (
      I => CLK_SCALE(4),
      O => NlwInverterSignal_CLK_SCALE_0_EXP_PT_0_IN3
    );
  NlwInverterBlock_CLK_SCALE_0_EXP_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN1
    );
  NlwInverterBlock_CLK_SCALE_0_EXP_PT_1_IN2 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_CLK_SCALE_0_EXP_PT_1_IN2
    );
  NlwInverterBlock_REG_0_0_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_0_RSTF,
      O => NlwInverterSignal_REG_0_0_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_0_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_0_CLKF_IN0
    );
  NlwInverterBlock_REG_0_0_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_0_CLKF_IN1
    );
  NlwInverterBlock_REG_0_0_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_0_SETF_IN1
    );
  NlwInverterBlock_REG_0_0_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_0_RSTF_IN1
    );
  NlwInverterBlock_REG_0_0_RSTF_IN2 : X_INV
    port map (
      I => DIN_0_IBUF,
      O => NlwInverterSignal_REG_0_0_RSTF_IN2
    );
  NlwInverterBlock_REG_0_0_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_0_EXP_PT_0_IN0
    );
  NlwInverterBlock_REG_0_0_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_0_EXP_PT_0_IN2
    );
  NlwInverterBlock_REG_0_0_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_0_EXP_PT_0_IN4
    );
  NlwInverterBlock_REG_0_0_EXP_PT_0_IN6 : X_INV
    port map (
      I => DIN_4_IBUF,
      O => NlwInverterSignal_REG_0_0_EXP_PT_0_IN6
    );
  NlwInverterBlock_REG_0_0_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_0_EXP_PT_1_IN0
    );
  NlwInverterBlock_REG_0_0_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_0_EXP_PT_1_IN2
    );
  NlwInverterBlock_REG_0_0_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_0_EXP_PT_1_IN4
    );
  NlwInverterBlock_REG_0_0_EXP_PT_1_IN5 : X_INV
    port map (
      I => REG_0_4,
      O => NlwInverterSignal_REG_0_0_EXP_PT_1_IN5
    );
  NlwInverterBlock_REG_0_1_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_1_RSTF,
      O => NlwInverterSignal_REG_0_1_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_1_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_1_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_1_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_1_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_1_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_1_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_1_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_1,
      O => NlwInverterSignal_REG_0_1_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_1_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_1_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_1_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_1_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_1_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_1_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_1_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_0,
      O => NlwInverterSignal_REG_0_1_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_1_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_1_CLKF_IN0
    );
  NlwInverterBlock_REG_0_1_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_1_CLKF_IN1
    );
  NlwInverterBlock_REG_0_1_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_1_SETF_IN1
    );
  NlwInverterBlock_REG_0_1_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_1_RSTF_IN1
    );
  NlwInverterBlock_REG_0_1_RSTF_IN2 : X_INV
    port map (
      I => DIN_1_IBUF,
      O => NlwInverterSignal_REG_0_1_RSTF_IN2
    );
  NlwInverterBlock_REG_0_10_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_10_RSTF,
      O => NlwInverterSignal_REG_0_10_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_10_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_10_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_10_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_10_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_10_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_10_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_10_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_9,
      O => NlwInverterSignal_REG_0_10_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_10_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_10_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_10_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_10_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_10_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_10_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_10_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_10,
      O => NlwInverterSignal_REG_0_10_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_10_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_10_CLKF_IN0
    );
  NlwInverterBlock_REG_0_10_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_10_CLKF_IN1
    );
  NlwInverterBlock_REG_0_10_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_10_SETF_IN1
    );
  NlwInverterBlock_REG_0_10_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_10_RSTF_IN1
    );
  NlwInverterBlock_REG_0_10_RSTF_IN2 : X_INV
    port map (
      I => DIN_10_IBUF,
      O => NlwInverterSignal_REG_0_10_RSTF_IN2
    );
  NlwInverterBlock_REG_0_11_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_11_RSTF,
      O => NlwInverterSignal_REG_0_11_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_11_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_11_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_11_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_11_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_11_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_11_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_11_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_11,
      O => NlwInverterSignal_REG_0_11_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_11_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_11_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_11_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_11_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_11_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_11_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_11_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_10,
      O => NlwInverterSignal_REG_0_11_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_11_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_11_CLKF_IN0
    );
  NlwInverterBlock_REG_0_11_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_11_CLKF_IN1
    );
  NlwInverterBlock_REG_0_11_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_11_SETF_IN1
    );
  NlwInverterBlock_REG_0_11_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_11_RSTF_IN1
    );
  NlwInverterBlock_REG_0_11_RSTF_IN2 : X_INV
    port map (
      I => DIN_11_IBUF,
      O => NlwInverterSignal_REG_0_11_RSTF_IN2
    );
  NlwInverterBlock_REG_0_12_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_12_RSTF,
      O => NlwInverterSignal_REG_0_12_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_12_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_12_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_12_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_12_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_12_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_12_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_12_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_12,
      O => NlwInverterSignal_REG_0_12_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_12_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_12_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_12_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_12_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_12_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_12_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_12_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_11,
      O => NlwInverterSignal_REG_0_12_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_12_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_12_CLKF_IN0
    );
  NlwInverterBlock_REG_0_12_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_12_CLKF_IN1
    );
  NlwInverterBlock_REG_0_12_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_12_SETF_IN1
    );
  NlwInverterBlock_REG_0_12_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_12_RSTF_IN1
    );
  NlwInverterBlock_REG_0_12_RSTF_IN2 : X_INV
    port map (
      I => DIN_12_IBUF,
      O => NlwInverterSignal_REG_0_12_RSTF_IN2
    );
  NlwInverterBlock_REG_0_13_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_13_RSTF,
      O => NlwInverterSignal_REG_0_13_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_13_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_13_CLKF_IN0
    );
  NlwInverterBlock_REG_0_13_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_13_CLKF_IN1
    );
  NlwInverterBlock_REG_0_13_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_13_SETF_IN1
    );
  NlwInverterBlock_REG_0_13_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_13_RSTF_IN1
    );
  NlwInverterBlock_REG_0_13_RSTF_IN2 : X_INV
    port map (
      I => DIN_13_IBUF,
      O => NlwInverterSignal_REG_0_13_RSTF_IN2
    );
  NlwInverterBlock_REG_0_13_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_13_EXP_PT_0_IN0
    );
  NlwInverterBlock_REG_0_13_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_13_EXP_PT_0_IN2
    );
  NlwInverterBlock_REG_0_13_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_13_EXP_PT_0_IN4
    );
  NlwInverterBlock_REG_0_13_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_12,
      O => NlwInverterSignal_REG_0_13_EXP_PT_0_IN6
    );
  NlwInverterBlock_REG_0_13_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_13_EXP_PT_1_IN0
    );
  NlwInverterBlock_REG_0_13_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_13_EXP_PT_1_IN2
    );
  NlwInverterBlock_REG_0_13_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_13_EXP_PT_1_IN4
    );
  NlwInverterBlock_REG_0_13_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_12_IBUF,
      O => NlwInverterSignal_REG_0_13_EXP_PT_1_IN5
    );
  NlwInverterBlock_REG_0_14_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_14_RSTF,
      O => NlwInverterSignal_REG_0_14_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_14_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_14_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_14_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_14_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_14_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_14_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_14_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_14,
      O => NlwInverterSignal_REG_0_14_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_14_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_14_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_14_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_14_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_14_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_14_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_14_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_13,
      O => NlwInverterSignal_REG_0_14_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_14_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_14_CLKF_IN0
    );
  NlwInverterBlock_REG_0_14_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_14_CLKF_IN1
    );
  NlwInverterBlock_REG_0_14_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_14_SETF_IN1
    );
  NlwInverterBlock_REG_0_14_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_14_RSTF_IN1
    );
  NlwInverterBlock_REG_0_14_RSTF_IN2 : X_INV
    port map (
      I => DIN_14_IBUF,
      O => NlwInverterSignal_REG_0_14_RSTF_IN2
    );
  NlwInverterBlock_REG_0_15_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_15_RSTF,
      O => NlwInverterSignal_REG_0_15_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_15_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_15_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_15_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_15_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_15_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_15_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_15_D2_PT_1_IN4 : X_INV
    port map (
      I => REG_0_14,
      O => NlwInverterSignal_REG_0_15_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_0_15_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_15_CLKF_IN0
    );
  NlwInverterBlock_REG_0_15_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_15_CLKF_IN1
    );
  NlwInverterBlock_REG_0_15_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_15_SETF_IN1
    );
  NlwInverterBlock_REG_0_15_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_15_RSTF_IN1
    );
  NlwInverterBlock_REG_0_15_RSTF_IN2 : X_INV
    port map (
      I => DIN_15_IBUF,
      O => NlwInverterSignal_REG_0_15_RSTF_IN2
    );
  NlwInverterBlock_REG_0_15_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_0_15_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_REG_0_15_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_REG_0_15_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => REG_0_16,
      O => NlwInverterSignal_REG_0_15_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_REG_0_16_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_16_RSTF,
      O => NlwInverterSignal_REG_0_16_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_16_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_16_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_16_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_16_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_16_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_16_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_16_D2_PT_2_IN5 : X_INV
    port map (
      I => REG_0_16,
      O => NlwInverterSignal_REG_0_16_D2_PT_2_IN5
    );
  NlwInverterBlock_REG_0_16_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_16_D2_PT_3_IN0
    );
  NlwInverterBlock_REG_0_16_D2_PT_3_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_16_D2_PT_3_IN1
    );
  NlwInverterBlock_REG_0_16_D2_PT_3_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_16_D2_PT_3_IN3
    );
  NlwInverterBlock_REG_0_16_D2_PT_3_IN4 : X_INV
    port map (
      I => REG_0_15,
      O => NlwInverterSignal_REG_0_16_D2_PT_3_IN4
    );
  NlwInverterBlock_REG_0_16_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_16_CLKF_IN0
    );
  NlwInverterBlock_REG_0_16_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_16_CLKF_IN1
    );
  NlwInverterBlock_REG_0_16_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_16_SETF_IN1
    );
  NlwInverterBlock_REG_0_16_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_16_RSTF_IN1
    );
  NlwInverterBlock_REG_0_16_RSTF_IN2 : X_INV
    port map (
      I => DIN_16_IBUF,
      O => NlwInverterSignal_REG_0_16_RSTF_IN2
    );
  NlwInverterBlock_REG_0_17_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_17_RSTF,
      O => NlwInverterSignal_REG_0_17_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_17_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_17_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_17_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_17_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_17_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_17_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_17_D2_PT_1_IN4 : X_INV
    port map (
      I => REG_0_16,
      O => NlwInverterSignal_REG_0_17_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_0_17_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_17_CLKF_IN0
    );
  NlwInverterBlock_REG_0_17_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_17_CLKF_IN1
    );
  NlwInverterBlock_REG_0_17_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_17_SETF_IN1
    );
  NlwInverterBlock_REG_0_17_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_17_RSTF_IN1
    );
  NlwInverterBlock_REG_0_17_RSTF_IN2 : X_INV
    port map (
      I => DIN_17_IBUF,
      O => NlwInverterSignal_REG_0_17_RSTF_IN2
    );
  NlwInverterBlock_REG_0_17_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_0_17_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_REG_0_17_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_REG_0_17_EXP_tsimrenamed_net_IN6 : X_INV
    port map (
      I => DIN_16_IBUF,
      O => NlwInverterSignal_REG_0_17_EXP_tsimrenamed_net_IN6
    );
  NlwInverterBlock_REG_0_18_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_18_RSTF,
      O => NlwInverterSignal_REG_0_18_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_18_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_18_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_18_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_18_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_18_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_18_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_18_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_18,
      O => NlwInverterSignal_REG_0_18_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_18_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_18_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_18_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_18_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_18_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_18_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_18_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_17,
      O => NlwInverterSignal_REG_0_18_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_18_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_18_CLKF_IN0
    );
  NlwInverterBlock_REG_0_18_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_18_CLKF_IN1
    );
  NlwInverterBlock_REG_0_18_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_18_SETF_IN1
    );
  NlwInverterBlock_REG_0_18_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_18_RSTF_IN1
    );
  NlwInverterBlock_REG_0_18_RSTF_IN2 : X_INV
    port map (
      I => DIN_18_IBUF,
      O => NlwInverterSignal_REG_0_18_RSTF_IN2
    );
  NlwInverterBlock_REG_0_19_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_19_RSTF,
      O => NlwInverterSignal_REG_0_19_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_19_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_19_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_19_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_19_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_19_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_19_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_19_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_19,
      O => NlwInverterSignal_REG_0_19_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_19_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_19_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_19_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_19_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_19_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_19_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_19_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_18,
      O => NlwInverterSignal_REG_0_19_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_19_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_19_CLKF_IN0
    );
  NlwInverterBlock_REG_0_19_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_19_CLKF_IN1
    );
  NlwInverterBlock_REG_0_19_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_19_SETF_IN1
    );
  NlwInverterBlock_REG_0_19_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_19_RSTF_IN1
    );
  NlwInverterBlock_REG_0_19_RSTF_IN2 : X_INV
    port map (
      I => DIN_19_IBUF,
      O => NlwInverterSignal_REG_0_19_RSTF_IN2
    );
  NlwInverterBlock_REG_0_2_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_2_RSTF,
      O => NlwInverterSignal_REG_0_2_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_2_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_2_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_2_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_2_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_2_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_2_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_2_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_2,
      O => NlwInverterSignal_REG_0_2_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_2_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_2_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_2_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_2_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_2_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_2_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_2_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_1,
      O => NlwInverterSignal_REG_0_2_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_2_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_2_CLKF_IN0
    );
  NlwInverterBlock_REG_0_2_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_2_CLKF_IN1
    );
  NlwInverterBlock_REG_0_2_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_2_SETF_IN1
    );
  NlwInverterBlock_REG_0_2_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_2_RSTF_IN1
    );
  NlwInverterBlock_REG_0_2_RSTF_IN2 : X_INV
    port map (
      I => DIN_2_IBUF,
      O => NlwInverterSignal_REG_0_2_RSTF_IN2
    );
  NlwInverterBlock_REG_0_20_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_20_RSTF,
      O => NlwInverterSignal_REG_0_20_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_20_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_20_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_20_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_20_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_20_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_20_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_20_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_20,
      O => NlwInverterSignal_REG_0_20_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_20_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_20_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_20_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_20_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_20_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_20_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_20_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_19,
      O => NlwInverterSignal_REG_0_20_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_20_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_20_CLKF_IN0
    );
  NlwInverterBlock_REG_0_20_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_20_CLKF_IN1
    );
  NlwInverterBlock_REG_0_20_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_20_SETF_IN1
    );
  NlwInverterBlock_REG_0_20_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_20_RSTF_IN1
    );
  NlwInverterBlock_REG_0_20_RSTF_IN2 : X_INV
    port map (
      I => DIN_20_IBUF,
      O => NlwInverterSignal_REG_0_20_RSTF_IN2
    );
  NlwInverterBlock_REG_0_21_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_21_RSTF,
      O => NlwInverterSignal_REG_0_21_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_21_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_21_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_21_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_21_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_21_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_21_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_21_D2_PT_1_IN4 : X_INV
    port map (
      I => REG_0_20,
      O => NlwInverterSignal_REG_0_21_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_0_21_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_21_CLKF_IN0
    );
  NlwInverterBlock_REG_0_21_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_21_CLKF_IN1
    );
  NlwInverterBlock_REG_0_21_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_21_SETF_IN1
    );
  NlwInverterBlock_REG_0_21_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_21_RSTF_IN1
    );
  NlwInverterBlock_REG_0_21_RSTF_IN2 : X_INV
    port map (
      I => DIN_21_IBUF,
      O => NlwInverterSignal_REG_0_21_RSTF_IN2
    );
  NlwInverterBlock_REG_0_21_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_0_21_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_REG_0_21_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_REG_0_21_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => REG_0_22,
      O => NlwInverterSignal_REG_0_21_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_REG_0_22_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_22_RSTF,
      O => NlwInverterSignal_REG_0_22_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_22_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_22_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_22_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_22_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_22_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_22_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_22_D2_PT_2_IN5 : X_INV
    port map (
      I => REG_0_22,
      O => NlwInverterSignal_REG_0_22_D2_PT_2_IN5
    );
  NlwInverterBlock_REG_0_22_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_22_D2_PT_3_IN0
    );
  NlwInverterBlock_REG_0_22_D2_PT_3_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_22_D2_PT_3_IN1
    );
  NlwInverterBlock_REG_0_22_D2_PT_3_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_22_D2_PT_3_IN3
    );
  NlwInverterBlock_REG_0_22_D2_PT_3_IN4 : X_INV
    port map (
      I => REG_0_21,
      O => NlwInverterSignal_REG_0_22_D2_PT_3_IN4
    );
  NlwInverterBlock_REG_0_22_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_22_CLKF_IN0
    );
  NlwInverterBlock_REG_0_22_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_22_CLKF_IN1
    );
  NlwInverterBlock_REG_0_22_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_22_SETF_IN1
    );
  NlwInverterBlock_REG_0_22_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_22_RSTF_IN1
    );
  NlwInverterBlock_REG_0_22_RSTF_IN2 : X_INV
    port map (
      I => DIN_22_IBUF,
      O => NlwInverterSignal_REG_0_22_RSTF_IN2
    );
  NlwInverterBlock_REG_0_23_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_23_RSTF,
      O => NlwInverterSignal_REG_0_23_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_23_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_23_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_23_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_23_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_23_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_23_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_23_D2_PT_1_IN4 : X_INV
    port map (
      I => REG_0_22,
      O => NlwInverterSignal_REG_0_23_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_0_23_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_23_CLKF_IN0
    );
  NlwInverterBlock_REG_0_23_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_23_CLKF_IN1
    );
  NlwInverterBlock_REG_0_23_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_23_SETF_IN1
    );
  NlwInverterBlock_REG_0_23_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_23_RSTF_IN1
    );
  NlwInverterBlock_REG_0_23_RSTF_IN2 : X_INV
    port map (
      I => DIN_23_IBUF,
      O => NlwInverterSignal_REG_0_23_RSTF_IN2
    );
  NlwInverterBlock_REG_0_23_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_0_23_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_REG_0_23_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_REG_0_23_EXP_tsimrenamed_net_IN6 : X_INV
    port map (
      I => DIN_22_IBUF,
      O => NlwInverterSignal_REG_0_23_EXP_tsimrenamed_net_IN6
    );
  NlwInverterBlock_REG_0_24_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_24_RSTF,
      O => NlwInverterSignal_REG_0_24_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_24_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_24_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_24_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_24_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_24_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_24_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_24_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_24,
      O => NlwInverterSignal_REG_0_24_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_24_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_24_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_24_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_24_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_24_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_24_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_24_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_23,
      O => NlwInverterSignal_REG_0_24_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_24_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_24_CLKF_IN0
    );
  NlwInverterBlock_REG_0_24_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_24_CLKF_IN1
    );
  NlwInverterBlock_REG_0_24_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_24_SETF_IN1
    );
  NlwInverterBlock_REG_0_24_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_24_RSTF_IN1
    );
  NlwInverterBlock_REG_0_24_RSTF_IN2 : X_INV
    port map (
      I => DIN_24_IBUF,
      O => NlwInverterSignal_REG_0_24_RSTF_IN2
    );
  NlwInverterBlock_REG_0_25_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_25_RSTF,
      O => NlwInverterSignal_REG_0_25_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_25_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_25_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_25_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_25_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_25_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_25_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_25_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_25,
      O => NlwInverterSignal_REG_0_25_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_25_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_25_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_25_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_25_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_25_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_25_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_25_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_24,
      O => NlwInverterSignal_REG_0_25_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_25_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_25_CLKF_IN0
    );
  NlwInverterBlock_REG_0_25_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_25_CLKF_IN1
    );
  NlwInverterBlock_REG_0_25_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_25_SETF_IN1
    );
  NlwInverterBlock_REG_0_25_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_25_RSTF_IN1
    );
  NlwInverterBlock_REG_0_25_RSTF_IN2 : X_INV
    port map (
      I => DIN_25_IBUF,
      O => NlwInverterSignal_REG_0_25_RSTF_IN2
    );
  NlwInverterBlock_REG_0_26_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_26_RSTF,
      O => NlwInverterSignal_REG_0_26_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_26_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_26_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_26_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_26_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_26_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_26_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_26_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_26,
      O => NlwInverterSignal_REG_0_26_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_26_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_26_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_26_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_26_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_26_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_26_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_26_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_25,
      O => NlwInverterSignal_REG_0_26_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_26_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_26_CLKF_IN0
    );
  NlwInverterBlock_REG_0_26_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_26_CLKF_IN1
    );
  NlwInverterBlock_REG_0_26_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_26_SETF_IN1
    );
  NlwInverterBlock_REG_0_26_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_26_RSTF_IN1
    );
  NlwInverterBlock_REG_0_26_RSTF_IN2 : X_INV
    port map (
      I => DIN_26_IBUF,
      O => NlwInverterSignal_REG_0_26_RSTF_IN2
    );
  NlwInverterBlock_REG_0_27_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_27_RSTF,
      O => NlwInverterSignal_REG_0_27_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_27_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_27_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_27_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_27_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_27_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_27_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_27_D2_PT_1_IN4 : X_INV
    port map (
      I => REG_0_26,
      O => NlwInverterSignal_REG_0_27_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_0_27_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_27_CLKF_IN0
    );
  NlwInverterBlock_REG_0_27_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_27_CLKF_IN1
    );
  NlwInverterBlock_REG_0_27_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_27_SETF_IN1
    );
  NlwInverterBlock_REG_0_27_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_27_RSTF_IN1
    );
  NlwInverterBlock_REG_0_27_RSTF_IN2 : X_INV
    port map (
      I => DIN_27_IBUF,
      O => NlwInverterSignal_REG_0_27_RSTF_IN2
    );
  NlwInverterBlock_REG_0_27_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_0_27_EXP_tsimrenamed_net_IN6 : X_INV
    port map (
      I => REG_1_23,
      O => NlwInverterSignal_REG_0_27_EXP_tsimrenamed_net_IN6
    );
  NlwInverterBlock_REG_0_28_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_28_RSTF,
      O => NlwInverterSignal_REG_0_28_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_28_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_28_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_28_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_28_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_28_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_28_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_28_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_28,
      O => NlwInverterSignal_REG_0_28_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_28_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_28_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_28_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_28_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_28_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_28_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_28_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_27,
      O => NlwInverterSignal_REG_0_28_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_28_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_28_CLKF_IN0
    );
  NlwInverterBlock_REG_0_28_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_28_CLKF_IN1
    );
  NlwInverterBlock_REG_0_28_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_28_SETF_IN1
    );
  NlwInverterBlock_REG_0_28_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_28_RSTF_IN1
    );
  NlwInverterBlock_REG_0_28_RSTF_IN2 : X_INV
    port map (
      I => DIN_28_IBUF,
      O => NlwInverterSignal_REG_0_28_RSTF_IN2
    );
  NlwInverterBlock_REG_0_29_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_29_RSTF,
      O => NlwInverterSignal_REG_0_29_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_29_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_29_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_29_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_29_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_29_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_29_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_29_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_29,
      O => NlwInverterSignal_REG_0_29_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_29_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_29_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_29_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_29_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_29_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_29_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_29_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_28,
      O => NlwInverterSignal_REG_0_29_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_29_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_29_CLKF_IN0
    );
  NlwInverterBlock_REG_0_29_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_29_CLKF_IN1
    );
  NlwInverterBlock_REG_0_29_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_29_SETF_IN1
    );
  NlwInverterBlock_REG_0_29_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_29_RSTF_IN1
    );
  NlwInverterBlock_REG_0_29_RSTF_IN2 : X_INV
    port map (
      I => DIN_29_IBUF,
      O => NlwInverterSignal_REG_0_29_RSTF_IN2
    );
  NlwInverterBlock_REG_0_3_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_3_RSTF,
      O => NlwInverterSignal_REG_0_3_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_3_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_3_CLKF_IN0
    );
  NlwInverterBlock_REG_0_3_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_3_CLKF_IN1
    );
  NlwInverterBlock_REG_0_3_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_3_SETF_IN1
    );
  NlwInverterBlock_REG_0_3_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_3_RSTF_IN1
    );
  NlwInverterBlock_REG_0_3_RSTF_IN2 : X_INV
    port map (
      I => DIN_3_IBUF,
      O => NlwInverterSignal_REG_0_3_RSTF_IN2
    );
  NlwInverterBlock_REG_0_3_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_3_EXP_PT_0_IN0
    );
  NlwInverterBlock_REG_0_3_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_3_EXP_PT_0_IN2
    );
  NlwInverterBlock_REG_0_3_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_3_EXP_PT_0_IN4
    );
  NlwInverterBlock_REG_0_3_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_2,
      O => NlwInverterSignal_REG_0_3_EXP_PT_0_IN6
    );
  NlwInverterBlock_REG_0_3_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_3_EXP_PT_1_IN0
    );
  NlwInverterBlock_REG_0_3_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_3_EXP_PT_1_IN2
    );
  NlwInverterBlock_REG_0_3_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_3_EXP_PT_1_IN4
    );
  NlwInverterBlock_REG_0_3_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_2_IBUF,
      O => NlwInverterSignal_REG_0_3_EXP_PT_1_IN5
    );
  NlwInverterBlock_REG_0_30_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_30_RSTF,
      O => NlwInverterSignal_REG_0_30_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_30_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_30_CLKF_IN0
    );
  NlwInverterBlock_REG_0_30_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_30_CLKF_IN1
    );
  NlwInverterBlock_REG_0_30_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_30_SETF_IN1
    );
  NlwInverterBlock_REG_0_30_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_30_RSTF_IN1
    );
  NlwInverterBlock_REG_0_30_RSTF_IN2 : X_INV
    port map (
      I => DIN_30_IBUF,
      O => NlwInverterSignal_REG_0_30_RSTF_IN2
    );
  NlwInverterBlock_REG_0_30_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_30_EXP_PT_0_IN0
    );
  NlwInverterBlock_REG_0_30_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_30_EXP_PT_0_IN2
    );
  NlwInverterBlock_REG_0_30_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_30_EXP_PT_0_IN4
    );
  NlwInverterBlock_REG_0_30_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_29,
      O => NlwInverterSignal_REG_0_30_EXP_PT_0_IN6
    );
  NlwInverterBlock_REG_0_30_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_30_EXP_PT_1_IN0
    );
  NlwInverterBlock_REG_0_30_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_30_EXP_PT_1_IN2
    );
  NlwInverterBlock_REG_0_30_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_30_EXP_PT_1_IN4
    );
  NlwInverterBlock_REG_0_30_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_29_IBUF,
      O => NlwInverterSignal_REG_0_30_EXP_PT_1_IN5
    );
  NlwInverterBlock_REG_0_31_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_31_RSTF,
      O => NlwInverterSignal_REG_0_31_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_31_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_31_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_31_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_31_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_31_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_31_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_31_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_31,
      O => NlwInverterSignal_REG_0_31_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_31_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_31_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_31_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_31_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_31_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_31_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_31_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_30,
      O => NlwInverterSignal_REG_0_31_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_31_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_31_CLKF_IN0
    );
  NlwInverterBlock_REG_0_31_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_31_CLKF_IN1
    );
  NlwInverterBlock_REG_0_31_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_31_SETF_IN1
    );
  NlwInverterBlock_REG_0_31_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_31_RSTF_IN1
    );
  NlwInverterBlock_REG_0_31_RSTF_IN2 : X_INV
    port map (
      I => DIN_31_IBUF,
      O => NlwInverterSignal_REG_0_31_RSTF_IN2
    );
  NlwInverterBlock_REG_0_4_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_4_RSTF,
      O => NlwInverterSignal_REG_0_4_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_4_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_4_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_4_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_4_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_4_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_4_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_4_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_3,
      O => NlwInverterSignal_REG_0_4_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_4_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_4_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_4_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_4_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_4_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_4_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_4_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_4,
      O => NlwInverterSignal_REG_0_4_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_4_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_4_CLKF_IN0
    );
  NlwInverterBlock_REG_0_4_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_4_CLKF_IN1
    );
  NlwInverterBlock_REG_0_4_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_4_SETF_IN1
    );
  NlwInverterBlock_REG_0_4_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_4_RSTF_IN1
    );
  NlwInverterBlock_REG_0_4_RSTF_IN2 : X_INV
    port map (
      I => DIN_4_IBUF,
      O => NlwInverterSignal_REG_0_4_RSTF_IN2
    );
  NlwInverterBlock_REG_0_5_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_5_RSTF,
      O => NlwInverterSignal_REG_0_5_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_5_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_5_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_5_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_5_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_5_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_5_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_5_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_5,
      O => NlwInverterSignal_REG_0_5_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_5_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_5_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_5_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_5_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_5_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_5_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_5_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_0_4,
      O => NlwInverterSignal_REG_0_5_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_0_5_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_5_CLKF_IN0
    );
  NlwInverterBlock_REG_0_5_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_5_CLKF_IN1
    );
  NlwInverterBlock_REG_0_5_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_5_SETF_IN1
    );
  NlwInverterBlock_REG_0_5_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_5_RSTF_IN1
    );
  NlwInverterBlock_REG_0_5_RSTF_IN2 : X_INV
    port map (
      I => DIN_5_IBUF,
      O => NlwInverterSignal_REG_0_5_RSTF_IN2
    );
  NlwInverterBlock_REG_0_6_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_6_RSTF,
      O => NlwInverterSignal_REG_0_6_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_6_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_6_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_6_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_6_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_6_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_6_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_6_D2_PT_2_IN5 : X_INV
    port map (
      I => REG_0_6,
      O => NlwInverterSignal_REG_0_6_D2_PT_2_IN5
    );
  NlwInverterBlock_REG_0_6_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_6_D2_PT_3_IN0
    );
  NlwInverterBlock_REG_0_6_D2_PT_3_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_6_D2_PT_3_IN1
    );
  NlwInverterBlock_REG_0_6_D2_PT_3_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_6_D2_PT_3_IN3
    );
  NlwInverterBlock_REG_0_6_D2_PT_3_IN4 : X_INV
    port map (
      I => REG_0_5,
      O => NlwInverterSignal_REG_0_6_D2_PT_3_IN4
    );
  NlwInverterBlock_REG_0_6_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_6_CLKF_IN0
    );
  NlwInverterBlock_REG_0_6_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_6_CLKF_IN1
    );
  NlwInverterBlock_REG_0_6_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_6_SETF_IN1
    );
  NlwInverterBlock_REG_0_6_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_6_RSTF_IN1
    );
  NlwInverterBlock_REG_0_6_RSTF_IN2 : X_INV
    port map (
      I => DIN_6_IBUF,
      O => NlwInverterSignal_REG_0_6_RSTF_IN2
    );
  NlwInverterBlock_REG_0_7_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_7_RSTF,
      O => NlwInverterSignal_REG_0_7_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_7_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_7_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_7_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_7_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_7_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_7_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_7_D2_PT_1_IN4 : X_INV
    port map (
      I => REG_0_6,
      O => NlwInverterSignal_REG_0_7_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_0_7_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_7_CLKF_IN0
    );
  NlwInverterBlock_REG_0_7_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_7_CLKF_IN1
    );
  NlwInverterBlock_REG_0_7_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_7_SETF_IN1
    );
  NlwInverterBlock_REG_0_7_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_7_RSTF_IN1
    );
  NlwInverterBlock_REG_0_7_RSTF_IN2 : X_INV
    port map (
      I => DIN_7_IBUF,
      O => NlwInverterSignal_REG_0_7_RSTF_IN2
    );
  NlwInverterBlock_REG_0_7_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_0_7_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_REG_0_7_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_REG_0_7_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => REG_0_8,
      O => NlwInverterSignal_REG_0_7_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_REG_0_8_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_8_RSTF,
      O => NlwInverterSignal_REG_0_8_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_8_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_8_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_0_8_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_8_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_0_8_D2_PT_2_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_8_D2_PT_2_IN3
    );
  NlwInverterBlock_REG_0_8_D2_PT_2_IN5 : X_INV
    port map (
      I => REG_0_8,
      O => NlwInverterSignal_REG_0_8_D2_PT_2_IN5
    );
  NlwInverterBlock_REG_0_8_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_8_D2_PT_3_IN0
    );
  NlwInverterBlock_REG_0_8_D2_PT_3_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_8_D2_PT_3_IN1
    );
  NlwInverterBlock_REG_0_8_D2_PT_3_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_8_D2_PT_3_IN3
    );
  NlwInverterBlock_REG_0_8_D2_PT_3_IN4 : X_INV
    port map (
      I => REG_0_7,
      O => NlwInverterSignal_REG_0_8_D2_PT_3_IN4
    );
  NlwInverterBlock_REG_0_8_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_8_CLKF_IN0
    );
  NlwInverterBlock_REG_0_8_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_8_CLKF_IN1
    );
  NlwInverterBlock_REG_0_8_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_8_SETF_IN1
    );
  NlwInverterBlock_REG_0_8_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_8_RSTF_IN1
    );
  NlwInverterBlock_REG_0_8_RSTF_IN2 : X_INV
    port map (
      I => DIN_8_IBUF,
      O => NlwInverterSignal_REG_0_8_RSTF_IN2
    );
  NlwInverterBlock_REG_0_9_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_0_9_RSTF,
      O => NlwInverterSignal_REG_0_9_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_0_9_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_9_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_0_9_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_0_9_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_0_9_D2_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_9_D2_PT_1_IN3
    );
  NlwInverterBlock_REG_0_9_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_0_8,
      O => NlwInverterSignal_REG_0_9_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_0_9_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_9_CLKF_IN0
    );
  NlwInverterBlock_REG_0_9_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_0_9_CLKF_IN1
    );
  NlwInverterBlock_REG_0_9_SETF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_9_SETF_IN1
    );
  NlwInverterBlock_REG_0_9_RSTF_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_9_RSTF_IN1
    );
  NlwInverterBlock_REG_0_9_RSTF_IN2 : X_INV
    port map (
      I => DIN_9_IBUF,
      O => NlwInverterSignal_REG_0_9_RSTF_IN2
    );
  NlwInverterBlock_REG_0_9_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_0_9_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_REG_0_9_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_REG_0_9_EXP_tsimrenamed_net_IN6 : X_INV
    port map (
      I => DIN_8_IBUF,
      O => NlwInverterSignal_REG_0_9_EXP_tsimrenamed_net_IN6
    );
  NlwInverterBlock_REG_1_0_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_0_RSTF,
      O => NlwInverterSignal_REG_1_0_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_0_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_0_CLKF_IN0
    );
  NlwInverterBlock_REG_1_0_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_0_CLKF_IN1
    );
  NlwInverterBlock_REG_1_0_RSTF_IN2 : X_INV
    port map (
      I => DIN_0_IBUF,
      O => NlwInverterSignal_REG_1_0_RSTF_IN2
    );
  NlwInverterBlock_REG_1_0_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_0_EXP_PT_0_IN0
    );
  NlwInverterBlock_REG_1_0_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_4,
      O => NlwInverterSignal_REG_1_0_EXP_PT_0_IN6
    );
  NlwInverterBlock_REG_1_0_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_0_EXP_PT_1_IN0
    );
  NlwInverterBlock_REG_1_0_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_4_IBUF,
      O => NlwInverterSignal_REG_1_0_EXP_PT_1_IN5
    );
  NlwInverterBlock_REG_1_1_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_1_RSTF,
      O => NlwInverterSignal_REG_1_1_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_1_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_1_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_1_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_1_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_1_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_1,
      O => NlwInverterSignal_REG_1_1_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_1_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_1_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_1_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_1_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_1_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_0,
      O => NlwInverterSignal_REG_1_1_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_1_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_1_CLKF_IN0
    );
  NlwInverterBlock_REG_1_1_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_1_CLKF_IN1
    );
  NlwInverterBlock_REG_1_1_RSTF_IN2 : X_INV
    port map (
      I => DIN_1_IBUF,
      O => NlwInverterSignal_REG_1_1_RSTF_IN2
    );
  NlwInverterBlock_REG_1_10_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_10_RSTF,
      O => NlwInverterSignal_REG_1_10_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_10_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_10_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_10_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_10_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_10_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_9,
      O => NlwInverterSignal_REG_1_10_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_10_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_10_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_10_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_10_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_10_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_10,
      O => NlwInverterSignal_REG_1_10_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_10_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_10_CLKF_IN0
    );
  NlwInverterBlock_REG_1_10_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_10_CLKF_IN1
    );
  NlwInverterBlock_REG_1_10_RSTF_IN2 : X_INV
    port map (
      I => DIN_10_IBUF,
      O => NlwInverterSignal_REG_1_10_RSTF_IN2
    );
  NlwInverterBlock_REG_1_11_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_11_RSTF,
      O => NlwInverterSignal_REG_1_11_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_11_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_11_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_11_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_11_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_11_D2_PT_1_IN4 : X_INV
    port map (
      I => REG_1_10,
      O => NlwInverterSignal_REG_1_11_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_1_11_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_11_CLKF_IN0
    );
  NlwInverterBlock_REG_1_11_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_11_CLKF_IN1
    );
  NlwInverterBlock_REG_1_11_RSTF_IN2 : X_INV
    port map (
      I => DIN_11_IBUF,
      O => NlwInverterSignal_REG_1_11_RSTF_IN2
    );
  NlwInverterBlock_REG_1_11_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_1_11_EXP_tsimrenamed_net_IN6 : X_INV
    port map (
      I => REG_1_12,
      O => NlwInverterSignal_REG_1_11_EXP_tsimrenamed_net_IN6
    );
  NlwInverterBlock_REG_1_12_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_12_RSTF,
      O => NlwInverterSignal_REG_1_12_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_12_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_12_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_12_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_12_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_12_D2_PT_2_IN5 : X_INV
    port map (
      I => REG_1_12,
      O => NlwInverterSignal_REG_1_12_D2_PT_2_IN5
    );
  NlwInverterBlock_REG_1_12_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_12_D2_PT_3_IN0
    );
  NlwInverterBlock_REG_1_12_D2_PT_3_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_12_D2_PT_3_IN1
    );
  NlwInverterBlock_REG_1_12_D2_PT_3_IN4 : X_INV
    port map (
      I => REG_1_11,
      O => NlwInverterSignal_REG_1_12_D2_PT_3_IN4
    );
  NlwInverterBlock_REG_1_12_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_12_CLKF_IN0
    );
  NlwInverterBlock_REG_1_12_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_12_CLKF_IN1
    );
  NlwInverterBlock_REG_1_12_RSTF_IN2 : X_INV
    port map (
      I => DIN_12_IBUF,
      O => NlwInverterSignal_REG_1_12_RSTF_IN2
    );
  NlwInverterBlock_REG_1_13_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_13_RSTF,
      O => NlwInverterSignal_REG_1_13_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_13_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_13_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_13_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_13_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_13_D2_PT_1_IN4 : X_INV
    port map (
      I => REG_1_12,
      O => NlwInverterSignal_REG_1_13_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_1_13_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_13_CLKF_IN0
    );
  NlwInverterBlock_REG_1_13_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_13_CLKF_IN1
    );
  NlwInverterBlock_REG_1_13_RSTF_IN2 : X_INV
    port map (
      I => DIN_13_IBUF,
      O => NlwInverterSignal_REG_1_13_RSTF_IN2
    );
  NlwInverterBlock_REG_1_13_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_1_13_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => DIN_12_IBUF,
      O => NlwInverterSignal_REG_1_13_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_REG_1_14_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_14_RSTF,
      O => NlwInverterSignal_REG_1_14_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_14_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_14_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_14_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_14_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_14_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_14,
      O => NlwInverterSignal_REG_1_14_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_14_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_14_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_14_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_14_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_14_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_13,
      O => NlwInverterSignal_REG_1_14_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_14_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_14_CLKF_IN0
    );
  NlwInverterBlock_REG_1_14_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_14_CLKF_IN1
    );
  NlwInverterBlock_REG_1_14_RSTF_IN2 : X_INV
    port map (
      I => DIN_14_IBUF,
      O => NlwInverterSignal_REG_1_14_RSTF_IN2
    );
  NlwInverterBlock_REG_1_15_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_15_RSTF,
      O => NlwInverterSignal_REG_1_15_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_15_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_15_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_15_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_15_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_15_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_15,
      O => NlwInverterSignal_REG_1_15_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_15_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_15_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_15_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_15_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_15_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_14,
      O => NlwInverterSignal_REG_1_15_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_15_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_15_CLKF_IN0
    );
  NlwInverterBlock_REG_1_15_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_15_CLKF_IN1
    );
  NlwInverterBlock_REG_1_15_RSTF_IN2 : X_INV
    port map (
      I => DIN_15_IBUF,
      O => NlwInverterSignal_REG_1_15_RSTF_IN2
    );
  NlwInverterBlock_REG_1_16_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_16_RSTF,
      O => NlwInverterSignal_REG_1_16_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_16_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_16_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_16_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_16_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_16_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_16,
      O => NlwInverterSignal_REG_1_16_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_16_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_16_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_16_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_16_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_16_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_15,
      O => NlwInverterSignal_REG_1_16_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_16_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_16_CLKF_IN0
    );
  NlwInverterBlock_REG_1_16_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_16_CLKF_IN1
    );
  NlwInverterBlock_REG_1_16_RSTF_IN2 : X_INV
    port map (
      I => DIN_16_IBUF,
      O => NlwInverterSignal_REG_1_16_RSTF_IN2
    );
  NlwInverterBlock_REG_1_17_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_17_RSTF,
      O => NlwInverterSignal_REG_1_17_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_17_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_17_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_17_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_17_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_17_D2_PT_1_IN4 : X_INV
    port map (
      I => REG_1_16,
      O => NlwInverterSignal_REG_1_17_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_1_17_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_17_CLKF_IN0
    );
  NlwInverterBlock_REG_1_17_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_17_CLKF_IN1
    );
  NlwInverterBlock_REG_1_17_RSTF_IN2 : X_INV
    port map (
      I => DIN_17_IBUF,
      O => NlwInverterSignal_REG_1_17_RSTF_IN2
    );
  NlwInverterBlock_REG_1_17_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_1_17_EXP_tsimrenamed_net_IN6 : X_INV
    port map (
      I => REG_1_18,
      O => NlwInverterSignal_REG_1_17_EXP_tsimrenamed_net_IN6
    );
  NlwInverterBlock_REG_1_18_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_18_RSTF,
      O => NlwInverterSignal_REG_1_18_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_18_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_18_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_18_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_18_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_18_D2_PT_2_IN5 : X_INV
    port map (
      I => REG_1_18,
      O => NlwInverterSignal_REG_1_18_D2_PT_2_IN5
    );
  NlwInverterBlock_REG_1_18_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_18_D2_PT_3_IN0
    );
  NlwInverterBlock_REG_1_18_D2_PT_3_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_18_D2_PT_3_IN1
    );
  NlwInverterBlock_REG_1_18_D2_PT_3_IN4 : X_INV
    port map (
      I => REG_1_17,
      O => NlwInverterSignal_REG_1_18_D2_PT_3_IN4
    );
  NlwInverterBlock_REG_1_18_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_18_CLKF_IN0
    );
  NlwInverterBlock_REG_1_18_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_18_CLKF_IN1
    );
  NlwInverterBlock_REG_1_18_RSTF_IN2 : X_INV
    port map (
      I => DIN_18_IBUF,
      O => NlwInverterSignal_REG_1_18_RSTF_IN2
    );
  NlwInverterBlock_REG_1_19_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_19_RSTF,
      O => NlwInverterSignal_REG_1_19_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_19_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_19_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_19_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_19_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_19_D2_PT_1_IN4 : X_INV
    port map (
      I => REG_1_18,
      O => NlwInverterSignal_REG_1_19_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_1_19_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_19_CLKF_IN0
    );
  NlwInverterBlock_REG_1_19_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_19_CLKF_IN1
    );
  NlwInverterBlock_REG_1_19_RSTF_IN2 : X_INV
    port map (
      I => DIN_19_IBUF,
      O => NlwInverterSignal_REG_1_19_RSTF_IN2
    );
  NlwInverterBlock_REG_1_19_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_1_19_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => DIN_18_IBUF,
      O => NlwInverterSignal_REG_1_19_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_REG_1_2_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_2_RSTF,
      O => NlwInverterSignal_REG_1_2_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_2_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_2_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_2_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_2_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_2_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_2,
      O => NlwInverterSignal_REG_1_2_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_2_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_2_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_2_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_2_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_2_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_1,
      O => NlwInverterSignal_REG_1_2_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_2_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_2_CLKF_IN0
    );
  NlwInverterBlock_REG_1_2_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_2_CLKF_IN1
    );
  NlwInverterBlock_REG_1_2_RSTF_IN2 : X_INV
    port map (
      I => DIN_2_IBUF,
      O => NlwInverterSignal_REG_1_2_RSTF_IN2
    );
  NlwInverterBlock_REG_1_20_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_20_RSTF,
      O => NlwInverterSignal_REG_1_20_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_20_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_20_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_20_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_20_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_20_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_20,
      O => NlwInverterSignal_REG_1_20_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_20_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_20_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_20_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_20_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_20_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_19,
      O => NlwInverterSignal_REG_1_20_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_20_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_20_CLKF_IN0
    );
  NlwInverterBlock_REG_1_20_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_20_CLKF_IN1
    );
  NlwInverterBlock_REG_1_20_RSTF_IN2 : X_INV
    port map (
      I => DIN_20_IBUF,
      O => NlwInverterSignal_REG_1_20_RSTF_IN2
    );
  NlwInverterBlock_REG_1_21_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_21_RSTF,
      O => NlwInverterSignal_REG_1_21_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_21_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_21_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_21_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_21_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_21_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_21,
      O => NlwInverterSignal_REG_1_21_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_21_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_21_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_21_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_21_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_21_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_20,
      O => NlwInverterSignal_REG_1_21_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_21_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_21_CLKF_IN0
    );
  NlwInverterBlock_REG_1_21_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_21_CLKF_IN1
    );
  NlwInverterBlock_REG_1_21_RSTF_IN2 : X_INV
    port map (
      I => DIN_21_IBUF,
      O => NlwInverterSignal_REG_1_21_RSTF_IN2
    );
  NlwInverterBlock_REG_1_22_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_22_RSTF,
      O => NlwInverterSignal_REG_1_22_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_22_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_22_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_22_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_22_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_22_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_22,
      O => NlwInverterSignal_REG_1_22_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_22_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_22_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_22_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_22_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_22_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_21,
      O => NlwInverterSignal_REG_1_22_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_22_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_22_CLKF_IN0
    );
  NlwInverterBlock_REG_1_22_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_22_CLKF_IN1
    );
  NlwInverterBlock_REG_1_22_RSTF_IN2 : X_INV
    port map (
      I => DIN_22_IBUF,
      O => NlwInverterSignal_REG_1_22_RSTF_IN2
    );
  NlwInverterBlock_REG_1_23_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_23_RSTF,
      O => NlwInverterSignal_REG_1_23_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_23_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_23_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_23_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_23_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_23_D2_PT_2_IN5 : X_INV
    port map (
      I => REG_1_22,
      O => NlwInverterSignal_REG_1_23_D2_PT_2_IN5
    );
  NlwInverterBlock_REG_1_23_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_23_D2_PT_3_IN0
    );
  NlwInverterBlock_REG_1_23_D2_PT_3_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_23_D2_PT_3_IN1
    );
  NlwInverterBlock_REG_1_23_D2_PT_3_IN4 : X_INV
    port map (
      I => REG_1_23,
      O => NlwInverterSignal_REG_1_23_D2_PT_3_IN4
    );
  NlwInverterBlock_REG_1_23_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_23_CLKF_IN0
    );
  NlwInverterBlock_REG_1_23_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_23_CLKF_IN1
    );
  NlwInverterBlock_REG_1_23_RSTF_IN2 : X_INV
    port map (
      I => DIN_23_IBUF,
      O => NlwInverterSignal_REG_1_23_RSTF_IN2
    );
  NlwInverterBlock_REG_1_24_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_24_RSTF,
      O => NlwInverterSignal_REG_1_24_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_24_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_24_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_24_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_24_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_24_D2_PT_1_IN4 : X_INV
    port map (
      I => REG_1_23,
      O => NlwInverterSignal_REG_1_24_D2_PT_1_IN4
    );
  NlwInverterBlock_REG_1_24_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_24_CLKF_IN0
    );
  NlwInverterBlock_REG_1_24_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_24_CLKF_IN1
    );
  NlwInverterBlock_REG_1_24_RSTF_IN2 : X_INV
    port map (
      I => DIN_24_IBUF,
      O => NlwInverterSignal_REG_1_24_RSTF_IN2
    );
  NlwInverterBlock_REG_1_24_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_REG_1_24_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => DIN_23_IBUF,
      O => NlwInverterSignal_REG_1_24_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_REG_1_25_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_25_RSTF,
      O => NlwInverterSignal_REG_1_25_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_25_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_25_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_25_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_25_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_25_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_25,
      O => NlwInverterSignal_REG_1_25_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_25_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_25_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_25_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_25_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_25_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_24,
      O => NlwInverterSignal_REG_1_25_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_25_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_25_CLKF_IN0
    );
  NlwInverterBlock_REG_1_25_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_25_CLKF_IN1
    );
  NlwInverterBlock_REG_1_25_RSTF_IN2 : X_INV
    port map (
      I => DIN_25_IBUF,
      O => NlwInverterSignal_REG_1_25_RSTF_IN2
    );
  NlwInverterBlock_REG_1_26_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_26_RSTF,
      O => NlwInverterSignal_REG_1_26_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_26_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_26_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_26_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_26_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_26_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_26,
      O => NlwInverterSignal_REG_1_26_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_26_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_26_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_26_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_26_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_26_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_25,
      O => NlwInverterSignal_REG_1_26_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_26_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_26_CLKF_IN0
    );
  NlwInverterBlock_REG_1_26_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_26_CLKF_IN1
    );
  NlwInverterBlock_REG_1_26_RSTF_IN2 : X_INV
    port map (
      I => DIN_26_IBUF,
      O => NlwInverterSignal_REG_1_26_RSTF_IN2
    );
  NlwInverterBlock_REG_1_27_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_27_RSTF,
      O => NlwInverterSignal_REG_1_27_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_27_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_27_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_27_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_27_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_27_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_27,
      O => NlwInverterSignal_REG_1_27_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_27_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_27_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_27_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_27_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_27_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_26,
      O => NlwInverterSignal_REG_1_27_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_27_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_27_CLKF_IN0
    );
  NlwInverterBlock_REG_1_27_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_27_CLKF_IN1
    );
  NlwInverterBlock_REG_1_27_RSTF_IN2 : X_INV
    port map (
      I => DIN_27_IBUF,
      O => NlwInverterSignal_REG_1_27_RSTF_IN2
    );
  NlwInverterBlock_REG_1_28_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_28_RSTF,
      O => NlwInverterSignal_REG_1_28_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_28_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_28_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_28_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_28_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_28_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_28,
      O => NlwInverterSignal_REG_1_28_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_28_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_28_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_28_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_28_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_28_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_27,
      O => NlwInverterSignal_REG_1_28_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_28_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_28_CLKF_IN0
    );
  NlwInverterBlock_REG_1_28_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_28_CLKF_IN1
    );
  NlwInverterBlock_REG_1_28_RSTF_IN2 : X_INV
    port map (
      I => DIN_28_IBUF,
      O => NlwInverterSignal_REG_1_28_RSTF_IN2
    );
  NlwInverterBlock_REG_1_29_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_29_RSTF,
      O => NlwInverterSignal_REG_1_29_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_29_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_29_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_29_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_29_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_29_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_29,
      O => NlwInverterSignal_REG_1_29_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_29_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_29_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_29_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_29_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_29_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_28,
      O => NlwInverterSignal_REG_1_29_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_29_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_29_CLKF_IN0
    );
  NlwInverterBlock_REG_1_29_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_29_CLKF_IN1
    );
  NlwInverterBlock_REG_1_29_RSTF_IN2 : X_INV
    port map (
      I => DIN_29_IBUF,
      O => NlwInverterSignal_REG_1_29_RSTF_IN2
    );
  NlwInverterBlock_REG_1_3_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_3_RSTF,
      O => NlwInverterSignal_REG_1_3_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_3_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_3_CLKF_IN0
    );
  NlwInverterBlock_REG_1_3_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_3_CLKF_IN1
    );
  NlwInverterBlock_REG_1_3_RSTF_IN2 : X_INV
    port map (
      I => DIN_3_IBUF,
      O => NlwInverterSignal_REG_1_3_RSTF_IN2
    );
  NlwInverterBlock_REG_1_3_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_3_EXP_PT_0_IN0
    );
  NlwInverterBlock_REG_1_3_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_2,
      O => NlwInverterSignal_REG_1_3_EXP_PT_0_IN6
    );
  NlwInverterBlock_REG_1_3_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_3_EXP_PT_1_IN0
    );
  NlwInverterBlock_REG_1_3_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_2_IBUF,
      O => NlwInverterSignal_REG_1_3_EXP_PT_1_IN5
    );
  NlwInverterBlock_REG_1_30_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_30_RSTF,
      O => NlwInverterSignal_REG_1_30_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_30_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_30_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_30_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_30_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_30_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_30,
      O => NlwInverterSignal_REG_1_30_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_30_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_30_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_30_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_30_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_30_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_29,
      O => NlwInverterSignal_REG_1_30_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_30_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_30_CLKF_IN0
    );
  NlwInverterBlock_REG_1_30_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_30_CLKF_IN1
    );
  NlwInverterBlock_REG_1_30_RSTF_IN2 : X_INV
    port map (
      I => DIN_30_IBUF,
      O => NlwInverterSignal_REG_1_30_RSTF_IN2
    );
  NlwInverterBlock_REG_1_31_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_31_RSTF,
      O => NlwInverterSignal_REG_1_31_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_31_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_31_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_31_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_31_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_31_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_31,
      O => NlwInverterSignal_REG_1_31_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_31_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_31_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_31_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_31_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_31_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_30,
      O => NlwInverterSignal_REG_1_31_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_31_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_31_CLKF_IN0
    );
  NlwInverterBlock_REG_1_31_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_31_CLKF_IN1
    );
  NlwInverterBlock_REG_1_31_RSTF_IN2 : X_INV
    port map (
      I => DIN_31_IBUF,
      O => NlwInverterSignal_REG_1_31_RSTF_IN2
    );
  NlwInverterBlock_REG_1_4_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_4_RSTF,
      O => NlwInverterSignal_REG_1_4_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_4_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_4_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_4_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_4_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_4_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_3,
      O => NlwInverterSignal_REG_1_4_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_4_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_4_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_4_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_4_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_4_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_4,
      O => NlwInverterSignal_REG_1_4_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_4_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_4_CLKF_IN0
    );
  NlwInverterBlock_REG_1_4_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_4_CLKF_IN1
    );
  NlwInverterBlock_REG_1_4_RSTF_IN2 : X_INV
    port map (
      I => DIN_4_IBUF,
      O => NlwInverterSignal_REG_1_4_RSTF_IN2
    );
  NlwInverterBlock_REG_1_5_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_5_RSTF,
      O => NlwInverterSignal_REG_1_5_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_5_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_5_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_5_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_5_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_5_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_5,
      O => NlwInverterSignal_REG_1_5_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_5_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_5_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_5_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_5_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_5_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_4,
      O => NlwInverterSignal_REG_1_5_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_5_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_5_CLKF_IN0
    );
  NlwInverterBlock_REG_1_5_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_5_CLKF_IN1
    );
  NlwInverterBlock_REG_1_5_RSTF_IN2 : X_INV
    port map (
      I => DIN_5_IBUF,
      O => NlwInverterSignal_REG_1_5_RSTF_IN2
    );
  NlwInverterBlock_REG_1_6_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_6_RSTF,
      O => NlwInverterSignal_REG_1_6_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_6_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_6_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_6_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_6_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_6_D2_PT_2_IN5 : X_INV
    port map (
      I => REG_1_6,
      O => NlwInverterSignal_REG_1_6_D2_PT_2_IN5
    );
  NlwInverterBlock_REG_1_6_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_6_D2_PT_3_IN0
    );
  NlwInverterBlock_REG_1_6_D2_PT_3_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_6_D2_PT_3_IN1
    );
  NlwInverterBlock_REG_1_6_D2_PT_3_IN4 : X_INV
    port map (
      I => REG_1_5,
      O => NlwInverterSignal_REG_1_6_D2_PT_3_IN4
    );
  NlwInverterBlock_REG_1_6_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_6_CLKF_IN0
    );
  NlwInverterBlock_REG_1_6_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_6_CLKF_IN1
    );
  NlwInverterBlock_REG_1_6_RSTF_IN2 : X_INV
    port map (
      I => DIN_6_IBUF,
      O => NlwInverterSignal_REG_1_6_RSTF_IN2
    );
  NlwInverterBlock_REG_1_7_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_7_RSTF,
      O => NlwInverterSignal_REG_1_7_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_7_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_7_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_7_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_7_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_7_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_7,
      O => NlwInverterSignal_REG_1_7_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_7_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_7_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_7_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_7_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_7_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_6,
      O => NlwInverterSignal_REG_1_7_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_7_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_7_CLKF_IN0
    );
  NlwInverterBlock_REG_1_7_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_7_CLKF_IN1
    );
  NlwInverterBlock_REG_1_7_RSTF_IN2 : X_INV
    port map (
      I => DIN_7_IBUF,
      O => NlwInverterSignal_REG_1_7_RSTF_IN2
    );
  NlwInverterBlock_REG_1_8_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_8_RSTF,
      O => NlwInverterSignal_REG_1_8_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_8_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_8_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_8_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_8_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_8_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_8,
      O => NlwInverterSignal_REG_1_8_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_8_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_8_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_8_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_8_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_8_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_7,
      O => NlwInverterSignal_REG_1_8_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_8_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_8_CLKF_IN0
    );
  NlwInverterBlock_REG_1_8_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_8_CLKF_IN1
    );
  NlwInverterBlock_REG_1_8_RSTF_IN2 : X_INV
    port map (
      I => DIN_8_IBUF,
      O => NlwInverterSignal_REG_1_8_RSTF_IN2
    );
  NlwInverterBlock_REG_1_9_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => REG_1_9_RSTF,
      O => NlwInverterSignal_REG_1_9_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_REG_1_9_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_9_D2_PT_1_IN0
    );
  NlwInverterBlock_REG_1_9_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_9_D2_PT_1_IN1
    );
  NlwInverterBlock_REG_1_9_D2_PT_1_IN5 : X_INV
    port map (
      I => REG_1_8,
      O => NlwInverterSignal_REG_1_9_D2_PT_1_IN5
    );
  NlwInverterBlock_REG_1_9_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_REG_1_9_D2_PT_2_IN0
    );
  NlwInverterBlock_REG_1_9_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_REG_1_9_D2_PT_2_IN1
    );
  NlwInverterBlock_REG_1_9_D2_PT_2_IN4 : X_INV
    port map (
      I => REG_1_9,
      O => NlwInverterSignal_REG_1_9_D2_PT_2_IN4
    );
  NlwInverterBlock_REG_1_9_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_9_CLKF_IN0
    );
  NlwInverterBlock_REG_1_9_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_REG_1_9_CLKF_IN1
    );
  NlwInverterBlock_REG_1_9_RSTF_IN2 : X_INV
    port map (
      I => DIN_9_IBUF,
      O => NlwInverterSignal_REG_1_9_RSTF_IN2
    );
  NlwInverterBlock_DOUT_OBUFE_D2_PT_1_IN0 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_DOUT_OBUFE_D2_PT_1_IN0
    );
  NlwInverterBlock_DOUT_OBUFE_TRST_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_DOUT_OBUFE_TRST_IN0
    );
  NlwInverterBlock_DOUT_OBUFE_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN0
    );
  NlwInverterBlock_DOUT_OBUFE_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_30,
      O => NlwInverterSignal_DOUT_OBUFE_EXP_PT_0_IN6
    );
  NlwInverterBlock_DOUT_OBUFE_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN0
    );
  NlwInverterBlock_DOUT_OBUFE_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_30_IBUF,
      O => NlwInverterSignal_DOUT_OBUFE_EXP_PT_1_IN5
    );
  NlwInverterBlock_state_0_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_state_0_EXP_PT_0_IN0
    );
  NlwInverterBlock_state_0_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_state_0_EXP_PT_0_IN2
    );
  NlwInverterBlock_state_0_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_state_0_EXP_PT_0_IN4
    );
  NlwInverterBlock_state_0_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_19,
      O => NlwInverterSignal_state_0_EXP_PT_0_IN6
    );
  NlwInverterBlock_state_0_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_state_0_EXP_PT_1_IN0
    );
  NlwInverterBlock_state_0_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_state_0_EXP_PT_1_IN2
    );
  NlwInverterBlock_state_0_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_state_0_EXP_PT_1_IN4
    );
  NlwInverterBlock_state_0_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_19_IBUF,
      O => NlwInverterSignal_state_0_EXP_PT_1_IN5
    );
  NlwInverterBlock_state_1_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_state_1_EXP_PT_0_IN0
    );
  NlwInverterBlock_state_1_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_state_1_EXP_PT_0_IN2
    );
  NlwInverterBlock_state_1_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_state_1_EXP_PT_0_IN4
    );
  NlwInverterBlock_state_1_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_25,
      O => NlwInverterSignal_state_1_EXP_PT_0_IN6
    );
  NlwInverterBlock_state_1_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_state_1_EXP_PT_1_IN0
    );
  NlwInverterBlock_state_1_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_state_1_EXP_PT_1_IN2
    );
  NlwInverterBlock_state_1_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_state_1_EXP_PT_1_IN4
    );
  NlwInverterBlock_state_1_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_25_IBUF,
      O => NlwInverterSignal_state_1_EXP_PT_1_IN5
    );
  NlwInverterBlock_CLK_SCALE_1_D2_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_1_D2_PT_0_IN0
    );
  NlwInverterBlock_CLK_SCALE_1_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN0
    );
  NlwInverterBlock_CLK_SCALE_1_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_CLK_SCALE_1_D2_PT_1_IN1
    );
  NlwInverterBlock_CLK_SCALE_1_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_1_D2_PT_2_IN0
    );
  NlwInverterBlock_CLK_SCALE_1_EXP_tsimrenamed_net_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN1
    );
  NlwInverterBlock_CLK_SCALE_1_EXP_tsimrenamed_net_IN3 : X_INV
    port map (
      I => CLK_SCALE(1),
      O => NlwInverterSignal_CLK_SCALE_1_EXP_tsimrenamed_net_IN3
    );
  NlwInverterBlock_CLK_SCALE_2_D2_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_2_D2_PT_0_IN0
    );
  NlwInverterBlock_CLK_SCALE_2_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN0
    );
  NlwInverterBlock_CLK_SCALE_2_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_CLK_SCALE_2_D2_PT_1_IN1
    );
  NlwInverterBlock_CLK_SCALE_2_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_2_D2_PT_2_IN0
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN0
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN1
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN2 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN2
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN3 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN3
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN4 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN4
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN5 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN5
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_0_IN6 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_0_IN6
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN0 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN0
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN1 : X_INV
    port map (
      I => count(4),
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN1
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN2 : X_INV
    port map (
      I => count(1),
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN2
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN3 : X_INV
    port map (
      I => count(2),
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN3
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN4 : X_INV
    port map (
      I => count(3),
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN4
    );
  NlwInverterBlock_CLK_SCALE_2_EXP_PT_1_IN5 : X_INV
    port map (
      I => count(5),
      O => NlwInverterSignal_CLK_SCALE_2_EXP_PT_1_IN5
    );
  NlwInverterBlock_CLK_SCALE_3_D2_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_3_D2_PT_0_IN0
    );
  NlwInverterBlock_CLK_SCALE_3_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN0
    );
  NlwInverterBlock_CLK_SCALE_3_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_CLK_SCALE_3_D2_PT_1_IN1
    );
  NlwInverterBlock_CLK_SCALE_3_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_3_D2_PT_2_IN0
    );
  NlwInverterBlock_CLK_SCALE_4_D2_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_4_D2_PT_0_IN0
    );
  NlwInverterBlock_CLK_SCALE_4_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN0
    );
  NlwInverterBlock_CLK_SCALE_4_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_CLK_SCALE_4_D2_PT_1_IN1
    );
  NlwInverterBlock_CLK_SCALE_4_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_4_D2_PT_2_IN0
    );
  NlwInverterBlock_CLK_SCALE_5_D2_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_5_D2_PT_0_IN0
    );
  NlwInverterBlock_CLK_SCALE_5_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN0
    );
  NlwInverterBlock_CLK_SCALE_5_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_CLK_SCALE_5_D2_PT_1_IN1
    );
  NlwInverterBlock_CLK_SCALE_5_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CLK_SCALE_5_D2_PT_2_IN0
    );
  NlwInverterBlock_tempID_0_D2_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_tempID_0_D2_PT_0_IN0
    );
  NlwInverterBlock_tempID_0_D2_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_tempID_0_D2_PT_0_IN1
    );
  NlwInverterBlock_tempID_0_D2_PT_0_IN3 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_tempID_0_D2_PT_0_IN3
    );
  NlwInverterBlock_tempID_0_D2_PT_0_IN4 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_tempID_0_D2_PT_0_IN4
    );
  NlwInverterBlock_tempID_0_D2_PT_0_IN5 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_tempID_0_D2_PT_0_IN5
    );
  NlwInverterBlock_tempID_0_D2_PT_0_IN6 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_tempID_0_D2_PT_0_IN6
    );
  NlwInverterBlock_tempID_0_D2_PT_0_IN7 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_tempID_0_D2_PT_0_IN7
    );
  NlwInverterBlock_tempID_0_D2_PT_0_IN10 : X_INV
    port map (
      I => tempID(0),
      O => NlwInverterSignal_tempID_0_D2_PT_0_IN10
    );
  NlwInverterBlock_tempID_0_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_tempID_0_D2_PT_1_IN0
    );
  NlwInverterBlock_tempID_0_D2_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_tempID_0_D2_PT_1_IN1
    );
  NlwInverterBlock_tempID_0_D2_PT_1_IN3 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_tempID_0_D2_PT_1_IN3
    );
  NlwInverterBlock_tempID_0_D2_PT_1_IN4 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_tempID_0_D2_PT_1_IN4
    );
  NlwInverterBlock_tempID_0_D2_PT_1_IN5 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_tempID_0_D2_PT_1_IN5
    );
  NlwInverterBlock_tempID_0_D2_PT_1_IN6 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_tempID_0_D2_PT_1_IN6
    );
  NlwInverterBlock_tempID_0_D2_PT_1_IN7 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_tempID_0_D2_PT_1_IN7
    );
  NlwInverterBlock_tempID_0_D2_PT_1_IN9 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_tempID_0_D2_PT_1_IN9
    );
  NlwInverterBlock_tempID_0_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_tempID_0_D2_PT_2_IN0
    );
  NlwInverterBlock_tempID_0_D2_PT_2_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_tempID_0_D2_PT_2_IN1
    );
  NlwInverterBlock_tempID_0_D2_PT_2_IN3 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_tempID_0_D2_PT_2_IN3
    );
  NlwInverterBlock_tempID_0_D2_PT_2_IN4 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_tempID_0_D2_PT_2_IN4
    );
  NlwInverterBlock_tempID_0_D2_PT_2_IN5 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_tempID_0_D2_PT_2_IN5
    );
  NlwInverterBlock_tempID_0_D2_PT_2_IN6 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_tempID_0_D2_PT_2_IN6
    );
  NlwInverterBlock_tempID_0_D2_PT_2_IN7 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_tempID_0_D2_PT_2_IN7
    );
  NlwInverterBlock_tempID_0_D2_PT_2_IN10 : X_INV
    port map (
      I => tempID(0),
      O => NlwInverterSignal_tempID_0_D2_PT_2_IN10
    );
  NlwInverterBlock_tempID_0_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_tempID_0_D2_PT_3_IN0
    );
  NlwInverterBlock_tempID_0_D2_PT_3_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_tempID_0_D2_PT_3_IN1
    );
  NlwInverterBlock_tempID_0_D2_PT_3_IN3 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_tempID_0_D2_PT_3_IN3
    );
  NlwInverterBlock_tempID_0_D2_PT_3_IN4 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_tempID_0_D2_PT_3_IN4
    );
  NlwInverterBlock_tempID_0_D2_PT_3_IN5 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_tempID_0_D2_PT_3_IN5
    );
  NlwInverterBlock_tempID_0_D2_PT_3_IN6 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_tempID_0_D2_PT_3_IN6
    );
  NlwInverterBlock_tempID_0_D2_PT_3_IN7 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_tempID_0_D2_PT_3_IN7
    );
  NlwInverterBlock_tempID_0_D2_PT_3_IN9 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_tempID_0_D2_PT_3_IN9
    );
  NlwInverterBlock_tempID_0_CLKF_IN0 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_tempID_0_CLKF_IN0
    );
  NlwInverterBlock_tempID_0_CLKF_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_tempID_0_CLKF_IN1
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN1 : X_INV
    port map (
      I => buf_depth(1),
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN1
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN2
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN3
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN4
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN5 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN5
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_D2_IN6 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_D2_IN6
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN0 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN0
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN1 : X_INV
    port map (
      I => SHIFT_EN,
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_2_IN1
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN0 : X_INV
    port map (
      I => buf_depth(0),
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN0
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN1 : X_INV
    port map (
      I => buf_depth(1),
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN1
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN2 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN2
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN3 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN3
    );
  NlwInverterBlock_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN4 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_BUF_IS_EMPTY_OBUF_EXP_PT_3_IN4
    );
  NlwInverterBlock_SHIFT_EN_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => SHIFT_EN_RSTF,
      O => NlwInverterSignal_SHIFT_EN_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_SHIFT_EN_SETF_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_EN_SETF_IN0
    );
  NlwInverterBlock_SHIFT_EN_SETF_IN1 : X_INV
    port map (
      I => state(0),
      O => NlwInverterSignal_SHIFT_EN_SETF_IN1
    );
  NlwInverterBlock_SHIFT_EN_RSTF_IN0 : X_INV
    port map (
      I => SHIFT_EN_SHIFT_EN_RSTF_INT_UIM,
      O => NlwInverterSignal_SHIFT_EN_RSTF_IN0
    );
  NlwInverterBlock_SHIFT_EN_RSTF_IN1 : X_INV
    port map (
      I => SHIFT_EN_SHIFT_EN_RSTF_INT_UIM,
      O => NlwInverterSignal_SHIFT_EN_RSTF_IN1
    );
  NlwInverterBlock_SHIFT_EN_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN0
    );
  NlwInverterBlock_SHIFT_EN_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN2
    );
  NlwInverterBlock_SHIFT_EN_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN4
    );
  NlwInverterBlock_SHIFT_EN_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_11,
      O => NlwInverterSignal_SHIFT_EN_EXP_PT_0_IN6
    );
  NlwInverterBlock_SHIFT_EN_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN0
    );
  NlwInverterBlock_SHIFT_EN_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN2
    );
  NlwInverterBlock_SHIFT_EN_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN4
    );
  NlwInverterBlock_SHIFT_EN_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_11_IBUF,
      O => NlwInverterSignal_SHIFT_EN_EXP_PT_1_IN5
    );
  NlwInverterBlock_next_state_0_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => next_state_0_RSTF,
      O => NlwInverterSignal_next_state_0_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_next_state_0_SETF_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_next_state_0_SETF_IN0
    );
  NlwInverterBlock_next_state_0_SETF_IN1 : X_INV
    port map (
      I => state(0),
      O => NlwInverterSignal_next_state_0_SETF_IN1
    );
  NlwInverterBlock_next_state_0_SETF_IN2 : X_INV
    port map (
      I => state(1),
      O => NlwInverterSignal_next_state_0_SETF_IN2
    );
  NlwInverterBlock_next_state_0_SETF_IN3 : X_INV
    port map (
      I => Q_OpTx_FX_DC_19_UIM,
      O => NlwInverterSignal_next_state_0_SETF_IN3
    );
  NlwInverterBlock_next_state_1_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => next_state_1_RSTF,
      O => NlwInverterSignal_next_state_1_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_next_state_1_SETF_IN1 : X_INV
    port map (
      I => next_state_1_next_state_1_RSTF_UIM,
      O => NlwInverterSignal_next_state_1_SETF_IN1
    );
  NlwInverterBlock_CCLK_OBUF_D_IN0 : X_INV
    port map (
      I => CCLK_OBUF_D1,
      O => NlwInverterSignal_CCLK_OBUF_D_IN0
    );
  NlwInverterBlock_CCLK_OBUF_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN0
    );
  NlwInverterBlock_CCLK_OBUF_D2_PT_1_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_CCLK_OBUF_D2_PT_1_IN1
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN0
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN1
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_0_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN3
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_0_13,
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_0_IN5
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN0
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN1
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN3
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_1_IN4 : X_INV
    port map (
      I => REG_0_12,
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_1_IN4
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN0
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_2_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN2
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_2_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN4
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_2_IN6 : X_INV
    port map (
      I => REG_0_13,
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_2_IN6
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN0
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_3_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN2
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_3_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN4
    );
  NlwInverterBlock_CCLK_OBUF_EXP_PT_3_IN5 : X_INV
    port map (
      I => DIN_13_IBUF,
      O => NlwInverterSignal_CCLK_OBUF_EXP_PT_3_IN5
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN0 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN0
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN2
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN3
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_0_IN4
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN0 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN0
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN2
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN3
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_1_IN4
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN0 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN0
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN1 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN1
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN2 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN2
    );
  NlwInverterBlock_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN3 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_buf_depth_0_buf_depth_0_RSTF_EXP_PT_2_IN3
    );
  NlwInverterBlock_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN1 : X_INV
    port map (
      I => buf_depth(0),
      O => NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN1
    );
  NlwInverterBlock_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN2 : X_INV
    port map (
      I => buf_depth(1),
      O => NlwInverterSignal_buf_depth_1_buf_depth_1_RSTF_D2_PT_2_IN2
    );
  NlwInverterBlock_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN0
    );
  NlwInverterBlock_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN2 : X_INV
    port map (
      I => state(1),
      O => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_0_IN2
    );
  NlwInverterBlock_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN0
    );
  NlwInverterBlock_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN1 : X_INV
    port map (
      I => state(0),
      O => NlwInverterSignal_SHIFT_EN_SHIFT_EN_RSTF_INT_D2_PT_1_IN1
    );
  NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN1 : X_INV
    port map (
      I => buf_depth(1),
      O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN1
    );
  NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN2
    );
  NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN3
    );
  NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN4
    );
  NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN5 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN5
    );
  NlwInverterBlock_OpTx_FX_DC_19_D2_PT_1_IN6 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_OpTx_FX_DC_19_D2_PT_1_IN6
    );
  NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_0_IN0
    );
  NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_1_IN0
    );
  NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_2_IN0
    );
  NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN0
    );
  NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN2 : X_INV
    port map (
      I => buf_depth(1),
      O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN2
    );
  NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN3 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN3
    );
  NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN4 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN4
    );
  NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN5 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN5
    );
  NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN6 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN6
    );
  NlwInverterBlock_next_state_0_next_state_0_RSTF_D2_PT_3_IN7 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_next_state_0_next_state_0_RSTF_D2_PT_3_IN7
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_0_IN0
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN0
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_1_IN1 : X_INV
    port map (
      I => nINIT_B_IBUF,
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_1_IN1
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_2_IN0
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN0
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_3_IN1 : X_INV
    port map (
      I => state(0),
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN1
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_3_IN2 : X_INV
    port map (
      I => state(1),
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_3_IN2
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN0
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN2 : X_INV
    port map (
      I => buf_depth(1),
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN2
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN3 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN3
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN4 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN4
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN5 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN5
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN6 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN6
    );
  NlwInverterBlock_next_state_1_next_state_1_RSTF_D2_PT_4_IN7 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_next_state_1_next_state_1_RSTF_D2_PT_4_IN7
    );
  NlwInverterBlock_EXP18_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP18_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP18_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP18_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP18_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP18_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP18_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_1,
      O => NlwInverterSignal_EXP18_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP18_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP18_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP18_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP18_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP18_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP18_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP18_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_1_IBUF,
      O => NlwInverterSignal_EXP18_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP19_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP19_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP19_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP19_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP19_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP19_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP19_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_5,
      O => NlwInverterSignal_EXP19_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP19_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP19_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP19_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP19_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP19_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP19_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP19_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_5_IBUF,
      O => NlwInverterSignal_EXP19_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP20_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_EXP20_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_EXP20_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_EXP20_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => DIN_6_IBUF,
      O => NlwInverterSignal_EXP20_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_EXP21_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_EXP21_EXP_tsimrenamed_net_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN2
    );
  NlwInverterBlock_EXP21_EXP_tsimrenamed_net_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN4
    );
  NlwInverterBlock_EXP21_EXP_tsimrenamed_net_IN6 : X_INV
    port map (
      I => REG_0_6,
      O => NlwInverterSignal_EXP21_EXP_tsimrenamed_net_IN6
    );
  NlwInverterBlock_EXP22_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP22_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP22_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP22_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP22_EXP_PT_0_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP22_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP22_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP22_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP22_EXP_PT_1_IN1 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP22_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP22_EXP_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP22_EXP_PT_1_IN3
    );
  NlwInverterBlock_EXP22_EXP_PT_1_IN4 : X_INV
    port map (
      I => DIN_0_IBUF,
      O => NlwInverterSignal_EXP22_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP22_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP22_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP22_EXP_PT_2_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP22_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP22_EXP_PT_2_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP22_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP22_EXP_PT_2_IN6 : X_INV
    port map (
      I => REG_0_0,
      O => NlwInverterSignal_EXP22_EXP_PT_2_IN6
    );
  NlwInverterBlock_EXP23_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP23_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP23_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP23_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP23_EXP_PT_0_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP23_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP23_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_0_3,
      O => NlwInverterSignal_EXP23_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP23_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP23_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP23_EXP_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP23_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP23_EXP_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP23_EXP_PT_1_IN3
    );
  NlwInverterBlock_EXP23_EXP_PT_1_IN4 : X_INV
    port map (
      I => REG_0_2,
      O => NlwInverterSignal_EXP23_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP23_EXP_PT_2_IN6 : X_INV
    port map (
      I => REG_0_3,
      O => NlwInverterSignal_EXP23_EXP_PT_2_IN6
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN2
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN4
    );
  NlwInverterBlock_EXP23_EXP_PT_3_IN5 : X_INV
    port map (
      I => DIN_3_IBUF,
      O => NlwInverterSignal_EXP23_EXP_PT_3_IN5
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP24_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_31,
      O => NlwInverterSignal_EXP24_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP24_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_31_IBUF,
      O => NlwInverterSignal_EXP24_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP25_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP25_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP25_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP25_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP25_EXP_PT_0_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP25_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP25_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_0_30,
      O => NlwInverterSignal_EXP25_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP25_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP25_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP25_EXP_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP25_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP25_EXP_PT_1_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP25_EXP_PT_1_IN3
    );
  NlwInverterBlock_EXP25_EXP_PT_1_IN4 : X_INV
    port map (
      I => REG_0_29,
      O => NlwInverterSignal_EXP25_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP25_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP25_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP25_EXP_PT_2_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP25_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP25_EXP_PT_2_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP25_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP25_EXP_PT_2_IN6 : X_INV
    port map (
      I => REG_0_30,
      O => NlwInverterSignal_EXP25_EXP_PT_2_IN6
    );
  NlwInverterBlock_EXP25_EXP_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP25_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP25_EXP_PT_3_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP25_EXP_PT_3_IN2
    );
  NlwInverterBlock_EXP25_EXP_PT_3_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP25_EXP_PT_3_IN4
    );
  NlwInverterBlock_EXP25_EXP_PT_3_IN5 : X_INV
    port map (
      I => DIN_30_IBUF,
      O => NlwInverterSignal_EXP25_EXP_PT_3_IN5
    );
  NlwInverterBlock_EXP26_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP26_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP26_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP26_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP26_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP26_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP26_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_28,
      O => NlwInverterSignal_EXP26_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP26_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP26_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP26_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP26_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP26_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP26_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP26_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_28_IBUF,
      O => NlwInverterSignal_EXP26_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP27_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP27_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP27_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_31,
      O => NlwInverterSignal_EXP27_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP27_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP27_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP27_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_31_IBUF,
      O => NlwInverterSignal_EXP27_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP28_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP28_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP28_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_29,
      O => NlwInverterSignal_EXP28_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP28_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP28_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP28_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_29_IBUF,
      O => NlwInverterSignal_EXP28_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP29_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP29_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP29_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP29_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP29_EXP_PT_0_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP29_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP29_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_0_17,
      O => NlwInverterSignal_EXP29_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP29_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP29_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP29_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP29_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP29_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP29_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP29_EXP_PT_1_IN6 : X_INV
    port map (
      I => REG_0_17,
      O => NlwInverterSignal_EXP29_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP29_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP29_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP29_EXP_PT_2_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP29_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP29_EXP_PT_2_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP29_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP29_EXP_PT_2_IN5 : X_INV
    port map (
      I => DIN_17_IBUF,
      O => NlwInverterSignal_EXP29_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP30_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_0_15,
      O => NlwInverterSignal_EXP30_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP30_EXP_PT_1_IN6 : X_INV
    port map (
      I => REG_0_15,
      O => NlwInverterSignal_EXP30_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP30_EXP_PT_2_IN5 : X_INV
    port map (
      I => DIN_15_IBUF,
      O => NlwInverterSignal_EXP30_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP31_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP31_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP31_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP31_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP31_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP31_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP31_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_20,
      O => NlwInverterSignal_EXP31_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP31_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP31_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP31_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP31_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP31_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP31_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP31_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_20_IBUF,
      O => NlwInverterSignal_EXP31_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP32_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP32_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP32_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP32_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP32_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP32_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP32_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_18,
      O => NlwInverterSignal_EXP32_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP32_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP32_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP32_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP32_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP32_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP32_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP32_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_18_IBUF,
      O => NlwInverterSignal_EXP32_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP33_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP33_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP33_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP33_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP33_EXP_PT_0_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP33_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP33_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_0_23,
      O => NlwInverterSignal_EXP33_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP33_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP33_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP33_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP33_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP33_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP33_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP33_EXP_PT_1_IN6 : X_INV
    port map (
      I => REG_0_23,
      O => NlwInverterSignal_EXP33_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP33_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP33_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP33_EXP_PT_2_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP33_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP33_EXP_PT_2_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP33_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP33_EXP_PT_2_IN5 : X_INV
    port map (
      I => DIN_23_IBUF,
      O => NlwInverterSignal_EXP33_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP34_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP34_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP34_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP34_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP34_EXP_PT_0_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP34_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP34_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_0_21,
      O => NlwInverterSignal_EXP34_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP34_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP34_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP34_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP34_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP34_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP34_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP34_EXP_PT_1_IN6 : X_INV
    port map (
      I => REG_0_21,
      O => NlwInverterSignal_EXP34_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP34_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP34_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP34_EXP_PT_2_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP34_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP34_EXP_PT_2_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP34_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP34_EXP_PT_2_IN5 : X_INV
    port map (
      I => DIN_21_IBUF,
      O => NlwInverterSignal_EXP34_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP35_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP35_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP35_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP35_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP35_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP35_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP35_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_26,
      O => NlwInverterSignal_EXP35_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP35_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP35_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP35_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP35_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP35_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP35_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP35_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_26_IBUF,
      O => NlwInverterSignal_EXP35_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP36_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP36_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP36_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP36_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP36_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP36_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP36_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_24,
      O => NlwInverterSignal_EXP36_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP36_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP36_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP36_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP36_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP36_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP36_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP36_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_24_IBUF,
      O => NlwInverterSignal_EXP36_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP37_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP37_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP37_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_27,
      O => NlwInverterSignal_EXP37_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP37_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP37_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP37_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_27_IBUF,
      O => NlwInverterSignal_EXP37_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP38_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP38_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP38_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP38_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP38_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_1_24,
      O => NlwInverterSignal_EXP38_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP38_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP38_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP38_EXP_PT_1_IN6 : X_INV
    port map (
      I => REG_1_24,
      O => NlwInverterSignal_EXP38_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP38_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP38_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP38_EXP_PT_2_IN5 : X_INV
    port map (
      I => DIN_24_IBUF,
      O => NlwInverterSignal_EXP38_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP39_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP39_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP39_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP39_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP39_EXP_PT_0_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP39_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP39_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_0_27,
      O => NlwInverterSignal_EXP39_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP39_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP39_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP39_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP39_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP39_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP39_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP39_EXP_PT_1_IN6 : X_INV
    port map (
      I => REG_0_27,
      O => NlwInverterSignal_EXP39_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP39_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP39_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP39_EXP_PT_2_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP39_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP39_EXP_PT_2_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP39_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP39_EXP_PT_2_IN5 : X_INV
    port map (
      I => DIN_27_IBUF,
      O => NlwInverterSignal_EXP39_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP40_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP40_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP40_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_26,
      O => NlwInverterSignal_EXP40_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP40_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP40_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP40_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_26_IBUF,
      O => NlwInverterSignal_EXP40_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP41_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP41_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP41_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_25,
      O => NlwInverterSignal_EXP41_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP41_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP41_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP41_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_25_IBUF,
      O => NlwInverterSignal_EXP41_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP42_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP42_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP42_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_7,
      O => NlwInverterSignal_EXP42_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP42_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP42_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP42_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_7_IBUF,
      O => NlwInverterSignal_EXP42_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP43_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP43_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP43_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_10,
      O => NlwInverterSignal_EXP43_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP43_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP43_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP43_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_10_IBUF,
      O => NlwInverterSignal_EXP43_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP44_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP44_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP44_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_9,
      O => NlwInverterSignal_EXP44_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP44_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP44_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP44_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_9_IBUF,
      O => NlwInverterSignal_EXP44_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP45_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP45_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP45_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP45_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP45_EXP_PT_0_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP45_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP45_EXP_PT_0_IN4 : X_INV
    port map (
      I => REG_0_9,
      O => NlwInverterSignal_EXP45_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP45_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP45_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP45_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP45_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP45_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP45_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP45_EXP_PT_1_IN6 : X_INV
    port map (
      I => DIN_9_IBUF,
      O => NlwInverterSignal_EXP45_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP45_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP45_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP45_EXP_PT_2_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP45_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP45_EXP_PT_2_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP45_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP45_EXP_PT_2_IN5 : X_INV
    port map (
      I => REG_0_9,
      O => NlwInverterSignal_EXP45_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP46_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP46_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP46_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP46_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP46_EXP_PT_0_IN3 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP46_EXP_PT_0_IN3
    );
  NlwInverterBlock_EXP46_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_0_7,
      O => NlwInverterSignal_EXP46_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP46_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP46_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP46_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP46_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP46_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP46_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP46_EXP_PT_1_IN6 : X_INV
    port map (
      I => REG_0_7,
      O => NlwInverterSignal_EXP46_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP46_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP46_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP46_EXP_PT_2_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP46_EXP_PT_2_IN2
    );
  NlwInverterBlock_EXP46_EXP_PT_2_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP46_EXP_PT_2_IN4
    );
  NlwInverterBlock_EXP46_EXP_PT_2_IN5 : X_INV
    port map (
      I => DIN_7_IBUF,
      O => NlwInverterSignal_EXP46_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP47_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP47_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP47_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_8,
      O => NlwInverterSignal_EXP47_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP47_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP47_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP47_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_8_IBUF,
      O => NlwInverterSignal_EXP47_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP48_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP48_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP48_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_1,
      O => NlwInverterSignal_EXP48_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP48_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP48_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP48_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_1_IBUF,
      O => NlwInverterSignal_EXP48_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP49_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP49_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP49_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_5,
      O => NlwInverterSignal_EXP49_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP49_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP49_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP49_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_5_IBUF,
      O => NlwInverterSignal_EXP49_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP50_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_EXP50_EXP_tsimrenamed_net_IN5 : X_INV
    port map (
      I => DIN_6_IBUF,
      O => NlwInverterSignal_EXP50_EXP_tsimrenamed_net_IN5
    );
  NlwInverterBlock_EXP51_EXP_tsimrenamed_net_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN0
    );
  NlwInverterBlock_EXP51_EXP_tsimrenamed_net_IN6 : X_INV
    port map (
      I => REG_1_6,
      O => NlwInverterSignal_EXP51_EXP_tsimrenamed_net_IN6
    );
  NlwInverterBlock_EXP52_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP52_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP52_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP52_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP52_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP52_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP52_EXP_PT_1_IN4 : X_INV
    port map (
      I => DIN_0_IBUF,
      O => NlwInverterSignal_EXP52_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP52_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP52_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP52_EXP_PT_2_IN6 : X_INV
    port map (
      I => REG_1_0,
      O => NlwInverterSignal_EXP52_EXP_PT_2_IN6
    );
  NlwInverterBlock_EXP53_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP53_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP53_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP53_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP53_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_1_3,
      O => NlwInverterSignal_EXP53_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP53_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP53_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP53_EXP_PT_1_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP53_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP53_EXP_PT_1_IN4 : X_INV
    port map (
      I => REG_1_2,
      O => NlwInverterSignal_EXP53_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP53_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP53_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP53_EXP_PT_2_IN6 : X_INV
    port map (
      I => REG_1_3,
      O => NlwInverterSignal_EXP53_EXP_PT_2_IN6
    );
  NlwInverterBlock_EXP53_EXP_PT_3_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP53_EXP_PT_3_IN0
    );
  NlwInverterBlock_EXP53_EXP_PT_3_IN5 : X_INV
    port map (
      I => DIN_3_IBUF,
      O => NlwInverterSignal_EXP53_EXP_PT_3_IN5
    );
  NlwInverterBlock_EXP54_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP54_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP54_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_16,
      O => NlwInverterSignal_EXP54_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP54_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP54_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP54_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_16_IBUF,
      O => NlwInverterSignal_EXP54_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP55_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP55_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP55_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP55_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP55_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_1_13,
      O => NlwInverterSignal_EXP55_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP55_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP55_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP55_EXP_PT_1_IN6 : X_INV
    port map (
      I => REG_1_13,
      O => NlwInverterSignal_EXP55_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP55_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP55_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP55_EXP_PT_2_IN5 : X_INV
    port map (
      I => DIN_13_IBUF,
      O => NlwInverterSignal_EXP55_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP56_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP56_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP56_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP56_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP56_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_1_11,
      O => NlwInverterSignal_EXP56_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP56_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP56_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP56_EXP_PT_1_IN6 : X_INV
    port map (
      I => REG_1_11,
      O => NlwInverterSignal_EXP56_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP56_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP56_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP56_EXP_PT_2_IN5 : X_INV
    port map (
      I => DIN_11_IBUF,
      O => NlwInverterSignal_EXP56_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP57_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP57_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP57_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_15,
      O => NlwInverterSignal_EXP57_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP57_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP57_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP57_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_15_IBUF,
      O => NlwInverterSignal_EXP57_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP58_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP58_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP58_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_14,
      O => NlwInverterSignal_EXP58_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP58_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP58_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP58_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_14_IBUF,
      O => NlwInverterSignal_EXP58_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP59_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP59_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP59_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_22,
      O => NlwInverterSignal_EXP59_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP59_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP59_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP59_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_22_IBUF,
      O => NlwInverterSignal_EXP59_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP60_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP60_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP60_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP60_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP60_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_1_19,
      O => NlwInverterSignal_EXP60_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP60_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP60_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP60_EXP_PT_1_IN6 : X_INV
    port map (
      I => REG_1_19,
      O => NlwInverterSignal_EXP60_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP60_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP60_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP60_EXP_PT_2_IN5 : X_INV
    port map (
      I => DIN_19_IBUF,
      O => NlwInverterSignal_EXP60_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP61_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP61_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP61_EXP_PT_0_IN1 : X_INV
    port map (
      I => LOAD_SREG_IBUF,
      O => NlwInverterSignal_EXP61_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP61_EXP_PT_0_IN5 : X_INV
    port map (
      I => REG_1_17,
      O => NlwInverterSignal_EXP61_EXP_PT_0_IN5
    );
  NlwInverterBlock_EXP61_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP61_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP61_EXP_PT_1_IN6 : X_INV
    port map (
      I => REG_1_17,
      O => NlwInverterSignal_EXP61_EXP_PT_1_IN6
    );
  NlwInverterBlock_EXP61_EXP_PT_2_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP61_EXP_PT_2_IN0
    );
  NlwInverterBlock_EXP61_EXP_PT_2_IN5 : X_INV
    port map (
      I => DIN_17_IBUF,
      O => NlwInverterSignal_EXP61_EXP_PT_2_IN5
    );
  NlwInverterBlock_EXP62_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP62_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP62_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_21,
      O => NlwInverterSignal_EXP62_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP62_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP62_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP62_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_21_IBUF,
      O => NlwInverterSignal_EXP62_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP63_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP63_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP63_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_20,
      O => NlwInverterSignal_EXP63_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP63_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP63_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP63_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_20_IBUF,
      O => NlwInverterSignal_EXP63_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP64_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP64_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP64_EXP_PT_0_IN1 : X_INV
    port map (
      I => SCLK,
      O => NlwInverterSignal_EXP64_EXP_PT_0_IN1
    );
  NlwInverterBlock_EXP64_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP64_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP65_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP65_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP65_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP65_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP65_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP65_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP65_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_10,
      O => NlwInverterSignal_EXP65_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP65_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP65_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP65_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP65_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP65_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP65_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP65_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_10_IBUF,
      O => NlwInverterSignal_EXP65_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP66_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP66_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP66_EXP_PT_0_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP66_EXP_PT_0_IN2
    );
  NlwInverterBlock_EXP66_EXP_PT_0_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP66_EXP_PT_0_IN4
    );
  NlwInverterBlock_EXP66_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_0_14,
      O => NlwInverterSignal_EXP66_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP66_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP66_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP66_EXP_PT_1_IN2 : X_INV
    port map (
      I => writeBufId(0),
      O => NlwInverterSignal_EXP66_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP66_EXP_PT_1_IN4 : X_INV
    port map (
      I => readBufId(0),
      O => NlwInverterSignal_EXP66_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP66_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_14_IBUF,
      O => NlwInverterSignal_EXP66_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP67_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP67_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP67_EXP_PT_1_IN1 : X_INV
    port map (
      I => LOAD_PRESCALER_IBUF,
      O => NlwInverterSignal_EXP67_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP67_EXP_PT_1_IN2 : X_INV
    port map (
      I => count(0),
      O => NlwInverterSignal_EXP67_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP68_EXP_PT_0_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP68_EXP_PT_0_IN0
    );
  NlwInverterBlock_EXP68_EXP_PT_0_IN6 : X_INV
    port map (
      I => REG_1_28,
      O => NlwInverterSignal_EXP68_EXP_PT_0_IN6
    );
  NlwInverterBlock_EXP68_EXP_PT_1_IN0 : X_INV
    port map (
      I => RES_IBUF,
      O => NlwInverterSignal_EXP68_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP68_EXP_PT_1_IN5 : X_INV
    port map (
      I => DIN_28_IBUF,
      O => NlwInverterSignal_EXP68_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP69_EXP_PT_1_IN0 : X_INV
    port map (
      I => buf_depth(0),
      O => NlwInverterSignal_EXP69_EXP_PT_1_IN0
    );
  NlwInverterBlock_EXP69_EXP_PT_1_IN1 : X_INV
    port map (
      I => buf_depth(1),
      O => NlwInverterSignal_EXP69_EXP_PT_1_IN1
    );
  NlwInverterBlock_EXP69_EXP_PT_1_IN2 : X_INV
    port map (
      I => SHIFT_CNT(0),
      O => NlwInverterSignal_EXP69_EXP_PT_1_IN2
    );
  NlwInverterBlock_EXP69_EXP_PT_1_IN3 : X_INV
    port map (
      I => SHIFT_CNT(1),
      O => NlwInverterSignal_EXP69_EXP_PT_1_IN3
    );
  NlwInverterBlock_EXP69_EXP_PT_1_IN4 : X_INV
    port map (
      I => SHIFT_CNT(2),
      O => NlwInverterSignal_EXP69_EXP_PT_1_IN4
    );
  NlwInverterBlock_EXP69_EXP_PT_1_IN5 : X_INV
    port map (
      I => SHIFT_CNT(3),
      O => NlwInverterSignal_EXP69_EXP_PT_1_IN5
    );
  NlwInverterBlock_EXP69_EXP_PT_1_IN6 : X_INV
    port map (
      I => SHIFT_CNT(4),
      O => NlwInverterSignal_EXP69_EXP_PT_1_IN6
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => PRLD);

end Structure;