-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/hpi_port.vhd,v 1.1 2008-09-04 17:48:15 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

	------------------------------------------------------------------
entity hpi_port is
	Port (
			rst			: in std_logic;
			clk			: in std_logic;
			we			: in std_logic;
			din			: in unsigned(31 downto 0);
			dout		: out unsigned(31 downto 0);
			hpi_d		: inout unsigned(15 downto 0);
			hpi_a		: out unsigned(1 downto 0);
			hpi_csn		: out std_logic;
			hpi_wrn		: out std_logic;
			hpi_rdn		: out std_logic
		);
	end hpi_port;

architecture Behavioral of hpi_port is

	type hpi_t is record
		d		: unsigned(15 downto 0);
		a		: unsigned(1 downto 0);
		cs		: std_logic;
		wr		: std_logic;
		rd		: std_logic;
		drive_d	: std_logic;
	end record;
	
	------------------------------------------------------------------
	begin

	proc_lcd_port:
	process(rst, clk)
	variable vhpi : hpi_t;
	begin
		if (rst = '1') then
			dout			<= (others => '0');
			vhpi.d			:= (others => '0');
			vhpi.a			:= (others => '0');
			vhpi.cs			:= '0';
			vhpi.wr			:= '0';
			vhpi.rd			:= '0';
			vhpi.drive_d	:= '0';
		elsif rising_edge(clk) then
			dout <= X"0000" & hpi_d;
			if we = '1' then
				vhpi.d			:= din(15 downto 0);
				vhpi.a			:= din(17 downto 16);
				vhpi.cs			:= din(18);
				vhpi.wr			:= din(19);
				vhpi.rd			:= din(20);
				vhpi.drive_d	:= din(21);
			end if;
		end if;	
		if vhpi.cs = '1' then	
			hpi_a	 <= vhpi.a;
		else
			hpi_a	 <= (others => 'Z');
		end if;
		if vhpi.drive_d = '1' and vhpi.rd = '0' then	
			hpi_d	 <= vhpi.d;
		else
			hpi_d	 <= (others => 'Z');
		end if;
		hpi_csn	<= not vhpi.cs;
		hpi_wrn	<= not vhpi.wr;
		hpi_rdn	<= not vhpi.rd;
	end process;
	------------------------------------------------------------------

end Behavioral;