--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   17:16:42 13.05.2007
-- Design Name:   tb_mix_cpx
-- Module Name:   tb_mix_cpx.vhd
-- Project Name:  mix_cpx
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; --  Imports the standard textio package.

library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;

library work;
use work.fixed_util_pkg.all;
use work.PCK_FIO.all;

ENTITY tb_undc_real IS
	Generic (
		nbits_data		: integer := 24;
		nbits_data_frac	: integer := 24;
		nbits_k			: integer := 24;
		nbits_k_frac	: integer := 24;
		has_in_reg		: boolean := true;
		rounding		: fixed_round_style_type := fixed_round;
		saturating		: fixed_overflow_style_type := fixed_saturate
        );
END tb_undc_real;

ARCHITECTURE behavior OF tb_undc_real IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT undc_real
	Generic
	(
		nbits_data		: integer;
		nbits_data_frac	: integer;
		nbits_k			: integer;
		nbits_k_frac	: integer;
		has_in_reg		: boolean;
		rounding		: fixed_round_style_type;
		saturating		: fixed_overflow_style_type
	);
	Port
	(
		srst		: in std_logic;
		clk			: in std_logic;
		din_valid	: in std_logic;
		din			: in sfixed;
		kin_valid	: in std_logic;
		kin			: in sfixed;
		dout_valid	: out std_logic;
		dout		: out sfixed;
		dc_out		: out sfixed
	);
	END COMPONENT;

	--Constants
	constant PERIOD : time := 10 ns;
	

	--Inputs
	SIGNAL clk       : std_logic := '0';
	SIGNAL srst      : std_logic := '1';
	SIGNAL din_valid : std_logic := '0';
	SIGNAL kin_valid : std_logic := '0';
	SIGNAL din	     : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
	SIGNAL kin	     : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low);

	--Outputs
	SIGNAL dout	     : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
	SIGNAL dc_out	     : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
	SIGNAL dout_valid   : std_logic;
	
	SIGNAL k    : real := 0.0;
	SIGNAL x    : real := 0.0;
	SIGNAL y    : real := 0.0;
	SIGNAL dc    : real := 0.0;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: undc_real 
	GENERIC MAP
	(
		nbits_data		=> nbits_data,
		nbits_data_frac	=> nbits_data_frac,
		nbits_k			=> nbits_k,
		nbits_k_frac	=> nbits_k_frac,
		has_in_reg		=> has_in_reg,
		rounding		=> rounding,
		saturating		=> saturating
	)
	PORT MAP
	(
		srst		=> srst,
		clk			=> clk,
		din_valid	=> din_valid,
		din			=> din,
		kin_valid	=> kin_valid,
		kin			=> kin,
		dout_valid	=> dout_valid,
		dout		=> dout,
		dc_out		=> dc_out
	);

 	tb_clk : PROCESS
	BEGIN
		clk <= not clk;
		wait for PERIOD/2;
	END PROCESS;

	tb : PROCESS

	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 4*PERIOD;
		srst <= '0';
		------------------------------------------
		-- Load k
		------------------------------------------
		wait for 2*PERIOD;
		wait until rising_edge(clk);
		kin <= to_sfixed(0.0005, kin);
		kin_valid <= '1';
		wait until rising_edge(clk);
		kin_valid <= '1';
		------------------------------------------
		-- Process
		------------------------------------------
		wait for 2*PERIOD;
		wait until rising_edge(clk);
		din <= to_sfixed(0.5, din);
		din_valid <= '1';
		wait until rising_edge(clk);
		din_valid <= '1';
		wait for 5*PERIOD;

		wait for 200*PERIOD;

		assert false report "Test finished" severity error;
		wait; 
	END PROCESS;
	
	k <= to_real(kin);
	x <= to_real(din);
	y <= to_real(dout);
	dc <= to_real(dc_out);
	
END;