-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: Reset generator (Virtex-4 specific)
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

Library UNISIM;
use UNISIM.vcomponents.all;

entity reset is
	port
	(
		clk			: in std_logic;
		rst_in		: in std_logic;
		rst_out		: out std_logic
	);
end;

architecture tech of reset is
   
	signal rst : std_logic;
	signal shift_pipe : std_logic_vector(3 downto 0);
	attribute KEEP : string;
	attribute KEEP of shift_pipe	: signal is "TRUE";

begin
   
	rst <= shift_pipe(0);

bufg_reset: bufg
	port map
	(
		o  => rst_out,  
		i  => rst
	);
	
fdp0: fdp
	generic map 
	(
		init	=> '1'
	)
	port map 
	(
		d		=> rst_in,
		c		=> clk,
		pre		=> '0',
		q		=> shift_pipe(3)
	);

fdp1: fdp
	generic map 
	(
		init	=> '1'
	)
	port map
	(

		d		=> shift_pipe(3),
		c		=> clk,
		pre		=> '0',
		q		=> shift_pipe(2)
	);

fdp2: fdp
	generic map 
	(
		init	=> '1'
	)
	port map
	(
		d		=> shift_pipe(2),
		c		=> clk,
		pre		=> '0',
		q		=> shift_pipe(1)
	);

fdp3: fdp
	generic map 
	(
		init	=> '1'
	)
	port map
	(

		d		=> shift_pipe(1),
		c		=> clk,
		pre		=> '0',
		q		=> shift_pipe(0)
	);
  
end tech;