-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY eval2clk_tb IS
END eval2clk_tb;

ARCHITECTURE behavior OF eval2clk_tb IS 

	COMPONENT eval2clk
	PORT(
		RES : IN std_logic;
		CLK : IN std_logic;    
		SCLK : INOUT std_logic;      
		dummy_out : INOUT std_logic
		);
	END COMPONENT;


	SIGNAL RES :  std_logic := '1';
	SIGNAL CLK :  std_logic := '0';
	SIGNAL SCLK :  std_logic;
	SIGNAL dummy_out :  std_logic := '0';

	constant ClockPeriod : Time := 16.667 ns;

BEGIN

	uut: eval2clk PORT MAP(
		RES => RES,
		CLK => CLK,
		SCLK => SCLK,
		dummy_out => dummy_out
	);

	busclock: process
	begin
		CLK <= '1';
		loop
			wait for (ClockPeriod / 2);
			CLK <= not CLK;
		end loop;  
	end process;

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN

	   wait for 20*ClockPeriod;
		RES <= '0';


      wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;