--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    11:25:45 10/15/05
-- Design Name:    
-- Module Name:    vga_ctrl_core - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.vga_types.all;

entity vga_timing is
	Generic
	(
		tsvga		: vga_timespec_t	:= ts_vga_800_600_72
	);
	Port
	(
		sys_rst			: in std_logic;
		vga_clk			: in std_logic;
		vga_ce			: in std_logic;
		sync_h			: out std_logic;
		sync_v			: out std_logic;
		scan_pos_h		: out natural range 0 to tsvga.ts_h.ncyc_scan-1;
		scan_pos_v		: out natural range 0 to tsvga.ts_v.ncyc_scan-1;
		is_scan_h		: out std_logic;
		is_scan_v		: out std_logic;
		scan_rdy_h		: out std_logic;
		scan_rdy_v		: out std_logic
	);
end vga_timing;

architecture Behavioral of vga_timing is

	---------------------------------------------------------------------------------------------
	signal is_scan_h_i		: std_logic;
	signal is_scan_v_i		: std_logic;
	signal scan_rdy_h_i		: std_logic;
	signal scan_rdy_v_i		: std_logic;
	signal sync_h_i			: std_logic;
	signal sync_v_i			: std_logic;
	
	---------------------------------------------------------------------------------------------
begin

	is_scan_h	<= is_scan_h_i;
	is_scan_v	<= is_scan_v_i;
	scan_rdy_h	<= scan_rdy_h_i;
	scan_rdy_v	<= scan_rdy_v_i;
	sync_h		<= sync_h_i;
	sync_v		<= sync_v_i;
	
	---------------------------------------------------------------------------------------------
	inst_vga_sync_h: entity work.vga_sync 
	GENERIC MAP
	(
		ts => tsvga.ts_h
	)		
	PORT MAP
	(
		rst			=> sys_rst,
		clk			=> vga_clk,
		ce			=> vga_ce,
		pos			=> scan_pos_h,
		sync		=> sync_h_i,
		is_scan		=> is_scan_h_i,
		rdy_scan	=> scan_rdy_h_i
	);

	inst_vga_sync_v: entity work.vga_sync 
	GENERIC MAP 
	(
		ts => tsvga.ts_v
	)
	PORT MAP
	(
		rst			=> sys_rst,
		clk			=> vga_clk,
		ce			=> scan_rdy_h_i,
		pos			=> scan_pos_v,
		sync		=> sync_v_i,
		is_scan		=> is_scan_v_i,
		rdy_scan	=> scan_rdy_v_i
	);

---------------------------------------------------------------------------------------------

end Behavioral;