--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   13:58:47 10/15/2005
-- Design Name:   vga_ctrl_top
-- Module Name:   tb_vga_ctrl.vhd
-- Project Name:  vga_ctrl
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: vga_ctrl_top
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.vga_types.all;

ENTITY tb_vga_ctrl IS
END tb_vga_ctrl;

ARCHITECTURE behavior OF tb_vga_ctrl IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT vga_ctrl_top
    GENERIC
    (
		tsvga			: vga_timespec_t
	);
	PORT
	(
		rst_in : IN std_logic;
		clk_in : IN std_logic;    
		      
		-- VGA signals
		vga_clk_in : IN std_logic;
		vga_clk_ce : IN std_logic;
		vga_red : OUT unsigned(7 downto 0);
		vga_green : OUT unsigned(7 downto 0);
		vga_blue : OUT unsigned(7 downto 0);
		vga_blank_n : OUT std_logic;
		vga_sync_n : OUT std_logic;
		vga_hsync : OUT std_logic;
		vga_vsync : OUT std_logic;
		
		-- Buttons and LEDs
		dip : in unsigned(7 downto 0);
		btn : in unsigned(4 downto 0);
		led : out unsigned(8 downto 0)
	);
	END COMPONENT;

	--Constants
	constant tsvga			: vga_timespec_t := ts_vga_testbench;
	constant PERIOD : time := 10 ns;
	constant CLK_PERIOD		: time := 10 ns;
	constant VGA_CLK_PERIOD	: time := (integer(1E9) / tsvga.f_pxl_clk) * 1 ns;

	--Inputs
	SIGNAL rst_in :  std_logic := '1';
	SIGNAL clk_in :  std_logic := '0';
	SIGNAL color_en :  unsigned(2 downto 0) := (others => '0');
	SIGNAL dip :  unsigned(7 downto 0) := (others => '0');
	SIGNAL btn :  unsigned(4 downto 0) := (others => '0');

	--Outputs
	SIGNAL vga_clk_ce :  std_logic := '1';
	SIGNAL vga_clk_in :  std_logic := '0';
	SIGNAL vga_red :  unsigned(7 downto 0);
	SIGNAL vga_green :  unsigned(7 downto 0);
	SIGNAL vga_blue :  unsigned(7 downto 0);
	SIGNAL vga_blank_n :  std_logic;
	SIGNAL vga_sync_n :  std_logic;
	SIGNAL vga_hsync :  std_logic;
	SIGNAL vga_vsync :  std_logic;
	SIGNAL led :  unsigned(8 downto 0);
	constant f_sys : real := 100.0;
	constant f_vga : real := 130.0;
--	SIGNAL test_M : natural := VGA_FREQ_M(f_sys, f_vga);
--	SIGNAL test_D : natural := VGA_FREQ_D(f_sys, f_vga);
	
BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: vga_ctrl_top 
	GENERIC MAP 
	(
		tsvga		=> tsvga
	)
	PORT MAP
	(
		rst_in => rst_in,
		clk_in => clk_in,

		vga_clk_in => vga_clk_in,
		vga_clk_ce => vga_clk_ce,
		vga_red => vga_red,
		vga_green => vga_green,
		vga_blue => vga_blue,
		vga_blank_n => vga_blank_n,
		vga_sync_n => vga_sync_n,
		vga_hsync => vga_hsync,
		vga_vsync => vga_vsync,
		
		dip => dip,
		btn => btn,
		led => led
	);

 	clk : PROCESS
	BEGIN
		clk_in <= not clk_in;
		wait for CLK_PERIOD/2;
	END PROCESS;

 	vga_clk : PROCESS
	BEGIN
		vga_clk_in <= not vga_clk_in;
		wait for VGA_CLK_PERIOD/2;
	END PROCESS;

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100*CLK_PERIOD;
		rst_in <= '0';

		wait for CLK_PERIOD;
		dip <= X"AA";

		wait for CLK_PERIOD;
		color_en <= "100";

		wait for 10*CLK_PERIOD;
		color_en <= "000";

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;