work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx_types.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx_instr.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\alu_types.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out_reset.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_out.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_file.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\reg.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\mux2.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\ir_extender.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\controller.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\alu.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out_reset-behavior.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out-behavior.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_out-behavior.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_file-behavior.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\reg-behavior.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\mux2-behavior.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\ir_extender-behavior.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\controller-behavior.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\alu-behavior.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\memory.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\clock_gen.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\memory-file_loaded.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx-rtl.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\clock_gen-behavior.vhdl"
work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx_test-verifier.vhdl"