--------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: JIPS top file 
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

library work;
use work.mips_types.all;

entity mips_embedded_syn is
	Port
	(
		sys_rst_n_in		: in  STD_LOGIC;
		sys_clk_in			: in  STD_LOGIC;
		sys_dip				: in  STD_LOGIC_VECTOR (7 downto 0);
		sys_btn				: in  STD_LOGIC_VECTOR (8 downto 0);
		sys_led				: out STD_LOGIC_VECTOR (7 downto 0);
		sys_rx				: in  STD_LOGIC;
		sys_tx				: out STD_LOGIC;
		sys_error			: out STD_LOGIC_VECTOR (1 downto 0)
	);
	
end mips_embedded_syn;

architecture struct of mips_embedded_syn is

	COMPONENT mips_embedded
	Port 
	(
		rst			: in  STD_LOGIC;
		clk			: in  STD_LOGIC;
		halt		: in  STD_LOGIC;
		int			: in  unsigned(5 downto 0);
		rxd			: in  STD_LOGIC;
		txd			: out STD_LOGIC;
		dout		: out word_t
	);
	END COMPONENT;

	signal dout			: word_t;
	signal rst			: STD_LOGIC;
	signal clk			: STD_LOGIC;
	signal halt			: STD_LOGIC;
	signal int			: unsigned(5 downto 0);
	signal btn_r		: unsigned (8 downto 0);
	signal dip_r		: unsigned (7 downto 0);

begin

-------------------------------------------------------------------
inst_mips_embedded: mips_embedded
	PORT MAP
	(
		rst				=> rst,
		clk				=> clk,
		halt			=> halt,
		int				=> int,
		rxd				=> sys_rx,
		txd				=> sys_tx,
		dout			=> dout
	);

	clk		<= sys_clk_in;
	rst		<= not sys_rst_n_in;

ERR_LED_reg:
	process(rst, clk)
	begin
		if rst = '1' then
			sys_error <= (others => '1');
		elsif rising_edge(clk) then
			sys_error <= STD_LOGIC_VECTOR(dout(31 downto 30));
		end if;
	end process;

LED_reg:
	process(rst, clk)
	begin
		if rst = '1' then
			sys_led <= (others => '0');
		elsif rising_edge(clk) then
			sys_led <= STD_LOGIC_VECTOR(dout(7 downto 0));
		end if;
	end process;

DIP_reg:
	process(rst, clk)
	begin
		if rst = '1' then
			dip_r <= (others => '0');
		elsif rising_edge(clk) then
			dip_r <= unsigned(sys_dip);
		end if;
	end process;

BTN_reg:
	process(rst, clk)
	begin
		if rst = '1' then
			btn_r <= (others => '0');
		elsif rising_edge(clk) then
			btn_r <= unsigned(sys_btn);
		end if;
	end process;

	halt <= btn_r(4) after 6.5 ns;
	int(0)	<= dip_r(0) and btn_r(3) after 1 ns;
	int(1)	<= dip_r(1) and btn_r(3) after 1 ns;
	int(2)	<= dip_r(2) and btn_r(3) after 1 ns;
	int(3)	<= dip_r(3) and btn_r(3) after 1 ns;
	int(4)	<= dip_r(4) and btn_r(3) after 1 ns;
	int(5)	<= dip_r(5) and btn_r(3) after 1 ns;
	
-------------------------------------------------------------------
	
end struct;