-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for embedded cpu with rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; --  Imports the standard textio package.

library work;
use work.cpu_pkg.all;

ENTITY tb_cpu_embedded IS
END tb_cpu_embedded;

ARCHITECTURE behavior OF tb_cpu_embedded IS 

	COMPONENT cpu_embedded
	Port (
		rst			: in  STD_LOGIC;
		clk			: in  STD_LOGIC;
		ce			: in  STD_LOGIC;
		int_in		: in  STD_LOGIC;
		int_ack		: out  STD_LOGIC;
		xmem_we		: out STD_LOGIC;
		xmem_re		: out STD_LOGIC;
		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
		io_sel		: out STD_LOGIC
	);
	END COMPONENT;

	constant CLK_PERIOD : time := 10 ns;
	type sram_t is array (integer range <>) of dmem_data_t;
	signal rst : std_logic := '1';
	signal clk : std_logic := '1';
	signal ce  : std_logic := '0';
	signal int_in : std_logic := '0';
	signal int_ack : std_logic;
	signal xmem_din : dmem_data_t := (others => '-');
	signal xmem_dout : dmem_data_t;
	signal xmem_addr : dmem_addr_t;
	signal xmem_we : std_logic;
	signal xmem_re : std_logic;
	signal io_sel : std_logic;
	signal sram : sram_t(0 to 2**dmem_addr_t'length-1);
	

BEGIN

uut: cpu_embedded
	PORT MAP(
		rst => rst,
		clk => clk,
		ce => ce,
		int_in => int_in,
		int_ack => int_ack,
		xmem_we => xmem_we,
		xmem_re => xmem_re,
		xmem_din => xmem_din,
		xmem_dout => xmem_dout,
		xmem_addr => xmem_addr,
		io_sel => io_sel
	);

CLK_GEN: process
	begin
		wait for CLK_PERIOD/2;
		clk <= not clk;
	end process;

STIMULUS: process

	begin

		wait for 3*CLK_PERIOD;
		rst <= '0';
		wait for 2*CLK_PERIOD;
	
		wait until rising_edge(clk);
		ce <= '1';
	
		wait for 1000*CLK_PERIOD;

		wait; 
	
	end process;

SRAM_RW: process(rst, clk, xmem_addr, xmem_dout, xmem_we)
	begin
		if (rst = '1') then
			xmem_din <= X"00";
		elsif rising_edge(clk) then
			if io_sel = '0' then
				if xmem_we = '1' then	
					sram(to_integer(xmem_addr)) <= xmem_dout;
				end if;	
				xmem_din <= to_01(sram(to_integer(xmem_addr)));
			else
				xmem_din <= X"FF";
			end if;	
		end if;
	end process;
	
END;