-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: loadable ROM
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

library UNISIM;
use UNISIM.VComponents.all;

library work;
use work.cpu_pkg.all;

ENTITY xrom IS
	Port (
		clk			: in  STD_LOGIC;
		ce			: in  STD_LOGIC;
		addr		: in  dmem_addr_t;
		dout		: out dmem_data_t
	);
	
END xrom;

ARCHITECTURE loadable OF xrom IS 

	-- JASM_ROM_INSERT_HERE

	-- Assembled from reti_issue.jsm
	type xmem_rom_t is array (0 to 255) of dmem_data_t;
	signal xmem_rom : xmem_rom_t :=
	(
		X"00", -- 0x00
		X"00", -- 0x01
		X"00", -- 0x02
		X"00", -- 0x03
		X"00", -- 0x04
		X"00", -- 0x05
		X"00", -- 0x06
		X"00", -- 0x07
		X"00", -- 0x08
		X"00", -- 0x09
		X"00", -- 0x0A
		X"00", -- 0x0B
		X"00", -- 0x0C
		X"00", -- 0x0D
		X"00", -- 0x0E
		X"00", -- 0x0F
		X"00", -- 0x10
		X"00", -- 0x11
		X"00", -- 0x12
		X"00", -- 0x13
		X"00", -- 0x14
		X"00", -- 0x15
		X"00", -- 0x16
		X"00", -- 0x17
		X"00", -- 0x18
		X"00", -- 0x19
		X"00", -- 0x1A
		X"00", -- 0x1B
		X"00", -- 0x1C
		X"00", -- 0x1D
		X"00", -- 0x1E
		X"00", -- 0x1F
		X"00", -- 0x20
		X"00", -- 0x21
		X"00", -- 0x22
		X"00", -- 0x23
		X"00", -- 0x24
		X"00", -- 0x25
		X"00", -- 0x26
		X"00", -- 0x27
		X"00", -- 0x28
		X"00", -- 0x29
		X"00", -- 0x2A
		X"00", -- 0x2B
		X"00", -- 0x2C
		X"00", -- 0x2D
		X"00", -- 0x2E
		X"00", -- 0x2F
		X"00", -- 0x30
		X"00", -- 0x31
		X"00", -- 0x32
		X"00", -- 0x33
		X"00", -- 0x34
		X"00", -- 0x35
		X"00", -- 0x36
		X"00", -- 0x37
		X"00", -- 0x38
		X"00", -- 0x39
		X"00", -- 0x3A
		X"00", -- 0x3B
		X"00", -- 0x3C
		X"00", -- 0x3D
		X"00", -- 0x3E
		X"00", -- 0x3F
		X"00", -- 0x40
		X"00", -- 0x41
		X"00", -- 0x42
		X"00", -- 0x43
		X"00", -- 0x44
		X"00", -- 0x45
		X"00", -- 0x46
		X"00", -- 0x47
		X"00", -- 0x48
		X"00", -- 0x49
		X"00", -- 0x4A
		X"00", -- 0x4B
		X"00", -- 0x4C
		X"00", -- 0x4D
		X"00", -- 0x4E
		X"00", -- 0x4F
		X"00", -- 0x50
		X"00", -- 0x51
		X"00", -- 0x52
		X"00", -- 0x53
		X"00", -- 0x54
		X"00", -- 0x55
		X"00", -- 0x56
		X"00", -- 0x57
		X"00", -- 0x58
		X"00", -- 0x59
		X"00", -- 0x5A
		X"00", -- 0x5B
		X"00", -- 0x5C
		X"00", -- 0x5D
		X"00", -- 0x5E
		X"00", -- 0x5F
		X"00", -- 0x60
		X"00", -- 0x61
		X"00", -- 0x62
		X"00", -- 0x63
		X"00", -- 0x64
		X"00", -- 0x65
		X"00", -- 0x66
		X"00", -- 0x67
		X"00", -- 0x68
		X"00", -- 0x69
		X"00", -- 0x6A
		X"00", -- 0x6B
		X"00", -- 0x6C
		X"00", -- 0x6D
		X"00", -- 0x6E
		X"00", -- 0x6F
		X"00", -- 0x70
		X"00", -- 0x71
		X"00", -- 0x72
		X"00", -- 0x73
		X"00", -- 0x74
		X"00", -- 0x75
		X"00", -- 0x76
		X"00", -- 0x77
		X"00", -- 0x78
		X"00", -- 0x79
		X"00", -- 0x7A
		X"00", -- 0x7B
		X"00", -- 0x7C
		X"00", -- 0x7D
		X"00", -- 0x7E
		X"00", -- 0x7F
		X"00", -- 0x80
		X"00", -- 0x81
		X"00", -- 0x82
		X"00", -- 0x83
		X"00", -- 0x84
		X"00", -- 0x85
		X"00", -- 0x86
		X"00", -- 0x87
		X"00", -- 0x88
		X"00", -- 0x89
		X"00", -- 0x8A
		X"00", -- 0x8B
		X"00", -- 0x8C
		X"00", -- 0x8D
		X"00", -- 0x8E
		X"00", -- 0x8F
		X"00", -- 0x90
		X"00", -- 0x91
		X"00", -- 0x92
		X"00", -- 0x93
		X"00", -- 0x94
		X"00", -- 0x95
		X"00", -- 0x96
		X"00", -- 0x97
		X"00", -- 0x98
		X"00", -- 0x99
		X"00", -- 0x9A
		X"00", -- 0x9B
		X"00", -- 0x9C
		X"00", -- 0x9D
		X"00", -- 0x9E
		X"00", -- 0x9F
		X"00", -- 0xA0
		X"00", -- 0xA1
		X"00", -- 0xA2
		X"00", -- 0xA3
		X"00", -- 0xA4
		X"00", -- 0xA5
		X"00", -- 0xA6
		X"00", -- 0xA7
		X"00", -- 0xA8
		X"00", -- 0xA9
		X"00", -- 0xAA
		X"00", -- 0xAB
		X"00", -- 0xAC
		X"00", -- 0xAD
		X"00", -- 0xAE
		X"00", -- 0xAF
		X"00", -- 0xB0
		X"00", -- 0xB1
		X"00", -- 0xB2
		X"00", -- 0xB3
		X"00", -- 0xB4
		X"00", -- 0xB5
		X"00", -- 0xB6
		X"00", -- 0xB7
		X"00", -- 0xB8
		X"00", -- 0xB9
		X"00", -- 0xBA
		X"00", -- 0xBB
		X"00", -- 0xBC
		X"00", -- 0xBD
		X"00", -- 0xBE
		X"00", -- 0xBF
		X"00", -- 0xC0
		X"00", -- 0xC1
		X"00", -- 0xC2
		X"00", -- 0xC3
		X"00", -- 0xC4
		X"00", -- 0xC5
		X"00", -- 0xC6
		X"00", -- 0xC7
		X"00", -- 0xC8
		X"00", -- 0xC9
		X"00", -- 0xCA
		X"00", -- 0xCB
		X"00", -- 0xCC
		X"00", -- 0xCD
		X"00", -- 0xCE
		X"00", -- 0xCF
		X"00", -- 0xD0
		X"00", -- 0xD1
		X"00", -- 0xD2
		X"00", -- 0xD3
		X"00", -- 0xD4
		X"00", -- 0xD5
		X"00", -- 0xD6
		X"00", -- 0xD7
		X"00", -- 0xD8
		X"00", -- 0xD9
		X"00", -- 0xDA
		X"00", -- 0xDB
		X"00", -- 0xDC
		X"00", -- 0xDD
		X"00", -- 0xDE
		X"00", -- 0xDF
		X"00", -- 0xE0
		X"00", -- 0xE1
		X"00", -- 0xE2
		X"00", -- 0xE3
		X"00", -- 0xE4
		X"00", -- 0xE5
		X"00", -- 0xE6
		X"00", -- 0xE7
		X"00", -- 0xE8
		X"00", -- 0xE9
		X"00", -- 0xEA
		X"00", -- 0xEB
		X"00", -- 0xEC
		X"00", -- 0xED
		X"00", -- 0xEE
		X"00", -- 0xEF
		X"00", -- 0xF0
		X"00", -- 0xF1
		X"00", -- 0xF2
		X"00", -- 0xF3
		X"00", -- 0xF4
		X"00", -- 0xF5
		X"00", -- 0xF6
		X"00", -- 0xF7
		X"00", -- 0xF8
		X"00", -- 0xF9
		X"00", -- 0xFA
		X"00", -- 0xFB
		X"00", -- 0xFC
		X"00", -- 0xFD
		X"00", -- 0xFE
		X"00"  -- 0xFF
	);

	signal jtag_ld_clk		: STD_LOGIC;
	signal jtag_ld_we		: STD_LOGIC;
	signal jtag_ld_addr		: dmem_addr_t;
	signal jtag_ld_dout		: dmem_data_t;
	signal jtag_ld_din		: dmem_data_t;
	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
	signal user_regi, user_rego : unsigned (15 downto 0);
	constant id : unsigned (15 downto 0) := X"BEEF";

begin

--------------------------------------------------------------------------
-- Virtex-4: JTAG Loader
--------------------------------------------------------------------------
	i00_BUFG : BUFG
	port map
	(
		O => bs_clk1,
        I => bs_clk0
	);
	
	i01_BUFG : BUFG
	port map
	(
		O => bs_update1,
        I => bs_update0
	);

	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
	generic map
	(
		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
	)
	port map 
	(
		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
		DRCK => bs_clk0,       -- Data register output for USER functions
		RESET => bs_rst,       -- Reset output from TAP controller
		SEL => bs_sel,         -- USER active output
		SHIFT => bs_shift,     -- SHIFT output from TAP controller
		TDI => bs_tdi,        -- TDI output from TAP controller
		UPDATE => bs_update0,   -- UPDATE output from TAP controller
		TDO => bs_tdo         -- Data input for USER function
	);

	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
	jtag_ld_clk <= bs_update1;
	jtag_ld_we <= bs_sel;
	
sipo:
	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
	begin
		if bs_rst = '1' then
			user_regi <= (others => '0');
		elsif rising_edge(bs_clk1) then
			if bs_shift = '1' then
				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
			end if;
		end if;
	end process;	

piso:
	process (bs_rst, bs_clk1, bs_shift, user_rego)
	begin
		bs_tdo <= user_rego(0);
		if bs_rst = '1' then
			user_rego <= (others => '0');
		elsif rising_edge(bs_clk1) then
			if bs_shift = '1' then
				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
			else
				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
--				user_rego <= id;	
			end if;
		end if;
	end process;	
	
--------------------------------------------------------------------------
-- ROM Read/Write
--------------------------------------------------------------------------
PROM_READ: 
	process(clk, ce)
	begin
		if rising_edge(clk) and ce = '1' then
			dout <= xmem_rom(to_integer(addr));
		end if;
	end process;

PROM_WRITE: 
	process(jtag_ld_clk, jtag_ld_we)
	begin
		if rising_edge(jtag_ld_clk) then
			if jtag_ld_we = '1' then
				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
			else	
				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
			end if;
		end if;	
	end process;

--------------------------------------------------------------------------
end loadable;