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-- Company: 
-- Engineer:
--
-- Create Date:   17:16:42 13.05.2007
-- Design Name:   tb_nco
-- Module Name:   tb_nco.vhd
-- Project Name:  nco
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;

library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;

library work;
use work.fixed_util_pkg.all;

	ENTITY syn_ddc IS
	Generic 
	(
		nbits_in			: integer := 16;
		nbits_in_frac		: integer := 14;
		nbits_out			: integer := 24;
		nbits_out_frac		: integer := 22;
		lo_nbits_phase		: integer := 20;
		lo_nbits_freq		: integer := 20;
		cic_nstages			: integer := 3;
		cic_ratio			: integer := 64;
		cic_scale_nbits		: integer := 18
	);
	PORT
	(
		rst					: in std_logic;
		clk					: in std_logic;
		lo_nco_rst			: in std_logic;
		lo_nco_en			: in std_logic;
		lo_freq_in			: in unsigned(lo_nbits_freq-1 downto 0);
		lo_phase_in			: in unsigned(lo_nbits_phase-1 downto 0);
		din_i				: in  signed(nbits_in-1 downto 0);
		din_q				: in  signed(nbits_in-1 downto 0);
		dout_i				: out signed(nbits_out-1 downto 0);
		dout_q				: out signed(nbits_out-1 downto 0);
		din_vld				: in  std_logic;
		dout_vld			: out std_logic
	);
	END syn_ddc;

ARCHITECTURE behavior OF syn_ddc IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ddc
	GENERIC 
	(
		nbits_in			: integer;
		nbits_in_frac		: integer;
		nbits_out			: integer;
		nbits_out_frac		: integer;
		lo_nbits_phase		: integer;
		lo_nbits_freq		: integer;
		cic_nstages			: integer;
		cic_ratio			: integer;
		cic_scale_nbits		: integer
	);
	PORT
	(
		rst					: in std_logic;
		clk					: in std_logic;
		lo_nco_rst			: in std_logic;
		lo_nco_en			: in std_logic;
		lo_freq_in			: in unsigned(lo_nbits_freq-1 downto 0);
		lo_phase_in			: in unsigned(lo_nbits_phase-1 downto 0);
		din_vld				: in  std_logic;
		din_i				: in  sfixed;
		din_q				: in  sfixed;
		dec_vld				: out std_logic;
		dec_i				: out sfixed;
		dec_q				: out sfixed;
		dout_vld			: out std_logic;
		dout_i				: out sfixed;
		dout_q				: out sfixed
	);
	END COMPONENT;

	--Outputs
	SIGNAL ddc_din_i		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
	SIGNAL ddc_din_q		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
	SIGNAL ddc_dout_i		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
	SIGNAL ddc_dout_q		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));

	SIGNAL dec_vld			: std_logic;
	SIGNAL ddc_dec_i		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
	SIGNAL ddc_dec_q		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	inst_ddc : ddc
	GENERIC MAP 
	(
		nbits_in			=> nbits_in,
		nbits_in_frac		=> nbits_in_frac,
		nbits_out			=> nbits_out,
		nbits_out_frac		=> nbits_out_frac,
		lo_nbits_phase		=> lo_nbits_phase,
		lo_nbits_freq		=> lo_nbits_freq,
		cic_nstages			=> cic_nstages,
		cic_ratio			=> cic_ratio,
		cic_scale_nbits		=> cic_scale_nbits
	)
	PORT MAP
	(
		rst					=> rst,
		clk					=> clk,
		lo_nco_rst			=> lo_nco_rst,
		lo_nco_en			=> lo_nco_en,
		lo_freq_in			=> lo_freq_in,
		lo_phase_in			=> lo_phase_in,
		din_vld				=> din_vld,
		din_i				=> ddc_din_i,
		din_q				=> ddc_din_q,
		dec_vld				=> dec_vld,
		dec_i				=> ddc_dec_i,
		dec_q				=> ddc_dec_q,
		dout_vld			=> dout_vld,
		dout_i				=> ddc_dout_i,
		dout_q				=> ddc_dout_q
	);
	
	ddc_din_i	<= to_sfixed(din_i, ddc_din_i);
	ddc_din_q	<= to_sfixed(din_q, ddc_din_q);
	
	dout_i	<= signed(ddc_dout_i);
	dout_q	<= signed(ddc_dout_q);
	
END;