-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read

-- Copyright (C) 2007 J. Ahrensfeld

-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.

-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- Lesser General Public License for more details.

-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA

-- For questions and ideas, please contact the author at jens@jayfield.org

-----------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity xmem_dual is
	Generic (
		addr_width : integer := 3;
		data_width : integer := 8
	);
	Port (
		clk			: in  STD_LOGIC;
		we			: in  STD_LOGIC;
		addr_w		: in  unsigned (addr_width-1 downto 0);
		addr_r		: in  unsigned (addr_width-1 downto 0);
		din			: in  unsigned (data_width-1 downto 0);
		dout		: out unsigned (data_width-1 downto 0)
	);
end xmem_dual;

architecture Behavioral of xmem_dual is

	constant depth : integer := 2**addr_width;
	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
	signal RAM : RAMtype;
	
begin

process (clk)
begin
if clk'event and clk = '1' then
	if we = '1' then
		RAM(to_integer(addr_w)) <= din;
	end if;
	dout <= RAM(to_integer(addr_r));
end if;
end process;

end Behavioral;