--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    12:37:26 10/02/05
-- Design Name:    
-- Module Name:    coeff_rom - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

library work;
use work.fixed_ja.all;
use work.cordic_pkg.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rom_arctan is
	Generic 
	(
	        nbits : integer := 8;
	        nbits_int : integer := 0
	);
	Port 
	(
			addr : in unsigned(6 downto 0);
			dout : out sfixed_t
	);
end rom_arctan;

architecture Behavioral of rom_arctan is

subtype word_t is sfixed_t(sproto(nbits, nbits_int)'high downto sproto(nbits, nbits_int)'low);
type rom_t is array (natural range <>) of word_t;

-------------------------------------------------------------------------------
function rom_gen(nstages : integer; round_mode : round_mode_t) return rom_t is
variable rom : rom_t (0 to nstages-1);
variable word : word_t;
begin

	for i in 0 to nstages-1 loop
		word := to_sfixed(arctan_tbl(i), word, round_mode);
		rom(i) := word;
	end loop;
	
	return rom;
end rom_gen;

-------------------------------------------------------------------------------
-- Create ROM
constant arctan_rom : rom_t (0 to max_iteration-1) := rom_gen(max_iteration, cordic_round_mode);

-------------------------------------------------------------------------------

begin

-- ROM implementation
rom_arctan: process(addr)
begin
	dout <= arctan_rom(to_integer(addr));
end process;

-------------------------------------------------------------------------------
end Behavioral;