--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    21:52:19 10/22/05
-- Design Name:    
-- Module Name:    singleshot - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-----------------------------------------------------------------------
-- Component Template
--
--	COMPONENT singleshot
--	GENERIC (mode : integer);
--	PORT(
--		rst : IN std_logic;
--		clk : IN std_logic;
--		input : IN std_logic;          
--		output : OUT std_logic
--		);
--	END COMPONENT;
--
-- Instantation Template
--
--	singleshot_int: oneshot 
--	GENERIC MAP (
--		mode => 1)		
--	PORT MAP(
--		rst => ,
--		clk => ,
--		input => ,
--		output => 
--	);
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity singleshot is
    Generic ( mode : integer range 0 to 2 := 1);
    Port ( rst : in std_logic;
           clk : in std_logic;
           input : in std_logic;
           output : out std_logic);
end singleshot;

architecture Behavioral of singleshot is

type s_t is (idle, shot_in, active, shot_out);
signal s, sn : s_t;

begin

process (rst, clk, sn)
begin
	if rising_edge(clk) then
		if rst = '1' then
			s <= idle;
		else
			s <= sn;
		end if;
	end if;	
end process;

mode_1:
if mode = 1 generate
begin
	process (input, s)
	begin
		output <= '0';
		sn <= s;
		case s is
			when idle =>
			if input = '1' then 
				sn <= shot_in;
			end if;	
			when shot_in =>
				output <= '1';
				sn <= active;
			when active =>
			if input = '0' then 
				sn <= shot_out;
			end if;
			when shot_out =>
				sn <= idle;
			when others => null;
		end case;	
	end process;
end generate;

mode_0:
if mode = 0 generate
begin
	process (input, s)
	begin
		output <= '0';
		sn <= s;
		case s is
			when idle =>
			if input = '1' then 
				sn <= shot_in;
			end if;	
			when shot_in =>
				sn <= active;
			when active =>
			if input = '0' then 
				sn <= shot_out;
			end if;
			when shot_out =>
				output <= '1';
				sn <= idle;
			when others => null;
		end case;	
	end process;
end generate;

mode_2:
if mode = 2 generate
begin
	process (input, s)
	begin
		output <= '0';
		sn <= s;
		case s is
			when idle =>
			if input = '1' then 
				sn <= shot_in;
			end if;	
			when shot_in =>
				output <= '1';
				sn <= active;
			when active =>
			if input = '0' then 
				sn <= shot_out;
			end if;
			when shot_out =>
				output <= '1';
				sn <= idle;
			when others => null;
		end case;	
	end process;
end generate;

end Behavioral;