-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/dcc_fpgacore.vhd,v 1.5 2006/03/16 00:57:41 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Digital Configuration Controller for FPGACORE -- /___/ /\ Filename : DCC_FPGACORE.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL DCC_FPGACORE ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity DCC_FPGACORE is generic ( DEVICE_SIZE : integer := 10 ); port ( BCLK : out std_ulogic; DONEOUT : out std_ulogic; DOUT0 : out std_ulogic; DOUT1 : out std_ulogic; DOUT2 : out std_ulogic; DOUT3 : out std_ulogic; DOUT4 : out std_ulogic; DOUT5 : out std_ulogic; DOUT6 : out std_ulogic; DOUT7 : out std_ulogic; GSR : out std_ulogic; GTS : out std_ulogic; GWE : out std_ulogic; INITBOUT : out std_ulogic; TDO : out std_ulogic; CCLK : in std_ulogic; CSB : in std_ulogic; DIN0 : in std_ulogic; DIN1 : in std_ulogic; DIN2 : in std_ulogic; DIN3 : in std_ulogic; DIN4 : in std_ulogic; DIN5 : in std_ulogic; DIN6 : in std_ulogic; DIN7 : in std_ulogic; DONEIN : in std_ulogic; LBISTISOLATEB : in std_ulogic; M0 : in std_ulogic; M1 : in std_ulogic; M2 : in std_ulogic; PROGB : in std_ulogic; TCK : in std_ulogic; TDI : in std_ulogic; TMS : in std_ulogic; WRITEB : in std_ulogic ); end DCC_FPGACORE; architecture DCC_FPGACORE_V of DCC_FPGACORE is component DCC_FPGACORE_SWIFT_BUS port ( BCLK : out std_ulogic; DONEOUT : out std_ulogic; DOUT0 : out std_ulogic; DOUT1 : out std_ulogic; DOUT2 : out std_ulogic; DOUT3 : out std_ulogic; DOUT4 : out std_ulogic; DOUT5 : out std_ulogic; DOUT6 : out std_ulogic; DOUT7 : out std_ulogic; GSR : out std_ulogic; GTS : out std_ulogic; GWE : out std_ulogic; INITBOUT : out std_ulogic; TDO : out std_ulogic; CCLK : in std_ulogic; CSB : in std_ulogic; DIN0 : in std_ulogic; DIN1 : in std_ulogic; DIN2 : in std_ulogic; DIN3 : in std_ulogic; DIN4 : in std_ulogic; DIN5 : in std_ulogic; DIN6 : in std_ulogic; DIN7 : in std_ulogic; DONEIN : in std_ulogic; LBISTISOLATEB : in std_ulogic; M0 : in std_ulogic; M1 : in std_ulogic; M2 : in std_ulogic; PROGB : in std_ulogic; TCK : in std_ulogic; TDI : in std_ulogic; TMS : in std_ulogic; WRITEB : in std_ulogic; XBID : in std_logic_vector(8 downto 0) ); end component; signal XBID_BINARY : std_logic_vector(8 downto 0); begin DCC_FPGACORE_inst : DCC_FPGACORE_SWIFT_BUS port map ( XBID => XBID_BINARY, CCLK => CCLK, CSB => CSB, DIN0 => DIN0, DIN1 => DIN1, DIN2 => DIN2, DIN3 => DIN3, DIN4 => DIN4, DIN5 => DIN5, DIN6 => DIN6, DIN7 => DIN7, DONEIN => DONEIN, LBISTISOLATEB => LBISTISOLATEB, M0 => M0, M1 => M1, M2 => M2, PROGB => PROGB, TCK => TCK, TDI => TDI, TMS => TMS, WRITEB => WRITEB, BCLK => BCLK, DONEOUT => DONEOUT, DOUT0 => DOUT0, DOUT1 => DOUT1, DOUT2 => DOUT2, DOUT3 => DOUT3, DOUT4 => DOUT4, DOUT5 => DOUT5, DOUT6 => DOUT6, DOUT7 => DOUT7, GSR => GSR, GTS => GTS, GWE => GWE, INITBOUT => INITBOUT, TDO => TDO ); INIPROC : process begin case DEVICE_SIZE is when 10 => XBID_BINARY <= "000001010"; when 20 => XBID_BINARY <= "000010100"; when 40 => XBID_BINARY <= "000101000"; when others => assert FALSE report "Error : DEVICE_SIZE is not in 10, 20, 40." severity warning; end case; wait; end process INIPROC; end DCC_FPGACORE_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_10ge_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for 10GE I/O Standard 4 Byte Data -- /___/ /\ Filename : GT10_10GE_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_10GE_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_10GE_4 is generic ( CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := TRUE; CHAN_BOND_64B66B_SV : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := TRUE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_CORRECT_USE : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SH_CNT_MAX : integer := 64; SH_INVALID_CNT_MAX : integer := 16; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_10GE_4; -- Architecture body -- architecture GT10_10GE_4_V of GT10_10GE_4 is signal OPEN4 : std_logic_vector(3 downto 0); signal OPEN32 : std_logic_vector(31 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => 8, CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "10000011110", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => 8, CLK_CORRECT_USE => CLK_CORRECT_USE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "6_32", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SH_CNT_MAX => SH_CNT_MAX, SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 4) => OPEN4, RXCHARISK(3 downto 0) => RXCHARISK, RXCHARISK(7 downto 4) => OPEN4, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(31 downto 0) => RXDATA, RXDATA(63 downto 32) => OPEN32, RXDISPERR(3 downto 0) => RXDISPERR, RXDISPERR(7 downto 4) => OPEN4, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 4) => OPEN4, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(3 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 4) => OPEN4, TXBUFERR => TXBUFERR, TXKERR(3 downto 0) => TXKERR, TXKERR(7 downto 4) => OPEN4, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(3 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 4) => OPEN4, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 4) => z4, TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 4) => z4, TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 4) => z4, TXCHARISK(3 downto 0) => TXCHARISK, TXCHARISK(7 downto 4) => z4, TXDATA(31 downto 0) => TXDATA, TXDATA(63 downto 32) => z32, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_10GE_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_10ge_8.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for 10GE I/O Standard 8 Byte Data -- /___/ /\ Filename : GT10_10GE_8.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_10GE_8 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_10GE_8 is generic ( CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := TRUE; CHAN_BOND_64B66B_SV : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := TRUE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_CORRECT_USE : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SH_CNT_MAX : integer := 64; SH_INVALID_CNT_MAX : integer := 16; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(7 downto 0); RXCHARISK : out std_logic_vector(7 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(63 downto 0); RXDISPERR : out std_logic_vector(7 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(7 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(7 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(7 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(7 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(7 downto 0); TXCHARDISPMODE : in std_logic_vector(7 downto 0); TXCHARDISPVAL : in std_logic_vector(7 downto 0); TXCHARISK : in std_logic_vector(7 downto 0); TXDATA : in std_logic_vector(63 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_10GE_8; -- Architecture body -- architecture GT10_10GE_8_V of GT10_10GE_8 is begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => 8, CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "10000011110", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => 8, CLK_CORRECT_USE => CLK_CORRECT_USE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "6_64", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SH_CNT_MAX => SH_CNT_MAX, SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP => RXRUNDISP, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP => TXRUNDISP, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_10GE_8_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_10gfc_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for 10GFC I/O Standard 4 Byte Data -- /___/ /\ Filename : GT10_10GFC_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_10GFC_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_10GFC_4 is generic ( CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := TRUE; CHAN_BOND_64B66B_SV : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := TRUE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_CORRECT_USE : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SH_CNT_MAX : integer := 64; SH_INVALID_CNT_MAX : integer := 16; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_10GFC_4; -- Architecture body -- architecture GT10_10GFC_4_V of GT10_10GFC_4 is signal OPEN4 : std_logic_vector(3 downto 0); signal OPEN32 : std_logic_vector(31 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => 8, CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "10000011110", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => 8, CLK_CORRECT_USE => CLK_CORRECT_USE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "0_32", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SH_CNT_MAX => SH_CNT_MAX, SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 4) => OPEN4, RXCHARISK(3 downto 0) => RXCHARISK, RXCHARISK(7 downto 4) => OPEN4, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(31 downto 0) => RXDATA, RXDATA(63 downto 32) => OPEN32, RXDISPERR(3 downto 0) => RXDISPERR, RXDISPERR(7 downto 4) => OPEN4, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 4) => OPEN4, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(3 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 4) => OPEN4, TXBUFERR => TXBUFERR, TXKERR(3 downto 0) => TXKERR, TXKERR(7 downto 4) => OPEN4, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(3 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 4) => OPEN4, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 4) => z4, TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 4) => z4, TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 4) => z4, TXCHARISK(3 downto 0) => TXCHARISK, TXCHARISK(7 downto 4) => z4, TXDATA(31 downto 0) => TXDATA, TXDATA(63 downto 32) => z32, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_10GFC_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_10gfc_8.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for 10GFC I/O Standard 8 Byte Data -- /___/ /\ Filename : GT10_10GFC_8.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_10GFC_8 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_10GFC_8 is generic ( CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := TRUE; CHAN_BOND_64B66B_SV : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := TRUE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_CORRECT_USE : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SH_CNT_MAX : integer := 64; SH_INVALID_CNT_MAX : integer := 16; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(7 downto 0); RXCHARISK : out std_logic_vector(7 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(63 downto 0); RXDISPERR : out std_logic_vector(7 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(7 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(7 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(7 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(7 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(7 downto 0); TXCHARDISPMODE : in std_logic_vector(7 downto 0); TXCHARDISPVAL : in std_logic_vector(7 downto 0); TXCHARISK : in std_logic_vector(7 downto 0); TXDATA : in std_logic_vector(63 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_10GFC_8; -- Architecture body -- architecture GT10_10GFC_8_V of GT10_10GFC_8 is begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => 8, CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "10000011110", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => 8, CLK_CORRECT_USE => CLK_CORRECT_USE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "0_64", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SH_CNT_MAX => SH_CNT_MAX, SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP => RXRUNDISP, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP => TXRUNDISP, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_10GFC_8_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_aurora_1.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for AURORA I/O Standard 1 Byte Data -- /___/ /\ Filename : GT10_AURORA_1.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_AURORA_1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_AURORA_1 is generic ( ALIGN_COMMA_WORD : integer := 1; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_CORRECT_USE : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32263068090104a628"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(0 downto 0); RXCHARISK : out std_logic_vector(0 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(7 downto 0); RXDISPERR : out std_logic_vector(0 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(0 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(0 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(0 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(0 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(0 downto 0); TXCHARDISPMODE : in std_logic_vector(0 downto 0); TXCHARDISPVAL : in std_logic_vector(0 downto 0); TXCHARISK : in std_logic_vector(0 downto 0); TXDATA : in std_logic_vector(7 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_AURORA_1; -- Architecture body -- architecture GT10_AURORA_1_V of GT10_AURORA_1 is signal OPEN7 : std_logic_vector(6 downto 0); signal OPEN56 : std_logic_vector(55 downto 0); signal z7 : std_logic_vector(6 downto 0) := "0000000"; signal z56 : std_logic_vector(55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 2, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00100011100", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => 2, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "25_10", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 1) => OPEN7, RXCHARISK(0 downto 0) => RXCHARISK, RXCHARISK(7 downto 1) => OPEN7, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(7 downto 0) => RXDATA, RXDATA(63 downto 8) => OPEN56, RXDISPERR(0 downto 0) => RXDISPERR, RXDISPERR(7 downto 1) => OPEN7, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 1) => OPEN7, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(0 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 1) => OPEN7, TXBUFERR => TXBUFERR, TXKERR(0 downto 0) => TXKERR, TXKERR(7 downto 1) => OPEN7, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(0 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 1) => OPEN7, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 1) => z7, TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 1) => z7, TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 1) => z7, TXCHARISK(0 downto 0) => TXCHARISK, TXCHARISK(7 downto 1) => z7, TXDATA(7 downto 0) => TXDATA, TXDATA(63 downto 8) => z56, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_AURORA_1_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_aurora_2.vhd,v 1.6 2005/07/23 00:03:51 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for AURORA I/O Standard 2 Byte Data -- /___/ /\ Filename : GT10_AURORA_2.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_AURORA_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_AURORA_2 is generic ( ALIGN_COMMA_WORD : integer := 1; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_CORRECT_USE : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32663068090105a628"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(1 downto 0); RXCHARISK : out std_logic_vector(1 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(15 downto 0); RXDISPERR : out std_logic_vector(1 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(1 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(1 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(1 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(1 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(1 downto 0); TXCHARDISPMODE : in std_logic_vector(1 downto 0); TXCHARDISPVAL : in std_logic_vector(1 downto 0); TXCHARISK : in std_logic_vector(1 downto 0); TXDATA : in std_logic_vector(15 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_AURORA_2; -- Architecture body -- architecture GT10_AURORA_2_V of GT10_AURORA_2 is signal OPEN6 : std_logic_vector(5 downto 0); signal OPEN48 : std_logic_vector(47 downto 0); signal z6 : std_logic_vector(5 downto 0) := "000000"; signal z48 : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 2, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00100011100", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => 2, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "25_20", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 2) => OPEN6, RXCHARISK(1 downto 0) => RXCHARISK, RXCHARISK(7 downto 2) => OPEN6, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(15 downto 0) => RXDATA, RXDATA(63 downto 16) => OPEN48, RXDISPERR(1 downto 0) => RXDISPERR, RXDISPERR(7 downto 2) => OPEN6, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 2) => OPEN6, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(1 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 2) => OPEN6, TXBUFERR => TXBUFERR, TXKERR(1 downto 0) => TXKERR, TXKERR(7 downto 2) => OPEN6, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(1 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 2) => OPEN6, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 2) => z6, TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 2) => z6, TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 2) => z6, TXCHARISK(1 downto 0) => TXCHARISK, TXCHARISK(7 downto 2) => z6, TXDATA(15 downto 0) => TXDATA, TXDATA(63 downto 16) => z48, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_AURORA_2_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_aurora_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for AURORA I/O Standard 4 Byte Data -- /___/ /\ Filename : GT10_AURORA_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_AURORA_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_AURORA_4 is generic ( ALIGN_COMMA_WORD : integer := 1; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_CORRECT_USE : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a628"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_AURORA_4; -- Architecture body -- architecture GT10_AURORA_4_V of GT10_AURORA_4 is signal OPEN4 : std_logic_vector(3 downto 0); signal OPEN32 : std_logic_vector(31 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 4, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00100011100", CLK_COR_SEQ_1_3 => "00100011100", CLK_COR_SEQ_1_4 => "00100011100", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => 4, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "25_40", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 4) => OPEN4, RXCHARISK(3 downto 0) => RXCHARISK, RXCHARISK(7 downto 4) => OPEN4, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(31 downto 0) => RXDATA, RXDATA(63 downto 32) => OPEN32, RXDISPERR(3 downto 0) => RXDISPERR, RXDISPERR(7 downto 4) => OPEN4, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 4) => OPEN4, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(3 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 4) => OPEN4, TXBUFERR => TXBUFERR, TXKERR(3 downto 0) => TXKERR, TXKERR(7 downto 4) => OPEN4, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(3 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 4) => OPEN4, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 4) => z4, TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 4) => z4, TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 4) => z4, TXCHARISK(3 downto 0) => TXCHARISK, TXCHARISK(7 downto 4) => z4, TXDATA(31 downto 0) => TXDATA, TXDATA(63 downto 32) => z32, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_AURORA_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_aurorax_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for AURORAX I/O Standard 4 Byte Data -- /___/ /\ Filename : GT10_AURORAX_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_AURORAX_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_AURORAX_4 is generic ( CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_64B66B_SV : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_CORRECT_USE : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SH_CNT_MAX : integer := 64; SH_INVALID_CNT_MAX : integer := 16; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_AURORAX_4; -- Architecture body -- architecture GT10_AURORAX_4_V of GT10_AURORAX_4 is signal OPEN4 : std_logic_vector(3 downto 0); signal OPEN32 : std_logic_vector(31 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 8, CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "10000011110", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => TRUE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => 8, CLK_CORRECT_USE => CLK_CORRECT_USE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "0_32", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SH_CNT_MAX => SH_CNT_MAX, SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 4) => OPEN4, RXCHARISK(3 downto 0) => RXCHARISK, RXCHARISK(7 downto 4) => OPEN4, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(31 downto 0) => RXDATA, RXDATA(63 downto 32) => OPEN32, RXDISPERR(3 downto 0) => RXDISPERR, RXDISPERR(7 downto 4) => OPEN4, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 4) => OPEN4, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(3 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 4) => OPEN4, TXBUFERR => TXBUFERR, TXKERR(3 downto 0) => TXKERR, TXKERR(7 downto 4) => OPEN4, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(3 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 4) => OPEN4, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 4) => z4, TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 4) => z4, TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 4) => z4, TXCHARISK(3 downto 0) => TXCHARISK, TXCHARISK(7 downto 4) => z4, TXDATA(31 downto 0) => TXDATA, TXDATA(63 downto 32) => z32, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_AURORAX_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_aurorax_8.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for AURORAX I/O Standard 8 Byte Data -- /___/ /\ Filename : GT10_AURORAX_8.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_AURORAX_8 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_AURORAX_8 is generic ( CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_64B66B_SV : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_CORRECT_USE : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SH_CNT_MAX : integer := 64; SH_INVALID_CNT_MAX : integer := 16; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(7 downto 0); RXCHARISK : out std_logic_vector(7 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(63 downto 0); RXDISPERR : out std_logic_vector(7 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(7 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(7 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(7 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(7 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(7 downto 0); TXCHARDISPMODE : in std_logic_vector(7 downto 0); TXCHARDISPVAL : in std_logic_vector(7 downto 0); TXCHARISK : in std_logic_vector(7 downto 0); TXDATA : in std_logic_vector(63 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_AURORAX_8; -- Architecture body -- architecture GT10_AURORAX_8_V of GT10_AURORAX_8 is begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 8, CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "10000011110", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => TRUE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => 8, CLK_CORRECT_USE => CLK_CORRECT_USE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "0_64", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SH_CNT_MAX => SH_CNT_MAX, SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP => RXRUNDISP, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP => TXRUNDISP, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_AURORAX_8_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_custom.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for CUSTOM I/O Standard -- /___/ /\ Filename : GT10_CUSTOM.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_CUSTOM ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_CUSTOM is generic ( ALIGN_COMMA_WORD : integer := 1; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 1; CHAN_BOND_64B66B_SV : boolean := FALSE; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 1; CLK_CORRECT_USE : boolean := TRUE; COMMA_10B_MASK : bit_vector := "0001111111"; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; MCOMMA_10B_VALUE : bit_vector := "1010000011"; MCOMMA_DETECT : boolean := TRUE; PCOMMA_10B_VALUE : bit_vector := "0101111100"; PCOMMA_DETECT : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED : string := "0_32"; PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SH_CNT_MAX : integer := 64; SH_INVALID_CNT_MAX : integer := 16; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(7 downto 0); RXCHARISK : out std_logic_vector(7 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(63 downto 0); RXDISPERR : out std_logic_vector(7 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(7 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(7 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(7 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(7 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(7 downto 0); TXCHARDISPMODE : in std_logic_vector(7 downto 0); TXCHARDISPVAL : in std_logic_vector(7 downto 0); TXCHARISK : in std_logic_vector(7 downto 0); TXDATA : in std_logic_vector(63 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_CUSTOM; -- Architecture body -- architecture GT10_CUSTOM_V of GT10_CUSTOM is begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1, CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2, CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3, CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4, CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1, CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2, CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3, CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4, CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1, CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2, CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3, CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4, CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1, CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2, CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3, CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4, CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => COMMA_10B_MASK, DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, MCOMMA_DETECT => MCOMMA_DETECT, PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, PCOMMA_DETECT => PCOMMA_DETECT, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => PMA_SPEED, PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SH_CNT_MAX => SH_CNT_MAX, SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP => RXRUNDISP, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP => TXRUNDISP, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_CUSTOM_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_infiniband_1.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for INFINIBAND I/O Standard 1 Byte Data -- /___/ /\ Filename : GT10_INFINIBAND_1.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_INFINIBAND_1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_INFINIBAND_1 is generic ( ALIGN_COMMA_WORD : integer := 2; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_LEN : integer := 2; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 2; CLK_CORRECT_USE : boolean := TRUE; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; LANE_ID : bit_vector := "00000000000"; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132263068090104a620"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(0 downto 0); RXCHARISK : out std_logic_vector(0 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(7 downto 0); RXDISPERR : out std_logic_vector(0 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(0 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(0 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(0 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(0 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(0 downto 0); TXCHARDISPMODE : in std_logic_vector(0 downto 0); TXCHARDISPVAL : in std_logic_vector(0 downto 0); TXCHARISK : in std_logic_vector(0 downto 0); TXDATA : in std_logic_vector(7 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_INFINIBAND_1; -- Architecture body -- architecture GT10_INFINIBAND_1_V of GT10_INFINIBAND_1 is signal OPEN7 : std_logic_vector(6 downto 0); signal OPEN56 : std_logic_vector(55 downto 0); signal z7 : std_logic_vector(6 downto 0) := "0000000"; signal z56 : std_logic_vector(55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => LANE_ID, CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => LANE_ID, CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => TRUE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "28_10", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 1) => OPEN7, RXCHARISK(0 downto 0) => RXCHARISK, RXCHARISK(7 downto 1) => OPEN7, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(7 downto 0) => RXDATA, RXDATA(63 downto 8) => OPEN56, RXDISPERR(0 downto 0) => RXDISPERR, RXDISPERR(7 downto 1) => OPEN7, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 1) => OPEN7, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(0 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 1) => OPEN7, TXBUFERR => TXBUFERR, TXKERR(0 downto 0) => TXKERR, TXKERR(7 downto 1) => OPEN7, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(0 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 1) => OPEN7, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 1) => z7, TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 1) => z7, TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 1) => z7, TXCHARISK(0 downto 0) => TXCHARISK, TXCHARISK(7 downto 1) => z7, TXDATA(7 downto 0) => TXDATA, TXDATA(63 downto 8) => z56, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_INFINIBAND_1_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_infiniband_2.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for INFINIBAND I/O Standard 2 Byte Data -- /___/ /\ Filename : GT10_INFINIBAND_2.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_INFINIBAND_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_INFINIBAND_2 is generic ( ALIGN_COMMA_WORD : integer := 2; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_LEN : integer := 2; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 2; CLK_CORRECT_USE : boolean := TRUE; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; LANE_ID : bit_vector := "00000000000"; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00fc0d300b0f32663068090105a620"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(1 downto 0); RXCHARISK : out std_logic_vector(1 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(15 downto 0); RXDISPERR : out std_logic_vector(1 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(1 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(1 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(1 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(1 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(1 downto 0); TXCHARDISPMODE : in std_logic_vector(1 downto 0); TXCHARDISPVAL : in std_logic_vector(1 downto 0); TXCHARISK : in std_logic_vector(1 downto 0); TXDATA : in std_logic_vector(15 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_INFINIBAND_2; -- Architecture body -- architecture GT10_INFINIBAND_2_V of GT10_INFINIBAND_2 is signal OPEN6 : std_logic_vector(5 downto 0); signal OPEN48 : std_logic_vector(47 downto 0); signal z6 : std_logic_vector(5 downto 0) := "000000"; signal z48 : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => LANE_ID, CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => LANE_ID, CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => TRUE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "28_20", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 2) => OPEN6, RXCHARISK(1 downto 0) => RXCHARISK, RXCHARISK(7 downto 2) => OPEN6, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(15 downto 0) => RXDATA, RXDATA(63 downto 16) => OPEN48, RXDISPERR(1 downto 0) => RXDISPERR, RXDISPERR(7 downto 2) => OPEN6, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 2) => OPEN6, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(1 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 2) => OPEN6, TXBUFERR => TXBUFERR, TXKERR(1 downto 0) => TXKERR, TXKERR(7 downto 2) => OPEN6, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(1 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 2) => OPEN6, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 2) => z6, TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 2) => z6, TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 2) => z6, TXCHARISK(1 downto 0) => TXCHARISK, TXCHARISK(7 downto 2) => z6, TXDATA(15 downto 0) => TXDATA, TXDATA(63 downto 16) => z48, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_INFINIBAND_2_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_infiniband_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for INFINIBAND I/O Standard 4 Byte Data -- /___/ /\ Filename : GT10_INFINIBAND_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:08 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_INFINIBAND_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_INFINIBAND_4 is generic ( ALIGN_COMMA_WORD : integer := 2; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_LEN : integer := 2; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 2; CLK_CORRECT_USE : boolean := TRUE; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; LANE_ID : bit_vector := "00000000000"; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a620"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_INFINIBAND_4; -- Architecture body -- architecture GT10_INFINIBAND_4_V of GT10_INFINIBAND_4 is signal OPEN4 : std_logic_vector(3 downto 0); signal OPEN32 : std_logic_vector(31 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => LANE_ID, CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => LANE_ID, CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => TRUE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "28_40", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 4) => OPEN4, RXCHARISK(3 downto 0) => RXCHARISK, RXCHARISK(7 downto 4) => OPEN4, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(31 downto 0) => RXDATA, RXDATA(63 downto 32) => OPEN32, RXDISPERR(3 downto 0) => RXDISPERR, RXDISPERR(7 downto 4) => OPEN4, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 4) => OPEN4, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(3 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 4) => OPEN4, TXBUFERR => TXBUFERR, TXKERR(3 downto 0) => TXKERR, TXKERR(7 downto 4) => OPEN4, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(3 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 4) => OPEN4, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 4) => z4, TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 4) => z4, TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 4) => z4, TXCHARISK(3 downto 0) => TXCHARISK, TXCHARISK(7 downto 4) => z4, TXDATA(31 downto 0) => TXDATA, TXDATA(63 downto 32) => z32, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_INFINIBAND_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_oc192_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for OC192 I/O Standard 4 Byte Data -- /___/ /\ Filename : GT10_OC192_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_OC192_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_OC192_4 is generic ( ALIGN_COMMA_WORD : integer := 1; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; MCOMMA_10B_VALUE : bit_vector := "0010101010"; MCOMMA_DETECT : boolean := TRUE; PCOMMA_10B_VALUE : bit_vector := "0010101010"; PCOMMA_DETECT : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504c00208c9050d0068"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLKBSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_OC192_4; -- Architecture body -- architecture GT10_OC192_4_V of GT10_OC192_4 is signal z1 : std_ulogic := '0'; signal OPEN4 : std_logic_vector(3 downto 0); signal OPEN32 : std_logic_vector(31 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, COMMA_10B_MASK => "0011111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, MCOMMA_DETECT => MCOMMA_DETECT, PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, PCOMMA_DETECT => PCOMMA_DETECT, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "15_32", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( REFCLK => z1, REFCLK2 => z1, REFCLKSEL => z1, CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 4) => OPEN4, RXCHARISK(3 downto 0) => RXCHARISK, RXCHARISK(7 downto 4) => OPEN4, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(31 downto 0) => RXDATA, RXDATA(63 downto 32) => OPEN32, RXDISPERR(3 downto 0) => RXDISPERR, RXDISPERR(7 downto 4) => OPEN4, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 4) => OPEN4, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(3 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 4) => OPEN4, TXBUFERR => TXBUFERR, TXKERR(3 downto 0) => TXKERR, TXKERR(7 downto 4) => OPEN4, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(3 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 4) => OPEN4, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLKBSEL => REFCLKBSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 4) => z4, TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 4) => z4, TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 4) => z4, TXCHARISK(3 downto 0) => TXCHARISK, TXCHARISK(7 downto 4) => z4, TXDATA(31 downto 0) => TXDATA, TXDATA(63 downto 32) => z32, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_OC192_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_oc192_8.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for OC192 I/O Standard 8 Byte Data -- /___/ /\ Filename : GT10_OC192_8.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_OC192_8 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_OC192_8 is generic ( ALIGN_COMMA_WORD : integer := 1; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; MCOMMA_10B_VALUE : bit_vector := "0010101010"; MCOMMA_DETECT : boolean := TRUE; PCOMMA_10B_VALUE : bit_vector := "0010101010"; PCOMMA_DETECT : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504c00208c9050d0068"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(7 downto 0); RXCHARISK : out std_logic_vector(7 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(63 downto 0); RXDISPERR : out std_logic_vector(7 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(7 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(7 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(7 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(7 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLKBSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(7 downto 0); TXCHARDISPMODE : in std_logic_vector(7 downto 0); TXCHARDISPVAL : in std_logic_vector(7 downto 0); TXCHARISK : in std_logic_vector(7 downto 0); TXDATA : in std_logic_vector(63 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_OC192_8; -- Architecture body -- architecture GT10_OC192_8_V of GT10_OC192_8 is signal z1 : std_ulogic := '0'; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, COMMA_10B_MASK => "0011111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, MCOMMA_DETECT => MCOMMA_DETECT, PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, PCOMMA_DETECT => PCOMMA_DETECT, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "15_64", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( REFCLK => z1, REFCLK2 => z1, REFCLKSEL => z1, CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP => RXRUNDISP, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP => TXRUNDISP, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLKBSEL => REFCLKBSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_OC192_8_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_oc48_1.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for OC48 I/O Standard 1 Byte Data -- /___/ /\ Filename : GT10_OC48_1.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_OC48_1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_OC48_1 is generic ( ALIGN_COMMA_WORD : integer := 1; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; MCOMMA_10B_VALUE : bit_vector := "0010101010"; MCOMMA_DETECT : boolean := TRUE; PCOMMA_10B_VALUE : bit_vector := "0010101010"; PCOMMA_DETECT : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd500b01300830680901040820"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(0 downto 0); RXCHARISK : out std_logic_vector(0 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(7 downto 0); RXDISPERR : out std_logic_vector(0 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(0 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(0 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(0 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(0 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(0 downto 0); TXCHARDISPMODE : in std_logic_vector(0 downto 0); TXCHARDISPVAL : in std_logic_vector(0 downto 0); TXCHARISK : in std_logic_vector(0 downto 0); TXDATA : in std_logic_vector(7 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_OC48_1; -- Architecture body -- architecture GT10_OC48_1_V of GT10_OC48_1 is signal OPEN7 : std_logic_vector(6 downto 0); signal OPEN56 : std_logic_vector(55 downto 0); signal z7 : std_logic_vector(6 downto 0) := "0000000"; signal z56 : std_logic_vector(55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, COMMA_10B_MASK => "0011111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, MCOMMA_DETECT => MCOMMA_DETECT, PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, PCOMMA_DETECT => PCOMMA_DETECT, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "31_8", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 1) => OPEN7, RXCHARISK(0 downto 0) => RXCHARISK, RXCHARISK(7 downto 1) => OPEN7, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(7 downto 0) => RXDATA, RXDATA(63 downto 8) => OPEN56, RXDISPERR(0 downto 0) => RXDISPERR, RXDISPERR(7 downto 1) => OPEN7, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 1) => OPEN7, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(0 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 1) => OPEN7, TXBUFERR => TXBUFERR, TXKERR(0 downto 0) => TXKERR, TXKERR(7 downto 1) => OPEN7, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(0 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 1) => OPEN7, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 1) => z7, TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 1) => z7, TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 1) => z7, TXCHARISK(0 downto 0) => TXCHARISK, TXCHARISK(7 downto 1) => z7, TXDATA(7 downto 0) => TXDATA, TXDATA(63 downto 8) => z56, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_OC48_1_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_oc48_2.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for OC48 I/O Standard 2 Byte Data -- /___/ /\ Filename : GT10_OC48_2.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_OC48_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_OC48_2 is generic ( ALIGN_COMMA_WORD : integer := 1; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; MCOMMA_10B_VALUE : bit_vector := "0010101010"; MCOMMA_DETECT : boolean := TRUE; PCOMMA_10B_VALUE : bit_vector := "0010101010"; PCOMMA_DETECT : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00fc0d300b0f304830680901050820"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(1 downto 0); RXCHARISK : out std_logic_vector(1 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(15 downto 0); RXDISPERR : out std_logic_vector(1 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(1 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(1 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(1 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(1 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(1 downto 0); TXCHARDISPMODE : in std_logic_vector(1 downto 0); TXCHARDISPVAL : in std_logic_vector(1 downto 0); TXCHARISK : in std_logic_vector(1 downto 0); TXDATA : in std_logic_vector(15 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_OC48_2; -- Architecture body -- architecture GT10_OC48_2_V of GT10_OC48_2 is signal OPEN6 : std_logic_vector(5 downto 0); signal OPEN48 : std_logic_vector(47 downto 0); signal z6 : std_logic_vector(5 downto 0) := "000000"; signal z48 : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, COMMA_10B_MASK => "0011111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, MCOMMA_DETECT => MCOMMA_DETECT, PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, PCOMMA_DETECT => PCOMMA_DETECT, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "31_16", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 2) => OPEN6, RXCHARISK(1 downto 0) => RXCHARISK, RXCHARISK(7 downto 2) => OPEN6, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(15 downto 0) => RXDATA, RXDATA(63 downto 16) => OPEN48, RXDISPERR(1 downto 0) => RXDISPERR, RXDISPERR(7 downto 2) => OPEN6, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 2) => OPEN6, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(1 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 2) => OPEN6, TXBUFERR => TXBUFERR, TXKERR(1 downto 0) => TXKERR, TXKERR(7 downto 2) => OPEN6, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(1 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 2) => OPEN6, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 2) => z6, TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 2) => z6, TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 2) => z6, TXCHARISK(1 downto 0) => TXCHARISK, TXCHARISK(7 downto 2) => z6, TXDATA(15 downto 0) => TXDATA, TXDATA(63 downto 16) => z48, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_OC48_2_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_oc48_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for OC48 I/O Standard 4 Byte Data -- /___/ /\ Filename : GT10_OC48_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_OC48_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_OC48_4 is generic ( ALIGN_COMMA_WORD : integer := 1; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; MCOMMA_10B_VALUE : bit_vector := "0010101010"; MCOMMA_DETECT : boolean := TRUE; PCOMMA_10B_VALUE : bit_vector := "0010101010"; PCOMMA_DETECT : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd500b01304830680901050820"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_OC48_4; -- Architecture body -- architecture GT10_OC48_4_V of GT10_OC48_4 is signal OPEN4 : std_logic_vector(3 downto 0); signal OPEN32 : std_logic_vector(31 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, COMMA_10B_MASK => "0011111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, MCOMMA_DETECT => MCOMMA_DETECT, PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, PCOMMA_DETECT => PCOMMA_DETECT, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "31_32", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 4) => OPEN4, RXCHARISK(3 downto 0) => RXCHARISK, RXCHARISK(7 downto 4) => OPEN4, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(31 downto 0) => RXDATA, RXDATA(63 downto 32) => OPEN32, RXDISPERR(3 downto 0) => RXDISPERR, RXDISPERR(7 downto 4) => OPEN4, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 4) => OPEN4, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(3 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 4) => OPEN4, TXBUFERR => TXBUFERR, TXKERR(3 downto 0) => TXKERR, TXKERR(7 downto 4) => OPEN4, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(3 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 4) => OPEN4, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 4) => z4, TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 4) => z4, TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 4) => z4, TXCHARISK(3 downto 0) => TXCHARISK, TXCHARISK(7 downto 4) => z4, TXDATA(31 downto 0) => TXDATA, TXDATA(63 downto 32) => z32, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_OC48_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_pci_express_1.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for PCI_EXPRESS I/O Standard 1 Byte Data -- /___/ /\ Filename : GT10_PCI_EXPRESS_1.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_PCI_EXPRESS_1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_PCI_EXPRESS_1 is generic ( ALIGN_COMMA_WORD : integer := 2; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 2; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 2; CLK_CORRECT_USE : boolean := TRUE; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132263068090104a620"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(0 downto 0); RXCHARISK : out std_logic_vector(0 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(7 downto 0); RXDISPERR : out std_logic_vector(0 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(0 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(0 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(0 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(0 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(0 downto 0); TXCHARDISPMODE : in std_logic_vector(0 downto 0); TXCHARDISPVAL : in std_logic_vector(0 downto 0); TXCHARISK : in std_logic_vector(0 downto 0); TXDATA : in std_logic_vector(7 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_PCI_EXPRESS_1; -- Architecture body -- architecture GT10_PCI_EXPRESS_1_V of GT10_PCI_EXPRESS_1 is signal OPEN7 : std_logic_vector(6 downto 0); signal OPEN56 : std_logic_vector(55 downto 0); signal z7 : std_logic_vector(6 downto 0) := "0000000"; signal z56 : std_logic_vector(55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "28_10", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 1) => OPEN7, RXCHARISK(0 downto 0) => RXCHARISK, RXCHARISK(7 downto 1) => OPEN7, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(7 downto 0) => RXDATA, RXDATA(63 downto 8) => OPEN56, RXDISPERR(0 downto 0) => RXDISPERR, RXDISPERR(7 downto 1) => OPEN7, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 1) => OPEN7, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(0 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 1) => OPEN7, TXBUFERR => TXBUFERR, TXKERR(0 downto 0) => TXKERR, TXKERR(7 downto 1) => OPEN7, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(0 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 1) => OPEN7, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 1) => z7, TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 1) => z7, TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 1) => z7, TXCHARISK(0 downto 0) => TXCHARISK, TXCHARISK(7 downto 1) => z7, TXDATA(7 downto 0) => TXDATA, TXDATA(63 downto 8) => z56, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_PCI_EXPRESS_1_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_pci_express_2.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for PCI_EXPRESS I/O Standard 2 Byte Data -- /___/ /\ Filename : GT10_PCI_EXPRESS_2.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_PCI_EXPRESS_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_PCI_EXPRESS_2 is generic ( ALIGN_COMMA_WORD : integer := 2; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 2; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 2; CLK_CORRECT_USE : boolean := TRUE; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00fc0d300b0f32663068090105a620"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(1 downto 0); RXCHARISK : out std_logic_vector(1 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(15 downto 0); RXDISPERR : out std_logic_vector(1 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(1 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(1 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(1 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(1 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(1 downto 0); TXCHARDISPMODE : in std_logic_vector(1 downto 0); TXCHARDISPVAL : in std_logic_vector(1 downto 0); TXCHARISK : in std_logic_vector(1 downto 0); TXDATA : in std_logic_vector(15 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_PCI_EXPRESS_2; -- Architecture body -- architecture GT10_PCI_EXPRESS_2_V of GT10_PCI_EXPRESS_2 is signal OPEN6 : std_logic_vector(5 downto 0); signal OPEN48 : std_logic_vector(47 downto 0); signal z6 : std_logic_vector(5 downto 0) := "000000"; signal z48 : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "28_20", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 2) => OPEN6, RXCHARISK(1 downto 0) => RXCHARISK, RXCHARISK(7 downto 2) => OPEN6, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(15 downto 0) => RXDATA, RXDATA(63 downto 16) => OPEN48, RXDISPERR(1 downto 0) => RXDISPERR, RXDISPERR(7 downto 2) => OPEN6, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 2) => OPEN6, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(1 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 2) => OPEN6, TXBUFERR => TXBUFERR, TXKERR(1 downto 0) => TXKERR, TXKERR(7 downto 2) => OPEN6, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(1 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 2) => OPEN6, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 2) => z6, TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 2) => z6, TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 2) => z6, TXCHARISK(1 downto 0) => TXCHARISK, TXCHARISK(7 downto 2) => z6, TXDATA(15 downto 0) => TXDATA, TXDATA(63 downto 16) => z48, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_PCI_EXPRESS_2_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_pci_express_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for PCI_EXPRESS I/O Standard 4 Byte Data -- /___/ /\ Filename : GT10_PCI_EXPRESS_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_PCI_EXPRESS_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_PCI_EXPRESS_4 is generic ( ALIGN_COMMA_WORD : integer := 2; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 2; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 2; CLK_CORRECT_USE : boolean := TRUE; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a620"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_PCI_EXPRESS_4; -- Architecture body -- architecture GT10_PCI_EXPRESS_4_V of GT10_PCI_EXPRESS_4 is signal OPEN4 : std_logic_vector(3 downto 0); signal OPEN32 : std_logic_vector(31 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "28_40", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 4) => OPEN4, RXCHARISK(3 downto 0) => RXCHARISK, RXCHARISK(7 downto 4) => OPEN4, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(31 downto 0) => RXDATA, RXDATA(63 downto 32) => OPEN32, RXDISPERR(3 downto 0) => RXDISPERR, RXDISPERR(7 downto 4) => OPEN4, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 4) => OPEN4, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(3 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 4) => OPEN4, TXBUFERR => TXBUFERR, TXKERR(3 downto 0) => TXKERR, TXKERR(7 downto 4) => OPEN4, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(3 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 4) => OPEN4, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 4) => z4, TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 4) => z4, TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 4) => z4, TXCHARISK(3 downto 0) => TXCHARISK, TXCHARISK(7 downto 4) => z4, TXDATA(31 downto 0) => TXDATA, TXDATA(63 downto 32) => z32, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_PCI_EXPRESS_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10.vhd,v 1.8 2006/03/16 00:57:41 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for High-Speed I/O for Simulation Model -- /___/ /\ Filename : GT10.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10 is generic ( in_delay : time := 0 ps; out_delay : VitalDelayType01 := (100 ps, 100 ps); ALIGN_COMMA_WORD : integer := 1; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 1; CHAN_BOND_64B66B_SV : boolean := FALSE; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 1; CLK_CORRECT_USE : boolean := TRUE; COMMA_10B_MASK : bit_vector := "0001111111"; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; MCOMMA_10B_VALUE : bit_vector := "1010000011"; MCOMMA_DETECT : boolean := TRUE; PCOMMA_10B_VALUE : bit_vector := "0101111100"; PCOMMA_DETECT : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED : string := "0_32"; PMA_SPEED_HEX : bit_vector := X"00ffcd24ca1504d00208c9050d4068"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SH_CNT_MAX : integer := 64; SH_INVALID_CNT_MAX : integer := 16; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(7 downto 0); RXCHARISK : out std_logic_vector(7 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(63 downto 0); RXDISPERR : out std_logic_vector(7 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(7 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(7 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(7 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(7 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(7 downto 0); TXCHARDISPMODE : in std_logic_vector(7 downto 0); TXCHARDISPVAL : in std_logic_vector(7 downto 0); TXCHARISK : in std_logic_vector(7 downto 0); TXDATA : in std_logic_vector(63 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10; -- Architecture body -- architecture GT10_V of GT10 is component GT10_SWIFT_BUS port ( CHBONDDONE : out STD_ULOGIC; CHBONDO : out STD_LOGIC_VECTOR(4 downto 0); PMARXLOCK : out STD_ULOGIC; RXBUFSTATUS : out STD_LOGIC_VECTOR(1 downto 0); RXCHARISCOMMA : out STD_LOGIC_VECTOR(7 downto 0); RXCHARISK : out STD_LOGIC_VECTOR(7 downto 0); RXCLKCORCNT : out STD_LOGIC_VECTOR(2 downto 0); RXCOMMADET : out STD_ULOGIC; RXDATA : out STD_LOGIC_VECTOR(63 downto 0); RXDISPERR : out STD_LOGIC_VECTOR(7 downto 0); RXLOSSOFSYNC : out STD_LOGIC_VECTOR(1 downto 0); RXNOTINTABLE : out STD_LOGIC_VECTOR(7 downto 0); RXREALIGN : out STD_ULOGIC; RXRECCLK : out STD_ULOGIC; RXRUNDISP : out STD_LOGIC_VECTOR(7 downto 0); TXBUFERR : out STD_ULOGIC; TXKERR : out STD_LOGIC_VECTOR(7 downto 0); TXN : out STD_ULOGIC; TXOUTCLK : out STD_ULOGIC; TXP : out STD_ULOGIC; TXRUNDISP : out STD_LOGIC_VECTOR(7 downto 0); BREFCLKNIN : in STD_ULOGIC; BREFCLKPIN : in STD_ULOGIC; CHBONDI : in STD_LOGIC_VECTOR(4 downto 0); ENCHANSYNC : in STD_ULOGIC; ENMCOMMAALIGN : in STD_ULOGIC; ENPCOMMAALIGN : in STD_ULOGIC; LOOPBACK : in STD_LOGIC_VECTOR(1 downto 0); PMAINIT : in STD_ULOGIC; PMAREGADDR : in STD_LOGIC_VECTOR(5 downto 0); PMAREGDATAIN : in STD_LOGIC_VECTOR(7 downto 0); PMAREGRW : in STD_ULOGIC; PMAREGSTROBE : in STD_ULOGIC; PMARXLOCKSEL : in STD_LOGIC_VECTOR(1 downto 0); POWERDOWN : in STD_ULOGIC; REFCLK : in STD_ULOGIC; REFCLK2 : in STD_ULOGIC; REFCLKBSEL : in STD_ULOGIC; REFCLKSEL : in STD_ULOGIC; RXBLOCKSYNC64B66BUSE : in STD_ULOGIC; RXCOMMADETUSE : in STD_ULOGIC; RXDATAWIDTH : in STD_LOGIC_VECTOR(1 downto 0); RXDEC64B66BUSE : in STD_ULOGIC; RXDEC8B10BUSE : in STD_ULOGIC; RXDESCRAM64B66BUSE : in STD_ULOGIC; RXIGNOREBTF : in STD_ULOGIC; RXINTDATAWIDTH : in STD_LOGIC_VECTOR(1 downto 0); RXN : in STD_ULOGIC; RXP : in STD_ULOGIC; RXPOLARITY : in STD_ULOGIC; RXRESET : in STD_ULOGIC; RXSLIDE : in STD_ULOGIC; RXUSRCLK : in STD_ULOGIC; RXUSRCLK2 : in STD_ULOGIC; TXBYPASS8B10B : in STD_LOGIC_VECTOR(7 downto 0); TXCHARDISPMODE : in STD_LOGIC_VECTOR(7 downto 0); TXCHARDISPVAL : in STD_LOGIC_VECTOR(7 downto 0); TXCHARISK : in STD_LOGIC_VECTOR(7 downto 0); TXDATA : in STD_LOGIC_VECTOR(63 downto 0); TXDATAWIDTH : in STD_LOGIC_VECTOR(1 downto 0); TXENC64B66BUSE : in STD_ULOGIC; TXENC8B10BUSE : in STD_ULOGIC; TXGEARBOX64B66BUSE : in STD_ULOGIC; TXINHIBIT : in STD_ULOGIC; TXINTDATAWIDTH : in STD_LOGIC_VECTOR(1 downto 0); TXPOLARITY : in STD_ULOGIC; TXRESET : in STD_ULOGIC; TXSCRAM64B66BUSE : in STD_ULOGIC; TXUSRCLK : in STD_ULOGIC; TXUSRCLK2 : in STD_ULOGIC; ALIGN_COMMA_WORD : in STD_LOGIC_VECTOR(1 downto 0); CHAN_BOND_LIMIT : in STD_LOGIC_VECTOR(5 downto 0); CHAN_BOND_MODE : in STD_LOGIC_VECTOR(1 downto 0); CHAN_BOND_ONE_SHOT : in STD_ULOGIC; CHAN_BOND_SEQ_1_1 : in STD_LOGIC_VECTOR(10 downto 0); CHAN_BOND_SEQ_1_2 : in STD_LOGIC_VECTOR(10 downto 0); CHAN_BOND_SEQ_1_3 : in STD_LOGIC_VECTOR(10 downto 0); CHAN_BOND_SEQ_1_4 : in STD_LOGIC_VECTOR(10 downto 0); CHAN_BOND_SEQ_1_MASK : in STD_LOGIC_VECTOR(3 downto 0); CHAN_BOND_SEQ_2_1 : in STD_LOGIC_VECTOR(10 downto 0); CHAN_BOND_SEQ_2_2 : in STD_LOGIC_VECTOR(10 downto 0); CHAN_BOND_SEQ_2_3 : in STD_LOGIC_VECTOR(10 downto 0); CHAN_BOND_SEQ_2_4 : in STD_LOGIC_VECTOR(10 downto 0); CHAN_BOND_SEQ_2_MASK : in STD_LOGIC_VECTOR(3 downto 0); CHAN_BOND_SEQ_2_USE : in STD_ULOGIC; CHAN_BOND_SEQ_LEN : in STD_LOGIC_VECTOR(2 downto 0); CHAN_BOND_64B66B_SV : in std_ulogic; CLK_COR_8B10B_DE : in STD_ULOGIC; CLK_COR_MAX_LAT : in STD_LOGIC_VECTOR(5 downto 0); CLK_COR_MIN_LAT : in STD_LOGIC_VECTOR(5 downto 0); CLK_COR_SEQ_1_1 : in STD_LOGIC_VECTOR(10 downto 0); CLK_COR_SEQ_1_2 : in STD_LOGIC_VECTOR(10 downto 0); CLK_COR_SEQ_1_3 : in STD_LOGIC_VECTOR(10 downto 0); CLK_COR_SEQ_1_4 : in STD_LOGIC_VECTOR(10 downto 0); CLK_COR_SEQ_1_MASK : in STD_LOGIC_VECTOR(3 downto 0); CLK_COR_SEQ_2_1 : in STD_LOGIC_VECTOR(10 downto 0); CLK_COR_SEQ_2_2 : in STD_LOGIC_VECTOR(10 downto 0); CLK_COR_SEQ_2_3 : in STD_LOGIC_VECTOR(10 downto 0); CLK_COR_SEQ_2_4 : in STD_LOGIC_VECTOR(10 downto 0); CLK_COR_SEQ_2_MASK : in STD_LOGIC_VECTOR(3 downto 0); CLK_COR_SEQ_2_USE : in STD_ULOGIC; CLK_COR_SEQ_DROP : in STD_ULOGIC; CLK_COR_SEQ_LEN : in STD_LOGIC_VECTOR(2 downto 0); CLK_CORRECT_USE : in STD_ULOGIC; COMMA_10B_MASK : in STD_LOGIC_VECTOR(9 downto 0); DEC_MCOMMA_DETECT : in STD_ULOGIC; DEC_PCOMMA_DETECT : in STD_ULOGIC; DEC_VALID_COMMA_ONLY : in STD_ULOGIC; MCOMMA_10B_VALUE : in STD_LOGIC_VECTOR(9 downto 0); MCOMMA_DETECT : in STD_ULOGIC; PCOMMA_10B_VALUE : in STD_LOGIC_VECTOR(9 downto 0); PCOMMA_DETECT : in STD_ULOGIC; PMA_SPEED : in STD_LOGIC_VECTOR(119 downto 0); PMA_PWR_CNTRL : in STD_LOGIC_VECTOR(7 downto 0); RX_BUFFER_USE : in STD_ULOGIC; RX_LOS_INVALID_INCR : in STD_LOGIC_VECTOR(7 downto 0); RX_LOS_THRESHOLD : in STD_LOGIC_VECTOR(7 downto 0); RX_LOSS_OF_SYNC_FSM : in STD_ULOGIC; SH_CNT_MAX : in STD_LOGIC_VECTOR(7 downto 0); SH_INVALID_CNT_MAX : in STD_LOGIC_VECTOR(7 downto 0); TX_BUFFER_USE : in STD_ULOGIC; GSR : in STD_ULOGIC ); end component; -- Attribute-to-Cell mapping signals signal ALIGN_COMMA_WORD_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_LIMIT_BINARY : std_logic_vector(5 downto 0); signal CHAN_BOND_MODE_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_ONE_SHOT_BINARY : std_ulogic; signal CHAN_BOND_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1); signal CHAN_BOND_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2); signal CHAN_BOND_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3); signal CHAN_BOND_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4); signal CHAN_BOND_SEQ_1_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_MASK); signal CHAN_BOND_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1); signal CHAN_BOND_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2); signal CHAN_BOND_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3); signal CHAN_BOND_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4); signal CHAN_BOND_SEQ_2_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_MASK); signal CHAN_BOND_SEQ_2_USE_BINARY : std_ulogic; signal CHAN_BOND_SEQ_LEN_BINARY : std_logic_vector(2 downto 0); signal CHAN_BOND_64B66B_SV_BINARY : std_ulogic; signal CLK_COR_8B10B_DE_BINARY : std_ulogic; signal CLK_COR_MAX_LAT_BINARY : std_logic_vector(5 downto 0); signal CLK_COR_MIN_LAT_BINARY : std_logic_vector(5 downto 0); signal CLK_COR_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1); signal CLK_COR_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2); signal CLK_COR_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3); signal CLK_COR_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4); signal CLK_COR_SEQ_1_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_MASK); signal CLK_COR_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1); signal CLK_COR_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2); signal CLK_COR_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3); signal CLK_COR_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4); signal CLK_COR_SEQ_2_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_MASK); signal CLK_COR_SEQ_2_USE_BINARY : std_ulogic; signal CLK_COR_SEQ_DROP_BINARY : std_ulogic; signal CLK_COR_SEQ_LEN_BINARY : std_logic_vector(2 downto 0); signal CLK_CORRECT_USE_BINARY : std_ulogic; signal COMMA_10B_MASK_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_MASK); signal DEC_MCOMMA_DETECT_BINARY : std_ulogic; signal DEC_PCOMMA_DETECT_BINARY : std_ulogic; signal DEC_VALID_COMMA_ONLY_BINARY : std_ulogic; signal MCOMMA_10B_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE); signal MCOMMA_DETECT_BINARY : std_ulogic; signal PCOMMA_10B_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE); signal PCOMMA_DETECT_BINARY : std_ulogic; signal PMA_PWR_CNTRL_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMA_PWR_CNTRL); signal PMA_SPEED_BINARY : std_logic_vector(119 downto 0); signal RX_BUFFER_USE_BINARY : std_ulogic; signal RX_LOS_INVALID_INCR_BINARY : std_logic_vector(7 downto 0); signal RX_LOS_THRESHOLD_BINARY : std_logic_vector(7 downto 0); signal RX_LOSS_OF_SYNC_FSM_BINARY : std_ulogic; signal SH_CNT_MAX_BINARY : std_logic_vector(7 downto 0); signal SH_INVALID_CNT_MAX_BINARY : std_logic_vector(7 downto 0); signal TX_BUFFER_USE_BINARY : std_ulogic; -- Input/Output Pin signals signal CHBONDDONE_out : std_ulogic; signal CHBONDO_out : std_logic_vector(4 downto 0); signal PMARXLOCK_out : std_ulogic; signal RXBUFSTATUS_out : std_logic_vector(1 downto 0); signal RXCHARISCOMMA_out : std_logic_vector(7 downto 0); signal RXCHARISK_out : std_logic_vector(7 downto 0); signal RXCLKCORCNT_out : std_logic_vector(2 downto 0); signal RXCOMMADET_out : std_ulogic; signal RXDATA_out : std_logic_vector(63 downto 0); signal RXDISPERR_out : std_logic_vector(7 downto 0); signal RXLOSSOFSYNC_out : std_logic_vector(1 downto 0); signal RXNOTINTABLE_out : std_logic_vector(7 downto 0); signal RXREALIGN_out : std_ulogic; signal RXRECCLK_out : std_ulogic; signal RXRUNDISP_out : std_logic_vector(7 downto 0); signal TXBUFERR_out : std_ulogic; signal TXKERR_out : std_logic_vector(7 downto 0); signal TXN_out : std_ulogic; signal TXOUTCLK_out : std_ulogic; signal TXP_out : std_ulogic; signal TXRUNDISP_out : std_logic_vector(7 downto 0); signal BREFCLKNIN_ipd : std_ulogic; signal BREFCLKPIN_ipd : std_ulogic; signal CHBONDI_ipd : std_logic_vector(4 downto 0); signal ENCHANSYNC_ipd : std_ulogic; signal ENMCOMMAALIGN_ipd : std_ulogic; signal ENPCOMMAALIGN_ipd : std_ulogic; signal LOOPBACK_ipd : std_logic_vector(1 downto 0); signal PMAINIT_ipd : std_ulogic; signal PMAREGADDR_ipd : std_logic_vector(5 downto 0); signal PMAREGDATAIN_ipd : std_logic_vector(7 downto 0); signal PMAREGRW_ipd : std_ulogic; signal PMAREGSTROBE_ipd : std_ulogic; signal PMARXLOCKSEL_ipd : std_logic_vector(1 downto 0); signal POWERDOWN_ipd : std_ulogic; signal REFCLK_ipd : std_ulogic; signal REFCLK2_ipd : std_ulogic; signal REFCLKBSEL_ipd : std_ulogic; signal REFCLKSEL_ipd : std_ulogic; signal RXBLOCKSYNC64B66BUSE_ipd : std_ulogic; signal RXCOMMADETUSE_ipd : std_ulogic; signal RXDATAWIDTH_ipd : std_logic_vector(1 downto 0); signal RXDEC64B66BUSE_ipd : std_ulogic; signal RXDEC8B10BUSE_ipd : std_ulogic; signal RXDESCRAM64B66BUSE_ipd : std_ulogic; signal RXIGNOREBTF_ipd : std_ulogic; signal RXINTDATAWIDTH_ipd : std_logic_vector(1 downto 0); signal RXN_ipd : std_ulogic; signal RXP_ipd : std_ulogic; signal RXPOLARITY_ipd : std_ulogic; signal RXRESET_ipd : std_ulogic; signal RXSLIDE_ipd : std_ulogic; signal RXUSRCLK_ipd : std_ulogic; signal RXUSRCLK2_ipd : std_ulogic; signal TXBYPASS8B10B_ipd : std_logic_vector(7 downto 0); signal TXCHARDISPMODE_ipd : std_logic_vector(7 downto 0); signal TXCHARDISPVAL_ipd : std_logic_vector(7 downto 0); signal TXCHARISK_ipd : std_logic_vector(7 downto 0); signal TXDATA_ipd : std_logic_vector(63 downto 0); signal TXDATAWIDTH_ipd : std_logic_vector(1 downto 0); signal TXENC64B66BUSE_ipd : std_ulogic; signal TXENC8B10BUSE_ipd : std_ulogic; signal TXGEARBOX64B66BUSE_ipd : std_ulogic; signal TXINHIBIT_ipd : std_ulogic; signal TXINTDATAWIDTH_ipd : std_logic_vector(1 downto 0); signal TXPOLARITY_ipd : std_ulogic; signal TXRESET_ipd : std_ulogic; signal TXSCRAM64B66BUSE_ipd : std_ulogic; signal TXUSRCLK_ipd : std_ulogic; signal TXUSRCLK2_ipd : std_ulogic; begin BREFCLKNIN_ipd <= BREFCLKNIN after in_delay; BREFCLKPIN_ipd <= BREFCLKPIN after in_delay; CHBONDI_ipd <= CHBONDI after in_delay; ENCHANSYNC_ipd <= ENCHANSYNC after in_delay; ENMCOMMAALIGN_ipd <= ENMCOMMAALIGN after in_delay; ENPCOMMAALIGN_ipd <= ENPCOMMAALIGN after in_delay; LOOPBACK_ipd <= LOOPBACK after in_delay; PMAINIT_ipd <= PMAINIT after in_delay; PMAREGADDR_ipd <= PMAREGADDR after in_delay; PMAREGDATAIN_ipd <= PMAREGDATAIN after in_delay; PMAREGRW_ipd <= PMAREGRW after in_delay; PMAREGSTROBE_ipd <= PMAREGSTROBE after in_delay; PMARXLOCKSEL_ipd <= PMARXLOCKSEL after in_delay; POWERDOWN_ipd <= POWERDOWN after in_delay; REFCLK_ipd <= REFCLK after in_delay; REFCLK2_ipd <= REFCLK2 after in_delay; REFCLKBSEL_ipd <= REFCLKBSEL after in_delay; REFCLKSEL_ipd <= REFCLKSEL after in_delay; RXBLOCKSYNC64B66BUSE_ipd <= RXBLOCKSYNC64B66BUSE after in_delay; RXCOMMADETUSE_ipd <= RXCOMMADETUSE after in_delay; RXDATAWIDTH_ipd <= RXDATAWIDTH after in_delay; RXDEC64B66BUSE_ipd <= RXDEC64B66BUSE after in_delay; RXDEC8B10BUSE_ipd <= RXDEC8B10BUSE after in_delay; RXDESCRAM64B66BUSE_ipd <= RXDESCRAM64B66BUSE after in_delay; RXIGNOREBTF_ipd <= RXIGNOREBTF after in_delay; RXINTDATAWIDTH_ipd <= RXINTDATAWIDTH after in_delay; RXN_ipd <= RXN after in_delay; RXP_ipd <= RXP after in_delay; RXPOLARITY_ipd <= RXPOLARITY after in_delay; RXRESET_ipd <= RXRESET after in_delay; RXSLIDE_ipd <= RXSLIDE after in_delay; RXUSRCLK_ipd <= RXUSRCLK after in_delay; RXUSRCLK2_ipd <= RXUSRCLK2 after in_delay; TXBYPASS8B10B_ipd <= TXBYPASS8B10B after in_delay; TXCHARDISPMODE_ipd <= TXCHARDISPMODE after in_delay; TXCHARDISPVAL_ipd <= TXCHARDISPVAL after in_delay; TXCHARISK_ipd <= TXCHARISK after in_delay; TXDATA_ipd <= TXDATA after in_delay; TXDATAWIDTH_ipd <= TXDATAWIDTH after in_delay; TXENC64B66BUSE_ipd <= TXENC64B66BUSE after in_delay; TXENC8B10BUSE_ipd <= TXENC8B10BUSE after in_delay; TXGEARBOX64B66BUSE_ipd <= TXGEARBOX64B66BUSE after in_delay; TXINHIBIT_ipd <= TXINHIBIT after in_delay; TXINTDATAWIDTH_ipd <= TXINTDATAWIDTH after in_delay; TXPOLARITY_ipd <= TXPOLARITY after in_delay; TXRESET_ipd <= TXRESET after in_delay; TXSCRAM64B66BUSE_ipd <= TXSCRAM64B66BUSE after in_delay; TXUSRCLK_ipd <= TXUSRCLK after in_delay; TXUSRCLK2_ipd <= TXUSRCLK2 after in_delay; gt10_swift_bw_1 : GT10_SWIFT_BUS port map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD_BINARY, BREFCLKNIN => BREFCLKNIN_ipd, BREFCLKPIN => BREFCLKPIN_ipd, CHAN_BOND_64B66B_SV => CHAN_BOND_64B66B_SV_BINARY, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT_BINARY, CHAN_BOND_MODE => CHAN_BOND_MODE_BINARY, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT_BINARY, CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1_BINARY, CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2_BINARY, CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3_BINARY, CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4_BINARY, CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK_BINARY, CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1_BINARY, CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2_BINARY, CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3_BINARY, CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4_BINARY, CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK_BINARY, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE_BINARY, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN_BINARY, CHBONDDONE => CHBONDDONE_out, CHBONDI => CHBONDI_ipd, CHBONDO => CHBONDO_out, CLK_CORRECT_USE => CLK_CORRECT_USE_BINARY, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE_BINARY, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT_BINARY, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT_BINARY, CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1_BINARY, CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2_BINARY, CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3_BINARY, CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4_BINARY, CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK_BINARY, CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1_BINARY, CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2_BINARY, CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3_BINARY, CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4_BINARY, CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK_BINARY, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE_BINARY, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP_BINARY, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN_BINARY, COMMA_10B_MASK => COMMA_10B_MASK_BINARY, DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT_BINARY, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT_BINARY, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY_BINARY, ENCHANSYNC => ENCHANSYNC_ipd, ENMCOMMAALIGN => ENMCOMMAALIGN_ipd, ENPCOMMAALIGN => ENPCOMMAALIGN_ipd, GSR => GSR, LOOPBACK => LOOPBACK_ipd, MCOMMA_10B_VALUE => MCOMMA_10B_VALUE_BINARY, MCOMMA_DETECT => MCOMMA_DETECT_BINARY, PCOMMA_10B_VALUE => PCOMMA_10B_VALUE_BINARY, PCOMMA_DETECT => PCOMMA_DETECT_BINARY, PMAINIT => PMAINIT_ipd, PMAREGADDR => PMAREGADDR_ipd, PMAREGDATAIN => PMAREGDATAIN_ipd, PMAREGRW => PMAREGRW_ipd, PMAREGSTROBE => PMAREGSTROBE_ipd, PMARXLOCK => PMARXLOCK_out, PMARXLOCKSEL => PMARXLOCKSEL_ipd, PMA_PWR_CNTRL => PMA_PWR_CNTRL_BINARY, PMA_SPEED => PMA_SPEED_BINARY, POWERDOWN => POWERDOWN_ipd, REFCLK => REFCLK_ipd, REFCLK2 => REFCLK2_ipd, REFCLKBSEL => REFCLKBSEL_ipd, REFCLKSEL => REFCLKSEL_ipd, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE_ipd, RXBUFSTATUS => RXBUFSTATUS_out, RXCHARISCOMMA => RXCHARISCOMMA_out, RXCHARISK => RXCHARISK_out, RXCLKCORCNT => RXCLKCORCNT_out, RXCOMMADET => RXCOMMADET_out, RXCOMMADETUSE => RXCOMMADETUSE_ipd, RXDATA => RXDATA_out, RXDATAWIDTH => RXDATAWIDTH_ipd, RXDEC64B66BUSE => RXDEC64B66BUSE_ipd, RXDEC8B10BUSE => RXDEC8B10BUSE_ipd, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE_ipd, RXDISPERR => RXDISPERR_out, RXIGNOREBTF => RXIGNOREBTF_ipd, RXINTDATAWIDTH => RXINTDATAWIDTH_ipd, RXLOSSOFSYNC => RXLOSSOFSYNC_out, RXN => RXN_ipd, RXNOTINTABLE => RXNOTINTABLE_out, RXP => RXP_ipd, RXPOLARITY => RXPOLARITY_ipd, RXREALIGN => RXREALIGN_out, RXRECCLK => RXRECCLK_out, RXRESET => RXRESET_ipd, RXRUNDISP => RXRUNDISP_out, RXSLIDE => RXSLIDE_ipd, RXUSRCLK => RXUSRCLK_ipd, RXUSRCLK2 => RXUSRCLK2_ipd, RX_BUFFER_USE => RX_BUFFER_USE_BINARY, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM_BINARY, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR_BINARY, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD_BINARY, SH_CNT_MAX => SH_CNT_MAX_BINARY, SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX_BINARY, TXBUFERR => TXBUFERR_out, TXBYPASS8B10B => TXBYPASS8B10B_ipd, TXCHARDISPMODE => TXCHARDISPMODE_ipd, TXCHARDISPVAL => TXCHARDISPVAL_ipd, TXCHARISK => TXCHARISK_ipd, TXDATA => TXDATA_ipd, TXDATAWIDTH => TXDATAWIDTH_ipd, TXENC64B66BUSE => TXENC64B66BUSE_ipd, TXENC8B10BUSE => TXENC8B10BUSE_ipd, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE_ipd, TXINHIBIT => TXINHIBIT_ipd, TXINTDATAWIDTH => TXINTDATAWIDTH_ipd, TXKERR => TXKERR_out, TXN => TXN_out, TXOUTCLK => TXOUTCLK_out, TXP => TXP_out, TXPOLARITY => TXPOLARITY_ipd, TXRESET => TXRESET_ipd, TXRUNDISP => TXRUNDISP_out, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE_ipd, TXUSRCLK => TXUSRCLK_ipd, TXUSRCLK2 => TXUSRCLK2_ipd, TX_BUFFER_USE => TX_BUFFER_USE_BINARY ); INIPROC : process variable PMA_SPEED_BIT_VECTOR : bit_vector(119 downto 0); begin case ALIGN_COMMA_WORD is when 1 => ALIGN_COMMA_WORD_BINARY <= "00"; when 2 => ALIGN_COMMA_WORD_BINARY <= "01"; when 4 => ALIGN_COMMA_WORD_BINARY <= "10"; when others => assert FALSE report "Error : ALIGN_COMMA_WORD is not in 1, 2, 4." severity warning; end case; case CHAN_BOND_LIMIT is when 0 => CHAN_BOND_LIMIT_BINARY <= "000000"; when 1 => CHAN_BOND_LIMIT_BINARY <= "000001"; when 2 => CHAN_BOND_LIMIT_BINARY <= "000010"; when 3 => CHAN_BOND_LIMIT_BINARY <= "000011"; when 4 => CHAN_BOND_LIMIT_BINARY <= "000100"; when 5 => CHAN_BOND_LIMIT_BINARY <= "000101"; when 6 => CHAN_BOND_LIMIT_BINARY <= "000110"; when 7 => CHAN_BOND_LIMIT_BINARY <= "000111"; when 8 => CHAN_BOND_LIMIT_BINARY <= "001000"; when 9 => CHAN_BOND_LIMIT_BINARY <= "001001"; when 10 => CHAN_BOND_LIMIT_BINARY <= "001010"; when 11 => CHAN_BOND_LIMIT_BINARY <= "001011"; when 12 => CHAN_BOND_LIMIT_BINARY <= "001100"; when 13 => CHAN_BOND_LIMIT_BINARY <= "001101"; when 14 => CHAN_BOND_LIMIT_BINARY <= "001110"; when 15 => CHAN_BOND_LIMIT_BINARY <= "001111"; when 16 => CHAN_BOND_LIMIT_BINARY <= "010000"; when 17 => CHAN_BOND_LIMIT_BINARY <= "010001"; when 18 => CHAN_BOND_LIMIT_BINARY <= "010010"; when 19 => CHAN_BOND_LIMIT_BINARY <= "010011"; when 20 => CHAN_BOND_LIMIT_BINARY <= "010100"; when 21 => CHAN_BOND_LIMIT_BINARY <= "010101"; when 22 => CHAN_BOND_LIMIT_BINARY <= "010110"; when 23 => CHAN_BOND_LIMIT_BINARY <= "010111"; when 24 => CHAN_BOND_LIMIT_BINARY <= "011000"; when 25 => CHAN_BOND_LIMIT_BINARY <= "011001"; when 26 => CHAN_BOND_LIMIT_BINARY <= "011010"; when 27 => CHAN_BOND_LIMIT_BINARY <= "011011"; when 28 => CHAN_BOND_LIMIT_BINARY <= "011100"; when 29 => CHAN_BOND_LIMIT_BINARY <= "011101"; when 30 => CHAN_BOND_LIMIT_BINARY <= "011110"; when 31 => CHAN_BOND_LIMIT_BINARY <= "011111"; when 32 => CHAN_BOND_LIMIT_BINARY <= "100000"; when 33 => CHAN_BOND_LIMIT_BINARY <= "100001"; when 34 => CHAN_BOND_LIMIT_BINARY <= "100010"; when 35 => CHAN_BOND_LIMIT_BINARY <= "100011"; when 36 => CHAN_BOND_LIMIT_BINARY <= "100100"; when 37 => CHAN_BOND_LIMIT_BINARY <= "100101"; when 38 => CHAN_BOND_LIMIT_BINARY <= "100110"; when 39 => CHAN_BOND_LIMIT_BINARY <= "100111"; when 40 => CHAN_BOND_LIMIT_BINARY <= "101000"; when 41 => CHAN_BOND_LIMIT_BINARY <= "101001"; when 42 => CHAN_BOND_LIMIT_BINARY <= "101010"; when 43 => CHAN_BOND_LIMIT_BINARY <= "101011"; when 44 => CHAN_BOND_LIMIT_BINARY <= "101100"; when 45 => CHAN_BOND_LIMIT_BINARY <= "101101"; when 46 => CHAN_BOND_LIMIT_BINARY <= "101110"; when 47 => CHAN_BOND_LIMIT_BINARY <= "101111"; when 48 => CHAN_BOND_LIMIT_BINARY <= "110000"; when 49 => CHAN_BOND_LIMIT_BINARY <= "110001"; when 50 => CHAN_BOND_LIMIT_BINARY <= "110010"; when 51 => CHAN_BOND_LIMIT_BINARY <= "110011"; when 52 => CHAN_BOND_LIMIT_BINARY <= "110100"; when 53 => CHAN_BOND_LIMIT_BINARY <= "110101"; when 54 => CHAN_BOND_LIMIT_BINARY <= "110110"; when 55 => CHAN_BOND_LIMIT_BINARY <= "110111"; when 56 => CHAN_BOND_LIMIT_BINARY <= "111000"; when 57 => CHAN_BOND_LIMIT_BINARY <= "111001"; when 58 => CHAN_BOND_LIMIT_BINARY <= "111010"; when 59 => CHAN_BOND_LIMIT_BINARY <= "111011"; when 60 => CHAN_BOND_LIMIT_BINARY <= "111100"; when 61 => CHAN_BOND_LIMIT_BINARY <= "111101"; when 62 => CHAN_BOND_LIMIT_BINARY <= "111110"; when 63 => CHAN_BOND_LIMIT_BINARY <= "111111"; when others => assert FALSE report "Error : CHAN_BOND_LIMIT is not in range 0...63." severity warning; end case; -- case CHAN_BOND_MODE is if((CHAN_BOND_MODE = "OFF") or (CHAN_BOND_MODE = "off")) then CHAN_BOND_MODE_BINARY <= "00"; elsif((CHAN_BOND_MODE = "MASTER") or (CHAN_BOND_MODE = "master")) then CHAN_BOND_MODE_BINARY <= "01"; elsif((CHAN_BOND_MODE = "SLAVE_1_HOP") or (CHAN_BOND_MODE = "slave_1_hop")) then CHAN_BOND_MODE_BINARY <= "10"; elsif((CHAN_BOND_MODE = "SLAVE_2_HOPS") or (CHAN_BOND_MODE = "slave_2_hops")) then CHAN_BOND_MODE_BINARY <= "11"; else assert FALSE report "Error : CHAN_BOND_MODE = is not OFF, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS." severity warning; end if; -- end case; case CHAN_BOND_ONE_SHOT is when FALSE => CHAN_BOND_ONE_SHOT_BINARY <= '0'; when TRUE => CHAN_BOND_ONE_SHOT_BINARY <= '1'; when others => assert FALSE report "Error : CHAN_BOND_ONE_SHOT is neither TRUE nor FALSE." severity warning; end case; case CHAN_BOND_SEQ_2_USE is when FALSE => CHAN_BOND_SEQ_2_USE_BINARY <= '0'; when TRUE => CHAN_BOND_SEQ_2_USE_BINARY <= '1'; when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE is neither TRUE nor FALSE." severity warning; end case; case CHAN_BOND_SEQ_LEN is when 1 => CHAN_BOND_SEQ_LEN_BINARY <= "000"; when 2 => CHAN_BOND_SEQ_LEN_BINARY <= "001"; when 3 => CHAN_BOND_SEQ_LEN_BINARY <= "010"; when 4 => CHAN_BOND_SEQ_LEN_BINARY <= "011"; when 8 => CHAN_BOND_SEQ_LEN_BINARY <= "111"; when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN is not in 1, 2, 3, 4, 8." severity warning; end case; case CHAN_BOND_64B66B_SV is when FALSE => CHAN_BOND_64B66B_SV_BINARY <= '0'; when TRUE => CHAN_BOND_64B66B_SV_BINARY <= '1'; when others => assert FALSE report "Error : CHAN_BOND_64B66B_SV is neither TRUE nor FALSE." severity warning; end case; case CLK_COR_8B10B_DE is when FALSE => CLK_COR_8B10B_DE_BINARY <= '0'; when TRUE => CLK_COR_8B10B_DE_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_8B10B_DE is neither TRUE nor FALSE." severity warning; end case; case CLK_COR_MAX_LAT is when 0 => CLK_COR_MAX_LAT_BINARY <= "000000"; when 1 => CLK_COR_MAX_LAT_BINARY <= "000001"; when 2 => CLK_COR_MAX_LAT_BINARY <= "000010"; when 3 => CLK_COR_MAX_LAT_BINARY <= "000011"; when 4 => CLK_COR_MAX_LAT_BINARY <= "000100"; when 5 => CLK_COR_MAX_LAT_BINARY <= "000101"; when 6 => CLK_COR_MAX_LAT_BINARY <= "000110"; when 7 => CLK_COR_MAX_LAT_BINARY <= "000111"; when 8 => CLK_COR_MAX_LAT_BINARY <= "001000"; when 9 => CLK_COR_MAX_LAT_BINARY <= "001001"; when 10 => CLK_COR_MAX_LAT_BINARY <= "001010"; when 11 => CLK_COR_MAX_LAT_BINARY <= "001011"; when 12 => CLK_COR_MAX_LAT_BINARY <= "001100"; when 13 => CLK_COR_MAX_LAT_BINARY <= "001101"; when 14 => CLK_COR_MAX_LAT_BINARY <= "001110"; when 15 => CLK_COR_MAX_LAT_BINARY <= "001111"; when 16 => CLK_COR_MAX_LAT_BINARY <= "010000"; when 17 => CLK_COR_MAX_LAT_BINARY <= "010001"; when 18 => CLK_COR_MAX_LAT_BINARY <= "010010"; when 19 => CLK_COR_MAX_LAT_BINARY <= "010011"; when 20 => CLK_COR_MAX_LAT_BINARY <= "010100"; when 21 => CLK_COR_MAX_LAT_BINARY <= "010101"; when 22 => CLK_COR_MAX_LAT_BINARY <= "010110"; when 23 => CLK_COR_MAX_LAT_BINARY <= "010111"; when 24 => CLK_COR_MAX_LAT_BINARY <= "011000"; when 25 => CLK_COR_MAX_LAT_BINARY <= "011001"; when 26 => CLK_COR_MAX_LAT_BINARY <= "011010"; when 27 => CLK_COR_MAX_LAT_BINARY <= "011011"; when 28 => CLK_COR_MAX_LAT_BINARY <= "011100"; when 29 => CLK_COR_MAX_LAT_BINARY <= "011101"; when 30 => CLK_COR_MAX_LAT_BINARY <= "011110"; when 31 => CLK_COR_MAX_LAT_BINARY <= "011111"; when 32 => CLK_COR_MAX_LAT_BINARY <= "100000"; when 33 => CLK_COR_MAX_LAT_BINARY <= "100001"; when 34 => CLK_COR_MAX_LAT_BINARY <= "100010"; when 35 => CLK_COR_MAX_LAT_BINARY <= "100011"; when 36 => CLK_COR_MAX_LAT_BINARY <= "100100"; when 37 => CLK_COR_MAX_LAT_BINARY <= "100101"; when 38 => CLK_COR_MAX_LAT_BINARY <= "100110"; when 39 => CLK_COR_MAX_LAT_BINARY <= "100111"; when 40 => CLK_COR_MAX_LAT_BINARY <= "101000"; when 41 => CLK_COR_MAX_LAT_BINARY <= "101001"; when 42 => CLK_COR_MAX_LAT_BINARY <= "101010"; when 43 => CLK_COR_MAX_LAT_BINARY <= "101011"; when 44 => CLK_COR_MAX_LAT_BINARY <= "101100"; when 45 => CLK_COR_MAX_LAT_BINARY <= "101101"; when 46 => CLK_COR_MAX_LAT_BINARY <= "101110"; when 47 => CLK_COR_MAX_LAT_BINARY <= "101111"; when 48 => CLK_COR_MAX_LAT_BINARY <= "110000"; when 49 => CLK_COR_MAX_LAT_BINARY <= "110001"; when 50 => CLK_COR_MAX_LAT_BINARY <= "110010"; when 51 => CLK_COR_MAX_LAT_BINARY <= "110011"; when 52 => CLK_COR_MAX_LAT_BINARY <= "110100"; when 53 => CLK_COR_MAX_LAT_BINARY <= "110101"; when 54 => CLK_COR_MAX_LAT_BINARY <= "110110"; when 55 => CLK_COR_MAX_LAT_BINARY <= "110111"; when 56 => CLK_COR_MAX_LAT_BINARY <= "111000"; when 57 => CLK_COR_MAX_LAT_BINARY <= "111001"; when 58 => CLK_COR_MAX_LAT_BINARY <= "111010"; when 59 => CLK_COR_MAX_LAT_BINARY <= "111011"; when 60 => CLK_COR_MAX_LAT_BINARY <= "111100"; when 61 => CLK_COR_MAX_LAT_BINARY <= "111101"; when 62 => CLK_COR_MAX_LAT_BINARY <= "111110"; when 63 => CLK_COR_MAX_LAT_BINARY <= "111111"; when others => assert FALSE report "Error : CLK_COR_MAX_LAT is not in range 0...63." severity warning; end case; case CLK_COR_MIN_LAT is when 0 => CLK_COR_MIN_LAT_BINARY <= "000000"; when 1 => CLK_COR_MIN_LAT_BINARY <= "000001"; when 2 => CLK_COR_MIN_LAT_BINARY <= "000010"; when 3 => CLK_COR_MIN_LAT_BINARY <= "000011"; when 4 => CLK_COR_MIN_LAT_BINARY <= "000100"; when 5 => CLK_COR_MIN_LAT_BINARY <= "000101"; when 6 => CLK_COR_MIN_LAT_BINARY <= "000110"; when 7 => CLK_COR_MIN_LAT_BINARY <= "000111"; when 8 => CLK_COR_MIN_LAT_BINARY <= "001000"; when 9 => CLK_COR_MIN_LAT_BINARY <= "001001"; when 10 => CLK_COR_MIN_LAT_BINARY <= "001010"; when 11 => CLK_COR_MIN_LAT_BINARY <= "001011"; when 12 => CLK_COR_MIN_LAT_BINARY <= "001100"; when 13 => CLK_COR_MIN_LAT_BINARY <= "001101"; when 14 => CLK_COR_MIN_LAT_BINARY <= "001110"; when 15 => CLK_COR_MIN_LAT_BINARY <= "001111"; when 16 => CLK_COR_MIN_LAT_BINARY <= "010000"; when 17 => CLK_COR_MIN_LAT_BINARY <= "010001"; when 18 => CLK_COR_MIN_LAT_BINARY <= "010010"; when 19 => CLK_COR_MIN_LAT_BINARY <= "010011"; when 20 => CLK_COR_MIN_LAT_BINARY <= "010100"; when 21 => CLK_COR_MIN_LAT_BINARY <= "010101"; when 22 => CLK_COR_MIN_LAT_BINARY <= "010110"; when 23 => CLK_COR_MIN_LAT_BINARY <= "010111"; when 24 => CLK_COR_MIN_LAT_BINARY <= "011000"; when 25 => CLK_COR_MIN_LAT_BINARY <= "011001"; when 26 => CLK_COR_MIN_LAT_BINARY <= "011010"; when 27 => CLK_COR_MIN_LAT_BINARY <= "011011"; when 28 => CLK_COR_MIN_LAT_BINARY <= "011100"; when 29 => CLK_COR_MIN_LAT_BINARY <= "011101"; when 30 => CLK_COR_MIN_LAT_BINARY <= "011110"; when 31 => CLK_COR_MIN_LAT_BINARY <= "011111"; when 32 => CLK_COR_MIN_LAT_BINARY <= "100000"; when 33 => CLK_COR_MIN_LAT_BINARY <= "100001"; when 34 => CLK_COR_MIN_LAT_BINARY <= "100010"; when 35 => CLK_COR_MIN_LAT_BINARY <= "100011"; when 36 => CLK_COR_MIN_LAT_BINARY <= "100100"; when 37 => CLK_COR_MIN_LAT_BINARY <= "100101"; when 38 => CLK_COR_MIN_LAT_BINARY <= "100110"; when 39 => CLK_COR_MIN_LAT_BINARY <= "100111"; when 40 => CLK_COR_MIN_LAT_BINARY <= "101000"; when 41 => CLK_COR_MIN_LAT_BINARY <= "101001"; when 42 => CLK_COR_MIN_LAT_BINARY <= "101010"; when 43 => CLK_COR_MIN_LAT_BINARY <= "101011"; when 44 => CLK_COR_MIN_LAT_BINARY <= "101100"; when 45 => CLK_COR_MIN_LAT_BINARY <= "101101"; when 46 => CLK_COR_MIN_LAT_BINARY <= "101110"; when 47 => CLK_COR_MIN_LAT_BINARY <= "101111"; when 48 => CLK_COR_MIN_LAT_BINARY <= "110000"; when 49 => CLK_COR_MIN_LAT_BINARY <= "110001"; when 50 => CLK_COR_MIN_LAT_BINARY <= "110010"; when 51 => CLK_COR_MIN_LAT_BINARY <= "110011"; when 52 => CLK_COR_MIN_LAT_BINARY <= "110100"; when 53 => CLK_COR_MIN_LAT_BINARY <= "110101"; when 54 => CLK_COR_MIN_LAT_BINARY <= "110110"; when 55 => CLK_COR_MIN_LAT_BINARY <= "110111"; when 56 => CLK_COR_MIN_LAT_BINARY <= "111000"; when 57 => CLK_COR_MIN_LAT_BINARY <= "111001"; when 58 => CLK_COR_MIN_LAT_BINARY <= "111010"; when 59 => CLK_COR_MIN_LAT_BINARY <= "111011"; when 60 => CLK_COR_MIN_LAT_BINARY <= "111100"; when 61 => CLK_COR_MIN_LAT_BINARY <= "111101"; when 62 => CLK_COR_MIN_LAT_BINARY <= "111110"; when 63 => CLK_COR_MIN_LAT_BINARY <= "111111"; when others => assert FALSE report "Error : CLK_COR_MIN_LAT is not in range 0...63." severity warning; end case; case CLK_COR_SEQ_2_USE is when FALSE => CLK_COR_SEQ_2_USE_BINARY <= '0'; when TRUE => CLK_COR_SEQ_2_USE_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE is neither TRUE nor FALSE." severity warning; end case; case CLK_COR_SEQ_DROP is when FALSE => CLK_COR_SEQ_DROP_BINARY <= '0'; when TRUE => CLK_COR_SEQ_DROP_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_SEQ_DROP is neither TRUE nor FALSE." severity warning; end case; case CLK_COR_SEQ_LEN is when 1 => CLK_COR_SEQ_LEN_BINARY <= "000"; when 2 => CLK_COR_SEQ_LEN_BINARY <= "001"; when 3 => CLK_COR_SEQ_LEN_BINARY <= "010"; when 4 => CLK_COR_SEQ_LEN_BINARY <= "011"; when 8 => CLK_COR_SEQ_LEN_BINARY <= "111"; when others => assert FALSE report "Error : CLK_COR_SEQ_LEN is not in 1, 2, 3, 4, 8." severity warning; end case; case CLK_CORRECT_USE is when FALSE => CLK_CORRECT_USE_BINARY <= '0'; when TRUE => CLK_CORRECT_USE_BINARY <= '1'; when others => assert FALSE report "Error : CLK_CORRECT_USE is neither TRUE nor FALSE." severity warning; end case; case DEC_MCOMMA_DETECT is when FALSE => DEC_MCOMMA_DETECT_BINARY <= '0'; when TRUE => DEC_MCOMMA_DETECT_BINARY <= '1'; when others => assert FALSE report "Error : DEC_MCOMMA_DETECT is neither TRUE nor FALSE." severity warning; end case; case DEC_PCOMMA_DETECT is when FALSE => DEC_PCOMMA_DETECT_BINARY <= '0'; when TRUE => DEC_PCOMMA_DETECT_BINARY <= '1'; when others => assert FALSE report "Error : DEC_PCOMMA_DETECT is neither TRUE nor FALSE." severity warning; end case; case DEC_VALID_COMMA_ONLY is when FALSE => DEC_VALID_COMMA_ONLY_BINARY <= '0'; when TRUE => DEC_VALID_COMMA_ONLY_BINARY <= '1'; when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY is neither TRUE nor FALSE." severity warning; end case; case MCOMMA_DETECT is when FALSE => MCOMMA_DETECT_BINARY <= '0'; when TRUE => MCOMMA_DETECT_BINARY <= '1'; when others => assert FALSE report "Error : MCOMMA_DETECT is neither TRUE nor FALSE." severity warning; end case; case PCOMMA_DETECT is when FALSE => PCOMMA_DETECT_BINARY <= '0'; when TRUE => PCOMMA_DETECT_BINARY <= '1'; when others => assert FALSE report "Error : PCOMMA_DETECT is neither TRUE nor FALSE." severity warning; end case; -- case PMA_SPEED_USE is if((PMA_SPEED_USE = "PMA_SPEED") or (PMA_SPEED_USE = "pma_speed")) then -- case PMA_SPEED is if (PMA_SPEED = "0_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d00208c9050d4068"; elsif (PMA_SPEED = "0_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d00208c9050d4068"; elsif (PMA_SPEED = "1_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d10208c9050d4168"; elsif (PMA_SPEED = "1_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d10208c9050d4168"; elsif (PMA_SPEED = "2_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d40208c9060d4468"; elsif (PMA_SPEED = "2_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d40208c9060d4468"; elsif (PMA_SPEED = "3_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d50208c9060d4568"; elsif (PMA_SPEED = "3_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d50208c9060d4568"; elsif (PMA_SPEED = "4_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d80208c9020d4868"; elsif (PMA_SPEED = "4_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d80208c9020d4868"; elsif (PMA_SPEED = "5_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d90208c9020d4968"; elsif (PMA_SPEED = "5_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d90208c9020d4968"; elsif (PMA_SPEED = "6_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d00208c9050d4068"; elsif (PMA_SPEED = "6_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d00208c9050d4068"; elsif (PMA_SPEED = "7_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d10208c9050d4168"; elsif (PMA_SPEED = "7_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d10208c9050d4168"; elsif (PMA_SPEED = "8_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d40208c9050d4468"; elsif (PMA_SPEED = "8_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d40208c9050d4468"; elsif (PMA_SPEED = "9_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d50208c9050d4568"; elsif (PMA_SPEED = "9_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d50208c9050d4568"; elsif (PMA_SPEED = "10_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d80208c9020d4868"; elsif (PMA_SPEED = "10_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d80208c9020d4868"; elsif (PMA_SPEED = "11_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d90208c9020d4968"; elsif (PMA_SPEED = "11_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504d90208c9020d4968"; elsif (PMA_SPEED = "12_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506e20208c9050da268"; elsif (PMA_SPEED = "12_80") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506e20208c9050da268"; elsif (PMA_SPEED = "13_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506e60208c9050da668"; elsif (PMA_SPEED = "13_80") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506e60208c9050da668"; elsif (PMA_SPEED = "14_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506ea0208c9020daa68"; elsif (PMA_SPEED = "14_80") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1506ea0208c9020daa68"; elsif (PMA_SPEED = "15_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c00208c9050d0068"; elsif (PMA_SPEED = "15_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c00208c9050d0068"; elsif (PMA_SPEED = "16_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c40208c9050d0468"; elsif (PMA_SPEED = "16_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c40208c9050d0468"; elsif (PMA_SPEED = "17_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c80208c9010d0868"; elsif (PMA_SPEED = "17_64") then PMA_SPEED_BIT_VECTOR := X"00ffcd24ca1504c80208c9010d0868"; elsif (PMA_SPEED = "18_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd50ca1106e21208c9050da228"; elsif (PMA_SPEED = "18_80") then PMA_SPEED_BIT_VECTOR := X"00ffcd50ca1106e21208c9050da228"; elsif (PMA_SPEED = "19_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd50ca1106e21208c9050da228"; elsif (PMA_SPEED = "19_80") then PMA_SPEED_BIT_VECTOR := X"00ffcd50ca1106e21208c9050da228"; elsif (PMA_SPEED = "20_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd30ca1106e21208c9050da228"; elsif (PMA_SPEED = "20_80") then PMA_SPEED_BIT_VECTOR := X"00ffcd50ca1106e21208c9050da228"; elsif (PMA_SPEED = "21_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd50ca0d06e21208c9050da228"; elsif (PMA_SPEED = "21_80") then PMA_SPEED_BIT_VECTOR := X"00ffcd50ca0d06e21208c9050da228"; elsif (PMA_SPEED = "22_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd50ca0d06e61208c9010da628"; elsif (PMA_SPEED = "22_80") then PMA_SPEED_BIT_VECTOR := X"00ffcd50ca0d06e61208c9010da628"; elsif (PMA_SPEED = "23_10") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132263068090104a628"; elsif (PMA_SPEED = "23_20") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132663068090105a628"; elsif (PMA_SPEED = "23_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132663068090105a628"; elsif (PMA_SPEED = "24_10") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132223068090504a228"; elsif (PMA_SPEED = "24_20") then PMA_SPEED_BIT_VECTOR := X"00fc0db00b0f32623068090505a228"; elsif (PMA_SPEED = "24_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132623068090505a228"; elsif (PMA_SPEED = "25_10") then PMA_SPEED_BIT_VECTOR := X"00fc0db00b0f32263068090104a628"; elsif (PMA_SPEED = "25_20") then PMA_SPEED_BIT_VECTOR := X"00fc0db00b0f32663068090105a628"; elsif (PMA_SPEED = "25_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132663068090105a628"; elsif (PMA_SPEED = "26_10") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b01322a3068090104aa28"; elsif (PMA_SPEED = "26_20") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b01326a3068090105aa28"; elsif (PMA_SPEED = "26_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b01326a3068090105aa28"; elsif (PMA_SPEED = "27_10") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132223068090504a220"; elsif (PMA_SPEED = "27_20") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132623068090505a220"; elsif (PMA_SPEED = "27_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132623068090505a220"; elsif (PMA_SPEED = "28_10") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132263068090104a620"; elsif (PMA_SPEED = "28_20") then PMA_SPEED_BIT_VECTOR := X"00fc0d300b0f32663068090105a620"; elsif (PMA_SPEED = "28_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b0132663068090105a620"; elsif (PMA_SPEED = "29_10") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b01322a3068090104aa20"; elsif (PMA_SPEED = "29_20") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b01326a3068090105aa20"; elsif (PMA_SPEED = "29_40") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b01326a3068090105aa20"; elsif (PMA_SPEED = "30_16") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b01304430680901050420"; elsif (PMA_SPEED = "30_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b01304430680901050420"; elsif (PMA_SPEED = "30_8") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b01300430680901040420"; elsif (PMA_SPEED = "31_16") then PMA_SPEED_BIT_VECTOR := X"00fc0d300b0f304830680901050820"; elsif (PMA_SPEED = "31_32") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b01304830680901050820"; elsif (PMA_SPEED = "31_8") then PMA_SPEED_BIT_VECTOR := X"00ffcd500b01300830680901040820"; else assert FALSE report "Error : PMA_SPEED = is not 0_32, 0_64, 1_32, 1_64, 2_32, 2_64, 3_32, 3_64, 4_32, 4_64, 5_32, 5_64, 6_32, 6_64, 7_32, 7_64, 8_32, 8_64, 9_32, 9_64, 10_32, 10_64, 11_32, 11_64, 12_40, 12_80, 13_40, 13_80, 14_40, 14_80, 15_32, 15_64, 16_32, 16_64, 17_32, 17_64, 18_40, 18_80, 19_40, 19_80, 20_40, 20_80, 21_40, 21_80, 22_40, 22_80, 23_10, 23_20, 23_40, 24_10, 24_20, 24_40, 25_10, 25_20, 25_40, 26_10, 26_20, 26_40, 27_10, 27_20, 27_40, 28_10, 28_20, 28_40, 29_10, 29_20, 29_40, 30_16, 30_32, 30_8, 31_16, 31_32, 31_8." severity warning; end if; -- end case; elsif((PMA_SPEED_USE = "PMA_SPEED_HEX") or (PMA_SPEED_USE = "pma_speed_hex")) then PMA_SPEED_BIT_VECTOR := PMA_SPEED_HEX; else assert FALSE report "Error : PMA_SPEED_USE is neither PMA_SPEED nor PMA_SPEED_HEX ." severity warning; end if; -- end case; PMA_SPEED_BINARY <= To_StdLogicVector(PMA_SPEED_BIT_VECTOR); case RX_BUFFER_USE is when FALSE => RX_BUFFER_USE_BINARY <= '0'; when TRUE => RX_BUFFER_USE_BINARY <= '1'; when others => assert FALSE report "Error : RX_BUFFER_USE is neither TRUE nor FALSE." severity warning; end case; case RX_LOS_INVALID_INCR is when 1 => RX_LOS_INVALID_INCR_BINARY <= "00000001"; when 2 => RX_LOS_INVALID_INCR_BINARY <= "00000010"; when 4 => RX_LOS_INVALID_INCR_BINARY <= "00000100"; when 8 => RX_LOS_INVALID_INCR_BINARY <= "00001000"; when 16 => RX_LOS_INVALID_INCR_BINARY <= "00010000"; when 32 => RX_LOS_INVALID_INCR_BINARY <= "00100000"; when 64 => RX_LOS_INVALID_INCR_BINARY <= "01000000"; when 128 => RX_LOS_INVALID_INCR_BINARY <= "10000000"; when others => assert FALSE report "Error : RX_LOS_INVALID_INCR is not in 1, 2, 4, 8, 16, 32, 64, 128." severity warning; end case; case RX_LOS_THRESHOLD is when 4 => RX_LOS_THRESHOLD_BINARY <= "00000001"; when 8 => RX_LOS_THRESHOLD_BINARY <= "00000010"; when 16 => RX_LOS_THRESHOLD_BINARY <= "00000100"; when 32 => RX_LOS_THRESHOLD_BINARY <= "00001000"; when 64 => RX_LOS_THRESHOLD_BINARY <= "00010000"; when 128 => RX_LOS_THRESHOLD_BINARY <= "00100000"; when 256 => RX_LOS_THRESHOLD_BINARY <= "01000000"; when 512 => RX_LOS_THRESHOLD_BINARY <= "10000000"; when others => assert FALSE report "Error : RX_LOS_THRESHOLD is not in 4, 8, 16, 32, 64, 128, 256, 512." severity warning; end case; case RX_LOSS_OF_SYNC_FSM is when FALSE => RX_LOSS_OF_SYNC_FSM_BINARY <= '0'; when TRUE => RX_LOSS_OF_SYNC_FSM_BINARY <= '1'; when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM is neither TRUE nor FALSE." severity warning; end case; case SH_CNT_MAX is when 1 => SH_CNT_MAX_BINARY <= "00000000"; when 2 => SH_CNT_MAX_BINARY <= "00000001"; when 3 => SH_CNT_MAX_BINARY <= "00000010"; when 4 => SH_CNT_MAX_BINARY <= "00000011"; when 5 => SH_CNT_MAX_BINARY <= "00000100"; when 6 => SH_CNT_MAX_BINARY <= "00000101"; when 7 => SH_CNT_MAX_BINARY <= "00000110"; when 8 => SH_CNT_MAX_BINARY <= "00000111"; when 9 => SH_CNT_MAX_BINARY <= "00001000"; when 10 => SH_CNT_MAX_BINARY <= "00001001"; when 11 => SH_CNT_MAX_BINARY <= "00001010"; when 12 => SH_CNT_MAX_BINARY <= "00001011"; when 13 => SH_CNT_MAX_BINARY <= "00001100"; when 14 => SH_CNT_MAX_BINARY <= "00001101"; when 15 => SH_CNT_MAX_BINARY <= "00001110"; when 16 => SH_CNT_MAX_BINARY <= "00001111"; when 17 => SH_CNT_MAX_BINARY <= "00010000"; when 18 => SH_CNT_MAX_BINARY <= "00010001"; when 19 => SH_CNT_MAX_BINARY <= "00010010"; when 20 => SH_CNT_MAX_BINARY <= "00010011"; when 21 => SH_CNT_MAX_BINARY <= "00010100"; when 22 => SH_CNT_MAX_BINARY <= "00010101"; when 23 => SH_CNT_MAX_BINARY <= "00010110"; when 24 => SH_CNT_MAX_BINARY <= "00010111"; when 25 => SH_CNT_MAX_BINARY <= "00011000"; when 26 => SH_CNT_MAX_BINARY <= "00011001"; when 27 => SH_CNT_MAX_BINARY <= "00011010"; when 28 => SH_CNT_MAX_BINARY <= "00011011"; when 29 => SH_CNT_MAX_BINARY <= "00011100"; when 30 => SH_CNT_MAX_BINARY <= "00011101"; when 31 => SH_CNT_MAX_BINARY <= "00011110"; when 32 => SH_CNT_MAX_BINARY <= "00011111"; when 33 => SH_CNT_MAX_BINARY <= "00100000"; when 34 => SH_CNT_MAX_BINARY <= "00100001"; when 35 => SH_CNT_MAX_BINARY <= "00100010"; when 36 => SH_CNT_MAX_BINARY <= "00100011"; when 37 => SH_CNT_MAX_BINARY <= "00100100"; when 38 => SH_CNT_MAX_BINARY <= "00100101"; when 39 => SH_CNT_MAX_BINARY <= "00100110"; when 40 => SH_CNT_MAX_BINARY <= "00100111"; when 41 => SH_CNT_MAX_BINARY <= "00101000"; when 42 => SH_CNT_MAX_BINARY <= "00101001"; when 43 => SH_CNT_MAX_BINARY <= "00101010"; when 44 => SH_CNT_MAX_BINARY <= "00101011"; when 45 => SH_CNT_MAX_BINARY <= "00101100"; when 46 => SH_CNT_MAX_BINARY <= "00101101"; when 47 => SH_CNT_MAX_BINARY <= "00101110"; when 48 => SH_CNT_MAX_BINARY <= "00101111"; when 49 => SH_CNT_MAX_BINARY <= "00110000"; when 50 => SH_CNT_MAX_BINARY <= "00110001"; when 51 => SH_CNT_MAX_BINARY <= "00110010"; when 52 => SH_CNT_MAX_BINARY <= "00110011"; when 53 => SH_CNT_MAX_BINARY <= "00110100"; when 54 => SH_CNT_MAX_BINARY <= "00110101"; when 55 => SH_CNT_MAX_BINARY <= "00110110"; when 56 => SH_CNT_MAX_BINARY <= "00110111"; when 57 => SH_CNT_MAX_BINARY <= "00111000"; when 58 => SH_CNT_MAX_BINARY <= "00111001"; when 59 => SH_CNT_MAX_BINARY <= "00111010"; when 60 => SH_CNT_MAX_BINARY <= "00111011"; when 61 => SH_CNT_MAX_BINARY <= "00111100"; when 62 => SH_CNT_MAX_BINARY <= "00111101"; when 63 => SH_CNT_MAX_BINARY <= "00111110"; when 64 => SH_CNT_MAX_BINARY <= "00111111"; when 65 => SH_CNT_MAX_BINARY <= "01000000"; when 66 => SH_CNT_MAX_BINARY <= "01000001"; when 67 => SH_CNT_MAX_BINARY <= "01000010"; when 68 => SH_CNT_MAX_BINARY <= "01000011"; when 69 => SH_CNT_MAX_BINARY <= "01000100"; when 70 => SH_CNT_MAX_BINARY <= "01000101"; when 71 => SH_CNT_MAX_BINARY <= "01000110"; when 72 => SH_CNT_MAX_BINARY <= "01000111"; when 73 => SH_CNT_MAX_BINARY <= "01001000"; when 74 => SH_CNT_MAX_BINARY <= "01001001"; when 75 => SH_CNT_MAX_BINARY <= "01001010"; when 76 => SH_CNT_MAX_BINARY <= "01001011"; when 77 => SH_CNT_MAX_BINARY <= "01001100"; when 78 => SH_CNT_MAX_BINARY <= "01001101"; when 79 => SH_CNT_MAX_BINARY <= "01001110"; when 80 => SH_CNT_MAX_BINARY <= "01001111"; when 81 => SH_CNT_MAX_BINARY <= "01010000"; when 82 => SH_CNT_MAX_BINARY <= "01010001"; when 83 => SH_CNT_MAX_BINARY <= "01010010"; when 84 => SH_CNT_MAX_BINARY <= "01010011"; when 85 => SH_CNT_MAX_BINARY <= "01010100"; when 86 => SH_CNT_MAX_BINARY <= "01010101"; when 87 => SH_CNT_MAX_BINARY <= "01010110"; when 88 => SH_CNT_MAX_BINARY <= "01010111"; when 89 => SH_CNT_MAX_BINARY <= "01011000"; when 90 => SH_CNT_MAX_BINARY <= "01011001"; when 91 => SH_CNT_MAX_BINARY <= "01011010"; when 92 => SH_CNT_MAX_BINARY <= "01011011"; when 93 => SH_CNT_MAX_BINARY <= "01011100"; when 94 => SH_CNT_MAX_BINARY <= "01011101"; when 95 => SH_CNT_MAX_BINARY <= "01011110"; when 96 => SH_CNT_MAX_BINARY <= "01011111"; when 97 => SH_CNT_MAX_BINARY <= "01100000"; when 98 => SH_CNT_MAX_BINARY <= "01100001"; when 99 => SH_CNT_MAX_BINARY <= "01100010"; when 100 => SH_CNT_MAX_BINARY <= "01100011"; when 101 => SH_CNT_MAX_BINARY <= "01100100"; when 102 => SH_CNT_MAX_BINARY <= "01100101"; when 103 => SH_CNT_MAX_BINARY <= "01100110"; when 104 => SH_CNT_MAX_BINARY <= "01100111"; when 105 => SH_CNT_MAX_BINARY <= "01101000"; when 106 => SH_CNT_MAX_BINARY <= "01101001"; when 107 => SH_CNT_MAX_BINARY <= "01101010"; when 108 => SH_CNT_MAX_BINARY <= "01101011"; when 109 => SH_CNT_MAX_BINARY <= "01101100"; when 110 => SH_CNT_MAX_BINARY <= "01101101"; when 111 => SH_CNT_MAX_BINARY <= "01101110"; when 112 => SH_CNT_MAX_BINARY <= "01101111"; when 113 => SH_CNT_MAX_BINARY <= "01110000"; when 114 => SH_CNT_MAX_BINARY <= "01110001"; when 115 => SH_CNT_MAX_BINARY <= "01110010"; when 116 => SH_CNT_MAX_BINARY <= "01110011"; when 117 => SH_CNT_MAX_BINARY <= "01110100"; when 118 => SH_CNT_MAX_BINARY <= "01110101"; when 119 => SH_CNT_MAX_BINARY <= "01110110"; when 120 => SH_CNT_MAX_BINARY <= "01110111"; when 121 => SH_CNT_MAX_BINARY <= "01111000"; when 122 => SH_CNT_MAX_BINARY <= "01111001"; when 123 => SH_CNT_MAX_BINARY <= "01111010"; when 124 => SH_CNT_MAX_BINARY <= "01111011"; when 125 => SH_CNT_MAX_BINARY <= "01111100"; when 126 => SH_CNT_MAX_BINARY <= "01111101"; when 127 => SH_CNT_MAX_BINARY <= "01111110"; when 128 => SH_CNT_MAX_BINARY <= "01111111"; when 129 => SH_CNT_MAX_BINARY <= "10000000"; when 130 => SH_CNT_MAX_BINARY <= "10000001"; when 131 => SH_CNT_MAX_BINARY <= "10000010"; when 132 => SH_CNT_MAX_BINARY <= "10000011"; when 133 => SH_CNT_MAX_BINARY <= "10000100"; when 134 => SH_CNT_MAX_BINARY <= "10000101"; when 135 => SH_CNT_MAX_BINARY <= "10000110"; when 136 => SH_CNT_MAX_BINARY <= "10000111"; when 137 => SH_CNT_MAX_BINARY <= "10001000"; when 138 => SH_CNT_MAX_BINARY <= "10001001"; when 139 => SH_CNT_MAX_BINARY <= "10001010"; when 140 => SH_CNT_MAX_BINARY <= "10001011"; when 141 => SH_CNT_MAX_BINARY <= "10001100"; when 142 => SH_CNT_MAX_BINARY <= "10001101"; when 143 => SH_CNT_MAX_BINARY <= "10001110"; when 144 => SH_CNT_MAX_BINARY <= "10001111"; when 145 => SH_CNT_MAX_BINARY <= "10010000"; when 146 => SH_CNT_MAX_BINARY <= "10010001"; when 147 => SH_CNT_MAX_BINARY <= "10010010"; when 148 => SH_CNT_MAX_BINARY <= "10010011"; when 149 => SH_CNT_MAX_BINARY <= "10010100"; when 150 => SH_CNT_MAX_BINARY <= "10010101"; when 151 => SH_CNT_MAX_BINARY <= "10010110"; when 152 => SH_CNT_MAX_BINARY <= "10010111"; when 153 => SH_CNT_MAX_BINARY <= "10011000"; when 154 => SH_CNT_MAX_BINARY <= "10011001"; when 155 => SH_CNT_MAX_BINARY <= "10011010"; when 156 => SH_CNT_MAX_BINARY <= "10011011"; when 157 => SH_CNT_MAX_BINARY <= "10011100"; when 158 => SH_CNT_MAX_BINARY <= "10011101"; when 159 => SH_CNT_MAX_BINARY <= "10011110"; when 160 => SH_CNT_MAX_BINARY <= "10011111"; when 161 => SH_CNT_MAX_BINARY <= "10100000"; when 162 => SH_CNT_MAX_BINARY <= "10100001"; when 163 => SH_CNT_MAX_BINARY <= "10100010"; when 164 => SH_CNT_MAX_BINARY <= "10100011"; when 165 => SH_CNT_MAX_BINARY <= "10100100"; when 166 => SH_CNT_MAX_BINARY <= "10100101"; when 167 => SH_CNT_MAX_BINARY <= "10100110"; when 168 => SH_CNT_MAX_BINARY <= "10100111"; when 169 => SH_CNT_MAX_BINARY <= "10101000"; when 170 => SH_CNT_MAX_BINARY <= "10101001"; when 171 => SH_CNT_MAX_BINARY <= "10101010"; when 172 => SH_CNT_MAX_BINARY <= "10101011"; when 173 => SH_CNT_MAX_BINARY <= "10101100"; when 174 => SH_CNT_MAX_BINARY <= "10101101"; when 175 => SH_CNT_MAX_BINARY <= "10101110"; when 176 => SH_CNT_MAX_BINARY <= "10101111"; when 177 => SH_CNT_MAX_BINARY <= "10110000"; when 178 => SH_CNT_MAX_BINARY <= "10110001"; when 179 => SH_CNT_MAX_BINARY <= "10110010"; when 180 => SH_CNT_MAX_BINARY <= "10110011"; when 181 => SH_CNT_MAX_BINARY <= "10110100"; when 182 => SH_CNT_MAX_BINARY <= "10110101"; when 183 => SH_CNT_MAX_BINARY <= "10110110"; when 184 => SH_CNT_MAX_BINARY <= "10110111"; when 185 => SH_CNT_MAX_BINARY <= "10111000"; when 186 => SH_CNT_MAX_BINARY <= "10111001"; when 187 => SH_CNT_MAX_BINARY <= "10111010"; when 188 => SH_CNT_MAX_BINARY <= "10111011"; when 189 => SH_CNT_MAX_BINARY <= "10111100"; when 190 => SH_CNT_MAX_BINARY <= "10111101"; when 191 => SH_CNT_MAX_BINARY <= "10111110"; when 192 => SH_CNT_MAX_BINARY <= "10111111"; when 193 => SH_CNT_MAX_BINARY <= "11000000"; when 194 => SH_CNT_MAX_BINARY <= "11000001"; when 195 => SH_CNT_MAX_BINARY <= "11000010"; when 196 => SH_CNT_MAX_BINARY <= "11000011"; when 197 => SH_CNT_MAX_BINARY <= "11000100"; when 198 => SH_CNT_MAX_BINARY <= "11000101"; when 199 => SH_CNT_MAX_BINARY <= "11000110"; when 200 => SH_CNT_MAX_BINARY <= "11000111"; when 201 => SH_CNT_MAX_BINARY <= "11001000"; when 202 => SH_CNT_MAX_BINARY <= "11001001"; when 203 => SH_CNT_MAX_BINARY <= "11001010"; when 204 => SH_CNT_MAX_BINARY <= "11001011"; when 205 => SH_CNT_MAX_BINARY <= "11001100"; when 206 => SH_CNT_MAX_BINARY <= "11001101"; when 207 => SH_CNT_MAX_BINARY <= "11001110"; when 208 => SH_CNT_MAX_BINARY <= "11001111"; when 209 => SH_CNT_MAX_BINARY <= "11010000"; when 210 => SH_CNT_MAX_BINARY <= "11010001"; when 211 => SH_CNT_MAX_BINARY <= "11010010"; when 212 => SH_CNT_MAX_BINARY <= "11010011"; when 213 => SH_CNT_MAX_BINARY <= "11010100"; when 214 => SH_CNT_MAX_BINARY <= "11010101"; when 215 => SH_CNT_MAX_BINARY <= "11010110"; when 216 => SH_CNT_MAX_BINARY <= "11010111"; when 217 => SH_CNT_MAX_BINARY <= "11011000"; when 218 => SH_CNT_MAX_BINARY <= "11011001"; when 219 => SH_CNT_MAX_BINARY <= "11011010"; when 220 => SH_CNT_MAX_BINARY <= "11011011"; when 221 => SH_CNT_MAX_BINARY <= "11011100"; when 222 => SH_CNT_MAX_BINARY <= "11011101"; when 223 => SH_CNT_MAX_BINARY <= "11011110"; when 224 => SH_CNT_MAX_BINARY <= "11011111"; when 225 => SH_CNT_MAX_BINARY <= "11100000"; when 226 => SH_CNT_MAX_BINARY <= "11100001"; when 227 => SH_CNT_MAX_BINARY <= "11100010"; when 228 => SH_CNT_MAX_BINARY <= "11100011"; when 229 => SH_CNT_MAX_BINARY <= "11100100"; when 230 => SH_CNT_MAX_BINARY <= "11100101"; when 231 => SH_CNT_MAX_BINARY <= "11100110"; when 232 => SH_CNT_MAX_BINARY <= "11100111"; when 233 => SH_CNT_MAX_BINARY <= "11101000"; when 234 => SH_CNT_MAX_BINARY <= "11101001"; when 235 => SH_CNT_MAX_BINARY <= "11101010"; when 236 => SH_CNT_MAX_BINARY <= "11101011"; when 237 => SH_CNT_MAX_BINARY <= "11101100"; when 238 => SH_CNT_MAX_BINARY <= "11101101"; when 239 => SH_CNT_MAX_BINARY <= "11101110"; when 240 => SH_CNT_MAX_BINARY <= "11101111"; when 241 => SH_CNT_MAX_BINARY <= "11110000"; when 242 => SH_CNT_MAX_BINARY <= "11110001"; when 243 => SH_CNT_MAX_BINARY <= "11110010"; when 244 => SH_CNT_MAX_BINARY <= "11110011"; when 245 => SH_CNT_MAX_BINARY <= "11110100"; when 246 => SH_CNT_MAX_BINARY <= "11110101"; when 247 => SH_CNT_MAX_BINARY <= "11110110"; when 248 => SH_CNT_MAX_BINARY <= "11110111"; when 249 => SH_CNT_MAX_BINARY <= "11111000"; when 250 => SH_CNT_MAX_BINARY <= "11111001"; when 251 => SH_CNT_MAX_BINARY <= "11111010"; when 252 => SH_CNT_MAX_BINARY <= "11111011"; when 253 => SH_CNT_MAX_BINARY <= "11111100"; when 254 => SH_CNT_MAX_BINARY <= "11111101"; when 255 => SH_CNT_MAX_BINARY <= "11111110"; when 256 => SH_CNT_MAX_BINARY <= "11111111"; when others => assert FALSE report "Error : SH_CNT_MAX is not in range 1...256." severity warning; end case; case SH_INVALID_CNT_MAX is when 1 => SH_INVALID_CNT_MAX_BINARY <= "00000000"; when 2 => SH_INVALID_CNT_MAX_BINARY <= "00000001"; when 3 => SH_INVALID_CNT_MAX_BINARY <= "00000010"; when 4 => SH_INVALID_CNT_MAX_BINARY <= "00000011"; when 5 => SH_INVALID_CNT_MAX_BINARY <= "00000100"; when 6 => SH_INVALID_CNT_MAX_BINARY <= "00000101"; when 7 => SH_INVALID_CNT_MAX_BINARY <= "00000110"; when 8 => SH_INVALID_CNT_MAX_BINARY <= "00000111"; when 9 => SH_INVALID_CNT_MAX_BINARY <= "00001000"; when 10 => SH_INVALID_CNT_MAX_BINARY <= "00001001"; when 11 => SH_INVALID_CNT_MAX_BINARY <= "00001010"; when 12 => SH_INVALID_CNT_MAX_BINARY <= "00001011"; when 13 => SH_INVALID_CNT_MAX_BINARY <= "00001100"; when 14 => SH_INVALID_CNT_MAX_BINARY <= "00001101"; when 15 => SH_INVALID_CNT_MAX_BINARY <= "00001110"; when 16 => SH_INVALID_CNT_MAX_BINARY <= "00001111"; when 17 => SH_INVALID_CNT_MAX_BINARY <= "00010000"; when 18 => SH_INVALID_CNT_MAX_BINARY <= "00010001"; when 19 => SH_INVALID_CNT_MAX_BINARY <= "00010010"; when 20 => SH_INVALID_CNT_MAX_BINARY <= "00010011"; when 21 => SH_INVALID_CNT_MAX_BINARY <= "00010100"; when 22 => SH_INVALID_CNT_MAX_BINARY <= "00010101"; when 23 => SH_INVALID_CNT_MAX_BINARY <= "00010110"; when 24 => SH_INVALID_CNT_MAX_BINARY <= "00010111"; when 25 => SH_INVALID_CNT_MAX_BINARY <= "00011000"; when 26 => SH_INVALID_CNT_MAX_BINARY <= "00011001"; when 27 => SH_INVALID_CNT_MAX_BINARY <= "00011010"; when 28 => SH_INVALID_CNT_MAX_BINARY <= "00011011"; when 29 => SH_INVALID_CNT_MAX_BINARY <= "00011100"; when 30 => SH_INVALID_CNT_MAX_BINARY <= "00011101"; when 31 => SH_INVALID_CNT_MAX_BINARY <= "00011110"; when 32 => SH_INVALID_CNT_MAX_BINARY <= "00011111"; when 33 => SH_INVALID_CNT_MAX_BINARY <= "00100000"; when 34 => SH_INVALID_CNT_MAX_BINARY <= "00100001"; when 35 => SH_INVALID_CNT_MAX_BINARY <= "00100010"; when 36 => SH_INVALID_CNT_MAX_BINARY <= "00100011"; when 37 => SH_INVALID_CNT_MAX_BINARY <= "00100100"; when 38 => SH_INVALID_CNT_MAX_BINARY <= "00100101"; when 39 => SH_INVALID_CNT_MAX_BINARY <= "00100110"; when 40 => SH_INVALID_CNT_MAX_BINARY <= "00100111"; when 41 => SH_INVALID_CNT_MAX_BINARY <= "00101000"; when 42 => SH_INVALID_CNT_MAX_BINARY <= "00101001"; when 43 => SH_INVALID_CNT_MAX_BINARY <= "00101010"; when 44 => SH_INVALID_CNT_MAX_BINARY <= "00101011"; when 45 => SH_INVALID_CNT_MAX_BINARY <= "00101100"; when 46 => SH_INVALID_CNT_MAX_BINARY <= "00101101"; when 47 => SH_INVALID_CNT_MAX_BINARY <= "00101110"; when 48 => SH_INVALID_CNT_MAX_BINARY <= "00101111"; when 49 => SH_INVALID_CNT_MAX_BINARY <= "00110000"; when 50 => SH_INVALID_CNT_MAX_BINARY <= "00110001"; when 51 => SH_INVALID_CNT_MAX_BINARY <= "00110010"; when 52 => SH_INVALID_CNT_MAX_BINARY <= "00110011"; when 53 => SH_INVALID_CNT_MAX_BINARY <= "00110100"; when 54 => SH_INVALID_CNT_MAX_BINARY <= "00110101"; when 55 => SH_INVALID_CNT_MAX_BINARY <= "00110110"; when 56 => SH_INVALID_CNT_MAX_BINARY <= "00110111"; when 57 => SH_INVALID_CNT_MAX_BINARY <= "00111000"; when 58 => SH_INVALID_CNT_MAX_BINARY <= "00111001"; when 59 => SH_INVALID_CNT_MAX_BINARY <= "00111010"; when 60 => SH_INVALID_CNT_MAX_BINARY <= "00111011"; when 61 => SH_INVALID_CNT_MAX_BINARY <= "00111100"; when 62 => SH_INVALID_CNT_MAX_BINARY <= "00111101"; when 63 => SH_INVALID_CNT_MAX_BINARY <= "00111110"; when 64 => SH_INVALID_CNT_MAX_BINARY <= "00111111"; when 65 => SH_INVALID_CNT_MAX_BINARY <= "01000000"; when 66 => SH_INVALID_CNT_MAX_BINARY <= "01000001"; when 67 => SH_INVALID_CNT_MAX_BINARY <= "01000010"; when 68 => SH_INVALID_CNT_MAX_BINARY <= "01000011"; when 69 => SH_INVALID_CNT_MAX_BINARY <= "01000100"; when 70 => SH_INVALID_CNT_MAX_BINARY <= "01000101"; when 71 => SH_INVALID_CNT_MAX_BINARY <= "01000110"; when 72 => SH_INVALID_CNT_MAX_BINARY <= "01000111"; when 73 => SH_INVALID_CNT_MAX_BINARY <= "01001000"; when 74 => SH_INVALID_CNT_MAX_BINARY <= "01001001"; when 75 => SH_INVALID_CNT_MAX_BINARY <= "01001010"; when 76 => SH_INVALID_CNT_MAX_BINARY <= "01001011"; when 77 => SH_INVALID_CNT_MAX_BINARY <= "01001100"; when 78 => SH_INVALID_CNT_MAX_BINARY <= "01001101"; when 79 => SH_INVALID_CNT_MAX_BINARY <= "01001110"; when 80 => SH_INVALID_CNT_MAX_BINARY <= "01001111"; when 81 => SH_INVALID_CNT_MAX_BINARY <= "01010000"; when 82 => SH_INVALID_CNT_MAX_BINARY <= "01010001"; when 83 => SH_INVALID_CNT_MAX_BINARY <= "01010010"; when 84 => SH_INVALID_CNT_MAX_BINARY <= "01010011"; when 85 => SH_INVALID_CNT_MAX_BINARY <= "01010100"; when 86 => SH_INVALID_CNT_MAX_BINARY <= "01010101"; when 87 => SH_INVALID_CNT_MAX_BINARY <= "01010110"; when 88 => SH_INVALID_CNT_MAX_BINARY <= "01010111"; when 89 => SH_INVALID_CNT_MAX_BINARY <= "01011000"; when 90 => SH_INVALID_CNT_MAX_BINARY <= "01011001"; when 91 => SH_INVALID_CNT_MAX_BINARY <= "01011010"; when 92 => SH_INVALID_CNT_MAX_BINARY <= "01011011"; when 93 => SH_INVALID_CNT_MAX_BINARY <= "01011100"; when 94 => SH_INVALID_CNT_MAX_BINARY <= "01011101"; when 95 => SH_INVALID_CNT_MAX_BINARY <= "01011110"; when 96 => SH_INVALID_CNT_MAX_BINARY <= "01011111"; when 97 => SH_INVALID_CNT_MAX_BINARY <= "01100000"; when 98 => SH_INVALID_CNT_MAX_BINARY <= "01100001"; when 99 => SH_INVALID_CNT_MAX_BINARY <= "01100010"; when 100 => SH_INVALID_CNT_MAX_BINARY <= "01100011"; when 101 => SH_INVALID_CNT_MAX_BINARY <= "01100100"; when 102 => SH_INVALID_CNT_MAX_BINARY <= "01100101"; when 103 => SH_INVALID_CNT_MAX_BINARY <= "01100110"; when 104 => SH_INVALID_CNT_MAX_BINARY <= "01100111"; when 105 => SH_INVALID_CNT_MAX_BINARY <= "01101000"; when 106 => SH_INVALID_CNT_MAX_BINARY <= "01101001"; when 107 => SH_INVALID_CNT_MAX_BINARY <= "01101010"; when 108 => SH_INVALID_CNT_MAX_BINARY <= "01101011"; when 109 => SH_INVALID_CNT_MAX_BINARY <= "01101100"; when 110 => SH_INVALID_CNT_MAX_BINARY <= "01101101"; when 111 => SH_INVALID_CNT_MAX_BINARY <= "01101110"; when 112 => SH_INVALID_CNT_MAX_BINARY <= "01101111"; when 113 => SH_INVALID_CNT_MAX_BINARY <= "01110000"; when 114 => SH_INVALID_CNT_MAX_BINARY <= "01110001"; when 115 => SH_INVALID_CNT_MAX_BINARY <= "01110010"; when 116 => SH_INVALID_CNT_MAX_BINARY <= "01110011"; when 117 => SH_INVALID_CNT_MAX_BINARY <= "01110100"; when 118 => SH_INVALID_CNT_MAX_BINARY <= "01110101"; when 119 => SH_INVALID_CNT_MAX_BINARY <= "01110110"; when 120 => SH_INVALID_CNT_MAX_BINARY <= "01110111"; when 121 => SH_INVALID_CNT_MAX_BINARY <= "01111000"; when 122 => SH_INVALID_CNT_MAX_BINARY <= "01111001"; when 123 => SH_INVALID_CNT_MAX_BINARY <= "01111010"; when 124 => SH_INVALID_CNT_MAX_BINARY <= "01111011"; when 125 => SH_INVALID_CNT_MAX_BINARY <= "01111100"; when 126 => SH_INVALID_CNT_MAX_BINARY <= "01111101"; when 127 => SH_INVALID_CNT_MAX_BINARY <= "01111110"; when 128 => SH_INVALID_CNT_MAX_BINARY <= "01111111"; when 129 => SH_INVALID_CNT_MAX_BINARY <= "10000000"; when 130 => SH_INVALID_CNT_MAX_BINARY <= "10000001"; when 131 => SH_INVALID_CNT_MAX_BINARY <= "10000010"; when 132 => SH_INVALID_CNT_MAX_BINARY <= "10000011"; when 133 => SH_INVALID_CNT_MAX_BINARY <= "10000100"; when 134 => SH_INVALID_CNT_MAX_BINARY <= "10000101"; when 135 => SH_INVALID_CNT_MAX_BINARY <= "10000110"; when 136 => SH_INVALID_CNT_MAX_BINARY <= "10000111"; when 137 => SH_INVALID_CNT_MAX_BINARY <= "10001000"; when 138 => SH_INVALID_CNT_MAX_BINARY <= "10001001"; when 139 => SH_INVALID_CNT_MAX_BINARY <= "10001010"; when 140 => SH_INVALID_CNT_MAX_BINARY <= "10001011"; when 141 => SH_INVALID_CNT_MAX_BINARY <= "10001100"; when 142 => SH_INVALID_CNT_MAX_BINARY <= "10001101"; when 143 => SH_INVALID_CNT_MAX_BINARY <= "10001110"; when 144 => SH_INVALID_CNT_MAX_BINARY <= "10001111"; when 145 => SH_INVALID_CNT_MAX_BINARY <= "10010000"; when 146 => SH_INVALID_CNT_MAX_BINARY <= "10010001"; when 147 => SH_INVALID_CNT_MAX_BINARY <= "10010010"; when 148 => SH_INVALID_CNT_MAX_BINARY <= "10010011"; when 149 => SH_INVALID_CNT_MAX_BINARY <= "10010100"; when 150 => SH_INVALID_CNT_MAX_BINARY <= "10010101"; when 151 => SH_INVALID_CNT_MAX_BINARY <= "10010110"; when 152 => SH_INVALID_CNT_MAX_BINARY <= "10010111"; when 153 => SH_INVALID_CNT_MAX_BINARY <= "10011000"; when 154 => SH_INVALID_CNT_MAX_BINARY <= "10011001"; when 155 => SH_INVALID_CNT_MAX_BINARY <= "10011010"; when 156 => SH_INVALID_CNT_MAX_BINARY <= "10011011"; when 157 => SH_INVALID_CNT_MAX_BINARY <= "10011100"; when 158 => SH_INVALID_CNT_MAX_BINARY <= "10011101"; when 159 => SH_INVALID_CNT_MAX_BINARY <= "10011110"; when 160 => SH_INVALID_CNT_MAX_BINARY <= "10011111"; when 161 => SH_INVALID_CNT_MAX_BINARY <= "10100000"; when 162 => SH_INVALID_CNT_MAX_BINARY <= "10100001"; when 163 => SH_INVALID_CNT_MAX_BINARY <= "10100010"; when 164 => SH_INVALID_CNT_MAX_BINARY <= "10100011"; when 165 => SH_INVALID_CNT_MAX_BINARY <= "10100100"; when 166 => SH_INVALID_CNT_MAX_BINARY <= "10100101"; when 167 => SH_INVALID_CNT_MAX_BINARY <= "10100110"; when 168 => SH_INVALID_CNT_MAX_BINARY <= "10100111"; when 169 => SH_INVALID_CNT_MAX_BINARY <= "10101000"; when 170 => SH_INVALID_CNT_MAX_BINARY <= "10101001"; when 171 => SH_INVALID_CNT_MAX_BINARY <= "10101010"; when 172 => SH_INVALID_CNT_MAX_BINARY <= "10101011"; when 173 => SH_INVALID_CNT_MAX_BINARY <= "10101100"; when 174 => SH_INVALID_CNT_MAX_BINARY <= "10101101"; when 175 => SH_INVALID_CNT_MAX_BINARY <= "10101110"; when 176 => SH_INVALID_CNT_MAX_BINARY <= "10101111"; when 177 => SH_INVALID_CNT_MAX_BINARY <= "10110000"; when 178 => SH_INVALID_CNT_MAX_BINARY <= "10110001"; when 179 => SH_INVALID_CNT_MAX_BINARY <= "10110010"; when 180 => SH_INVALID_CNT_MAX_BINARY <= "10110011"; when 181 => SH_INVALID_CNT_MAX_BINARY <= "10110100"; when 182 => SH_INVALID_CNT_MAX_BINARY <= "10110101"; when 183 => SH_INVALID_CNT_MAX_BINARY <= "10110110"; when 184 => SH_INVALID_CNT_MAX_BINARY <= "10110111"; when 185 => SH_INVALID_CNT_MAX_BINARY <= "10111000"; when 186 => SH_INVALID_CNT_MAX_BINARY <= "10111001"; when 187 => SH_INVALID_CNT_MAX_BINARY <= "10111010"; when 188 => SH_INVALID_CNT_MAX_BINARY <= "10111011"; when 189 => SH_INVALID_CNT_MAX_BINARY <= "10111100"; when 190 => SH_INVALID_CNT_MAX_BINARY <= "10111101"; when 191 => SH_INVALID_CNT_MAX_BINARY <= "10111110"; when 192 => SH_INVALID_CNT_MAX_BINARY <= "10111111"; when 193 => SH_INVALID_CNT_MAX_BINARY <= "11000000"; when 194 => SH_INVALID_CNT_MAX_BINARY <= "11000001"; when 195 => SH_INVALID_CNT_MAX_BINARY <= "11000010"; when 196 => SH_INVALID_CNT_MAX_BINARY <= "11000011"; when 197 => SH_INVALID_CNT_MAX_BINARY <= "11000100"; when 198 => SH_INVALID_CNT_MAX_BINARY <= "11000101"; when 199 => SH_INVALID_CNT_MAX_BINARY <= "11000110"; when 200 => SH_INVALID_CNT_MAX_BINARY <= "11000111"; when 201 => SH_INVALID_CNT_MAX_BINARY <= "11001000"; when 202 => SH_INVALID_CNT_MAX_BINARY <= "11001001"; when 203 => SH_INVALID_CNT_MAX_BINARY <= "11001010"; when 204 => SH_INVALID_CNT_MAX_BINARY <= "11001011"; when 205 => SH_INVALID_CNT_MAX_BINARY <= "11001100"; when 206 => SH_INVALID_CNT_MAX_BINARY <= "11001101"; when 207 => SH_INVALID_CNT_MAX_BINARY <= "11001110"; when 208 => SH_INVALID_CNT_MAX_BINARY <= "11001111"; when 209 => SH_INVALID_CNT_MAX_BINARY <= "11010000"; when 210 => SH_INVALID_CNT_MAX_BINARY <= "11010001"; when 211 => SH_INVALID_CNT_MAX_BINARY <= "11010010"; when 212 => SH_INVALID_CNT_MAX_BINARY <= "11010011"; when 213 => SH_INVALID_CNT_MAX_BINARY <= "11010100"; when 214 => SH_INVALID_CNT_MAX_BINARY <= "11010101"; when 215 => SH_INVALID_CNT_MAX_BINARY <= "11010110"; when 216 => SH_INVALID_CNT_MAX_BINARY <= "11010111"; when 217 => SH_INVALID_CNT_MAX_BINARY <= "11011000"; when 218 => SH_INVALID_CNT_MAX_BINARY <= "11011001"; when 219 => SH_INVALID_CNT_MAX_BINARY <= "11011010"; when 220 => SH_INVALID_CNT_MAX_BINARY <= "11011011"; when 221 => SH_INVALID_CNT_MAX_BINARY <= "11011100"; when 222 => SH_INVALID_CNT_MAX_BINARY <= "11011101"; when 223 => SH_INVALID_CNT_MAX_BINARY <= "11011110"; when 224 => SH_INVALID_CNT_MAX_BINARY <= "11011111"; when 225 => SH_INVALID_CNT_MAX_BINARY <= "11100000"; when 226 => SH_INVALID_CNT_MAX_BINARY <= "11100001"; when 227 => SH_INVALID_CNT_MAX_BINARY <= "11100010"; when 228 => SH_INVALID_CNT_MAX_BINARY <= "11100011"; when 229 => SH_INVALID_CNT_MAX_BINARY <= "11100100"; when 230 => SH_INVALID_CNT_MAX_BINARY <= "11100101"; when 231 => SH_INVALID_CNT_MAX_BINARY <= "11100110"; when 232 => SH_INVALID_CNT_MAX_BINARY <= "11100111"; when 233 => SH_INVALID_CNT_MAX_BINARY <= "11101000"; when 234 => SH_INVALID_CNT_MAX_BINARY <= "11101001"; when 235 => SH_INVALID_CNT_MAX_BINARY <= "11101010"; when 236 => SH_INVALID_CNT_MAX_BINARY <= "11101011"; when 237 => SH_INVALID_CNT_MAX_BINARY <= "11101100"; when 238 => SH_INVALID_CNT_MAX_BINARY <= "11101101"; when 239 => SH_INVALID_CNT_MAX_BINARY <= "11101110"; when 240 => SH_INVALID_CNT_MAX_BINARY <= "11101111"; when 241 => SH_INVALID_CNT_MAX_BINARY <= "11110000"; when 242 => SH_INVALID_CNT_MAX_BINARY <= "11110001"; when 243 => SH_INVALID_CNT_MAX_BINARY <= "11110010"; when 244 => SH_INVALID_CNT_MAX_BINARY <= "11110011"; when 245 => SH_INVALID_CNT_MAX_BINARY <= "11110100"; when 246 => SH_INVALID_CNT_MAX_BINARY <= "11110101"; when 247 => SH_INVALID_CNT_MAX_BINARY <= "11110110"; when 248 => SH_INVALID_CNT_MAX_BINARY <= "11110111"; when 249 => SH_INVALID_CNT_MAX_BINARY <= "11111000"; when 250 => SH_INVALID_CNT_MAX_BINARY <= "11111001"; when 251 => SH_INVALID_CNT_MAX_BINARY <= "11111010"; when 252 => SH_INVALID_CNT_MAX_BINARY <= "11111011"; when 253 => SH_INVALID_CNT_MAX_BINARY <= "11111100"; when 254 => SH_INVALID_CNT_MAX_BINARY <= "11111101"; when 255 => SH_INVALID_CNT_MAX_BINARY <= "11111110"; when 256 => SH_INVALID_CNT_MAX_BINARY <= "11111111"; when others => assert FALSE report "Error : SH_INVALID_CNT_MAX is not in range 1...256." severity warning; end case; case TX_BUFFER_USE is when FALSE => TX_BUFFER_USE_BINARY <= '0'; when TRUE => TX_BUFFER_USE_BINARY <= '1'; when others => assert FALSE report "Error : TX_BUFFER_USE is neither TRUE nor FALSE." severity warning; end case; wait; end process INIPROC; TIMING : process -- Pin timing violations (clock input pins) -- Pin Timing Violations (all input pins) -- Output Pin glitch declaration variable CHBONDDONE_GlitchData : VitalGlitchDataType; variable CHBONDO0_GlitchData : VitalGlitchDataType; variable CHBONDO1_GlitchData : VitalGlitchDataType; variable CHBONDO2_GlitchData : VitalGlitchDataType; variable CHBONDO3_GlitchData : VitalGlitchDataType; variable CHBONDO4_GlitchData : VitalGlitchDataType; variable PMARXLOCK_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS0_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS1_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA0_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA1_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA2_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA3_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA4_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA5_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA6_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA7_GlitchData : VitalGlitchDataType; variable RXCHARISK0_GlitchData : VitalGlitchDataType; variable RXCHARISK1_GlitchData : VitalGlitchDataType; variable RXCHARISK2_GlitchData : VitalGlitchDataType; variable RXCHARISK3_GlitchData : VitalGlitchDataType; variable RXCHARISK4_GlitchData : VitalGlitchDataType; variable RXCHARISK5_GlitchData : VitalGlitchDataType; variable RXCHARISK6_GlitchData : VitalGlitchDataType; variable RXCHARISK7_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT0_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT1_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT2_GlitchData : VitalGlitchDataType; variable RXCOMMADET_GlitchData : VitalGlitchDataType; variable RXDATA0_GlitchData : VitalGlitchDataType; variable RXDATA1_GlitchData : VitalGlitchDataType; variable RXDATA2_GlitchData : VitalGlitchDataType; variable RXDATA3_GlitchData : VitalGlitchDataType; variable RXDATA4_GlitchData : VitalGlitchDataType; variable RXDATA5_GlitchData : VitalGlitchDataType; variable RXDATA6_GlitchData : VitalGlitchDataType; variable RXDATA7_GlitchData : VitalGlitchDataType; variable RXDATA8_GlitchData : VitalGlitchDataType; variable RXDATA9_GlitchData : VitalGlitchDataType; variable RXDATA10_GlitchData : VitalGlitchDataType; variable RXDATA11_GlitchData : VitalGlitchDataType; variable RXDATA12_GlitchData : VitalGlitchDataType; variable RXDATA13_GlitchData : VitalGlitchDataType; variable RXDATA14_GlitchData : VitalGlitchDataType; variable RXDATA15_GlitchData : VitalGlitchDataType; variable RXDATA16_GlitchData : VitalGlitchDataType; variable RXDATA17_GlitchData : VitalGlitchDataType; variable RXDATA18_GlitchData : VitalGlitchDataType; variable RXDATA19_GlitchData : VitalGlitchDataType; variable RXDATA20_GlitchData : VitalGlitchDataType; variable RXDATA21_GlitchData : VitalGlitchDataType; variable RXDATA22_GlitchData : VitalGlitchDataType; variable RXDATA23_GlitchData : VitalGlitchDataType; variable RXDATA24_GlitchData : VitalGlitchDataType; variable RXDATA25_GlitchData : VitalGlitchDataType; variable RXDATA26_GlitchData : VitalGlitchDataType; variable RXDATA27_GlitchData : VitalGlitchDataType; variable RXDATA28_GlitchData : VitalGlitchDataType; variable RXDATA29_GlitchData : VitalGlitchDataType; variable RXDATA30_GlitchData : VitalGlitchDataType; variable RXDATA31_GlitchData : VitalGlitchDataType; variable RXDATA32_GlitchData : VitalGlitchDataType; variable RXDATA33_GlitchData : VitalGlitchDataType; variable RXDATA34_GlitchData : VitalGlitchDataType; variable RXDATA35_GlitchData : VitalGlitchDataType; variable RXDATA36_GlitchData : VitalGlitchDataType; variable RXDATA37_GlitchData : VitalGlitchDataType; variable RXDATA38_GlitchData : VitalGlitchDataType; variable RXDATA39_GlitchData : VitalGlitchDataType; variable RXDATA40_GlitchData : VitalGlitchDataType; variable RXDATA41_GlitchData : VitalGlitchDataType; variable RXDATA42_GlitchData : VitalGlitchDataType; variable RXDATA43_GlitchData : VitalGlitchDataType; variable RXDATA44_GlitchData : VitalGlitchDataType; variable RXDATA45_GlitchData : VitalGlitchDataType; variable RXDATA46_GlitchData : VitalGlitchDataType; variable RXDATA47_GlitchData : VitalGlitchDataType; variable RXDATA48_GlitchData : VitalGlitchDataType; variable RXDATA49_GlitchData : VitalGlitchDataType; variable RXDATA50_GlitchData : VitalGlitchDataType; variable RXDATA51_GlitchData : VitalGlitchDataType; variable RXDATA52_GlitchData : VitalGlitchDataType; variable RXDATA53_GlitchData : VitalGlitchDataType; variable RXDATA54_GlitchData : VitalGlitchDataType; variable RXDATA55_GlitchData : VitalGlitchDataType; variable RXDATA56_GlitchData : VitalGlitchDataType; variable RXDATA57_GlitchData : VitalGlitchDataType; variable RXDATA58_GlitchData : VitalGlitchDataType; variable RXDATA59_GlitchData : VitalGlitchDataType; variable RXDATA60_GlitchData : VitalGlitchDataType; variable RXDATA61_GlitchData : VitalGlitchDataType; variable RXDATA62_GlitchData : VitalGlitchDataType; variable RXDATA63_GlitchData : VitalGlitchDataType; variable RXDISPERR0_GlitchData : VitalGlitchDataType; variable RXDISPERR1_GlitchData : VitalGlitchDataType; variable RXDISPERR2_GlitchData : VitalGlitchDataType; variable RXDISPERR3_GlitchData : VitalGlitchDataType; variable RXDISPERR4_GlitchData : VitalGlitchDataType; variable RXDISPERR5_GlitchData : VitalGlitchDataType; variable RXDISPERR6_GlitchData : VitalGlitchDataType; variable RXDISPERR7_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC0_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC1_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE0_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE1_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE2_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE3_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE4_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE5_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE6_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE7_GlitchData : VitalGlitchDataType; variable RXREALIGN_GlitchData : VitalGlitchDataType; -- variable RXRECCLK_GlitchData : VitalGlitchDataType; variable RXRUNDISP0_GlitchData : VitalGlitchDataType; variable RXRUNDISP1_GlitchData : VitalGlitchDataType; variable RXRUNDISP2_GlitchData : VitalGlitchDataType; variable RXRUNDISP3_GlitchData : VitalGlitchDataType; variable RXRUNDISP4_GlitchData : VitalGlitchDataType; variable RXRUNDISP5_GlitchData : VitalGlitchDataType; variable RXRUNDISP6_GlitchData : VitalGlitchDataType; variable RXRUNDISP7_GlitchData : VitalGlitchDataType; variable TXBUFERR_GlitchData : VitalGlitchDataType; variable TXKERR0_GlitchData : VitalGlitchDataType; variable TXKERR1_GlitchData : VitalGlitchDataType; variable TXKERR2_GlitchData : VitalGlitchDataType; variable TXKERR3_GlitchData : VitalGlitchDataType; variable TXKERR4_GlitchData : VitalGlitchDataType; variable TXKERR5_GlitchData : VitalGlitchDataType; variable TXKERR6_GlitchData : VitalGlitchDataType; variable TXKERR7_GlitchData : VitalGlitchDataType; -- variable TXN_GlitchData : VitalGlitchDataType; -- variable TXOUTCLK_GlitchData : VitalGlitchDataType; -- variable TXP_GlitchData : VitalGlitchDataType; variable TXRUNDISP0_GlitchData : VitalGlitchDataType; variable TXRUNDISP1_GlitchData : VitalGlitchDataType; variable TXRUNDISP2_GlitchData : VitalGlitchDataType; variable TXRUNDISP3_GlitchData : VitalGlitchDataType; variable TXRUNDISP4_GlitchData : VitalGlitchDataType; variable TXRUNDISP5_GlitchData : VitalGlitchDataType; variable TXRUNDISP6_GlitchData : VitalGlitchDataType; variable TXRUNDISP7_GlitchData : VitalGlitchDataType; begin -- Setup/Hold Check Violations (all input pins) -- End of (TimingChecksOn) -- Output-to-Clock path delay VitalPathDelay01 ( OutSignal => CHBONDDONE, GlitchData => CHBONDDONE_GlitchData, OutSignalName => "CHBONDDONE", OutTemp => CHBONDDONE_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(0), GlitchData => CHBONDO0_GlitchData, OutSignalName => "CHBONDO(0)", OutTemp => CHBONDO_OUT(0), Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(1), GlitchData => CHBONDO1_GlitchData, OutSignalName => "CHBONDO(1)", OutTemp => CHBONDO_OUT(1), Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(2), GlitchData => CHBONDO2_GlitchData, OutSignalName => "CHBONDO(2)", OutTemp => CHBONDO_OUT(2), Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(3), GlitchData => CHBONDO3_GlitchData, OutSignalName => "CHBONDO(3)", OutTemp => CHBONDO_OUT(3), Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(4), GlitchData => CHBONDO4_GlitchData, OutSignalName => "CHBONDO(4)", OutTemp => CHBONDO_OUT(4), Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS(0), GlitchData => RXBUFSTATUS0_GlitchData, OutSignalName => "RXBUFSTATUS(0)", OutTemp => RXBUFSTATUS_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS(1), GlitchData => RXBUFSTATUS1_GlitchData, OutSignalName => "RXBUFSTATUS(1)", OutTemp => RXBUFSTATUS_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(0), GlitchData => RXCHARISCOMMA0_GlitchData, OutSignalName => "RXCHARISCOMMA(0)", OutTemp => RXCHARISCOMMA_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(1), GlitchData => RXCHARISCOMMA1_GlitchData, OutSignalName => "RXCHARISCOMMA(1)", OutTemp => RXCHARISCOMMA_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(2), GlitchData => RXCHARISCOMMA2_GlitchData, OutSignalName => "RXCHARISCOMMA(2)", OutTemp => RXCHARISCOMMA_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(3), GlitchData => RXCHARISCOMMA3_GlitchData, OutSignalName => "RXCHARISCOMMA(3)", OutTemp => RXCHARISCOMMA_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(4), GlitchData => RXCHARISCOMMA4_GlitchData, OutSignalName => "RXCHARISCOMMA(4)", OutTemp => RXCHARISCOMMA_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(5), GlitchData => RXCHARISCOMMA5_GlitchData, OutSignalName => "RXCHARISCOMMA(5)", OutTemp => RXCHARISCOMMA_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(6), GlitchData => RXCHARISCOMMA6_GlitchData, OutSignalName => "RXCHARISCOMMA(6)", OutTemp => RXCHARISCOMMA_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(7), GlitchData => RXCHARISCOMMA7_GlitchData, OutSignalName => "RXCHARISCOMMA(7)", OutTemp => RXCHARISCOMMA_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(0), GlitchData => RXCHARISK0_GlitchData, OutSignalName => "RXCHARISK(0)", OutTemp => RXCHARISK_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(1), GlitchData => RXCHARISK1_GlitchData, OutSignalName => "RXCHARISK(1)", OutTemp => RXCHARISK_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(2), GlitchData => RXCHARISK2_GlitchData, OutSignalName => "RXCHARISK(2)", OutTemp => RXCHARISK_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(3), GlitchData => RXCHARISK3_GlitchData, OutSignalName => "RXCHARISK(3)", OutTemp => RXCHARISK_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(4), GlitchData => RXCHARISK4_GlitchData, OutSignalName => "RXCHARISK(4)", OutTemp => RXCHARISK_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(5), GlitchData => RXCHARISK5_GlitchData, OutSignalName => "RXCHARISK(5)", OutTemp => RXCHARISK_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(6), GlitchData => RXCHARISK6_GlitchData, OutSignalName => "RXCHARISK(6)", OutTemp => RXCHARISK_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(7), GlitchData => RXCHARISK7_GlitchData, OutSignalName => "RXCHARISK(7)", OutTemp => RXCHARISK_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT(0), GlitchData => RXCLKCORCNT0_GlitchData, OutSignalName => "RXCLKCORCNT(0)", OutTemp => RXCLKCORCNT_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT(1), GlitchData => RXCLKCORCNT1_GlitchData, OutSignalName => "RXCLKCORCNT(1)", OutTemp => RXCLKCORCNT_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT(2), GlitchData => RXCLKCORCNT2_GlitchData, OutSignalName => "RXCLKCORCNT(2)", OutTemp => RXCLKCORCNT_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCOMMADET, GlitchData => RXCOMMADET_GlitchData, OutSignalName => "RXCOMMADET", OutTemp => RXCOMMADET_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(0), GlitchData => RXDATA0_GlitchData, OutSignalName => "RXDATA(0)", OutTemp => RXDATA_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(1), GlitchData => RXDATA1_GlitchData, OutSignalName => "RXDATA(1)", OutTemp => RXDATA_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(2), GlitchData => RXDATA2_GlitchData, OutSignalName => "RXDATA(2)", OutTemp => RXDATA_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(3), GlitchData => RXDATA3_GlitchData, OutSignalName => "RXDATA(3)", OutTemp => RXDATA_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(4), GlitchData => RXDATA4_GlitchData, OutSignalName => "RXDATA(4)", OutTemp => RXDATA_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(5), GlitchData => RXDATA5_GlitchData, OutSignalName => "RXDATA(5)", OutTemp => RXDATA_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(6), GlitchData => RXDATA6_GlitchData, OutSignalName => "RXDATA(6)", OutTemp => RXDATA_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(7), GlitchData => RXDATA7_GlitchData, OutSignalName => "RXDATA(7)", OutTemp => RXDATA_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(8), GlitchData => RXDATA8_GlitchData, OutSignalName => "RXDATA(8)", OutTemp => RXDATA_OUT(8), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(9), GlitchData => RXDATA9_GlitchData, OutSignalName => "RXDATA(9)", OutTemp => RXDATA_OUT(9), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(10), GlitchData => RXDATA10_GlitchData, OutSignalName => "RXDATA(10)", OutTemp => RXDATA_OUT(10), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(11), GlitchData => RXDATA11_GlitchData, OutSignalName => "RXDATA(11)", OutTemp => RXDATA_OUT(11), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(12), GlitchData => RXDATA12_GlitchData, OutSignalName => "RXDATA(12)", OutTemp => RXDATA_OUT(12), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(13), GlitchData => RXDATA13_GlitchData, OutSignalName => "RXDATA(13)", OutTemp => RXDATA_OUT(13), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(14), GlitchData => RXDATA14_GlitchData, OutSignalName => "RXDATA(14)", OutTemp => RXDATA_OUT(14), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(15), GlitchData => RXDATA15_GlitchData, OutSignalName => "RXDATA(15)", OutTemp => RXDATA_OUT(15), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(16), GlitchData => RXDATA16_GlitchData, OutSignalName => "RXDATA(16)", OutTemp => RXDATA_OUT(16), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(17), GlitchData => RXDATA17_GlitchData, OutSignalName => "RXDATA(17)", OutTemp => RXDATA_OUT(17), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(18), GlitchData => RXDATA18_GlitchData, OutSignalName => "RXDATA(18)", OutTemp => RXDATA_OUT(18), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(19), GlitchData => RXDATA19_GlitchData, OutSignalName => "RXDATA(19)", OutTemp => RXDATA_OUT(19), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(20), GlitchData => RXDATA20_GlitchData, OutSignalName => "RXDATA(20)", OutTemp => RXDATA_OUT(20), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(21), GlitchData => RXDATA21_GlitchData, OutSignalName => "RXDATA(21)", OutTemp => RXDATA_OUT(21), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(22), GlitchData => RXDATA22_GlitchData, OutSignalName => "RXDATA(22)", OutTemp => RXDATA_OUT(22), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(23), GlitchData => RXDATA23_GlitchData, OutSignalName => "RXDATA(23)", OutTemp => RXDATA_OUT(23), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(24), GlitchData => RXDATA24_GlitchData, OutSignalName => "RXDATA(24)", OutTemp => RXDATA_OUT(24), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(25), GlitchData => RXDATA25_GlitchData, OutSignalName => "RXDATA(25)", OutTemp => RXDATA_OUT(25), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(26), GlitchData => RXDATA26_GlitchData, OutSignalName => "RXDATA(26)", OutTemp => RXDATA_OUT(26), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(27), GlitchData => RXDATA27_GlitchData, OutSignalName => "RXDATA(27)", OutTemp => RXDATA_OUT(27), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(28), GlitchData => RXDATA28_GlitchData, OutSignalName => "RXDATA(28)", OutTemp => RXDATA_OUT(28), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(29), GlitchData => RXDATA29_GlitchData, OutSignalName => "RXDATA(29)", OutTemp => RXDATA_OUT(29), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(30), GlitchData => RXDATA30_GlitchData, OutSignalName => "RXDATA(30)", OutTemp => RXDATA_OUT(30), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(31), GlitchData => RXDATA31_GlitchData, OutSignalName => "RXDATA(31)", OutTemp => RXDATA_OUT(31), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(32), GlitchData => RXDATA32_GlitchData, OutSignalName => "RXDATA(32)", OutTemp => RXDATA_OUT(32), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(33), GlitchData => RXDATA33_GlitchData, OutSignalName => "RXDATA(33)", OutTemp => RXDATA_OUT(33), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(34), GlitchData => RXDATA34_GlitchData, OutSignalName => "RXDATA(34)", OutTemp => RXDATA_OUT(34), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(35), GlitchData => RXDATA35_GlitchData, OutSignalName => "RXDATA(35)", OutTemp => RXDATA_OUT(35), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(36), GlitchData => RXDATA36_GlitchData, OutSignalName => "RXDATA(36)", OutTemp => RXDATA_OUT(36), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(37), GlitchData => RXDATA37_GlitchData, OutSignalName => "RXDATA(37)", OutTemp => RXDATA_OUT(37), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(38), GlitchData => RXDATA38_GlitchData, OutSignalName => "RXDATA(38)", OutTemp => RXDATA_OUT(38), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(39), GlitchData => RXDATA39_GlitchData, OutSignalName => "RXDATA(39)", OutTemp => RXDATA_OUT(39), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(40), GlitchData => RXDATA40_GlitchData, OutSignalName => "RXDATA(40)", OutTemp => RXDATA_OUT(40), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(41), GlitchData => RXDATA41_GlitchData, OutSignalName => "RXDATA(41)", OutTemp => RXDATA_OUT(41), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(42), GlitchData => RXDATA42_GlitchData, OutSignalName => "RXDATA(42)", OutTemp => RXDATA_OUT(42), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(43), GlitchData => RXDATA43_GlitchData, OutSignalName => "RXDATA(43)", OutTemp => RXDATA_OUT(43), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(44), GlitchData => RXDATA44_GlitchData, OutSignalName => "RXDATA(44)", OutTemp => RXDATA_OUT(44), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(45), GlitchData => RXDATA45_GlitchData, OutSignalName => "RXDATA(45)", OutTemp => RXDATA_OUT(45), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(46), GlitchData => RXDATA46_GlitchData, OutSignalName => "RXDATA(46)", OutTemp => RXDATA_OUT(46), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(47), GlitchData => RXDATA47_GlitchData, OutSignalName => "RXDATA(47)", OutTemp => RXDATA_OUT(47), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(48), GlitchData => RXDATA48_GlitchData, OutSignalName => "RXDATA(48)", OutTemp => RXDATA_OUT(48), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(49), GlitchData => RXDATA49_GlitchData, OutSignalName => "RXDATA(49)", OutTemp => RXDATA_OUT(49), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(50), GlitchData => RXDATA50_GlitchData, OutSignalName => "RXDATA(50)", OutTemp => RXDATA_OUT(50), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(51), GlitchData => RXDATA51_GlitchData, OutSignalName => "RXDATA(51)", OutTemp => RXDATA_OUT(51), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(52), GlitchData => RXDATA52_GlitchData, OutSignalName => "RXDATA(52)", OutTemp => RXDATA_OUT(52), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(53), GlitchData => RXDATA53_GlitchData, OutSignalName => "RXDATA(53)", OutTemp => RXDATA_OUT(53), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(54), GlitchData => RXDATA54_GlitchData, OutSignalName => "RXDATA(54)", OutTemp => RXDATA_OUT(54), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(55), GlitchData => RXDATA55_GlitchData, OutSignalName => "RXDATA(55)", OutTemp => RXDATA_OUT(55), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(56), GlitchData => RXDATA56_GlitchData, OutSignalName => "RXDATA(56)", OutTemp => RXDATA_OUT(56), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(57), GlitchData => RXDATA57_GlitchData, OutSignalName => "RXDATA(57)", OutTemp => RXDATA_OUT(57), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(58), GlitchData => RXDATA58_GlitchData, OutSignalName => "RXDATA(58)", OutTemp => RXDATA_OUT(58), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(59), GlitchData => RXDATA59_GlitchData, OutSignalName => "RXDATA(59)", OutTemp => RXDATA_OUT(59), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(60), GlitchData => RXDATA60_GlitchData, OutSignalName => "RXDATA(60)", OutTemp => RXDATA_OUT(60), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(61), GlitchData => RXDATA61_GlitchData, OutSignalName => "RXDATA(61)", OutTemp => RXDATA_OUT(61), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(62), GlitchData => RXDATA62_GlitchData, OutSignalName => "RXDATA(62)", OutTemp => RXDATA_OUT(62), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(63), GlitchData => RXDATA63_GlitchData, OutSignalName => "RXDATA(63)", OutTemp => RXDATA_OUT(63), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(0), GlitchData => RXDISPERR0_GlitchData, OutSignalName => "RXDISPERR(0)", OutTemp => RXDISPERR_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(1), GlitchData => RXDISPERR1_GlitchData, OutSignalName => "RXDISPERR(1)", OutTemp => RXDISPERR_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(2), GlitchData => RXDISPERR2_GlitchData, OutSignalName => "RXDISPERR(2)", OutTemp => RXDISPERR_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(3), GlitchData => RXDISPERR3_GlitchData, OutSignalName => "RXDISPERR(3)", OutTemp => RXDISPERR_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(4), GlitchData => RXDISPERR4_GlitchData, OutSignalName => "RXDISPERR(4)", OutTemp => RXDISPERR_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(5), GlitchData => RXDISPERR5_GlitchData, OutSignalName => "RXDISPERR(5)", OutTemp => RXDISPERR_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(6), GlitchData => RXDISPERR6_GlitchData, OutSignalName => "RXDISPERR(6)", OutTemp => RXDISPERR_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(7), GlitchData => RXDISPERR7_GlitchData, OutSignalName => "RXDISPERR(7)", OutTemp => RXDISPERR_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC(0), GlitchData => RXLOSSOFSYNC0_GlitchData, OutSignalName => "RXLOSSOFSYNC(0)", OutTemp => RXLOSSOFSYNC_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC(1), GlitchData => RXLOSSOFSYNC1_GlitchData, OutSignalName => "RXLOSSOFSYNC(1)", OutTemp => RXLOSSOFSYNC_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(0), GlitchData => RXNOTINTABLE0_GlitchData, OutSignalName => "RXNOTINTABLE(0)", OutTemp => RXNOTINTABLE_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(1), GlitchData => RXNOTINTABLE1_GlitchData, OutSignalName => "RXNOTINTABLE(1)", OutTemp => RXNOTINTABLE_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(2), GlitchData => RXNOTINTABLE2_GlitchData, OutSignalName => "RXNOTINTABLE(2)", OutTemp => RXNOTINTABLE_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(3), GlitchData => RXNOTINTABLE3_GlitchData, OutSignalName => "RXNOTINTABLE(3)", OutTemp => RXNOTINTABLE_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(4), GlitchData => RXNOTINTABLE4_GlitchData, OutSignalName => "RXNOTINTABLE(4)", OutTemp => RXNOTINTABLE_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(5), GlitchData => RXNOTINTABLE5_GlitchData, OutSignalName => "RXNOTINTABLE(5)", OutTemp => RXNOTINTABLE_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(6), GlitchData => RXNOTINTABLE6_GlitchData, OutSignalName => "RXNOTINTABLE(6)", OutTemp => RXNOTINTABLE_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(7), GlitchData => RXNOTINTABLE7_GlitchData, OutSignalName => "RXNOTINTABLE(7)", OutTemp => RXNOTINTABLE_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXREALIGN, GlitchData => RXREALIGN_GlitchData, OutSignalName => "RXREALIGN", OutTemp => RXREALIGN_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(0), GlitchData => RXRUNDISP0_GlitchData, OutSignalName => "RXRUNDISP(0)", OutTemp => RXRUNDISP_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(1), GlitchData => RXRUNDISP1_GlitchData, OutSignalName => "RXRUNDISP(1)", OutTemp => RXRUNDISP_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(2), GlitchData => RXRUNDISP2_GlitchData, OutSignalName => "RXRUNDISP(2)", OutTemp => RXRUNDISP_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(3), GlitchData => RXRUNDISP3_GlitchData, OutSignalName => "RXRUNDISP(3)", OutTemp => RXRUNDISP_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(4), GlitchData => RXRUNDISP4_GlitchData, OutSignalName => "RXRUNDISP(4)", OutTemp => RXRUNDISP_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(5), GlitchData => RXRUNDISP5_GlitchData, OutSignalName => "RXRUNDISP(5)", OutTemp => RXRUNDISP_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(6), GlitchData => RXRUNDISP6_GlitchData, OutSignalName => "RXRUNDISP(6)", OutTemp => RXRUNDISP_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(7), GlitchData => RXRUNDISP7_GlitchData, OutSignalName => "RXRUNDISP(7)", OutTemp => RXRUNDISP_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXBUFERR, GlitchData => TXBUFERR_GlitchData, OutSignalName => "TXBUFERR", OutTemp => TXBUFERR_OUT, Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(0), GlitchData => TXKERR0_GlitchData, OutSignalName => "TXKERR(0)", OutTemp => TXKERR_OUT(0), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(1), GlitchData => TXKERR1_GlitchData, OutSignalName => "TXKERR(1)", OutTemp => TXKERR_OUT(1), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(2), GlitchData => TXKERR2_GlitchData, OutSignalName => "TXKERR(2)", OutTemp => TXKERR_OUT(2), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(3), GlitchData => TXKERR3_GlitchData, OutSignalName => "TXKERR(3)", OutTemp => TXKERR_OUT(3), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(4), GlitchData => TXKERR4_GlitchData, OutSignalName => "TXKERR(4)", OutTemp => TXKERR_OUT(4), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(5), GlitchData => TXKERR5_GlitchData, OutSignalName => "TXKERR(5)", OutTemp => TXKERR_OUT(5), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(6), GlitchData => TXKERR6_GlitchData, OutSignalName => "TXKERR(6)", OutTemp => TXKERR_OUT(6), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(7), GlitchData => TXKERR7_GlitchData, OutSignalName => "TXKERR(7)", OutTemp => TXKERR_OUT(7), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(0), GlitchData => TXRUNDISP0_GlitchData, OutSignalName => "TXRUNDISP(0)", OutTemp => TXRUNDISP_OUT(0), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(1), GlitchData => TXRUNDISP1_GlitchData, OutSignalName => "TXRUNDISP(1)", OutTemp => TXRUNDISP_OUT(1), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(2), GlitchData => TXRUNDISP2_GlitchData, OutSignalName => "TXRUNDISP(2)", OutTemp => TXRUNDISP_OUT(2), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(3), GlitchData => TXRUNDISP3_GlitchData, OutSignalName => "TXRUNDISP(3)", OutTemp => TXRUNDISP_OUT(3), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(4), GlitchData => TXRUNDISP4_GlitchData, OutSignalName => "TXRUNDISP(4)", OutTemp => TXRUNDISP_OUT(4), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(5), GlitchData => TXRUNDISP5_GlitchData, OutSignalName => "TXRUNDISP(5)", OutTemp => TXRUNDISP_OUT(5), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(6), GlitchData => TXRUNDISP6_GlitchData, OutSignalName => "TXRUNDISP(6)", OutTemp => TXRUNDISP_OUT(6), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(7), GlitchData => TXRUNDISP7_GlitchData, OutSignalName => "TXRUNDISP(7)", OutTemp => TXRUNDISP_OUT(7), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); -- Wait signal (input/output pins) wait on CHBONDDONE_OUT, CHBONDO_OUT, -- PMARXLOCK_OUT, RXBUFSTATUS_OUT, RXCHARISCOMMA_OUT, RXCHARISK_OUT, RXCLKCORCNT_OUT, RXCOMMADET_OUT, RXDATA_OUT, RXDISPERR_OUT, RXLOSSOFSYNC_OUT, RXNOTINTABLE_OUT, RXREALIGN_OUT, -- RXRECCLK_OUT, RXRUNDISP_OUT, TXBUFERR_OUT, TXKERR_OUT, -- TXN_OUT, -- TXOUTCLK_OUT, -- TXP_OUT, TXRUNDISP_OUT, BREFCLKNIN_ipd, BREFCLKPIN_ipd, CHBONDI_ipd, ENCHANSYNC_ipd, ENMCOMMAALIGN_ipd, ENPCOMMAALIGN_ipd, LOOPBACK_ipd, PMAINIT_ipd, PMAREGADDR_ipd, PMAREGDATAIN_ipd, PMAREGRW_ipd, PMAREGSTROBE_ipd, PMARXLOCKSEL_ipd, POWERDOWN_ipd, REFCLK_ipd, REFCLK2_ipd, REFCLKBSEL_ipd, REFCLKSEL_ipd, RXBLOCKSYNC64B66BUSE_ipd, RXCOMMADETUSE_ipd, RXDATAWIDTH_ipd, RXDEC64B66BUSE_ipd, RXDEC8B10BUSE_ipd, RXDESCRAM64B66BUSE_ipd, RXIGNOREBTF_ipd, RXINTDATAWIDTH_ipd, RXN_ipd, RXP_ipd, RXPOLARITY_ipd, RXRESET_ipd, RXSLIDE_ipd, RXUSRCLK_ipd, RXUSRCLK2_ipd, TXBYPASS8B10B_ipd, TXCHARDISPMODE_ipd, TXCHARDISPVAL_ipd, TXCHARISK_ipd, TXDATA_ipd, TXDATAWIDTH_ipd, TXENC64B66BUSE_ipd, TXENC8B10BUSE_ipd, TXGEARBOX64B66BUSE_ipd, TXINHIBIT_ipd, TXINTDATAWIDTH_ipd, TXPOLARITY_ipd, TXRESET_ipd, TXSCRAM64B66BUSE_ipd, TXUSRCLK_ipd, TXUSRCLK2_ipd; end process TIMING; TXN <= TXN_OUT; TXP <= TXP_OUT; RXRECCLK <= RXRECCLK_OUT; TXOUTCLK <= TXOUTCLK_OUT; PMARXLOCK <= PMARXLOCK_OUT; end GT10_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_xaui_1.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for XAUI I/O Standard 1 Byte Data -- /___/ /\ Filename : GT10_XAUI_1.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:09 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_XAUI_1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_XAUI_1 is generic ( ALIGN_COMMA_WORD : integer := 2; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 2; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 2; CLK_CORRECT_USE : boolean := TRUE; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32263068090104a628"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(0 downto 0); RXCHARISK : out std_logic_vector(0 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(7 downto 0); RXDISPERR : out std_logic_vector(0 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(0 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(0 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(0 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(0 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(0 downto 0); TXCHARDISPMODE : in std_logic_vector(0 downto 0); TXCHARDISPVAL : in std_logic_vector(0 downto 0); TXCHARISK : in std_logic_vector(0 downto 0); TXDATA : in std_logic_vector(7 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_XAUI_1; -- Architecture body -- architecture GT10_XAUI_1_V of GT10_XAUI_1 is signal OPEN7 : std_logic_vector(6 downto 0); signal OPEN56 : std_logic_vector(55 downto 0); signal z7 : std_logic_vector(6 downto 0) := "0000000"; signal z56 : std_logic_vector(55 downto 0) := "00000000000000000000000000000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00101111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "25_10", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 1) => OPEN7, RXCHARISK(0 downto 0) => RXCHARISK, RXCHARISK(7 downto 1) => OPEN7, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(7 downto 0) => RXDATA, RXDATA(63 downto 8) => OPEN56, RXDISPERR(0 downto 0) => RXDISPERR, RXDISPERR(7 downto 1) => OPEN7, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 1) => OPEN7, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(0 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 1) => OPEN7, TXBUFERR => TXBUFERR, TXKERR(0 downto 0) => TXKERR, TXKERR(7 downto 1) => OPEN7, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(0 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 1) => OPEN7, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 1) => z7, TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 1) => z7, TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 1) => z7, TXCHARISK(0 downto 0) => TXCHARISK, TXCHARISK(7 downto 1) => z7, TXDATA(7 downto 0) => TXDATA, TXDATA(63 downto 8) => z56, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_XAUI_1_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_xaui_2.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for XAUI I/O Standard 2 Byte Data -- /___/ /\ Filename : GT10_XAUI_2.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_XAUI_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_XAUI_2 is generic ( ALIGN_COMMA_WORD : integer := 2; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 2; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 2; CLK_CORRECT_USE : boolean := TRUE; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00fc0db00b0f32663068090105a628"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(1 downto 0); RXCHARISK : out std_logic_vector(1 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(15 downto 0); RXDISPERR : out std_logic_vector(1 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(1 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(1 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(1 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(1 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(1 downto 0); TXCHARDISPMODE : in std_logic_vector(1 downto 0); TXCHARDISPVAL : in std_logic_vector(1 downto 0); TXCHARISK : in std_logic_vector(1 downto 0); TXDATA : in std_logic_vector(15 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_XAUI_2; -- Architecture body -- architecture GT10_XAUI_2_V of GT10_XAUI_2 is signal OPEN6 : std_logic_vector(5 downto 0); signal OPEN48 : std_logic_vector(47 downto 0); signal z6 : std_logic_vector(5 downto 0) := "000000"; signal z48 : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00101111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "25_20", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 2) => OPEN6, RXCHARISK(1 downto 0) => RXCHARISK, RXCHARISK(7 downto 2) => OPEN6, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(15 downto 0) => RXDATA, RXDATA(63 downto 16) => OPEN48, RXDISPERR(1 downto 0) => RXDISPERR, RXDISPERR(7 downto 2) => OPEN6, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 2) => OPEN6, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(1 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 2) => OPEN6, TXBUFERR => TXBUFERR, TXKERR(1 downto 0) => TXKERR, TXKERR(7 downto 2) => OPEN6, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(1 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 2) => OPEN6, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 2) => z6, TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 2) => z6, TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 2) => z6, TXCHARISK(1 downto 0) => TXCHARISK, TXCHARISK(7 downto 2) => z6, TXDATA(15 downto 0) => TXDATA, TXDATA(63 downto 16) => z48, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_XAUI_2_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt10_xaui_4.vhd,v 1.5 2005/03/10 22:45:34 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 10-Gigabit Transceiver for XAUI I/O Standard 4 Byte Data -- /___/ /\ Filename : GT10_XAUI_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT10_XAUI_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT10_XAUI_4 is generic ( ALIGN_COMMA_WORD : integer := 2; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 2; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 36; CLK_COR_MIN_LAT : integer := 28; CLK_COR_SEQ_1_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_MASK : bit_vector := "0000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 2; CLK_CORRECT_USE : boolean := TRUE; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; PMA_PWR_CNTRL : bit_vector := "11111111"; PMA_SPEED_HEX : bit_vector := X"00ffcd500b0132663068090105a628"; PMA_SPEED_USE : string := "PMA_SPEED"; RX_BUFFER_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; TX_BUFFER_USE : boolean := TRUE ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(4 downto 0); PMARXLOCK : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXOUTCLK : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLKNIN : in std_ulogic; BREFCLKPIN : in std_ulogic; CHBONDI : in std_logic_vector(4 downto 0); ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); PMAINIT : in std_ulogic; PMAREGADDR : in std_logic_vector(5 downto 0); PMAREGDATAIN : in std_logic_vector(7 downto 0); PMAREGRW : in std_ulogic; PMAREGSTROBE : in std_ulogic; PMARXLOCKSEL : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKBSEL : in std_ulogic; REFCLKSEL : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT10_XAUI_4; -- Architecture body -- architecture GT10_XAUI_4_V of GT10_XAUI_4 is signal OPEN4 : std_logic_vector(3 downto 0); signal OPEN32 : std_logic_vector(31 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; begin -- GT10 Instatiation (port map, generic map) GT10_inst : GT10 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00101111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => "0001111111", DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_10B_VALUE => "1010000011", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0101111100", PCOMMA_DETECT => TRUE, PMA_PWR_CNTRL => PMA_PWR_CNTRL, PMA_SPEED => "25_40", PMA_SPEED_HEX => PMA_SPEED_HEX, PMA_SPEED_USE => PMA_SPEED_USE, RX_BUFFER_USE => RX_BUFFER_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, TX_BUFFER_USE => TX_BUFFER_USE ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, PMARXLOCK => PMARXLOCK, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(7 downto 4) => OPEN4, RXCHARISK(3 downto 0) => RXCHARISK, RXCHARISK(7 downto 4) => OPEN4, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXDATA(31 downto 0) => RXDATA, RXDATA(63 downto 32) => OPEN32, RXDISPERR(3 downto 0) => RXDISPERR, RXDISPERR(7 downto 4) => OPEN4, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(3 downto 0) => RXNOTINTABLE, RXNOTINTABLE(7 downto 4) => OPEN4, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(3 downto 0) => RXRUNDISP, RXRUNDISP(7 downto 4) => OPEN4, TXBUFERR => TXBUFERR, TXKERR(3 downto 0) => TXKERR, TXKERR(7 downto 4) => OPEN4, TXN => TXN, TXOUTCLK => TXOUTCLK, TXP => TXP, TXRUNDISP(3 downto 0) => TXRUNDISP, TXRUNDISP(7 downto 4) => OPEN4, BREFCLKNIN => BREFCLKNIN, BREFCLKPIN => BREFCLKPIN, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, PMAINIT => PMAINIT, PMAREGADDR => PMAREGADDR, PMAREGDATAIN => PMAREGDATAIN, PMAREGRW => PMAREGRW, PMAREGSTROBE => PMAREGSTROBE, PMARXLOCKSEL => PMARXLOCKSEL, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKBSEL => REFCLKBSEL, REFCLKSEL => REFCLKSEL, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(3 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(7 downto 4) => z4, TXCHARDISPMODE(3 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(7 downto 4) => z4, TXCHARDISPVAL(3 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(7 downto 4) => z4, TXCHARISK(3 downto 0) => TXCHARISK, TXCHARISK(7 downto 4) => z4, TXDATA(31 downto 0) => TXDATA, TXDATA(63 downto 32) => z32, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT10_XAUI_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_aurora_1.vhd,v 1.4 2004/04/08 18:46:22 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for AURORA I/O Standard 1 Byte Data -- /___/ /\ Filename : GT_AURORA_1.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_AURORA_1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_AURORA_1 is generic ( CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(3 downto 0); CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(0 downto 0); RXCHARISK : out std_logic_vector(0 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(7 downto 0); RXDISPERR : out std_logic_vector(0 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(0 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(0 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(0 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(0 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CHBONDI : in std_logic_vector(3 downto 0); CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(0 downto 0); TXCHARDISPMODE : in std_logic_vector(0 downto 0); TXCHARDISPVAL : in std_logic_vector(0 downto 0); TXCHARISK : in std_logic_vector(0 downto 0); TXDATA : in std_logic_vector(7 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_AURORA_1; -- Architecture body -- architecture GT_AURORA_1_V of GT_AURORA_1 is signal OPEN3 : std_logic_vector(2 downto 0); signal OPEN24 : std_logic_vector(23 downto 0); signal z3 : std_logic_vector(2 downto 0) := "000"; signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 16, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_OFFSET => 8, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00101111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 8, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00111110111", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 1, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111111", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "USER_MODE", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000101", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111010", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 1, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 1, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(3 downto 1) => OPEN3, RXCHARISK(0 downto 0) => RXCHARISK, RXCHARISK(3 downto 1) => OPEN3, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA(7 downto 0) => RXDATA, RXDATA(31 downto 8) => OPEN24, RXDISPERR(0 downto 0) => RXDISPERR, RXDISPERR(3 downto 1) => OPEN3, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, RXNOTINTABLE(3 downto 1) => OPEN3, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(0 downto 0) => RXRUNDISP, RXRUNDISP(3 downto 1) => OPEN3, TXBUFERR => TXBUFERR, TXKERR(0 downto 0) => TXKERR, TXKERR(3 downto 1) => OPEN3, TXN => TXN, TXP => TXP, TXRUNDISP(0 downto 0) => TXRUNDISP, TXRUNDISP(3 downto 1) => OPEN3, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CHBONDI => CHBONDI, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(3 downto 1) => z3, TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(3 downto 1) => z3, TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(3 downto 1) => z3, TXCHARISK(0 downto 0) => TXCHARISK, TXCHARISK(3 downto 1) => z3, TXDATA(7 downto 0) => TXDATA, TXDATA(31 downto 8) => z24, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_AURORA_1_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_aurora_2.vhd,v 1.4 2004/04/08 18:46:22 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for AURORA I/O Standard 2 Byte Data -- /___/ /\ Filename : GT_AURORA_2.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_AURORA_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_AURORA_2 is generic ( CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(3 downto 0); CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(1 downto 0); RXCHARISK : out std_logic_vector(1 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(15 downto 0); RXDISPERR : out std_logic_vector(1 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(1 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(1 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(1 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(1 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CHBONDI : in std_logic_vector(3 downto 0); CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(1 downto 0); TXCHARDISPMODE : in std_logic_vector(1 downto 0); TXCHARDISPVAL : in std_logic_vector(1 downto 0); TXCHARISK : in std_logic_vector(1 downto 0); TXDATA : in std_logic_vector(15 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_AURORA_2; -- Architecture body -- architecture GT_AURORA_2_V of GT_AURORA_2 is signal OPEN2 : std_logic_vector(1 downto 0); signal OPEN16 : std_logic_vector(15 downto 0); signal z2 : std_logic_vector(1 downto 0) := "00"; signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 16, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_OFFSET => 8, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00101111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 8, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00111110111", CLK_COR_SEQ_1_2 => "00111110111", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 2, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111111", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "USER_MODE", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000101", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111010", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 2, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 2, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(3 downto 2) => OPEN2, RXCHARISK(1 downto 0) => RXCHARISK, RXCHARISK(3 downto 2) => OPEN2, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA(15 downto 0) => RXDATA, RXDATA(31 downto 16) => OPEN16, RXDISPERR(1 downto 0) => RXDISPERR, RXDISPERR(3 downto 2) => OPEN2, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, RXNOTINTABLE(3 downto 2) => OPEN2, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(1 downto 0) => RXRUNDISP, RXRUNDISP(3 downto 2) => OPEN2, TXBUFERR => TXBUFERR, TXKERR(1 downto 0) => TXKERR, TXKERR(3 downto 2) => OPEN2, TXN => TXN, TXP => TXP, TXRUNDISP(1 downto 0) => TXRUNDISP, TXRUNDISP(3 downto 2) => OPEN2, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CHBONDI => CHBONDI, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(3 downto 2) => z2, TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(3 downto 2) => z2, TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(3 downto 2) => z2, TXCHARISK(1 downto 0) => TXCHARISK, TXCHARISK(3 downto 2) => z2, TXDATA(15 downto 0) => TXDATA, TXDATA(31 downto 16) => z16, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_AURORA_2_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_aurora_4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for AURORA I/O Standard 4 Byte Data -- /___/ /\ Filename : GT_AURORA_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_AURORA_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_AURORA_4 is generic ( CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(3 downto 0); CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CHBONDI : in std_logic_vector(3 downto 0); CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_AURORA_4; -- Architecture body -- architecture GT_AURORA_4_V of GT_AURORA_4 is begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 16, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_OFFSET => 8, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00101111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 8, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00111110111", CLK_COR_SEQ_1_2 => "00111110111", CLK_COR_SEQ_1_3 => "00111110111", CLK_COR_SEQ_1_4 => "00111110111", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 4, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111111", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "USER_MODE", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000101", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111010", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 4, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 4, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP => RXRUNDISP, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXN => TXN, TXP => TXP, TXRUNDISP => TXRUNDISP, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CHBONDI => CHBONDI, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_AURORA_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_custom.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for CUSTOM I/O Standard -- /___/ /\ Filename : GT_CUSTOM.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_CUSTOM ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_CUSTOM is generic ( ALIGN_COMMA_MSB : boolean := FALSE; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_OFFSET : integer := 8; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 1; CHAN_BOND_WAIT : integer := 8; CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 1; CLK_CORRECT_USE : boolean := TRUE; COMMA_10B_MASK : bit_vector := "1111111000"; CRC_END_OF_PKT : string := "K29_7"; CRC_FORMAT : string := "USER_MODE"; CRC_START_OF_PKT : string := "K27_7"; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; MCOMMA_10B_VALUE : bit_vector := "1100000000"; MCOMMA_DETECT : boolean := TRUE; PCOMMA_10B_VALUE : bit_vector := "0011111000"; PCOMMA_DETECT : boolean := TRUE; REF_CLK_V_SEL : integer := 0; RX_BUFFER_USE : boolean := TRUE; RX_CRC_USE : boolean := FALSE; RX_DATA_WIDTH : integer := 2; RX_DECODE_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_BUFFER_USE : boolean := TRUE; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DATA_WIDTH : integer := 2; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(3 downto 0); CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CHBONDI : in std_logic_vector(3 downto 0); CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_CUSTOM; -- Architecture body -- architecture GT_CUSTOM_V of GT_CUSTOM is begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => ALIGN_COMMA_MSB, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_OFFSET => CHAN_BOND_OFFSET, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1, CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2, CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3, CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4, CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1, CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2, CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3, CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, CHAN_BOND_WAIT => CHAN_BOND_WAIT, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1, CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2, CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3, CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4, CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1, CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2, CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3, CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, COMMA_10B_MASK => COMMA_10B_MASK, CRC_END_OF_PKT => CRC_END_OF_PKT, CRC_FORMAT => CRC_FORMAT, CRC_START_OF_PKT => CRC_START_OF_PKT, DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_10B_VALUE => MCOMMA_10B_VALUE, MCOMMA_DETECT => MCOMMA_DETECT, PCOMMA_10B_VALUE => PCOMMA_10B_VALUE, PCOMMA_DETECT => PCOMMA_DETECT, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => RX_BUFFER_USE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => RX_DATA_WIDTH, RX_DECODE_USE => RX_DECODE_USE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TX_BUFFER_USE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => TX_DATA_WIDTH, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP => RXRUNDISP, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXN => TXN, TXP => TXP, TXRUNDISP => TXRUNDISP, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CHBONDI => CHBONDI, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_CUSTOM_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_ethernet_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for ETHERNET I/O Standard 1 Byte Data -- /___/ /\ Filename : GT_ETHERNET_1.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_ETHERNET_1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_ETHERNET_1 is generic ( CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(0 downto 0); RXCHARISK : out std_logic_vector(0 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(7 downto 0); RXDISPERR : out std_logic_vector(0 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(0 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(0 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(0 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(0 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(0 downto 0); TXCHARDISPMODE : in std_logic_vector(0 downto 0); TXCHARDISPVAL : in std_logic_vector(0 downto 0); TXCHARISK : in std_logic_vector(0 downto 0); TXDATA : in std_logic_vector(7 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_ETHERNET_1; -- Architecture body -- architecture GT_ETHERNET_1_V of GT_ETHERNET_1 is signal OPEN1 : std_ulogic; signal OPEN4 : std_logic_vector(3 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z1 : std_ulogic := '0'; signal OPEN3 : std_logic_vector(2 downto 0); signal OPEN24 : std_logic_vector(23 downto 0); signal z3 : std_logic_vector(2 downto 0) := "000"; signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 1, CHAN_BOND_MODE => "OFF", CHAN_BOND_OFFSET => 0, CHAN_BOND_ONE_SHOT => TRUE, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 7, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00110111100", CLK_COR_SEQ_1_2 => "00001010000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 2, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "ETHERNET", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 1, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 1, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => OPEN1, CHBONDO => OPEN4, CHBONDI => z4, ENCHANSYNC => z1, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(3 downto 1) => OPEN3, RXCHARISK(0 downto 0) => RXCHARISK, RXCHARISK(3 downto 1) => OPEN3, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA(7 downto 0) => RXDATA, RXDATA(31 downto 8) => OPEN24, RXDISPERR(0 downto 0) => RXDISPERR, RXDISPERR(3 downto 1) => OPEN3, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, RXNOTINTABLE(3 downto 1) => OPEN3, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(0 downto 0) => RXRUNDISP, RXRUNDISP(3 downto 1) => OPEN3, TXBUFERR => TXBUFERR, TXKERR(0 downto 0) => TXKERR, TXKERR(3 downto 1) => OPEN3, TXN => TXN, TXP => TXP, TXRUNDISP(0 downto 0) => TXRUNDISP, TXRUNDISP(3 downto 1) => OPEN3, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(3 downto 1) => z3, TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(3 downto 1) => z3, TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(3 downto 1) => z3, TXCHARISK(0 downto 0) => TXCHARISK, TXCHARISK(3 downto 1) => z3, TXDATA(7 downto 0) => TXDATA, TXDATA(31 downto 8) => z24, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_ETHERNET_1_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_ethernet_2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for ETHERNET I/O Standard 2 Byte Data -- /___/ /\ Filename : GT_ETHERNET_2.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_ETHERNET_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_ETHERNET_2 is generic ( CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(1 downto 0); RXCHARISK : out std_logic_vector(1 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(15 downto 0); RXDISPERR : out std_logic_vector(1 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(1 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(1 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(1 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(1 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(1 downto 0); TXCHARDISPMODE : in std_logic_vector(1 downto 0); TXCHARDISPVAL : in std_logic_vector(1 downto 0); TXCHARISK : in std_logic_vector(1 downto 0); TXDATA : in std_logic_vector(15 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_ETHERNET_2; -- Architecture body -- architecture GT_ETHERNET_2_V of GT_ETHERNET_2 is signal OPEN1 : std_ulogic; signal OPEN4 : std_logic_vector(3 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z1 : std_ulogic := '0'; signal OPEN2 : std_logic_vector(1 downto 0); signal OPEN16 : std_logic_vector(15 downto 0); signal z2 : std_logic_vector(1 downto 0) := "00"; signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 1, CHAN_BOND_MODE => "OFF", CHAN_BOND_OFFSET => 0, CHAN_BOND_ONE_SHOT => TRUE, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 7, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00110111100", CLK_COR_SEQ_1_2 => "00001010000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 2, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "ETHERNET", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 2, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 2, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => OPEN1, CHBONDO => OPEN4, CHBONDI => z4, ENCHANSYNC => z1, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(3 downto 2) => OPEN2, RXCHARISK(1 downto 0) => RXCHARISK, RXCHARISK(3 downto 2) => OPEN2, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA(15 downto 0) => RXDATA, RXDATA(31 downto 16) => OPEN16, RXDISPERR(1 downto 0) => RXDISPERR, RXDISPERR(3 downto 2) => OPEN2, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, RXNOTINTABLE(3 downto 2) => OPEN2, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(1 downto 0) => RXRUNDISP, RXRUNDISP(3 downto 2) => OPEN2, TXBUFERR => TXBUFERR, TXKERR(1 downto 0) => TXKERR, TXKERR(3 downto 2) => OPEN2, TXN => TXN, TXP => TXP, TXRUNDISP(1 downto 0) => TXRUNDISP, TXRUNDISP(3 downto 2) => OPEN2, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(3 downto 2) => z2, TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(3 downto 2) => z2, TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(3 downto 2) => z2, TXCHARISK(1 downto 0) => TXCHARISK, TXCHARISK(3 downto 2) => z2, TXDATA(15 downto 0) => TXDATA, TXDATA(31 downto 16) => z16, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_ETHERNET_2_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_ethernet_4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for ETHERNET I/O Standard 4 Byte Data -- /___/ /\ Filename : GT_ETHERNET_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:10 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_ETHERNET_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_ETHERNET_4 is generic ( CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_ETHERNET_4; -- Architecture body -- architecture GT_ETHERNET_4_V of GT_ETHERNET_4 is signal OPEN1 : std_ulogic; signal OPEN4 : std_logic_vector(3 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z1 : std_ulogic := '0'; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 1, CHAN_BOND_MODE => "OFF", CHAN_BOND_OFFSET => 0, CHAN_BOND_ONE_SHOT => TRUE, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 7, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00110111100", CLK_COR_SEQ_1_2 => "00001010000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 2, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "ETHERNET", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 4, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 4, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => OPEN1, CHBONDO => OPEN4, CHBONDI => z4, ENCHANSYNC => z1, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP => RXRUNDISP, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXN => TXN, TXP => TXP, TXRUNDISP => TXRUNDISP, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_ETHERNET_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_fibre_chan_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for FIBRE_CHAN I/O Standard 1 Byte Data -- /___/ /\ Filename : GT_FIBRE_CHAN_1.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_FIBRE_CHAN_1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_FIBRE_CHAN_1 is generic ( CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 2; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(0 downto 0); RXCHARISK : out std_logic_vector(0 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(7 downto 0); RXDISPERR : out std_logic_vector(0 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(0 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(0 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(0 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(0 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(0 downto 0); TXCHARDISPMODE : in std_logic_vector(0 downto 0); TXCHARDISPVAL : in std_logic_vector(0 downto 0); TXCHARISK : in std_logic_vector(0 downto 0); TXDATA : in std_logic_vector(7 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_FIBRE_CHAN_1; -- Architecture body -- architecture GT_FIBRE_CHAN_1_V of GT_FIBRE_CHAN_1 is signal OPEN1 : std_ulogic; signal OPEN4 : std_logic_vector(3 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z1 : std_ulogic := '0'; signal OPEN3 : std_logic_vector(2 downto 0); signal OPEN24 : std_logic_vector(23 downto 0); signal z3 : std_logic_vector(2 downto 0) := "000"; signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 1, CHAN_BOND_MODE => "OFF", CHAN_BOND_OFFSET => 0, CHAN_BOND_ONE_SHOT => TRUE, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 7, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00110111100", CLK_COR_SEQ_1_2 => "00010010101", CLK_COR_SEQ_1_3 => "00010110101", CLK_COR_SEQ_1_4 => "00010110101", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 4, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "FIBRE_CHAN", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 1, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 1, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => OPEN1, CHBONDO => OPEN4, CHBONDI => z4, ENCHANSYNC => z1, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(3 downto 1) => OPEN3, RXCHARISK(0 downto 0) => RXCHARISK, RXCHARISK(3 downto 1) => OPEN3, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA(7 downto 0) => RXDATA, RXDATA(31 downto 8) => OPEN24, RXDISPERR(0 downto 0) => RXDISPERR, RXDISPERR(3 downto 1) => OPEN3, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, RXNOTINTABLE(3 downto 1) => OPEN3, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(0 downto 0) => RXRUNDISP, RXRUNDISP(3 downto 1) => OPEN3, TXBUFERR => TXBUFERR, TXKERR(0 downto 0) => TXKERR, TXKERR(3 downto 1) => OPEN3, TXN => TXN, TXP => TXP, TXRUNDISP(0 downto 0) => TXRUNDISP, TXRUNDISP(3 downto 1) => OPEN3, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(3 downto 1) => z3, TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(3 downto 1) => z3, TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(3 downto 1) => z3, TXCHARISK(0 downto 0) => TXCHARISK, TXCHARISK(3 downto 1) => z3, TXDATA(7 downto 0) => TXDATA, TXDATA(31 downto 8) => z24, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_FIBRE_CHAN_1_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_fibre_chan_2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for FIBRE_CHAN I/O Standard 2 Byte Data -- /___/ /\ Filename : GT_FIBRE_CHAN_2.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_FIBRE_CHAN_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_FIBRE_CHAN_2 is generic ( CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 2; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(1 downto 0); RXCHARISK : out std_logic_vector(1 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(15 downto 0); RXDISPERR : out std_logic_vector(1 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(1 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(1 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(1 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(1 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(1 downto 0); TXCHARDISPMODE : in std_logic_vector(1 downto 0); TXCHARDISPVAL : in std_logic_vector(1 downto 0); TXCHARISK : in std_logic_vector(1 downto 0); TXDATA : in std_logic_vector(15 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_FIBRE_CHAN_2; -- Architecture body -- architecture GT_FIBRE_CHAN_2_V of GT_FIBRE_CHAN_2 is signal OPEN1 : std_ulogic; signal OPEN4 : std_logic_vector(3 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z1 : std_ulogic := '0'; signal OPEN2 : std_logic_vector(1 downto 0); signal OPEN16 : std_logic_vector(15 downto 0); signal z2 : std_logic_vector(1 downto 0) := "00"; signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 1, CHAN_BOND_MODE => "OFF", CHAN_BOND_OFFSET => 0, CHAN_BOND_ONE_SHOT => TRUE, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 7, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00110111100", CLK_COR_SEQ_1_2 => "00010010101", CLK_COR_SEQ_1_3 => "00010110101", CLK_COR_SEQ_1_4 => "00010110101", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 4, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "FIBRE_CHAN", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 2, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 2, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => OPEN1, CHBONDO => OPEN4, CHBONDI => z4, ENCHANSYNC => z1, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(3 downto 2) => OPEN2, RXCHARISK(1 downto 0) => RXCHARISK, RXCHARISK(3 downto 2) => OPEN2, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA(15 downto 0) => RXDATA, RXDATA(31 downto 16) => OPEN16, RXDISPERR(1 downto 0) => RXDISPERR, RXDISPERR(3 downto 2) => OPEN2, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, RXNOTINTABLE(3 downto 2) => OPEN2, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(1 downto 0) => RXRUNDISP, RXRUNDISP(3 downto 2) => OPEN2, TXBUFERR => TXBUFERR, TXKERR(1 downto 0) => TXKERR, TXKERR(3 downto 2) => OPEN2, TXN => TXN, TXP => TXP, TXRUNDISP(1 downto 0) => TXRUNDISP, TXRUNDISP(3 downto 2) => OPEN2, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(3 downto 2) => z2, TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(3 downto 2) => z2, TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(3 downto 2) => z2, TXCHARISK(1 downto 0) => TXCHARISK, TXCHARISK(3 downto 2) => z2, TXDATA(15 downto 0) => TXDATA, TXDATA(31 downto 16) => z16, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_FIBRE_CHAN_2_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_fibre_chan_4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for FIBRE_CHAN I/O Standard 4 Byte Data -- /___/ /\ Filename : GT_FIBRE_CHAN_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_FIBRE_CHAN_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_FIBRE_CHAN_4 is generic ( CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 2; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_FIBRE_CHAN_4; -- Architecture body -- architecture GT_FIBRE_CHAN_4_V of GT_FIBRE_CHAN_4 is signal OPEN1 : std_ulogic; signal OPEN4 : std_logic_vector(3 downto 0); signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z1 : std_ulogic := '0'; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 1, CHAN_BOND_MODE => "OFF", CHAN_BOND_OFFSET => 0, CHAN_BOND_ONE_SHOT => TRUE, CHAN_BOND_SEQ_1_1 => "00000000000", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 7, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00110111100", CLK_COR_SEQ_1_2 => "00010010101", CLK_COR_SEQ_1_3 => "00010110101", CLK_COR_SEQ_1_4 => "00010110101", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 4, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "FIBRE_CHAN", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 4, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 4, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => OPEN1, CHBONDO => OPEN4, CHBONDI => z4, ENCHANSYNC => z1, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP => RXRUNDISP, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXN => TXN, TXP => TXP, TXRUNDISP => TXRUNDISP, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_FIBRE_CHAN_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_infiniband_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for INFINIBAND I/O Standard 1 Byte Data -- /___/ /\ Filename : GT_INFINIBAND_1.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_INFINIBAND_1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_INFINIBAND_1 is generic ( CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; LANE_ID : bit_vector := "00000000000"; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(3 downto 0); CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(0 downto 0); RXCHARISK : out std_logic_vector(0 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(7 downto 0); RXDISPERR : out std_logic_vector(0 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(0 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(0 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(0 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(0 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CHBONDI : in std_logic_vector(3 downto 0); CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(0 downto 0); TXCHARDISPMODE : in std_logic_vector(0 downto 0); TXCHARDISPVAL : in std_logic_vector(0 downto 0); TXCHARISK : in std_logic_vector(0 downto 0); TXDATA : in std_logic_vector(7 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_INFINIBAND_1; -- Architecture body -- architecture GT_INFINIBAND_1_V of GT_INFINIBAND_1 is signal OPEN3 : std_logic_vector(2 downto 0); signal OPEN24 : std_logic_vector(23 downto 0); signal z3 : std_logic_vector(2 downto 0) := "000"; signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 16, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_OFFSET => 8, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => LANE_ID, CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => LANE_ID, CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_USE => TRUE, CHAN_BOND_SEQ_LEN => 4, CHAN_BOND_WAIT => 8, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 1, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "INFINIBAND", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 1, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 1, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(3 downto 1) => OPEN3, RXCHARISK(0 downto 0) => RXCHARISK, RXCHARISK(3 downto 1) => OPEN3, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA(7 downto 0) => RXDATA, RXDATA(31 downto 8) => OPEN24, RXDISPERR(0 downto 0) => RXDISPERR, RXDISPERR(3 downto 1) => OPEN3, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, RXNOTINTABLE(3 downto 1) => OPEN3, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(0 downto 0) => RXRUNDISP, RXRUNDISP(3 downto 1) => OPEN3, TXBUFERR => TXBUFERR, TXKERR(0 downto 0) => TXKERR, TXKERR(3 downto 1) => OPEN3, TXN => TXN, TXP => TXP, TXRUNDISP(0 downto 0) => TXRUNDISP, TXRUNDISP(3 downto 1) => OPEN3, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CHBONDI => CHBONDI, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(3 downto 1) => z3, TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(3 downto 1) => z3, TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(3 downto 1) => z3, TXCHARISK(0 downto 0) => TXCHARISK, TXCHARISK(3 downto 1) => z3, TXDATA(7 downto 0) => TXDATA, TXDATA(31 downto 8) => z24, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_INFINIBAND_1_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_infiniband_2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for INFINIBAND I/O Standard 2 Byte Data -- /___/ /\ Filename : GT_INFINIBAND_2.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_INFINIBAND_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_INFINIBAND_2 is generic ( CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; LANE_ID : bit_vector := "00000000000"; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(3 downto 0); CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(1 downto 0); RXCHARISK : out std_logic_vector(1 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(15 downto 0); RXDISPERR : out std_logic_vector(1 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(1 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(1 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(1 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(1 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CHBONDI : in std_logic_vector(3 downto 0); CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(1 downto 0); TXCHARDISPMODE : in std_logic_vector(1 downto 0); TXCHARDISPVAL : in std_logic_vector(1 downto 0); TXCHARISK : in std_logic_vector(1 downto 0); TXDATA : in std_logic_vector(15 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_INFINIBAND_2; -- Architecture body -- architecture GT_INFINIBAND_2_V of GT_INFINIBAND_2 is signal OPEN2 : std_logic_vector(1 downto 0); signal OPEN16 : std_logic_vector(15 downto 0); signal z2 : std_logic_vector(1 downto 0) := "00"; signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 16, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_OFFSET => 8, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => LANE_ID, CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => LANE_ID, CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_USE => TRUE, CHAN_BOND_SEQ_LEN => 4, CHAN_BOND_WAIT => 8, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 1, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "INFINIBAND", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 2, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 2, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(3 downto 2) => OPEN2, RXCHARISK(1 downto 0) => RXCHARISK, RXCHARISK(3 downto 2) => OPEN2, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA(15 downto 0) => RXDATA, RXDATA(31 downto 16) => OPEN16, RXDISPERR(1 downto 0) => RXDISPERR, RXDISPERR(3 downto 2) => OPEN2, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, RXNOTINTABLE(3 downto 2) => OPEN2, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(1 downto 0) => RXRUNDISP, RXRUNDISP(3 downto 2) => OPEN2, TXBUFERR => TXBUFERR, TXKERR(1 downto 0) => TXKERR, TXKERR(3 downto 2) => OPEN2, TXN => TXN, TXP => TXP, TXRUNDISP(1 downto 0) => TXRUNDISP, TXRUNDISP(3 downto 2) => OPEN2, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CHBONDI => CHBONDI, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(3 downto 2) => z2, TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(3 downto 2) => z2, TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(3 downto 2) => z2, TXCHARISK(1 downto 0) => TXCHARISK, TXCHARISK(3 downto 2) => z2, TXDATA(15 downto 0) => TXDATA, TXDATA(31 downto 16) => z16, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_INFINIBAND_2_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_infiniband_4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for INFINIBAND I/O Standard 4 Byte Data -- /___/ /\ Filename : GT_INFINIBAND_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_INFINIBAND_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_INFINIBAND_4 is generic ( CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; LANE_ID : bit_vector := "00000000000"; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(3 downto 0); CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CHBONDI : in std_logic_vector(3 downto 0); CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_INFINIBAND_4; -- Architecture body -- architecture GT_INFINIBAND_4_V of GT_INFINIBAND_4 is begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 16, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_OFFSET => 8, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00110111100", CHAN_BOND_SEQ_1_2 => LANE_ID, CHAN_BOND_SEQ_1_3 => "00001001010", CHAN_BOND_SEQ_1_4 => "00001001010", CHAN_BOND_SEQ_2_1 => "00110111100", CHAN_BOND_SEQ_2_2 => LANE_ID, CHAN_BOND_SEQ_2_3 => "00001000101", CHAN_BOND_SEQ_2_4 => "00001000101", CHAN_BOND_SEQ_2_USE => TRUE, CHAN_BOND_SEQ_LEN => 4, CHAN_BOND_WAIT => 8, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 1, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => "K29_7", CRC_FORMAT => "INFINIBAND", CRC_START_OF_PKT => "K27_7", DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 4, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 4, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP => RXRUNDISP, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXN => TXN, TXP => TXP, TXRUNDISP => TXRUNDISP, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CHBONDI => CHBONDI, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_INFINIBAND_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt.vhd,v 1.5 2006/03/16 00:57:41 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for High-Speed I/O Simulation Model -- /___/ /\ Filename : GT.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:07 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT ----- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; entity GT is generic ( in_delay : time := 0 ps; out_delay : VitalDelayType01 := (100 ps, 100 ps); ALIGN_COMMA_MSB : boolean := FALSE; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_OFFSET : integer := 8; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 1; CHAN_BOND_WAIT : integer := 8; CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 1; CLK_CORRECT_USE : boolean := TRUE; COMMA_10B_MASK : bit_vector := "1111111000"; CRC_END_OF_PKT : string := "K29_7"; CRC_FORMAT : string := "USER_MODE"; CRC_START_OF_PKT : string := "K27_7"; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; MCOMMA_10B_VALUE : bit_vector := "1100000000"; MCOMMA_DETECT : boolean := TRUE; PCOMMA_10B_VALUE : bit_vector := "0011111000"; PCOMMA_DETECT : boolean := TRUE; REF_CLK_V_SEL : integer := 0; RX_BUFFER_USE : boolean := TRUE; RX_CRC_USE : boolean := FALSE; RX_DATA_WIDTH : integer := 2; RX_DECODE_USE : boolean := TRUE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_BUFFER_USE : boolean := TRUE; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DATA_WIDTH : integer := 2; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(3 downto 0); CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CHBONDI : in std_logic_vector(3 downto 0); CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT; -- Architecture body -- architecture GT_V of GT is component GT_SWIFT_BUS port ( TX_CRC_FORCE_VALUE : in std_logic_vector(7 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXCLKCORCNT : out std_logic_vector(2 downto 0); RXP : in std_ulogic; RXN : in std_ulogic; GSR : in std_ulogic; TXP : out std_ulogic; TXN : out std_ulogic; CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; CONFIGOUT : out std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; CRC_END_OF_PKT : in std_logic_vector(7 downto 0); CRC_FORMAT : in std_logic_vector(1 downto 0); CRC_START_OF_PKT : in std_logic_vector(7 downto 0); CHAN_BOND_LIMIT : in std_logic_vector(4 downto 0); REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXUSRCLK : in std_ulogic; TXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXUSRCLK2 : in std_ulogic; RXRESET : in std_ulogic; TXRESET : in std_ulogic; POWERDOWN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); TXDATA : in std_logic_vector(31 downto 0); RX_LOSS_OF_SYNC_FSM : in std_ulogic; RX_LOS_INVALID_INCR : in std_logic_vector(2 downto 0); RX_LOS_THRESHOLD : in std_logic_vector(2 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXPOLARITY : in std_ulogic; TXINHIBIT : in std_ulogic; ENCHANSYNC : in std_ulogic; RXPOLARITY : in std_ulogic; CHBONDI : in std_logic_vector(3 downto 0); RXRECCLK : out std_ulogic; TXBUFERR : out std_ulogic; TXFORCECRCERR : in std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); TXKERR : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXCOMMADET : out std_ulogic; RXCHECKINGCRC : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXRUNDISP : out std_logic_vector(3 downto 0); RXBUFSTATUS : out std_logic_vector(1 downto 0); CHBONDO : out std_logic_vector(3 downto 0); CHBONDDONE : out std_ulogic; TX_PREEMPHASIS : in std_logic_vector(1 downto 0); TX_DIFF_CTRL : in std_logic_vector(2 downto 0); TERMINATION_IMP : in std_ulogic; SERDES_10B : in std_ulogic; ALIGN_COMMA_MSB : in std_ulogic; PCOMMA_DETECT : in std_ulogic; MCOMMA_DETECT : in std_ulogic; PCOMMA_10B_VALUE : in std_logic_vector(0 to 9); MCOMMA_10B_VALUE : in std_logic_vector(0 to 9); COMMA_10B_MASK : in std_logic_vector(0 to 9); DEC_PCOMMA_DETECT : in std_ulogic; DEC_MCOMMA_DETECT : in std_ulogic; DEC_VALID_COMMA_ONLY : in std_ulogic; RX_DECODE_USE : in std_ulogic; RX_BUFFER_USE : in std_ulogic; TX_BUFFER_USE : in std_ulogic; CLK_CORRECT_USE : in std_ulogic; CLK_COR_SEQ_LEN : in std_logic_vector(1 downto 0); CLK_COR_INSERT_IDLE_FLAG : in std_ulogic; CLK_COR_KEEP_IDLE : in std_ulogic; CLK_COR_REPEAT_WAIT : in std_logic_vector(4 downto 0); CLK_COR_SEQ_1_1 : in std_logic_vector(10 downto 0); CLK_COR_SEQ_1_2 : in std_logic_vector(10 downto 0); CLK_COR_SEQ_1_3 : in std_logic_vector(10 downto 0); CLK_COR_SEQ_1_4 : in std_logic_vector(10 downto 0); CLK_COR_SEQ_2_USE : in std_ulogic; CLK_COR_SEQ_2_1 : in std_logic_vector(10 downto 0); CLK_COR_SEQ_2_2 : in std_logic_vector(10 downto 0); CLK_COR_SEQ_2_3 : in std_logic_vector(10 downto 0); CLK_COR_SEQ_2_4 : in std_logic_vector(10 downto 0); CHAN_BOND_MODE : in std_logic_vector(1 downto 0); CHAN_BOND_SEQ_LEN : in std_logic_vector(1 downto 0); CHAN_BOND_SEQ_1_1 : in std_logic_vector(10 downto 0); CHAN_BOND_SEQ_1_2 : in std_logic_vector(10 downto 0); CHAN_BOND_SEQ_1_3 : in std_logic_vector(10 downto 0); CHAN_BOND_SEQ_1_4 : in std_logic_vector(10 downto 0); CHAN_BOND_SEQ_2_USE : in std_ulogic; CHAN_BOND_SEQ_2_1 : in std_logic_vector(10 downto 0); CHAN_BOND_SEQ_2_2 : in std_logic_vector(10 downto 0); CHAN_BOND_SEQ_2_3 : in std_logic_vector(10 downto 0); CHAN_BOND_SEQ_2_4 : in std_logic_vector(10 downto 0); CHAN_BOND_WAIT : in std_logic_vector(3 downto 0); CHAN_BOND_OFFSET : in std_logic_vector(3 downto 0); TX_CRC_USE : in std_ulogic; RX_CRC_USE : in std_ulogic; CHAN_BOND_ONE_SHOT : in std_ulogic; RX_DATA_WIDTH : in std_logic_vector(1 downto 0); TX_DATA_WIDTH : in std_logic_vector(1 downto 0); BREFCLK : in std_ulogic; BREFCLK2 : in std_ulogic; REF_CLK_V_SEL : in std_ulogic ); end component; -- Attribute-to-Cell mapping signals signal ALIGN_COMMA_MSB_BINARY : std_ulogic; signal CHAN_BOND_LIMIT_BINARY : std_logic_vector(4 downto 0); signal CHAN_BOND_MODE_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_OFFSET_BINARY : std_logic_vector(3 downto 0); signal CHAN_BOND_ONE_SHOT_BINARY : std_ulogic; signal CHAN_BOND_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1); signal CHAN_BOND_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2); signal CHAN_BOND_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3); signal CHAN_BOND_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4); signal CHAN_BOND_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1); signal CHAN_BOND_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2); signal CHAN_BOND_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3); signal CHAN_BOND_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4); signal CHAN_BOND_SEQ_2_USE_BINARY : std_ulogic; signal CHAN_BOND_SEQ_LEN_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_WAIT_BINARY : std_logic_vector(3 downto 0); signal CLK_COR_INSERT_IDLE_FLAG_BINARY : std_ulogic; signal CLK_COR_KEEP_IDLE_BINARY : std_ulogic; signal CLK_COR_REPEAT_WAIT_BINARY : std_logic_vector(4 downto 0); signal CLK_COR_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1); signal CLK_COR_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2); signal CLK_COR_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3); signal CLK_COR_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4); signal CLK_COR_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1); signal CLK_COR_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2); signal CLK_COR_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3); signal CLK_COR_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4); signal CLK_COR_SEQ_2_USE_BINARY : std_ulogic; signal CLK_COR_SEQ_LEN_BINARY : std_logic_vector(1 downto 0); signal CLK_CORRECT_USE_BINARY : std_ulogic; signal COMMA_10B_MASK_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_MASK); signal CRC_END_OF_PKT_BINARY : std_logic_vector(7 downto 0); signal CRC_FORMAT_BINARY : std_logic_vector(1 downto 0); signal CRC_START_OF_PKT_BINARY : std_logic_vector(7 downto 0); signal DEC_MCOMMA_DETECT_BINARY : std_ulogic; signal DEC_PCOMMA_DETECT_BINARY : std_ulogic; signal DEC_VALID_COMMA_ONLY_BINARY : std_ulogic; signal MCOMMA_10B_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE); signal MCOMMA_DETECT_BINARY : std_ulogic; signal PCOMMA_10B_VALUE_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE); signal PCOMMA_DETECT_BINARY : std_ulogic; signal REF_CLK_V_SEL_BINARY : std_ulogic; signal RX_BUFFER_USE_BINARY : std_ulogic; signal RX_CRC_USE_BINARY : std_ulogic; signal RX_DATA_WIDTH_BINARY : std_logic_vector(1 downto 0); signal RX_DECODE_USE_BINARY : std_ulogic; signal RX_LOS_INVALID_INCR_BINARY : std_logic_vector(2 downto 0); signal RX_LOS_THRESHOLD_BINARY : std_logic_vector(2 downto 0); signal RX_LOSS_OF_SYNC_FSM_BINARY : std_ulogic; signal SERDES_10B_BINARY : std_ulogic; signal TERMINATION_IMP_BINARY : std_ulogic; signal TX_BUFFER_USE_BINARY : std_ulogic; signal TX_CRC_FORCE_VALUE_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(TX_CRC_FORCE_VALUE); signal TX_CRC_USE_BINARY : std_ulogic; signal TX_DATA_WIDTH_BINARY : std_logic_vector(1 downto 0); signal TX_DIFF_CTRL_BINARY : std_logic_vector(2 downto 0); signal TX_PREEMPHASIS_BINARY : std_logic_vector(1 downto 0); -- Input/Output Pin signals signal CHBONDDONE_out : std_ulogic; signal CHBONDO_out : std_logic_vector(3 downto 0); signal CONFIGOUT_out : std_ulogic; signal RXBUFSTATUS_out : std_logic_vector(1 downto 0); signal RXCHARISCOMMA_out : std_logic_vector(3 downto 0); signal RXCHARISK_out : std_logic_vector(3 downto 0); signal RXCHECKINGCRC_out : std_ulogic; signal RXCLKCORCNT_out : std_logic_vector(2 downto 0); signal RXCOMMADET_out : std_ulogic; signal RXCRCERR_out : std_ulogic; signal RXDATA_out : std_logic_vector(31 downto 0); signal RXDISPERR_out : std_logic_vector(3 downto 0); signal RXLOSSOFSYNC_out : std_logic_vector(1 downto 0); signal RXNOTINTABLE_out : std_logic_vector(3 downto 0); signal RXREALIGN_out : std_ulogic; signal RXRECCLK_out : std_ulogic; signal RXRUNDISP_out : std_logic_vector(3 downto 0); signal TXBUFERR_out : std_ulogic; signal TXKERR_out : std_logic_vector(3 downto 0); signal TXN_out : std_ulogic; signal TXP_out : std_ulogic; signal TXRUNDISP_out : std_logic_vector(3 downto 0); signal BREFCLK_ipd : std_ulogic; signal BREFCLK2_ipd : std_ulogic; signal CHBONDI_ipd : std_logic_vector(3 downto 0); signal CONFIGENABLE_ipd : std_ulogic; signal CONFIGIN_ipd : std_ulogic; signal ENCHANSYNC_ipd : std_ulogic; signal ENMCOMMAALIGN_ipd : std_ulogic; signal ENPCOMMAALIGN_ipd : std_ulogic; signal LOOPBACK_ipd : std_logic_vector(1 downto 0); signal POWERDOWN_ipd : std_ulogic; signal REFCLK_ipd : std_ulogic; signal REFCLK2_ipd : std_ulogic; signal REFCLKSEL_ipd : std_ulogic; signal RXN_ipd : std_ulogic; signal RXP_ipd : std_ulogic; signal RXPOLARITY_ipd : std_ulogic; signal RXRESET_ipd : std_ulogic; signal RXUSRCLK_ipd : std_ulogic; signal RXUSRCLK2_ipd : std_ulogic; signal TXBYPASS8B10B_ipd : std_logic_vector(3 downto 0); signal TXCHARDISPMODE_ipd : std_logic_vector(3 downto 0); signal TXCHARDISPVAL_ipd : std_logic_vector(3 downto 0); signal TXCHARISK_ipd : std_logic_vector(3 downto 0); signal TXDATA_ipd : std_logic_vector(31 downto 0); signal TXFORCECRCERR_ipd : std_ulogic; signal TXINHIBIT_ipd : std_ulogic; signal TXPOLARITY_ipd : std_ulogic; signal TXRESET_ipd : std_ulogic; signal TXUSRCLK_ipd : std_ulogic; signal TXUSRCLK2_ipd : std_ulogic; begin BREFCLK_ipd <= BREFCLK after in_delay; BREFCLK2_ipd <= BREFCLK2 after in_delay; CHBONDI_ipd <= CHBONDI after in_delay; CONFIGENABLE_ipd <= CONFIGENABLE after in_delay; CONFIGIN_ipd <= CONFIGIN after in_delay; ENCHANSYNC_ipd <= ENCHANSYNC after in_delay; ENMCOMMAALIGN_ipd <= ENMCOMMAALIGN after in_delay; ENPCOMMAALIGN_ipd <= ENPCOMMAALIGN after in_delay; LOOPBACK_ipd <= LOOPBACK after in_delay; POWERDOWN_ipd <= POWERDOWN after in_delay; REFCLK_ipd <= REFCLK after in_delay; REFCLK2_ipd <= REFCLK2 after in_delay; REFCLKSEL_ipd <= REFCLKSEL after in_delay; RXN_ipd <= RXN after in_delay; RXP_ipd <= RXP after in_delay; RXPOLARITY_ipd <= RXPOLARITY after in_delay; RXRESET_ipd <= RXRESET after in_delay; RXUSRCLK_ipd <= RXUSRCLK after in_delay; RXUSRCLK2_ipd <= RXUSRCLK2 after in_delay; TXBYPASS8B10B_ipd <= TXBYPASS8B10B after in_delay; TXCHARDISPMODE_ipd <= TXCHARDISPMODE after in_delay; TXCHARDISPVAL_ipd <= TXCHARDISPVAL after in_delay; TXCHARISK_ipd <= TXCHARISK after in_delay; TXDATA_ipd <= TXDATA after in_delay; TXFORCECRCERR_ipd <= TXFORCECRCERR after in_delay; TXINHIBIT_ipd <= TXINHIBIT after in_delay; TXPOLARITY_ipd <= TXPOLARITY after in_delay; TXRESET_ipd <= TXRESET after in_delay; TXUSRCLK_ipd <= TXUSRCLK after in_delay; TXUSRCLK2_ipd <= TXUSRCLK2 after in_delay; gt_swift_bw_1 : GT_SWIFT_BUS port map ( ALIGN_COMMA_MSB => ALIGN_COMMA_MSB_BINARY, BREFCLK => BREFCLK_ipd, BREFCLK2 => BREFCLK2_ipd, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT_BINARY, CHAN_BOND_MODE => CHAN_BOND_MODE_BINARY, CHAN_BOND_OFFSET => CHAN_BOND_OFFSET_BINARY, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT_BINARY, CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1_BINARY, CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2_BINARY, CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3_BINARY, CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4_BINARY, CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1_BINARY, CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2_BINARY, CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3_BINARY, CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4_BINARY, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE_BINARY, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN_BINARY, CHAN_BOND_WAIT => CHAN_BOND_WAIT_BINARY, CHBONDDONE => CHBONDDONE_out, CHBONDI => CHBONDI_ipd, CHBONDO => CHBONDO_out, CLK_CORRECT_USE => CLK_CORRECT_USE_BINARY, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG_BINARY, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE_BINARY, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT_BINARY, CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1_BINARY, CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2_BINARY, CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3_BINARY, CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4_BINARY, CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1_BINARY, CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2_BINARY, CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3_BINARY, CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4_BINARY, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE_BINARY, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN_BINARY, COMMA_10B_MASK => COMMA_10B_MASK_BINARY, CONFIGENABLE => CONFIGENABLE_ipd, CONFIGIN => CONFIGIN_ipd, CONFIGOUT => CONFIGOUT_out, CRC_END_OF_PKT => CRC_END_OF_PKT_BINARY, CRC_FORMAT => CRC_FORMAT_BINARY, CRC_START_OF_PKT => CRC_START_OF_PKT_BINARY, DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT_BINARY, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT_BINARY, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY_BINARY, ENCHANSYNC => ENCHANSYNC_ipd, ENMCOMMAALIGN => ENMCOMMAALIGN_ipd, ENPCOMMAALIGN => ENPCOMMAALIGN_ipd, GSR => GSR, LOOPBACK => LOOPBACK_ipd, MCOMMA_10B_VALUE => MCOMMA_10B_VALUE_BINARY, MCOMMA_DETECT => MCOMMA_DETECT_BINARY, PCOMMA_10B_VALUE => PCOMMA_10B_VALUE_BINARY, PCOMMA_DETECT => PCOMMA_DETECT_BINARY, POWERDOWN => POWERDOWN_ipd, REFCLK => REFCLK_ipd, REFCLK2 => REFCLK2_ipd, REFCLKSEL => REFCLKSEL_ipd, REF_CLK_V_SEL => REF_CLK_V_SEL_BINARY, RXBUFSTATUS => RXBUFSTATUS_out, RXCHARISCOMMA => RXCHARISCOMMA_out, RXCHARISK => RXCHARISK_out, RXCHECKINGCRC => RXCHECKINGCRC_out, RXCLKCORCNT => RXCLKCORCNT_out, RXCOMMADET => RXCOMMADET_out, RXCRCERR => RXCRCERR_out, RXDATA => RXDATA_out, RXDISPERR => RXDISPERR_out, RXLOSSOFSYNC => RXLOSSOFSYNC_out, RXN => RXN_ipd, RXNOTINTABLE => RXNOTINTABLE_out, RXP => RXP_ipd, RXPOLARITY => RXPOLARITY_ipd, RXREALIGN => RXREALIGN_out, RXRECCLK => RXRECCLK_out, RXRESET => RXRESET_ipd, RXRUNDISP => RXRUNDISP_out, RXUSRCLK => RXUSRCLK_ipd, RXUSRCLK2 => RXUSRCLK2_ipd, RX_BUFFER_USE => RX_BUFFER_USE_BINARY, RX_CRC_USE => RX_CRC_USE_BINARY, RX_DATA_WIDTH => RX_DATA_WIDTH_BINARY, RX_DECODE_USE => RX_DECODE_USE_BINARY, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM_BINARY, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR_BINARY, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD_BINARY, SERDES_10B => SERDES_10B_BINARY, TERMINATION_IMP => TERMINATION_IMP_BINARY, TXBUFERR => TXBUFERR_out, TXBYPASS8B10B => TXBYPASS8B10B_ipd, TXCHARDISPMODE => TXCHARDISPMODE_ipd, TXCHARDISPVAL => TXCHARDISPVAL_ipd, TXCHARISK => TXCHARISK_ipd, TXDATA => TXDATA_ipd, TXFORCECRCERR => TXFORCECRCERR_ipd, TXINHIBIT => TXINHIBIT_ipd, TXKERR => TXKERR_out, TXN => TXN_out, TXP => TXP_out, TXPOLARITY => TXPOLARITY_ipd, TXRESET => TXRESET_ipd, TXRUNDISP => TXRUNDISP_out, TXUSRCLK => TXUSRCLK_ipd, TXUSRCLK2 => TXUSRCLK2_ipd, TX_BUFFER_USE => TX_BUFFER_USE_BINARY, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE_BINARY, TX_CRC_USE => TX_CRC_USE_BINARY, TX_DATA_WIDTH => TX_DATA_WIDTH_BINARY, TX_DIFF_CTRL => TX_DIFF_CTRL_BINARY, TX_PREEMPHASIS => TX_PREEMPHASIS_BINARY ); INIPROC : process begin case ALIGN_COMMA_MSB is when FALSE => ALIGN_COMMA_MSB_BINARY <= '0'; when TRUE => ALIGN_COMMA_MSB_BINARY <= '1'; when others => assert FALSE report "Error : ALIGN_COMMA_MSB is neither TRUE nor FALSE." severity warning; end case; case CHAN_BOND_LIMIT is when 1 => CHAN_BOND_LIMIT_BINARY <= "00001"; when 2 => CHAN_BOND_LIMIT_BINARY <= "00010"; when 3 => CHAN_BOND_LIMIT_BINARY <= "00011"; when 4 => CHAN_BOND_LIMIT_BINARY <= "00100"; when 5 => CHAN_BOND_LIMIT_BINARY <= "00101"; when 6 => CHAN_BOND_LIMIT_BINARY <= "00110"; when 7 => CHAN_BOND_LIMIT_BINARY <= "00111"; when 8 => CHAN_BOND_LIMIT_BINARY <= "01000"; when 9 => CHAN_BOND_LIMIT_BINARY <= "01001"; when 10 => CHAN_BOND_LIMIT_BINARY <= "01010"; when 11 => CHAN_BOND_LIMIT_BINARY <= "01011"; when 12 => CHAN_BOND_LIMIT_BINARY <= "01100"; when 13 => CHAN_BOND_LIMIT_BINARY <= "01101"; when 14 => CHAN_BOND_LIMIT_BINARY <= "01110"; when 15 => CHAN_BOND_LIMIT_BINARY <= "01111"; when 16 => CHAN_BOND_LIMIT_BINARY <= "10000"; when 17 => CHAN_BOND_LIMIT_BINARY <= "10001"; when 18 => CHAN_BOND_LIMIT_BINARY <= "10010"; when 19 => CHAN_BOND_LIMIT_BINARY <= "10011"; when 20 => CHAN_BOND_LIMIT_BINARY <= "10100"; when 21 => CHAN_BOND_LIMIT_BINARY <= "10101"; when 22 => CHAN_BOND_LIMIT_BINARY <= "10110"; when 23 => CHAN_BOND_LIMIT_BINARY <= "10111"; when 24 => CHAN_BOND_LIMIT_BINARY <= "11000"; when 25 => CHAN_BOND_LIMIT_BINARY <= "11001"; when 26 => CHAN_BOND_LIMIT_BINARY <= "11010"; when 27 => CHAN_BOND_LIMIT_BINARY <= "11011"; when 28 => CHAN_BOND_LIMIT_BINARY <= "11100"; when 29 => CHAN_BOND_LIMIT_BINARY <= "11101"; when 30 => CHAN_BOND_LIMIT_BINARY <= "11110"; when 31 => CHAN_BOND_LIMIT_BINARY <= "11111"; when others => assert FALSE report "Error : CHAN_BOND_LIMIT is not in range 1...31." severity warning; end case; -- case CHAN_BOND_MODE is if((CHAN_BOND_MODE = "OFF") or (CHAN_BOND_MODE = "off")) then CHAN_BOND_MODE_BINARY <= "00"; elsif((CHAN_BOND_MODE = "MASTER") or (CHAN_BOND_MODE = "master")) then CHAN_BOND_MODE_BINARY <= "01"; elsif((CHAN_BOND_MODE = "SLAVE_1_HOP") or (CHAN_BOND_MODE = "slave_1_hop")) then CHAN_BOND_MODE_BINARY <= "10"; elsif((CHAN_BOND_MODE = "SLAVE_2_HOPS") or (CHAN_BOND_MODE = "slave_2_hops")) then CHAN_BOND_MODE_BINARY <= "11"; else assert FALSE report "Error : CHAN_BOND_MODE = is not OFF, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS." severity warning; end if; -- end case; case CHAN_BOND_OFFSET is when 0 => CHAN_BOND_OFFSET_BINARY <= "0000"; when 1 => CHAN_BOND_OFFSET_BINARY <= "0001"; when 2 => CHAN_BOND_OFFSET_BINARY <= "0010"; when 3 => CHAN_BOND_OFFSET_BINARY <= "0011"; when 4 => CHAN_BOND_OFFSET_BINARY <= "0100"; when 5 => CHAN_BOND_OFFSET_BINARY <= "0101"; when 6 => CHAN_BOND_OFFSET_BINARY <= "0110"; when 7 => CHAN_BOND_OFFSET_BINARY <= "0111"; when 8 => CHAN_BOND_OFFSET_BINARY <= "1000"; when 9 => CHAN_BOND_OFFSET_BINARY <= "1001"; when 10 => CHAN_BOND_OFFSET_BINARY <= "1010"; when 11 => CHAN_BOND_OFFSET_BINARY <= "1011"; when 12 => CHAN_BOND_OFFSET_BINARY <= "1100"; when 13 => CHAN_BOND_OFFSET_BINARY <= "1101"; when 14 => CHAN_BOND_OFFSET_BINARY <= "1110"; when 15 => CHAN_BOND_OFFSET_BINARY <= "1111"; when others => assert FALSE report "Error : CHAN_BOND_OFFSET is not in range 0...15." severity warning; end case; case CHAN_BOND_ONE_SHOT is when FALSE => CHAN_BOND_ONE_SHOT_BINARY <= '0'; when TRUE => CHAN_BOND_ONE_SHOT_BINARY <= '1'; when others => assert FALSE report "Error : CHAN_BOND_ONE_SHOT is neither TRUE nor FALSE." severity warning; end case; case CHAN_BOND_SEQ_2_USE is when FALSE => CHAN_BOND_SEQ_2_USE_BINARY <= '0'; when TRUE => CHAN_BOND_SEQ_2_USE_BINARY <= '1'; when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE is neither TRUE nor FALSE." severity warning; end case; case CHAN_BOND_SEQ_LEN is when 1 => CHAN_BOND_SEQ_LEN_BINARY <= "01"; when 2 => CHAN_BOND_SEQ_LEN_BINARY <= "10"; when 3 => CHAN_BOND_SEQ_LEN_BINARY <= "11"; when 4 => CHAN_BOND_SEQ_LEN_BINARY <= "00"; when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN is not in range 1...4." severity warning; end case; case CHAN_BOND_WAIT is when 1 => CHAN_BOND_WAIT_BINARY <= "0001"; when 2 => CHAN_BOND_WAIT_BINARY <= "0010"; when 3 => CHAN_BOND_WAIT_BINARY <= "0011"; when 4 => CHAN_BOND_WAIT_BINARY <= "0100"; when 5 => CHAN_BOND_WAIT_BINARY <= "0101"; when 6 => CHAN_BOND_WAIT_BINARY <= "0110"; when 7 => CHAN_BOND_WAIT_BINARY <= "0111"; when 8 => CHAN_BOND_WAIT_BINARY <= "1000"; when 9 => CHAN_BOND_WAIT_BINARY <= "1001"; when 10 => CHAN_BOND_WAIT_BINARY <= "1010"; when 11 => CHAN_BOND_WAIT_BINARY <= "1011"; when 12 => CHAN_BOND_WAIT_BINARY <= "1100"; when 13 => CHAN_BOND_WAIT_BINARY <= "1101"; when 14 => CHAN_BOND_WAIT_BINARY <= "1110"; when 15 => CHAN_BOND_WAIT_BINARY <= "1111"; when others => assert FALSE report "Error : CHAN_BOND_WAIT is not in range 1...15." severity warning; end case; case CLK_COR_INSERT_IDLE_FLAG is when FALSE => CLK_COR_INSERT_IDLE_FLAG_BINARY <= '0'; when TRUE => CLK_COR_INSERT_IDLE_FLAG_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG is neither TRUE nor FALSE." severity warning; end case; case CLK_COR_KEEP_IDLE is when FALSE => CLK_COR_KEEP_IDLE_BINARY <= '0'; when TRUE => CLK_COR_KEEP_IDLE_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE is neither TRUE nor FALSE." severity warning; end case; case CLK_COR_REPEAT_WAIT is when 0 => CLK_COR_REPEAT_WAIT_BINARY <= "00000"; when 1 => CLK_COR_REPEAT_WAIT_BINARY <= "00001"; when 2 => CLK_COR_REPEAT_WAIT_BINARY <= "00010"; when 3 => CLK_COR_REPEAT_WAIT_BINARY <= "00011"; when 4 => CLK_COR_REPEAT_WAIT_BINARY <= "00100"; when 5 => CLK_COR_REPEAT_WAIT_BINARY <= "00101"; when 6 => CLK_COR_REPEAT_WAIT_BINARY <= "00110"; when 7 => CLK_COR_REPEAT_WAIT_BINARY <= "00111"; when 8 => CLK_COR_REPEAT_WAIT_BINARY <= "01000"; when 9 => CLK_COR_REPEAT_WAIT_BINARY <= "01001"; when 10 => CLK_COR_REPEAT_WAIT_BINARY <= "01010"; when 11 => CLK_COR_REPEAT_WAIT_BINARY <= "01011"; when 12 => CLK_COR_REPEAT_WAIT_BINARY <= "01100"; when 13 => CLK_COR_REPEAT_WAIT_BINARY <= "01101"; when 14 => CLK_COR_REPEAT_WAIT_BINARY <= "01110"; when 15 => CLK_COR_REPEAT_WAIT_BINARY <= "01111"; when 16 => CLK_COR_REPEAT_WAIT_BINARY <= "10000"; when 17 => CLK_COR_REPEAT_WAIT_BINARY <= "10001"; when 18 => CLK_COR_REPEAT_WAIT_BINARY <= "10010"; when 19 => CLK_COR_REPEAT_WAIT_BINARY <= "10011"; when 20 => CLK_COR_REPEAT_WAIT_BINARY <= "10100"; when 21 => CLK_COR_REPEAT_WAIT_BINARY <= "10101"; when 22 => CLK_COR_REPEAT_WAIT_BINARY <= "10110"; when 23 => CLK_COR_REPEAT_WAIT_BINARY <= "10111"; when 24 => CLK_COR_REPEAT_WAIT_BINARY <= "11000"; when 25 => CLK_COR_REPEAT_WAIT_BINARY <= "11001"; when 26 => CLK_COR_REPEAT_WAIT_BINARY <= "11010"; when 27 => CLK_COR_REPEAT_WAIT_BINARY <= "11011"; when 28 => CLK_COR_REPEAT_WAIT_BINARY <= "11100"; when 29 => CLK_COR_REPEAT_WAIT_BINARY <= "11101"; when 30 => CLK_COR_REPEAT_WAIT_BINARY <= "11110"; when 31 => CLK_COR_REPEAT_WAIT_BINARY <= "11111"; when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT is not in range 0...31." severity warning; end case; case CLK_COR_SEQ_2_USE is when FALSE => CLK_COR_SEQ_2_USE_BINARY <= '0'; when TRUE => CLK_COR_SEQ_2_USE_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE is neither TRUE nor FALSE." severity warning; end case; case CLK_COR_SEQ_LEN is when 1 => CLK_COR_SEQ_LEN_BINARY <= "01"; when 2 => CLK_COR_SEQ_LEN_BINARY <= "10"; when 3 => CLK_COR_SEQ_LEN_BINARY <= "11"; when 4 => CLK_COR_SEQ_LEN_BINARY <= "00"; when others => assert FALSE report "Error : CLK_COR_SEQ_LEN is not in range 1...4." severity warning; end case; case CLK_CORRECT_USE is when FALSE => CLK_CORRECT_USE_BINARY <= '0'; when TRUE => CLK_CORRECT_USE_BINARY <= '1'; when others => assert FALSE report "Error : CLK_CORRECT_USE is neither TRUE nor FALSE." severity warning; end case; -- case CRC_END_OF_PKT is if((CRC_END_OF_PKT = "K28_0") or (CRC_END_OF_PKT = "k28_0")) then CRC_END_OF_PKT_BINARY <= "00011100"; elsif((CRC_END_OF_PKT = "K28_1") or (CRC_END_OF_PKT = "k28_1")) then CRC_END_OF_PKT_BINARY <= "00111100"; elsif((CRC_END_OF_PKT = "K28_2") or (CRC_END_OF_PKT = "k28_2")) then CRC_END_OF_PKT_BINARY <= "01011100"; elsif((CRC_END_OF_PKT = "K28_3") or (CRC_END_OF_PKT = "k28_3")) then CRC_END_OF_PKT_BINARY <= "01111100"; elsif((CRC_END_OF_PKT = "K28_4") or (CRC_END_OF_PKT = "k28_4")) then CRC_END_OF_PKT_BINARY <= "10011100"; elsif((CRC_END_OF_PKT = "K28_5") or (CRC_END_OF_PKT = "k28_5")) then CRC_END_OF_PKT_BINARY <= "10111100"; elsif((CRC_END_OF_PKT = "K28_6") or (CRC_END_OF_PKT = "k28_6")) then CRC_END_OF_PKT_BINARY <= "11011100"; elsif((CRC_END_OF_PKT = "K28_7") or (CRC_END_OF_PKT = "k28_7")) then CRC_END_OF_PKT_BINARY <= "11111100"; elsif((CRC_END_OF_PKT = "K23_7") or (CRC_END_OF_PKT = "k23_7")) then CRC_END_OF_PKT_BINARY <= "11110111"; elsif((CRC_END_OF_PKT = "K27_7") or (CRC_END_OF_PKT = "k27_7")) then CRC_END_OF_PKT_BINARY <= "11111011"; elsif((CRC_END_OF_PKT = "K29_7") or (CRC_END_OF_PKT = "k29_7")) then CRC_END_OF_PKT_BINARY <= "11111101"; elsif((CRC_END_OF_PKT = "K30_7") or (CRC_END_OF_PKT = "k30_7")) then CRC_END_OF_PKT_BINARY <= "11111110"; else assert FALSE report "Error : CRC_END_OF_PKT = is not K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7, K29_7, K30_7." severity warning; end if; -- end case; -- case CRC_FORMAT is if((CRC_FORMAT = "USER_MODE") or (CRC_FORMAT = "user_mode")) then CRC_FORMAT_BINARY <= "00"; elsif((CRC_FORMAT = "ETHERNET") or (CRC_FORMAT = "ethernet")) then CRC_FORMAT_BINARY <= "01"; elsif((CRC_FORMAT = "INFINIBAND") or (CRC_FORMAT = "infiniband")) then CRC_FORMAT_BINARY <= "10"; elsif((CRC_FORMAT = "FIBRE_CHAN") or (CRC_FORMAT = "fibre_chan")) then CRC_FORMAT_BINARY <= "11"; else assert FALSE report "Error : CRC_FORMAT = is not USER_MODE, ETHERNET, INFINIBAND, FIBRE_CHAN." severity warning; end if; -- end case; -- case CRC_START_OF_PKT is if((CRC_START_OF_PKT = "K28_0") or (CRC_START_OF_PKT = "k28_0")) then CRC_START_OF_PKT_BINARY <= "00011100"; elsif((CRC_START_OF_PKT = "K28_1") or (CRC_START_OF_PKT = "k28_1")) then CRC_START_OF_PKT_BINARY <= "00111100"; elsif((CRC_START_OF_PKT = "K28_2") or (CRC_START_OF_PKT = "k28_2")) then CRC_START_OF_PKT_BINARY <= "01011100"; elsif((CRC_START_OF_PKT = "K28_3") or (CRC_START_OF_PKT = "k28_3")) then CRC_START_OF_PKT_BINARY <= "01111100"; elsif((CRC_START_OF_PKT = "K28_4") or (CRC_START_OF_PKT = "k28_4")) then CRC_START_OF_PKT_BINARY <= "10011100"; elsif((CRC_START_OF_PKT = "K28_5") or (CRC_START_OF_PKT = "k28_5")) then CRC_START_OF_PKT_BINARY <= "10111100"; elsif((CRC_START_OF_PKT = "K28_6") or (CRC_START_OF_PKT = "k28_6")) then CRC_START_OF_PKT_BINARY <= "11011100"; elsif((CRC_START_OF_PKT = "K28_7") or (CRC_START_OF_PKT = "k28_7")) then CRC_START_OF_PKT_BINARY <= "11111100"; elsif((CRC_START_OF_PKT = "K23_7") or (CRC_START_OF_PKT = "k23_7")) then CRC_START_OF_PKT_BINARY <= "11110111"; elsif((CRC_START_OF_PKT = "K27_7") or (CRC_START_OF_PKT = "k27_7")) then CRC_START_OF_PKT_BINARY <= "11111011"; elsif((CRC_START_OF_PKT = "K29_7") or (CRC_START_OF_PKT = "k29_7")) then CRC_START_OF_PKT_BINARY <= "11111101"; elsif((CRC_START_OF_PKT = "K30_7") or (CRC_START_OF_PKT = "k30_7")) then CRC_START_OF_PKT_BINARY <= "11111110"; else assert FALSE report "Error : CRC_START_OF_PKT = is not K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7, K29_7, K30_7." severity warning; end if; -- end case; case DEC_MCOMMA_DETECT is when FALSE => DEC_MCOMMA_DETECT_BINARY <= '0'; when TRUE => DEC_MCOMMA_DETECT_BINARY <= '1'; when others => assert FALSE report "Error : DEC_MCOMMA_DETECT is neither TRUE nor FALSE." severity warning; end case; case DEC_PCOMMA_DETECT is when FALSE => DEC_PCOMMA_DETECT_BINARY <= '0'; when TRUE => DEC_PCOMMA_DETECT_BINARY <= '1'; when others => assert FALSE report "Error : DEC_PCOMMA_DETECT is neither TRUE nor FALSE." severity warning; end case; case DEC_VALID_COMMA_ONLY is when FALSE => DEC_VALID_COMMA_ONLY_BINARY <= '0'; when TRUE => DEC_VALID_COMMA_ONLY_BINARY <= '1'; when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY is neither TRUE nor FALSE." severity warning; end case; case MCOMMA_DETECT is when FALSE => MCOMMA_DETECT_BINARY <= '0'; when TRUE => MCOMMA_DETECT_BINARY <= '1'; when others => assert FALSE report "Error : MCOMMA_DETECT is neither TRUE nor FALSE." severity warning; end case; case PCOMMA_DETECT is when FALSE => PCOMMA_DETECT_BINARY <= '0'; when TRUE => PCOMMA_DETECT_BINARY <= '1'; when others => assert FALSE report "Error : PCOMMA_DETECT is neither TRUE nor FALSE." severity warning; end case; case REF_CLK_V_SEL is when 0 => REF_CLK_V_SEL_BINARY <= '0'; when 1 => REF_CLK_V_SEL_BINARY <= '1'; when others => assert FALSE report "Error : REF_CLK_V_SEL is not in 0, 1." severity warning; end case; case RX_BUFFER_USE is when FALSE => RX_BUFFER_USE_BINARY <= '0'; when TRUE => RX_BUFFER_USE_BINARY <= '1'; when others => assert FALSE report "Error : RX_BUFFER_USE is neither TRUE nor FALSE." severity warning; end case; case RX_CRC_USE is when FALSE => RX_CRC_USE_BINARY <= '0'; when TRUE => RX_CRC_USE_BINARY <= '1'; when others => assert FALSE report "Error : RX_CRC_USE is neither TRUE nor FALSE." severity warning; end case; case RX_DATA_WIDTH is when 1 => RX_DATA_WIDTH_BINARY <= "01"; when 2 => RX_DATA_WIDTH_BINARY <= "10"; when 4 => RX_DATA_WIDTH_BINARY <= "00"; when others => assert FALSE report "Error : RX_DATA_WIDTH is not in 1, 2, 4." severity warning; end case; case RX_DECODE_USE is when FALSE => RX_DECODE_USE_BINARY <= '0'; when TRUE => RX_DECODE_USE_BINARY <= '1'; when others => assert FALSE report "Error : RX_DECODE_USE is neither TRUE nor FALSE." severity warning; end case; case RX_LOS_INVALID_INCR is when 1 => RX_LOS_INVALID_INCR_BINARY <= "000"; when 2 => RX_LOS_INVALID_INCR_BINARY <= "001"; when 4 => RX_LOS_INVALID_INCR_BINARY <= "010"; when 8 => RX_LOS_INVALID_INCR_BINARY <= "011"; when 16 => RX_LOS_INVALID_INCR_BINARY <= "100"; when 32 => RX_LOS_INVALID_INCR_BINARY <= "101"; when 64 => RX_LOS_INVALID_INCR_BINARY <= "110"; when 128 => RX_LOS_INVALID_INCR_BINARY <= "111"; when others => assert FALSE report "Error : RX_LOS_INVALID_INCR is not in 1, 2, 4, 8, 16, 32, 64, 128." severity warning; end case; case RX_LOS_THRESHOLD is when 4 => RX_LOS_THRESHOLD_BINARY <= "000"; when 8 => RX_LOS_THRESHOLD_BINARY <= "001"; when 16 => RX_LOS_THRESHOLD_BINARY <= "010"; when 32 => RX_LOS_THRESHOLD_BINARY <= "011"; when 64 => RX_LOS_THRESHOLD_BINARY <= "100"; when 128 => RX_LOS_THRESHOLD_BINARY <= "101"; when 256 => RX_LOS_THRESHOLD_BINARY <= "110"; when 512 => RX_LOS_THRESHOLD_BINARY <= "111"; when others => assert FALSE report "Error : RX_LOS_THRESHOLD is not in 4, 8, 16, 32, 64, 128, 256, 512." severity warning; end case; case RX_LOSS_OF_SYNC_FSM is when FALSE => RX_LOSS_OF_SYNC_FSM_BINARY <= '0'; when TRUE => RX_LOSS_OF_SYNC_FSM_BINARY <= '1'; when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM is neither TRUE nor FALSE." severity warning; end case; case SERDES_10B is when FALSE => SERDES_10B_BINARY <= '0'; when TRUE => SERDES_10B_BINARY <= '1'; when others => assert FALSE report "Error : SERDES_10B is neither TRUE nor FALSE." severity warning; end case; case TERMINATION_IMP is when 50 => TERMINATION_IMP_BINARY <= '0'; when 75 => TERMINATION_IMP_BINARY <= '1'; when others => assert FALSE report "Error : TERMINATION_IMP is not in 50, 75." severity warning; end case; case TX_BUFFER_USE is when FALSE => TX_BUFFER_USE_BINARY <= '0'; when TRUE => TX_BUFFER_USE_BINARY <= '1'; when others => assert FALSE report "Error : TX_BUFFER_USE is neither TRUE nor FALSE." severity warning; end case; case TX_CRC_USE is when FALSE => TX_CRC_USE_BINARY <= '0'; when TRUE => TX_CRC_USE_BINARY <= '1'; when others => assert FALSE report "Error : TX_CRC_USE is neither TRUE nor FALSE." severity warning; end case; case TX_DATA_WIDTH is when 1 => TX_DATA_WIDTH_BINARY <= "01"; when 2 => TX_DATA_WIDTH_BINARY <= "10"; when 4 => TX_DATA_WIDTH_BINARY <= "00"; when others => assert FALSE report "Error : TX_DATA_WIDTH is not in 1, 2, 4." severity warning; end case; case TX_DIFF_CTRL is when 400 => TX_DIFF_CTRL_BINARY <= "010"; when 500 => TX_DIFF_CTRL_BINARY <= "000"; when 600 => TX_DIFF_CTRL_BINARY <= "001"; when 700 => TX_DIFF_CTRL_BINARY <= "011"; when 800 => TX_DIFF_CTRL_BINARY <= "110"; when others => assert FALSE report "Error : TX_DIFF_CTRL is not in 400, 500, 600, 700, 800." severity warning; end case; case TX_PREEMPHASIS is when 0 => TX_PREEMPHASIS_BINARY <= "00"; when 1 => TX_PREEMPHASIS_BINARY <= "01"; when 2 => TX_PREEMPHASIS_BINARY <= "10"; when 3 => TX_PREEMPHASIS_BINARY <= "11"; when others => assert FALSE report "Error : TX_PREEMPHASIS is not in 0, 1, 2, 3." severity warning; end case; wait; end process INIPROC; TIMING : process -- Pin timing violations (clock input pins) -- Pin Timing Violations (all input pins) -- Output Pin glitch declaration variable CHBONDDONE_GlitchData : VitalGlitchDataType; variable CHBONDO0_GlitchData : VitalGlitchDataType; variable CHBONDO1_GlitchData : VitalGlitchDataType; variable CHBONDO2_GlitchData : VitalGlitchDataType; variable CHBONDO3_GlitchData : VitalGlitchDataType; variable CONFIGOUT_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS0_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS1_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA0_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA1_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA2_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA3_GlitchData : VitalGlitchDataType; variable RXCHARISK0_GlitchData : VitalGlitchDataType; variable RXCHARISK1_GlitchData : VitalGlitchDataType; variable RXCHARISK2_GlitchData : VitalGlitchDataType; variable RXCHARISK3_GlitchData : VitalGlitchDataType; variable RXCHECKINGCRC_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT0_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT1_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT2_GlitchData : VitalGlitchDataType; variable RXCOMMADET_GlitchData : VitalGlitchDataType; variable RXCRCERR_GlitchData : VitalGlitchDataType; variable RXDATA0_GlitchData : VitalGlitchDataType; variable RXDATA1_GlitchData : VitalGlitchDataType; variable RXDATA2_GlitchData : VitalGlitchDataType; variable RXDATA3_GlitchData : VitalGlitchDataType; variable RXDATA4_GlitchData : VitalGlitchDataType; variable RXDATA5_GlitchData : VitalGlitchDataType; variable RXDATA6_GlitchData : VitalGlitchDataType; variable RXDATA7_GlitchData : VitalGlitchDataType; variable RXDATA8_GlitchData : VitalGlitchDataType; variable RXDATA9_GlitchData : VitalGlitchDataType; variable RXDATA10_GlitchData : VitalGlitchDataType; variable RXDATA11_GlitchData : VitalGlitchDataType; variable RXDATA12_GlitchData : VitalGlitchDataType; variable RXDATA13_GlitchData : VitalGlitchDataType; variable RXDATA14_GlitchData : VitalGlitchDataType; variable RXDATA15_GlitchData : VitalGlitchDataType; variable RXDATA16_GlitchData : VitalGlitchDataType; variable RXDATA17_GlitchData : VitalGlitchDataType; variable RXDATA18_GlitchData : VitalGlitchDataType; variable RXDATA19_GlitchData : VitalGlitchDataType; variable RXDATA20_GlitchData : VitalGlitchDataType; variable RXDATA21_GlitchData : VitalGlitchDataType; variable RXDATA22_GlitchData : VitalGlitchDataType; variable RXDATA23_GlitchData : VitalGlitchDataType; variable RXDATA24_GlitchData : VitalGlitchDataType; variable RXDATA25_GlitchData : VitalGlitchDataType; variable RXDATA26_GlitchData : VitalGlitchDataType; variable RXDATA27_GlitchData : VitalGlitchDataType; variable RXDATA28_GlitchData : VitalGlitchDataType; variable RXDATA29_GlitchData : VitalGlitchDataType; variable RXDATA30_GlitchData : VitalGlitchDataType; variable RXDATA31_GlitchData : VitalGlitchDataType; variable RXDISPERR0_GlitchData : VitalGlitchDataType; variable RXDISPERR1_GlitchData : VitalGlitchDataType; variable RXDISPERR2_GlitchData : VitalGlitchDataType; variable RXDISPERR3_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC0_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC1_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE0_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE1_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE2_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE3_GlitchData : VitalGlitchDataType; variable RXREALIGN_GlitchData : VitalGlitchDataType; -- variable RXRECCLK_GlitchData : VitalGlitchDataType; variable RXRUNDISP0_GlitchData : VitalGlitchDataType; variable RXRUNDISP1_GlitchData : VitalGlitchDataType; variable RXRUNDISP2_GlitchData : VitalGlitchDataType; variable RXRUNDISP3_GlitchData : VitalGlitchDataType; variable TXBUFERR_GlitchData : VitalGlitchDataType; variable TXKERR0_GlitchData : VitalGlitchDataType; variable TXKERR1_GlitchData : VitalGlitchDataType; variable TXKERR2_GlitchData : VitalGlitchDataType; variable TXKERR3_GlitchData : VitalGlitchDataType; -- variable TXN_GlitchData : VitalGlitchDataType; -- variable TXP_GlitchData : VitalGlitchDataType; variable TXRUNDISP0_GlitchData : VitalGlitchDataType; variable TXRUNDISP1_GlitchData : VitalGlitchDataType; variable TXRUNDISP2_GlitchData : VitalGlitchDataType; variable TXRUNDISP3_GlitchData : VitalGlitchDataType; begin -- Setup/Hold Check Violations (all input pins) -- End of (TimingChecksOn) -- Output-to-Clock path delay VitalPathDelay01 ( OutSignal => CHBONDDONE, GlitchData => CHBONDDONE_GlitchData, OutSignalName => "CHBONDDONE", OutTemp => CHBONDDONE_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(0), GlitchData => CHBONDO0_GlitchData, OutSignalName => "CHBONDO(0)", OutTemp => CHBONDO_OUT(0), Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(1), GlitchData => CHBONDO1_GlitchData, OutSignalName => "CHBONDO(1)", OutTemp => CHBONDO_OUT(1), Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(2), GlitchData => CHBONDO2_GlitchData, OutSignalName => "CHBONDO(2)", OutTemp => CHBONDO_OUT(2), Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(3), GlitchData => CHBONDO3_GlitchData, OutSignalName => "CHBONDO(3)", OutTemp => CHBONDO_OUT(3), Paths => (0 => (RXUSRCLK_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CONFIGOUT, GlitchData => CONFIGOUT_GlitchData, OutSignalName => "CONFIGOUT", OutTemp => CONFIGOUT_OUT, Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS(0), GlitchData => RXBUFSTATUS0_GlitchData, OutSignalName => "RXBUFSTATUS(0)", OutTemp => RXBUFSTATUS_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS(1), GlitchData => RXBUFSTATUS1_GlitchData, OutSignalName => "RXBUFSTATUS(1)", OutTemp => RXBUFSTATUS_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(0), GlitchData => RXCHARISCOMMA0_GlitchData, OutSignalName => "RXCHARISCOMMA(0)", OutTemp => RXCHARISCOMMA_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(1), GlitchData => RXCHARISCOMMA1_GlitchData, OutSignalName => "RXCHARISCOMMA(1)", OutTemp => RXCHARISCOMMA_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(2), GlitchData => RXCHARISCOMMA2_GlitchData, OutSignalName => "RXCHARISCOMMA(2)", OutTemp => RXCHARISCOMMA_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(3), GlitchData => RXCHARISCOMMA3_GlitchData, OutSignalName => "RXCHARISCOMMA(3)", OutTemp => RXCHARISCOMMA_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(0), GlitchData => RXCHARISK0_GlitchData, OutSignalName => "RXCHARISK(0)", OutTemp => RXCHARISK_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(1), GlitchData => RXCHARISK1_GlitchData, OutSignalName => "RXCHARISK(1)", OutTemp => RXCHARISK_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(2), GlitchData => RXCHARISK2_GlitchData, OutSignalName => "RXCHARISK(2)", OutTemp => RXCHARISK_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(3), GlitchData => RXCHARISK3_GlitchData, OutSignalName => "RXCHARISK(3)", OutTemp => RXCHARISK_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHECKINGCRC, GlitchData => RXCHECKINGCRC_GlitchData, OutSignalName => "RXCHECKINGCRC", OutTemp => RXCHECKINGCRC_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT(0), GlitchData => RXCLKCORCNT0_GlitchData, OutSignalName => "RXCLKCORCNT(0)", OutTemp => RXCLKCORCNT_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT(1), GlitchData => RXCLKCORCNT1_GlitchData, OutSignalName => "RXCLKCORCNT(1)", OutTemp => RXCLKCORCNT_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT(2), GlitchData => RXCLKCORCNT2_GlitchData, OutSignalName => "RXCLKCORCNT(2)", OutTemp => RXCLKCORCNT_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCOMMADET, GlitchData => RXCOMMADET_GlitchData, OutSignalName => "RXCOMMADET", OutTemp => RXCOMMADET_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCERR, GlitchData => RXCRCERR_GlitchData, OutSignalName => "RXCRCERR", OutTemp => RXCRCERR_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(0), GlitchData => RXDATA0_GlitchData, OutSignalName => "RXDATA(0)", OutTemp => RXDATA_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(1), GlitchData => RXDATA1_GlitchData, OutSignalName => "RXDATA(1)", OutTemp => RXDATA_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(2), GlitchData => RXDATA2_GlitchData, OutSignalName => "RXDATA(2)", OutTemp => RXDATA_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(3), GlitchData => RXDATA3_GlitchData, OutSignalName => "RXDATA(3)", OutTemp => RXDATA_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(4), GlitchData => RXDATA4_GlitchData, OutSignalName => "RXDATA(4)", OutTemp => RXDATA_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(5), GlitchData => RXDATA5_GlitchData, OutSignalName => "RXDATA(5)", OutTemp => RXDATA_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(6), GlitchData => RXDATA6_GlitchData, OutSignalName => "RXDATA(6)", OutTemp => RXDATA_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(7), GlitchData => RXDATA7_GlitchData, OutSignalName => "RXDATA(7)", OutTemp => RXDATA_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(8), GlitchData => RXDATA8_GlitchData, OutSignalName => "RXDATA(8)", OutTemp => RXDATA_OUT(8), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(9), GlitchData => RXDATA9_GlitchData, OutSignalName => "RXDATA(9)", OutTemp => RXDATA_OUT(9), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(10), GlitchData => RXDATA10_GlitchData, OutSignalName => "RXDATA(10)", OutTemp => RXDATA_OUT(10), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(11), GlitchData => RXDATA11_GlitchData, OutSignalName => "RXDATA(11)", OutTemp => RXDATA_OUT(11), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(12), GlitchData => RXDATA12_GlitchData, OutSignalName => "RXDATA(12)", OutTemp => RXDATA_OUT(12), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(13), GlitchData => RXDATA13_GlitchData, OutSignalName => "RXDATA(13)", OutTemp => RXDATA_OUT(13), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(14), GlitchData => RXDATA14_GlitchData, OutSignalName => "RXDATA(14)", OutTemp => RXDATA_OUT(14), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(15), GlitchData => RXDATA15_GlitchData, OutSignalName => "RXDATA(15)", OutTemp => RXDATA_OUT(15), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(16), GlitchData => RXDATA16_GlitchData, OutSignalName => "RXDATA(16)", OutTemp => RXDATA_OUT(16), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(17), GlitchData => RXDATA17_GlitchData, OutSignalName => "RXDATA(17)", OutTemp => RXDATA_OUT(17), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(18), GlitchData => RXDATA18_GlitchData, OutSignalName => "RXDATA(18)", OutTemp => RXDATA_OUT(18), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(19), GlitchData => RXDATA19_GlitchData, OutSignalName => "RXDATA(19)", OutTemp => RXDATA_OUT(19), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(20), GlitchData => RXDATA20_GlitchData, OutSignalName => "RXDATA(20)", OutTemp => RXDATA_OUT(20), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(21), GlitchData => RXDATA21_GlitchData, OutSignalName => "RXDATA(21)", OutTemp => RXDATA_OUT(21), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(22), GlitchData => RXDATA22_GlitchData, OutSignalName => "RXDATA(22)", OutTemp => RXDATA_OUT(22), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(23), GlitchData => RXDATA23_GlitchData, OutSignalName => "RXDATA(23)", OutTemp => RXDATA_OUT(23), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(24), GlitchData => RXDATA24_GlitchData, OutSignalName => "RXDATA(24)", OutTemp => RXDATA_OUT(24), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(25), GlitchData => RXDATA25_GlitchData, OutSignalName => "RXDATA(25)", OutTemp => RXDATA_OUT(25), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(26), GlitchData => RXDATA26_GlitchData, OutSignalName => "RXDATA(26)", OutTemp => RXDATA_OUT(26), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(27), GlitchData => RXDATA27_GlitchData, OutSignalName => "RXDATA(27)", OutTemp => RXDATA_OUT(27), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(28), GlitchData => RXDATA28_GlitchData, OutSignalName => "RXDATA(28)", OutTemp => RXDATA_OUT(28), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(29), GlitchData => RXDATA29_GlitchData, OutSignalName => "RXDATA(29)", OutTemp => RXDATA_OUT(29), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(30), GlitchData => RXDATA30_GlitchData, OutSignalName => "RXDATA(30)", OutTemp => RXDATA_OUT(30), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(31), GlitchData => RXDATA31_GlitchData, OutSignalName => "RXDATA(31)", OutTemp => RXDATA_OUT(31), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(0), GlitchData => RXDISPERR0_GlitchData, OutSignalName => "RXDISPERR(0)", OutTemp => RXDISPERR_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(1), GlitchData => RXDISPERR1_GlitchData, OutSignalName => "RXDISPERR(1)", OutTemp => RXDISPERR_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(2), GlitchData => RXDISPERR2_GlitchData, OutSignalName => "RXDISPERR(2)", OutTemp => RXDISPERR_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(3), GlitchData => RXDISPERR3_GlitchData, OutSignalName => "RXDISPERR(3)", OutTemp => RXDISPERR_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC(0), GlitchData => RXLOSSOFSYNC0_GlitchData, OutSignalName => "RXLOSSOFSYNC(0)", OutTemp => RXLOSSOFSYNC_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC(1), GlitchData => RXLOSSOFSYNC1_GlitchData, OutSignalName => "RXLOSSOFSYNC(1)", OutTemp => RXLOSSOFSYNC_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(0), GlitchData => RXNOTINTABLE0_GlitchData, OutSignalName => "RXNOTINTABLE(0)", OutTemp => RXNOTINTABLE_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(1), GlitchData => RXNOTINTABLE1_GlitchData, OutSignalName => "RXNOTINTABLE(1)", OutTemp => RXNOTINTABLE_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(2), GlitchData => RXNOTINTABLE2_GlitchData, OutSignalName => "RXNOTINTABLE(2)", OutTemp => RXNOTINTABLE_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(3), GlitchData => RXNOTINTABLE3_GlitchData, OutSignalName => "RXNOTINTABLE(3)", OutTemp => RXNOTINTABLE_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXREALIGN, GlitchData => RXREALIGN_GlitchData, OutSignalName => "RXREALIGN", OutTemp => RXREALIGN_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(0), GlitchData => RXRUNDISP0_GlitchData, OutSignalName => "RXRUNDISP(0)", OutTemp => RXRUNDISP_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(1), GlitchData => RXRUNDISP1_GlitchData, OutSignalName => "RXRUNDISP(1)", OutTemp => RXRUNDISP_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(2), GlitchData => RXRUNDISP2_GlitchData, OutSignalName => "RXRUNDISP(2)", OutTemp => RXRUNDISP_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(3), GlitchData => RXRUNDISP3_GlitchData, OutSignalName => "RXRUNDISP(3)", OutTemp => RXRUNDISP_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXBUFERR, GlitchData => TXBUFERR_GlitchData, OutSignalName => "TXBUFERR", OutTemp => TXBUFERR_OUT, Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(0), GlitchData => TXKERR0_GlitchData, OutSignalName => "TXKERR(0)", OutTemp => TXKERR_OUT(0), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(1), GlitchData => TXKERR1_GlitchData, OutSignalName => "TXKERR(1)", OutTemp => TXKERR_OUT(1), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(2), GlitchData => TXKERR2_GlitchData, OutSignalName => "TXKERR(2)", OutTemp => TXKERR_OUT(2), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(3), GlitchData => TXKERR3_GlitchData, OutSignalName => "TXKERR(3)", OutTemp => TXKERR_OUT(3), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(0), GlitchData => TXRUNDISP0_GlitchData, OutSignalName => "TXRUNDISP(0)", OutTemp => TXRUNDISP_OUT(0), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(1), GlitchData => TXRUNDISP1_GlitchData, OutSignalName => "TXRUNDISP(1)", OutTemp => TXRUNDISP_OUT(1), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(2), GlitchData => TXRUNDISP2_GlitchData, OutSignalName => "TXRUNDISP(2)", OutTemp => TXRUNDISP_OUT(2), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(3), GlitchData => TXRUNDISP3_GlitchData, OutSignalName => "TXRUNDISP(3)", OutTemp => TXRUNDISP_OUT(3), Paths => (0 => (TXUSRCLK2_ipd'last_event, out_delay,TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING ); -- Wait signal (input/output pins) wait on CHBONDDONE_OUT, CHBONDO_OUT, CONFIGOUT_OUT, RXBUFSTATUS_OUT, RXCHARISCOMMA_OUT, RXCHARISK_OUT, RXCHECKINGCRC_OUT, RXCLKCORCNT_OUT, RXCOMMADET_OUT, RXCRCERR_OUT, RXDATA_OUT, RXDISPERR_OUT, RXLOSSOFSYNC_OUT, RXNOTINTABLE_OUT, RXREALIGN_OUT, -- RXRECCLK_OUT, RXRUNDISP_OUT, TXBUFERR_OUT, TXKERR_OUT, -- TXN_OUT, -- TXP_OUT, TXRUNDISP_OUT, BREFCLK_ipd, BREFCLK2_ipd, CHBONDI_ipd, CONFIGENABLE_ipd, CONFIGIN_ipd, ENCHANSYNC_ipd, ENMCOMMAALIGN_ipd, ENPCOMMAALIGN_ipd, LOOPBACK_ipd, POWERDOWN_ipd, REFCLK_ipd, REFCLK2_ipd, REFCLKSEL_ipd, RXN_ipd, RXP_ipd, RXPOLARITY_ipd, RXRESET_ipd, RXUSRCLK_ipd, RXUSRCLK2_ipd, TXBYPASS8B10B_ipd, TXCHARDISPMODE_ipd, TXCHARDISPVAL_ipd, TXCHARISK_ipd, TXDATA_ipd, TXFORCECRCERR_ipd, TXINHIBIT_ipd, TXPOLARITY_ipd, TXRESET_ipd, TXUSRCLK_ipd, TXUSRCLK2_ipd; end process TIMING; TXN <= TXN_OUT; TXP <= TXP_OUT; RXRECCLK <= RXRECCLK_OUT; end GT_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_xaui_1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for XAUI I/O Standard 1 Byte Data -- /___/ /\ Filename : GT_XAUI_1.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_XAUI_1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_XAUI_1 is generic ( CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; CRC_END_OF_PKT : string := "K29_7"; CRC_FORMAT : string := "USER_MODE"; CRC_START_OF_PKT : string := "K27_7"; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(3 downto 0); CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(0 downto 0); RXCHARISK : out std_logic_vector(0 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(7 downto 0); RXDISPERR : out std_logic_vector(0 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(0 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(0 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(0 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(0 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CHBONDI : in std_logic_vector(3 downto 0); CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(0 downto 0); TXCHARDISPMODE : in std_logic_vector(0 downto 0); TXCHARDISPVAL : in std_logic_vector(0 downto 0); TXCHARISK : in std_logic_vector(0 downto 0); TXDATA : in std_logic_vector(7 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_XAUI_1; -- Architecture body -- architecture GT_XAUI_1_V of GT_XAUI_1 is signal OPEN3 : std_logic_vector(2 downto 0); signal OPEN24 : std_logic_vector(23 downto 0); signal z3 : std_logic_vector(2 downto 0) := "000"; signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 16, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_OFFSET => 8, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00101111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 8, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 1, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => CRC_END_OF_PKT, CRC_FORMAT => CRC_FORMAT, CRC_START_OF_PKT => CRC_START_OF_PKT, DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 1, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 1, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(0 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(3 downto 1) => OPEN3, RXCHARISK(0 downto 0) => RXCHARISK, RXCHARISK(3 downto 1) => OPEN3, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA(7 downto 0) => RXDATA, RXDATA(31 downto 8) => OPEN24, RXDISPERR(0 downto 0) => RXDISPERR, RXDISPERR(3 downto 1) => OPEN3, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(0 downto 0) => RXNOTINTABLE, RXNOTINTABLE(3 downto 1) => OPEN3, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(0 downto 0) => RXRUNDISP, RXRUNDISP(3 downto 1) => OPEN3, TXBUFERR => TXBUFERR, TXKERR(0 downto 0) => TXKERR, TXKERR(3 downto 1) => OPEN3, TXN => TXN, TXP => TXP, TXRUNDISP(0 downto 0) => TXRUNDISP, TXRUNDISP(3 downto 1) => OPEN3, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CHBONDI => CHBONDI, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(0 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(3 downto 1) => z3, TXCHARDISPMODE(0 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(3 downto 1) => z3, TXCHARDISPVAL(0 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(3 downto 1) => z3, TXCHARISK(0 downto 0) => TXCHARISK, TXCHARISK(3 downto 1) => z3, TXDATA(7 downto 0) => TXDATA, TXDATA(31 downto 8) => z24, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_XAUI_1_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_xaui_2.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for XAUI I/O Standard 2 Byte Data -- /___/ /\ Filename : GT_XAUI_2.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_XAUI_2 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_XAUI_2 is generic ( CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; CRC_END_OF_PKT : string := "K29_7"; CRC_FORMAT : string := "USER_MODE"; CRC_START_OF_PKT : string := "K27_7"; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(3 downto 0); CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(1 downto 0); RXCHARISK : out std_logic_vector(1 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(15 downto 0); RXDISPERR : out std_logic_vector(1 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(1 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(1 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(1 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(1 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CHBONDI : in std_logic_vector(3 downto 0); CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(1 downto 0); TXCHARDISPMODE : in std_logic_vector(1 downto 0); TXCHARDISPVAL : in std_logic_vector(1 downto 0); TXCHARISK : in std_logic_vector(1 downto 0); TXDATA : in std_logic_vector(15 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_XAUI_2; -- Architecture body -- architecture GT_XAUI_2_V of GT_XAUI_2 is signal OPEN2 : std_logic_vector(1 downto 0); signal OPEN16 : std_logic_vector(15 downto 0); signal z2 : std_logic_vector(1 downto 0) := "00"; signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 16, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_OFFSET => 8, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00101111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 8, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 1, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => CRC_END_OF_PKT, CRC_FORMAT => CRC_FORMAT, CRC_START_OF_PKT => CRC_START_OF_PKT, DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 2, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 2, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA, RXCHARISCOMMA(3 downto 2) => OPEN2, RXCHARISK(1 downto 0) => RXCHARISK, RXCHARISK(3 downto 2) => OPEN2, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA(15 downto 0) => RXDATA, RXDATA(31 downto 16) => OPEN16, RXDISPERR(1 downto 0) => RXDISPERR, RXDISPERR(3 downto 2) => OPEN2, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE(1 downto 0) => RXNOTINTABLE, RXNOTINTABLE(3 downto 2) => OPEN2, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP(1 downto 0) => RXRUNDISP, RXRUNDISP(3 downto 2) => OPEN2, TXBUFERR => TXBUFERR, TXKERR(1 downto 0) => TXKERR, TXKERR(3 downto 2) => OPEN2, TXN => TXN, TXP => TXP, TXRUNDISP(1 downto 0) => TXRUNDISP, TXRUNDISP(3 downto 2) => OPEN2, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CHBONDI => CHBONDI, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B(1 downto 0) => TXBYPASS8B10B, TXBYPASS8B10B(3 downto 2) => z2, TXCHARDISPMODE(1 downto 0) => TXCHARDISPMODE, TXCHARDISPMODE(3 downto 2) => z2, TXCHARDISPVAL(1 downto 0) => TXCHARDISPVAL, TXCHARDISPVAL(3 downto 2) => z2, TXCHARISK(1 downto 0) => TXCHARISK, TXCHARISK(3 downto 2) => z2, TXDATA(15 downto 0) => TXDATA, TXDATA(31 downto 16) => z16, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_XAUI_2_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/gt_xaui_4.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Gigabit Transceiver for XAUI I/O Standard 4 Byte Data -- /___/ /\ Filename : GT_XAUI_4.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:11 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL GT_XAUI_4 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity GT_XAUI_4 is generic ( CHAN_BOND_MODE : string := "OFF"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE; CLK_COR_KEEP_IDLE : boolean := FALSE; CLK_COR_REPEAT_WAIT : integer := 1; CRC_END_OF_PKT : string := "K29_7"; CRC_FORMAT : string := "USER_MODE"; CRC_START_OF_PKT : string := "K27_7"; REF_CLK_V_SEL : integer := 0; RX_CRC_USE : boolean := FALSE; RX_LOS_INVALID_INCR : integer := 1; RX_LOS_THRESHOLD : integer := 4; RX_LOSS_OF_SYNC_FSM : boolean := TRUE; SERDES_10B : boolean := FALSE; TERMINATION_IMP : integer := 50; TX_CRC_FORCE_VALUE : bit_vector := "11010110"; TX_CRC_USE : boolean := FALSE; TX_DIFF_CTRL : integer := 500; TX_PREEMPHASIS : integer := 0 ); port ( CHBONDDONE : out std_ulogic; CHBONDO : out std_logic_vector(3 downto 0); CONFIGOUT : out std_ulogic; RXBUFSTATUS : out std_logic_vector(1 downto 0); RXCHARISCOMMA : out std_logic_vector(3 downto 0); RXCHARISK : out std_logic_vector(3 downto 0); RXCHECKINGCRC : out std_ulogic; RXCLKCORCNT : out std_logic_vector(2 downto 0); RXCOMMADET : out std_ulogic; RXCRCERR : out std_ulogic; RXDATA : out std_logic_vector(31 downto 0); RXDISPERR : out std_logic_vector(3 downto 0); RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXNOTINTABLE : out std_logic_vector(3 downto 0); RXREALIGN : out std_ulogic; RXRECCLK : out std_ulogic; RXRUNDISP : out std_logic_vector(3 downto 0); TXBUFERR : out std_ulogic; TXKERR : out std_logic_vector(3 downto 0); TXN : out std_ulogic; TXP : out std_ulogic; TXRUNDISP : out std_logic_vector(3 downto 0); BREFCLK : in std_ulogic := 'X'; BREFCLK2 : in std_ulogic := 'X'; CHBONDI : in std_logic_vector(3 downto 0); CONFIGENABLE : in std_ulogic; CONFIGIN : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK : in std_ulogic; REFCLK2 : in std_ulogic; REFCLKSEL : in std_ulogic; RXN : in std_ulogic; RXP : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(3 downto 0); TXCHARDISPMODE : in std_logic_vector(3 downto 0); TXCHARDISPVAL : in std_logic_vector(3 downto 0); TXCHARISK : in std_logic_vector(3 downto 0); TXDATA : in std_logic_vector(31 downto 0); TXFORCECRCERR : in std_ulogic; TXINHIBIT : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT_XAUI_4; -- Architecture body -- architecture GT_XAUI_4_V of GT_XAUI_4 is begin -- GT Instatiation (port map, generic map) GT_inst : GT generic map ( ALIGN_COMMA_MSB => FALSE, CHAN_BOND_LIMIT => 16, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_OFFSET => 8, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_1_1 => "00101111100", CHAN_BOND_SEQ_1_2 => "00000000000", CHAN_BOND_SEQ_1_3 => "00000000000", CHAN_BOND_SEQ_1_4 => "00000000000", CHAN_BOND_SEQ_2_1 => "00000000000", CHAN_BOND_SEQ_2_2 => "00000000000", CHAN_BOND_SEQ_2_3 => "00000000000", CHAN_BOND_SEQ_2_4 => "00000000000", CHAN_BOND_SEQ_2_USE => FALSE, CHAN_BOND_SEQ_LEN => 1, CHAN_BOND_WAIT => 8, CLK_COR_INSERT_IDLE_FLAG => CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE => CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT => CLK_COR_REPEAT_WAIT, CLK_COR_SEQ_1_1 => "00100011100", CLK_COR_SEQ_1_2 => "00000000000", CLK_COR_SEQ_1_3 => "00000000000", CLK_COR_SEQ_1_4 => "00000000000", CLK_COR_SEQ_2_1 => "00000000000", CLK_COR_SEQ_2_2 => "00000000000", CLK_COR_SEQ_2_3 => "00000000000", CLK_COR_SEQ_2_4 => "00000000000", CLK_COR_SEQ_2_USE => FALSE, CLK_COR_SEQ_LEN => 1, CLK_CORRECT_USE => TRUE, COMMA_10B_MASK => "1111111000", CRC_END_OF_PKT => CRC_END_OF_PKT, CRC_FORMAT => CRC_FORMAT, CRC_START_OF_PKT => CRC_START_OF_PKT, DEC_MCOMMA_DETECT => TRUE, DEC_PCOMMA_DETECT => TRUE, DEC_VALID_COMMA_ONLY => TRUE, MCOMMA_10B_VALUE => "1100000000", MCOMMA_DETECT => TRUE, PCOMMA_10B_VALUE => "0011111000", PCOMMA_DETECT => TRUE, REF_CLK_V_SEL => REF_CLK_V_SEL, RX_BUFFER_USE => TRUE, RX_CRC_USE => RX_CRC_USE, RX_DATA_WIDTH => 4, RX_DECODE_USE => TRUE, RX_LOS_INVALID_INCR => RX_LOS_INVALID_INCR, RX_LOS_THRESHOLD => RX_LOS_THRESHOLD, RX_LOSS_OF_SYNC_FSM => RX_LOSS_OF_SYNC_FSM, SERDES_10B => SERDES_10B, TERMINATION_IMP => TERMINATION_IMP, TX_BUFFER_USE => TRUE, TX_CRC_FORCE_VALUE => TX_CRC_FORCE_VALUE, TX_CRC_USE => TX_CRC_USE, TX_DATA_WIDTH => 4, TX_DIFF_CTRL => TX_DIFF_CTRL, TX_PREEMPHASIS => TX_PREEMPHASIS ) port map ( CHBONDDONE => CHBONDDONE, CHBONDO => CHBONDO, CONFIGOUT => CONFIGOUT, RXBUFSTATUS => RXBUFSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCHECKINGCRC => RXCHECKINGCRC, RXCLKCORCNT => RXCLKCORCNT, RXCOMMADET => RXCOMMADET, RXCRCERR => RXCRCERR, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRECCLK => RXRECCLK, RXRUNDISP => RXRUNDISP, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXN => TXN, TXP => TXP, TXRUNDISP => TXRUNDISP, BREFCLK => BREFCLK, BREFCLK2 => BREFCLK2, CHBONDI => CHBONDI, CONFIGENABLE => CONFIGENABLE, CONFIGIN => CONFIGIN, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, REFCLK => REFCLK, REFCLK2 => REFCLK2, REFCLKSEL => REFCLKSEL, RXN => RXN, RXP => RXP, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXFORCECRCERR => TXFORCECRCERR, TXINHIBIT => TXINHIBIT, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2 ); end GT_XAUI_4_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/jtagppc.vhd,v 1.5 2004/09/09 23:33:00 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / JTAG Primitive for Power PC -- /___/ /\ Filename : JTAGPPC.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:12 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ----- CELL JTAGPPC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; entity JTAGPPC is port ( TCK : out std_ulogic; TDIPPC : out std_ulogic; TMS : out std_ulogic; TDOPPC : in std_ulogic; TDOTSPPC : in std_ulogic ); end JTAGPPC; architecture JTAGPPC_v of JTAGPPC is begin TCK <= '1'; TDIPPC <= '1'; TMS <= '1'; end JTAGPPC_v; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/SMODEL/Attic/ppc405.vhd,v 1.9 2006/03/16 00:57:42 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Power PC Core -- /___/ /\ Filename : PPC405.vhd -- \ \ / \ Timestamp : Thu Apr 8 10:55:12 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. library IEEE; use IEEE.STD_LOGIC_1164.all; entity FPGA_startup is port ( bus_reset : out std_ulogic; ghigh_b : out std_ulogic; done : out std_ulogic; gsr : out std_ulogic; gwe : out std_ulogic; gts_b : out std_ulogic; shutdown : in std_ulogic; cclk : in std_ulogic; por : in std_ulogic ); end FPGA_startup; architecture FPGA_startup_v of FPGA_startup is signal count_changed : boolean := false; begin set_output:process(cclk, por) variable abus_reset : std_ulogic := '0'; variable aghigh_b : std_ulogic := '0'; variable agsr : std_ulogic := '0'; variable adone : std_ulogic := '0'; variable agwe : std_ulogic := '0'; variable agts_b : std_ulogic := '0'; variable count : integer := 0; variable count_last_value : integer := 0; begin if (((cclk'event) and (cclk = '1') and (cclk'last_value = '0')) or ((por'event) and (por = '1') and (por'last_value = '0')))then count_last_value := count; if (por = '1') then count := 0; elsif ((shutdown ='1') and (count > 0)) then count := count - 1; elsif ((shutdown ='0') and (count < 255)) then count := count + 1; end if; if(count_last_value /= count) then count_changed <= true; end if; if (por = '1') then bus_reset <= '0'; ghigh_b <= '0'; gsr <= '0'; done <= '0'; gwe <= '0'; gts_b <= '0'; else bus_reset <= abus_reset; ghigh_b <= aghigh_b; gsr <= agsr; done <= adone; gwe <= agwe; gts_b <= agts_b; end if; end if; if(count_last_value /= count) then abus_reset := '1'; aghigh_b := '0'; agsr := '0'; adone := '0'; agwe := '0'; agts_b := '0'; if (count >= 04) then abus_reset := '0'; end if; if ((count = 33) or (count = 34)) then agsr := '1'; end if; if (count > 38) then aghigh_b := '1'; end if; if (count > 49) then adone := '1'; end if; if (count > 50) then agwe := '1'; end if; if (count > 51) then agts_b := '1'; end if; end if; end process set_output; end FPGA_startup_v; ----- CELL PPC405 ----- ------------------------------------------------------------------------------- -- Model for power pc (for simulation only) ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; entity PPC405 is generic ( PPCUSER : std_logic_vector(0 to 3) := "0000" ) ; port ( C405CPMCORESLEEPREQ : out std_ulogic; C405CPMMSRCE : out std_ulogic; C405CPMMSREE : out std_ulogic; C405CPMTIMERIRQ : out std_ulogic; C405CPMTIMERRESETREQ : out std_ulogic; C405DBGMSRWE : out std_ulogic; C405DBGSTOPACK : out std_ulogic; C405DBGWBCOMPLETE : out std_ulogic; C405DBGWBFULL : out std_ulogic; C405DBGWBIAR : out std_logic_vector(0 TO 29); C405DCRABUS : out std_logic_vector(0 TO 9); C405DCRDBUSOUT : out std_logic_vector(0 TO 31); C405DCRREAD : out std_ulogic; C405DCRWRITE : out std_ulogic; C405JTGCAPTUREDR : out std_ulogic; C405JTGEXTEST : out std_ulogic; C405JTGPGMOUT : out std_ulogic; C405JTGSHIFTDR : out std_ulogic; C405JTGTDO : out std_ulogic; C405JTGTDOEN : out std_ulogic; C405JTGUPDATEDR : out std_ulogic; C405PLBDCUABORT : out std_ulogic; C405PLBDCUABUS : out std_logic_vector(0 TO 31); C405PLBDCUBE : out std_logic_vector(0 TO 7); C405PLBDCUCACHEABLE : out std_ulogic; C405PLBDCUGUARDED : out std_ulogic; C405PLBDCUPRIORITY : out std_logic_vector(0 TO 1); C405PLBDCUREQUEST : out std_ulogic; C405PLBDCURNW : out std_ulogic; C405PLBDCUSIZE2 : out std_ulogic; C405PLBDCUU0ATTR : out std_ulogic; C405PLBDCUWRDBUS : out std_logic_vector(0 TO 63); C405PLBDCUWRITETHRU : out std_ulogic; C405PLBICUABORT : out std_ulogic; C405PLBICUABUS : out std_logic_vector(0 TO 29); C405PLBICUCACHEABLE : out std_ulogic; C405PLBICUPRIORITY : out std_logic_vector(0 TO 1); C405PLBICUREQUEST : out std_ulogic; C405PLBICUSIZE : out std_logic_vector(2 TO 3); C405PLBICUU0ATTR : out std_ulogic; C405RSTCHIPRESETREQ : out std_ulogic; C405RSTCORERESETREQ : out std_ulogic; C405RSTSYSRESETREQ : out std_ulogic; C405TRCCYCLE : out std_ulogic; C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 TO 1); C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 TO 1); C405TRCTRACESTATUS : out std_logic_vector(0 TO 3); C405TRCTRIGGEREVENTOUT : out std_ulogic; C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 TO 10); C405XXXMACHINECHECK : out std_ulogic; DSOCMBRAMABUS : out std_logic_vector(8 TO 29); DSOCMBRAMBYTEWRITE : out std_logic_vector(0 TO 3); DSOCMBRAMEN : out std_ulogic; DSOCMBRAMWRDBUS : out std_logic_vector(0 TO 31); DSOCMBUSY : out std_ulogic; ISOCMBRAMEN : out std_ulogic; ISOCMBRAMEVENWRITEEN : out std_ulogic; ISOCMBRAMODDWRITEEN : out std_ulogic; ISOCMBRAMRDABUS : out std_logic_vector(8 TO 28); ISOCMBRAMWRABUS : out std_logic_vector(8 TO 28); ISOCMBRAMWRDBUS : out std_logic_vector(0 TO 31); BRAMDSOCMCLK : in std_ulogic; BRAMDSOCMRDDBUS : in std_logic_vector(0 TO 31); BRAMISOCMCLK : in std_ulogic; BRAMISOCMRDDBUS : in std_logic_vector(0 TO 63); CPMC405CLOCK : in std_ulogic; CPMC405CORECLKINACTIVE : in std_ulogic; CPMC405CPUCLKEN : in std_ulogic; CPMC405JTAGCLKEN : in std_ulogic; CPMC405TIMERCLKEN : in std_ulogic; CPMC405TIMERTICK : in std_ulogic; DBGC405DEBUGHALT : in std_ulogic; DBGC405EXTBUSHOLDACK : in std_ulogic; DBGC405UNCONDDEBUGEVENT : in std_ulogic; DCRC405ACK : in std_ulogic; DCRC405DBUSIN : in std_logic_vector(0 TO 31); DSARCVALUE : in std_logic_vector(0 TO 7); DSCNTLVALUE : in std_logic_vector(0 TO 7); EICC405CRITINPUTIRQ : in std_ulogic; EICC405EXTINPUTIRQ : in std_ulogic; ISARCVALUE : in std_logic_vector(0 TO 7); ISCNTLVALUE : in std_logic_vector(0 TO 7); JTGC405BNDSCANTDO : in std_ulogic; JTGC405TCK : in std_ulogic; JTGC405TDI : in std_ulogic; JTGC405TMS : in std_ulogic; JTGC405TRSTNEG : in std_ulogic; MCBCPUCLKEN : in std_ulogic; MCBJTAGEN : in std_ulogic; MCBTIMEREN : in std_ulogic; MCPPCRST : in std_ulogic; PLBC405DCUADDRACK : in std_ulogic; PLBC405DCUBUSY : in std_ulogic; PLBC405DCUERR : in std_ulogic; PLBC405DCURDDACK : in std_ulogic; PLBC405DCURDDBUS : in std_logic_vector(0 TO 63); PLBC405DCURDWDADDR : in std_logic_vector(1 TO 3); PLBC405DCUSSIZE1 : in std_ulogic; PLBC405DCUWRDACK : in std_ulogic; PLBC405ICUADDRACK : in std_ulogic; PLBC405ICUBUSY : in std_ulogic; PLBC405ICUERR : in std_ulogic; PLBC405ICURDDACK : in std_ulogic; PLBC405ICURDDBUS : in std_logic_vector(0 TO 63); PLBC405ICURDWDADDR : in std_logic_vector(1 TO 3); PLBC405ICUSSIZE1 : in std_ulogic; PLBCLK : in std_ulogic; RSTC405RESETCHIP : in std_ulogic; RSTC405RESETCORE : in std_ulogic; RSTC405RESETSYS : in std_ulogic; TIEC405DETERMINISTICMULT : in std_ulogic; TIEC405DISOPERANDFWD : in std_ulogic; TIEC405MMUEN : in std_ulogic; TIEDSOCMDCRADDR : in std_logic_vector(0 TO 7); TIEISOCMDCRADDR : in std_logic_vector(0 TO 7); TRCC405TRACEDISABLE : in std_ulogic; TRCC405TRIGGEREVENTIN : in std_ulogic ); end PPC405; -- architecture body -- architecture PPC405_v of PPC405 is component PPC405_SWIFT_BUS port ( BUS_CLK : in std_ulogic; BUS_RESET : in std_ulogic; GWE : in std_ulogic; GHIGHB : in std_ulogic; GSR : in std_ulogic; CPMC405CPUCLKEN : in std_ulogic; CPMC405JTAGCLKEN : in std_ulogic; CPMC405TIMERCLKEN : in std_ulogic; C405JTGPGMOUT : out std_ulogic; MCBCPUCLKEN : in std_ulogic; MCBJTAGEN : in std_ulogic; MCBTIMEREN : in std_ulogic; MCPPCRST : in std_ulogic; C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 TO 1); C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 TO 1); CPMC405CLOCK : in std_ulogic; CPMC405CORECLKINACTIVE : in std_ulogic; PLBCLK : in std_ulogic; CPMC405TIMERTICK : in std_ulogic; C405CPMMSREE : out std_ulogic; C405CPMMSRCE : out std_ulogic; C405CPMTIMERIRQ : out std_ulogic; C405CPMTIMERRESETREQ : out std_ulogic; C405CPMCORESLEEPREQ : out std_ulogic; TIEC405DISOPERANDFWD : in std_ulogic; TIEC405DETERMINISTICMULT : in std_ulogic; TIEC405MMUEN : in std_ulogic; TIEC405PVR : in std_logic_vector(28 TO 31); C405XXXMACHINECHECK : out std_ulogic; C405RSTCHIPRESETREQ : out std_ulogic; C405RSTCORERESETREQ : out std_ulogic; C405RSTSYSRESETREQ : out std_ulogic; RSTC405RESETCHIP : in std_ulogic; RSTC405RESETCORE : in std_ulogic; RSTC405RESETSYS : in std_ulogic; C405PLBICUREQUEST : out std_ulogic; C405PLBICUPRIORITY : out std_logic_vector(0 TO 1); C405PLBICUCACHEABLE : out std_ulogic; C405PLBICUABUS : out std_logic_vector(0 TO 29); C405PLBICUSIZE : out std_logic_vector(2 TO 3); C405PLBICUABORT : out std_ulogic; C405PLBICUU0ATTR : out std_ulogic; PLBC405ICUADDRACK : in std_ulogic; PLBC405ICUBUSY : in std_ulogic; PLBC405ICUERR : in std_ulogic; PLBC405ICURDDACK : in std_ulogic; PLBC405ICURDDBUS : in std_logic_vector(0 TO 63); PLBC405ICUSSIZE1 : in std_ulogic; PLBC405ICURDWDADDR : in std_logic_vector(1 TO 3); C405PLBDCUREQUEST : out std_ulogic; C405PLBDCURNW : out std_ulogic; C405PLBDCUABUS : out std_logic_vector(0 TO 31); C405PLBDCUBE : out std_logic_vector(0 TO 7); C405PLBDCUCACHEABLE : out std_ulogic; C405PLBDCUGUARDED : out std_ulogic; C405PLBDCUPRIORITY : out std_logic_vector(0 TO 1); C405PLBDCUSIZE2 : out std_ulogic; C405PLBDCUABORT : out std_ulogic; C405PLBDCUWRDBUS : out std_logic_vector(0 TO 63); C405PLBDCUU0ATTR : out std_ulogic; C405PLBDCUWRITETHRU : out std_ulogic; PLBC405DCUADDRACK : in std_ulogic; PLBC405DCUBUSY : in std_ulogic; PLBC405DCUERR : in std_ulogic; PLBC405DCURDDACK : in std_ulogic; PLBC405DCURDDBUS : in std_logic_vector(0 TO 63); PLBC405DCURDWDADDR : in std_logic_vector(1 TO 3); PLBC405DCUSSIZE1 : in std_ulogic; PLBC405DCUWRDACK : in std_ulogic; ISOCMBRAMRDABUS : out std_logic_vector(8 TO 28); ISOCMBRAMWRABUS : out std_logic_vector(8 TO 28); ISOCMBRAMEN : out std_ulogic; ISOCMBRAMODDWRITEEN : out std_ulogic; ISOCMBRAMEVENWRITEEN : out std_ulogic; ISOCMBRAMWRDBUS : out std_logic_vector(0 TO 31); BRAMISOCMRDDBUS : in std_logic_vector(0 TO 63); TIEISOCMDCRADDR : in std_logic_vector(0 TO 7); ISARCVALUE : in std_logic_vector(0 TO 7); ISCNTLVALUE : in std_logic_vector(0 TO 7); BRAMISOCMCLK : in std_ulogic; DSOCMBRAMABUS : out std_logic_vector(8 TO 29); DSOCMBRAMBYTEWRITE : out std_logic_vector(0 TO 3); DSOCMBRAMEN : out std_ulogic; DSOCMBRAMWRDBUS : out std_logic_vector(0 TO 31); BRAMDSOCMRDDBUS : in std_logic_vector(0 TO 31); DSOCMBUSY : out std_ulogic; TIEDSOCMDCRADDR : in std_logic_vector(0 TO 7); DSARCVALUE : in std_logic_vector(0 TO 7); DSCNTLVALUE : in std_logic_vector(0 TO 7); BRAMDSOCMCLK : in std_ulogic; C405DCRREAD : out std_ulogic; C405DCRWRITE : out std_ulogic; C405DCRABUS : out std_logic_vector(0 TO 9); C405DCRDBUSOUT : out std_logic_vector(0 TO 31); DCRC405ACK : in std_ulogic; DCRC405DBUSIN : in std_logic_vector(0 TO 31); EICC405EXTINPUTIRQ : in std_ulogic; EICC405CRITINPUTIRQ : in std_ulogic; JTGC405BNDSCANTDO : in std_ulogic; JTGC405TCK : in std_ulogic; JTGC405TDI : in std_ulogic; JTGC405TMS : in std_ulogic; JTGC405TRSTNEG : in std_ulogic; C405JTGTDO : out std_ulogic; C405JTGTDOEN : out std_ulogic; C405JTGEXTEST : out std_ulogic; C405JTGCAPTUREDR : out std_ulogic; C405JTGSHIFTDR : out std_ulogic; C405JTGUPDATEDR : out std_ulogic; DBGC405DEBUGHALT : in std_ulogic; DBGC405UNCONDDEBUGEVENT : in std_ulogic; DBGC405EXTBUSHOLDACK : in std_ulogic; C405DBGMSRWE : out std_ulogic; C405DBGSTOPACK : out std_ulogic; C405DBGWBCOMPLETE : out std_ulogic; C405DBGWBFULL : out std_ulogic; C405DBGWBIAR : out std_logic_vector(0 TO 29); C405TRCTRIGGEREVENTOUT : out std_ulogic; C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 TO 10); C405TRCCYCLE : out std_ulogic; C405TRCTRACESTATUS : out std_logic_vector(0 TO 3); TRCC405TRACEDISABLE : in std_ulogic; TRCC405TRIGGEREVENTIN : in std_ulogic ); end component; component FPGA_STARTUP port ( bus_reset : out std_ulogic; ghigh_b : out std_ulogic; done : out std_ulogic; gsr : out std_ulogic; gwe : out std_ulogic; gts_b : out std_ulogic; shutdown : in std_ulogic; cclk : in std_ulogic; por : in std_ulogic ); end component; constant in_delay : time := 1 ps; constant out_delay : VitalDelayType01 := (100 ps, 100 ps); signal TIEC405PVR_ipd : std_logic_vector(31 downto 28); signal BRAMDSOCMCLK_ipd : std_ulogic; signal BRAMDSOCMRDDBUS_ipd : std_logic_vector(0 TO 31); signal BRAMISOCMCLK_ipd : std_ulogic; signal BRAMISOCMRDDBUS_ipd : std_logic_vector(0 TO 63); signal CPMC405CLOCK_ipd : std_ulogic; signal CPMC405CORECLKINACTIVE_ipd : std_ulogic; signal CPMC405CPUCLKEN_ipd : std_ulogic; signal CPMC405JTAGCLKEN_ipd : std_ulogic; signal CPMC405TIMERCLKEN_ipd : std_ulogic; signal CPMC405TIMERTICK_ipd : std_ulogic; signal DBGC405DEBUGHALT_ipd : std_ulogic; signal DBGC405EXTBUSHOLDACK_ipd : std_ulogic; signal DBGC405UNCONDDEBUGEVENT_ipd : std_ulogic; signal DCRC405ACK_ipd : std_ulogic; signal DCRC405DBUSIN_ipd : std_logic_vector(0 TO 31); signal DSARCVALUE_ipd : std_logic_vector(0 TO 7); signal DSCNTLVALUE_ipd : std_logic_vector(0 TO 7); signal EICC405CRITINPUTIRQ_ipd : std_ulogic; signal EICC405EXTINPUTIRQ_ipd : std_ulogic; signal ISARCVALUE_ipd : std_logic_vector(0 TO 7); signal ISCNTLVALUE_ipd : std_logic_vector(0 TO 7); signal JTGC405BNDSCANTDO_ipd : std_ulogic; signal JTGC405TCK_ipd : std_ulogic; signal JTGC405TDI_ipd : std_ulogic; signal JTGC405TMS_ipd : std_ulogic; signal JTGC405TRSTNEG_ipd : std_ulogic; signal MCBCPUCLKEN_ipd : std_ulogic; signal MCBJTAGEN_ipd : std_ulogic; signal MCBTIMEREN_ipd : std_ulogic; signal MCPPCRST_ipd : std_ulogic; signal PLBC405DCUADDRACK_ipd : std_ulogic; signal PLBC405DCUBUSY_ipd : std_ulogic; signal PLBC405DCUERR_ipd : std_ulogic; signal PLBC405DCURDDACK_ipd : std_ulogic; signal PLBC405DCURDDBUS_ipd : std_logic_vector(0 TO 63); signal PLBC405DCURDWDADDR_ipd : std_logic_vector(1 TO 3); signal PLBC405DCUSSIZE1_ipd : std_ulogic; signal PLBC405DCUWRDACK_ipd : std_ulogic; signal PLBC405ICUADDRACK_ipd : std_ulogic; signal PLBC405ICUBUSY_ipd : std_ulogic; signal PLBC405ICUERR_ipd : std_ulogic; signal PLBC405ICURDDACK_ipd : std_ulogic; signal PLBC405ICURDDBUS_ipd : std_logic_vector(0 TO 63); signal PLBC405ICURDWDADDR_ipd : std_logic_vector(1 TO 3); signal PLBC405ICUSSIZE1_ipd : std_ulogic; signal PLBCLK_ipd : std_ulogic; signal RSTC405RESETCHIP_ipd : std_ulogic; signal RSTC405RESETCORE_ipd : std_ulogic; signal RSTC405RESETSYS_ipd : std_ulogic; signal TIEC405DETERMINISTICMULT_ipd : std_ulogic; signal TIEC405DISOPERANDFWD_ipd : std_ulogic; signal TIEC405MMUEN_ipd : std_ulogic; signal TIEDSOCMDCRADDR_ipd : std_logic_vector(0 TO 7); signal TIEISOCMDCRADDR_ipd : std_logic_vector(0 TO 7); signal TRCC405TRACEDISABLE_ipd : std_ulogic; signal TRCC405TRIGGEREVENTIN_ipd : std_ulogic; signal TIEC405PVR_ipd_1 : std_logic_vector(31 downto 28); signal BRAMDSOCMCLK_ipd_1 : std_ulogic; signal BRAMDSOCMRDDBUS_ipd_1 : std_logic_vector(0 TO 31); signal BRAMISOCMCLK_ipd_1 : std_ulogic; signal BRAMISOCMRDDBUS_ipd_1 : std_logic_vector(0 TO 63); signal CPMC405CLOCK_ipd_1 : std_ulogic; signal CPMC405CORECLKINACTIVE_ipd_1 : std_ulogic; signal CPMC405CPUCLKEN_ipd_1 : std_ulogic; signal CPMC405JTAGCLKEN_ipd_1 : std_ulogic; signal CPMC405TIMERCLKEN_ipd_1 : std_ulogic; signal CPMC405TIMERTICK_ipd_1 : std_ulogic; signal DBGC405DEBUGHALT_ipd_1 : std_ulogic; signal DBGC405EXTBUSHOLDACK_ipd_1 : std_ulogic; signal DBGC405UNCONDDEBUGEVENT_ipd_1 : std_ulogic; signal DCRC405ACK_ipd_1 : std_ulogic; signal DCRC405DBUSIN_ipd_1 : std_logic_vector(0 TO 31); signal DSARCVALUE_ipd_1 : std_logic_vector(0 TO 7); signal DSCNTLVALUE_ipd_1 : std_logic_vector(0 TO 7); signal EICC405CRITINPUTIRQ_ipd_1 : std_ulogic; signal EICC405EXTINPUTIRQ_ipd_1 : std_ulogic; signal ISARCVALUE_ipd_1 : std_logic_vector(0 TO 7); signal ISCNTLVALUE_ipd_1 : std_logic_vector(0 TO 7); signal JTGC405BNDSCANTDO_ipd_1 : std_ulogic; signal JTGC405TCK_ipd_1 : std_ulogic; signal JTGC405TDI_ipd_1 : std_ulogic; signal JTGC405TMS_ipd_1 : std_ulogic; signal JTGC405TRSTNEG_ipd_1 : std_ulogic; signal MCBCPUCLKEN_ipd_1 : std_ulogic; signal MCBJTAGEN_ipd_1 : std_ulogic; signal MCBTIMEREN_ipd_1 : std_ulogic; signal MCPPCRST_ipd_1 : std_ulogic; signal PLBC405DCUADDRACK_ipd_1 : std_ulogic; signal PLBC405DCUBUSY_ipd_1 : std_ulogic; signal PLBC405DCUERR_ipd_1 : std_ulogic; signal PLBC405DCURDDACK_ipd_1 : std_ulogic; signal PLBC405DCURDDBUS_ipd_1 : std_logic_vector(0 TO 63); signal PLBC405DCURDWDADDR_ipd_1 : std_logic_vector(1 TO 3); signal PLBC405DCUSSIZE1_ipd_1 : std_ulogic; signal PLBC405DCUWRDACK_ipd_1 : std_ulogic; signal PLBC405ICUADDRACK_ipd_1 : std_ulogic; signal PLBC405ICUBUSY_ipd_1 : std_ulogic; signal PLBC405ICUERR_ipd_1 : std_ulogic; signal PLBC405ICURDDACK_ipd_1 : std_ulogic; signal PLBC405ICURDDBUS_ipd_1 : std_logic_vector(0 TO 63); signal PLBC405ICURDWDADDR_ipd_1 : std_logic_vector(1 TO 3); signal PLBC405ICUSSIZE1_ipd_1 : std_ulogic; signal PLBCLK_ipd_1 : std_ulogic; signal RSTC405RESETCHIP_ipd_1 : std_ulogic; signal RSTC405RESETCORE_ipd_1 : std_ulogic; signal RSTC405RESETSYS_ipd_1 : std_ulogic; signal TIEC405DETERMINISTICMULT_ipd_1 : std_ulogic; signal TIEC405DISOPERANDFWD_ipd_1 : std_ulogic; signal TIEC405MMUEN_ipd_1 : std_ulogic; signal TIEDSOCMDCRADDR_ipd_1 : std_logic_vector(0 TO 7); signal TIEISOCMDCRADDR_ipd_1 : std_logic_vector(0 TO 7); signal TRCC405TRACEDISABLE_ipd_1 : std_ulogic; signal TRCC405TRIGGEREVENTIN_ipd_1 : std_ulogic; signal C405CPMCORESLEEPREQ_OUT : std_ulogic; signal C405CPMMSRCE_OUT : std_ulogic; signal C405CPMMSREE_OUT : std_ulogic; signal C405CPMTIMERIRQ_OUT : std_ulogic; signal C405CPMTIMERRESETREQ_OUT : std_ulogic; signal C405DBGMSRWE_OUT : std_ulogic; signal C405DBGSTOPACK_OUT : std_ulogic; signal C405DBGWBCOMPLETE_OUT : std_ulogic; signal C405DBGWBFULL_OUT : std_ulogic; signal C405DBGWBIAR_OUT : std_logic_vector(0 TO 29); signal C405DCRABUS_OUT : std_logic_vector(0 TO 9); signal C405DCRDBUSOUT_OUT : std_logic_vector(0 TO 31); signal C405DCRREAD_OUT : std_ulogic; signal C405DCRWRITE_OUT : std_ulogic; signal C405JTGCAPTUREDR_OUT : std_ulogic; signal C405JTGEXTEST_OUT : std_ulogic; signal C405JTGPGMOUT_OUT : std_ulogic; signal C405JTGSHIFTDR_OUT : std_ulogic; signal C405JTGTDO_OUT : std_ulogic; signal C405JTGTDOEN_OUT : std_ulogic; signal C405JTGUPDATEDR_OUT : std_ulogic; signal C405PLBDCUABORT_OUT : std_ulogic; signal C405PLBDCUABUS_OUT : std_logic_vector(0 TO 31); signal C405PLBDCUBE_OUT : std_logic_vector(0 TO 7); signal C405PLBDCUCACHEABLE_OUT : std_ulogic; signal C405PLBDCUGUARDED_OUT : std_ulogic; signal C405PLBDCUPRIORITY_OUT : std_logic_vector(0 TO 1); signal C405PLBDCUREQUEST_OUT : std_ulogic; signal C405PLBDCURNW_OUT : std_ulogic; signal C405PLBDCUSIZE2_OUT : std_ulogic; signal C405PLBDCUU0ATTR_OUT : std_ulogic; signal C405PLBDCUWRDBUS_OUT : std_logic_vector(0 TO 63); signal C405PLBDCUWRITETHRU_OUT : std_ulogic; signal C405PLBICUABORT_OUT : std_ulogic; signal C405PLBICUABUS_OUT : std_logic_vector(0 TO 29); signal C405PLBICUCACHEABLE_OUT : std_ulogic; signal C405PLBICUPRIORITY_OUT : std_logic_vector(0 TO 1); signal C405PLBICUREQUEST_OUT : std_ulogic; signal C405PLBICUSIZE_OUT : std_logic_vector(2 TO 3); signal C405PLBICUU0ATTR_OUT : std_ulogic; signal C405RSTCHIPRESETREQ_OUT : std_ulogic; signal C405RSTCORERESETREQ_OUT : std_ulogic; signal C405RSTSYSRESETREQ_OUT : std_ulogic; signal C405TRCCYCLE_OUT : std_ulogic; signal C405TRCEVENEXECUTIONSTATUS_OUT : std_logic_vector(0 TO 1); signal C405TRCODDEXECUTIONSTATUS_OUT : std_logic_vector(0 TO 1); signal C405TRCTRACESTATUS_OUT : std_logic_vector(0 TO 3); signal C405TRCTRIGGEREVENTOUT_OUT : std_ulogic; signal C405TRCTRIGGEREVENTTYPE_OUT : std_logic_vector(0 TO 10); signal C405XXXMACHINECHECK_OUT : std_ulogic; signal DSOCMBRAMABUS_OUT : std_logic_vector(8 TO 29); signal DSOCMBRAMBYTEWRITE_OUT : std_logic_vector(0 TO 3); signal DSOCMBRAMEN_OUT : std_ulogic; signal DSOCMBRAMWRDBUS_OUT : std_logic_vector(0 TO 31); signal DSOCMBUSY_OUT : std_ulogic; signal ISOCMBRAMEN_OUT : std_ulogic; signal ISOCMBRAMEVENWRITEEN_OUT : std_ulogic; signal ISOCMBRAMODDWRITEEN_OUT : std_ulogic; signal ISOCMBRAMRDABUS_OUT : std_logic_vector(8 TO 28); signal ISOCMBRAMWRABUS_OUT : std_logic_vector(8 TO 28); signal ISOCMBRAMWRDBUS_OUT : std_logic_vector(0 TO 31); signal FPGA_CCLK : std_ulogic := '0'; signal FPGA_POR : std_ulogic := '1'; signal FPGA_BUS_RESET : std_ulogic := '0'; signal FPGA_GWE : std_ulogic := '0'; signal FPGA_GHIGHB : std_ulogic := '0'; signal FPGA_GSR : std_ulogic := '0'; signal GSR_OR : std_ulogic := '0'; signal GSR : std_ulogic := '0'; signal FPGA_SHUTDOWN : std_ulogic := '0'; signal FPGA_CCLK_delay : std_ulogic := '0'; signal FPGA_BUS_RESET_delay : std_ulogic := '0'; signal GSR_delay : std_ulogic := '0'; signal FPGA_GWE_delay : std_ulogic := '0'; signal FPGA_GHIGHB_delay : std_ulogic := '0'; signal ppcuser_binary : std_logic_vector(0 to 3) := PPCUSER; begin BRAMDSOCMCLK_ipd <= BRAMDSOCMCLK after 0 ps; BRAMDSOCMRDDBUS_ipd <= BRAMDSOCMRDDBUS after 0 ps; BRAMISOCMCLK_ipd <= BRAMISOCMCLK after 0 ps; BRAMISOCMRDDBUS_ipd <= BRAMISOCMRDDBUS after 0 ps; CPMC405CLOCK_ipd <= CPMC405CLOCK after 0 ps; CPMC405CORECLKINACTIVE_ipd <= CPMC405CORECLKINACTIVE after 0 ps; CPMC405CPUCLKEN_ipd <= CPMC405CPUCLKEN after 0 ps; CPMC405JTAGCLKEN_ipd <= CPMC405JTAGCLKEN after 0 ps; CPMC405TIMERCLKEN_ipd <= CPMC405TIMERCLKEN after 0 ps; CPMC405TIMERTICK_ipd <= CPMC405TIMERTICK after 0 ps; DBGC405DEBUGHALT_ipd <= DBGC405DEBUGHALT after 0 ps; DBGC405EXTBUSHOLDACK_ipd <= DBGC405EXTBUSHOLDACK after 0 ps; DBGC405UNCONDDEBUGEVENT_ipd <= DBGC405UNCONDDEBUGEVENT after 0 ps; DCRC405ACK_ipd <= DCRC405ACK after 0 ps; DCRC405DBUSIN_ipd <= DCRC405DBUSIN after 0 ps; DSARCVALUE_ipd <= DSARCVALUE after 0 ps; DSCNTLVALUE_ipd <= DSCNTLVALUE after 0 ps; EICC405CRITINPUTIRQ_ipd <= EICC405CRITINPUTIRQ after 0 ps; EICC405EXTINPUTIRQ_ipd <= EICC405EXTINPUTIRQ after 0 ps; ISARCVALUE_ipd <= ISARCVALUE after 0 ps; ISCNTLVALUE_ipd <= ISCNTLVALUE after 0 ps; JTGC405BNDSCANTDO_ipd <= JTGC405BNDSCANTDO after 0 ps; JTGC405TCK_ipd <= JTGC405TCK after 0 ps; JTGC405TDI_ipd <= JTGC405TDI after 0 ps; JTGC405TMS_ipd <= JTGC405TMS after 0 ps; JTGC405TRSTNEG_ipd <= JTGC405TRSTNEG after 0 ps; MCBCPUCLKEN_ipd <= MCBCPUCLKEN after 0 ps; MCBJTAGEN_ipd <= MCBJTAGEN after 0 ps; MCBTIMEREN_ipd <= MCBTIMEREN after 0 ps; MCPPCRST_ipd <= MCPPCRST after 0 ps; PLBC405DCUADDRACK_ipd <= PLBC405DCUADDRACK after 0 ps; PLBC405DCUBUSY_ipd <= PLBC405DCUBUSY after 0 ps; PLBC405DCUERR_ipd <= PLBC405DCUERR after 0 ps; PLBC405DCURDDACK_ipd <= PLBC405DCURDDACK after 0 ps; PLBC405DCURDDBUS_ipd <= PLBC405DCURDDBUS after 0 ps; PLBC405DCURDWDADDR_ipd <= PLBC405DCURDWDADDR after 0 ps; PLBC405DCUSSIZE1_ipd <= PLBC405DCUSSIZE1 after 0 ps; PLBC405DCUWRDACK_ipd <= PLBC405DCUWRDACK after 0 ps; PLBC405ICUADDRACK_ipd <= PLBC405ICUADDRACK after 0 ps; PLBC405ICUBUSY_ipd <= PLBC405ICUBUSY after 0 ps; PLBC405ICUERR_ipd <= PLBC405ICUERR after 0 ps; PLBC405ICURDDACK_ipd <= PLBC405ICURDDACK after 0 ps; PLBC405ICURDDBUS_ipd <= PLBC405ICURDDBUS after 0 ps; PLBC405ICURDWDADDR_ipd <= PLBC405ICURDWDADDR after 0 ps; PLBC405ICUSSIZE1_ipd <= PLBC405ICUSSIZE1 after 0 ps; PLBCLK_ipd <= PLBCLK after 0 ps; RSTC405RESETCHIP_ipd <= RSTC405RESETCHIP after 0 ps; RSTC405RESETCORE_ipd <= RSTC405RESETCORE after 0 ps; RSTC405RESETSYS_ipd <= RSTC405RESETSYS after 0 ps; TIEC405DETERMINISTICMULT_ipd <= TIEC405DETERMINISTICMULT after 0 ps; TIEC405DISOPERANDFWD_ipd <= TIEC405DISOPERANDFWD after 0 ps; TIEC405MMUEN_ipd <= TIEC405MMUEN after 0 ps; TIEDSOCMDCRADDR_ipd <= TIEDSOCMDCRADDR after 0 ps; TIEISOCMDCRADDR_ipd <= TIEISOCMDCRADDR after 0 ps; TRCC405TRACEDISABLE_ipd <= TRCC405TRACEDISABLE after 0 ps; TRCC405TRIGGEREVENTIN_ipd <= TRCC405TRIGGEREVENTIN after 0 ps; BRAMDSOCMCLK_ipd_1 <= BRAMDSOCMCLK_ipd after in_delay; BRAMDSOCMRDDBUS_ipd_1 <= BRAMDSOCMRDDBUS_ipd after in_delay; BRAMISOCMCLK_ipd_1 <= BRAMISOCMCLK_ipd after in_delay; BRAMISOCMRDDBUS_ipd_1 <= BRAMISOCMRDDBUS_ipd after in_delay; CPMC405CLOCK_ipd_1 <= CPMC405CLOCK_ipd after in_delay; CPMC405CORECLKINACTIVE_ipd_1 <= CPMC405CORECLKINACTIVE_ipd after in_delay; CPMC405CPUCLKEN_ipd_1 <= CPMC405CPUCLKEN_ipd after in_delay; CPMC405JTAGCLKEN_ipd_1 <= CPMC405JTAGCLKEN_ipd after in_delay; CPMC405TIMERCLKEN_ipd_1 <= CPMC405TIMERCLKEN_ipd after in_delay; CPMC405TIMERTICK_ipd_1 <= CPMC405TIMERTICK_ipd after in_delay; DBGC405DEBUGHALT_ipd_1 <= DBGC405DEBUGHALT_ipd after in_delay; DBGC405EXTBUSHOLDACK_ipd_1 <= DBGC405EXTBUSHOLDACK_ipd after in_delay; DBGC405UNCONDDEBUGEVENT_ipd_1 <= DBGC405UNCONDDEBUGEVENT_ipd after in_delay; DCRC405ACK_ipd_1 <= DCRC405ACK_ipd after in_delay; DCRC405DBUSIN_ipd_1 <= DCRC405DBUSIN_ipd after in_delay; DSARCVALUE_ipd_1 <= DSARCVALUE_ipd after in_delay; DSCNTLVALUE_ipd_1 <= DSCNTLVALUE_ipd after in_delay; EICC405CRITINPUTIRQ_ipd_1 <= EICC405CRITINPUTIRQ_ipd after in_delay; EICC405EXTINPUTIRQ_ipd_1 <= EICC405EXTINPUTIRQ_ipd after in_delay; ISARCVALUE_ipd_1 <= ISARCVALUE_ipd after in_delay; ISCNTLVALUE_ipd_1 <= ISCNTLVALUE_ipd after in_delay; JTGC405BNDSCANTDO_ipd_1 <= JTGC405BNDSCANTDO_ipd after in_delay; JTGC405TCK_ipd_1 <= JTGC405TCK_ipd after in_delay; JTGC405TDI_ipd_1 <= JTGC405TDI_ipd after in_delay; JTGC405TMS_ipd_1 <= JTGC405TMS_ipd after in_delay; JTGC405TRSTNEG_ipd_1 <= JTGC405TRSTNEG_ipd after in_delay; MCBCPUCLKEN_ipd_1 <= MCBCPUCLKEN_ipd after in_delay; MCBJTAGEN_ipd_1 <= MCBJTAGEN_ipd after in_delay; MCBTIMEREN_ipd_1 <= MCBTIMEREN_ipd after in_delay; MCPPCRST_ipd_1 <= MCPPCRST_ipd after in_delay; PLBC405DCUADDRACK_ipd_1 <= PLBC405DCUADDRACK_ipd after in_delay; PLBC405DCUBUSY_ipd_1 <= PLBC405DCUBUSY_ipd after in_delay; PLBC405DCUERR_ipd_1 <= PLBC405DCUERR_ipd after in_delay; PLBC405DCURDDACK_ipd_1 <= PLBC405DCURDDACK_ipd after in_delay; PLBC405DCURDDBUS_ipd_1 <= PLBC405DCURDDBUS_ipd after in_delay; PLBC405DCURDWDADDR_ipd_1 <= PLBC405DCURDWDADDR_ipd after in_delay; PLBC405DCUSSIZE1_ipd_1 <= PLBC405DCUSSIZE1_ipd after in_delay; PLBC405DCUWRDACK_ipd_1 <= PLBC405DCUWRDACK_ipd after in_delay; PLBC405ICUADDRACK_ipd_1 <= PLBC405ICUADDRACK_ipd after in_delay; PLBC405ICUBUSY_ipd_1 <= PLBC405ICUBUSY_ipd after in_delay; PLBC405ICUERR_ipd_1 <= PLBC405ICUERR_ipd after in_delay; PLBC405ICURDDACK_ipd_1 <= PLBC405ICURDDACK_ipd after in_delay; PLBC405ICURDDBUS_ipd_1 <= PLBC405ICURDDBUS_ipd after in_delay; PLBC405ICURDWDADDR_ipd_1 <= PLBC405ICURDWDADDR_ipd after in_delay; PLBC405ICUSSIZE1_ipd_1 <= PLBC405ICUSSIZE1_ipd after in_delay; PLBCLK_ipd_1 <= PLBCLK_ipd after in_delay; RSTC405RESETCHIP_ipd_1 <= RSTC405RESETCHIP_ipd after in_delay; RSTC405RESETCORE_ipd_1 <= RSTC405RESETCORE_ipd after in_delay; RSTC405RESETSYS_ipd_1 <= RSTC405RESETSYS_ipd after in_delay; TIEC405DETERMINISTICMULT_ipd_1 <= TIEC405DETERMINISTICMULT_ipd after in_delay; TIEC405DISOPERANDFWD_ipd_1 <= TIEC405DISOPERANDFWD_ipd after in_delay; TIEC405MMUEN_ipd_1 <= TIEC405MMUEN_ipd after in_delay; TIEDSOCMDCRADDR_ipd_1 <= TIEDSOCMDCRADDR_ipd after in_delay; TIEISOCMDCRADDR_ipd_1 <= TIEISOCMDCRADDR_ipd after in_delay; TRCC405TRACEDISABLE_ipd_1 <= TRCC405TRACEDISABLE_ipd after in_delay; TRCC405TRIGGEREVENTIN_ipd_1 <= TRCC405TRIGGEREVENTIN_ipd after in_delay; IPPC405_SWIFT : PPC405_SWIFT_BUS port map ( BUS_CLK => FPGA_CCLK, BUS_RESET => FPGA_BUS_RESET_delay, GSR => GSR_delay , GWE => FPGA_GWE_delay, GHIGHB => FPGA_GHIGHB_delay, CPMC405CPUCLKEN => CPMC405CPUCLKEN_ipd_1 , CPMC405JTAGCLKEN => CPMC405JTAGCLKEN_ipd_1 , CPMC405TIMERCLKEN => CPMC405TIMERCLKEN_ipd_1 , C405JTGPGMOUT => C405JTGPGMOUT_OUT , MCBCPUCLKEN => MCBCPUCLKEN_ipd_1 , MCBJTAGEN => MCBJTAGEN_ipd_1 , MCBTIMEREN => MCBTIMEREN_ipd_1 , MCPPCRST => MCPPCRST_ipd_1 , C405TRCODDEXECUTIONSTATUS => C405TRCODDEXECUTIONSTATUS_OUT , C405TRCEVENEXECUTIONSTATUS => C405TRCEVENEXECUTIONSTATUS_OUT , CPMC405CLOCK => CPMC405CLOCK , CPMC405CORECLKINACTIVE => CPMC405CORECLKINACTIVE_ipd_1 , PLBCLK => PLBCLK , CPMC405TIMERTICK => CPMC405TIMERTICK_ipd_1 , C405CPMMSREE => C405CPMMSREE_OUT , C405CPMMSRCE => C405CPMMSRCE_OUT , C405CPMTIMERIRQ => C405CPMTIMERIRQ_OUT , C405CPMTIMERRESETREQ => C405CPMTIMERRESETREQ_OUT , C405CPMCORESLEEPREQ => C405CPMCORESLEEPREQ_OUT , TIEC405DISOPERANDFWD => TIEC405DISOPERANDFWD_ipd_1 , TIEC405DETERMINISTICMULT => TIEC405DETERMINISTICMULT_ipd_1 , TIEC405MMUEN => TIEC405MMUEN_ipd_1 , TIEC405PVR => ppcuser_binary , C405XXXMACHINECHECK => C405XXXMACHINECHECK_OUT , C405RSTCHIPRESETREQ => C405RSTCHIPRESETREQ_OUT , C405RSTCORERESETREQ => C405RSTCORERESETREQ_OUT , C405RSTSYSRESETREQ => C405RSTSYSRESETREQ_OUT , RSTC405RESETCHIP => RSTC405RESETCHIP_ipd_1 , RSTC405RESETCORE => RSTC405RESETCORE_ipd_1 , RSTC405RESETSYS => RSTC405RESETSYS_ipd_1 , C405PLBICUREQUEST => C405PLBICUREQUEST_OUT , C405PLBICUPRIORITY => C405PLBICUPRIORITY_OUT , C405PLBICUCACHEABLE => C405PLBICUCACHEABLE_OUT , C405PLBICUABUS => C405PLBICUABUS_OUT , C405PLBICUSIZE => C405PLBICUSIZE_OUT , C405PLBICUABORT => C405PLBICUABORT_OUT , C405PLBICUU0ATTR => C405PLBICUU0ATTR_OUT , PLBC405ICUADDRACK => PLBC405ICUADDRACK_ipd_1 , PLBC405ICUBUSY => PLBC405ICUBUSY_ipd_1 , PLBC405ICUERR => PLBC405ICUERR_ipd_1 , PLBC405ICURDDACK => PLBC405ICURDDACK_ipd_1 , PLBC405ICURDDBUS => PLBC405ICURDDBUS_ipd_1 , PLBC405ICUSSIZE1 => PLBC405ICUSSIZE1_ipd_1 , PLBC405ICURDWDADDR => PLBC405ICURDWDADDR_ipd_1 , C405PLBDCUREQUEST => C405PLBDCUREQUEST_OUT , C405PLBDCURNW => C405PLBDCURNW_OUT , C405PLBDCUABUS => C405PLBDCUABUS_OUT , C405PLBDCUBE => C405PLBDCUBE_OUT , C405PLBDCUCACHEABLE => C405PLBDCUCACHEABLE_OUT , C405PLBDCUGUARDED => C405PLBDCUGUARDED_OUT , C405PLBDCUPRIORITY => C405PLBDCUPRIORITY_OUT , C405PLBDCUSIZE2 => C405PLBDCUSIZE2_OUT , C405PLBDCUABORT => C405PLBDCUABORT_OUT , C405PLBDCUWRDBUS => C405PLBDCUWRDBUS_OUT , C405PLBDCUU0ATTR => C405PLBDCUU0ATTR_OUT , C405PLBDCUWRITETHRU => C405PLBDCUWRITETHRU_OUT , PLBC405DCUADDRACK => PLBC405DCUADDRACK_ipd_1 , PLBC405DCUBUSY => PLBC405DCUBUSY_ipd_1 , PLBC405DCUERR => PLBC405DCUERR_ipd_1 , PLBC405DCURDDACK => PLBC405DCURDDACK_ipd_1 , PLBC405DCURDDBUS => PLBC405DCURDDBUS_ipd_1 , PLBC405DCURDWDADDR => PLBC405DCURDWDADDR_ipd_1 , PLBC405DCUSSIZE1 => PLBC405DCUSSIZE1_ipd_1 , PLBC405DCUWRDACK => PLBC405DCUWRDACK_ipd_1 , ISOCMBRAMRDABUS => ISOCMBRAMRDABUS_OUT , ISOCMBRAMWRABUS => ISOCMBRAMWRABUS_OUT , ISOCMBRAMEN => ISOCMBRAMEN_OUT , ISOCMBRAMODDWRITEEN => ISOCMBRAMODDWRITEEN_OUT , ISOCMBRAMEVENWRITEEN => ISOCMBRAMEVENWRITEEN_OUT , ISOCMBRAMWRDBUS => ISOCMBRAMWRDBUS_OUT , BRAMISOCMRDDBUS => BRAMISOCMRDDBUS_ipd_1 , TIEISOCMDCRADDR => TIEISOCMDCRADDR_ipd_1 , ISARCVALUE => ISARCVALUE_ipd_1 , ISCNTLVALUE => ISCNTLVALUE_ipd_1 , BRAMISOCMCLK => BRAMISOCMCLK , DSOCMBRAMABUS => DSOCMBRAMABUS_OUT , DSOCMBRAMBYTEWRITE => DSOCMBRAMBYTEWRITE_OUT , DSOCMBRAMEN => DSOCMBRAMEN_OUT , DSOCMBRAMWRDBUS => DSOCMBRAMWRDBUS_OUT , BRAMDSOCMRDDBUS => BRAMDSOCMRDDBUS_ipd_1 , DSOCMBUSY => DSOCMBUSY_OUT , TIEDSOCMDCRADDR => TIEDSOCMDCRADDR_ipd_1 , DSARCVALUE => DSARCVALUE_ipd_1 , DSCNTLVALUE => DSCNTLVALUE_ipd_1 , BRAMDSOCMCLK => BRAMDSOCMCLK , C405DCRREAD => C405DCRREAD_OUT , C405DCRWRITE => C405DCRWRITE_OUT , C405DCRABUS => C405DCRABUS_OUT , C405DCRDBUSOUT => C405DCRDBUSOUT_OUT , DCRC405ACK => DCRC405ACK_ipd_1 , DCRC405DBUSIN => DCRC405DBUSIN_ipd_1 , EICC405EXTINPUTIRQ => EICC405EXTINPUTIRQ_ipd_1 , EICC405CRITINPUTIRQ => EICC405CRITINPUTIRQ_ipd_1 , JTGC405BNDSCANTDO => JTGC405BNDSCANTDO_ipd_1 , JTGC405TCK => JTGC405TCK_ipd_1 , JTGC405TDI => JTGC405TDI_ipd_1 , JTGC405TMS => JTGC405TMS_ipd_1 , JTGC405TRSTNEG => JTGC405TRSTNEG_ipd_1 , C405JTGTDO => C405JTGTDO_OUT , C405JTGTDOEN => C405JTGTDOEN_OUT , C405JTGEXTEST => C405JTGEXTEST_OUT , C405JTGCAPTUREDR => C405JTGCAPTUREDR_OUT , C405JTGSHIFTDR => C405JTGSHIFTDR_OUT , C405JTGUPDATEDR => C405JTGUPDATEDR_OUT , DBGC405DEBUGHALT => DBGC405DEBUGHALT_ipd_1 , DBGC405UNCONDDEBUGEVENT => DBGC405UNCONDDEBUGEVENT_ipd_1 , DBGC405EXTBUSHOLDACK => DBGC405EXTBUSHOLDACK_ipd_1 , C405DBGMSRWE => C405DBGMSRWE_OUT , C405DBGSTOPACK => C405DBGSTOPACK_OUT , C405DBGWBCOMPLETE => C405DBGWBCOMPLETE_OUT , C405DBGWBFULL => C405DBGWBFULL_OUT , C405DBGWBIAR => C405DBGWBIAR_OUT , C405TRCTRIGGEREVENTOUT => C405TRCTRIGGEREVENTOUT_OUT , C405TRCTRIGGEREVENTTYPE => C405TRCTRIGGEREVENTTYPE_OUT , C405TRCCYCLE => C405TRCCYCLE_OUT , C405TRCTRACESTATUS => C405TRCTRACESTATUS_OUT , TRCC405TRACEDISABLE => TRCC405TRACEDISABLE_ipd_1 , TRCC405TRIGGEREVENTIN => TRCC405TRIGGEREVENTIN_ipd_1 ); FPGA_CCLK <= NOT(FPGA_CCLK) after 5000 ps; FPGA_POR <= '0' after 100 ps; GSR_OR <= FPGA_GSR or GSR; start_blk : FPGA_startup port map ( bus_reset => FPGA_BUS_RESET, ghigh_b => FPGA_GHIGHB, gsr => FPGA_GSR, gwe => FPGA_GWE, shutdown => FPGA_SHUTDOWN, cclk => FPGA_CCLK, por => FPGA_POR); FPGA_BUS_RESET_delay <= FPGA_BUS_RESET after 10 ps ; GSR_delay <= GSR_OR after 10 ps; FPGA_GWE_delay <= FPGA_GWE after 10 ps; FPGA_GHIGHB_delay <= FPGA_GHIGHB after 10 ps; TIMING : process VARIABLE DSOCMBRAMABUS8_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS9_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS10_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS11_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS12_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS13_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS14_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS15_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS16_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS17_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS18_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS19_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS20_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS21_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS22_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS23_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS24_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS25_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS26_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS27_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS28_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMABUS29_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMBYTEWRITE0_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMBYTEWRITE1_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMBYTEWRITE2_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMBYTEWRITE3_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMEN_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS0_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS1_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS2_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS3_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS4_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS5_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS6_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS7_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS8_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS9_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS10_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS11_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS12_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS13_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS14_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS15_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS16_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS17_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS18_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS19_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS20_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS21_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS22_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS23_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS24_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS25_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS26_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS27_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS28_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS29_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS30_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBRAMWRDBUS31_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMEN_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMEVENWRITEEN_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMODDWRITEEN_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS8_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS9_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS10_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS11_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS12_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS13_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS14_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS15_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS16_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS17_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS18_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS19_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS20_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS21_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS22_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS23_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS24_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS25_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS26_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS27_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMRDABUS28_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS8_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS9_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS10_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS11_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS12_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS13_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS14_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS15_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS16_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS17_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS18_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS19_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS20_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS21_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS22_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS23_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS24_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS25_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS26_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS27_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRABUS28_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS0_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS1_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS2_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS3_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS4_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS5_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS6_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS7_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS8_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS9_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS10_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS11_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS12_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS13_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS14_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS15_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS16_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS17_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS18_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS19_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS20_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS21_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS22_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS23_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS24_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS25_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS26_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS27_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS28_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS29_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS30_GlitchData: VitalGlitchDataType; VARIABLE ISOCMBRAMWRDBUS31_GlitchData: VitalGlitchDataType; VARIABLE C405CPMCORESLEEPREQ_GlitchData: VitalGlitchDataType; VARIABLE C405CPMMSRCE_GlitchData: VitalGlitchDataType; VARIABLE C405CPMMSREE_GlitchData: VitalGlitchDataType; VARIABLE C405CPMTIMERIRQ_GlitchData: VitalGlitchDataType; VARIABLE C405CPMTIMERRESETREQ_GlitchData: VitalGlitchDataType; VARIABLE C405DBGMSRWE_GlitchData: VitalGlitchDataType; VARIABLE C405DBGSTOPACK_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBCOMPLETE_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBFULL_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR0_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR1_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR2_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR3_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR4_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR5_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR6_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR7_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR8_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR9_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR10_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR11_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR12_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR13_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR14_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR15_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR16_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR17_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR18_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR19_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR20_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR21_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR22_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR23_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR24_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR25_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR26_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR27_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR28_GlitchData: VitalGlitchDataType; VARIABLE C405DBGWBIAR29_GlitchData: VitalGlitchDataType; VARIABLE C405DCRABUS0_GlitchData: VitalGlitchDataType; VARIABLE C405DCRABUS1_GlitchData: VitalGlitchDataType; VARIABLE C405DCRABUS2_GlitchData: VitalGlitchDataType; VARIABLE C405DCRABUS3_GlitchData: VitalGlitchDataType; VARIABLE C405DCRABUS4_GlitchData: VitalGlitchDataType; VARIABLE C405DCRABUS5_GlitchData: VitalGlitchDataType; VARIABLE C405DCRABUS6_GlitchData: VitalGlitchDataType; VARIABLE C405DCRABUS7_GlitchData: VitalGlitchDataType; VARIABLE C405DCRABUS8_GlitchData: VitalGlitchDataType; VARIABLE C405DCRABUS9_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT0_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT1_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT2_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT3_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT4_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT5_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT6_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT7_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT8_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT9_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT10_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT11_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT12_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT13_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT14_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT15_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT16_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT17_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT18_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT19_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT20_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT21_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT22_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT23_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT24_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT25_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT26_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT27_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT28_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT29_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT30_GlitchData: VitalGlitchDataType; VARIABLE C405DCRDBUSOUT31_GlitchData: VitalGlitchDataType; VARIABLE C405DCRREAD_GlitchData: VitalGlitchDataType; VARIABLE C405DCRWRITE_GlitchData: VitalGlitchDataType; VARIABLE C405JTGPGMOUT_GlitchData: VitalGlitchDataType; VARIABLE C405RSTCHIPRESETREQ_GlitchData: VitalGlitchDataType; VARIABLE C405RSTCORERESETREQ_GlitchData: VitalGlitchDataType; VARIABLE C405RSTSYSRESETREQ_GlitchData: VitalGlitchDataType; VARIABLE C405TRCCYCLE_GlitchData: VitalGlitchDataType; VARIABLE C405TRCEVENEXECUTIONSTATUS0_GlitchData: VitalGlitchDataType; VARIABLE C405TRCEVENEXECUTIONSTATUS1_GlitchData: VitalGlitchDataType; VARIABLE C405TRCODDEXECUTIONSTATUS0_GlitchData: VitalGlitchDataType; VARIABLE C405TRCODDEXECUTIONSTATUS1_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRACESTATUS0_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRACESTATUS1_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRACESTATUS2_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRACESTATUS3_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTOUT_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTTYPE0_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTTYPE1_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTTYPE2_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTTYPE3_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTTYPE4_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTTYPE5_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTTYPE6_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTTYPE7_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTTYPE8_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTTYPE9_GlitchData: VitalGlitchDataType; VARIABLE C405TRCTRIGGEREVENTTYPE10_GlitchData: VitalGlitchDataType; VARIABLE C405XXXMACHINECHECK_GlitchData: VitalGlitchDataType; VARIABLE DSOCMBUSY_GlitchData: VitalGlitchDataType; VARIABLE C405JTGCAPTUREDR_GlitchData: VitalGlitchDataType; VARIABLE C405JTGEXTEST_GlitchData: VitalGlitchDataType; VARIABLE C405JTGSHIFTDR_GlitchData: VitalGlitchDataType; VARIABLE C405JTGTDO_GlitchData: VitalGlitchDataType; VARIABLE C405JTGTDOEN_GlitchData: VitalGlitchDataType; VARIABLE C405JTGUPDATEDR_GlitchData: VitalGlitchDataType; VARIABLE Tviol_CPMC405CORECLKINACTIVE_jtgc405tck_posedge: STD_ULOGIC := '0'; VARIABLE Tmkr_CPMC405CORECLKINACTIVE_jtgc405tck_posedge: VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_DBGC405EXTBUSHOLDACK_jtgc405tck_posedge: STD_ULOGIC := '0'; VARIABLE Tmkr_DBGC405EXTBUSHOLDACK_jtgc405tck_posedge: VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_JTGC405BNDSCANTDO_jtgc405tck_posedge: STD_ULOGIC := '0'; VARIABLE Tmkr_JTGC405BNDSCANTDO_jtgc405tck_posedge: VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_JTGC405TDI_jtgc405tck_posedge: STD_ULOGIC := '0'; VARIABLE Tmkr_JTGC405TDI_jtgc405tck_posedge: VitalTimingDataType := VitalTimingDataInit; VARIABLE Tviol_JTGC405TMS_jtgc405tck_posedge: STD_ULOGIC := '0'; VARIABLE Tmkr_JTGC405TMS_jtgc405tck_posedge: VitalTimingDataType := VitalTimingDataInit; VARIABLE C405PLBDCUABORT_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS0_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS1_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS2_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS3_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS4_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS5_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS6_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS7_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS8_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS9_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS10_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS11_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS12_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS13_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS14_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS15_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS16_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS17_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS18_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS19_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS20_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS21_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS22_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS23_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS24_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS25_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS26_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS27_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS28_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS29_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS30_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUABUS31_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUBE0_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUBE1_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUBE2_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUBE3_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUBE4_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUBE5_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUBE6_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUBE7_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUCACHEABLE_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUGUARDED_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUPRIORITY0_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUPRIORITY1_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUREQUEST_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCURNW_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUSIZE2_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUU0ATTR_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS0_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS1_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS2_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS3_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS4_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS5_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS6_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS7_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS8_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS9_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS10_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS11_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS12_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS13_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS14_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS15_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS16_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS17_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS18_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS19_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS20_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS21_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS22_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS23_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS24_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS25_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS26_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS27_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS28_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS29_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS30_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS31_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS32_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS33_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS34_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS35_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS36_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS37_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS38_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS39_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS40_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS41_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS42_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS43_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS44_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS45_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS46_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS47_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS48_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS49_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS50_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS51_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS52_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS53_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS54_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS55_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS56_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS57_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS58_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS59_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS60_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS61_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS62_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRDBUS63_GlitchData: VitalGlitchDataType; VARIABLE C405PLBDCUWRITETHRU_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABORT_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS0_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS1_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS2_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS3_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS4_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS5_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS6_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS7_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS8_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS9_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS10_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS11_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS12_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS13_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS14_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS15_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS16_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS17_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS18_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS19_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS20_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS21_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS22_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS23_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS24_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS25_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS26_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS27_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS28_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUABUS29_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUCACHEABLE_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUPRIORITY0_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUPRIORITY1_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUREQUEST_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUSIZE2_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUSIZE3_GlitchData: VitalGlitchDataType; VARIABLE C405PLBICUU0ATTR_GlitchData: VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(8), GlitchData => DSOCMBRAMABUS8_GlitchData, OutSignalName => "DSOCMBRAMABUS(8)", OutTemp => DSOCMBRAMABUS_OUT(8), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(9), GlitchData => DSOCMBRAMABUS9_GlitchData, OutSignalName => "DSOCMBRAMABUS(9)", OutTemp => DSOCMBRAMABUS_OUT(9), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(10), GlitchData => DSOCMBRAMABUS10_GlitchData, OutSignalName => "DSOCMBRAMABUS(10)", OutTemp => DSOCMBRAMABUS_OUT(10), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(11), GlitchData => DSOCMBRAMABUS11_GlitchData, OutSignalName => "DSOCMBRAMABUS(11)", OutTemp => DSOCMBRAMABUS_OUT(11), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(12), GlitchData => DSOCMBRAMABUS12_GlitchData, OutSignalName => "DSOCMBRAMABUS(12)", OutTemp => DSOCMBRAMABUS_OUT(12), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(13), GlitchData => DSOCMBRAMABUS13_GlitchData, OutSignalName => "DSOCMBRAMABUS(13)", OutTemp => DSOCMBRAMABUS_OUT(13), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(14), GlitchData => DSOCMBRAMABUS14_GlitchData, OutSignalName => "DSOCMBRAMABUS(14)", OutTemp => DSOCMBRAMABUS_OUT(14), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(15), GlitchData => DSOCMBRAMABUS15_GlitchData, OutSignalName => "DSOCMBRAMABUS(15)", OutTemp => DSOCMBRAMABUS_OUT(15), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(16), GlitchData => DSOCMBRAMABUS16_GlitchData, OutSignalName => "DSOCMBRAMABUS(16)", OutTemp => DSOCMBRAMABUS_OUT(16), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(17), GlitchData => DSOCMBRAMABUS17_GlitchData, OutSignalName => "DSOCMBRAMABUS(17)", OutTemp => DSOCMBRAMABUS_OUT(17), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(18), GlitchData => DSOCMBRAMABUS18_GlitchData, OutSignalName => "DSOCMBRAMABUS(18)", OutTemp => DSOCMBRAMABUS_OUT(18), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(19), GlitchData => DSOCMBRAMABUS19_GlitchData, OutSignalName => "DSOCMBRAMABUS(19)", OutTemp => DSOCMBRAMABUS_OUT(19), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(20), GlitchData => DSOCMBRAMABUS20_GlitchData, OutSignalName => "DSOCMBRAMABUS(20)", OutTemp => DSOCMBRAMABUS_OUT(20), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(21), GlitchData => DSOCMBRAMABUS21_GlitchData, OutSignalName => "DSOCMBRAMABUS(21)", OutTemp => DSOCMBRAMABUS_OUT(21), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(22), GlitchData => DSOCMBRAMABUS22_GlitchData, OutSignalName => "DSOCMBRAMABUS(22)", OutTemp => DSOCMBRAMABUS_OUT(22), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(23), GlitchData => DSOCMBRAMABUS23_GlitchData, OutSignalName => "DSOCMBRAMABUS(23)", OutTemp => DSOCMBRAMABUS_OUT(23), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(24), GlitchData => DSOCMBRAMABUS24_GlitchData, OutSignalName => "DSOCMBRAMABUS(24)", OutTemp => DSOCMBRAMABUS_OUT(24), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(25), GlitchData => DSOCMBRAMABUS25_GlitchData, OutSignalName => "DSOCMBRAMABUS(25)", OutTemp => DSOCMBRAMABUS_OUT(25), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(26), GlitchData => DSOCMBRAMABUS26_GlitchData, OutSignalName => "DSOCMBRAMABUS(26)", OutTemp => DSOCMBRAMABUS_OUT(26), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(27), GlitchData => DSOCMBRAMABUS27_GlitchData, OutSignalName => "DSOCMBRAMABUS(27)", OutTemp => DSOCMBRAMABUS_OUT(27), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(28), GlitchData => DSOCMBRAMABUS28_GlitchData, OutSignalName => "DSOCMBRAMABUS(28)", OutTemp => DSOCMBRAMABUS_OUT(28), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(29), GlitchData => DSOCMBRAMABUS29_GlitchData, OutSignalName => "DSOCMBRAMABUS(29)", OutTemp => DSOCMBRAMABUS_OUT(29), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMBYTEWRITE(0), GlitchData => DSOCMBRAMBYTEWRITE0_GlitchData, OutSignalName => "DSOCMBRAMBYTEWRITE(0)", OutTemp => DSOCMBRAMBYTEWRITE_OUT(0), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMBYTEWRITE(1), GlitchData => DSOCMBRAMBYTEWRITE1_GlitchData, OutSignalName => "DSOCMBRAMBYTEWRITE(1)", OutTemp => DSOCMBRAMBYTEWRITE_OUT(1), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMBYTEWRITE(2), GlitchData => DSOCMBRAMBYTEWRITE2_GlitchData, OutSignalName => "DSOCMBRAMBYTEWRITE(2)", OutTemp => DSOCMBRAMBYTEWRITE_OUT(2), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMBYTEWRITE(3), GlitchData => DSOCMBRAMBYTEWRITE3_GlitchData, OutSignalName => "DSOCMBRAMBYTEWRITE(3)", OutTemp => DSOCMBRAMBYTEWRITE_OUT(3), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMEN, GlitchData => DSOCMBRAMEN_GlitchData, OutSignalName => "DSOCMBRAMEN", OutTemp => DSOCMBRAMEN_OUT, Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(0), GlitchData => DSOCMBRAMWRDBUS0_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(0)", OutTemp => DSOCMBRAMWRDBUS_OUT(0), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(1), GlitchData => DSOCMBRAMWRDBUS1_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(1)", OutTemp => DSOCMBRAMWRDBUS_OUT(1), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(2), GlitchData => DSOCMBRAMWRDBUS2_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(2)", OutTemp => DSOCMBRAMWRDBUS_OUT(2), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(3), GlitchData => DSOCMBRAMWRDBUS3_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(3)", OutTemp => DSOCMBRAMWRDBUS_OUT(3), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(4), GlitchData => DSOCMBRAMWRDBUS4_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(4)", OutTemp => DSOCMBRAMWRDBUS_OUT(4), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(5), GlitchData => DSOCMBRAMWRDBUS5_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(5)", OutTemp => DSOCMBRAMWRDBUS_OUT(5), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(6), GlitchData => DSOCMBRAMWRDBUS6_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(6)", OutTemp => DSOCMBRAMWRDBUS_OUT(6), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(7), GlitchData => DSOCMBRAMWRDBUS7_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(7)", OutTemp => DSOCMBRAMWRDBUS_OUT(7), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(8), GlitchData => DSOCMBRAMWRDBUS8_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(8)", OutTemp => DSOCMBRAMWRDBUS_OUT(8), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(9), GlitchData => DSOCMBRAMWRDBUS9_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(9)", OutTemp => DSOCMBRAMWRDBUS_OUT(9), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(10), GlitchData => DSOCMBRAMWRDBUS10_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(10)", OutTemp => DSOCMBRAMWRDBUS_OUT(10), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(11), GlitchData => DSOCMBRAMWRDBUS11_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(11)", OutTemp => DSOCMBRAMWRDBUS_OUT(11), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(12), GlitchData => DSOCMBRAMWRDBUS12_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(12)", OutTemp => DSOCMBRAMWRDBUS_OUT(12), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(13), GlitchData => DSOCMBRAMWRDBUS13_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(13)", OutTemp => DSOCMBRAMWRDBUS_OUT(13), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(14), GlitchData => DSOCMBRAMWRDBUS14_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(14)", OutTemp => DSOCMBRAMWRDBUS_OUT(14), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(15), GlitchData => DSOCMBRAMWRDBUS15_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(15)", OutTemp => DSOCMBRAMWRDBUS_OUT(15), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(16), GlitchData => DSOCMBRAMWRDBUS16_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(16)", OutTemp => DSOCMBRAMWRDBUS_OUT(16), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(17), GlitchData => DSOCMBRAMWRDBUS17_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(17)", OutTemp => DSOCMBRAMWRDBUS_OUT(17), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(18), GlitchData => DSOCMBRAMWRDBUS18_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(18)", OutTemp => DSOCMBRAMWRDBUS_OUT(18), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(19), GlitchData => DSOCMBRAMWRDBUS19_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(19)", OutTemp => DSOCMBRAMWRDBUS_OUT(19), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(20), GlitchData => DSOCMBRAMWRDBUS20_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(20)", OutTemp => DSOCMBRAMWRDBUS_OUT(20), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(21), GlitchData => DSOCMBRAMWRDBUS21_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(21)", OutTemp => DSOCMBRAMWRDBUS_OUT(21), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(22), GlitchData => DSOCMBRAMWRDBUS22_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(22)", OutTemp => DSOCMBRAMWRDBUS_OUT(22), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(23), GlitchData => DSOCMBRAMWRDBUS23_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(23)", OutTemp => DSOCMBRAMWRDBUS_OUT(23), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(24), GlitchData => DSOCMBRAMWRDBUS24_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(24)", OutTemp => DSOCMBRAMWRDBUS_OUT(24), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(25), GlitchData => DSOCMBRAMWRDBUS25_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(25)", OutTemp => DSOCMBRAMWRDBUS_OUT(25), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(26), GlitchData => DSOCMBRAMWRDBUS26_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(26)", OutTemp => DSOCMBRAMWRDBUS_OUT(26), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(27), GlitchData => DSOCMBRAMWRDBUS27_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(27)", OutTemp => DSOCMBRAMWRDBUS_OUT(27), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(28), GlitchData => DSOCMBRAMWRDBUS28_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(28)", OutTemp => DSOCMBRAMWRDBUS_OUT(28), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(29), GlitchData => DSOCMBRAMWRDBUS29_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(29)", OutTemp => DSOCMBRAMWRDBUS_OUT(29), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(30), GlitchData => DSOCMBRAMWRDBUS30_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(30)", OutTemp => DSOCMBRAMWRDBUS_OUT(30), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(31), GlitchData => DSOCMBRAMWRDBUS31_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(31)", OutTemp => DSOCMBRAMWRDBUS_OUT(31), Paths => (0 => (bramdsocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMEN, GlitchData => ISOCMBRAMEN_GlitchData, OutSignalName => "ISOCMBRAMEN", OutTemp => ISOCMBRAMEN_OUT, Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMEVENWRITEEN, GlitchData => ISOCMBRAMEVENWRITEEN_GlitchData, OutSignalName => "ISOCMBRAMEVENWRITEEN", OutTemp => ISOCMBRAMEVENWRITEEN_OUT, Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMODDWRITEEN, GlitchData => ISOCMBRAMODDWRITEEN_GlitchData, OutSignalName => "ISOCMBRAMODDWRITEEN", OutTemp => ISOCMBRAMODDWRITEEN_OUT, Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(8), GlitchData => ISOCMBRAMRDABUS8_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(8)", OutTemp => ISOCMBRAMRDABUS_OUT(8), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(9), GlitchData => ISOCMBRAMRDABUS9_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(9)", OutTemp => ISOCMBRAMRDABUS_OUT(9), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(10), GlitchData => ISOCMBRAMRDABUS10_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(10)", OutTemp => ISOCMBRAMRDABUS_OUT(10), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(11), GlitchData => ISOCMBRAMRDABUS11_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(11)", OutTemp => ISOCMBRAMRDABUS_OUT(11), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(12), GlitchData => ISOCMBRAMRDABUS12_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(12)", OutTemp => ISOCMBRAMRDABUS_OUT(12), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(13), GlitchData => ISOCMBRAMRDABUS13_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(13)", OutTemp => ISOCMBRAMRDABUS_OUT(13), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(14), GlitchData => ISOCMBRAMRDABUS14_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(14)", OutTemp => ISOCMBRAMRDABUS_OUT(14), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(15), GlitchData => ISOCMBRAMRDABUS15_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(15)", OutTemp => ISOCMBRAMRDABUS_OUT(15), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(16), GlitchData => ISOCMBRAMRDABUS16_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(16)", OutTemp => ISOCMBRAMRDABUS_OUT(16), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(17), GlitchData => ISOCMBRAMRDABUS17_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(17)", OutTemp => ISOCMBRAMRDABUS_OUT(17), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(18), GlitchData => ISOCMBRAMRDABUS18_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(18)", OutTemp => ISOCMBRAMRDABUS_OUT(18), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(19), GlitchData => ISOCMBRAMRDABUS19_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(19)", OutTemp => ISOCMBRAMRDABUS_OUT(19), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(20), GlitchData => ISOCMBRAMRDABUS20_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(20)", OutTemp => ISOCMBRAMRDABUS_OUT(20), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(21), GlitchData => ISOCMBRAMRDABUS21_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(21)", OutTemp => ISOCMBRAMRDABUS_OUT(21), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(22), GlitchData => ISOCMBRAMRDABUS22_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(22)", OutTemp => ISOCMBRAMRDABUS_OUT(22), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(23), GlitchData => ISOCMBRAMRDABUS23_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(23)", OutTemp => ISOCMBRAMRDABUS_OUT(23), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(24), GlitchData => ISOCMBRAMRDABUS24_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(24)", OutTemp => ISOCMBRAMRDABUS_OUT(24), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(25), GlitchData => ISOCMBRAMRDABUS25_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(25)", OutTemp => ISOCMBRAMRDABUS_OUT(25), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(26), GlitchData => ISOCMBRAMRDABUS26_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(26)", OutTemp => ISOCMBRAMRDABUS_OUT(26), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(27), GlitchData => ISOCMBRAMRDABUS27_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(27)", OutTemp => ISOCMBRAMRDABUS_OUT(27), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(28), GlitchData => ISOCMBRAMRDABUS28_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(28)", OutTemp => ISOCMBRAMRDABUS_OUT(28), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(8), GlitchData => ISOCMBRAMWRABUS8_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(8)", OutTemp => ISOCMBRAMWRABUS_OUT(8), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(9), GlitchData => ISOCMBRAMWRABUS9_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(9)", OutTemp => ISOCMBRAMWRABUS_OUT(9), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(10), GlitchData => ISOCMBRAMWRABUS10_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(10)", OutTemp => ISOCMBRAMWRABUS_OUT(10), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(11), GlitchData => ISOCMBRAMWRABUS11_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(11)", OutTemp => ISOCMBRAMWRABUS_OUT(11), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(12), GlitchData => ISOCMBRAMWRABUS12_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(12)", OutTemp => ISOCMBRAMWRABUS_OUT(12), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(13), GlitchData => ISOCMBRAMWRABUS13_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(13)", OutTemp => ISOCMBRAMWRABUS_OUT(13), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(14), GlitchData => ISOCMBRAMWRABUS14_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(14)", OutTemp => ISOCMBRAMWRABUS_OUT(14), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(15), GlitchData => ISOCMBRAMWRABUS15_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(15)", OutTemp => ISOCMBRAMWRABUS_OUT(15), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(16), GlitchData => ISOCMBRAMWRABUS16_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(16)", OutTemp => ISOCMBRAMWRABUS_OUT(16), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(17), GlitchData => ISOCMBRAMWRABUS17_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(17)", OutTemp => ISOCMBRAMWRABUS_OUT(17), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(18), GlitchData => ISOCMBRAMWRABUS18_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(18)", OutTemp => ISOCMBRAMWRABUS_OUT(18), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(19), GlitchData => ISOCMBRAMWRABUS19_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(19)", OutTemp => ISOCMBRAMWRABUS_OUT(19), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(20), GlitchData => ISOCMBRAMWRABUS20_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(20)", OutTemp => ISOCMBRAMWRABUS_OUT(20), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(21), GlitchData => ISOCMBRAMWRABUS21_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(21)", OutTemp => ISOCMBRAMWRABUS_OUT(21), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(22), GlitchData => ISOCMBRAMWRABUS22_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(22)", OutTemp => ISOCMBRAMWRABUS_OUT(22), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(23), GlitchData => ISOCMBRAMWRABUS23_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(23)", OutTemp => ISOCMBRAMWRABUS_OUT(23), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(24), GlitchData => ISOCMBRAMWRABUS24_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(24)", OutTemp => ISOCMBRAMWRABUS_OUT(24), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(25), GlitchData => ISOCMBRAMWRABUS25_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(25)", OutTemp => ISOCMBRAMWRABUS_OUT(25), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(26), GlitchData => ISOCMBRAMWRABUS26_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(26)", OutTemp => ISOCMBRAMWRABUS_OUT(26), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(27), GlitchData => ISOCMBRAMWRABUS27_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(27)", OutTemp => ISOCMBRAMWRABUS_OUT(27), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(28), GlitchData => ISOCMBRAMWRABUS28_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(28)", OutTemp => ISOCMBRAMWRABUS_OUT(28), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(0), GlitchData => ISOCMBRAMWRDBUS0_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(0)", OutTemp => ISOCMBRAMWRDBUS_OUT(0), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(1), GlitchData => ISOCMBRAMWRDBUS1_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(1)", OutTemp => ISOCMBRAMWRDBUS_OUT(1), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(2), GlitchData => ISOCMBRAMWRDBUS2_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(2)", OutTemp => ISOCMBRAMWRDBUS_OUT(2), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(3), GlitchData => ISOCMBRAMWRDBUS3_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(3)", OutTemp => ISOCMBRAMWRDBUS_OUT(3), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(4), GlitchData => ISOCMBRAMWRDBUS4_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(4)", OutTemp => ISOCMBRAMWRDBUS_OUT(4), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(5), GlitchData => ISOCMBRAMWRDBUS5_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(5)", OutTemp => ISOCMBRAMWRDBUS_OUT(5), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(6), GlitchData => ISOCMBRAMWRDBUS6_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(6)", OutTemp => ISOCMBRAMWRDBUS_OUT(6), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(7), GlitchData => ISOCMBRAMWRDBUS7_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(7)", OutTemp => ISOCMBRAMWRDBUS_OUT(7), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(8), GlitchData => ISOCMBRAMWRDBUS8_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(8)", OutTemp => ISOCMBRAMWRDBUS_OUT(8), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(9), GlitchData => ISOCMBRAMWRDBUS9_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(9)", OutTemp => ISOCMBRAMWRDBUS_OUT(9), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(10), GlitchData => ISOCMBRAMWRDBUS10_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(10)", OutTemp => ISOCMBRAMWRDBUS_OUT(10), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(11), GlitchData => ISOCMBRAMWRDBUS11_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(11)", OutTemp => ISOCMBRAMWRDBUS_OUT(11), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(12), GlitchData => ISOCMBRAMWRDBUS12_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(12)", OutTemp => ISOCMBRAMWRDBUS_OUT(12), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(13), GlitchData => ISOCMBRAMWRDBUS13_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(13)", OutTemp => ISOCMBRAMWRDBUS_OUT(13), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(14), GlitchData => ISOCMBRAMWRDBUS14_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(14)", OutTemp => ISOCMBRAMWRDBUS_OUT(14), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(15), GlitchData => ISOCMBRAMWRDBUS15_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(15)", OutTemp => ISOCMBRAMWRDBUS_OUT(15), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(16), GlitchData => ISOCMBRAMWRDBUS16_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(16)", OutTemp => ISOCMBRAMWRDBUS_OUT(16), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(17), GlitchData => ISOCMBRAMWRDBUS17_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(17)", OutTemp => ISOCMBRAMWRDBUS_OUT(17), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(18), GlitchData => ISOCMBRAMWRDBUS18_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(18)", OutTemp => ISOCMBRAMWRDBUS_OUT(18), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(19), GlitchData => ISOCMBRAMWRDBUS19_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(19)", OutTemp => ISOCMBRAMWRDBUS_OUT(19), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(20), GlitchData => ISOCMBRAMWRDBUS20_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(20)", OutTemp => ISOCMBRAMWRDBUS_OUT(20), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(21), GlitchData => ISOCMBRAMWRDBUS21_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(21)", OutTemp => ISOCMBRAMWRDBUS_OUT(21), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(22), GlitchData => ISOCMBRAMWRDBUS22_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(22)", OutTemp => ISOCMBRAMWRDBUS_OUT(22), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(23), GlitchData => ISOCMBRAMWRDBUS23_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(23)", OutTemp => ISOCMBRAMWRDBUS_OUT(23), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(24), GlitchData => ISOCMBRAMWRDBUS24_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(24)", OutTemp => ISOCMBRAMWRDBUS_OUT(24), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(25), GlitchData => ISOCMBRAMWRDBUS25_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(25)", OutTemp => ISOCMBRAMWRDBUS_OUT(25), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(26), GlitchData => ISOCMBRAMWRDBUS26_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(26)", OutTemp => ISOCMBRAMWRDBUS_OUT(26), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(27), GlitchData => ISOCMBRAMWRDBUS27_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(27)", OutTemp => ISOCMBRAMWRDBUS_OUT(27), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(28), GlitchData => ISOCMBRAMWRDBUS28_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(28)", OutTemp => ISOCMBRAMWRDBUS_OUT(28), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(29), GlitchData => ISOCMBRAMWRDBUS29_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(29)", OutTemp => ISOCMBRAMWRDBUS_OUT(29), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(30), GlitchData => ISOCMBRAMWRDBUS30_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(30)", OutTemp => ISOCMBRAMWRDBUS_OUT(30), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(31), GlitchData => ISOCMBRAMWRDBUS31_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(31)", OutTemp => ISOCMBRAMWRDBUS_OUT(31), Paths => (0 => (bramisocmclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405CPMCORESLEEPREQ, GlitchData => C405CPMCORESLEEPREQ_GlitchData, OutSignalName => "C405CPMCORESLEEPREQ", OutTemp => C405CPMCORESLEEPREQ_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405CPMMSRCE, GlitchData => C405CPMMSRCE_GlitchData, OutSignalName => "C405CPMMSRCE", OutTemp => C405CPMMSRCE_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405CPMMSREE, GlitchData => C405CPMMSREE_GlitchData, OutSignalName => "C405CPMMSREE", OutTemp => C405CPMMSREE_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405CPMTIMERIRQ, GlitchData => C405CPMTIMERIRQ_GlitchData, OutSignalName => "C405CPMTIMERIRQ", OutTemp => C405CPMTIMERIRQ_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405CPMTIMERRESETREQ, GlitchData => C405CPMTIMERRESETREQ_GlitchData, OutSignalName => "C405CPMTIMERRESETREQ", OutTemp => C405CPMTIMERRESETREQ_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGMSRWE, GlitchData => C405DBGMSRWE_GlitchData, OutSignalName => "C405DBGMSRWE", OutTemp => C405DBGMSRWE_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGSTOPACK, GlitchData => C405DBGSTOPACK_GlitchData, OutSignalName => "C405DBGSTOPACK", OutTemp => C405DBGSTOPACK_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBCOMPLETE, GlitchData => C405DBGWBCOMPLETE_GlitchData, OutSignalName => "C405DBGWBCOMPLETE", OutTemp => C405DBGWBCOMPLETE_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBFULL, GlitchData => C405DBGWBFULL_GlitchData, OutSignalName => "C405DBGWBFULL", OutTemp => C405DBGWBFULL_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(0), GlitchData => C405DBGWBIAR0_GlitchData, OutSignalName => "C405DBGWBIAR(0)", OutTemp => C405DBGWBIAR_OUT(0), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(1), GlitchData => C405DBGWBIAR1_GlitchData, OutSignalName => "C405DBGWBIAR(1)", OutTemp => C405DBGWBIAR_OUT(1), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(2), GlitchData => C405DBGWBIAR2_GlitchData, OutSignalName => "C405DBGWBIAR(2)", OutTemp => C405DBGWBIAR_OUT(2), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(3), GlitchData => C405DBGWBIAR3_GlitchData, OutSignalName => "C405DBGWBIAR(3)", OutTemp => C405DBGWBIAR_OUT(3), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(4), GlitchData => C405DBGWBIAR4_GlitchData, OutSignalName => "C405DBGWBIAR(4)", OutTemp => C405DBGWBIAR_OUT(4), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(5), GlitchData => C405DBGWBIAR5_GlitchData, OutSignalName => "C405DBGWBIAR(5)", OutTemp => C405DBGWBIAR_OUT(5), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(6), GlitchData => C405DBGWBIAR6_GlitchData, OutSignalName => "C405DBGWBIAR(6)", OutTemp => C405DBGWBIAR_OUT(6), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(7), GlitchData => C405DBGWBIAR7_GlitchData, OutSignalName => "C405DBGWBIAR(7)", OutTemp => C405DBGWBIAR_OUT(7), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(8), GlitchData => C405DBGWBIAR8_GlitchData, OutSignalName => "C405DBGWBIAR(8)", OutTemp => C405DBGWBIAR_OUT(8), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(9), GlitchData => C405DBGWBIAR9_GlitchData, OutSignalName => "C405DBGWBIAR(9)", OutTemp => C405DBGWBIAR_OUT(9), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(10), GlitchData => C405DBGWBIAR10_GlitchData, OutSignalName => "C405DBGWBIAR(10)", OutTemp => C405DBGWBIAR_OUT(10), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(11), GlitchData => C405DBGWBIAR11_GlitchData, OutSignalName => "C405DBGWBIAR(11)", OutTemp => C405DBGWBIAR_OUT(11), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(12), GlitchData => C405DBGWBIAR12_GlitchData, OutSignalName => "C405DBGWBIAR(12)", OutTemp => C405DBGWBIAR_OUT(12), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(13), GlitchData => C405DBGWBIAR13_GlitchData, OutSignalName => "C405DBGWBIAR(13)", OutTemp => C405DBGWBIAR_OUT(13), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(14), GlitchData => C405DBGWBIAR14_GlitchData, OutSignalName => "C405DBGWBIAR(14)", OutTemp => C405DBGWBIAR_OUT(14), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(15), GlitchData => C405DBGWBIAR15_GlitchData, OutSignalName => "C405DBGWBIAR(15)", OutTemp => C405DBGWBIAR_OUT(15), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(16), GlitchData => C405DBGWBIAR16_GlitchData, OutSignalName => "C405DBGWBIAR(16)", OutTemp => C405DBGWBIAR_OUT(16), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(17), GlitchData => C405DBGWBIAR17_GlitchData, OutSignalName => "C405DBGWBIAR(17)", OutTemp => C405DBGWBIAR_OUT(17), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(18), GlitchData => C405DBGWBIAR18_GlitchData, OutSignalName => "C405DBGWBIAR(18)", OutTemp => C405DBGWBIAR_OUT(18), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(19), GlitchData => C405DBGWBIAR19_GlitchData, OutSignalName => "C405DBGWBIAR(19)", OutTemp => C405DBGWBIAR_OUT(19), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(20), GlitchData => C405DBGWBIAR20_GlitchData, OutSignalName => "C405DBGWBIAR(20)", OutTemp => C405DBGWBIAR_OUT(20), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(21), GlitchData => C405DBGWBIAR21_GlitchData, OutSignalName => "C405DBGWBIAR(21)", OutTemp => C405DBGWBIAR_OUT(21), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(22), GlitchData => C405DBGWBIAR22_GlitchData, OutSignalName => "C405DBGWBIAR(22)", OutTemp => C405DBGWBIAR_OUT(22), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(23), GlitchData => C405DBGWBIAR23_GlitchData, OutSignalName => "C405DBGWBIAR(23)", OutTemp => C405DBGWBIAR_OUT(23), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(24), GlitchData => C405DBGWBIAR24_GlitchData, OutSignalName => "C405DBGWBIAR(24)", OutTemp => C405DBGWBIAR_OUT(24), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(25), GlitchData => C405DBGWBIAR25_GlitchData, OutSignalName => "C405DBGWBIAR(25)", OutTemp => C405DBGWBIAR_OUT(25), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(26), GlitchData => C405DBGWBIAR26_GlitchData, OutSignalName => "C405DBGWBIAR(26)", OutTemp => C405DBGWBIAR_OUT(26), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(27), GlitchData => C405DBGWBIAR27_GlitchData, OutSignalName => "C405DBGWBIAR(27)", OutTemp => C405DBGWBIAR_OUT(27), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(28), GlitchData => C405DBGWBIAR28_GlitchData, OutSignalName => "C405DBGWBIAR(28)", OutTemp => C405DBGWBIAR_OUT(28), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(29), GlitchData => C405DBGWBIAR29_GlitchData, OutSignalName => "C405DBGWBIAR(29)", OutTemp => C405DBGWBIAR_OUT(29), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRABUS(0), GlitchData => C405DCRABUS0_GlitchData, OutSignalName => "C405DCRABUS(0)", OutTemp => C405DCRABUS_OUT(0), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRABUS(1), GlitchData => C405DCRABUS1_GlitchData, OutSignalName => "C405DCRABUS(1)", OutTemp => C405DCRABUS_OUT(1), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRABUS(2), GlitchData => C405DCRABUS2_GlitchData, OutSignalName => "C405DCRABUS(2)", OutTemp => C405DCRABUS_OUT(2), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRABUS(3), GlitchData => C405DCRABUS3_GlitchData, OutSignalName => "C405DCRABUS(3)", OutTemp => C405DCRABUS_OUT(3), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRABUS(4), GlitchData => C405DCRABUS4_GlitchData, OutSignalName => "C405DCRABUS(4)", OutTemp => C405DCRABUS_OUT(4), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRABUS(5), GlitchData => C405DCRABUS5_GlitchData, OutSignalName => "C405DCRABUS(5)", OutTemp => C405DCRABUS_OUT(5), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRABUS(6), GlitchData => C405DCRABUS6_GlitchData, OutSignalName => "C405DCRABUS(6)", OutTemp => C405DCRABUS_OUT(6), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRABUS(7), GlitchData => C405DCRABUS7_GlitchData, OutSignalName => "C405DCRABUS(7)", OutTemp => C405DCRABUS_OUT(7), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRABUS(8), GlitchData => C405DCRABUS8_GlitchData, OutSignalName => "C405DCRABUS(8)", OutTemp => C405DCRABUS_OUT(8), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRABUS(9), GlitchData => C405DCRABUS9_GlitchData, OutSignalName => "C405DCRABUS(9)", OutTemp => C405DCRABUS_OUT(9), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(0), GlitchData => C405DCRDBUSOUT0_GlitchData, OutSignalName => "C405DCRDBUSOUT(0)", OutTemp => C405DCRDBUSOUT_OUT(0), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(1), GlitchData => C405DCRDBUSOUT1_GlitchData, OutSignalName => "C405DCRDBUSOUT(1)", OutTemp => C405DCRDBUSOUT_OUT(1), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(2), GlitchData => C405DCRDBUSOUT2_GlitchData, OutSignalName => "C405DCRDBUSOUT(2)", OutTemp => C405DCRDBUSOUT_OUT(2), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(3), GlitchData => C405DCRDBUSOUT3_GlitchData, OutSignalName => "C405DCRDBUSOUT(3)", OutTemp => C405DCRDBUSOUT_OUT(3), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(4), GlitchData => C405DCRDBUSOUT4_GlitchData, OutSignalName => "C405DCRDBUSOUT(4)", OutTemp => C405DCRDBUSOUT_OUT(4), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(5), GlitchData => C405DCRDBUSOUT5_GlitchData, OutSignalName => "C405DCRDBUSOUT(5)", OutTemp => C405DCRDBUSOUT_OUT(5), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(6), GlitchData => C405DCRDBUSOUT6_GlitchData, OutSignalName => "C405DCRDBUSOUT(6)", OutTemp => C405DCRDBUSOUT_OUT(6), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(7), GlitchData => C405DCRDBUSOUT7_GlitchData, OutSignalName => "C405DCRDBUSOUT(7)", OutTemp => C405DCRDBUSOUT_OUT(7), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(8), GlitchData => C405DCRDBUSOUT8_GlitchData, OutSignalName => "C405DCRDBUSOUT(8)", OutTemp => C405DCRDBUSOUT_OUT(8), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(9), GlitchData => C405DCRDBUSOUT9_GlitchData, OutSignalName => "C405DCRDBUSOUT(9)", OutTemp => C405DCRDBUSOUT_OUT(9), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(10), GlitchData => C405DCRDBUSOUT10_GlitchData, OutSignalName => "C405DCRDBUSOUT(10)", OutTemp => C405DCRDBUSOUT_OUT(10), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(11), GlitchData => C405DCRDBUSOUT11_GlitchData, OutSignalName => "C405DCRDBUSOUT(11)", OutTemp => C405DCRDBUSOUT_OUT(11), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(12), GlitchData => C405DCRDBUSOUT12_GlitchData, OutSignalName => "C405DCRDBUSOUT(12)", OutTemp => C405DCRDBUSOUT_OUT(12), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(13), GlitchData => C405DCRDBUSOUT13_GlitchData, OutSignalName => "C405DCRDBUSOUT(13)", OutTemp => C405DCRDBUSOUT_OUT(13), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(14), GlitchData => C405DCRDBUSOUT14_GlitchData, OutSignalName => "C405DCRDBUSOUT(14)", OutTemp => C405DCRDBUSOUT_OUT(14), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(15), GlitchData => C405DCRDBUSOUT15_GlitchData, OutSignalName => "C405DCRDBUSOUT(15)", OutTemp => C405DCRDBUSOUT_OUT(15), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(16), GlitchData => C405DCRDBUSOUT16_GlitchData, OutSignalName => "C405DCRDBUSOUT(16)", OutTemp => C405DCRDBUSOUT_OUT(16), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(17), GlitchData => C405DCRDBUSOUT17_GlitchData, OutSignalName => "C405DCRDBUSOUT(17)", OutTemp => C405DCRDBUSOUT_OUT(17), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(18), GlitchData => C405DCRDBUSOUT18_GlitchData, OutSignalName => "C405DCRDBUSOUT(18)", OutTemp => C405DCRDBUSOUT_OUT(18), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(19), GlitchData => C405DCRDBUSOUT19_GlitchData, OutSignalName => "C405DCRDBUSOUT(19)", OutTemp => C405DCRDBUSOUT_OUT(19), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(20), GlitchData => C405DCRDBUSOUT20_GlitchData, OutSignalName => "C405DCRDBUSOUT(20)", OutTemp => C405DCRDBUSOUT_OUT(20), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(21), GlitchData => C405DCRDBUSOUT21_GlitchData, OutSignalName => "C405DCRDBUSOUT(21)", OutTemp => C405DCRDBUSOUT_OUT(21), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(22), GlitchData => C405DCRDBUSOUT22_GlitchData, OutSignalName => "C405DCRDBUSOUT(22)", OutTemp => C405DCRDBUSOUT_OUT(22), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(23), GlitchData => C405DCRDBUSOUT23_GlitchData, OutSignalName => "C405DCRDBUSOUT(23)", OutTemp => C405DCRDBUSOUT_OUT(23), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(24), GlitchData => C405DCRDBUSOUT24_GlitchData, OutSignalName => "C405DCRDBUSOUT(24)", OutTemp => C405DCRDBUSOUT_OUT(24), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(25), GlitchData => C405DCRDBUSOUT25_GlitchData, OutSignalName => "C405DCRDBUSOUT(25)", OutTemp => C405DCRDBUSOUT_OUT(25), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(26), GlitchData => C405DCRDBUSOUT26_GlitchData, OutSignalName => "C405DCRDBUSOUT(26)", OutTemp => C405DCRDBUSOUT_OUT(26), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(27), GlitchData => C405DCRDBUSOUT27_GlitchData, OutSignalName => "C405DCRDBUSOUT(27)", OutTemp => C405DCRDBUSOUT_OUT(27), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(28), GlitchData => C405DCRDBUSOUT28_GlitchData, OutSignalName => "C405DCRDBUSOUT(28)", OutTemp => C405DCRDBUSOUT_OUT(28), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(29), GlitchData => C405DCRDBUSOUT29_GlitchData, OutSignalName => "C405DCRDBUSOUT(29)", OutTemp => C405DCRDBUSOUT_OUT(29), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(30), GlitchData => C405DCRDBUSOUT30_GlitchData, OutSignalName => "C405DCRDBUSOUT(30)", OutTemp => C405DCRDBUSOUT_OUT(30), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRDBUSOUT(31), GlitchData => C405DCRDBUSOUT31_GlitchData, OutSignalName => "C405DCRDBUSOUT(31)", OutTemp => C405DCRDBUSOUT_OUT(31), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRREAD, GlitchData => C405DCRREAD_GlitchData, OutSignalName => "C405DCRREAD", OutTemp => C405DCRREAD_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405DCRWRITE, GlitchData => C405DCRWRITE_GlitchData, OutSignalName => "C405DCRWRITE", OutTemp => C405DCRWRITE_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405JTGPGMOUT, GlitchData => C405JTGPGMOUT_GlitchData, OutSignalName => "C405JTGPGMOUT", OutTemp => C405JTGPGMOUT_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405RSTCHIPRESETREQ, GlitchData => C405RSTCHIPRESETREQ_GlitchData, OutSignalName => "C405RSTCHIPRESETREQ", OutTemp => C405RSTCHIPRESETREQ_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405RSTCORERESETREQ, GlitchData => C405RSTCORERESETREQ_GlitchData, OutSignalName => "C405RSTCORERESETREQ", OutTemp => C405RSTCORERESETREQ_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405RSTSYSRESETREQ, GlitchData => C405RSTSYSRESETREQ_GlitchData, OutSignalName => "C405RSTSYSRESETREQ", OutTemp => C405RSTSYSRESETREQ_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCCYCLE, GlitchData => C405TRCCYCLE_GlitchData, OutSignalName => "C405TRCCYCLE", OutTemp => C405TRCCYCLE_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCEVENEXECUTIONSTATUS(0), GlitchData => C405TRCEVENEXECUTIONSTATUS0_GlitchData, OutSignalName => "C405TRCEVENEXECUTIONSTATUS(0)", OutTemp => C405TRCEVENEXECUTIONSTATUS_OUT(0), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCEVENEXECUTIONSTATUS(1), GlitchData => C405TRCEVENEXECUTIONSTATUS1_GlitchData, OutSignalName => "C405TRCEVENEXECUTIONSTATUS(1)", OutTemp => C405TRCEVENEXECUTIONSTATUS_OUT(1), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCODDEXECUTIONSTATUS(0), GlitchData => C405TRCODDEXECUTIONSTATUS0_GlitchData, OutSignalName => "C405TRCODDEXECUTIONSTATUS(0)", OutTemp => C405TRCODDEXECUTIONSTATUS_OUT(0), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCODDEXECUTIONSTATUS(1), GlitchData => C405TRCODDEXECUTIONSTATUS1_GlitchData, OutSignalName => "C405TRCODDEXECUTIONSTATUS(1)", OutTemp => C405TRCODDEXECUTIONSTATUS_OUT(1), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRACESTATUS(0), GlitchData => C405TRCTRACESTATUS0_GlitchData, OutSignalName => "C405TRCTRACESTATUS(0)", OutTemp => C405TRCTRACESTATUS_OUT(0), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRACESTATUS(1), GlitchData => C405TRCTRACESTATUS1_GlitchData, OutSignalName => "C405TRCTRACESTATUS(1)", OutTemp => C405TRCTRACESTATUS_OUT(1), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRACESTATUS(2), GlitchData => C405TRCTRACESTATUS2_GlitchData, OutSignalName => "C405TRCTRACESTATUS(2)", OutTemp => C405TRCTRACESTATUS_OUT(2), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRACESTATUS(3), GlitchData => C405TRCTRACESTATUS3_GlitchData, OutSignalName => "C405TRCTRACESTATUS(3)", OutTemp => C405TRCTRACESTATUS_OUT(3), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTOUT, GlitchData => C405TRCTRIGGEREVENTOUT_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTOUT", OutTemp => C405TRCTRIGGEREVENTOUT_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(0), GlitchData => C405TRCTRIGGEREVENTTYPE0_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(0)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(0), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(1), GlitchData => C405TRCTRIGGEREVENTTYPE1_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(1)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(1), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(2), GlitchData => C405TRCTRIGGEREVENTTYPE2_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(2)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(2), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(3), GlitchData => C405TRCTRIGGEREVENTTYPE3_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(3)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(3), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(4), GlitchData => C405TRCTRIGGEREVENTTYPE4_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(4)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(4), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(5), GlitchData => C405TRCTRIGGEREVENTTYPE5_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(5)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(5), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(6), GlitchData => C405TRCTRIGGEREVENTTYPE6_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(6)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(6), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(7), GlitchData => C405TRCTRIGGEREVENTTYPE7_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(7)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(7), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(8), GlitchData => C405TRCTRIGGEREVENTTYPE8_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(8)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(8), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(9), GlitchData => C405TRCTRIGGEREVENTTYPE9_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(9)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(9), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(10), GlitchData => C405TRCTRIGGEREVENTTYPE10_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(10)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(10), Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405XXXMACHINECHECK, GlitchData => C405XXXMACHINECHECK_GlitchData, OutSignalName => "C405XXXMACHINECHECK", OutTemp => C405XXXMACHINECHECK_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => DSOCMBUSY, GlitchData => DSOCMBUSY_GlitchData, OutSignalName => "DSOCMBUSY", OutTemp => DSOCMBUSY_OUT, Paths => (0 => (cpmc405clock_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405JTGCAPTUREDR, GlitchData => C405JTGCAPTUREDR_GlitchData, OutSignalName => "C405JTGCAPTUREDR", OutTemp => C405JTGCAPTUREDR_OUT, Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405JTGEXTEST, GlitchData => C405JTGEXTEST_GlitchData, OutSignalName => "C405JTGEXTEST", OutTemp => C405JTGEXTEST_OUT, Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405JTGSHIFTDR, GlitchData => C405JTGSHIFTDR_GlitchData, OutSignalName => "C405JTGSHIFTDR", OutTemp => C405JTGSHIFTDR_OUT, Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405JTGTDO, GlitchData => C405JTGTDO_GlitchData, OutSignalName => "C405JTGTDO", OutTemp => C405JTGTDO_OUT, Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405JTGTDOEN, GlitchData => C405JTGTDOEN_GlitchData, OutSignalName => "C405JTGTDOEN", OutTemp => C405JTGTDOEN_OUT, Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405JTGUPDATEDR, GlitchData => C405JTGUPDATEDR_GlitchData, OutSignalName => "C405JTGUPDATEDR", OutTemp => C405JTGUPDATEDR_OUT, Paths => (0 => (jtgc405tck_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABORT, GlitchData => C405PLBDCUABORT_GlitchData, OutSignalName => "C405PLBDCUABORT", OutTemp => C405PLBDCUABORT_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(0), GlitchData => C405PLBDCUABUS0_GlitchData, OutSignalName => "C405PLBDCUABUS(0)", OutTemp => C405PLBDCUABUS_OUT(0), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(1), GlitchData => C405PLBDCUABUS1_GlitchData, OutSignalName => "C405PLBDCUABUS(1)", OutTemp => C405PLBDCUABUS_OUT(1), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(2), GlitchData => C405PLBDCUABUS2_GlitchData, OutSignalName => "C405PLBDCUABUS(2)", OutTemp => C405PLBDCUABUS_OUT(2), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(3), GlitchData => C405PLBDCUABUS3_GlitchData, OutSignalName => "C405PLBDCUABUS(3)", OutTemp => C405PLBDCUABUS_OUT(3), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(4), GlitchData => C405PLBDCUABUS4_GlitchData, OutSignalName => "C405PLBDCUABUS(4)", OutTemp => C405PLBDCUABUS_OUT(4), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(5), GlitchData => C405PLBDCUABUS5_GlitchData, OutSignalName => "C405PLBDCUABUS(5)", OutTemp => C405PLBDCUABUS_OUT(5), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(6), GlitchData => C405PLBDCUABUS6_GlitchData, OutSignalName => "C405PLBDCUABUS(6)", OutTemp => C405PLBDCUABUS_OUT(6), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(7), GlitchData => C405PLBDCUABUS7_GlitchData, OutSignalName => "C405PLBDCUABUS(7)", OutTemp => C405PLBDCUABUS_OUT(7), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(8), GlitchData => C405PLBDCUABUS8_GlitchData, OutSignalName => "C405PLBDCUABUS(8)", OutTemp => C405PLBDCUABUS_OUT(8), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(9), GlitchData => C405PLBDCUABUS9_GlitchData, OutSignalName => "C405PLBDCUABUS(9)", OutTemp => C405PLBDCUABUS_OUT(9), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(10), GlitchData => C405PLBDCUABUS10_GlitchData, OutSignalName => "C405PLBDCUABUS(10)", OutTemp => C405PLBDCUABUS_OUT(10), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(11), GlitchData => C405PLBDCUABUS11_GlitchData, OutSignalName => "C405PLBDCUABUS(11)", OutTemp => C405PLBDCUABUS_OUT(11), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(12), GlitchData => C405PLBDCUABUS12_GlitchData, OutSignalName => "C405PLBDCUABUS(12)", OutTemp => C405PLBDCUABUS_OUT(12), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(13), GlitchData => C405PLBDCUABUS13_GlitchData, OutSignalName => "C405PLBDCUABUS(13)", OutTemp => C405PLBDCUABUS_OUT(13), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(14), GlitchData => C405PLBDCUABUS14_GlitchData, OutSignalName => "C405PLBDCUABUS(14)", OutTemp => C405PLBDCUABUS_OUT(14), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(15), GlitchData => C405PLBDCUABUS15_GlitchData, OutSignalName => "C405PLBDCUABUS(15)", OutTemp => C405PLBDCUABUS_OUT(15), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(16), GlitchData => C405PLBDCUABUS16_GlitchData, OutSignalName => "C405PLBDCUABUS(16)", OutTemp => C405PLBDCUABUS_OUT(16), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(17), GlitchData => C405PLBDCUABUS17_GlitchData, OutSignalName => "C405PLBDCUABUS(17)", OutTemp => C405PLBDCUABUS_OUT(17), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(18), GlitchData => C405PLBDCUABUS18_GlitchData, OutSignalName => "C405PLBDCUABUS(18)", OutTemp => C405PLBDCUABUS_OUT(18), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(19), GlitchData => C405PLBDCUABUS19_GlitchData, OutSignalName => "C405PLBDCUABUS(19)", OutTemp => C405PLBDCUABUS_OUT(19), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(20), GlitchData => C405PLBDCUABUS20_GlitchData, OutSignalName => "C405PLBDCUABUS(20)", OutTemp => C405PLBDCUABUS_OUT(20), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(21), GlitchData => C405PLBDCUABUS21_GlitchData, OutSignalName => "C405PLBDCUABUS(21)", OutTemp => C405PLBDCUABUS_OUT(21), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(22), GlitchData => C405PLBDCUABUS22_GlitchData, OutSignalName => "C405PLBDCUABUS(22)", OutTemp => C405PLBDCUABUS_OUT(22), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(23), GlitchData => C405PLBDCUABUS23_GlitchData, OutSignalName => "C405PLBDCUABUS(23)", OutTemp => C405PLBDCUABUS_OUT(23), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(24), GlitchData => C405PLBDCUABUS24_GlitchData, OutSignalName => "C405PLBDCUABUS(24)", OutTemp => C405PLBDCUABUS_OUT(24), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(25), GlitchData => C405PLBDCUABUS25_GlitchData, OutSignalName => "C405PLBDCUABUS(25)", OutTemp => C405PLBDCUABUS_OUT(25), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(26), GlitchData => C405PLBDCUABUS26_GlitchData, OutSignalName => "C405PLBDCUABUS(26)", OutTemp => C405PLBDCUABUS_OUT(26), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(27), GlitchData => C405PLBDCUABUS27_GlitchData, OutSignalName => "C405PLBDCUABUS(27)", OutTemp => C405PLBDCUABUS_OUT(27), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(28), GlitchData => C405PLBDCUABUS28_GlitchData, OutSignalName => "C405PLBDCUABUS(28)", OutTemp => C405PLBDCUABUS_OUT(28), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(29), GlitchData => C405PLBDCUABUS29_GlitchData, OutSignalName => "C405PLBDCUABUS(29)", OutTemp => C405PLBDCUABUS_OUT(29), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(30), GlitchData => C405PLBDCUABUS30_GlitchData, OutSignalName => "C405PLBDCUABUS(30)", OutTemp => C405PLBDCUABUS_OUT(30), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(31), GlitchData => C405PLBDCUABUS31_GlitchData, OutSignalName => "C405PLBDCUABUS(31)", OutTemp => C405PLBDCUABUS_OUT(31), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(0), GlitchData => C405PLBDCUBE0_GlitchData, OutSignalName => "C405PLBDCUBE(0)", OutTemp => C405PLBDCUBE_OUT(0), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(1), GlitchData => C405PLBDCUBE1_GlitchData, OutSignalName => "C405PLBDCUBE(1)", OutTemp => C405PLBDCUBE_OUT(1), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(2), GlitchData => C405PLBDCUBE2_GlitchData, OutSignalName => "C405PLBDCUBE(2)", OutTemp => C405PLBDCUBE_OUT(2), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(3), GlitchData => C405PLBDCUBE3_GlitchData, OutSignalName => "C405PLBDCUBE(3)", OutTemp => C405PLBDCUBE_OUT(3), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(4), GlitchData => C405PLBDCUBE4_GlitchData, OutSignalName => "C405PLBDCUBE(4)", OutTemp => C405PLBDCUBE_OUT(4), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(5), GlitchData => C405PLBDCUBE5_GlitchData, OutSignalName => "C405PLBDCUBE(5)", OutTemp => C405PLBDCUBE_OUT(5), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(6), GlitchData => C405PLBDCUBE6_GlitchData, OutSignalName => "C405PLBDCUBE(6)", OutTemp => C405PLBDCUBE_OUT(6), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(7), GlitchData => C405PLBDCUBE7_GlitchData, OutSignalName => "C405PLBDCUBE(7)", OutTemp => C405PLBDCUBE_OUT(7), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUCACHEABLE, GlitchData => C405PLBDCUCACHEABLE_GlitchData, OutSignalName => "C405PLBDCUCACHEABLE", OutTemp => C405PLBDCUCACHEABLE_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUGUARDED, GlitchData => C405PLBDCUGUARDED_GlitchData, OutSignalName => "C405PLBDCUGUARDED", OutTemp => C405PLBDCUGUARDED_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUPRIORITY(0), GlitchData => C405PLBDCUPRIORITY0_GlitchData, OutSignalName => "C405PLBDCUPRIORITY(0)", OutTemp => C405PLBDCUPRIORITY_OUT(0), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUPRIORITY(1), GlitchData => C405PLBDCUPRIORITY1_GlitchData, OutSignalName => "C405PLBDCUPRIORITY(1)", OutTemp => C405PLBDCUPRIORITY_OUT(1), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUREQUEST, GlitchData => C405PLBDCUREQUEST_GlitchData, OutSignalName => "C405PLBDCUREQUEST", OutTemp => C405PLBDCUREQUEST_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCURNW, GlitchData => C405PLBDCURNW_GlitchData, OutSignalName => "C405PLBDCURNW", OutTemp => C405PLBDCURNW_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUSIZE2, GlitchData => C405PLBDCUSIZE2_GlitchData, OutSignalName => "C405PLBDCUSIZE2", OutTemp => C405PLBDCUSIZE2_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUU0ATTR, GlitchData => C405PLBDCUU0ATTR_GlitchData, OutSignalName => "C405PLBDCUU0ATTR", OutTemp => C405PLBDCUU0ATTR_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(0), GlitchData => C405PLBDCUWRDBUS0_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(0)", OutTemp => C405PLBDCUWRDBUS_OUT(0), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(1), GlitchData => C405PLBDCUWRDBUS1_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(1)", OutTemp => C405PLBDCUWRDBUS_OUT(1), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(2), GlitchData => C405PLBDCUWRDBUS2_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(2)", OutTemp => C405PLBDCUWRDBUS_OUT(2), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(3), GlitchData => C405PLBDCUWRDBUS3_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(3)", OutTemp => C405PLBDCUWRDBUS_OUT(3), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(4), GlitchData => C405PLBDCUWRDBUS4_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(4)", OutTemp => C405PLBDCUWRDBUS_OUT(4), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(5), GlitchData => C405PLBDCUWRDBUS5_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(5)", OutTemp => C405PLBDCUWRDBUS_OUT(5), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(6), GlitchData => C405PLBDCUWRDBUS6_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(6)", OutTemp => C405PLBDCUWRDBUS_OUT(6), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(7), GlitchData => C405PLBDCUWRDBUS7_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(7)", OutTemp => C405PLBDCUWRDBUS_OUT(7), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(8), GlitchData => C405PLBDCUWRDBUS8_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(8)", OutTemp => C405PLBDCUWRDBUS_OUT(8), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(9), GlitchData => C405PLBDCUWRDBUS9_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(9)", OutTemp => C405PLBDCUWRDBUS_OUT(9), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(10), GlitchData => C405PLBDCUWRDBUS10_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(10)", OutTemp => C405PLBDCUWRDBUS_OUT(10), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(11), GlitchData => C405PLBDCUWRDBUS11_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(11)", OutTemp => C405PLBDCUWRDBUS_OUT(11), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(12), GlitchData => C405PLBDCUWRDBUS12_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(12)", OutTemp => C405PLBDCUWRDBUS_OUT(12), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(13), GlitchData => C405PLBDCUWRDBUS13_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(13)", OutTemp => C405PLBDCUWRDBUS_OUT(13), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(14), GlitchData => C405PLBDCUWRDBUS14_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(14)", OutTemp => C405PLBDCUWRDBUS_OUT(14), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(15), GlitchData => C405PLBDCUWRDBUS15_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(15)", OutTemp => C405PLBDCUWRDBUS_OUT(15), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(16), GlitchData => C405PLBDCUWRDBUS16_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(16)", OutTemp => C405PLBDCUWRDBUS_OUT(16), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(17), GlitchData => C405PLBDCUWRDBUS17_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(17)", OutTemp => C405PLBDCUWRDBUS_OUT(17), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(18), GlitchData => C405PLBDCUWRDBUS18_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(18)", OutTemp => C405PLBDCUWRDBUS_OUT(18), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(19), GlitchData => C405PLBDCUWRDBUS19_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(19)", OutTemp => C405PLBDCUWRDBUS_OUT(19), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(20), GlitchData => C405PLBDCUWRDBUS20_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(20)", OutTemp => C405PLBDCUWRDBUS_OUT(20), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(21), GlitchData => C405PLBDCUWRDBUS21_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(21)", OutTemp => C405PLBDCUWRDBUS_OUT(21), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(22), GlitchData => C405PLBDCUWRDBUS22_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(22)", OutTemp => C405PLBDCUWRDBUS_OUT(22), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(23), GlitchData => C405PLBDCUWRDBUS23_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(23)", OutTemp => C405PLBDCUWRDBUS_OUT(23), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(24), GlitchData => C405PLBDCUWRDBUS24_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(24)", OutTemp => C405PLBDCUWRDBUS_OUT(24), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(25), GlitchData => C405PLBDCUWRDBUS25_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(25)", OutTemp => C405PLBDCUWRDBUS_OUT(25), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(26), GlitchData => C405PLBDCUWRDBUS26_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(26)", OutTemp => C405PLBDCUWRDBUS_OUT(26), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(27), GlitchData => C405PLBDCUWRDBUS27_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(27)", OutTemp => C405PLBDCUWRDBUS_OUT(27), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(28), GlitchData => C405PLBDCUWRDBUS28_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(28)", OutTemp => C405PLBDCUWRDBUS_OUT(28), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(29), GlitchData => C405PLBDCUWRDBUS29_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(29)", OutTemp => C405PLBDCUWRDBUS_OUT(29), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(30), GlitchData => C405PLBDCUWRDBUS30_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(30)", OutTemp => C405PLBDCUWRDBUS_OUT(30), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(31), GlitchData => C405PLBDCUWRDBUS31_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(31)", OutTemp => C405PLBDCUWRDBUS_OUT(31), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(32), GlitchData => C405PLBDCUWRDBUS32_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(32)", OutTemp => C405PLBDCUWRDBUS_OUT(32), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(33), GlitchData => C405PLBDCUWRDBUS33_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(33)", OutTemp => C405PLBDCUWRDBUS_OUT(33), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(34), GlitchData => C405PLBDCUWRDBUS34_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(34)", OutTemp => C405PLBDCUWRDBUS_OUT(34), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(35), GlitchData => C405PLBDCUWRDBUS35_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(35)", OutTemp => C405PLBDCUWRDBUS_OUT(35), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(36), GlitchData => C405PLBDCUWRDBUS36_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(36)", OutTemp => C405PLBDCUWRDBUS_OUT(36), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(37), GlitchData => C405PLBDCUWRDBUS37_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(37)", OutTemp => C405PLBDCUWRDBUS_OUT(37), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(38), GlitchData => C405PLBDCUWRDBUS38_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(38)", OutTemp => C405PLBDCUWRDBUS_OUT(38), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(39), GlitchData => C405PLBDCUWRDBUS39_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(39)", OutTemp => C405PLBDCUWRDBUS_OUT(39), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(40), GlitchData => C405PLBDCUWRDBUS40_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(40)", OutTemp => C405PLBDCUWRDBUS_OUT(40), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(41), GlitchData => C405PLBDCUWRDBUS41_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(41)", OutTemp => C405PLBDCUWRDBUS_OUT(41), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(42), GlitchData => C405PLBDCUWRDBUS42_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(42)", OutTemp => C405PLBDCUWRDBUS_OUT(42), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(43), GlitchData => C405PLBDCUWRDBUS43_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(43)", OutTemp => C405PLBDCUWRDBUS_OUT(43), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(44), GlitchData => C405PLBDCUWRDBUS44_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(44)", OutTemp => C405PLBDCUWRDBUS_OUT(44), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(45), GlitchData => C405PLBDCUWRDBUS45_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(45)", OutTemp => C405PLBDCUWRDBUS_OUT(45), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(46), GlitchData => C405PLBDCUWRDBUS46_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(46)", OutTemp => C405PLBDCUWRDBUS_OUT(46), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(47), GlitchData => C405PLBDCUWRDBUS47_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(47)", OutTemp => C405PLBDCUWRDBUS_OUT(47), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(48), GlitchData => C405PLBDCUWRDBUS48_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(48)", OutTemp => C405PLBDCUWRDBUS_OUT(48), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(49), GlitchData => C405PLBDCUWRDBUS49_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(49)", OutTemp => C405PLBDCUWRDBUS_OUT(49), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(50), GlitchData => C405PLBDCUWRDBUS50_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(50)", OutTemp => C405PLBDCUWRDBUS_OUT(50), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(51), GlitchData => C405PLBDCUWRDBUS51_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(51)", OutTemp => C405PLBDCUWRDBUS_OUT(51), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(52), GlitchData => C405PLBDCUWRDBUS52_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(52)", OutTemp => C405PLBDCUWRDBUS_OUT(52), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(53), GlitchData => C405PLBDCUWRDBUS53_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(53)", OutTemp => C405PLBDCUWRDBUS_OUT(53), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(54), GlitchData => C405PLBDCUWRDBUS54_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(54)", OutTemp => C405PLBDCUWRDBUS_OUT(54), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(55), GlitchData => C405PLBDCUWRDBUS55_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(55)", OutTemp => C405PLBDCUWRDBUS_OUT(55), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(56), GlitchData => C405PLBDCUWRDBUS56_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(56)", OutTemp => C405PLBDCUWRDBUS_OUT(56), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(57), GlitchData => C405PLBDCUWRDBUS57_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(57)", OutTemp => C405PLBDCUWRDBUS_OUT(57), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(58), GlitchData => C405PLBDCUWRDBUS58_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(58)", OutTemp => C405PLBDCUWRDBUS_OUT(58), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(59), GlitchData => C405PLBDCUWRDBUS59_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(59)", OutTemp => C405PLBDCUWRDBUS_OUT(59), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(60), GlitchData => C405PLBDCUWRDBUS60_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(60)", OutTemp => C405PLBDCUWRDBUS_OUT(60), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(61), GlitchData => C405PLBDCUWRDBUS61_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(61)", OutTemp => C405PLBDCUWRDBUS_OUT(61), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(62), GlitchData => C405PLBDCUWRDBUS62_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(62)", OutTemp => C405PLBDCUWRDBUS_OUT(62), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(63), GlitchData => C405PLBDCUWRDBUS63_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(63)", OutTemp => C405PLBDCUWRDBUS_OUT(63), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBDCUWRITETHRU, GlitchData => C405PLBDCUWRITETHRU_GlitchData, OutSignalName => "C405PLBDCUWRITETHRU", OutTemp => C405PLBDCUWRITETHRU_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABORT, GlitchData => C405PLBICUABORT_GlitchData, OutSignalName => "C405PLBICUABORT", OutTemp => C405PLBICUABORT_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(0), GlitchData => C405PLBICUABUS0_GlitchData, OutSignalName => "C405PLBICUABUS(0)", OutTemp => C405PLBICUABUS_OUT(0), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(1), GlitchData => C405PLBICUABUS1_GlitchData, OutSignalName => "C405PLBICUABUS(1)", OutTemp => C405PLBICUABUS_OUT(1), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(2), GlitchData => C405PLBICUABUS2_GlitchData, OutSignalName => "C405PLBICUABUS(2)", OutTemp => C405PLBICUABUS_OUT(2), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(3), GlitchData => C405PLBICUABUS3_GlitchData, OutSignalName => "C405PLBICUABUS(3)", OutTemp => C405PLBICUABUS_OUT(3), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(4), GlitchData => C405PLBICUABUS4_GlitchData, OutSignalName => "C405PLBICUABUS(4)", OutTemp => C405PLBICUABUS_OUT(4), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(5), GlitchData => C405PLBICUABUS5_GlitchData, OutSignalName => "C405PLBICUABUS(5)", OutTemp => C405PLBICUABUS_OUT(5), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(6), GlitchData => C405PLBICUABUS6_GlitchData, OutSignalName => "C405PLBICUABUS(6)", OutTemp => C405PLBICUABUS_OUT(6), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(7), GlitchData => C405PLBICUABUS7_GlitchData, OutSignalName => "C405PLBICUABUS(7)", OutTemp => C405PLBICUABUS_OUT(7), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(8), GlitchData => C405PLBICUABUS8_GlitchData, OutSignalName => "C405PLBICUABUS(8)", OutTemp => C405PLBICUABUS_OUT(8), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(9), GlitchData => C405PLBICUABUS9_GlitchData, OutSignalName => "C405PLBICUABUS(9)", OutTemp => C405PLBICUABUS_OUT(9), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(10), GlitchData => C405PLBICUABUS10_GlitchData, OutSignalName => "C405PLBICUABUS(10)", OutTemp => C405PLBICUABUS_OUT(10), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(11), GlitchData => C405PLBICUABUS11_GlitchData, OutSignalName => "C405PLBICUABUS(11)", OutTemp => C405PLBICUABUS_OUT(11), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(12), GlitchData => C405PLBICUABUS12_GlitchData, OutSignalName => "C405PLBICUABUS(12)", OutTemp => C405PLBICUABUS_OUT(12), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(13), GlitchData => C405PLBICUABUS13_GlitchData, OutSignalName => "C405PLBICUABUS(13)", OutTemp => C405PLBICUABUS_OUT(13), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(14), GlitchData => C405PLBICUABUS14_GlitchData, OutSignalName => "C405PLBICUABUS(14)", OutTemp => C405PLBICUABUS_OUT(14), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(15), GlitchData => C405PLBICUABUS15_GlitchData, OutSignalName => "C405PLBICUABUS(15)", OutTemp => C405PLBICUABUS_OUT(15), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(16), GlitchData => C405PLBICUABUS16_GlitchData, OutSignalName => "C405PLBICUABUS(16)", OutTemp => C405PLBICUABUS_OUT(16), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(17), GlitchData => C405PLBICUABUS17_GlitchData, OutSignalName => "C405PLBICUABUS(17)", OutTemp => C405PLBICUABUS_OUT(17), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(18), GlitchData => C405PLBICUABUS18_GlitchData, OutSignalName => "C405PLBICUABUS(18)", OutTemp => C405PLBICUABUS_OUT(18), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(19), GlitchData => C405PLBICUABUS19_GlitchData, OutSignalName => "C405PLBICUABUS(19)", OutTemp => C405PLBICUABUS_OUT(19), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(20), GlitchData => C405PLBICUABUS20_GlitchData, OutSignalName => "C405PLBICUABUS(20)", OutTemp => C405PLBICUABUS_OUT(20), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(21), GlitchData => C405PLBICUABUS21_GlitchData, OutSignalName => "C405PLBICUABUS(21)", OutTemp => C405PLBICUABUS_OUT(21), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(22), GlitchData => C405PLBICUABUS22_GlitchData, OutSignalName => "C405PLBICUABUS(22)", OutTemp => C405PLBICUABUS_OUT(22), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(23), GlitchData => C405PLBICUABUS23_GlitchData, OutSignalName => "C405PLBICUABUS(23)", OutTemp => C405PLBICUABUS_OUT(23), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(24), GlitchData => C405PLBICUABUS24_GlitchData, OutSignalName => "C405PLBICUABUS(24)", OutTemp => C405PLBICUABUS_OUT(24), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(25), GlitchData => C405PLBICUABUS25_GlitchData, OutSignalName => "C405PLBICUABUS(25)", OutTemp => C405PLBICUABUS_OUT(25), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(26), GlitchData => C405PLBICUABUS26_GlitchData, OutSignalName => "C405PLBICUABUS(26)", OutTemp => C405PLBICUABUS_OUT(26), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(27), GlitchData => C405PLBICUABUS27_GlitchData, OutSignalName => "C405PLBICUABUS(27)", OutTemp => C405PLBICUABUS_OUT(27), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(28), GlitchData => C405PLBICUABUS28_GlitchData, OutSignalName => "C405PLBICUABUS(28)", OutTemp => C405PLBICUABUS_OUT(28), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(29), GlitchData => C405PLBICUABUS29_GlitchData, OutSignalName => "C405PLBICUABUS(29)", OutTemp => C405PLBICUABUS_OUT(29), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUCACHEABLE, GlitchData => C405PLBICUCACHEABLE_GlitchData, OutSignalName => "C405PLBICUCACHEABLE", OutTemp => C405PLBICUCACHEABLE_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUPRIORITY(0), GlitchData => C405PLBICUPRIORITY0_GlitchData, OutSignalName => "C405PLBICUPRIORITY(0)", OutTemp => C405PLBICUPRIORITY_OUT(0), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUPRIORITY(1), GlitchData => C405PLBICUPRIORITY1_GlitchData, OutSignalName => "C405PLBICUPRIORITY(1)", OutTemp => C405PLBICUPRIORITY_OUT(1), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUREQUEST, GlitchData => C405PLBICUREQUEST_GlitchData, OutSignalName => "C405PLBICUREQUEST", OutTemp => C405PLBICUREQUEST_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUSIZE(2), GlitchData => C405PLBICUSIZE2_GlitchData, OutSignalName => "C405PLBICUSIZE(2)", OutTemp => C405PLBICUSIZE_OUT(2), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUSIZE(3), GlitchData => C405PLBICUSIZE3_GlitchData, OutSignalName => "C405PLBICUSIZE(3)", OutTemp => C405PLBICUSIZE_OUT(3), Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); VitalPathDelay01 ( OutSignal => C405PLBICUU0ATTR, GlitchData => C405PLBICUU0ATTR_GlitchData, OutSignalName => "C405PLBICUU0ATTR", OutTemp => C405PLBICUU0ATTR_OUT, Paths => (0 => (plbclk_ipd'last_event, out_delay, TRUE)), Mode => VitalTransport, Xon => False, MsgOn => False, MsgSeverity => WARNING); wait on BRAMDSOCMCLK_ipd , BRAMDSOCMRDDBUS_ipd , BRAMISOCMCLK_ipd , BRAMISOCMRDDBUS_ipd , CPMC405CLOCK_ipd , CPMC405CORECLKINACTIVE_ipd , CPMC405CPUCLKEN_ipd , CPMC405JTAGCLKEN_ipd , CPMC405TIMERCLKEN_ipd , CPMC405TIMERTICK_ipd , DBGC405DEBUGHALT_ipd , DBGC405EXTBUSHOLDACK_ipd , DBGC405UNCONDDEBUGEVENT_ipd , DCRC405ACK_ipd , DCRC405DBUSIN_ipd , DSARCVALUE_ipd , DSCNTLVALUE_ipd , EICC405CRITINPUTIRQ_ipd , EICC405EXTINPUTIRQ_ipd , ISARCVALUE_ipd , ISCNTLVALUE_ipd , JTGC405BNDSCANTDO_ipd , JTGC405TCK_ipd , JTGC405TDI_ipd , JTGC405TMS_ipd , JTGC405TRSTNEG_ipd , MCBCPUCLKEN_ipd , MCBJTAGEN_ipd , MCBTIMEREN_ipd , MCPPCRST_ipd , PLBC405DCUADDRACK_ipd , PLBC405DCUBUSY_ipd , PLBC405DCUERR_ipd , PLBC405DCURDDACK_ipd , PLBC405DCURDDBUS_ipd , PLBC405DCURDWDADDR_ipd , PLBC405DCUSSIZE1_ipd , PLBC405DCUWRDACK_ipd , PLBC405ICUADDRACK_ipd , PLBC405ICUBUSY_ipd , PLBC405ICUERR_ipd , PLBC405ICURDDACK_ipd , PLBC405ICURDDBUS_ipd , PLBC405ICURDWDADDR_ipd , PLBC405ICUSSIZE1_ipd , PLBCLK_ipd , RSTC405RESETCHIP_ipd , RSTC405RESETCORE_ipd , RSTC405RESETSYS_ipd , TIEC405DETERMINISTICMULT_ipd , TIEC405DISOPERANDFWD_ipd , TIEC405MMUEN_ipd , TIEDSOCMDCRADDR_ipd , TIEISOCMDCRADDR_ipd , TRCC405TRACEDISABLE_ipd , TRCC405TRIGGEREVENTIN_ipd , C405CPMCORESLEEPREQ_OUT , C405CPMMSRCE_OUT , C405CPMMSREE_OUT , C405CPMTIMERIRQ_OUT , C405CPMTIMERRESETREQ_OUT , C405DBGMSRWE_OUT , C405DBGSTOPACK_OUT , C405DBGWBCOMPLETE_OUT , C405DBGWBFULL_OUT , C405DBGWBIAR_OUT , C405DCRABUS_OUT , C405DCRDBUSOUT_OUT , C405DCRREAD_OUT , C405DCRWRITE_OUT , C405JTGCAPTUREDR_OUT , C405JTGEXTEST_OUT , C405JTGPGMOUT_OUT , C405JTGSHIFTDR_OUT , C405JTGTDO_OUT , C405JTGTDOEN_OUT , C405JTGUPDATEDR_OUT , C405PLBDCUABORT_OUT , C405PLBDCUABUS_OUT , C405PLBDCUBE_OUT , C405PLBDCUCACHEABLE_OUT , C405PLBDCUGUARDED_OUT , C405PLBDCUPRIORITY_OUT , C405PLBDCUREQUEST_OUT , C405PLBDCURNW_OUT , C405PLBDCUSIZE2_OUT , C405PLBDCUU0ATTR_OUT , C405PLBDCUWRDBUS_OUT , C405PLBDCUWRITETHRU_OUT , C405PLBICUABORT_OUT , C405PLBICUABUS_OUT , C405PLBICUCACHEABLE_OUT , C405PLBICUPRIORITY_OUT , C405PLBICUREQUEST_OUT , C405PLBICUSIZE_OUT , C405PLBICUU0ATTR_OUT , C405RSTCHIPRESETREQ_OUT , C405RSTCORERESETREQ_OUT , C405RSTSYSRESETREQ_OUT , C405TRCCYCLE_OUT , C405TRCEVENEXECUTIONSTATUS_OUT , C405TRCODDEXECUTIONSTATUS_OUT , C405TRCTRACESTATUS_OUT , C405TRCTRIGGEREVENTOUT_OUT , C405TRCTRIGGEREVENTTYPE_OUT , C405XXXMACHINECHECK_OUT , DSOCMBRAMABUS_OUT , DSOCMBRAMBYTEWRITE_OUT , DSOCMBRAMEN_OUT , DSOCMBRAMWRDBUS_OUT , DSOCMBUSY_OUT , ISOCMBRAMEN_OUT , ISOCMBRAMEVENWRITEEN_OUT , ISOCMBRAMODDWRITEEN_OUT , ISOCMBRAMRDABUS_OUT , ISOCMBRAMWRABUS_OUT , ISOCMBRAMWRDBUS_OUT ; end process TIMING; end PPC405_v; ----- CELL EMAC ----- ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Ethernet Media Access Controller -- /___/ /\ Filename : EMAC.vhd -- \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. -- 10/04/05 - Fixed CR#217767. Fixed connectivity for three output ports EMACDCRACK, EMACDCRDBUS and DCRHOSTDONEIR -- 12/07/07 - Fixed CR#455025. Added delays for 16 bit client mode -- 02/04/08 - Fixed CR#460680. Changed delay to 125ps -- End Revision library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; entity EMAC is generic ( IN_DELAY : time := 0 ps; OUT_DELAY : VitalDelayType01 := (100 ps, 100 ps) -- clk-to-output path delays ); port ( DCRHOSTDONEIR : out std_ulogic; EMAC0CLIENTANINTERRUPT : out std_ulogic; EMAC0CLIENTRXBADFRAME : out std_ulogic; EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); EMAC0CLIENTRXDVLD : out std_ulogic; EMAC0CLIENTRXDVLDMSW : out std_ulogic; EMAC0CLIENTRXDVREG6 : out std_ulogic; EMAC0CLIENTRXFRAMEDROP : out std_ulogic; EMAC0CLIENTRXGOODFRAME : out std_ulogic; EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; EMAC0CLIENTRXSTATSVLD : out std_ulogic; EMAC0CLIENTTXACK : out std_ulogic; EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; EMAC0CLIENTTXCOLLISION : out std_ulogic; EMAC0CLIENTTXGMIIMIICLKOUT : out std_ulogic; EMAC0CLIENTTXRETRANSMIT : out std_ulogic; EMAC0CLIENTTXSTATS : out std_ulogic; EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; EMAC0CLIENTTXSTATSVLD : out std_ulogic; EMAC0PHYENCOMMAALIGN : out std_ulogic; EMAC0PHYLOOPBACKMSB : out std_ulogic; EMAC0PHYMCLKOUT : out std_ulogic; EMAC0PHYMDOUT : out std_ulogic; EMAC0PHYMDTRI : out std_ulogic; EMAC0PHYMGTRXRESET : out std_ulogic; EMAC0PHYMGTTXRESET : out std_ulogic; EMAC0PHYPOWERDOWN : out std_ulogic; EMAC0PHYSYNCACQSTATUS : out std_ulogic; EMAC0PHYTXCHARDISPMODE : out std_ulogic; EMAC0PHYTXCHARDISPVAL : out std_ulogic; EMAC0PHYTXCHARISK : out std_ulogic; EMAC0PHYTXCLK : out std_ulogic; EMAC0PHYTXD : out std_logic_vector(7 downto 0); EMAC0PHYTXEN : out std_ulogic; EMAC0PHYTXER : out std_ulogic; EMAC1CLIENTANINTERRUPT : out std_ulogic; EMAC1CLIENTRXBADFRAME : out std_ulogic; EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); EMAC1CLIENTRXDVLD : out std_ulogic; EMAC1CLIENTRXDVLDMSW : out std_ulogic; EMAC1CLIENTRXDVREG6 : out std_ulogic; EMAC1CLIENTRXFRAMEDROP : out std_ulogic; EMAC1CLIENTRXGOODFRAME : out std_ulogic; EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; EMAC1CLIENTRXSTATSVLD : out std_ulogic; EMAC1CLIENTTXACK : out std_ulogic; EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; EMAC1CLIENTTXCOLLISION : out std_ulogic; EMAC1CLIENTTXGMIIMIICLKOUT : out std_ulogic; EMAC1CLIENTTXRETRANSMIT : out std_ulogic; EMAC1CLIENTTXSTATS : out std_ulogic; EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; EMAC1CLIENTTXSTATSVLD : out std_ulogic; EMAC1PHYENCOMMAALIGN : out std_ulogic; EMAC1PHYLOOPBACKMSB : out std_ulogic; EMAC1PHYMCLKOUT : out std_ulogic; EMAC1PHYMDOUT : out std_ulogic; EMAC1PHYMDTRI : out std_ulogic; EMAC1PHYMGTRXRESET : out std_ulogic; EMAC1PHYMGTTXRESET : out std_ulogic; EMAC1PHYPOWERDOWN : out std_ulogic; EMAC1PHYSYNCACQSTATUS : out std_ulogic; EMAC1PHYTXCHARDISPMODE : out std_ulogic; EMAC1PHYTXCHARDISPVAL : out std_ulogic; EMAC1PHYTXCHARISK : out std_ulogic; EMAC1PHYTXCLK : out std_ulogic; EMAC1PHYTXD : out std_logic_vector(7 downto 0); EMAC1PHYTXEN : out std_ulogic; EMAC1PHYTXER : out std_ulogic; EMACDCRACK : out std_ulogic; EMACDCRDBUS : out std_logic_vector(0 to 31); HOSTMIIMRDY : out std_ulogic; HOSTRDDATA : out std_logic_vector(31 downto 0); CLIENTEMAC0DCMLOCKED : in std_ulogic; CLIENTEMAC0PAUSEREQ : in std_ulogic; CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); CLIENTEMAC0TXDVLD : in std_ulogic; CLIENTEMAC0TXDVLDMSW : in std_ulogic; CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; CLIENTEMAC0TXGMIIMIICLKIN : in std_ulogic; CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); CLIENTEMAC0TXUNDERRUN : in std_ulogic; CLIENTEMAC1DCMLOCKED : in std_ulogic; CLIENTEMAC1PAUSEREQ : in std_ulogic; CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); CLIENTEMAC1TXDVLD : in std_ulogic; CLIENTEMAC1TXDVLDMSW : in std_ulogic; CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; CLIENTEMAC1TXGMIIMIICLKIN : in std_ulogic; CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); CLIENTEMAC1TXUNDERRUN : in std_ulogic; DCREMACABUS : in std_logic_vector(8 to 9); DCREMACCLK : in std_ulogic; DCREMACDBUS : in std_logic_vector(0 to 31); DCREMACENABLE : in std_ulogic; DCREMACREAD : in std_ulogic; DCREMACWRITE : in std_ulogic; HOSTADDR : in std_logic_vector(9 downto 0); HOSTCLK : in std_ulogic; HOSTEMAC1SEL : in std_ulogic; HOSTMIIMSEL : in std_ulogic; HOSTOPCODE : in std_logic_vector(1 downto 0); HOSTREQ : in std_ulogic; HOSTWRDATA : in std_logic_vector(31 downto 0); PHYEMAC0COL : in std_ulogic; PHYEMAC0CRS : in std_ulogic; PHYEMAC0GTXCLK : in std_ulogic; PHYEMAC0MCLKIN : in std_ulogic; PHYEMAC0MDIN : in std_ulogic; PHYEMAC0MIITXCLK : in std_ulogic; PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); PHYEMAC0RXBUFERR : in std_ulogic; PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); PHYEMAC0RXCHARISCOMMA : in std_ulogic; PHYEMAC0RXCHARISK : in std_ulogic; PHYEMAC0RXCHECKINGCRC : in std_ulogic; PHYEMAC0RXCLK : in std_ulogic; PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); PHYEMAC0RXCOMMADET : in std_ulogic; PHYEMAC0RXD : in std_logic_vector(7 downto 0); PHYEMAC0RXDISPERR : in std_ulogic; PHYEMAC0RXDV : in std_ulogic; PHYEMAC0RXER : in std_ulogic; PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); PHYEMAC0RXNOTINTABLE : in std_ulogic; PHYEMAC0RXRUNDISP : in std_ulogic; PHYEMAC0SIGNALDET : in std_ulogic; PHYEMAC0TXBUFERR : in std_ulogic; PHYEMAC1COL : in std_ulogic; PHYEMAC1CRS : in std_ulogic; PHYEMAC1GTXCLK : in std_ulogic; PHYEMAC1MCLKIN : in std_ulogic; PHYEMAC1MDIN : in std_ulogic; PHYEMAC1MIITXCLK : in std_ulogic; PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); PHYEMAC1RXBUFERR : in std_ulogic; PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); PHYEMAC1RXCHARISCOMMA : in std_ulogic; PHYEMAC1RXCHARISK : in std_ulogic; PHYEMAC1RXCHECKINGCRC : in std_ulogic; PHYEMAC1RXCLK : in std_ulogic; PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); PHYEMAC1RXCOMMADET : in std_ulogic; PHYEMAC1RXD : in std_logic_vector(7 downto 0); PHYEMAC1RXDISPERR : in std_ulogic; PHYEMAC1RXDV : in std_ulogic; PHYEMAC1RXER : in std_ulogic; PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); PHYEMAC1RXNOTINTABLE : in std_ulogic; PHYEMAC1RXRUNDISP : in std_ulogic; PHYEMAC1SIGNALDET : in std_ulogic; PHYEMAC1TXBUFERR : in std_ulogic; RESET : in std_ulogic; TIEEMAC0CONFIGVEC : in std_logic_vector(79 downto 0); TIEEMAC0UNICASTADDR : in std_logic_vector(47 downto 0); TIEEMAC1CONFIGVEC : in std_logic_vector(79 downto 0); TIEEMAC1UNICASTADDR : in std_logic_vector(47 downto 0) ); end EMAC; -- Architecture body -- architecture EMAC_V of EMAC is component EMAC_SWIFT_BUS port ( DCRHOSTDONEIR : out std_ulogic; EMAC0CLIENTANINTERRUPT : out std_ulogic; EMAC0CLIENTRXBADFRAME : out std_ulogic; EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); EMAC0CLIENTRXDVLD : out std_ulogic; EMAC0CLIENTRXDVLDMSW : out std_ulogic; EMAC0CLIENTRXDVREG6 : out std_ulogic; EMAC0CLIENTRXFRAMEDROP : out std_ulogic; EMAC0CLIENTRXGOODFRAME : out std_ulogic; EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; EMAC0CLIENTRXSTATSVLD : out std_ulogic; EMAC0CLIENTTXACK : out std_ulogic; EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; EMAC0CLIENTTXCOLLISION : out std_ulogic; EMAC0CLIENTTXGMIIMIICLKOUT : out std_ulogic; EMAC0CLIENTTXRETRANSMIT : out std_ulogic; EMAC0CLIENTTXSTATS : out std_ulogic; EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; EMAC0CLIENTTXSTATSVLD : out std_ulogic; EMAC0PHYENCOMMAALIGN : out std_ulogic; EMAC0PHYLOOPBACKMSB : out std_ulogic; EMAC0PHYMCLKOUT : out std_ulogic; EMAC0PHYMDOUT : out std_ulogic; EMAC0PHYMDTRI : out std_ulogic; EMAC0PHYMGTRXRESET : out std_ulogic; EMAC0PHYMGTTXRESET : out std_ulogic; EMAC0PHYPOWERDOWN : out std_ulogic; EMAC0PHYSYNCACQSTATUS : out std_ulogic; EMAC0PHYTXCHARDISPMODE : out std_ulogic; EMAC0PHYTXCHARDISPVAL : out std_ulogic; EMAC0PHYTXCHARISK : out std_ulogic; EMAC0PHYTXCLK : out std_ulogic; EMAC0PHYTXD : out std_logic_vector(7 downto 0); EMAC0PHYTXEN : out std_ulogic; EMAC0PHYTXER : out std_ulogic; EMAC1CLIENTANINTERRUPT : out std_ulogic; EMAC1CLIENTRXBADFRAME : out std_ulogic; EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); EMAC1CLIENTRXDVLD : out std_ulogic; EMAC1CLIENTRXDVLDMSW : out std_ulogic; EMAC1CLIENTRXDVREG6 : out std_ulogic; EMAC1CLIENTRXFRAMEDROP : out std_ulogic; EMAC1CLIENTRXGOODFRAME : out std_ulogic; EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; EMAC1CLIENTRXSTATSVLD : out std_ulogic; EMAC1CLIENTTXACK : out std_ulogic; EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; EMAC1CLIENTTXCOLLISION : out std_ulogic; EMAC1CLIENTTXGMIIMIICLKOUT : out std_ulogic; EMAC1CLIENTTXRETRANSMIT : out std_ulogic; EMAC1CLIENTTXSTATS : out std_ulogic; EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; EMAC1CLIENTTXSTATSVLD : out std_ulogic; EMAC1PHYENCOMMAALIGN : out std_ulogic; EMAC1PHYLOOPBACKMSB : out std_ulogic; EMAC1PHYMCLKOUT : out std_ulogic; EMAC1PHYMDOUT : out std_ulogic; EMAC1PHYMDTRI : out std_ulogic; EMAC1PHYMGTRXRESET : out std_ulogic; EMAC1PHYMGTTXRESET : out std_ulogic; EMAC1PHYPOWERDOWN : out std_ulogic; EMAC1PHYSYNCACQSTATUS : out std_ulogic; EMAC1PHYTXCHARDISPMODE : out std_ulogic; EMAC1PHYTXCHARDISPVAL : out std_ulogic; EMAC1PHYTXCHARISK : out std_ulogic; EMAC1PHYTXCLK : out std_ulogic; EMAC1PHYTXD : out std_logic_vector(7 downto 0); EMAC1PHYTXEN : out std_ulogic; EMAC1PHYTXER : out std_ulogic; EMACDCRACK : out std_ulogic; EMACDCRDBUS : out std_logic_vector(0 to 31); HOSTMIIMRDY : out std_ulogic; HOSTRDDATA : out std_logic_vector(31 downto 0); CLIENTEMAC0DCMLOCKED : in std_ulogic; CLIENTEMAC0PAUSEREQ : in std_ulogic; CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); CLIENTEMAC0TXDVLD : in std_ulogic; CLIENTEMAC0TXDVLDMSW : in std_ulogic; CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; CLIENTEMAC0TXGMIIMIICLKIN : in std_ulogic; CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); CLIENTEMAC0TXUNDERRUN : in std_ulogic; CLIENTEMAC1DCMLOCKED : in std_ulogic; CLIENTEMAC1PAUSEREQ : in std_ulogic; CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); CLIENTEMAC1TXDVLD : in std_ulogic; CLIENTEMAC1TXDVLDMSW : in std_ulogic; CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; CLIENTEMAC1TXGMIIMIICLKIN : in std_ulogic; CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); CLIENTEMAC1TXUNDERRUN : in std_ulogic; DCREMACABUS : in std_logic_vector(8 to 9); DCREMACCLK : in std_ulogic; DCREMACDBUS : in std_logic_vector(0 to 31); DCREMACENABLE : in std_ulogic; DCREMACREAD : in std_ulogic; DCREMACWRITE : in std_ulogic; HOSTADDR : in std_logic_vector(9 downto 0); HOSTCLK : in std_ulogic; HOSTEMAC1SEL : in std_ulogic; HOSTMIIMSEL : in std_ulogic; HOSTOPCODE : in std_logic_vector(1 downto 0); HOSTREQ : in std_ulogic; HOSTWRDATA : in std_logic_vector(31 downto 0); PHYEMAC0COL : in std_ulogic; PHYEMAC0CRS : in std_ulogic; PHYEMAC0GTXCLK : in std_ulogic; PHYEMAC0MCLKIN : in std_ulogic; PHYEMAC0MDIN : in std_ulogic; PHYEMAC0MIITXCLK : in std_ulogic; PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); PHYEMAC0RXBUFERR : in std_ulogic; PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); PHYEMAC0RXCHARISCOMMA : in std_ulogic; PHYEMAC0RXCHARISK : in std_ulogic; PHYEMAC0RXCHECKINGCRC : in std_ulogic; PHYEMAC0RXCLK : in std_ulogic; PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); PHYEMAC0RXCOMMADET : in std_ulogic; PHYEMAC0RXD : in std_logic_vector(7 downto 0); PHYEMAC0RXDISPERR : in std_ulogic; PHYEMAC0RXDV : in std_ulogic; PHYEMAC0RXER : in std_ulogic; PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); PHYEMAC0RXNOTINTABLE : in std_ulogic; PHYEMAC0RXRUNDISP : in std_ulogic; PHYEMAC0SIGNALDET : in std_ulogic; PHYEMAC0TXBUFERR : in std_ulogic; PHYEMAC1COL : in std_ulogic; PHYEMAC1CRS : in std_ulogic; PHYEMAC1GTXCLK : in std_ulogic; PHYEMAC1MCLKIN : in std_ulogic; PHYEMAC1MDIN : in std_ulogic; PHYEMAC1MIITXCLK : in std_ulogic; PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); PHYEMAC1RXBUFERR : in std_ulogic; PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); PHYEMAC1RXCHARISCOMMA : in std_ulogic; PHYEMAC1RXCHARISK : in std_ulogic; PHYEMAC1RXCHECKINGCRC : in std_ulogic; PHYEMAC1RXCLK : in std_ulogic; PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); PHYEMAC1RXCOMMADET : in std_ulogic; PHYEMAC1RXD : in std_logic_vector(7 downto 0); PHYEMAC1RXDISPERR : in std_ulogic; PHYEMAC1RXDV : in std_ulogic; PHYEMAC1RXER : in std_ulogic; PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); PHYEMAC1RXNOTINTABLE : in std_ulogic; PHYEMAC1RXRUNDISP : in std_ulogic; PHYEMAC1SIGNALDET : in std_ulogic; PHYEMAC1TXBUFERR : in std_ulogic; RESET : in std_ulogic; TIEEMAC0CONFIGVEC : in std_logic_vector(79 downto 0); TIEEMAC0UNICASTADDR : in std_logic_vector(47 downto 0); TIEEMAC1CONFIGVEC : in std_logic_vector(79 downto 0); TIEEMAC1UNICASTADDR : in std_logic_vector(47 downto 0) ); end component; -- CR 455025 -- Delay wrapper for 16-bit client mode signal PHYEMAC0MIITXCLK_delay : std_ulogic; signal CLIENTEMAC0TXD_delay : std_logic_vector(15 downto 0); signal CLIENTEMAC0TXDVLD_delay : std_ulogic; signal CLIENTEMAC0TXDVLDMSW_delay : std_ulogic; signal PHYEMAC0MIITXCLK_skewed : std_ulogic; signal CLIENTEMAC0TXD_client16_delay : std_logic_vector(15 downto 0); signal CLIENTEMAC0TXDVLD_client16_delay : std_ulogic; signal CLIENTEMAC0TXDVLDMSW_client16_delay : std_ulogic; signal PHYEMAC1MIITXCLK_delay : std_ulogic; signal CLIENTEMAC1TXD_delay : std_logic_vector(15 downto 0); signal CLIENTEMAC1TXDVLD_delay : std_ulogic; signal CLIENTEMAC1TXDVLDMSW_delay : std_ulogic; signal PHYEMAC1MIITXCLK_skewed : std_ulogic; signal CLIENTEMAC1TXD_client16_delay : std_logic_vector(15 downto 0); signal CLIENTEMAC1TXDVLD_client16_delay : std_ulogic; signal CLIENTEMAC1TXDVLDMSW_client16_delay : std_ulogic; constant client_in_delay : time := 125 ps; constant miitxclk_delay : time := 125 ps; -- Attribute-to-Cell mapping signals -- Input/Output Pin signals signal CLIENTEMAC0DCMLOCKED_ipd : std_ulogic; signal CLIENTEMAC0PAUSEREQ_ipd : std_ulogic; signal CLIENTEMAC0PAUSEVAL_ipd : std_logic_vector(15 downto 0); signal CLIENTEMAC0RXCLIENTCLKIN_ipd : std_ulogic; signal CLIENTEMAC0TXCLIENTCLKIN_ipd : std_ulogic; signal CLIENTEMAC0TXD_ipd : std_logic_vector(15 downto 0); signal CLIENTEMAC0TXDVLD_ipd : std_ulogic; signal CLIENTEMAC0TXDVLDMSW_ipd : std_ulogic; signal CLIENTEMAC0TXFIRSTBYTE_ipd : std_ulogic; signal CLIENTEMAC0TXGMIIMIICLKIN_ipd : std_ulogic; signal CLIENTEMAC0TXIFGDELAY_ipd : std_logic_vector(7 downto 0); signal CLIENTEMAC0TXUNDERRUN_ipd : std_ulogic; signal CLIENTEMAC1DCMLOCKED_ipd : std_ulogic; signal CLIENTEMAC1PAUSEREQ_ipd : std_ulogic; signal CLIENTEMAC1PAUSEVAL_ipd : std_logic_vector(15 downto 0); signal CLIENTEMAC1RXCLIENTCLKIN_ipd : std_ulogic; signal CLIENTEMAC1TXCLIENTCLKIN_ipd : std_ulogic; signal CLIENTEMAC1TXD_ipd : std_logic_vector(15 downto 0); signal CLIENTEMAC1TXDVLD_ipd : std_ulogic; signal CLIENTEMAC1TXDVLDMSW_ipd : std_ulogic; signal CLIENTEMAC1TXFIRSTBYTE_ipd : std_ulogic; signal CLIENTEMAC1TXGMIIMIICLKIN_ipd : std_ulogic; signal CLIENTEMAC1TXIFGDELAY_ipd : std_logic_vector(7 downto 0); signal CLIENTEMAC1TXUNDERRUN_ipd : std_ulogic; signal DCREMACENABLE_ipd : std_ulogic; signal HOSTADDR_ipd : std_logic_vector(9 downto 0); signal HOSTCLK_ipd : std_ulogic; signal HOSTEMAC1SEL_ipd : std_ulogic; signal HOSTMIIMSEL_ipd : std_ulogic; signal HOSTOPCODE_ipd : std_logic_vector(1 downto 0); signal HOSTREQ_ipd : std_ulogic; signal HOSTWRDATA_ipd : std_logic_vector(31 downto 0); signal PHYEMAC0COL_ipd : std_ulogic; signal PHYEMAC0CRS_ipd : std_ulogic; signal PHYEMAC0GTXCLK_ipd : std_ulogic; signal PHYEMAC0MCLKIN_ipd : std_ulogic; signal PHYEMAC0MDIN_ipd : std_ulogic; signal PHYEMAC0MIITXCLK_ipd : std_ulogic; signal PHYEMAC0PHYAD_ipd : std_logic_vector(4 downto 0); signal PHYEMAC0RXBUFERR_ipd : std_ulogic; signal PHYEMAC0RXBUFSTATUS_ipd : std_logic_vector(1 downto 0); signal PHYEMAC0RXCHARISCOMMA_ipd : std_ulogic; signal PHYEMAC0RXCHARISK_ipd : std_ulogic; signal PHYEMAC0RXCHECKINGCRC_ipd : std_ulogic; signal PHYEMAC0RXCLK_ipd : std_ulogic; signal PHYEMAC0RXCLKCORCNT_ipd : std_logic_vector(2 downto 0); signal PHYEMAC0RXCOMMADET_ipd : std_ulogic; signal PHYEMAC0RXD_ipd : std_logic_vector(7 downto 0); signal PHYEMAC0RXDISPERR_ipd : std_ulogic; signal PHYEMAC0RXDV_ipd : std_ulogic; signal PHYEMAC0RXER_ipd : std_ulogic; signal PHYEMAC0RXLOSSOFSYNC_ipd : std_logic_vector(1 downto 0); signal PHYEMAC0RXNOTINTABLE_ipd : std_ulogic; signal PHYEMAC0RXRUNDISP_ipd : std_ulogic; signal PHYEMAC0SIGNALDET_ipd : std_ulogic; signal PHYEMAC0TXBUFERR_ipd : std_ulogic; signal PHYEMAC1COL_ipd : std_ulogic; signal PHYEMAC1CRS_ipd : std_ulogic; signal PHYEMAC1GTXCLK_ipd : std_ulogic; signal PHYEMAC1MCLKIN_ipd : std_ulogic; signal PHYEMAC1MDIN_ipd : std_ulogic; signal PHYEMAC1MIITXCLK_ipd : std_ulogic; signal PHYEMAC1PHYAD_ipd : std_logic_vector(4 downto 0); signal PHYEMAC1RXBUFERR_ipd : std_ulogic; signal PHYEMAC1RXBUFSTATUS_ipd : std_logic_vector(1 downto 0); signal PHYEMAC1RXCHARISCOMMA_ipd : std_ulogic; signal PHYEMAC1RXCHARISK_ipd : std_ulogic; signal PHYEMAC1RXCHECKINGCRC_ipd : std_ulogic; signal PHYEMAC1RXCLK_ipd : std_ulogic; signal PHYEMAC1RXCLKCORCNT_ipd : std_logic_vector(2 downto 0); signal PHYEMAC1RXCOMMADET_ipd : std_ulogic; signal PHYEMAC1RXD_ipd : std_logic_vector(7 downto 0); signal PHYEMAC1RXDISPERR_ipd : std_ulogic; signal PHYEMAC1RXDV_ipd : std_ulogic; signal PHYEMAC1RXER_ipd : std_ulogic; signal PHYEMAC1RXLOSSOFSYNC_ipd : std_logic_vector(1 downto 0); signal PHYEMAC1RXNOTINTABLE_ipd : std_ulogic; signal PHYEMAC1RXRUNDISP_ipd : std_ulogic; signal PHYEMAC1SIGNALDET_ipd : std_ulogic; signal PHYEMAC1TXBUFERR_ipd : std_ulogic; signal RESET_ipd : std_ulogic; signal TIEEMAC0CONFIGVEC_ipd : std_logic_vector(79 downto 0); signal TIEEMAC0UNICASTADDR_ipd : std_logic_vector(47 downto 0); signal TIEEMAC1CONFIGVEC_ipd : std_logic_vector(79 downto 0); signal TIEEMAC1UNICASTADDR_ipd : std_logic_vector(47 downto 0); signal DCREMACWRITE_ipd : std_ulogic; signal DCREMACREAD_ipd : std_ulogic; signal DCREMACDBUS_ipd : std_logic_vector(0 to 31); signal DCREMACABUS_ipd : std_logic_vector(8 to 9); signal DCREMACCLK_ipd : std_ulogic; signal DCRHOSTDONEIR_out : std_ulogic; signal EMAC0CLIENTANINTERRUPT_out : std_ulogic; signal EMAC0CLIENTRXBADFRAME_out : std_ulogic; signal EMAC0CLIENTRXCLIENTCLKOUT_out : std_ulogic; signal EMAC0CLIENTRXD_out : std_logic_vector(15 downto 0); signal EMAC0CLIENTRXDVLD_out : std_ulogic; signal EMAC0CLIENTRXDVLDMSW_out : std_ulogic; signal EMAC0CLIENTRXDVREG6_out : std_ulogic; signal EMAC0CLIENTRXFRAMEDROP_out : std_ulogic; signal EMAC0CLIENTRXGOODFRAME_out : std_ulogic; signal EMAC0CLIENTRXSTATS_out : std_logic_vector(6 downto 0); signal EMAC0CLIENTRXSTATSBYTEVLD_out : std_ulogic; signal EMAC0CLIENTRXSTATSVLD_out : std_ulogic; signal EMAC0CLIENTTXACK_out : std_ulogic; signal EMAC0CLIENTTXCLIENTCLKOUT_out : std_ulogic; signal EMAC0CLIENTTXCOLLISION_out : std_ulogic; signal EMAC0CLIENTTXGMIIMIICLKOUT_out : std_ulogic; signal EMAC0CLIENTTXRETRANSMIT_out : std_ulogic; signal EMAC0CLIENTTXSTATS_out : std_ulogic; signal EMAC0CLIENTTXSTATSBYTEVLD_out : std_ulogic; signal EMAC0CLIENTTXSTATSVLD_out : std_ulogic; signal EMAC0PHYENCOMMAALIGN_out : std_ulogic; signal EMAC0PHYLOOPBACKMSB_out : std_ulogic; signal EMAC0PHYMCLKOUT_out : std_ulogic; signal EMAC0PHYMDOUT_out : std_ulogic; signal EMAC0PHYMDTRI_out : std_ulogic; signal EMAC0PHYMGTRXRESET_out : std_ulogic; signal EMAC0PHYMGTTXRESET_out : std_ulogic; signal EMAC0PHYPOWERDOWN_out : std_ulogic; signal EMAC0PHYSYNCACQSTATUS_out : std_ulogic; signal EMAC0PHYTXCHARDISPMODE_out : std_ulogic; signal EMAC0PHYTXCHARDISPVAL_out : std_ulogic; signal EMAC0PHYTXCHARISK_out : std_ulogic; signal EMAC0PHYTXCLK_out : std_ulogic; signal EMAC0PHYTXD_out : std_logic_vector(7 downto 0); signal EMAC0PHYTXEN_out : std_ulogic; signal EMAC0PHYTXER_out : std_ulogic; signal EMAC1CLIENTANINTERRUPT_out : std_ulogic; signal EMAC1CLIENTRXBADFRAME_out : std_ulogic; signal EMAC1CLIENTRXCLIENTCLKOUT_out : std_ulogic; signal EMAC1CLIENTRXD_out : std_logic_vector(15 downto 0); signal EMAC1CLIENTRXDVLD_out : std_ulogic; signal EMAC1CLIENTRXDVLDMSW_out : std_ulogic; signal EMAC1CLIENTRXDVREG6_out : std_ulogic; signal EMAC1CLIENTRXFRAMEDROP_out : std_ulogic; signal EMAC1CLIENTRXGOODFRAME_out : std_ulogic; signal EMAC1CLIENTRXSTATS_out : std_logic_vector(6 downto 0); signal EMAC1CLIENTRXSTATSBYTEVLD_out : std_ulogic; signal EMAC1CLIENTRXSTATSVLD_out : std_ulogic; signal EMAC1CLIENTTXACK_out : std_ulogic; signal EMAC1CLIENTTXCLIENTCLKOUT_out : std_ulogic; signal EMAC1CLIENTTXCOLLISION_out : std_ulogic; signal EMAC1CLIENTTXGMIIMIICLKOUT_out : std_ulogic; signal EMAC1CLIENTTXRETRANSMIT_out : std_ulogic; signal EMAC1CLIENTTXSTATS_out : std_ulogic; signal EMAC1CLIENTTXSTATSBYTEVLD_out : std_ulogic; signal EMAC1CLIENTTXSTATSVLD_out : std_ulogic; signal EMAC1PHYENCOMMAALIGN_out : std_ulogic; signal EMAC1PHYLOOPBACKMSB_out : std_ulogic; signal EMAC1PHYMCLKOUT_out : std_ulogic; signal EMAC1PHYMDOUT_out : std_ulogic; signal EMAC1PHYMDTRI_out : std_ulogic; signal EMAC1PHYMGTRXRESET_out : std_ulogic; signal EMAC1PHYMGTTXRESET_out : std_ulogic; signal EMAC1PHYPOWERDOWN_out : std_ulogic; signal EMAC1PHYSYNCACQSTATUS_out : std_ulogic; signal EMAC1PHYTXCHARDISPMODE_out : std_ulogic; signal EMAC1PHYTXCHARDISPVAL_out : std_ulogic; signal EMAC1PHYTXCHARISK_out : std_ulogic; signal EMAC1PHYTXCLK_out : std_ulogic; signal EMAC1PHYTXD_out : std_logic_vector(7 downto 0); signal EMAC1PHYTXEN_out : std_ulogic; signal EMAC1PHYTXER_out : std_ulogic; signal HOSTMIIMRDY_out : std_ulogic; signal HOSTRDDATA_out : std_logic_vector(31 downto 0); signal EMACDCRDBUS_out : std_logic_vector(0 to 31); signal EMACDCRACK_out : std_ulogic; begin CLIENTEMAC0DCMLOCKED_ipd <= CLIENTEMAC0DCMLOCKED after IN_DELAY; CLIENTEMAC0PAUSEREQ_ipd <= CLIENTEMAC0PAUSEREQ after IN_DELAY; CLIENTEMAC0PAUSEVAL_ipd <= CLIENTEMAC0PAUSEVAL after IN_DELAY; CLIENTEMAC0RXCLIENTCLKIN_ipd <= CLIENTEMAC0RXCLIENTCLKIN after IN_DELAY; CLIENTEMAC0TXCLIENTCLKIN_ipd <= CLIENTEMAC0TXCLIENTCLKIN after IN_DELAY; CLIENTEMAC0TXD_ipd <= CLIENTEMAC0TXD after IN_DELAY; CLIENTEMAC0TXDVLD_ipd <= CLIENTEMAC0TXDVLD after IN_DELAY; CLIENTEMAC0TXDVLDMSW_ipd <= CLIENTEMAC0TXDVLDMSW after IN_DELAY; CLIENTEMAC0TXFIRSTBYTE_ipd <= CLIENTEMAC0TXFIRSTBYTE after IN_DELAY; CLIENTEMAC0TXGMIIMIICLKIN_ipd <= CLIENTEMAC0TXGMIIMIICLKIN after IN_DELAY; CLIENTEMAC0TXIFGDELAY_ipd <= CLIENTEMAC0TXIFGDELAY after IN_DELAY; CLIENTEMAC0TXUNDERRUN_ipd <= CLIENTEMAC0TXUNDERRUN after IN_DELAY; CLIENTEMAC1DCMLOCKED_ipd <= CLIENTEMAC1DCMLOCKED after IN_DELAY; CLIENTEMAC1PAUSEREQ_ipd <= CLIENTEMAC1PAUSEREQ after IN_DELAY; CLIENTEMAC1PAUSEVAL_ipd <= CLIENTEMAC1PAUSEVAL after IN_DELAY; CLIENTEMAC1RXCLIENTCLKIN_ipd <= CLIENTEMAC1RXCLIENTCLKIN after IN_DELAY; CLIENTEMAC1TXCLIENTCLKIN_ipd <= CLIENTEMAC1TXCLIENTCLKIN after IN_DELAY; CLIENTEMAC1TXD_ipd <= CLIENTEMAC1TXD after IN_DELAY; CLIENTEMAC1TXDVLD_ipd <= CLIENTEMAC1TXDVLD after IN_DELAY; CLIENTEMAC1TXDVLDMSW_ipd <= CLIENTEMAC1TXDVLDMSW after IN_DELAY; CLIENTEMAC1TXFIRSTBYTE_ipd <= CLIENTEMAC1TXFIRSTBYTE after IN_DELAY; CLIENTEMAC1TXGMIIMIICLKIN_ipd <= CLIENTEMAC1TXGMIIMIICLKIN after IN_DELAY; CLIENTEMAC1TXIFGDELAY_ipd <= CLIENTEMAC1TXIFGDELAY after IN_DELAY; CLIENTEMAC1TXUNDERRUN_ipd <= CLIENTEMAC1TXUNDERRUN after IN_DELAY; DCREMACENABLE_ipd <= DCREMACENABLE after IN_DELAY; HOSTADDR_ipd <= HOSTADDR after IN_DELAY; HOSTCLK_ipd <= HOSTCLK after IN_DELAY; HOSTEMAC1SEL_ipd <= HOSTEMAC1SEL after IN_DELAY; HOSTMIIMSEL_ipd <= HOSTMIIMSEL after IN_DELAY; HOSTOPCODE_ipd <= HOSTOPCODE after IN_DELAY; HOSTREQ_ipd <= HOSTREQ after IN_DELAY; HOSTWRDATA_ipd <= HOSTWRDATA after IN_DELAY; PHYEMAC0COL_ipd <= PHYEMAC0COL after IN_DELAY; PHYEMAC0CRS_ipd <= PHYEMAC0CRS after IN_DELAY; PHYEMAC0GTXCLK_ipd <= PHYEMAC0GTXCLK after IN_DELAY; PHYEMAC0MCLKIN_ipd <= PHYEMAC0MCLKIN after IN_DELAY; PHYEMAC0MDIN_ipd <= PHYEMAC0MDIN after IN_DELAY; PHYEMAC0MIITXCLK_ipd <= PHYEMAC0MIITXCLK after IN_DELAY; PHYEMAC0PHYAD_ipd <= PHYEMAC0PHYAD after IN_DELAY; PHYEMAC0RXBUFERR_ipd <= PHYEMAC0RXBUFERR after IN_DELAY; PHYEMAC0RXBUFSTATUS_ipd <= PHYEMAC0RXBUFSTATUS after IN_DELAY; PHYEMAC0RXCHARISCOMMA_ipd <= PHYEMAC0RXCHARISCOMMA after IN_DELAY; PHYEMAC0RXCHARISK_ipd <= PHYEMAC0RXCHARISK after IN_DELAY; PHYEMAC0RXCHECKINGCRC_ipd <= PHYEMAC0RXCHECKINGCRC after IN_DELAY; PHYEMAC0RXCLK_ipd <= PHYEMAC0RXCLK after IN_DELAY; PHYEMAC0RXCLKCORCNT_ipd <= PHYEMAC0RXCLKCORCNT after IN_DELAY; PHYEMAC0RXCOMMADET_ipd <= PHYEMAC0RXCOMMADET after IN_DELAY; PHYEMAC0RXD_ipd <= PHYEMAC0RXD after IN_DELAY; PHYEMAC0RXDISPERR_ipd <= PHYEMAC0RXDISPERR after IN_DELAY; PHYEMAC0RXDV_ipd <= PHYEMAC0RXDV after IN_DELAY; PHYEMAC0RXER_ipd <= PHYEMAC0RXER after IN_DELAY; PHYEMAC0RXLOSSOFSYNC_ipd <= PHYEMAC0RXLOSSOFSYNC after IN_DELAY; PHYEMAC0RXNOTINTABLE_ipd <= PHYEMAC0RXNOTINTABLE after IN_DELAY; PHYEMAC0RXRUNDISP_ipd <= PHYEMAC0RXRUNDISP after IN_DELAY; PHYEMAC0SIGNALDET_ipd <= PHYEMAC0SIGNALDET after IN_DELAY; PHYEMAC0TXBUFERR_ipd <= PHYEMAC0TXBUFERR after IN_DELAY; PHYEMAC1COL_ipd <= PHYEMAC1COL after IN_DELAY; PHYEMAC1CRS_ipd <= PHYEMAC1CRS after IN_DELAY; PHYEMAC1GTXCLK_ipd <= PHYEMAC1GTXCLK after IN_DELAY; PHYEMAC1MCLKIN_ipd <= PHYEMAC1MCLKIN after IN_DELAY; PHYEMAC1MDIN_ipd <= PHYEMAC1MDIN after IN_DELAY; PHYEMAC1MIITXCLK_ipd <= PHYEMAC1MIITXCLK after IN_DELAY; PHYEMAC1PHYAD_ipd <= PHYEMAC1PHYAD after IN_DELAY; PHYEMAC1RXBUFERR_ipd <= PHYEMAC1RXBUFERR after IN_DELAY; PHYEMAC1RXBUFSTATUS_ipd <= PHYEMAC1RXBUFSTATUS after IN_DELAY; PHYEMAC1RXCHARISCOMMA_ipd <= PHYEMAC1RXCHARISCOMMA after IN_DELAY; PHYEMAC1RXCHARISK_ipd <= PHYEMAC1RXCHARISK after IN_DELAY; PHYEMAC1RXCHECKINGCRC_ipd <= PHYEMAC1RXCHECKINGCRC after IN_DELAY; PHYEMAC1RXCLK_ipd <= PHYEMAC1RXCLK after IN_DELAY; PHYEMAC1RXCLKCORCNT_ipd <= PHYEMAC1RXCLKCORCNT after IN_DELAY; PHYEMAC1RXCOMMADET_ipd <= PHYEMAC1RXCOMMADET after IN_DELAY; PHYEMAC1RXD_ipd <= PHYEMAC1RXD after IN_DELAY; PHYEMAC1RXDISPERR_ipd <= PHYEMAC1RXDISPERR after IN_DELAY; PHYEMAC1RXDV_ipd <= PHYEMAC1RXDV after IN_DELAY; PHYEMAC1RXER_ipd <= PHYEMAC1RXER after IN_DELAY; PHYEMAC1RXLOSSOFSYNC_ipd <= PHYEMAC1RXLOSSOFSYNC after IN_DELAY; PHYEMAC1RXNOTINTABLE_ipd <= PHYEMAC1RXNOTINTABLE after IN_DELAY; PHYEMAC1RXRUNDISP_ipd <= PHYEMAC1RXRUNDISP after IN_DELAY; PHYEMAC1SIGNALDET_ipd <= PHYEMAC1SIGNALDET after IN_DELAY; PHYEMAC1TXBUFERR_ipd <= PHYEMAC1TXBUFERR after IN_DELAY; RESET_ipd <= RESET after IN_DELAY; TIEEMAC0CONFIGVEC_ipd <= TIEEMAC0CONFIGVEC after IN_DELAY; TIEEMAC0UNICASTADDR_ipd <= TIEEMAC0UNICASTADDR after IN_DELAY; TIEEMAC1CONFIGVEC_ipd <= TIEEMAC1CONFIGVEC after IN_DELAY; TIEEMAC1UNICASTADDR_ipd <= TIEEMAC1UNICASTADDR after IN_DELAY; DCREMACWRITE_ipd <= DCREMACWRITE after IN_DELAY; DCREMACREAD_ipd <= DCREMACREAD after IN_DELAY; DCREMACDBUS_ipd <= DCREMACDBUS after IN_DELAY; DCREMACABUS_ipd <= DCREMACABUS after IN_DELAY; DCREMACCLK_ipd <= DCREMACCLK after IN_DELAY; -- CR 455025 Delay EMAC# client input signals in 16-bit client mode -- EMAC0 CLIENTEMAC0TXD_delay <= CLIENTEMAC0TXD_ipd after client_in_delay; CLIENTEMAC0TXDVLD_delay <= CLIENTEMAC0TXDVLD_ipd after client_in_delay; CLIENTEMAC0TXDVLDMSW_delay <= CLIENTEMAC0TXDVLDMSW_ipd after client_in_delay; CLIENTEMAC0TXD_client16_delay <= CLIENTEMAC0TXD_delay when TIEEMAC0CONFIGVEC(66) = '1' else CLIENTEMAC0TXD_ipd; -- CONFIGVEC[66] is 16-bit Tx client CLIENTEMAC0TXDVLD_client16_delay <= CLIENTEMAC0TXDVLD_delay when TIEEMAC0CONFIGVEC(66) = '1' else CLIENTEMAC0TXDVLD_ipd; CLIENTEMAC0TXDVLDMSW_client16_delay <= CLIENTEMAC0TXDVLDMSW_delay when TIEEMAC0CONFIGVEC(66) = '1' else CLIENTEMAC0TXDVLDMSW_ipd; -- EMAC1 CLIENTEMAC1TXD_delay <= CLIENTEMAC1TXD_ipd after client_in_delay; CLIENTEMAC1TXDVLD_delay <= CLIENTEMAC1TXDVLD_ipd after client_in_delay; CLIENTEMAC1TXDVLDMSW_delay <= CLIENTEMAC1TXDVLDMSW_ipd after client_in_delay; CLIENTEMAC1TXD_client16_delay <= CLIENTEMAC1TXD_delay when TIEEMAC1CONFIGVEC(66) = '1' else CLIENTEMAC1TXD_ipd; -- CONFIGVEC[66] is 16-bit Tx client CLIENTEMAC1TXDVLD_client16_delay <= CLIENTEMAC1TXDVLD_delay when TIEEMAC1CONFIGVEC(66) = '1' else CLIENTEMAC1TXDVLD_ipd; CLIENTEMAC1TXDVLDMSW_client16_delay <= CLIENTEMAC1TXDVLDMSW_delay when TIEEMAC1CONFIGVEC(66) = '1' else CLIENTEMAC1TXDVLDMSW_ipd; --Skew 125 MHz clock EMAC#MIITXCLK against 250 MHz clock in 16-bit client mode PHYEMAC0MIITXCLK_delay <= PHYEMAC0MIITXCLK_ipd after miitxclk_delay; PHYEMAC0MIITXCLK_skewed <= PHYEMAC0MIITXCLK_delay when TIEEMAC0CONFIGVEC(66) = '1' else PHYEMAC0MIITXCLK_ipd; -- In TXCLIENT16 mode PHYEMAC1MIITXCLK_delay <= PHYEMAC1MIITXCLK_ipd after miitxclk_delay; PHYEMAC1MIITXCLK_skewed <= PHYEMAC1MIITXCLK_delay when TIEEMAC1CONFIGVEC(66) = '1' else PHYEMAC1MIITXCLK_ipd; -- In TXCLIENT16 mode emac_swift_bw_1 : EMAC_SWIFT_BUS port map ( CLIENTEMAC0DCMLOCKED => CLIENTEMAC0DCMLOCKED_ipd, CLIENTEMAC0PAUSEREQ => CLIENTEMAC0PAUSEREQ_ipd, CLIENTEMAC0PAUSEVAL => CLIENTEMAC0PAUSEVAL_ipd, CLIENTEMAC0RXCLIENTCLKIN => CLIENTEMAC0RXCLIENTCLKIN_ipd, CLIENTEMAC0TXCLIENTCLKIN => CLIENTEMAC0TXCLIENTCLKIN_ipd, CLIENTEMAC0TXD => CLIENTEMAC0TXD_client16_delay, CLIENTEMAC0TXDVLD => CLIENTEMAC0TXDVLD_client16_delay, CLIENTEMAC0TXDVLDMSW => CLIENTEMAC0TXDVLDMSW_client16_delay, CLIENTEMAC0TXFIRSTBYTE => CLIENTEMAC0TXFIRSTBYTE_ipd, CLIENTEMAC0TXGMIIMIICLKIN => CLIENTEMAC0TXGMIIMIICLKIN_ipd, CLIENTEMAC0TXIFGDELAY => CLIENTEMAC0TXIFGDELAY_ipd, CLIENTEMAC0TXUNDERRUN => CLIENTEMAC0TXUNDERRUN_ipd, CLIENTEMAC1DCMLOCKED => CLIENTEMAC1DCMLOCKED_ipd, CLIENTEMAC1PAUSEREQ => CLIENTEMAC1PAUSEREQ_ipd, CLIENTEMAC1PAUSEVAL => CLIENTEMAC1PAUSEVAL_ipd, CLIENTEMAC1RXCLIENTCLKIN => CLIENTEMAC1RXCLIENTCLKIN_ipd, CLIENTEMAC1TXCLIENTCLKIN => CLIENTEMAC1TXCLIENTCLKIN_ipd, CLIENTEMAC1TXD => CLIENTEMAC1TXD_client16_delay, CLIENTEMAC1TXDVLD => CLIENTEMAC1TXDVLD_client16_delay, CLIENTEMAC1TXDVLDMSW => CLIENTEMAC1TXDVLDMSW_client16_delay, CLIENTEMAC1TXFIRSTBYTE => CLIENTEMAC1TXFIRSTBYTE_ipd, CLIENTEMAC1TXGMIIMIICLKIN => CLIENTEMAC1TXGMIIMIICLKIN_ipd, CLIENTEMAC1TXIFGDELAY => CLIENTEMAC1TXIFGDELAY_ipd, CLIENTEMAC1TXUNDERRUN => CLIENTEMAC1TXUNDERRUN_ipd, DCREMACABUS => DCREMACABUS_ipd, DCREMACCLK => DCREMACCLK_ipd, DCREMACDBUS => DCREMACDBUS_ipd, DCREMACENABLE => DCREMACENABLE_ipd, DCREMACREAD => DCREMACREAD_ipd, DCREMACWRITE => DCREMACWRITE_ipd, DCRHOSTDONEIR => DCRHOSTDONEIR_out, EMAC0CLIENTANINTERRUPT => EMAC0CLIENTANINTERRUPT_out, EMAC0CLIENTRXBADFRAME => EMAC0CLIENTRXBADFRAME_out, EMAC0CLIENTRXCLIENTCLKOUT => EMAC0CLIENTRXCLIENTCLKOUT_out, EMAC0CLIENTRXD => EMAC0CLIENTRXD_out, EMAC0CLIENTRXDVLD => EMAC0CLIENTRXDVLD_out, EMAC0CLIENTRXDVLDMSW => EMAC0CLIENTRXDVLDMSW_out, EMAC0CLIENTRXDVREG6 => EMAC0CLIENTRXDVREG6_out, EMAC0CLIENTRXFRAMEDROP => EMAC0CLIENTRXFRAMEDROP_out, EMAC0CLIENTRXGOODFRAME => EMAC0CLIENTRXGOODFRAME_out, EMAC0CLIENTRXSTATS => EMAC0CLIENTRXSTATS_out, EMAC0CLIENTRXSTATSBYTEVLD => EMAC0CLIENTRXSTATSBYTEVLD_out, EMAC0CLIENTRXSTATSVLD => EMAC0CLIENTRXSTATSVLD_out, EMAC0CLIENTTXACK => EMAC0CLIENTTXACK_out, EMAC0CLIENTTXCLIENTCLKOUT => EMAC0CLIENTTXCLIENTCLKOUT_out, EMAC0CLIENTTXCOLLISION => EMAC0CLIENTTXCOLLISION_out, EMAC0CLIENTTXGMIIMIICLKOUT => EMAC0CLIENTTXGMIIMIICLKOUT_out, EMAC0CLIENTTXRETRANSMIT => EMAC0CLIENTTXRETRANSMIT_out, EMAC0CLIENTTXSTATS => EMAC0CLIENTTXSTATS_out, EMAC0CLIENTTXSTATSBYTEVLD => EMAC0CLIENTTXSTATSBYTEVLD_out, EMAC0CLIENTTXSTATSVLD => EMAC0CLIENTTXSTATSVLD_out, EMAC0PHYENCOMMAALIGN => EMAC0PHYENCOMMAALIGN_out, EMAC0PHYLOOPBACKMSB => EMAC0PHYLOOPBACKMSB_out, EMAC0PHYMCLKOUT => EMAC0PHYMCLKOUT_out, EMAC0PHYMDOUT => EMAC0PHYMDOUT_out, EMAC0PHYMDTRI => EMAC0PHYMDTRI_out, EMAC0PHYMGTRXRESET => EMAC0PHYMGTRXRESET_out, EMAC0PHYMGTTXRESET => EMAC0PHYMGTTXRESET_out, EMAC0PHYPOWERDOWN => EMAC0PHYPOWERDOWN_out, EMAC0PHYSYNCACQSTATUS => EMAC0PHYSYNCACQSTATUS_out, EMAC0PHYTXCHARDISPMODE => EMAC0PHYTXCHARDISPMODE_out, EMAC0PHYTXCHARDISPVAL => EMAC0PHYTXCHARDISPVAL_out, EMAC0PHYTXCHARISK => EMAC0PHYTXCHARISK_out, EMAC0PHYTXCLK => EMAC0PHYTXCLK_out, EMAC0PHYTXD => EMAC0PHYTXD_out, EMAC0PHYTXEN => EMAC0PHYTXEN_out, EMAC0PHYTXER => EMAC0PHYTXER_out, EMAC1CLIENTANINTERRUPT => EMAC1CLIENTANINTERRUPT_out, EMAC1CLIENTRXBADFRAME => EMAC1CLIENTRXBADFRAME_out, EMAC1CLIENTRXCLIENTCLKOUT => EMAC1CLIENTRXCLIENTCLKOUT_out, EMAC1CLIENTRXD => EMAC1CLIENTRXD_out, EMAC1CLIENTRXDVLD => EMAC1CLIENTRXDVLD_out, EMAC1CLIENTRXDVLDMSW => EMAC1CLIENTRXDVLDMSW_out, EMAC1CLIENTRXDVREG6 => EMAC1CLIENTRXDVREG6_out, EMAC1CLIENTRXFRAMEDROP => EMAC1CLIENTRXFRAMEDROP_out, EMAC1CLIENTRXGOODFRAME => EMAC1CLIENTRXGOODFRAME_out, EMAC1CLIENTRXSTATS => EMAC1CLIENTRXSTATS_out, EMAC1CLIENTRXSTATSBYTEVLD => EMAC1CLIENTRXSTATSBYTEVLD_out, EMAC1CLIENTRXSTATSVLD => EMAC1CLIENTRXSTATSVLD_out, EMAC1CLIENTTXACK => EMAC1CLIENTTXACK_out, EMAC1CLIENTTXCLIENTCLKOUT => EMAC1CLIENTTXCLIENTCLKOUT_out, EMAC1CLIENTTXCOLLISION => EMAC1CLIENTTXCOLLISION_out, EMAC1CLIENTTXGMIIMIICLKOUT => EMAC1CLIENTTXGMIIMIICLKOUT_out, EMAC1CLIENTTXRETRANSMIT => EMAC1CLIENTTXRETRANSMIT_out, EMAC1CLIENTTXSTATS => EMAC1CLIENTTXSTATS_out, EMAC1CLIENTTXSTATSBYTEVLD => EMAC1CLIENTTXSTATSBYTEVLD_out, EMAC1CLIENTTXSTATSVLD => EMAC1CLIENTTXSTATSVLD_out, EMAC1PHYENCOMMAALIGN => EMAC1PHYENCOMMAALIGN_out, EMAC1PHYLOOPBACKMSB => EMAC1PHYLOOPBACKMSB_out, EMAC1PHYMCLKOUT => EMAC1PHYMCLKOUT_out, EMAC1PHYMDOUT => EMAC1PHYMDOUT_out, EMAC1PHYMDTRI => EMAC1PHYMDTRI_out, EMAC1PHYMGTRXRESET => EMAC1PHYMGTRXRESET_out, EMAC1PHYMGTTXRESET => EMAC1PHYMGTTXRESET_out, EMAC1PHYPOWERDOWN => EMAC1PHYPOWERDOWN_out, EMAC1PHYSYNCACQSTATUS => EMAC1PHYSYNCACQSTATUS_out, EMAC1PHYTXCHARDISPMODE => EMAC1PHYTXCHARDISPMODE_out, EMAC1PHYTXCHARDISPVAL => EMAC1PHYTXCHARDISPVAL_out, EMAC1PHYTXCHARISK => EMAC1PHYTXCHARISK_out, EMAC1PHYTXCLK => EMAC1PHYTXCLK_out, EMAC1PHYTXD => EMAC1PHYTXD_out, EMAC1PHYTXEN => EMAC1PHYTXEN_out, EMAC1PHYTXER => EMAC1PHYTXER_out, EMACDCRACK => EMACDCRACK_out, EMACDCRDBUS => EMACDCRDBUS_out, HOSTADDR => HOSTADDR_ipd, HOSTCLK => HOSTCLK_ipd, HOSTEMAC1SEL => HOSTEMAC1SEL_ipd, HOSTMIIMRDY => HOSTMIIMRDY_out, HOSTMIIMSEL => HOSTMIIMSEL_ipd, HOSTOPCODE => HOSTOPCODE_ipd, HOSTRDDATA => HOSTRDDATA_out, HOSTREQ => HOSTREQ_ipd, HOSTWRDATA => HOSTWRDATA_ipd, PHYEMAC0COL => PHYEMAC0COL_ipd, PHYEMAC0CRS => PHYEMAC0CRS_ipd, PHYEMAC0GTXCLK => PHYEMAC0GTXCLK_ipd, PHYEMAC0MCLKIN => PHYEMAC0MCLKIN_ipd, PHYEMAC0MDIN => PHYEMAC0MDIN_ipd, PHYEMAC0MIITXCLK => PHYEMAC0MIITXCLK_skewed, PHYEMAC0PHYAD => PHYEMAC0PHYAD_ipd, PHYEMAC0RXBUFERR => PHYEMAC0RXBUFERR_ipd, PHYEMAC0RXBUFSTATUS => PHYEMAC0RXBUFSTATUS_ipd, PHYEMAC0RXCHARISCOMMA => PHYEMAC0RXCHARISCOMMA_ipd, PHYEMAC0RXCHARISK => PHYEMAC0RXCHARISK_ipd, PHYEMAC0RXCHECKINGCRC => PHYEMAC0RXCHECKINGCRC_ipd, PHYEMAC0RXCLK => PHYEMAC0RXCLK_ipd, PHYEMAC0RXCLKCORCNT => PHYEMAC0RXCLKCORCNT_ipd, PHYEMAC0RXCOMMADET => PHYEMAC0RXCOMMADET_ipd, PHYEMAC0RXD => PHYEMAC0RXD_ipd, PHYEMAC0RXDISPERR => PHYEMAC0RXDISPERR_ipd, PHYEMAC0RXDV => PHYEMAC0RXDV_ipd, PHYEMAC0RXER => PHYEMAC0RXER_ipd, PHYEMAC0RXLOSSOFSYNC => PHYEMAC0RXLOSSOFSYNC_ipd, PHYEMAC0RXNOTINTABLE => PHYEMAC0RXNOTINTABLE_ipd, PHYEMAC0RXRUNDISP => PHYEMAC0RXRUNDISP_ipd, PHYEMAC0SIGNALDET => PHYEMAC0SIGNALDET_ipd, PHYEMAC0TXBUFERR => PHYEMAC0TXBUFERR_ipd, PHYEMAC1COL => PHYEMAC1COL_ipd, PHYEMAC1CRS => PHYEMAC1CRS_ipd, PHYEMAC1GTXCLK => PHYEMAC1GTXCLK_ipd, PHYEMAC1MCLKIN => PHYEMAC1MCLKIN_ipd, PHYEMAC1MDIN => PHYEMAC1MDIN_ipd, PHYEMAC1MIITXCLK => PHYEMAC1MIITXCLK_skewed, PHYEMAC1PHYAD => PHYEMAC1PHYAD_ipd, PHYEMAC1RXBUFERR => PHYEMAC1RXBUFERR_ipd, PHYEMAC1RXBUFSTATUS => PHYEMAC1RXBUFSTATUS_ipd, PHYEMAC1RXCHARISCOMMA => PHYEMAC1RXCHARISCOMMA_ipd, PHYEMAC1RXCHARISK => PHYEMAC1RXCHARISK_ipd, PHYEMAC1RXCHECKINGCRC => PHYEMAC1RXCHECKINGCRC_ipd, PHYEMAC1RXCLK => PHYEMAC1RXCLK_ipd, PHYEMAC1RXCLKCORCNT => PHYEMAC1RXCLKCORCNT_ipd, PHYEMAC1RXCOMMADET => PHYEMAC1RXCOMMADET_ipd, PHYEMAC1RXD => PHYEMAC1RXD_ipd, PHYEMAC1RXDISPERR => PHYEMAC1RXDISPERR_ipd, PHYEMAC1RXDV => PHYEMAC1RXDV_ipd, PHYEMAC1RXER => PHYEMAC1RXER_ipd, PHYEMAC1RXLOSSOFSYNC => PHYEMAC1RXLOSSOFSYNC_ipd, PHYEMAC1RXNOTINTABLE => PHYEMAC1RXNOTINTABLE_ipd, PHYEMAC1RXRUNDISP => PHYEMAC1RXRUNDISP_ipd, PHYEMAC1SIGNALDET => PHYEMAC1SIGNALDET_ipd, PHYEMAC1TXBUFERR => PHYEMAC1TXBUFERR_ipd, RESET => RESET_ipd, TIEEMAC0CONFIGVEC => TIEEMAC0CONFIGVEC_ipd, TIEEMAC0UNICASTADDR => TIEEMAC0UNICASTADDR_ipd, TIEEMAC1CONFIGVEC => TIEEMAC1CONFIGVEC_ipd, TIEEMAC1UNICASTADDR => TIEEMAC1UNICASTADDR_ipd ); TIMING : process -- Pin timing violations (clock input pins) -- Pin Timing Violations (all input pins) -- Output Pin glitch declaration variable DCRHOSTDONEIR_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTANINTERRUPT_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXBADFRAME_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD0_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD1_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD2_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD3_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD4_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD5_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD6_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD7_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD8_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD9_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD10_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD11_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD12_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD13_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD14_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD15_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXDVLD_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXDVLDMSW_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXDVREG6_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXFRAMEDROP_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXGOODFRAME_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS0_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS1_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS2_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS3_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS4_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS5_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS6_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATSVLD_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXACK_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXCOLLISION_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXGMIIMIICLKOUT_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXRETRANSMIT_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXSTATS_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXSTATSVLD_GlitchData : VitalGlitchDataType; variable EMAC0PHYENCOMMAALIGN_GlitchData : VitalGlitchDataType; variable EMAC0PHYLOOPBACKMSB_GlitchData : VitalGlitchDataType; variable EMAC0PHYMCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC0PHYMDOUT_GlitchData : VitalGlitchDataType; variable EMAC0PHYMDTRI_GlitchData : VitalGlitchDataType; variable EMAC0PHYMGTRXRESET_GlitchData : VitalGlitchDataType; variable EMAC0PHYMGTTXRESET_GlitchData : VitalGlitchDataType; variable EMAC0PHYPOWERDOWN_GlitchData : VitalGlitchDataType; variable EMAC0PHYSYNCACQSTATUS_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXCHARDISPMODE_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXCHARDISPVAL_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXCHARISK_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXCLK_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD0_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD1_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD2_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD3_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD4_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD5_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD6_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD7_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXEN_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXER_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTANINTERRUPT_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXBADFRAME_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD0_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD1_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD2_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD3_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD4_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD5_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD6_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD7_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD8_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD9_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD10_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD11_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD12_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD13_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD14_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD15_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXDVLD_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXDVLDMSW_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXDVREG6_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXFRAMEDROP_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXGOODFRAME_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS0_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS1_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS2_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS3_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS4_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS5_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS6_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATSVLD_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXACK_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXCOLLISION_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXGMIIMIICLKOUT_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXRETRANSMIT_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXSTATS_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXSTATSVLD_GlitchData : VitalGlitchDataType; variable EMAC1PHYENCOMMAALIGN_GlitchData : VitalGlitchDataType; variable EMAC1PHYLOOPBACKMSB_GlitchData : VitalGlitchDataType; variable EMAC1PHYMCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC1PHYMDOUT_GlitchData : VitalGlitchDataType; variable EMAC1PHYMDTRI_GlitchData : VitalGlitchDataType; variable EMAC1PHYMGTRXRESET_GlitchData : VitalGlitchDataType; variable EMAC1PHYMGTTXRESET_GlitchData : VitalGlitchDataType; variable EMAC1PHYPOWERDOWN_GlitchData : VitalGlitchDataType; variable EMAC1PHYSYNCACQSTATUS_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXCHARDISPMODE_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXCHARDISPVAL_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXCHARISK_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXCLK_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD0_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD1_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD2_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD3_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD4_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD5_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD6_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD7_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXEN_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXER_GlitchData : VitalGlitchDataType; variable HOSTMIIMRDY_GlitchData : VitalGlitchDataType; variable HOSTRDDATA0_GlitchData : VitalGlitchDataType; variable HOSTRDDATA1_GlitchData : VitalGlitchDataType; variable HOSTRDDATA2_GlitchData : VitalGlitchDataType; variable HOSTRDDATA3_GlitchData : VitalGlitchDataType; variable HOSTRDDATA4_GlitchData : VitalGlitchDataType; variable HOSTRDDATA5_GlitchData : VitalGlitchDataType; variable HOSTRDDATA6_GlitchData : VitalGlitchDataType; variable HOSTRDDATA7_GlitchData : VitalGlitchDataType; variable HOSTRDDATA8_GlitchData : VitalGlitchDataType; variable HOSTRDDATA9_GlitchData : VitalGlitchDataType; variable HOSTRDDATA10_GlitchData : VitalGlitchDataType; variable HOSTRDDATA11_GlitchData : VitalGlitchDataType; variable HOSTRDDATA12_GlitchData : VitalGlitchDataType; variable HOSTRDDATA13_GlitchData : VitalGlitchDataType; variable HOSTRDDATA14_GlitchData : VitalGlitchDataType; variable HOSTRDDATA15_GlitchData : VitalGlitchDataType; variable HOSTRDDATA16_GlitchData : VitalGlitchDataType; variable HOSTRDDATA17_GlitchData : VitalGlitchDataType; variable HOSTRDDATA18_GlitchData : VitalGlitchDataType; variable HOSTRDDATA19_GlitchData : VitalGlitchDataType; variable HOSTRDDATA20_GlitchData : VitalGlitchDataType; variable HOSTRDDATA21_GlitchData : VitalGlitchDataType; variable HOSTRDDATA22_GlitchData : VitalGlitchDataType; variable HOSTRDDATA23_GlitchData : VitalGlitchDataType; variable HOSTRDDATA24_GlitchData : VitalGlitchDataType; variable HOSTRDDATA25_GlitchData : VitalGlitchDataType; variable HOSTRDDATA26_GlitchData : VitalGlitchDataType; variable HOSTRDDATA27_GlitchData : VitalGlitchDataType; variable HOSTRDDATA28_GlitchData : VitalGlitchDataType; variable HOSTRDDATA29_GlitchData : VitalGlitchDataType; variable HOSTRDDATA30_GlitchData : VitalGlitchDataType; variable HOSTRDDATA31_GlitchData : VitalGlitchDataType; variable EMACDCRACK_GlitchData : VitalGlitchDataType; begin EMACDCRACK <= EMACDCRACK_out; EMACDCRDBUS <= EMACDCRDBUS_out; DCRHOSTDONEIR <= DCRHOSTDONEIR_out; -- Output-to-Clock path delay VitalPathDelay01 ( OutSignal => EMAC0CLIENTANINTERRUPT, GlitchData => EMAC0CLIENTANINTERRUPT_GlitchData, OutSignalName => "EMAC0CLIENTANINTERRUPT", OutTemp => EMAC0CLIENTANINTERRUPT_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXBADFRAME, GlitchData => EMAC0CLIENTRXBADFRAME_GlitchData, OutSignalName => "EMAC0CLIENTRXBADFRAME", OutTemp => EMAC0CLIENTRXBADFRAME_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(0), GlitchData => EMAC0CLIENTRXD0_GlitchData, OutSignalName => "EMAC0CLIENTRXD(0)", OutTemp => EMAC0CLIENTRXD_OUT(0), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(1), GlitchData => EMAC0CLIENTRXD1_GlitchData, OutSignalName => "EMAC0CLIENTRXD(1)", OutTemp => EMAC0CLIENTRXD_OUT(1), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(2), GlitchData => EMAC0CLIENTRXD2_GlitchData, OutSignalName => "EMAC0CLIENTRXD(2)", OutTemp => EMAC0CLIENTRXD_OUT(2), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(3), GlitchData => EMAC0CLIENTRXD3_GlitchData, OutSignalName => "EMAC0CLIENTRXD(3)", OutTemp => EMAC0CLIENTRXD_OUT(3), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(4), GlitchData => EMAC0CLIENTRXD4_GlitchData, OutSignalName => "EMAC0CLIENTRXD(4)", OutTemp => EMAC0CLIENTRXD_OUT(4), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(5), GlitchData => EMAC0CLIENTRXD5_GlitchData, OutSignalName => "EMAC0CLIENTRXD(5)", OutTemp => EMAC0CLIENTRXD_OUT(5), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(6), GlitchData => EMAC0CLIENTRXD6_GlitchData, OutSignalName => "EMAC0CLIENTRXD(6)", OutTemp => EMAC0CLIENTRXD_OUT(6), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(7), GlitchData => EMAC0CLIENTRXD7_GlitchData, OutSignalName => "EMAC0CLIENTRXD(7)", OutTemp => EMAC0CLIENTRXD_OUT(7), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(8), GlitchData => EMAC0CLIENTRXD8_GlitchData, OutSignalName => "EMAC0CLIENTRXD(8)", OutTemp => EMAC0CLIENTRXD_OUT(8), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(9), GlitchData => EMAC0CLIENTRXD9_GlitchData, OutSignalName => "EMAC0CLIENTRXD(9)", OutTemp => EMAC0CLIENTRXD_OUT(9), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(10), GlitchData => EMAC0CLIENTRXD10_GlitchData, OutSignalName => "EMAC0CLIENTRXD(10)", OutTemp => EMAC0CLIENTRXD_OUT(10), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(11), GlitchData => EMAC0CLIENTRXD11_GlitchData, OutSignalName => "EMAC0CLIENTRXD(11)", OutTemp => EMAC0CLIENTRXD_OUT(11), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(12), GlitchData => EMAC0CLIENTRXD12_GlitchData, OutSignalName => "EMAC0CLIENTRXD(12)", OutTemp => EMAC0CLIENTRXD_OUT(12), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(13), GlitchData => EMAC0CLIENTRXD13_GlitchData, OutSignalName => "EMAC0CLIENTRXD(13)", OutTemp => EMAC0CLIENTRXD_OUT(13), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(14), GlitchData => EMAC0CLIENTRXD14_GlitchData, OutSignalName => "EMAC0CLIENTRXD(14)", OutTemp => EMAC0CLIENTRXD_OUT(14), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(15), GlitchData => EMAC0CLIENTRXD15_GlitchData, OutSignalName => "EMAC0CLIENTRXD(15)", OutTemp => EMAC0CLIENTRXD_OUT(15), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXDVLD, GlitchData => EMAC0CLIENTRXDVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXDVLD", OutTemp => EMAC0CLIENTRXDVLD_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXDVLDMSW, GlitchData => EMAC0CLIENTRXDVLDMSW_GlitchData, OutSignalName => "EMAC0CLIENTRXDVLDMSW", OutTemp => EMAC0CLIENTRXDVLDMSW_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXDVREG6, GlitchData => EMAC0CLIENTRXDVREG6_GlitchData, OutSignalName => "EMAC0CLIENTRXDVREG6", OutTemp => EMAC0CLIENTRXDVREG6_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXFRAMEDROP, GlitchData => EMAC0CLIENTRXFRAMEDROP_GlitchData, OutSignalName => "EMAC0CLIENTRXFRAMEDROP", OutTemp => EMAC0CLIENTRXFRAMEDROP_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXGOODFRAME, GlitchData => EMAC0CLIENTRXGOODFRAME_GlitchData, OutSignalName => "EMAC0CLIENTRXGOODFRAME", OutTemp => EMAC0CLIENTRXGOODFRAME_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(0), GlitchData => EMAC0CLIENTRXSTATS0_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(0)", OutTemp => EMAC0CLIENTRXSTATS_OUT(0), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(1), GlitchData => EMAC0CLIENTRXSTATS1_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(1)", OutTemp => EMAC0CLIENTRXSTATS_OUT(1), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(2), GlitchData => EMAC0CLIENTRXSTATS2_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(2)", OutTemp => EMAC0CLIENTRXSTATS_OUT(2), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(3), GlitchData => EMAC0CLIENTRXSTATS3_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(3)", OutTemp => EMAC0CLIENTRXSTATS_OUT(3), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(4), GlitchData => EMAC0CLIENTRXSTATS4_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(4)", OutTemp => EMAC0CLIENTRXSTATS_OUT(4), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(5), GlitchData => EMAC0CLIENTRXSTATS5_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(5)", OutTemp => EMAC0CLIENTRXSTATS_OUT(5), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(6), GlitchData => EMAC0CLIENTRXSTATS6_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(6)", OutTemp => EMAC0CLIENTRXSTATS_OUT(6), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATSBYTEVLD, GlitchData => EMAC0CLIENTRXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATSBYTEVLD", OutTemp => EMAC0CLIENTRXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATSVLD, GlitchData => EMAC0CLIENTRXSTATSVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATSVLD", OutTemp => EMAC0CLIENTRXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXACK, GlitchData => EMAC0CLIENTTXACK_GlitchData, OutSignalName => "EMAC0CLIENTTXACK", OutTemp => EMAC0CLIENTTXACK_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXCLIENTCLKOUT, GlitchData => EMAC0CLIENTTXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC0CLIENTTXCLIENTCLKOUT", OutTemp => EMAC0CLIENTTXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXCOLLISION, GlitchData => EMAC0CLIENTTXCOLLISION_GlitchData, OutSignalName => "EMAC0CLIENTTXCOLLISION", OutTemp => EMAC0CLIENTTXCOLLISION_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXGMIIMIICLKOUT, GlitchData => EMAC0CLIENTTXGMIIMIICLKOUT_GlitchData, OutSignalName => "EMAC0CLIENTTXGMIIMIICLKOUT", OutTemp => EMAC0CLIENTTXGMIIMIICLKOUT_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXRETRANSMIT, GlitchData => EMAC0CLIENTTXRETRANSMIT_GlitchData, OutSignalName => "EMAC0CLIENTTXRETRANSMIT", OutTemp => EMAC0CLIENTTXRETRANSMIT_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATS, GlitchData => EMAC0CLIENTTXSTATS_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATS", OutTemp => EMAC0CLIENTTXSTATS_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATSBYTEVLD, GlitchData => EMAC0CLIENTTXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATSBYTEVLD", OutTemp => EMAC0CLIENTTXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATSVLD, GlitchData => EMAC0CLIENTTXSTATSVLD_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATSVLD", OutTemp => EMAC0CLIENTTXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYENCOMMAALIGN, GlitchData => EMAC0PHYENCOMMAALIGN_GlitchData, OutSignalName => "EMAC0PHYENCOMMAALIGN", OutTemp => EMAC0PHYENCOMMAALIGN_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYLOOPBACKMSB, GlitchData => EMAC0PHYLOOPBACKMSB_GlitchData, OutSignalName => "EMAC0PHYLOOPBACKMSB", OutTemp => EMAC0PHYLOOPBACKMSB_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMCLKOUT, GlitchData => EMAC0PHYMCLKOUT_GlitchData, OutSignalName => "EMAC0PHYMCLKOUT", OutTemp => EMAC0PHYMCLKOUT_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMDOUT, GlitchData => EMAC0PHYMDOUT_GlitchData, OutSignalName => "EMAC0PHYMDOUT", OutTemp => EMAC0PHYMDOUT_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMDTRI, GlitchData => EMAC0PHYMDTRI_GlitchData, OutSignalName => "EMAC0PHYMDTRI", OutTemp => EMAC0PHYMDTRI_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMGTRXRESET, GlitchData => EMAC0PHYMGTRXRESET_GlitchData, OutSignalName => "EMAC0PHYMGTRXRESET", OutTemp => EMAC0PHYMGTRXRESET_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMGTTXRESET, GlitchData => EMAC0PHYMGTTXRESET_GlitchData, OutSignalName => "EMAC0PHYMGTTXRESET", OutTemp => EMAC0PHYMGTTXRESET_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYPOWERDOWN, GlitchData => EMAC0PHYPOWERDOWN_GlitchData, OutSignalName => "EMAC0PHYPOWERDOWN", OutTemp => EMAC0PHYPOWERDOWN_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYSYNCACQSTATUS, GlitchData => EMAC0PHYSYNCACQSTATUS_GlitchData, OutSignalName => "EMAC0PHYSYNCACQSTATUS", OutTemp => EMAC0PHYSYNCACQSTATUS_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARDISPMODE, GlitchData => EMAC0PHYTXCHARDISPMODE_GlitchData, OutSignalName => "EMAC0PHYTXCHARDISPMODE", OutTemp => EMAC0PHYTXCHARDISPMODE_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARDISPVAL, GlitchData => EMAC0PHYTXCHARDISPVAL_GlitchData, OutSignalName => "EMAC0PHYTXCHARDISPVAL", OutTemp => EMAC0PHYTXCHARDISPVAL_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARISK, GlitchData => EMAC0PHYTXCHARISK_GlitchData, OutSignalName => "EMAC0PHYTXCHARISK", OutTemp => EMAC0PHYTXCHARISK_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCLK, GlitchData => EMAC0PHYTXCLK_GlitchData, OutSignalName => "EMAC0PHYTXCLK", OutTemp => EMAC0PHYTXCLK_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(0), GlitchData => EMAC0PHYTXD0_GlitchData, OutSignalName => "EMAC0PHYTXD(0)", OutTemp => EMAC0PHYTXD_OUT(0), Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(1), GlitchData => EMAC0PHYTXD1_GlitchData, OutSignalName => "EMAC0PHYTXD(1)", OutTemp => EMAC0PHYTXD_OUT(1), Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(2), GlitchData => EMAC0PHYTXD2_GlitchData, OutSignalName => "EMAC0PHYTXD(2)", OutTemp => EMAC0PHYTXD_OUT(2), Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(3), GlitchData => EMAC0PHYTXD3_GlitchData, OutSignalName => "EMAC0PHYTXD(3)", OutTemp => EMAC0PHYTXD_OUT(3), Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(4), GlitchData => EMAC0PHYTXD4_GlitchData, OutSignalName => "EMAC0PHYTXD(4)", OutTemp => EMAC0PHYTXD_OUT(4), Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(5), GlitchData => EMAC0PHYTXD5_GlitchData, OutSignalName => "EMAC0PHYTXD(5)", OutTemp => EMAC0PHYTXD_OUT(5), Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(6), GlitchData => EMAC0PHYTXD6_GlitchData, OutSignalName => "EMAC0PHYTXD(6)", OutTemp => EMAC0PHYTXD_OUT(6), Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(7), GlitchData => EMAC0PHYTXD7_GlitchData, OutSignalName => "EMAC0PHYTXD(7)", OutTemp => EMAC0PHYTXD_OUT(7), Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXEN, GlitchData => EMAC0PHYTXEN_GlitchData, OutSignalName => "EMAC0PHYTXEN", OutTemp => EMAC0PHYTXEN_OUT, Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXER, GlitchData => EMAC0PHYTXER_GlitchData, OutSignalName => "EMAC0PHYTXER", OutTemp => EMAC0PHYTXER_OUT, Paths => (0 => (CLIENTEMAC0TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTANINTERRUPT, GlitchData => EMAC1CLIENTANINTERRUPT_GlitchData, OutSignalName => "EMAC1CLIENTANINTERRUPT", OutTemp => EMAC1CLIENTANINTERRUPT_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXBADFRAME, GlitchData => EMAC1CLIENTRXBADFRAME_GlitchData, OutSignalName => "EMAC1CLIENTRXBADFRAME", OutTemp => EMAC1CLIENTRXBADFRAME_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(0), GlitchData => EMAC1CLIENTRXD0_GlitchData, OutSignalName => "EMAC1CLIENTRXD(0)", OutTemp => EMAC1CLIENTRXD_OUT(0), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(1), GlitchData => EMAC1CLIENTRXD1_GlitchData, OutSignalName => "EMAC1CLIENTRXD(1)", OutTemp => EMAC1CLIENTRXD_OUT(1), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(2), GlitchData => EMAC1CLIENTRXD2_GlitchData, OutSignalName => "EMAC1CLIENTRXD(2)", OutTemp => EMAC1CLIENTRXD_OUT(2), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(3), GlitchData => EMAC1CLIENTRXD3_GlitchData, OutSignalName => "EMAC1CLIENTRXD(3)", OutTemp => EMAC1CLIENTRXD_OUT(3), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(4), GlitchData => EMAC1CLIENTRXD4_GlitchData, OutSignalName => "EMAC1CLIENTRXD(4)", OutTemp => EMAC1CLIENTRXD_OUT(4), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(5), GlitchData => EMAC1CLIENTRXD5_GlitchData, OutSignalName => "EMAC1CLIENTRXD(5)", OutTemp => EMAC1CLIENTRXD_OUT(5), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(6), GlitchData => EMAC1CLIENTRXD6_GlitchData, OutSignalName => "EMAC1CLIENTRXD(6)", OutTemp => EMAC1CLIENTRXD_OUT(6), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(7), GlitchData => EMAC1CLIENTRXD7_GlitchData, OutSignalName => "EMAC1CLIENTRXD(7)", OutTemp => EMAC1CLIENTRXD_OUT(7), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(8), GlitchData => EMAC1CLIENTRXD8_GlitchData, OutSignalName => "EMAC1CLIENTRXD(8)", OutTemp => EMAC1CLIENTRXD_OUT(8), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(9), GlitchData => EMAC1CLIENTRXD9_GlitchData, OutSignalName => "EMAC1CLIENTRXD(9)", OutTemp => EMAC1CLIENTRXD_OUT(9), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(10), GlitchData => EMAC1CLIENTRXD10_GlitchData, OutSignalName => "EMAC1CLIENTRXD(10)", OutTemp => EMAC1CLIENTRXD_OUT(10), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(11), GlitchData => EMAC1CLIENTRXD11_GlitchData, OutSignalName => "EMAC1CLIENTRXD(11)", OutTemp => EMAC1CLIENTRXD_OUT(11), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(12), GlitchData => EMAC1CLIENTRXD12_GlitchData, OutSignalName => "EMAC1CLIENTRXD(12)", OutTemp => EMAC1CLIENTRXD_OUT(12), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(13), GlitchData => EMAC1CLIENTRXD13_GlitchData, OutSignalName => "EMAC1CLIENTRXD(13)", OutTemp => EMAC1CLIENTRXD_OUT(13), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(14), GlitchData => EMAC1CLIENTRXD14_GlitchData, OutSignalName => "EMAC1CLIENTRXD(14)", OutTemp => EMAC1CLIENTRXD_OUT(14), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(15), GlitchData => EMAC1CLIENTRXD15_GlitchData, OutSignalName => "EMAC1CLIENTRXD(15)", OutTemp => EMAC1CLIENTRXD_OUT(15), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXDVLD, GlitchData => EMAC1CLIENTRXDVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXDVLD", OutTemp => EMAC1CLIENTRXDVLD_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXDVLDMSW, GlitchData => EMAC1CLIENTRXDVLDMSW_GlitchData, OutSignalName => "EMAC1CLIENTRXDVLDMSW", OutTemp => EMAC1CLIENTRXDVLDMSW_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXDVREG6, GlitchData => EMAC1CLIENTRXDVREG6_GlitchData, OutSignalName => "EMAC1CLIENTRXDVREG6", OutTemp => EMAC1CLIENTRXDVREG6_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXFRAMEDROP, GlitchData => EMAC1CLIENTRXFRAMEDROP_GlitchData, OutSignalName => "EMAC1CLIENTRXFRAMEDROP", OutTemp => EMAC1CLIENTRXFRAMEDROP_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXGOODFRAME, GlitchData => EMAC1CLIENTRXGOODFRAME_GlitchData, OutSignalName => "EMAC1CLIENTRXGOODFRAME", OutTemp => EMAC1CLIENTRXGOODFRAME_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(0), GlitchData => EMAC1CLIENTRXSTATS0_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(0)", OutTemp => EMAC1CLIENTRXSTATS_OUT(0), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(1), GlitchData => EMAC1CLIENTRXSTATS1_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(1)", OutTemp => EMAC1CLIENTRXSTATS_OUT(1), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(2), GlitchData => EMAC1CLIENTRXSTATS2_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(2)", OutTemp => EMAC1CLIENTRXSTATS_OUT(2), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(3), GlitchData => EMAC1CLIENTRXSTATS3_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(3)", OutTemp => EMAC1CLIENTRXSTATS_OUT(3), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(4), GlitchData => EMAC1CLIENTRXSTATS4_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(4)", OutTemp => EMAC1CLIENTRXSTATS_OUT(4), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(5), GlitchData => EMAC1CLIENTRXSTATS5_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(5)", OutTemp => EMAC1CLIENTRXSTATS_OUT(5), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(6), GlitchData => EMAC1CLIENTRXSTATS6_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(6)", OutTemp => EMAC1CLIENTRXSTATS_OUT(6), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATSBYTEVLD, GlitchData => EMAC1CLIENTRXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATSBYTEVLD", OutTemp => EMAC1CLIENTRXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATSVLD, GlitchData => EMAC1CLIENTRXSTATSVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATSVLD", OutTemp => EMAC1CLIENTRXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXACK, GlitchData => EMAC1CLIENTTXACK_GlitchData, OutSignalName => "EMAC1CLIENTTXACK", OutTemp => EMAC1CLIENTTXACK_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXCLIENTCLKOUT, GlitchData => EMAC1CLIENTTXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC1CLIENTTXCLIENTCLKOUT", OutTemp => EMAC1CLIENTTXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXCOLLISION, GlitchData => EMAC1CLIENTTXCOLLISION_GlitchData, OutSignalName => "EMAC1CLIENTTXCOLLISION", OutTemp => EMAC1CLIENTTXCOLLISION_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXGMIIMIICLKOUT, GlitchData => EMAC1CLIENTTXGMIIMIICLKOUT_GlitchData, OutSignalName => "EMAC1CLIENTTXGMIIMIICLKOUT", OutTemp => EMAC1CLIENTTXGMIIMIICLKOUT_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXRETRANSMIT, GlitchData => EMAC1CLIENTTXRETRANSMIT_GlitchData, OutSignalName => "EMAC1CLIENTTXRETRANSMIT", OutTemp => EMAC1CLIENTTXRETRANSMIT_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATS, GlitchData => EMAC1CLIENTTXSTATS_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATS", OutTemp => EMAC1CLIENTTXSTATS_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATSBYTEVLD, GlitchData => EMAC1CLIENTTXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATSBYTEVLD", OutTemp => EMAC1CLIENTTXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATSVLD, GlitchData => EMAC1CLIENTTXSTATSVLD_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATSVLD", OutTemp => EMAC1CLIENTTXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYENCOMMAALIGN, GlitchData => EMAC1PHYENCOMMAALIGN_GlitchData, OutSignalName => "EMAC1PHYENCOMMAALIGN", OutTemp => EMAC1PHYENCOMMAALIGN_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYLOOPBACKMSB, GlitchData => EMAC1PHYLOOPBACKMSB_GlitchData, OutSignalName => "EMAC1PHYLOOPBACKMSB", OutTemp => EMAC1PHYLOOPBACKMSB_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMCLKOUT, GlitchData => EMAC1PHYMCLKOUT_GlitchData, OutSignalName => "EMAC1PHYMCLKOUT", OutTemp => EMAC1PHYMCLKOUT_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMDOUT, GlitchData => EMAC1PHYMDOUT_GlitchData, OutSignalName => "EMAC1PHYMDOUT", OutTemp => EMAC1PHYMDOUT_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMDTRI, GlitchData => EMAC1PHYMDTRI_GlitchData, OutSignalName => "EMAC1PHYMDTRI", OutTemp => EMAC1PHYMDTRI_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMGTRXRESET, GlitchData => EMAC1PHYMGTRXRESET_GlitchData, OutSignalName => "EMAC1PHYMGTRXRESET", OutTemp => EMAC1PHYMGTRXRESET_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMGTTXRESET, GlitchData => EMAC1PHYMGTTXRESET_GlitchData, OutSignalName => "EMAC1PHYMGTTXRESET", OutTemp => EMAC1PHYMGTTXRESET_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYPOWERDOWN, GlitchData => EMAC1PHYPOWERDOWN_GlitchData, OutSignalName => "EMAC1PHYPOWERDOWN", OutTemp => EMAC1PHYPOWERDOWN_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYSYNCACQSTATUS, GlitchData => EMAC1PHYSYNCACQSTATUS_GlitchData, OutSignalName => "EMAC1PHYSYNCACQSTATUS", OutTemp => EMAC1PHYSYNCACQSTATUS_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARDISPMODE, GlitchData => EMAC1PHYTXCHARDISPMODE_GlitchData, OutSignalName => "EMAC1PHYTXCHARDISPMODE", OutTemp => EMAC1PHYTXCHARDISPMODE_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARDISPVAL, GlitchData => EMAC1PHYTXCHARDISPVAL_GlitchData, OutSignalName => "EMAC1PHYTXCHARDISPVAL", OutTemp => EMAC1PHYTXCHARDISPVAL_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARISK, GlitchData => EMAC1PHYTXCHARISK_GlitchData, OutSignalName => "EMAC1PHYTXCHARISK", OutTemp => EMAC1PHYTXCHARISK_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCLK, GlitchData => EMAC1PHYTXCLK_GlitchData, OutSignalName => "EMAC1PHYTXCLK", OutTemp => EMAC1PHYTXCLK_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(0), GlitchData => EMAC1PHYTXD0_GlitchData, OutSignalName => "EMAC1PHYTXD(0)", OutTemp => EMAC1PHYTXD_OUT(0), Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(1), GlitchData => EMAC1PHYTXD1_GlitchData, OutSignalName => "EMAC1PHYTXD(1)", OutTemp => EMAC1PHYTXD_OUT(1), Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(2), GlitchData => EMAC1PHYTXD2_GlitchData, OutSignalName => "EMAC1PHYTXD(2)", OutTemp => EMAC1PHYTXD_OUT(2), Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(3), GlitchData => EMAC1PHYTXD3_GlitchData, OutSignalName => "EMAC1PHYTXD(3)", OutTemp => EMAC1PHYTXD_OUT(3), Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(4), GlitchData => EMAC1PHYTXD4_GlitchData, OutSignalName => "EMAC1PHYTXD(4)", OutTemp => EMAC1PHYTXD_OUT(4), Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(5), GlitchData => EMAC1PHYTXD5_GlitchData, OutSignalName => "EMAC1PHYTXD(5)", OutTemp => EMAC1PHYTXD_OUT(5), Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(6), GlitchData => EMAC1PHYTXD6_GlitchData, OutSignalName => "EMAC1PHYTXD(6)", OutTemp => EMAC1PHYTXD_OUT(6), Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(7), GlitchData => EMAC1PHYTXD7_GlitchData, OutSignalName => "EMAC1PHYTXD(7)", OutTemp => EMAC1PHYTXD_OUT(7), Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXEN, GlitchData => EMAC1PHYTXEN_GlitchData, OutSignalName => "EMAC1PHYTXEN", OutTemp => EMAC1PHYTXEN_OUT, Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXER, GlitchData => EMAC1PHYTXER_GlitchData, OutSignalName => "EMAC1PHYTXER", OutTemp => EMAC1PHYTXER_OUT, Paths => (0 => (CLIENTEMAC1TXGMIIMIICLKIN_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTMIIMRDY, GlitchData => HOSTMIIMRDY_GlitchData, OutSignalName => "HOSTMIIMRDY", OutTemp => HOSTMIIMRDY_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(0), GlitchData => HOSTRDDATA0_GlitchData, OutSignalName => "HOSTRDDATA(0)", OutTemp => HOSTRDDATA_OUT(0), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(1), GlitchData => HOSTRDDATA1_GlitchData, OutSignalName => "HOSTRDDATA(1)", OutTemp => HOSTRDDATA_OUT(1), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(2), GlitchData => HOSTRDDATA2_GlitchData, OutSignalName => "HOSTRDDATA(2)", OutTemp => HOSTRDDATA_OUT(2), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(3), GlitchData => HOSTRDDATA3_GlitchData, OutSignalName => "HOSTRDDATA(3)", OutTemp => HOSTRDDATA_OUT(3), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(4), GlitchData => HOSTRDDATA4_GlitchData, OutSignalName => "HOSTRDDATA(4)", OutTemp => HOSTRDDATA_OUT(4), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(5), GlitchData => HOSTRDDATA5_GlitchData, OutSignalName => "HOSTRDDATA(5)", OutTemp => HOSTRDDATA_OUT(5), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(6), GlitchData => HOSTRDDATA6_GlitchData, OutSignalName => "HOSTRDDATA(6)", OutTemp => HOSTRDDATA_OUT(6), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(7), GlitchData => HOSTRDDATA7_GlitchData, OutSignalName => "HOSTRDDATA(7)", OutTemp => HOSTRDDATA_OUT(7), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(8), GlitchData => HOSTRDDATA8_GlitchData, OutSignalName => "HOSTRDDATA(8)", OutTemp => HOSTRDDATA_OUT(8), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(9), GlitchData => HOSTRDDATA9_GlitchData, OutSignalName => "HOSTRDDATA(9)", OutTemp => HOSTRDDATA_OUT(9), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(10), GlitchData => HOSTRDDATA10_GlitchData, OutSignalName => "HOSTRDDATA(10)", OutTemp => HOSTRDDATA_OUT(10), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(11), GlitchData => HOSTRDDATA11_GlitchData, OutSignalName => "HOSTRDDATA(11)", OutTemp => HOSTRDDATA_OUT(11), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(12), GlitchData => HOSTRDDATA12_GlitchData, OutSignalName => "HOSTRDDATA(12)", OutTemp => HOSTRDDATA_OUT(12), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(13), GlitchData => HOSTRDDATA13_GlitchData, OutSignalName => "HOSTRDDATA(13)", OutTemp => HOSTRDDATA_OUT(13), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(14), GlitchData => HOSTRDDATA14_GlitchData, OutSignalName => "HOSTRDDATA(14)", OutTemp => HOSTRDDATA_OUT(14), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(15), GlitchData => HOSTRDDATA15_GlitchData, OutSignalName => "HOSTRDDATA(15)", OutTemp => HOSTRDDATA_OUT(15), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(16), GlitchData => HOSTRDDATA16_GlitchData, OutSignalName => "HOSTRDDATA(16)", OutTemp => HOSTRDDATA_OUT(16), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(17), GlitchData => HOSTRDDATA17_GlitchData, OutSignalName => "HOSTRDDATA(17)", OutTemp => HOSTRDDATA_OUT(17), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(18), GlitchData => HOSTRDDATA18_GlitchData, OutSignalName => "HOSTRDDATA(18)", OutTemp => HOSTRDDATA_OUT(18), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(19), GlitchData => HOSTRDDATA19_GlitchData, OutSignalName => "HOSTRDDATA(19)", OutTemp => HOSTRDDATA_OUT(19), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(20), GlitchData => HOSTRDDATA20_GlitchData, OutSignalName => "HOSTRDDATA(20)", OutTemp => HOSTRDDATA_OUT(20), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(21), GlitchData => HOSTRDDATA21_GlitchData, OutSignalName => "HOSTRDDATA(21)", OutTemp => HOSTRDDATA_OUT(21), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(22), GlitchData => HOSTRDDATA22_GlitchData, OutSignalName => "HOSTRDDATA(22)", OutTemp => HOSTRDDATA_OUT(22), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(23), GlitchData => HOSTRDDATA23_GlitchData, OutSignalName => "HOSTRDDATA(23)", OutTemp => HOSTRDDATA_OUT(23), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(24), GlitchData => HOSTRDDATA24_GlitchData, OutSignalName => "HOSTRDDATA(24)", OutTemp => HOSTRDDATA_OUT(24), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(25), GlitchData => HOSTRDDATA25_GlitchData, OutSignalName => "HOSTRDDATA(25)", OutTemp => HOSTRDDATA_OUT(25), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(26), GlitchData => HOSTRDDATA26_GlitchData, OutSignalName => "HOSTRDDATA(26)", OutTemp => HOSTRDDATA_OUT(26), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(27), GlitchData => HOSTRDDATA27_GlitchData, OutSignalName => "HOSTRDDATA(27)", OutTemp => HOSTRDDATA_OUT(27), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(28), GlitchData => HOSTRDDATA28_GlitchData, OutSignalName => "HOSTRDDATA(28)", OutTemp => HOSTRDDATA_OUT(28), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(29), GlitchData => HOSTRDDATA29_GlitchData, OutSignalName => "HOSTRDDATA(29)", OutTemp => HOSTRDDATA_OUT(29), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(30), GlitchData => HOSTRDDATA30_GlitchData, OutSignalName => "HOSTRDDATA(30)", OutTemp => HOSTRDDATA_OUT(30), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(31), GlitchData => HOSTRDDATA31_GlitchData, OutSignalName => "HOSTRDDATA(31)", OutTemp => HOSTRDDATA_OUT(31), Paths => (0 => (HOSTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); -- Wait signal (input/output pins) wait on CLIENTEMAC0DCMLOCKED_ipd, CLIENTEMAC0PAUSEREQ_ipd, CLIENTEMAC0PAUSEVAL_ipd, CLIENTEMAC0RXCLIENTCLKIN_ipd, CLIENTEMAC0TXCLIENTCLKIN_ipd, CLIENTEMAC0TXD_client16_delay, CLIENTEMAC0TXDVLD_client16_delay, CLIENTEMAC0TXDVLDMSW_client16_delay, CLIENTEMAC0TXFIRSTBYTE_ipd, CLIENTEMAC0TXGMIIMIICLKIN_ipd, CLIENTEMAC0TXIFGDELAY_ipd, CLIENTEMAC0TXUNDERRUN_ipd, CLIENTEMAC1DCMLOCKED_ipd, CLIENTEMAC1PAUSEREQ_ipd, CLIENTEMAC1PAUSEVAL_ipd, CLIENTEMAC1RXCLIENTCLKIN_ipd, CLIENTEMAC1TXCLIENTCLKIN_ipd, CLIENTEMAC1TXD_client16_delay, CLIENTEMAC1TXDVLD_client16_delay, CLIENTEMAC1TXDVLDMSW_client16_delay, CLIENTEMAC1TXFIRSTBYTE_ipd, CLIENTEMAC1TXGMIIMIICLKIN_ipd, CLIENTEMAC1TXIFGDELAY_ipd, CLIENTEMAC1TXUNDERRUN_ipd, DCREMACENABLE_ipd, DCRHOSTDONEIR_OUT, EMAC0CLIENTANINTERRUPT_OUT, EMAC0CLIENTRXBADFRAME_OUT, EMAC0CLIENTRXCLIENTCLKOUT_OUT, EMAC0CLIENTRXD_OUT, EMAC0CLIENTRXDVLD_OUT, EMAC0CLIENTRXDVLDMSW_OUT, EMAC0CLIENTRXDVREG6_OUT, EMAC0CLIENTRXFRAMEDROP_OUT, EMAC0CLIENTRXGOODFRAME_OUT, EMAC0CLIENTRXSTATS_OUT, EMAC0CLIENTRXSTATSBYTEVLD_OUT, EMAC0CLIENTRXSTATSVLD_OUT, EMAC0CLIENTTXACK_OUT, EMAC0CLIENTTXCLIENTCLKOUT_OUT, EMAC0CLIENTTXCOLLISION_OUT, EMAC0CLIENTTXGMIIMIICLKOUT_OUT, EMAC0CLIENTTXRETRANSMIT_OUT, EMAC0CLIENTTXSTATS_OUT, EMAC0CLIENTTXSTATSBYTEVLD_OUT, EMAC0CLIENTTXSTATSVLD_OUT, EMAC0PHYENCOMMAALIGN_OUT, EMAC0PHYLOOPBACKMSB_OUT, EMAC0PHYMCLKOUT_OUT, EMAC0PHYMDOUT_OUT, EMAC0PHYMDTRI_OUT, EMAC0PHYMGTRXRESET_OUT, EMAC0PHYMGTTXRESET_OUT, EMAC0PHYPOWERDOWN_OUT, EMAC0PHYSYNCACQSTATUS_OUT, EMAC0PHYTXCHARDISPMODE_OUT, EMAC0PHYTXCHARDISPVAL_OUT, EMAC0PHYTXCHARISK_OUT, EMAC0PHYTXCLK_OUT, EMAC0PHYTXD_OUT, EMAC0PHYTXEN_OUT, EMAC0PHYTXER_OUT, EMAC1CLIENTANINTERRUPT_OUT, EMAC1CLIENTRXBADFRAME_OUT, EMAC1CLIENTRXCLIENTCLKOUT_OUT, EMAC1CLIENTRXD_OUT, EMAC1CLIENTRXDVLD_OUT, EMAC1CLIENTRXDVLDMSW_OUT, EMAC1CLIENTRXDVREG6_OUT, EMAC1CLIENTRXFRAMEDROP_OUT, EMAC1CLIENTRXGOODFRAME_OUT, EMAC1CLIENTRXSTATS_OUT, EMAC1CLIENTRXSTATSBYTEVLD_OUT, EMAC1CLIENTRXSTATSVLD_OUT, EMAC1CLIENTTXACK_OUT, EMAC1CLIENTTXCLIENTCLKOUT_OUT, EMAC1CLIENTTXCOLLISION_OUT, EMAC1CLIENTTXGMIIMIICLKOUT_OUT, EMAC1CLIENTTXRETRANSMIT_OUT, EMAC1CLIENTTXSTATS_OUT, EMAC1CLIENTTXSTATSBYTEVLD_OUT, EMAC1CLIENTTXSTATSVLD_OUT, EMAC1PHYENCOMMAALIGN_OUT, EMAC1PHYLOOPBACKMSB_OUT, EMAC1PHYMCLKOUT_OUT, EMAC1PHYMDOUT_OUT, EMAC1PHYMDTRI_OUT, EMAC1PHYMGTRXRESET_OUT, EMAC1PHYMGTTXRESET_OUT, EMAC1PHYPOWERDOWN_OUT, EMAC1PHYSYNCACQSTATUS_OUT, EMAC1PHYTXCHARDISPMODE_OUT, EMAC1PHYTXCHARDISPVAL_OUT, EMAC1PHYTXCHARISK_OUT, EMAC1PHYTXCLK_OUT, EMAC1PHYTXD_OUT, EMAC1PHYTXEN_OUT, EMAC1PHYTXER_OUT, HOSTADDR_ipd, HOSTCLK_ipd, HOSTEMAC1SEL_ipd, HOSTMIIMRDY_OUT, HOSTMIIMSEL_ipd, HOSTOPCODE_ipd, HOSTRDDATA_OUT, HOSTREQ_ipd, HOSTWRDATA_ipd, PHYEMAC0COL_ipd, PHYEMAC0CRS_ipd, PHYEMAC0GTXCLK_ipd, PHYEMAC0MCLKIN_ipd, PHYEMAC0MDIN_ipd, PHYEMAC0MIITXCLK_skewed, PHYEMAC0PHYAD_ipd, PHYEMAC0RXBUFERR_ipd, PHYEMAC0RXBUFSTATUS_ipd, PHYEMAC0RXCHARISCOMMA_ipd, PHYEMAC0RXCHARISK_ipd, PHYEMAC0RXCHECKINGCRC_ipd, PHYEMAC0RXCLK_ipd, PHYEMAC0RXCLKCORCNT_ipd, PHYEMAC0RXCOMMADET_ipd, PHYEMAC0RXD_ipd, PHYEMAC0RXDISPERR_ipd, PHYEMAC0RXDV_ipd, PHYEMAC0RXER_ipd, PHYEMAC0RXLOSSOFSYNC_ipd, PHYEMAC0RXNOTINTABLE_ipd, PHYEMAC0RXRUNDISP_ipd, PHYEMAC0SIGNALDET_ipd, PHYEMAC0TXBUFERR_ipd, PHYEMAC1COL_ipd, PHYEMAC1CRS_ipd, PHYEMAC1GTXCLK_ipd, PHYEMAC1MCLKIN_ipd, PHYEMAC1MDIN_ipd, PHYEMAC1MIITXCLK_skewed, PHYEMAC1PHYAD_ipd, PHYEMAC1RXBUFERR_ipd, PHYEMAC1RXBUFSTATUS_ipd, PHYEMAC1RXCHARISCOMMA_ipd, PHYEMAC1RXCHARISK_ipd, PHYEMAC1RXCHECKINGCRC_ipd, PHYEMAC1RXCLK_ipd, PHYEMAC1RXCLKCORCNT_ipd, PHYEMAC1RXCOMMADET_ipd, PHYEMAC1RXD_ipd, PHYEMAC1RXDISPERR_ipd, PHYEMAC1RXDV_ipd, PHYEMAC1RXER_ipd, PHYEMAC1RXLOSSOFSYNC_ipd, PHYEMAC1RXNOTINTABLE_ipd, PHYEMAC1RXRUNDISP_ipd, PHYEMAC1SIGNALDET_ipd, PHYEMAC1TXBUFERR_ipd, RESET_ipd, TIEEMAC0CONFIGVEC_ipd, TIEEMAC0UNICASTADDR_ipd, TIEEMAC1CONFIGVEC_ipd, TIEEMAC1UNICASTADDR_ipd, DCREMACWRITE_ipd, DCREMACREAD_ipd, DCREMACDBUS_ipd, DCREMACABUS_ipd, DCREMACCLK_ipd, EMACDCRDBUS_OUT, EMACDCRACK_OUT; end process TIMING; end EMAC_V; ----- CELL GT11_CUSTOM ----- ------------------------------------------------------------------------------- -- Copyright (c) 1995-2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 11-Gigabit Transceiver for High-Speed I/O CUSTOM Simulation Model -- /___/ /\ Filename : GT11_CUSTOM.vhd -- \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. -- 05/16/05 - Changed default values for some parameters and removed two parameters. Fixed CR#207101. -- 08/08/05 - Changed default parameter values for some parameters (CR 214282). -- 02/28/06 - CR#226322 - Addition of new parameters and change of default values for some parameters. -- End Revision library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; entity GT11_CUSTOM is generic ( ALIGN_COMMA_WORD : integer := 4; BANDGAPSEL : boolean := FALSE; BIASRESSEL : boolean := FALSE; CCCB_ARBITRATOR_DISABLE : boolean := FALSE; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "NONE"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_MASK : bit_vector := "1110"; CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "1110"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 1; CLK_CORRECT_USE : boolean := FALSE; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 48; CLK_COR_MIN_LAT : integer := 36; CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; CLK_COR_SEQ_1_MASK : bit_vector := "1110"; CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; CLK_COR_SEQ_2_MASK : bit_vector := "1110"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 1; COMMA32 : boolean := FALSE; COMMA_10B_MASK : bit_vector := X"3FF"; CYCLE_LIMIT_SEL : bit_vector := "00"; DCDR_FILTER : bit_vector := "010"; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; DIGRX_FWDCLK : bit_vector := "00"; DIGRX_SYNC_MODE : boolean := FALSE; ENABLE_DCDR : boolean := FALSE; FDET_HYS_CAL : bit_vector := "010"; FDET_HYS_SEL : bit_vector := "100"; FDET_LCK_CAL : bit_vector := "100"; FDET_LCK_SEL : bit_vector := "001"; IREFBIASMODE : bit_vector := "11"; LOOPCAL_WAIT : bit_vector := "00"; MCOMMA_32B_VALUE : bit_vector := X"00000000"; MCOMMA_DETECT : boolean := TRUE; OPPOSITE_SELECT : boolean := FALSE; PCOMMA_32B_VALUE : bit_vector := X"00000000"; PCOMMA_DETECT : boolean := TRUE; PCS_BIT_SLIP : boolean := FALSE; PMACLKENABLE : boolean := TRUE; PMACOREPWRENABLE : boolean := TRUE; PMAIREFTRIM : bit_vector := "0111"; PMAVBGCTRL : bit_vector := "00000"; PMAVREFTRIM : bit_vector := "0111"; PMA_BIT_SLIP : boolean := FALSE; POWER_ENABLE : boolean := TRUE; REPEATER : boolean := FALSE; RXACTST : boolean := FALSE; RXAFEEQ : bit_vector := "000000000"; RXAFEPD : boolean := FALSE; RXAFETST : boolean := FALSE; RXAPD : boolean := FALSE; RXAREGCTRL : bit_vector := "00000"; RXASYNCDIVIDE : bit_vector := "11"; RXBY_32 : boolean := FALSE; RXCDRLOS : bit_vector := "000000"; RXCLK0_FORCE_PMACLK : boolean := FALSE; RXCLKMODE : bit_vector := "110001"; RXCLMODE : bit_vector := "00"; RXCMADJ : bit_vector := "01"; RXCPSEL : boolean := TRUE; RXCPTST : boolean := FALSE; RXCRCCLOCKDOUBLE : boolean := FALSE; RXCRCENABLE : boolean := FALSE; RXCRCINITVAL : bit_vector := X"00000000"; RXCRCINVERTGEN : boolean := FALSE; RXCRCSAMECLOCK : boolean := FALSE; RXCTRL1 : bit_vector := X"200"; RXCYCLE_LIMIT_SEL : bit_vector := "00"; RXDATA_SEL : bit_vector := "00"; RXDCCOUPLE : boolean := FALSE; RXDIGRESET : boolean := FALSE; RXDIGRX : boolean := FALSE; RXEQ : bit_vector := X"4000000000000000"; RXFDCAL_CLOCK_DIVIDE : string := "NONE"; RXFDET_HYS_CAL : bit_vector := "010"; RXFDET_HYS_SEL : bit_vector := "100"; RXFDET_LCK_CAL : bit_vector := "100"; RXFDET_LCK_SEL : bit_vector := "001"; RXFECONTROL1 : bit_vector := "00"; RXFECONTROL2 : bit_vector := "000"; RXFETUNE : bit_vector := "01"; RXLB : boolean := FALSE; RXLKADJ : bit_vector := "00000"; RXLKAPD : boolean := FALSE; RXLOOPCAL_WAIT : bit_vector := "00"; RXLOOPFILT : bit_vector := "0111"; RXMODE : bit_vector := "000000"; RXOUTDIV2SEL : integer := 1; RXPD : boolean := FALSE; RXPDDTST : boolean := TRUE; RXPLLNDIVSEL : integer := 8; RXPMACLKSEL : string := "REFCLK1"; RXRCPADJ : bit_vector := "011"; RXRCPPD : boolean := FALSE; RXRECCLK1_USE_SYNC : boolean := FALSE; RXRIBADJ : bit_vector := "11"; RXRPDPD : boolean := FALSE; RXRSDPD : boolean := FALSE; RXSLOWDOWN_CAL : bit_vector := "00"; RXTUNE : bit_vector := X"0000"; RXUSRDIVISOR : integer := 1; RXVCODAC_INIT : bit_vector := "1010000000"; RXVCO_CTRL_ENABLE : boolean := FALSE; RX_BUFFER_USE : boolean := TRUE; RX_CLOCK_DIVIDER : bit_vector := "00"; SAMPLE_8X : boolean := FALSE; SH_CNT_MAX : integer := 64; SH_INVALID_CNT_MAX : integer := 16; SLOWDOWN_CAL : bit_vector := "00"; TXABPMACLKSEL : string := "REFCLK1"; TXAPD : boolean := FALSE; TXAREFBIASSEL : boolean := TRUE; TXASYNCDIVIDE : bit_vector := "11"; TXCLK0_FORCE_PMACLK : boolean := FALSE; TXCLKMODE : bit_vector := "1001"; TXCLMODE : bit_vector := "00"; TXCPSEL : boolean := TRUE; TXCRCCLOCKDOUBLE : boolean := FALSE; TXCRCENABLE : boolean := FALSE; TXCRCINITVAL : bit_vector := X"00000000"; TXCRCINVERTGEN : boolean := FALSE; TXCRCSAMECLOCK : boolean := FALSE; TXCTRL1 : bit_vector := X"200"; TXDATA_SEL : bit_vector := "00"; TXDAT_PRDRV_DAC : bit_vector := "111"; TXDAT_TAP_DAC : bit_vector := "10110"; TXDIGPD : boolean := FALSE; TXFDCAL_CLOCK_DIVIDE : string := "NONE"; TXHIGHSIGNALEN : boolean := TRUE; TXLOOPFILT : bit_vector := "0111"; TXLVLSHFTPD : boolean := FALSE; TXOUTCLK1_USE_SYNC : boolean := FALSE; TXOUTDIV2SEL : integer := 1; TXPD : boolean := FALSE; TXPHASESEL : boolean := FALSE; TXPLLNDIVSEL : integer := 8; TXPOST_PRDRV_DAC : bit_vector := "111"; TXPOST_TAP_DAC : bit_vector := "01110"; TXPOST_TAP_PD : boolean := TRUE; TXPRE_PRDRV_DAC : bit_vector := "111"; TXPRE_TAP_DAC : bit_vector := "00000"; TXPRE_TAP_PD : boolean := TRUE; TXSLEWRATE : boolean := FALSE; TXTERMTRIM : bit_vector := "1100"; TXTUNE : bit_vector := X"0000"; TX_BUFFER_USE : boolean := TRUE; TX_CLOCK_DIVIDER : bit_vector := "00"; VCODAC_INIT : bit_vector := "1010000000"; VCO_CTRL_ENABLE : boolean := FALSE; VREFBIASMODE : bit_vector := "11" ); port ( CHBONDO : out std_logic_vector(4 downto 0); DO : out std_logic_vector(15 downto 0); DRDY : out std_ulogic; RXBUFERR : out std_ulogic; RXCALFAIL : out std_ulogic; RXCHARISCOMMA : out std_logic_vector(7 downto 0); RXCHARISK : out std_logic_vector(7 downto 0); RXCOMMADET : out std_ulogic; RXCRCOUT : out std_logic_vector(31 downto 0); RXCYCLELIMIT : out std_ulogic; RXDATA : out std_logic_vector(63 downto 0); RXDISPERR : out std_logic_vector(7 downto 0); RXLOCK : out std_ulogic; RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXMCLK : out std_ulogic; RXNOTINTABLE : out std_logic_vector(7 downto 0); RXPCSHCLKOUT : out std_ulogic; RXREALIGN : out std_ulogic; RXRECCLK1 : out std_ulogic; RXRECCLK2 : out std_ulogic; RXRUNDISP : out std_logic_vector(7 downto 0); RXSIGDET : out std_ulogic; RXSTATUS : out std_logic_vector(5 downto 0); TX1N : out std_ulogic; TX1P : out std_ulogic; TXBUFERR : out std_ulogic; TXCALFAIL : out std_ulogic; TXCRCOUT : out std_logic_vector(31 downto 0); TXCYCLELIMIT : out std_ulogic; TXKERR : out std_logic_vector(7 downto 0); TXLOCK : out std_ulogic; TXOUTCLK1 : out std_ulogic; TXOUTCLK2 : out std_ulogic; TXPCSHCLKOUT : out std_ulogic; TXRUNDISP : out std_logic_vector(7 downto 0); CHBONDI : in std_logic_vector(4 downto 0); DADDR : in std_logic_vector(7 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; GREFCLK : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK1 : in std_ulogic; REFCLK2 : in std_ulogic; RX1N : in std_ulogic; RX1P : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCLKSTABLE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXCRCCLK : in std_ulogic; RXCRCDATAVALID : in std_ulogic; RXCRCDATAWIDTH : in std_logic_vector(2 downto 0); RXCRCIN : in std_logic_vector(63 downto 0); RXCRCINIT : in std_ulogic; RXCRCINTCLK : in std_ulogic; RXCRCPD : in std_ulogic; RXCRCRESET : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXPMARESET : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXSYNC : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(7 downto 0); TXCHARDISPMODE : in std_logic_vector(7 downto 0); TXCHARDISPVAL : in std_logic_vector(7 downto 0); TXCHARISK : in std_logic_vector(7 downto 0); TXCLKSTABLE : in std_ulogic; TXCRCCLK : in std_ulogic; TXCRCDATAVALID : in std_ulogic; TXCRCDATAWIDTH : in std_logic_vector(2 downto 0); TXCRCIN : in std_logic_vector(63 downto 0); TXCRCINIT : in std_ulogic; TXCRCINTCLK : in std_ulogic; TXCRCPD : in std_ulogic; TXCRCRESET : in std_ulogic; TXDATA : in std_logic_vector(63 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXENOOB : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPMARESET : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXSYNC : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT11_CUSTOM; -- Architecture body -- architecture GT11_CUSTOM_V of GT11_CUSTOM is signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; signal OPEN16 : std_logic_vector(15 downto 0); begin -- GT11 Instatiation (port map, generic map) GT11_inst : GT11 generic map ( GT11_MODE => "SINGLE", CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1, CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2, CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3, CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4, CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT, CHAN_BOND_MODE => CHAN_BOND_MODE, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN, RX_BUFFER_USE => RX_BUFFER_USE, TX_BUFFER_USE => TX_BUFFER_USE, CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1, CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2, CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3, CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4, CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK, POWER_ENABLE => POWER_ENABLE, OPPOSITE_SELECT => OPPOSITE_SELECT, CCCB_ARBITRATOR_DISABLE => CCCB_ARBITRATOR_DISABLE, CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1, CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2, CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3, CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4, CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK, DIGRX_SYNC_MODE => DIGRX_SYNC_MODE, DIGRX_FWDCLK => DIGRX_FWDCLK, PCS_BIT_SLIP => PCS_BIT_SLIP, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT, TXDATA_SEL => TXDATA_SEL, RXDATA_SEL => RXDATA_SEL, CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1, CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2, CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3, CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4, CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN, CLK_CORRECT_USE => CLK_CORRECT_USE, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE, SH_CNT_MAX => SH_CNT_MAX, SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX, ALIGN_COMMA_WORD => ALIGN_COMMA_WORD, DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY, MCOMMA_DETECT => MCOMMA_DETECT, PCOMMA_DETECT => PCOMMA_DETECT, COMMA32 => COMMA32, COMMA_10B_MASK => COMMA_10B_MASK, MCOMMA_32B_VALUE => MCOMMA_32B_VALUE, PCOMMA_32B_VALUE => PCOMMA_32B_VALUE, RXUSRDIVISOR => RXUSRDIVISOR, DCDR_FILTER => DCDR_FILTER, SAMPLE_8X => SAMPLE_8X, ENABLE_DCDR => ENABLE_DCDR, REPEATER => REPEATER, RXBY_32 => RXBY_32, TXFDCAL_CLOCK_DIVIDE => TXFDCAL_CLOCK_DIVIDE, RXFDCAL_CLOCK_DIVIDE => RXFDCAL_CLOCK_DIVIDE, RXCYCLE_LIMIT_SEL => RXCYCLE_LIMIT_SEL, RXVCO_CTRL_ENABLE => RXVCO_CTRL_ENABLE, RXFDET_LCK_SEL => RXFDET_LCK_SEL, RXFDET_HYS_SEL => RXFDET_HYS_SEL, RXFDET_LCK_CAL => RXFDET_LCK_CAL, RXFDET_HYS_CAL => RXFDET_HYS_CAL, RXLOOPCAL_WAIT => RXLOOPCAL_WAIT, RXSLOWDOWN_CAL => RXSLOWDOWN_CAL, RXVCODAC_INIT => RXVCODAC_INIT, CYCLE_LIMIT_SEL => CYCLE_LIMIT_SEL, VCO_CTRL_ENABLE => VCO_CTRL_ENABLE, FDET_LCK_SEL => FDET_LCK_SEL, FDET_HYS_SEL => FDET_HYS_SEL, FDET_LCK_CAL => FDET_LCK_CAL, FDET_HYS_CAL => FDET_HYS_CAL, LOOPCAL_WAIT => LOOPCAL_WAIT, SLOWDOWN_CAL => SLOWDOWN_CAL, VCODAC_INIT => VCODAC_INIT, RXCRCCLOCKDOUBLE => RXCRCCLOCKDOUBLE, RXCRCINVERTGEN => RXCRCINVERTGEN, RXCRCSAMECLOCK => RXCRCSAMECLOCK, RXCRCENABLE => RXCRCENABLE, RXCRCINITVAL => RXCRCINITVAL, TXCRCCLOCKDOUBLE => TXCRCCLOCKDOUBLE, TXCRCINVERTGEN => TXCRCINVERTGEN, TXCRCSAMECLOCK => TXCRCSAMECLOCK, TXCRCINITVAL => TXCRCINITVAL, TXCRCENABLE => TXCRCENABLE, RX_CLOCK_DIVIDER => RX_CLOCK_DIVIDER, TX_CLOCK_DIVIDER => TX_CLOCK_DIVIDER, RXCLK0_FORCE_PMACLK => RXCLK0_FORCE_PMACLK, TXCLK0_FORCE_PMACLK => TXCLK0_FORCE_PMACLK, TXOUTCLK1_USE_SYNC => TXOUTCLK1_USE_SYNC, RXRECCLK1_USE_SYNC => RXRECCLK1_USE_SYNC, RXPMACLKSEL => RXPMACLKSEL, TXABPMACLKSEL => TXABPMACLKSEL, RXAREGCTRL => RXAREGCTRL, PMAVBGCTRL => PMAVBGCTRL, BANDGAPSEL => BANDGAPSEL, PMAIREFTRIM => PMAIREFTRIM, IREFBIASMODE => IREFBIASMODE, BIASRESSEL => BIASRESSEL, PMAVREFTRIM => PMAVREFTRIM, VREFBIASMODE => VREFBIASMODE, TXPHASESEL => TXPHASESEL, PMACLKENABLE => PMACLKENABLE, PMACOREPWRENABLE => PMACOREPWRENABLE, RXMODE => RXMODE, PMA_BIT_SLIP => PMA_BIT_SLIP, RXASYNCDIVIDE => RXASYNCDIVIDE, RXCLKMODE => RXCLKMODE, RXLB => RXLB, RXFETUNE => RXFETUNE, RXRCPADJ => RXRCPADJ, RXRIBADJ => RXRIBADJ, RXAFEEQ => RXAFEEQ, RXCMADJ => RXCMADJ, RXCDRLOS => RXCDRLOS, RXDCCOUPLE => RXDCCOUPLE, RXLKADJ => RXLKADJ, RXDIGRESET => RXDIGRESET, RXFECONTROL2 => RXFECONTROL2, RXCPTST => RXCPTST, RXPDDTST => RXPDDTST, RXACTST => RXACTST, RXAFETST => RXAFETST, RXFECONTROL1 => RXFECONTROL1, RXLKAPD => RXLKAPD, RXRSDPD => RXRSDPD, RXRCPPD => RXRCPPD, RXRPDPD => RXRPDPD, RXAFEPD => RXAFEPD, RXPD => RXPD, RXEQ => RXEQ, TXOUTDIV2SEL => TXOUTDIV2SEL, TXPLLNDIVSEL => TXPLLNDIVSEL, TXCLMODE => TXCLMODE, TXLOOPFILT => TXLOOPFILT, TXTUNE => TXTUNE, TXCPSEL => TXCPSEL, TXCTRL1 => TXCTRL1, TXAPD => TXAPD, TXLVLSHFTPD => TXLVLSHFTPD, TXPRE_PRDRV_DAC => TXPRE_PRDRV_DAC, TXPRE_TAP_PD => TXPRE_TAP_PD, TXPRE_TAP_DAC => TXPRE_TAP_DAC, TXDIGPD => TXDIGPD, TXCLKMODE => TXCLKMODE, TXHIGHSIGNALEN => TXHIGHSIGNALEN, TXAREFBIASSEL => TXAREFBIASSEL, TXTERMTRIM => TXTERMTRIM, TXASYNCDIVIDE => TXASYNCDIVIDE, TXSLEWRATE => TXSLEWRATE, TXPOST_PRDRV_DAC => TXPOST_PRDRV_DAC, TXDAT_PRDRV_DAC => TXDAT_PRDRV_DAC, TXPOST_TAP_PD => TXPOST_TAP_PD, TXPOST_TAP_DAC => TXPOST_TAP_DAC, TXDAT_TAP_DAC => TXDAT_TAP_DAC, TXPD => TXPD, RXOUTDIV2SEL => RXOUTDIV2SEL, RXPLLNDIVSEL => RXPLLNDIVSEL, RXCLMODE => RXCLMODE, RXLOOPFILT => RXLOOPFILT, RXDIGRX => RXDIGRX, RXTUNE => RXTUNE, RXCPSEL => RXCPSEL, RXCTRL1 => RXCTRL1, RXAPD => RXAPD ) port map ( COMBUSIN => z16, COMBUSOUT => OPEN16, CHBONDO => CHBONDO, RXSTATUS => RXSTATUS, RXCHARISCOMMA => RXCHARISCOMMA, RXCHARISK => RXCHARISK, RXCOMMADET => RXCOMMADET, RXDATA => RXDATA, RXDISPERR => RXDISPERR, RXLOSSOFSYNC => RXLOSSOFSYNC, RXNOTINTABLE => RXNOTINTABLE, RXREALIGN => RXREALIGN, RXRUNDISP => RXRUNDISP, RXBUFERR => RXBUFERR, TXBUFERR => TXBUFERR, TXKERR => TXKERR, TXRUNDISP => TXRUNDISP, RXRECCLK1 => RXRECCLK1, RXRECCLK2 => RXRECCLK2, TXOUTCLK1 => TXOUTCLK1, TXOUTCLK2 => TXOUTCLK2, RXLOCK => RXLOCK, TXLOCK => TXLOCK, RXCYCLELIMIT => RXCYCLELIMIT, TXCYCLELIMIT => TXCYCLELIMIT, RXCALFAIL => RXCALFAIL, TXCALFAIL => TXCALFAIL, RXCRCOUT => RXCRCOUT, TXCRCOUT => TXCRCOUT, RXSIGDET => RXSIGDET, DRDY => DRDY, DO => DO, CHBONDI => CHBONDI, ENCHANSYNC => ENCHANSYNC, ENMCOMMAALIGN => ENMCOMMAALIGN, ENPCOMMAALIGN => ENPCOMMAALIGN, LOOPBACK => LOOPBACK, POWERDOWN => POWERDOWN, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE, RXCOMMADETUSE => RXCOMMADETUSE, RXDATAWIDTH => RXDATAWIDTH, RXDEC64B66BUSE => RXDEC64B66BUSE, RXDEC8B10BUSE => RXDEC8B10BUSE, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE, RXIGNOREBTF => RXIGNOREBTF, RXINTDATAWIDTH => RXINTDATAWIDTH, RXPOLARITY => RXPOLARITY, RXRESET => RXRESET, RXSLIDE => RXSLIDE, RXUSRCLK => RXUSRCLK, RXUSRCLK2 => RXUSRCLK2, TXBYPASS8B10B => TXBYPASS8B10B, TXCHARDISPMODE => TXCHARDISPMODE, TXCHARDISPVAL => TXCHARDISPVAL, TXCHARISK => TXCHARISK, TXDATA => TXDATA, TXDATAWIDTH => TXDATAWIDTH, TXENC64B66BUSE => TXENC64B66BUSE, TXENC8B10BUSE => TXENC8B10BUSE, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE, TXINHIBIT => TXINHIBIT, TXINTDATAWIDTH => TXINTDATAWIDTH, TXPOLARITY => TXPOLARITY, TXRESET => TXRESET, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE, TXUSRCLK => TXUSRCLK, TXUSRCLK2 => TXUSRCLK2, RXCLKSTABLE => RXCLKSTABLE, RXPMARESET => RXPMARESET, TXCLKSTABLE => TXCLKSTABLE, TXPMARESET => TXPMARESET, RXCRCIN => RXCRCIN, RXCRCDATAWIDTH => RXCRCDATAWIDTH, RXCRCDATAVALID => RXCRCDATAVALID, RXCRCINIT => RXCRCINIT, RXCRCRESET => RXCRCRESET, RXCRCPD => RXCRCPD, RXCRCCLK => RXCRCCLK, RXCRCINTCLK => RXCRCINTCLK, TXCRCIN => TXCRCIN, TXCRCDATAWIDTH => TXCRCDATAWIDTH, TXCRCDATAVALID => TXCRCDATAVALID, TXCRCINIT => TXCRCINIT, TXCRCRESET => TXCRCRESET, TXCRCPD => TXCRCPD, TXCRCCLK => TXCRCCLK, TXCRCINTCLK => TXCRCINTCLK, TXSYNC => TXSYNC, RXSYNC => RXSYNC, TXENOOB => TXENOOB, DCLK => DCLK, DADDR => DADDR, DEN => DEN, DWE => DWE, DI => DI, RXMCLK => RXMCLK, TX1P => TX1P, TX1N => TX1N, RX1P => RX1P, RX1N => RX1N, GREFCLK => GREFCLK, REFCLK1 => REFCLK1, REFCLK2 => REFCLK2, TXPCSHCLKOUT => TXPCSHCLKOUT, RXPCSHCLKOUT => RXPCSHCLKOUT ); end GT11_CUSTOM_V; ----- CELL GT11_DUAL ----- ------------------------------------------------------------------------------- -- Copyright (c) 1995-2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 11-Gigabit Transceiver for High-Speed I/O DUAL Simulation Model -- /___/ /\ Filename : GT11_DUAL.vhd -- \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. -- 05/16/05 - Changed default values for some parameters and removed two parameters. Fixed CR#207101. -- 09/06/05 - Fixed CR#215006. Attribute default values update. -- 02/28/06 - CR#226322 - Addition of new parameters and change of default values for some parameters. -- End Revision library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; entity GT11_DUAL is generic ( ALIGN_COMMA_WORD_A : integer := 4; ALIGN_COMMA_WORD_B : integer := 4; BANDGAPSEL_A : boolean := FALSE; BANDGAPSEL_B : boolean := FALSE; BIASRESSEL_A : boolean := FALSE; BIASRESSEL_B : boolean := FALSE; CCCB_ARBITRATOR_DISABLE_A : boolean := FALSE; CCCB_ARBITRATOR_DISABLE_B : boolean := FALSE; CHAN_BOND_LIMIT_A : integer := 16; CHAN_BOND_LIMIT_B : integer := 16; CHAN_BOND_MODE_A : string := "NONE"; CHAN_BOND_MODE_B : string := "NONE"; CHAN_BOND_ONE_SHOT_A : boolean := FALSE; CHAN_BOND_ONE_SHOT_B : boolean := FALSE; CHAN_BOND_SEQ_1_1_A : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_1_B : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_2_A : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_2_B : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_3_A : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_3_B : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_4_A : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_4_B : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_MASK_A : bit_vector := "1110"; CHAN_BOND_SEQ_1_MASK_B : bit_vector := "1110"; CHAN_BOND_SEQ_2_1_A : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_1_B : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_2_A : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_2_B : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_3_A : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_3_B : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_4_A : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_4_B : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_MASK_A : bit_vector := "1110"; CHAN_BOND_SEQ_2_MASK_B : bit_vector := "1110"; CHAN_BOND_SEQ_2_USE_A : boolean := FALSE; CHAN_BOND_SEQ_2_USE_B : boolean := FALSE; CHAN_BOND_SEQ_LEN_A : integer := 1; CHAN_BOND_SEQ_LEN_B : integer := 1; CLK_CORRECT_USE_A : boolean := FALSE; CLK_CORRECT_USE_B : boolean := FALSE; CLK_COR_8B10B_DE_A : boolean := FALSE; CLK_COR_8B10B_DE_B : boolean := FALSE; CLK_COR_MAX_LAT_A : integer := 48; CLK_COR_MAX_LAT_B : integer := 48; CLK_COR_MIN_LAT_A : integer := 36; CLK_COR_MIN_LAT_B : integer := 36; CLK_COR_SEQ_1_1_A : bit_vector := "00000000000"; CLK_COR_SEQ_1_1_B : bit_vector := "00000000000"; CLK_COR_SEQ_1_2_A : bit_vector := "00000000000"; CLK_COR_SEQ_1_2_B : bit_vector := "00000000000"; CLK_COR_SEQ_1_3_A : bit_vector := "00000000000"; CLK_COR_SEQ_1_3_B : bit_vector := "00000000000"; CLK_COR_SEQ_1_4_A : bit_vector := "00000000000"; CLK_COR_SEQ_1_4_B : bit_vector := "00000000000"; CLK_COR_SEQ_1_MASK_A : bit_vector := "1110"; CLK_COR_SEQ_1_MASK_B : bit_vector := "1110"; CLK_COR_SEQ_2_1_A : bit_vector := "00000000000"; CLK_COR_SEQ_2_1_B : bit_vector := "00000000000"; CLK_COR_SEQ_2_2_A : bit_vector := "00000000000"; CLK_COR_SEQ_2_2_B : bit_vector := "00000000000"; CLK_COR_SEQ_2_3_A : bit_vector := "00000000000"; CLK_COR_SEQ_2_3_B : bit_vector := "00000000000"; CLK_COR_SEQ_2_4_A : bit_vector := "00000000000"; CLK_COR_SEQ_2_4_B : bit_vector := "00000000000"; CLK_COR_SEQ_2_MASK_A : bit_vector := "1110"; CLK_COR_SEQ_2_MASK_B : bit_vector := "1110"; CLK_COR_SEQ_2_USE_A : boolean := FALSE; CLK_COR_SEQ_2_USE_B : boolean := FALSE; CLK_COR_SEQ_DROP_A : boolean := FALSE; CLK_COR_SEQ_DROP_B : boolean := FALSE; CLK_COR_SEQ_LEN_A : integer := 1; CLK_COR_SEQ_LEN_B : integer := 1; COMMA32_A : boolean := FALSE; COMMA32_B : boolean := FALSE; COMMA_10B_MASK_A : bit_vector := X"3FF"; COMMA_10B_MASK_B : bit_vector := X"3FF"; CYCLE_LIMIT_SEL_A : bit_vector := "00"; CYCLE_LIMIT_SEL_B : bit_vector := "00"; DCDR_FILTER_A : bit_vector := "010"; DCDR_FILTER_B : bit_vector := "010"; DEC_MCOMMA_DETECT_A : boolean := TRUE; DEC_MCOMMA_DETECT_B : boolean := TRUE; DEC_PCOMMA_DETECT_A : boolean := TRUE; DEC_PCOMMA_DETECT_B : boolean := TRUE; DEC_VALID_COMMA_ONLY_A : boolean := TRUE; DEC_VALID_COMMA_ONLY_B : boolean := TRUE; DIGRX_FWDCLK_A : bit_vector := "00"; DIGRX_FWDCLK_B : bit_vector := "00"; DIGRX_SYNC_MODE_A : boolean := FALSE; DIGRX_SYNC_MODE_B : boolean := FALSE; ENABLE_DCDR_A : boolean := FALSE; ENABLE_DCDR_B : boolean := FALSE; FDET_HYS_CAL_A : bit_vector := "010"; FDET_HYS_CAL_B : bit_vector := "010"; FDET_HYS_SEL_A : bit_vector := "100"; FDET_HYS_SEL_B : bit_vector := "100"; FDET_LCK_CAL_A : bit_vector := "100"; FDET_LCK_CAL_B : bit_vector := "100"; FDET_LCK_SEL_A : bit_vector := "001"; FDET_LCK_SEL_B : bit_vector := "001"; IREFBIASMODE_A : bit_vector := "11"; IREFBIASMODE_B : bit_vector := "11"; LOOPCAL_WAIT_A : bit_vector := "00"; LOOPCAL_WAIT_B : bit_vector := "00"; MCOMMA_32B_VALUE_A : bit_vector := X"00000000"; MCOMMA_32B_VALUE_B : bit_vector := X"00000000"; MCOMMA_DETECT_A : boolean := TRUE; MCOMMA_DETECT_B : boolean := TRUE; OPPOSITE_SELECT_A : boolean := FALSE; OPPOSITE_SELECT_B : boolean := FALSE; PCOMMA_32B_VALUE_A : bit_vector := X"00000000"; PCOMMA_32B_VALUE_B : bit_vector := X"00000000"; PCOMMA_DETECT_A : boolean := TRUE; PCOMMA_DETECT_B : boolean := TRUE; PCS_BIT_SLIP_A : boolean := FALSE; PCS_BIT_SLIP_B : boolean := FALSE; PMACLKENABLE_A : boolean := TRUE; PMACLKENABLE_B : boolean := TRUE; PMACOREPWRENABLE_A : boolean := TRUE; PMACOREPWRENABLE_B : boolean := TRUE; PMAIREFTRIM_A : bit_vector := "0111"; PMAIREFTRIM_B : bit_vector := "0111"; PMAVBGCTRL_A : bit_vector := "00000"; PMAVBGCTRL_B : bit_vector := "00000"; PMAVREFTRIM_A : bit_vector := "0111"; PMAVREFTRIM_B : bit_vector := "0111"; PMA_BIT_SLIP_A : boolean := FALSE; PMA_BIT_SLIP_B : boolean := FALSE; POWER_ENABLE_A : boolean := TRUE; POWER_ENABLE_B : boolean := TRUE; REPEATER_A : boolean := FALSE; REPEATER_B : boolean := FALSE; RXACTST_A : boolean := FALSE; RXACTST_B : boolean := FALSE; RXAFEEQ_A : bit_vector := "000000000"; RXAFEEQ_B : bit_vector := "000000000"; RXAFEPD_A : boolean := FALSE; RXAFEPD_B : boolean := FALSE; RXAFETST_A : boolean := FALSE; RXAFETST_B : boolean := FALSE; RXAPD_A : boolean := FALSE; RXAPD_B : boolean := FALSE; RXAREGCTRL_A : bit_vector := "00000"; RXAREGCTRL_B : bit_vector := "00000"; RXASYNCDIVIDE_A : bit_vector := "11"; RXASYNCDIVIDE_B : bit_vector := "11"; RXBY_32_A : boolean := FALSE; RXBY_32_B : boolean := FALSE; RXCDRLOS_A : bit_vector := "000000"; RXCDRLOS_B : bit_vector := "000000"; RXCLK0_FORCE_PMACLK_A : boolean := FALSE; RXCLK0_FORCE_PMACLK_B : boolean := FALSE; RXCLKMODE_A : bit_vector := "110001"; RXCLKMODE_B : bit_vector := "110001"; RXCLMODE_A : bit_vector := "00"; RXCLMODE_B : bit_vector := "00"; RXCMADJ_A : bit_vector := "01"; RXCMADJ_B : bit_vector := "01"; RXCPSEL_A : boolean := TRUE; RXCPSEL_B : boolean := TRUE; RXCPTST_A : boolean := FALSE; RXCPTST_B : boolean := FALSE; RXCRCCLOCKDOUBLE_A : boolean := FALSE; RXCRCCLOCKDOUBLE_B : boolean := FALSE; RXCRCENABLE_A : boolean := FALSE; RXCRCENABLE_B : boolean := FALSE; RXCRCINITVAL_A : bit_vector := X"00000000"; RXCRCINITVAL_B : bit_vector := X"00000000"; RXCRCINVERTGEN_A : boolean := FALSE; RXCRCINVERTGEN_B : boolean := FALSE; RXCRCSAMECLOCK_A : boolean := FALSE; RXCRCSAMECLOCK_B : boolean := FALSE; RXCTRL1_A : bit_vector := X"200"; RXCTRL1_B : bit_vector := X"200"; RXCYCLE_LIMIT_SEL_A : bit_vector := "00"; RXCYCLE_LIMIT_SEL_B : bit_vector := "00"; RXDATA_SEL_A : bit_vector := "00"; RXDATA_SEL_B : bit_vector := "00"; RXDCCOUPLE_A : boolean := FALSE; RXDCCOUPLE_B : boolean := FALSE; RXDIGRESET_A : boolean := FALSE; RXDIGRESET_B : boolean := FALSE; RXDIGRX_A : boolean := FALSE; RXDIGRX_B : boolean := FALSE; RXEQ_A : bit_vector := X"4000000000000000"; RXEQ_B : bit_vector := X"4000000000000000"; RXFDCAL_CLOCK_DIVIDE_A : string := "NONE"; RXFDCAL_CLOCK_DIVIDE_B : string := "NONE"; RXFDET_HYS_CAL_A : bit_vector := "010"; RXFDET_HYS_CAL_B : bit_vector := "010"; RXFDET_HYS_SEL_A : bit_vector := "100"; RXFDET_HYS_SEL_B : bit_vector := "100"; RXFDET_LCK_CAL_A : bit_vector := "100"; RXFDET_LCK_CAL_B : bit_vector := "100"; RXFDET_LCK_SEL_A : bit_vector := "001"; RXFDET_LCK_SEL_B : bit_vector := "001"; RXFECONTROL1_A : bit_vector := "00"; RXFECONTROL1_B : bit_vector := "00"; RXFECONTROL2_A : bit_vector := "000"; RXFECONTROL2_B : bit_vector := "000"; RXFETUNE_A : bit_vector := "01"; RXFETUNE_B : bit_vector := "01"; RXLB_A : boolean := FALSE; RXLB_B : boolean := FALSE; RXLKADJ_A : bit_vector := "00000"; RXLKADJ_B : bit_vector := "00000"; RXLKAPD_A : boolean := FALSE; RXLKAPD_B : boolean := FALSE; RXLOOPCAL_WAIT_A : bit_vector := "00"; RXLOOPCAL_WAIT_B : bit_vector := "00"; RXLOOPFILT_A : bit_vector := "0111"; RXLOOPFILT_B : bit_vector := "0111"; RXMODE_A : bit_vector := "000000"; RXMODE_B : bit_vector := "000000"; RXOUTDIV2SEL_A : integer := 1; RXOUTDIV2SEL_B : integer := 1; RXPDDTST_A : boolean := TRUE; RXPDDTST_B : boolean := TRUE; RXPD_A : boolean := FALSE; RXPD_B : boolean := FALSE; RXPLLNDIVSEL_A : integer := 8; RXPLLNDIVSEL_B : integer := 8; RXPMACLKSEL_A : string := "REFCLK1"; RXPMACLKSEL_B : string := "REFCLK1"; RXRCPADJ_A : bit_vector := "011"; RXRCPADJ_B : bit_vector := "011"; RXRCPPD_A : boolean := FALSE; RXRCPPD_B : boolean := FALSE; RXRECCLK1_USE_SYNC_A : boolean := FALSE; RXRECCLK1_USE_SYNC_B : boolean := FALSE; RXRIBADJ_A : bit_vector := "11"; RXRIBADJ_B : bit_vector := "11"; RXRPDPD_A : boolean := FALSE; RXRPDPD_B : boolean := FALSE; RXRSDPD_A : boolean := FALSE; RXRSDPD_B : boolean := FALSE; RXSLOWDOWN_CAL_A : bit_vector := "00"; RXSLOWDOWN_CAL_B : bit_vector := "00"; RXTUNE_A : bit_vector := X"0000"; RXTUNE_B : bit_vector := X"0000"; RXUSRDIVISOR_A : integer := 1; RXUSRDIVISOR_B : integer := 1; RXVCODAC_INIT_A : bit_vector := "1010000000"; RXVCODAC_INIT_B : bit_vector := "1010000000"; RXVCO_CTRL_ENABLE_A : boolean := FALSE; RXVCO_CTRL_ENABLE_B : boolean := FALSE; RX_BUFFER_USE_A : boolean := TRUE; RX_BUFFER_USE_B : boolean := TRUE; RX_CLOCK_DIVIDER_A : bit_vector := "00"; RX_CLOCK_DIVIDER_B : bit_vector := "00"; SAMPLE_8X_A : boolean := FALSE; SAMPLE_8X_B : boolean := FALSE; SH_CNT_MAX_A : integer := 64; SH_CNT_MAX_B : integer := 64; SH_INVALID_CNT_MAX_A : integer := 16; SH_INVALID_CNT_MAX_B : integer := 16; SLOWDOWN_CAL_A : bit_vector := "00"; SLOWDOWN_CAL_B : bit_vector := "00"; TXABPMACLKSEL_A : string := "REFCLK1"; TXABPMACLKSEL_B : string := "REFCLK1"; TXAPD_A : boolean := FALSE; TXAPD_B : boolean := FALSE; TXAREFBIASSEL_A : boolean := TRUE; TXAREFBIASSEL_B : boolean := TRUE; TXASYNCDIVIDE_A : bit_vector := "11"; TXASYNCDIVIDE_B : bit_vector := "11"; TXCLK0_FORCE_PMACLK_A : boolean := FALSE; TXCLK0_FORCE_PMACLK_B : boolean := FALSE; TXCLKMODE_A : bit_vector := "1001"; TXCLKMODE_B : bit_vector := "1001"; TXCLMODE_A : bit_vector := "00"; TXCLMODE_B : bit_vector := "00"; TXCPSEL_A : boolean := TRUE; TXCPSEL_B : boolean := TRUE; TXCRCCLOCKDOUBLE_A : boolean := FALSE; TXCRCCLOCKDOUBLE_B : boolean := FALSE; TXCRCENABLE_A : boolean := FALSE; TXCRCENABLE_B : boolean := FALSE; TXCRCINITVAL_A : bit_vector := X"00000000"; TXCRCINITVAL_B : bit_vector := X"00000000"; TXCRCINVERTGEN_A : boolean := FALSE; TXCRCINVERTGEN_B : boolean := FALSE; TXCRCSAMECLOCK_A : boolean := FALSE; TXCRCSAMECLOCK_B : boolean := FALSE; TXCTRL1_A : bit_vector := X"200"; TXCTRL1_B : bit_vector := X"200"; TXDATA_SEL_A : bit_vector := "00"; TXDATA_SEL_B : bit_vector := "00"; TXDAT_PRDRV_DAC_A : bit_vector := "111"; TXDAT_PRDRV_DAC_B : bit_vector := "111"; TXDAT_TAP_DAC_A : bit_vector := "10110"; TXDAT_TAP_DAC_B : bit_vector := "10110"; TXDIGPD_A : boolean := FALSE; TXDIGPD_B : boolean := FALSE; TXFDCAL_CLOCK_DIVIDE_A : string := "NONE"; TXFDCAL_CLOCK_DIVIDE_B : string := "NONE"; TXHIGHSIGNALEN_A : boolean := TRUE; TXHIGHSIGNALEN_B : boolean := TRUE; TXLOOPFILT_A : bit_vector := "0111"; TXLOOPFILT_B : bit_vector := "0111"; TXLVLSHFTPD_A : boolean := FALSE; TXLVLSHFTPD_B : boolean := FALSE; TXOUTCLK1_USE_SYNC_A : boolean := FALSE; TXOUTCLK1_USE_SYNC_B : boolean := FALSE; TXOUTDIV2SEL_A : integer := 1; TXOUTDIV2SEL_B : integer := 1; TXPD_A : boolean := FALSE; TXPD_B : boolean := FALSE; TXPHASESEL_A : boolean := FALSE; TXPHASESEL_B : boolean := FALSE; TXPLLNDIVSEL_A : integer := 8; TXPLLNDIVSEL_B : integer := 8; TXPOST_PRDRV_DAC_A : bit_vector := "111"; TXPOST_PRDRV_DAC_B : bit_vector := "111"; TXPOST_TAP_DAC_A : bit_vector := "01110"; TXPOST_TAP_DAC_B : bit_vector := "01110"; TXPOST_TAP_PD_A : boolean := TRUE; TXPOST_TAP_PD_B : boolean := TRUE; TXPRE_PRDRV_DAC_A : bit_vector := "111"; TXPRE_PRDRV_DAC_B : bit_vector := "111"; TXPRE_TAP_DAC_A : bit_vector := "00000"; TXPRE_TAP_DAC_B : bit_vector := "00000"; TXPRE_TAP_PD_A : boolean := TRUE; TXPRE_TAP_PD_B : boolean := TRUE; TXSLEWRATE_A : boolean := FALSE; TXSLEWRATE_B : boolean := FALSE; TXTERMTRIM_A : bit_vector := "1100"; TXTERMTRIM_B : bit_vector := "1100"; TXTUNE_A : bit_vector := X"0000"; TXTUNE_B : bit_vector := X"0000"; TX_BUFFER_USE_A : boolean := TRUE; TX_BUFFER_USE_B : boolean := TRUE; TX_CLOCK_DIVIDER_A : bit_vector := "00"; TX_CLOCK_DIVIDER_B : bit_vector := "00"; VCODAC_INIT_A : bit_vector := "1010000000"; VCODAC_INIT_B : bit_vector := "1010000000"; VCO_CTRL_ENABLE_A : boolean := FALSE; VCO_CTRL_ENABLE_B : boolean := FALSE; VREFBIASMODE_A : bit_vector := "11"; VREFBIASMODE_B : bit_vector := "11" ); port ( CHBONDOA : out std_logic_vector(4 downto 0); CHBONDOB : out std_logic_vector(4 downto 0); DOA : out std_logic_vector(15 downto 0); DOB : out std_logic_vector(15 downto 0); DRDYA : out std_ulogic; DRDYB : out std_ulogic; RXBUFERRA : out std_ulogic; RXBUFERRB : out std_ulogic; RXCALFAILA : out std_ulogic; RXCALFAILB : out std_ulogic; RXCHARISCOMMAA : out std_logic_vector(7 downto 0); RXCHARISCOMMAB : out std_logic_vector(7 downto 0); RXCHARISKA : out std_logic_vector(7 downto 0); RXCHARISKB : out std_logic_vector(7 downto 0); RXCOMMADETA : out std_ulogic; RXCOMMADETB : out std_ulogic; RXCRCOUTA : out std_logic_vector(31 downto 0); RXCRCOUTB : out std_logic_vector(31 downto 0); RXCYCLELIMITA : out std_ulogic; RXCYCLELIMITB : out std_ulogic; RXDATAA : out std_logic_vector(63 downto 0); RXDATAB : out std_logic_vector(63 downto 0); RXDISPERRA : out std_logic_vector(7 downto 0); RXDISPERRB : out std_logic_vector(7 downto 0); RXLOCKA : out std_ulogic; RXLOCKB : out std_ulogic; RXLOSSOFSYNCA : out std_logic_vector(1 downto 0); RXLOSSOFSYNCB : out std_logic_vector(1 downto 0); RXMCLKA : out std_ulogic; RXMCLKB : out std_ulogic; RXNOTINTABLEA : out std_logic_vector(7 downto 0); RXNOTINTABLEB : out std_logic_vector(7 downto 0); RXPCSHCLKOUTA : out std_ulogic; RXPCSHCLKOUTB : out std_ulogic; RXREALIGNA : out std_ulogic; RXREALIGNB : out std_ulogic; RXRECCLK1A : out std_ulogic; RXRECCLK1B : out std_ulogic; RXRECCLK2A : out std_ulogic; RXRECCLK2B : out std_ulogic; RXRUNDISPA : out std_logic_vector(7 downto 0); RXRUNDISPB : out std_logic_vector(7 downto 0); RXSIGDETA : out std_ulogic; RXSIGDETB : out std_ulogic; RXSTATUSA : out std_logic_vector(5 downto 0); RXSTATUSB : out std_logic_vector(5 downto 0); TX1NA : out std_ulogic; TX1NB : out std_ulogic; TX1PA : out std_ulogic; TX1PB : out std_ulogic; TXBUFERRA : out std_ulogic; TXBUFERRB : out std_ulogic; TXCALFAILA : out std_ulogic; TXCALFAILB : out std_ulogic; TXCRCOUTA : out std_logic_vector(31 downto 0); TXCRCOUTB : out std_logic_vector(31 downto 0); TXCYCLELIMITA : out std_ulogic; TXCYCLELIMITB : out std_ulogic; TXKERRA : out std_logic_vector(7 downto 0); TXKERRB : out std_logic_vector(7 downto 0); TXLOCKA : out std_ulogic; TXLOCKB : out std_ulogic; TXOUTCLK1A : out std_ulogic; TXOUTCLK1B : out std_ulogic; TXOUTCLK2A : out std_ulogic; TXOUTCLK2B : out std_ulogic; TXPCSHCLKOUTA : out std_ulogic; TXPCSHCLKOUTB : out std_ulogic; TXRUNDISPA : out std_logic_vector(7 downto 0); TXRUNDISPB : out std_logic_vector(7 downto 0); CHBONDIA : in std_logic_vector(4 downto 0); CHBONDIB : in std_logic_vector(4 downto 0); DADDRA : in std_logic_vector(7 downto 0); DADDRB : in std_logic_vector(7 downto 0); DCLKA : in std_ulogic; DCLKB : in std_ulogic; DENA : in std_ulogic; DENB : in std_ulogic; DIA : in std_logic_vector(15 downto 0); DIB : in std_logic_vector(15 downto 0); DWEA : in std_ulogic; DWEB : in std_ulogic; ENCHANSYNCA : in std_ulogic; ENCHANSYNCB : in std_ulogic; ENMCOMMAALIGNA : in std_ulogic; ENMCOMMAALIGNB : in std_ulogic; ENPCOMMAALIGNA : in std_ulogic; ENPCOMMAALIGNB : in std_ulogic; GREFCLKA : in std_ulogic; GREFCLKB : in std_ulogic; LOOPBACKA : in std_logic_vector(1 downto 0); LOOPBACKB : in std_logic_vector(1 downto 0); POWERDOWNA : in std_ulogic; POWERDOWNB : in std_ulogic; REFCLK1A : in std_ulogic; REFCLK1B : in std_ulogic; REFCLK2A : in std_ulogic; REFCLK2B : in std_ulogic; RX1NA : in std_ulogic; RX1NB : in std_ulogic; RX1PA : in std_ulogic; RX1PB : in std_ulogic; RXBLOCKSYNC64B66BUSEA : in std_ulogic; RXBLOCKSYNC64B66BUSEB : in std_ulogic; RXCLKSTABLEA : in std_ulogic; RXCLKSTABLEB : in std_ulogic; RXCOMMADETUSEA : in std_ulogic; RXCOMMADETUSEB : in std_ulogic; RXCRCCLKA : in std_ulogic; RXCRCCLKB : in std_ulogic; RXCRCDATAVALIDA : in std_ulogic; RXCRCDATAVALIDB : in std_ulogic; RXCRCDATAWIDTHA : in std_logic_vector(2 downto 0); RXCRCDATAWIDTHB : in std_logic_vector(2 downto 0); RXCRCINA : in std_logic_vector(63 downto 0); RXCRCINB : in std_logic_vector(63 downto 0); RXCRCINITA : in std_ulogic; RXCRCINITB : in std_ulogic; RXCRCINTCLKA : in std_ulogic; RXCRCINTCLKB : in std_ulogic; RXCRCPDA : in std_ulogic; RXCRCPDB : in std_ulogic; RXCRCRESETA : in std_ulogic; RXCRCRESETB : in std_ulogic; RXDATAWIDTHA : in std_logic_vector(1 downto 0); RXDATAWIDTHB : in std_logic_vector(1 downto 0); RXDEC64B66BUSEA : in std_ulogic; RXDEC64B66BUSEB : in std_ulogic; RXDEC8B10BUSEA : in std_ulogic; RXDEC8B10BUSEB : in std_ulogic; RXDESCRAM64B66BUSEA : in std_ulogic; RXDESCRAM64B66BUSEB : in std_ulogic; RXIGNOREBTFA : in std_ulogic; RXIGNOREBTFB : in std_ulogic; RXINTDATAWIDTHA : in std_logic_vector(1 downto 0); RXINTDATAWIDTHB : in std_logic_vector(1 downto 0); RXPMARESETA : in std_ulogic; RXPMARESETB : in std_ulogic; RXPOLARITYA : in std_ulogic; RXPOLARITYB : in std_ulogic; RXRESETA : in std_ulogic; RXRESETB : in std_ulogic; RXSLIDEA : in std_ulogic; RXSLIDEB : in std_ulogic; RXSYNCA : in std_ulogic; RXSYNCB : in std_ulogic; RXUSRCLK2A : in std_ulogic; RXUSRCLK2B : in std_ulogic; RXUSRCLKA : in std_ulogic; RXUSRCLKB : in std_ulogic; TXBYPASS8B10BA : in std_logic_vector(7 downto 0); TXBYPASS8B10BB : in std_logic_vector(7 downto 0); TXCHARDISPMODEA : in std_logic_vector(7 downto 0); TXCHARDISPMODEB : in std_logic_vector(7 downto 0); TXCHARDISPVALA : in std_logic_vector(7 downto 0); TXCHARDISPVALB : in std_logic_vector(7 downto 0); TXCHARISKA : in std_logic_vector(7 downto 0); TXCHARISKB : in std_logic_vector(7 downto 0); TXCLKSTABLEA : in std_ulogic; TXCLKSTABLEB : in std_ulogic; TXCRCCLKA : in std_ulogic; TXCRCCLKB : in std_ulogic; TXCRCDATAVALIDA : in std_ulogic; TXCRCDATAVALIDB : in std_ulogic; TXCRCDATAWIDTHA : in std_logic_vector(2 downto 0); TXCRCDATAWIDTHB : in std_logic_vector(2 downto 0); TXCRCINA : in std_logic_vector(63 downto 0); TXCRCINB : in std_logic_vector(63 downto 0); TXCRCINITA : in std_ulogic; TXCRCINITB : in std_ulogic; TXCRCINTCLKA : in std_ulogic; TXCRCINTCLKB : in std_ulogic; TXCRCPDA : in std_ulogic; TXCRCPDB : in std_ulogic; TXCRCRESETA : in std_ulogic; TXCRCRESETB : in std_ulogic; TXDATAA : in std_logic_vector(63 downto 0); TXDATAB : in std_logic_vector(63 downto 0); TXDATAWIDTHA : in std_logic_vector(1 downto 0); TXDATAWIDTHB : in std_logic_vector(1 downto 0); TXENC64B66BUSEA : in std_ulogic; TXENC64B66BUSEB : in std_ulogic; TXENC8B10BUSEA : in std_ulogic; TXENC8B10BUSEB : in std_ulogic; TXENOOBA : in std_ulogic; TXENOOBB : in std_ulogic; TXGEARBOX64B66BUSEA : in std_ulogic; TXGEARBOX64B66BUSEB : in std_ulogic; TXINHIBITA : in std_ulogic; TXINHIBITB : in std_ulogic; TXINTDATAWIDTHA : in std_logic_vector(1 downto 0); TXINTDATAWIDTHB : in std_logic_vector(1 downto 0); TXPMARESETA : in std_ulogic; TXPMARESETB : in std_ulogic; TXPOLARITYA : in std_ulogic; TXPOLARITYB : in std_ulogic; TXRESETA : in std_ulogic; TXRESETB : in std_ulogic; TXSCRAM64B66BUSEA : in std_ulogic; TXSCRAM64B66BUSEB : in std_ulogic; TXSYNCA : in std_ulogic; TXSYNCB : in std_ulogic; TXUSRCLK2A : in std_ulogic; TXUSRCLK2B : in std_ulogic; TXUSRCLKA : in std_ulogic; TXUSRCLKB : in std_ulogic ); end GT11_DUAL; architecture GT11_DUAL_V of GT11_DUAL is signal COMBUSINA : std_logic_vector(15 downto 0); signal COMBUSINB : std_logic_vector(15 downto 0); begin GT11_inst_a : GT11 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD_A, BANDGAPSEL => BANDGAPSEL_A, BIASRESSEL => BIASRESSEL_A, CCCB_ARBITRATOR_DISABLE => CCCB_ARBITRATOR_DISABLE_A, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT_A, CHAN_BOND_MODE => CHAN_BOND_MODE_A, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT_A, CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1_A, CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2_A, CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3_A, CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4_A, CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK_A, CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1_A, CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2_A, CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3_A, CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4_A, CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK_A, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE_A, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN_A, CLK_CORRECT_USE => CLK_CORRECT_USE_A, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE_A, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT_A, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT_A, CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1_A, CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2_A, CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3_A, CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4_A, CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK_A, CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1_A, CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2_A, CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3_A, CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4_A, CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK_A, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE_A, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP_A, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN_A, COMMA32 => COMMA32_A, COMMA_10B_MASK => COMMA_10B_MASK_A, CYCLE_LIMIT_SEL => CYCLE_LIMIT_SEL_A, DCDR_FILTER => DCDR_FILTER_A, DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT_A, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT_A, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY_A, DIGRX_FWDCLK => DIGRX_FWDCLK_A, DIGRX_SYNC_MODE => DIGRX_SYNC_MODE_A, ENABLE_DCDR => ENABLE_DCDR_A, FDET_HYS_CAL => FDET_HYS_CAL_A, FDET_HYS_SEL => FDET_HYS_SEL_A, FDET_LCK_CAL => FDET_LCK_CAL_A, FDET_LCK_SEL => FDET_LCK_SEL_A, GT11_MODE => "A", IREFBIASMODE => IREFBIASMODE_A, LOOPCAL_WAIT => LOOPCAL_WAIT_A, MCOMMA_32B_VALUE => MCOMMA_32B_VALUE_A, MCOMMA_DETECT => MCOMMA_DETECT_A, OPPOSITE_SELECT => OPPOSITE_SELECT_A, PCOMMA_32B_VALUE => PCOMMA_32B_VALUE_A, PCOMMA_DETECT => PCOMMA_DETECT_A, PCS_BIT_SLIP => PCS_BIT_SLIP_A, PMACLKENABLE => PMACLKENABLE_A, PMACOREPWRENABLE => PMACOREPWRENABLE_A, PMAIREFTRIM => PMAIREFTRIM_A, PMAVBGCTRL => PMAVBGCTRL_A, PMAVREFTRIM => PMAVREFTRIM_A, PMA_BIT_SLIP => PMA_BIT_SLIP_A, POWER_ENABLE => POWER_ENABLE_A, REPEATER => REPEATER_A, RXACTST => RXACTST_A, RXAFEEQ => RXAFEEQ_A, RXAFEPD => RXAFEPD_A, RXAFETST => RXAFETST_A, RXAPD => RXAPD_A, RXAREGCTRL => RXAREGCTRL_A, RXASYNCDIVIDE => RXASYNCDIVIDE_A, RXBY_32 => RXBY_32_A, RXCDRLOS => RXCDRLOS_A, RXCLK0_FORCE_PMACLK => RXCLK0_FORCE_PMACLK_A, RXCLKMODE => RXCLKMODE_A, RXCLMODE => RXCLMODE_A, RXCMADJ => RXCMADJ_A, RXCPSEL => RXCPSEL_A, RXCPTST => RXCPTST_A, RXCRCCLOCKDOUBLE => RXCRCCLOCKDOUBLE_A, RXCRCENABLE => RXCRCENABLE_A, RXCRCINITVAL => RXCRCINITVAL_A, RXCRCINVERTGEN => RXCRCINVERTGEN_A, RXCRCSAMECLOCK => RXCRCSAMECLOCK_A, RXCTRL1 => RXCTRL1_A, RXCYCLE_LIMIT_SEL => RXCYCLE_LIMIT_SEL_A, RXDATA_SEL => RXDATA_SEL_A, RXDCCOUPLE => RXDCCOUPLE_A, RXDIGRESET => RXDIGRESET_A, RXDIGRX => RXDIGRX_A, RXEQ => RXEQ_A, RXFDCAL_CLOCK_DIVIDE => RXFDCAL_CLOCK_DIVIDE_A, RXFDET_HYS_CAL => RXFDET_HYS_CAL_A, RXFDET_HYS_SEL => RXFDET_HYS_SEL_A, RXFDET_LCK_CAL => RXFDET_LCK_CAL_A, RXFDET_LCK_SEL => RXFDET_LCK_SEL_A, RXFECONTROL1 => RXFECONTROL1_A, RXFECONTROL2 => RXFECONTROL2_A, RXFETUNE => RXFETUNE_A, RXLB => RXLB_A, RXLKADJ => RXLKADJ_A, RXLKAPD => RXLKAPD_A, RXLOOPCAL_WAIT => RXLOOPCAL_WAIT_A, RXLOOPFILT => RXLOOPFILT_A, RXMODE => RXMODE_A, RXOUTDIV2SEL => RXOUTDIV2SEL_A, RXPD => RXPD_A, RXPDDTST => RXPDDTST_A, RXPLLNDIVSEL => RXPLLNDIVSEL_A, RXPMACLKSEL => RXPMACLKSEL_A, RXRCPADJ => RXRCPADJ_A, RXRCPPD => RXRCPPD_A, RXRECCLK1_USE_SYNC => RXRECCLK1_USE_SYNC_A, RXRIBADJ => RXRIBADJ_A, RXRPDPD => RXRPDPD_A, RXRSDPD => RXRSDPD_A, RXSLOWDOWN_CAL => RXSLOWDOWN_CAL_A, RXTUNE => RXTUNE_A, RXUSRDIVISOR => RXUSRDIVISOR_A, RXVCODAC_INIT => RXVCODAC_INIT_A, RXVCO_CTRL_ENABLE => RXVCO_CTRL_ENABLE_A, RX_BUFFER_USE => RX_BUFFER_USE_A, RX_CLOCK_DIVIDER => RX_CLOCK_DIVIDER_A, SAMPLE_8X => SAMPLE_8X_A, SH_CNT_MAX => SH_CNT_MAX_A, SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX_A, SLOWDOWN_CAL => SLOWDOWN_CAL_A, TXABPMACLKSEL => TXABPMACLKSEL_A, TXAPD => TXAPD_A, TXAREFBIASSEL => TXAREFBIASSEL_A, TXASYNCDIVIDE => TXASYNCDIVIDE_A, TXCLK0_FORCE_PMACLK => TXCLK0_FORCE_PMACLK_A, TXCLKMODE => TXCLKMODE_A, TXCLMODE => TXCLMODE_A, TXCPSEL => TXCPSEL_A, TXCRCCLOCKDOUBLE => TXCRCCLOCKDOUBLE_A, TXCRCENABLE => TXCRCENABLE_A, TXCRCINITVAL => TXCRCINITVAL_A, TXCRCINVERTGEN => TXCRCINVERTGEN_A, TXCRCSAMECLOCK => TXCRCSAMECLOCK_A, TXCTRL1 => TXCTRL1_A, TXDATA_SEL => TXDATA_SEL_A, TXDAT_PRDRV_DAC => TXDAT_PRDRV_DAC_A, TXDAT_TAP_DAC => TXDAT_TAP_DAC_A, TXDIGPD => TXDIGPD_A, TXFDCAL_CLOCK_DIVIDE => TXFDCAL_CLOCK_DIVIDE_A, TXHIGHSIGNALEN => TXHIGHSIGNALEN_A, TXLOOPFILT => TXLOOPFILT_A, TXLVLSHFTPD => TXLVLSHFTPD_A, TXOUTCLK1_USE_SYNC => TXOUTCLK1_USE_SYNC_A, TXOUTDIV2SEL => TXOUTDIV2SEL_A, TXPD => TXPD_A, TXPHASESEL => TXPHASESEL_A, TXPLLNDIVSEL => TXPLLNDIVSEL_A, TXPOST_PRDRV_DAC => TXPOST_PRDRV_DAC_A, TXPOST_TAP_DAC => TXPOST_TAP_DAC_A, TXPOST_TAP_PD => TXPOST_TAP_PD_A, TXPRE_PRDRV_DAC => TXPRE_PRDRV_DAC_A, TXPRE_TAP_DAC => TXPRE_TAP_DAC_A, TXPRE_TAP_PD => TXPRE_TAP_PD_A, TXSLEWRATE => TXSLEWRATE_A, TXTERMTRIM => TXTERMTRIM_A, TXTUNE => TXTUNE_A, TX_BUFFER_USE => TX_BUFFER_USE_A, TX_CLOCK_DIVIDER => TX_CLOCK_DIVIDER_A, VCODAC_INIT => VCODAC_INIT_A, VCO_CTRL_ENABLE => VCO_CTRL_ENABLE_A, VREFBIASMODE => VREFBIASMODE_A ) port map ( CHBONDO => CHBONDOA, COMBUSOUT => COMBUSINB, DO => DOA, DRDY => DRDYA, RXBUFERR => RXBUFERRA, RXCALFAIL => RXCALFAILA, RXCHARISCOMMA => RXCHARISCOMMAA, RXCHARISK => RXCHARISKA, RXCOMMADET => RXCOMMADETA, RXCRCOUT => RXCRCOUTA, RXCYCLELIMIT => RXCYCLELIMITA, RXDATA => RXDATAA, RXDISPERR => RXDISPERRA, RXLOCK => RXLOCKA, RXLOSSOFSYNC => RXLOSSOFSYNCA, RXMCLK => RXMCLKA, RXNOTINTABLE => RXNOTINTABLEA, RXPCSHCLKOUT => RXPCSHCLKOUTA, RXREALIGN => RXREALIGNA, RXRECCLK1 => RXRECCLK1A, RXRECCLK2 => RXRECCLK2A, RXRUNDISP => RXRUNDISPA, RXSIGDET => RXSIGDETA, RXSTATUS => RXSTATUSA, TX1N => TX1NA, TX1P => TX1PA, TXBUFERR => TXBUFERRA, TXCALFAIL => TXCALFAILA, TXCRCOUT => TXCRCOUTA, TXCYCLELIMIT => TXCYCLELIMITA, TXKERR => TXKERRA, TXLOCK => TXLOCKA, TXOUTCLK1 => TXOUTCLK1A, TXOUTCLK2 => TXOUTCLK2A, TXPCSHCLKOUT => TXPCSHCLKOUTA, TXRUNDISP => TXRUNDISPA, CHBONDI => CHBONDIA, COMBUSIN => COMBUSINA, DADDR => DADDRA, DCLK => DCLKA, DEN => DENA, DI => DIA, DWE => DWEA, ENCHANSYNC => ENCHANSYNCA, ENMCOMMAALIGN => ENMCOMMAALIGNA, ENPCOMMAALIGN => ENPCOMMAALIGNA, GREFCLK => GREFCLKA, LOOPBACK => LOOPBACKA, POWERDOWN => POWERDOWNA, REFCLK1 => REFCLK1A, REFCLK2 => REFCLK2A, RX1N => RX1NA, RX1P => RX1PA, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSEA, RXCLKSTABLE => RXCLKSTABLEA, RXCOMMADETUSE => RXCOMMADETUSEA, RXCRCCLK => RXCRCCLKA, RXCRCDATAVALID => RXCRCDATAVALIDA, RXCRCDATAWIDTH => RXCRCDATAWIDTHA, RXCRCIN => RXCRCINA, RXCRCINIT => RXCRCINITA, RXCRCINTCLK => RXCRCINTCLKA, RXCRCPD => RXCRCPDA, RXCRCRESET => RXCRCRESETA, RXDATAWIDTH => RXDATAWIDTHA, RXDEC64B66BUSE => RXDEC64B66BUSEA, RXDEC8B10BUSE => RXDEC8B10BUSEA, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSEA, RXIGNOREBTF => RXIGNOREBTFA, RXINTDATAWIDTH => RXINTDATAWIDTHA, RXPMARESET => RXPMARESETA, RXPOLARITY => RXPOLARITYA, RXRESET => RXRESETA, RXSLIDE => RXSLIDEA, RXSYNC => RXSYNCA, RXUSRCLK => RXUSRCLKA, RXUSRCLK2 => RXUSRCLK2A, TXBYPASS8B10B => TXBYPASS8B10BA, TXCHARDISPMODE => TXCHARDISPMODEA, TXCHARDISPVAL => TXCHARDISPVALA, TXCHARISK => TXCHARISKA, TXCLKSTABLE => TXCLKSTABLEA, TXCRCCLK => TXCRCCLKA, TXCRCDATAVALID => TXCRCDATAVALIDA, TXCRCDATAWIDTH => TXCRCDATAWIDTHA, TXCRCIN => TXCRCINA, TXCRCINIT => TXCRCINITA, TXCRCINTCLK => TXCRCINTCLKA, TXCRCPD => TXCRCPDA, TXCRCRESET => TXCRCRESETA, TXDATA => TXDATAA, TXDATAWIDTH => TXDATAWIDTHA, TXENC64B66BUSE => TXENC64B66BUSEA, TXENC8B10BUSE => TXENC8B10BUSEA, TXENOOB => TXENOOBA, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSEA, TXINHIBIT => TXINHIBITA, TXINTDATAWIDTH => TXINTDATAWIDTHA, TXPMARESET => TXPMARESETA, TXPOLARITY => TXPOLARITYA, TXRESET => TXRESETA, TXSCRAM64B66BUSE => TXSCRAM64B66BUSEA, TXSYNC => TXSYNCA, TXUSRCLK => TXUSRCLKA, TXUSRCLK2 => TXUSRCLK2A ); GT11_inst_b : GT11 generic map ( ALIGN_COMMA_WORD => ALIGN_COMMA_WORD_B, BANDGAPSEL => BANDGAPSEL_B, BIASRESSEL => BIASRESSEL_B, CCCB_ARBITRATOR_DISABLE => CCCB_ARBITRATOR_DISABLE_B, CHAN_BOND_LIMIT => CHAN_BOND_LIMIT_B, CHAN_BOND_MODE => CHAN_BOND_MODE_B, CHAN_BOND_ONE_SHOT => CHAN_BOND_ONE_SHOT_B, CHAN_BOND_SEQ_1_1 => CHAN_BOND_SEQ_1_1_B, CHAN_BOND_SEQ_1_2 => CHAN_BOND_SEQ_1_2_B, CHAN_BOND_SEQ_1_3 => CHAN_BOND_SEQ_1_3_B, CHAN_BOND_SEQ_1_4 => CHAN_BOND_SEQ_1_4_B, CHAN_BOND_SEQ_1_MASK => CHAN_BOND_SEQ_1_MASK_B, CHAN_BOND_SEQ_2_1 => CHAN_BOND_SEQ_2_1_B, CHAN_BOND_SEQ_2_2 => CHAN_BOND_SEQ_2_2_B, CHAN_BOND_SEQ_2_3 => CHAN_BOND_SEQ_2_3_B, CHAN_BOND_SEQ_2_4 => CHAN_BOND_SEQ_2_4_B, CHAN_BOND_SEQ_2_MASK => CHAN_BOND_SEQ_2_MASK_B, CHAN_BOND_SEQ_2_USE => CHAN_BOND_SEQ_2_USE_B, CHAN_BOND_SEQ_LEN => CHAN_BOND_SEQ_LEN_B, CLK_CORRECT_USE => CLK_CORRECT_USE_B, CLK_COR_8B10B_DE => CLK_COR_8B10B_DE_B, CLK_COR_MAX_LAT => CLK_COR_MAX_LAT_B, CLK_COR_MIN_LAT => CLK_COR_MIN_LAT_B, CLK_COR_SEQ_1_1 => CLK_COR_SEQ_1_1_B, CLK_COR_SEQ_1_2 => CLK_COR_SEQ_1_2_B, CLK_COR_SEQ_1_3 => CLK_COR_SEQ_1_3_B, CLK_COR_SEQ_1_4 => CLK_COR_SEQ_1_4_B, CLK_COR_SEQ_1_MASK => CLK_COR_SEQ_1_MASK_B, CLK_COR_SEQ_2_1 => CLK_COR_SEQ_2_1_B, CLK_COR_SEQ_2_2 => CLK_COR_SEQ_2_2_B, CLK_COR_SEQ_2_3 => CLK_COR_SEQ_2_3_B, CLK_COR_SEQ_2_4 => CLK_COR_SEQ_2_4_B, CLK_COR_SEQ_2_MASK => CLK_COR_SEQ_2_MASK_B, CLK_COR_SEQ_2_USE => CLK_COR_SEQ_2_USE_B, CLK_COR_SEQ_DROP => CLK_COR_SEQ_DROP_B, CLK_COR_SEQ_LEN => CLK_COR_SEQ_LEN_B, COMMA32 => COMMA32_B, COMMA_10B_MASK => COMMA_10B_MASK_B, CYCLE_LIMIT_SEL => CYCLE_LIMIT_SEL_B, DCDR_FILTER => DCDR_FILTER_B, DEC_MCOMMA_DETECT => DEC_MCOMMA_DETECT_B, DEC_PCOMMA_DETECT => DEC_PCOMMA_DETECT_B, DEC_VALID_COMMA_ONLY => DEC_VALID_COMMA_ONLY_B, DIGRX_FWDCLK => DIGRX_FWDCLK_B, DIGRX_SYNC_MODE => DIGRX_SYNC_MODE_B, ENABLE_DCDR => ENABLE_DCDR_B, FDET_HYS_CAL => FDET_HYS_CAL_B, FDET_HYS_SEL => FDET_HYS_SEL_B, FDET_LCK_CAL => FDET_LCK_CAL_B, FDET_LCK_SEL => FDET_LCK_SEL_B, GT11_MODE => "B", IREFBIASMODE => IREFBIASMODE_B, LOOPCAL_WAIT => LOOPCAL_WAIT_B, MCOMMA_32B_VALUE => MCOMMA_32B_VALUE_B, MCOMMA_DETECT => MCOMMA_DETECT_B, OPPOSITE_SELECT => OPPOSITE_SELECT_B, PCOMMA_32B_VALUE => PCOMMA_32B_VALUE_B, PCOMMA_DETECT => PCOMMA_DETECT_B, PCS_BIT_SLIP => PCS_BIT_SLIP_B, PMACLKENABLE => PMACLKENABLE_B, PMACOREPWRENABLE => PMACOREPWRENABLE_B, PMAIREFTRIM => PMAIREFTRIM_B, PMAVBGCTRL => PMAVBGCTRL_B, PMAVREFTRIM => PMAVREFTRIM_B, PMA_BIT_SLIP => PMA_BIT_SLIP_B, POWER_ENABLE => POWER_ENABLE_B, REPEATER => REPEATER_B, RXACTST => RXACTST_B, RXAFEEQ => RXAFEEQ_B, RXAFEPD => RXAFEPD_B, RXAFETST => RXAFETST_B, RXAPD => RXAPD_B, RXAREGCTRL => RXAREGCTRL_B, RXASYNCDIVIDE => RXASYNCDIVIDE_B, RXBY_32 => RXBY_32_B, RXCDRLOS => RXCDRLOS_B, RXCLK0_FORCE_PMACLK => RXCLK0_FORCE_PMACLK_B, RXCLKMODE => RXCLKMODE_B, RXCLMODE => RXCLMODE_B, RXCMADJ => RXCMADJ_B, RXCPSEL => RXCPSEL_B, RXCPTST => RXCPTST_B, RXCRCCLOCKDOUBLE => RXCRCCLOCKDOUBLE_B, RXCRCENABLE => RXCRCENABLE_B, RXCRCINITVAL => RXCRCINITVAL_B, RXCRCINVERTGEN => RXCRCINVERTGEN_B, RXCRCSAMECLOCK => RXCRCSAMECLOCK_B, RXCTRL1 => RXCTRL1_B, RXCYCLE_LIMIT_SEL => RXCYCLE_LIMIT_SEL_B, RXDATA_SEL => RXDATA_SEL_B, RXDCCOUPLE => RXDCCOUPLE_B, RXDIGRESET => RXDIGRESET_B, RXDIGRX => RXDIGRX_B, RXEQ => RXEQ_B, RXFDCAL_CLOCK_DIVIDE => RXFDCAL_CLOCK_DIVIDE_B, RXFDET_HYS_CAL => RXFDET_HYS_CAL_B, RXFDET_HYS_SEL => RXFDET_HYS_SEL_B, RXFDET_LCK_CAL => RXFDET_LCK_CAL_B, RXFDET_LCK_SEL => RXFDET_LCK_SEL_B, RXFECONTROL1 => RXFECONTROL1_B, RXFECONTROL2 => RXFECONTROL2_B, RXFETUNE => RXFETUNE_B, RXLB => RXLB_B, RXLKADJ => RXLKADJ_B, RXLKAPD => RXLKAPD_B, RXLOOPCAL_WAIT => RXLOOPCAL_WAIT_B, RXLOOPFILT => RXLOOPFILT_B, RXMODE => RXMODE_B, RXOUTDIV2SEL => RXOUTDIV2SEL_B, RXPD => RXPD_B, RXPDDTST => RXPDDTST_B, RXPLLNDIVSEL => RXPLLNDIVSEL_B, RXPMACLKSEL => RXPMACLKSEL_B, RXRCPADJ => RXRCPADJ_B, RXRCPPD => RXRCPPD_B, RXRECCLK1_USE_SYNC => RXRECCLK1_USE_SYNC_B, RXRIBADJ => RXRIBADJ_B, RXRPDPD => RXRPDPD_B, RXRSDPD => RXRSDPD_B, RXSLOWDOWN_CAL => RXSLOWDOWN_CAL_B, RXTUNE => RXTUNE_B, RXUSRDIVISOR => RXUSRDIVISOR_B, RXVCODAC_INIT => RXVCODAC_INIT_B, RXVCO_CTRL_ENABLE => RXVCO_CTRL_ENABLE_B, RX_BUFFER_USE => RX_BUFFER_USE_B, RX_CLOCK_DIVIDER => RX_CLOCK_DIVIDER_B, SAMPLE_8X => SAMPLE_8X_B, SH_CNT_MAX => SH_CNT_MAX_B, SH_INVALID_CNT_MAX => SH_INVALID_CNT_MAX_B, SLOWDOWN_CAL => SLOWDOWN_CAL_B, TXABPMACLKSEL => TXABPMACLKSEL_B, TXAPD => TXAPD_B, TXAREFBIASSEL => TXAREFBIASSEL_B, TXASYNCDIVIDE => TXASYNCDIVIDE_B, TXCLK0_FORCE_PMACLK => TXCLK0_FORCE_PMACLK_B, TXCLKMODE => TXCLKMODE_B, TXCLMODE => TXCLMODE_B, TXCPSEL => TXCPSEL_B, TXCRCCLOCKDOUBLE => TXCRCCLOCKDOUBLE_B, TXCRCENABLE => TXCRCENABLE_B, TXCRCINITVAL => TXCRCINITVAL_B, TXCRCINVERTGEN => TXCRCINVERTGEN_B, TXCRCSAMECLOCK => TXCRCSAMECLOCK_B, TXCTRL1 => TXCTRL1_B, TXDATA_SEL => TXDATA_SEL_B, TXDAT_PRDRV_DAC => TXDAT_PRDRV_DAC_B, TXDAT_TAP_DAC => TXDAT_TAP_DAC_B, TXDIGPD => TXDIGPD_B, TXFDCAL_CLOCK_DIVIDE => TXFDCAL_CLOCK_DIVIDE_B, TXHIGHSIGNALEN => TXHIGHSIGNALEN_B, TXLOOPFILT => TXLOOPFILT_B, TXLVLSHFTPD => TXLVLSHFTPD_B, TXOUTCLK1_USE_SYNC => TXOUTCLK1_USE_SYNC_B, TXOUTDIV2SEL => TXOUTDIV2SEL_B, TXPD => TXPD_B, TXPHASESEL => TXPHASESEL_B, TXPLLNDIVSEL => TXPLLNDIVSEL_B, TXPOST_PRDRV_DAC => TXPOST_PRDRV_DAC_B, TXPOST_TAP_DAC => TXPOST_TAP_DAC_B, TXPOST_TAP_PD => TXPOST_TAP_PD_B, TXPRE_PRDRV_DAC => TXPRE_PRDRV_DAC_B, TXPRE_TAP_DAC => TXPRE_TAP_DAC_B, TXPRE_TAP_PD => TXPRE_TAP_PD_B, TXSLEWRATE => TXSLEWRATE_B, TXTERMTRIM => TXTERMTRIM_B, TXTUNE => TXTUNE_B, TX_BUFFER_USE => TX_BUFFER_USE_B, TX_CLOCK_DIVIDER => TX_CLOCK_DIVIDER_B, VCODAC_INIT => VCODAC_INIT_B, VCO_CTRL_ENABLE => VCO_CTRL_ENABLE_B, VREFBIASMODE => VREFBIASMODE_B ) port map ( CHBONDO => CHBONDOB, COMBUSOUT => COMBUSINA, DO => DOB, DRDY => DRDYB, RXBUFERR => RXBUFERRB, RXCALFAIL => RXCALFAILB, RXCHARISCOMMA => RXCHARISCOMMAB, RXCHARISK => RXCHARISKB, RXCOMMADET => RXCOMMADETB, RXCRCOUT => RXCRCOUTB, RXCYCLELIMIT => RXCYCLELIMITB, RXDATA => RXDATAB, RXDISPERR => RXDISPERRB, RXLOCK => RXLOCKB, RXLOSSOFSYNC => RXLOSSOFSYNCB, RXMCLK => RXMCLKB, RXNOTINTABLE => RXNOTINTABLEB, RXPCSHCLKOUT => RXPCSHCLKOUTB, RXREALIGN => RXREALIGNB, RXRECCLK1 => RXRECCLK1B, RXRECCLK2 => RXRECCLK2B, RXRUNDISP => RXRUNDISPB, RXSIGDET => RXSIGDETB, RXSTATUS => RXSTATUSB, TX1N => TX1NB, TX1P => TX1PB, TXBUFERR => TXBUFERRB, TXCALFAIL => TXCALFAILB, TXCRCOUT => TXCRCOUTB, TXCYCLELIMIT => TXCYCLELIMITB, TXKERR => TXKERRB, TXLOCK => TXLOCKB, TXOUTCLK1 => TXOUTCLK1B, TXOUTCLK2 => TXOUTCLK2B, TXPCSHCLKOUT => TXPCSHCLKOUTB, TXRUNDISP => TXRUNDISPB, CHBONDI => CHBONDIB, COMBUSIN => COMBUSINB, DADDR => DADDRB, DCLK => DCLKB, DEN => DENB, DI => DIB, DWE => DWEB, ENCHANSYNC => ENCHANSYNCB, ENMCOMMAALIGN => ENMCOMMAALIGNB, ENPCOMMAALIGN => ENPCOMMAALIGNB, GREFCLK => GREFCLKB, LOOPBACK => LOOPBACKB, POWERDOWN => POWERDOWNB, REFCLK1 => REFCLK1B, REFCLK2 => REFCLK2B, RX1N => RX1NB, RX1P => RX1PB, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSEB, RXCLKSTABLE => RXCLKSTABLEB, RXCOMMADETUSE => RXCOMMADETUSEB, RXCRCCLK => RXCRCCLKB, RXCRCDATAVALID => RXCRCDATAVALIDB, RXCRCDATAWIDTH => RXCRCDATAWIDTHB, RXCRCIN => RXCRCINB, RXCRCINIT => RXCRCINITB, RXCRCINTCLK => RXCRCINTCLKB, RXCRCPD => RXCRCPDB, RXCRCRESET => RXCRCRESETB, RXDATAWIDTH => RXDATAWIDTHB, RXDEC64B66BUSE => RXDEC64B66BUSEB, RXDEC8B10BUSE => RXDEC8B10BUSEB, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSEB, RXIGNOREBTF => RXIGNOREBTFB, RXINTDATAWIDTH => RXINTDATAWIDTHB, RXPMARESET => RXPMARESETB, RXPOLARITY => RXPOLARITYB, RXRESET => RXRESETB, RXSLIDE => RXSLIDEB, RXSYNC => RXSYNCB, RXUSRCLK => RXUSRCLKB, RXUSRCLK2 => RXUSRCLK2B, TXBYPASS8B10B => TXBYPASS8B10BB, TXCHARDISPMODE => TXCHARDISPMODEB, TXCHARDISPVAL => TXCHARDISPVALB, TXCHARISK => TXCHARISKB, TXCLKSTABLE => TXCLKSTABLEB, TXCRCCLK => TXCRCCLKB, TXCRCDATAVALID => TXCRCDATAVALIDB, TXCRCDATAWIDTH => TXCRCDATAWIDTHB, TXCRCIN => TXCRCINB, TXCRCINIT => TXCRCINITB, TXCRCINTCLK => TXCRCINTCLKB, TXCRCPD => TXCRCPDB, TXCRCRESET => TXCRCRESETB, TXDATA => TXDATAB, TXDATAWIDTH => TXDATAWIDTHB, TXENC64B66BUSE => TXENC64B66BUSEB, TXENC8B10BUSE => TXENC8B10BUSEB, TXENOOB => TXENOOBB, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSEB, TXINHIBIT => TXINHIBITB, TXINTDATAWIDTH => TXINTDATAWIDTHB, TXPMARESET => TXPMARESETB, TXPOLARITY => TXPOLARITYB, TXRESET => TXRESETB, TXSCRAM64B66BUSE => TXSCRAM64B66BUSEB, TXSYNC => TXSYNCB, TXUSRCLK => TXUSRCLKB, TXUSRCLK2 => TXUSRCLK2B ); end GT11_DUAL_V; ----- CELL GT11 ----- ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / 11-Gigabit Transceiver for High-Speed I/O Simulation Model -- /___/ /\ Filename : GT11.vhd -- \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. -- 05/16/05 - Changed default values for some parameters and removed two parameters. Fixed CR#207101. -- 08/08/05 - Changed default parameter values for some parameters (CR 214282). -- 02/28/06 - CR#226322 - Addition of new parameters and change of default values for some parameters. -- End Revision library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; entity GT11 is generic ( IN_DELAY : time := 0 ps; OUT_DELAY : VitalDelayType01 := (100 ps, 100 ps); ALIGN_COMMA_WORD : integer := 4; BANDGAPSEL : boolean := FALSE; BIASRESSEL : boolean := FALSE; CCCB_ARBITRATOR_DISABLE : boolean := FALSE; CHAN_BOND_LIMIT : integer := 16; CHAN_BOND_MODE : string := "NONE"; CHAN_BOND_ONE_SHOT : boolean := FALSE; CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_1_MASK : bit_vector := "1110"; CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000"; CHAN_BOND_SEQ_2_MASK : bit_vector := "1110"; CHAN_BOND_SEQ_2_USE : boolean := FALSE; CHAN_BOND_SEQ_LEN : integer := 1; CLK_CORRECT_USE : boolean := FALSE; CLK_COR_8B10B_DE : boolean := FALSE; CLK_COR_MAX_LAT : integer := 48; CLK_COR_MIN_LAT : integer := 36; CLK_COR_SEQ_1_1 : bit_vector := "00000000000"; CLK_COR_SEQ_1_2 : bit_vector := "00000000000"; CLK_COR_SEQ_1_3 : bit_vector := "00000000000"; CLK_COR_SEQ_1_4 : bit_vector := "00000000000"; CLK_COR_SEQ_1_MASK : bit_vector := "1110"; CLK_COR_SEQ_2_1 : bit_vector := "00000000000"; CLK_COR_SEQ_2_2 : bit_vector := "00000000000"; CLK_COR_SEQ_2_3 : bit_vector := "00000000000"; CLK_COR_SEQ_2_4 : bit_vector := "00000000000"; CLK_COR_SEQ_2_MASK : bit_vector := "1110"; CLK_COR_SEQ_2_USE : boolean := FALSE; CLK_COR_SEQ_DROP : boolean := FALSE; CLK_COR_SEQ_LEN : integer := 1; COMMA32 : boolean := FALSE; COMMA_10B_MASK : bit_vector := X"3FF"; CYCLE_LIMIT_SEL : bit_vector := "00"; DCDR_FILTER : bit_vector := "010"; DEC_MCOMMA_DETECT : boolean := TRUE; DEC_PCOMMA_DETECT : boolean := TRUE; DEC_VALID_COMMA_ONLY : boolean := TRUE; DIGRX_FWDCLK : bit_vector := "00"; DIGRX_SYNC_MODE : boolean := FALSE; ENABLE_DCDR : boolean := FALSE; FDET_HYS_CAL : bit_vector := "010"; FDET_HYS_SEL : bit_vector := "100"; FDET_LCK_CAL : bit_vector := "100"; FDET_LCK_SEL : bit_vector := "001"; GT11_MODE : string := "DONT_CARE"; IREFBIASMODE : bit_vector := "11"; LOOPCAL_WAIT : bit_vector := "00"; MCOMMA_32B_VALUE : bit_vector := X"00000000"; MCOMMA_DETECT : boolean := TRUE; OPPOSITE_SELECT : boolean := FALSE; PCOMMA_32B_VALUE : bit_vector := X"00000000"; PCOMMA_DETECT : boolean := TRUE; PCS_BIT_SLIP : boolean := FALSE; PMACLKENABLE : boolean := TRUE; PMACOREPWRENABLE : boolean := TRUE; PMAIREFTRIM : bit_vector := "0111"; PMAVBGCTRL : bit_vector := "00000"; PMAVREFTRIM : bit_vector := "0111"; PMA_BIT_SLIP : boolean := FALSE; POWER_ENABLE : boolean := TRUE; REPEATER : boolean := FALSE; RXACTST : boolean := FALSE; RXAFEEQ : bit_vector := "000000000"; RXAFEPD : boolean := FALSE; RXAFETST : boolean := FALSE; RXAPD : boolean := FALSE; RXAREGCTRL : bit_vector := "00000"; RXASYNCDIVIDE : bit_vector := "11"; RXBY_32 : boolean := FALSE; RXCDRLOS : bit_vector := "000000"; RXCLK0_FORCE_PMACLK : boolean := FALSE; RXCLKMODE : bit_vector := "110001"; RXCLMODE : bit_vector := "00"; RXCMADJ : bit_vector := "01"; RXCPSEL : boolean := TRUE; RXCPTST : boolean := FALSE; RXCRCCLOCKDOUBLE : boolean := FALSE; RXCRCENABLE : boolean := FALSE; RXCRCINITVAL : bit_vector := X"00000000"; RXCRCINVERTGEN : boolean := FALSE; RXCRCSAMECLOCK : boolean := FALSE; RXCTRL1 : bit_vector := X"200"; RXCYCLE_LIMIT_SEL : bit_vector := "00"; RXDATA_SEL : bit_vector := "00"; RXDCCOUPLE : boolean := FALSE; RXDIGRESET : boolean := FALSE; RXDIGRX : boolean := FALSE; RXEQ : bit_vector := X"4000000000000000"; RXFDCAL_CLOCK_DIVIDE : string := "NONE"; RXFDET_HYS_CAL : bit_vector := "010"; RXFDET_HYS_SEL : bit_vector := "100"; RXFDET_LCK_CAL : bit_vector := "100"; RXFDET_LCK_SEL : bit_vector := "001"; RXFECONTROL1 : bit_vector := "00"; RXFECONTROL2 : bit_vector := "000"; RXFETUNE : bit_vector := "01"; RXLB : boolean := FALSE; RXLKADJ : bit_vector := "00000"; RXLKAPD : boolean := FALSE; RXLOOPCAL_WAIT : bit_vector := "00"; RXLOOPFILT : bit_vector := "0111"; RXMODE : bit_vector := "000000"; RXOUTDIV2SEL : integer := 1; RXPD : boolean := FALSE; RXPDDTST : boolean := TRUE; RXPLLNDIVSEL : integer := 8; RXPMACLKSEL : string := "REFCLK1"; RXRCPADJ : bit_vector := "011"; RXRCPPD : boolean := FALSE; RXRECCLK1_USE_SYNC : boolean := FALSE; RXRIBADJ : bit_vector := "11"; RXRPDPD : boolean := FALSE; RXRSDPD : boolean := FALSE; RXSLOWDOWN_CAL : bit_vector := "00"; RXTUNE : bit_vector := X"0000"; RXUSRDIVISOR : integer := 1; RXVCODAC_INIT : bit_vector := "1010000000"; RXVCO_CTRL_ENABLE : boolean := FALSE; RX_BUFFER_USE : boolean := TRUE; RX_CLOCK_DIVIDER : bit_vector := "00"; SAMPLE_8X : boolean := FALSE; SH_CNT_MAX : integer := 64; SH_INVALID_CNT_MAX : integer := 16; SLOWDOWN_CAL : bit_vector := "00"; TXABPMACLKSEL : string := "REFCLK1"; TXAPD : boolean := FALSE; TXAREFBIASSEL : boolean := TRUE; TXASYNCDIVIDE : bit_vector := "11"; TXCLK0_FORCE_PMACLK : boolean := FALSE; TXCLKMODE : bit_vector := "1001"; TXCLMODE : bit_vector := "00"; TXCPSEL : boolean := TRUE; TXCRCCLOCKDOUBLE : boolean := FALSE; TXCRCENABLE : boolean := FALSE; TXCRCINITVAL : bit_vector := X"00000000"; TXCRCINVERTGEN : boolean := FALSE; TXCRCSAMECLOCK : boolean := FALSE; TXCTRL1 : bit_vector := X"200"; TXDATA_SEL : bit_vector := "00"; TXDAT_PRDRV_DAC : bit_vector := "111"; TXDAT_TAP_DAC : bit_vector := "10110"; TXDIGPD : boolean := FALSE; TXFDCAL_CLOCK_DIVIDE : string := "NONE"; TXHIGHSIGNALEN : boolean := TRUE; TXLOOPFILT : bit_vector := "0111"; TXLVLSHFTPD : boolean := FALSE; TXOUTCLK1_USE_SYNC : boolean := FALSE; TXOUTDIV2SEL : integer := 1; TXPD : boolean := FALSE; TXPHASESEL : boolean := FALSE; TXPLLNDIVSEL : integer := 8; TXPOST_PRDRV_DAC : bit_vector := "111"; TXPOST_TAP_DAC : bit_vector := "01110"; TXPOST_TAP_PD : boolean := TRUE; TXPRE_PRDRV_DAC : bit_vector := "111"; TXPRE_TAP_DAC : bit_vector := "00000"; TXPRE_TAP_PD : boolean := TRUE; TXSLEWRATE : boolean := FALSE; TXTERMTRIM : bit_vector := "1100"; TXTUNE : bit_vector := X"0000"; TX_BUFFER_USE : boolean := TRUE; TX_CLOCK_DIVIDER : bit_vector := "00"; VCODAC_INIT : bit_vector := "1010000000"; VCO_CTRL_ENABLE : boolean := FALSE; VREFBIASMODE : bit_vector := "11" -- clk-to-output path delays ); port ( CHBONDO : out std_logic_vector(4 downto 0); COMBUSOUT : out std_logic_vector(15 downto 0); DO : out std_logic_vector(15 downto 0); DRDY : out std_ulogic; RXBUFERR : out std_ulogic; RXCALFAIL : out std_ulogic; RXCHARISCOMMA : out std_logic_vector(7 downto 0); RXCHARISK : out std_logic_vector(7 downto 0); RXCOMMADET : out std_ulogic; RXCRCOUT : out std_logic_vector(31 downto 0); RXCYCLELIMIT : out std_ulogic; RXDATA : out std_logic_vector(63 downto 0); RXDISPERR : out std_logic_vector(7 downto 0); RXLOCK : out std_ulogic; RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXMCLK : out std_ulogic; RXNOTINTABLE : out std_logic_vector(7 downto 0); RXPCSHCLKOUT : out std_ulogic; RXREALIGN : out std_ulogic; RXRECCLK1 : out std_ulogic; RXRECCLK2 : out std_ulogic; RXRUNDISP : out std_logic_vector(7 downto 0); RXSIGDET : out std_ulogic; RXSTATUS : out std_logic_vector(5 downto 0); TX1N : out std_ulogic; TX1P : out std_ulogic; TXBUFERR : out std_ulogic; TXCALFAIL : out std_ulogic; TXCRCOUT : out std_logic_vector(31 downto 0); TXCYCLELIMIT : out std_ulogic; TXKERR : out std_logic_vector(7 downto 0); TXLOCK : out std_ulogic; TXOUTCLK1 : out std_ulogic; TXOUTCLK2 : out std_ulogic; TXPCSHCLKOUT : out std_ulogic; TXRUNDISP : out std_logic_vector(7 downto 0); CHBONDI : in std_logic_vector(4 downto 0); COMBUSIN : in std_logic_vector(15 downto 0); DADDR : in std_logic_vector(7 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; GREFCLK : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK1 : in std_ulogic; REFCLK2 : in std_ulogic; RX1N : in std_ulogic; RX1P : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCLKSTABLE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXCRCCLK : in std_ulogic; RXCRCDATAVALID : in std_ulogic; RXCRCDATAWIDTH : in std_logic_vector(2 downto 0); RXCRCIN : in std_logic_vector(63 downto 0); RXCRCINIT : in std_ulogic; RXCRCINTCLK : in std_ulogic; RXCRCPD : in std_ulogic; RXCRCRESET : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXPMARESET : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXSYNC : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(7 downto 0); TXCHARDISPMODE : in std_logic_vector(7 downto 0); TXCHARDISPVAL : in std_logic_vector(7 downto 0); TXCHARISK : in std_logic_vector(7 downto 0); TXCLKSTABLE : in std_ulogic; TXCRCCLK : in std_ulogic; TXCRCDATAVALID : in std_ulogic; TXCRCDATAWIDTH : in std_logic_vector(2 downto 0); TXCRCIN : in std_logic_vector(63 downto 0); TXCRCINIT : in std_ulogic; TXCRCINTCLK : in std_ulogic; TXCRCPD : in std_ulogic; TXCRCRESET : in std_ulogic; TXDATA : in std_logic_vector(63 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXENOOB : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPMARESET : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXSYNC : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end GT11; -- Architecture body -- architecture GT11_V of GT11 is component GT11_SWIFT_BUS port ( CHBONDO : out std_logic_vector(4 downto 0); COMBUSOUT : out std_logic_vector(15 downto 0); DO : out std_logic_vector(15 downto 0); DRDY : out std_ulogic; RXBUFERR : out std_ulogic; RXCALFAIL : out std_ulogic; RXCHARISCOMMA : out std_logic_vector(7 downto 0); RXCHARISK : out std_logic_vector(7 downto 0); RXCOMMADET : out std_ulogic; RXCRCOUT : out std_logic_vector(31 downto 0); RXCYCLELIMIT : out std_ulogic; RXDATA : out std_logic_vector(63 downto 0); RXDISPERR : out std_logic_vector(7 downto 0); RXLOCK : out std_ulogic; RXLOSSOFSYNC : out std_logic_vector(1 downto 0); RXMCLK : out std_ulogic; RXNOTINTABLE : out std_logic_vector(7 downto 0); RXPCSHCLKOUT : out std_ulogic; RXREALIGN : out std_ulogic; RXRECCLK1 : out std_ulogic; RXRECCLK2 : out std_ulogic; RXRUNDISP : out std_logic_vector(7 downto 0); RXSIGDET : out std_ulogic; RXSTATUS : out std_logic_vector(5 downto 0); TX1N : out std_ulogic; TX1P : out std_ulogic; TXBUFERR : out std_ulogic; TXCALFAIL : out std_ulogic; TXCRCOUT : out std_logic_vector(31 downto 0); TXCYCLELIMIT : out std_ulogic; TXKERR : out std_logic_vector(7 downto 0); TXLOCK : out std_ulogic; TXOUTCLK1 : out std_ulogic; TXOUTCLK2 : out std_ulogic; TXPCSHCLKOUT : out std_ulogic; TXRUNDISP : out std_logic_vector(7 downto 0); GT11_MODE : in std_logic_vector(1 downto 0); PMACFG : in std_logic_vector(63 downto 0); PMACFG2 : in std_logic_vector(63 downto 0); RXACLCFG : in std_logic_vector(63 downto 0); RXAEQCFG : in std_logic_vector(63 downto 0); RXAFECFG : in std_logic_vector(63 downto 0); synDigCfgChnBnd1 : in std_logic_vector(63 downto 0); synDigCfgChnBnd2 : in std_logic_vector(63 downto 0); synDigCfgClkCor1 : in std_logic_vector(63 downto 0); synDigCfgClkCor2 : in std_logic_vector(63 downto 0); synDigCfgComma1 : in std_logic_vector(63 downto 0); synDigCfgComma2 : in std_logic_vector(63 downto 0); synDigCfgCrc : in std_logic_vector(63 downto 0); synDigCfgMisc : in std_logic_vector(63 downto 0); synDigCfgSynPmaFD : in std_logic_vector(63 downto 0); TXACFG : in std_logic_vector(63 downto 0); TXCLCFG : in std_logic_vector(63 downto 0); CHBONDI : in std_logic_vector(4 downto 0); COMBUSIN : in std_logic_vector(15 downto 0); DADDR : in std_logic_vector(7 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; ENCHANSYNC : in std_ulogic; ENMCOMMAALIGN : in std_ulogic; ENPCOMMAALIGN : in std_ulogic; GREFCLK : in std_ulogic; GSR : in std_ulogic; LOOPBACK : in std_logic_vector(1 downto 0); POWERDOWN : in std_ulogic; REFCLK1 : in std_ulogic; REFCLK2 : in std_ulogic; RX1N : in std_ulogic; RX1P : in std_ulogic; RXBLOCKSYNC64B66BUSE : in std_ulogic; RXCLKSTABLE : in std_ulogic; RXCOMMADETUSE : in std_ulogic; RXCRCCLK : in std_ulogic; RXCRCDATAVALID : in std_ulogic; RXCRCDATAWIDTH : in std_logic_vector(2 downto 0); RXCRCIN : in std_logic_vector(63 downto 0); RXCRCINIT : in std_ulogic; RXCRCINTCLK : in std_ulogic; RXCRCPD : in std_ulogic; RXCRCRESET : in std_ulogic; RXDATAWIDTH : in std_logic_vector(1 downto 0); RXDEC64B66BUSE : in std_ulogic; RXDEC8B10BUSE : in std_ulogic; RXDESCRAM64B66BUSE : in std_ulogic; RXIGNOREBTF : in std_ulogic; RXINTDATAWIDTH : in std_logic_vector(1 downto 0); RXPMARESET : in std_ulogic; RXPOLARITY : in std_ulogic; RXRESET : in std_ulogic; RXSLIDE : in std_ulogic; RXSYNC : in std_ulogic; RXUSRCLK : in std_ulogic; RXUSRCLK2 : in std_ulogic; TXBYPASS8B10B : in std_logic_vector(7 downto 0); TXCHARDISPMODE : in std_logic_vector(7 downto 0); TXCHARDISPVAL : in std_logic_vector(7 downto 0); TXCHARISK : in std_logic_vector(7 downto 0); TXCLKSTABLE : in std_ulogic; TXCRCCLK : in std_ulogic; TXCRCDATAVALID : in std_ulogic; TXCRCDATAWIDTH : in std_logic_vector(2 downto 0); TXCRCIN : in std_logic_vector(63 downto 0); TXCRCINIT : in std_ulogic; TXCRCINTCLK : in std_ulogic; TXCRCPD : in std_ulogic; TXCRCRESET : in std_ulogic; TXDATA : in std_logic_vector(63 downto 0); TXDATAWIDTH : in std_logic_vector(1 downto 0); TXENC64B66BUSE : in std_ulogic; TXENC8B10BUSE : in std_ulogic; TXENOOB : in std_ulogic; TXGEARBOX64B66BUSE : in std_ulogic; TXINHIBIT : in std_ulogic; TXINTDATAWIDTH : in std_logic_vector(1 downto 0); TXPMARESET : in std_ulogic; TXPOLARITY : in std_ulogic; TXRESET : in std_ulogic; TXSCRAM64B66BUSE : in std_ulogic; TXSYNC : in std_ulogic; TXUSRCLK : in std_ulogic; TXUSRCLK2 : in std_ulogic ); end component; -- Attribute-to-Cell mapping signals signal GT11_MODE_BINARY : std_logic_vector(1 downto 0); -- Input/Output Pin signals signal GSR_ipd : std_ulogic; signal CHBONDI_ipd : std_logic_vector(4 downto 0); signal ENCHANSYNC_ipd : std_ulogic; signal ENMCOMMAALIGN_ipd : std_ulogic; signal ENPCOMMAALIGN_ipd : std_ulogic; signal LOOPBACK_ipd : std_logic_vector(1 downto 0); signal POWERDOWN_ipd : std_ulogic; signal RXBLOCKSYNC64B66BUSE_ipd : std_ulogic; signal RXCOMMADETUSE_ipd : std_ulogic; signal RXDATAWIDTH_ipd : std_logic_vector(1 downto 0); signal RXDEC64B66BUSE_ipd : std_ulogic; signal RXDEC8B10BUSE_ipd : std_ulogic; signal RXDESCRAM64B66BUSE_ipd : std_ulogic; signal RXIGNOREBTF_ipd : std_ulogic; signal RXINTDATAWIDTH_ipd : std_logic_vector(1 downto 0); signal RXPOLARITY_ipd : std_ulogic; signal RXRESET_ipd : std_ulogic; signal RXSLIDE_ipd : std_ulogic; signal RXUSRCLK_ipd : std_ulogic; signal RXUSRCLK2_ipd : std_ulogic; signal TXBYPASS8B10B_ipd : std_logic_vector(7 downto 0); signal TXCHARDISPMODE_ipd : std_logic_vector(7 downto 0); signal TXCHARDISPVAL_ipd : std_logic_vector(7 downto 0); signal TXCHARISK_ipd : std_logic_vector(7 downto 0); signal TXDATA_ipd : std_logic_vector(63 downto 0); signal TXDATAWIDTH_ipd : std_logic_vector(1 downto 0); signal TXENC64B66BUSE_ipd : std_ulogic; signal TXENC8B10BUSE_ipd : std_ulogic; signal TXGEARBOX64B66BUSE_ipd : std_ulogic; signal TXINHIBIT_ipd : std_ulogic; signal TXINTDATAWIDTH_ipd : std_logic_vector(1 downto 0); signal TXPOLARITY_ipd : std_ulogic; signal TXRESET_ipd : std_ulogic; signal TXSCRAM64B66BUSE_ipd : std_ulogic; signal TXUSRCLK_ipd : std_ulogic; signal TXUSRCLK2_ipd : std_ulogic; signal RXCLKSTABLE_ipd : std_ulogic; signal RXPMARESET_ipd : std_ulogic; signal TXCLKSTABLE_ipd : std_ulogic; signal TXPMARESET_ipd : std_ulogic; signal RXCRCIN_ipd : std_logic_vector(63 downto 0); signal RXCRCDATAWIDTH_ipd : std_logic_vector(2 downto 0); signal RXCRCDATAVALID_ipd : std_ulogic; signal RXCRCINIT_ipd : std_ulogic; signal RXCRCRESET_ipd : std_ulogic; signal RXCRCPD_ipd : std_ulogic; signal RXCRCCLK_ipd : std_ulogic; signal RXCRCINTCLK_ipd : std_ulogic; signal TXCRCIN_ipd : std_logic_vector(63 downto 0); signal TXCRCDATAWIDTH_ipd : std_logic_vector(2 downto 0); signal TXCRCDATAVALID_ipd : std_ulogic; signal TXCRCINIT_ipd : std_ulogic; signal TXCRCRESET_ipd : std_ulogic; signal TXCRCPD_ipd : std_ulogic; signal TXCRCCLK_ipd : std_ulogic; signal TXCRCINTCLK_ipd : std_ulogic; signal TXSYNC_ipd : std_ulogic; signal RXSYNC_ipd : std_ulogic; signal TXENOOB_ipd : std_ulogic; signal DCLK_ipd : std_ulogic; signal DADDR_ipd : std_logic_vector(7 downto 0); signal DEN_ipd : std_ulogic; signal DWE_ipd : std_ulogic; signal DI_ipd : std_logic_vector(15 downto 0); signal RX1P_ipd : std_ulogic; signal RX1N_ipd : std_ulogic; signal GREFCLK_ipd : std_ulogic; signal REFCLK1_ipd : std_ulogic; signal REFCLK2_ipd : std_ulogic; signal COMBUSIN_ipd : std_logic_vector(15 downto 0); signal CHBONDO_out : std_logic_vector(4 downto 0); signal RXSTATUS_out : std_logic_vector(5 downto 0); signal RXCHARISCOMMA_out : std_logic_vector(7 downto 0); signal RXCHARISK_out : std_logic_vector(7 downto 0); signal RXCOMMADET_out : std_ulogic; signal RXDATA_out : std_logic_vector(63 downto 0); signal RXDISPERR_out : std_logic_vector(7 downto 0); signal RXLOSSOFSYNC_out : std_logic_vector(1 downto 0); signal RXNOTINTABLE_out : std_logic_vector(7 downto 0); signal RXREALIGN_out : std_ulogic; signal RXRUNDISP_out : std_logic_vector(7 downto 0); signal RXBUFERR_out : std_ulogic; signal TXBUFERR_out : std_ulogic; signal TXKERR_out : std_logic_vector(7 downto 0); signal TXRUNDISP_out : std_logic_vector(7 downto 0); signal RXRECCLK1_out : std_ulogic; signal RXRECCLK2_out : std_ulogic; signal TXOUTCLK1_out : std_ulogic; signal TXOUTCLK2_out : std_ulogic; signal RXLOCK_out : std_ulogic; signal TXLOCK_out : std_ulogic; signal RXCYCLELIMIT_out : std_ulogic; signal TXCYCLELIMIT_out : std_ulogic; signal RXCALFAIL_out : std_ulogic; signal TXCALFAIL_out : std_ulogic; signal RXCRCOUT_out : std_logic_vector(31 downto 0); signal TXCRCOUT_out : std_logic_vector(31 downto 0); signal RXSIGDET_out : std_ulogic; signal DRDY_out : std_ulogic; signal DO_out : std_logic_vector(15 downto 0); signal RXMCLK_out : std_ulogic; signal TX1P_out : std_ulogic; signal TX1N_out : std_ulogic; signal TXPCSHCLKOUT_out : std_ulogic; signal RXPCSHCLKOUT_out : std_ulogic; signal COMBUSOUT_out : std_logic_vector(15 downto 0); signal PMACFG : std_logic_vector(63 downto 0); signal PMACFG2 : std_logic_vector(63 downto 0); signal RXACLCFG : std_logic_vector(63 downto 0); signal RXAEQCFG : std_logic_vector(63 downto 0); signal RXAFECFG : std_logic_vector(63 downto 0); signal TXACFG : std_logic_vector(63 downto 0); signal TXCLCFG : std_logic_vector(63 downto 0); signal synDigCfgChnBnd1 : std_logic_vector(63 downto 0); signal synDigCfgChnBnd2 : std_logic_vector(63 downto 0); signal synDigCfgClkCor1 : std_logic_vector(63 downto 0); signal synDigCfgClkCor2 : std_logic_vector(63 downto 0); signal synDigCfgComma1 : std_logic_vector(63 downto 0); signal synDigCfgComma2 : std_logic_vector(63 downto 0); signal synDigCfgCrc : std_logic_vector(63 downto 0); signal synDigCfgMisc : std_logic_vector(63 downto 0); signal synDigCfgSynPmaFD : std_logic_vector(63 downto 0); begin GSR_ipd <= GSR; CHBONDI_ipd <= CHBONDI after IN_DELAY; ENCHANSYNC_ipd <= ENCHANSYNC after IN_DELAY; ENMCOMMAALIGN_ipd <= ENMCOMMAALIGN after IN_DELAY; ENPCOMMAALIGN_ipd <= ENPCOMMAALIGN after IN_DELAY; LOOPBACK_ipd <= LOOPBACK after IN_DELAY; POWERDOWN_ipd <= POWERDOWN after IN_DELAY; RXBLOCKSYNC64B66BUSE_ipd <= RXBLOCKSYNC64B66BUSE after IN_DELAY; RXCOMMADETUSE_ipd <= RXCOMMADETUSE after IN_DELAY; RXDATAWIDTH_ipd <= RXDATAWIDTH after IN_DELAY; RXDEC64B66BUSE_ipd <= RXDEC64B66BUSE after IN_DELAY; RXDEC8B10BUSE_ipd <= RXDEC8B10BUSE after IN_DELAY; RXDESCRAM64B66BUSE_ipd <= RXDESCRAM64B66BUSE after IN_DELAY; RXIGNOREBTF_ipd <= RXIGNOREBTF after IN_DELAY; RXINTDATAWIDTH_ipd <= RXINTDATAWIDTH after IN_DELAY; RXPOLARITY_ipd <= RXPOLARITY after IN_DELAY; RXRESET_ipd <= RXRESET after IN_DELAY; RXSLIDE_ipd <= RXSLIDE after IN_DELAY; RXUSRCLK_ipd <= RXUSRCLK after IN_DELAY; RXUSRCLK2_ipd <= RXUSRCLK2 after IN_DELAY; TXBYPASS8B10B_ipd <= TXBYPASS8B10B after IN_DELAY; TXCHARDISPMODE_ipd <= TXCHARDISPMODE after IN_DELAY; TXCHARDISPVAL_ipd <= TXCHARDISPVAL after IN_DELAY; TXCHARISK_ipd <= TXCHARISK after IN_DELAY; TXDATA_ipd <= TXDATA after IN_DELAY; TXDATAWIDTH_ipd <= TXDATAWIDTH after IN_DELAY; TXENC64B66BUSE_ipd <= TXENC64B66BUSE after IN_DELAY; TXENC8B10BUSE_ipd <= TXENC8B10BUSE after IN_DELAY; TXGEARBOX64B66BUSE_ipd <= TXGEARBOX64B66BUSE after IN_DELAY; TXINHIBIT_ipd <= TXINHIBIT after IN_DELAY; TXINTDATAWIDTH_ipd <= TXINTDATAWIDTH after IN_DELAY; TXPOLARITY_ipd <= TXPOLARITY after IN_DELAY; TXRESET_ipd <= TXRESET after IN_DELAY; TXSCRAM64B66BUSE_ipd <= TXSCRAM64B66BUSE after IN_DELAY; TXUSRCLK_ipd <= TXUSRCLK after IN_DELAY; TXUSRCLK2_ipd <= TXUSRCLK2 after IN_DELAY; RXCLKSTABLE_ipd <= RXCLKSTABLE after IN_DELAY; RXPMARESET_ipd <= RXPMARESET after IN_DELAY; TXCLKSTABLE_ipd <= TXCLKSTABLE after IN_DELAY; TXPMARESET_ipd <= TXPMARESET after IN_DELAY; RXCRCIN_ipd <= RXCRCIN after IN_DELAY; RXCRCDATAWIDTH_ipd <= RXCRCDATAWIDTH after IN_DELAY; RXCRCDATAVALID_ipd <= RXCRCDATAVALID after IN_DELAY; RXCRCINIT_ipd <= RXCRCINIT after IN_DELAY; RXCRCRESET_ipd <= RXCRCRESET after IN_DELAY; RXCRCPD_ipd <= RXCRCPD after IN_DELAY; RXCRCCLK_ipd <= RXCRCCLK after IN_DELAY; RXCRCINTCLK_ipd <= RXCRCINTCLK after IN_DELAY; TXCRCIN_ipd <= TXCRCIN after IN_DELAY; TXCRCDATAWIDTH_ipd <= TXCRCDATAWIDTH after IN_DELAY; TXCRCDATAVALID_ipd <= TXCRCDATAVALID after IN_DELAY; TXCRCINIT_ipd <= TXCRCINIT after IN_DELAY; TXCRCRESET_ipd <= TXCRCRESET after IN_DELAY; TXCRCPD_ipd <= TXCRCPD after IN_DELAY; TXCRCCLK_ipd <= TXCRCCLK after IN_DELAY; TXCRCINTCLK_ipd <= TXCRCINTCLK after IN_DELAY; TXSYNC_ipd <= TXSYNC after IN_DELAY; RXSYNC_ipd <= RXSYNC after IN_DELAY; TXENOOB_ipd <= TXENOOB after IN_DELAY; DCLK_ipd <= DCLK after IN_DELAY; DADDR_ipd <= DADDR after IN_DELAY; DEN_ipd <= DEN after IN_DELAY; DWE_ipd <= DWE after IN_DELAY; DI_ipd <= DI after IN_DELAY; RX1P_ipd <= RX1P after IN_DELAY; RX1N_ipd <= RX1N after IN_DELAY; GREFCLK_ipd <= GREFCLK after IN_DELAY; REFCLK1_ipd <= REFCLK1 after IN_DELAY; REFCLK2_ipd <= REFCLK2 after IN_DELAY; COMBUSIN_ipd <= COMBUSIN after IN_DELAY; gt11_swift_bw_1 : GT11_SWIFT_BUS port map ( CHBONDO => CHBONDO_OUT, COMBUSOUT => COMBUSOUT_OUT, DO => DO_OUT, DRDY => DRDY_OUT, RXBUFERR => RXBUFERR_OUT, RXCALFAIL => RXCALFAIL_OUT, RXCHARISCOMMA => RXCHARISCOMMA_OUT, RXCHARISK => RXCHARISK_OUT, RXCOMMADET => RXCOMMADET_OUT, RXCRCOUT => RXCRCOUT_OUT, RXCYCLELIMIT => RXCYCLELIMIT_OUT, RXDATA => RXDATA_OUT, RXDISPERR => RXDISPERR_OUT, RXLOCK => RXLOCK_OUT, RXLOSSOFSYNC => RXLOSSOFSYNC_OUT, RXMCLK => RXMCLK_OUT, RXNOTINTABLE => RXNOTINTABLE_OUT, RXPCSHCLKOUT => RXPCSHCLKOUT_OUT, RXREALIGN => RXREALIGN_OUT, RXRECCLK1 => RXRECCLK1_OUT, RXRECCLK2 => RXRECCLK2_OUT, RXRUNDISP => RXRUNDISP_OUT, RXSIGDET => RXSIGDET_OUT, RXSTATUS => RXSTATUS_OUT, TX1N => TX1N_OUT, TX1P => TX1P_OUT, TXBUFERR => TXBUFERR_OUT, TXCALFAIL => TXCALFAIL_OUT, TXCRCOUT => TXCRCOUT_OUT, TXCYCLELIMIT => TXCYCLELIMIT_OUT, TXKERR => TXKERR_OUT, TXLOCK => TXLOCK_OUT, TXOUTCLK1 => TXOUTCLK1_OUT, TXOUTCLK2 => TXOUTCLK2_OUT, TXPCSHCLKOUT => TXPCSHCLKOUT_OUT, TXRUNDISP => TXRUNDISP_OUT, GT11_MODE => GT11_MODE_BINARY, PMACFG2 => PMACFG2, PMACFG => PMACFG, RXACLCFG => RXACLCFG, RXAEQCFG => RXAEQCFG, RXAFECFG => RXAFECFG, synDigCfgChnBnd1 => synDigCfgChnBnd1, synDigCfgChnBnd2 => synDigCfgChnBnd2, synDigCfgClkCor1 => synDigCfgClkCor1, synDigCfgClkCor2 => synDigCfgClkCor2, synDigCfgComma1 => synDigCfgComma1, synDigCfgComma2 => synDigCfgComma2, synDigCfgCrc => synDigCfgCrc, synDigCfgMisc => synDigCfgMisc, synDigCfgSynPmaFD => synDigCfgSynPmaFD, TXACFG => TXACFG, TXCLCFG => TXCLCFG, CHBONDI => CHBONDI_ipd, COMBUSIN => COMBUSIN_ipd, DADDR => DADDR_ipd, DCLK => DCLK_ipd, DEN => DEN_ipd, DI => DI_ipd, DWE => DWE_ipd, ENCHANSYNC => ENCHANSYNC_ipd, ENMCOMMAALIGN => ENMCOMMAALIGN_ipd, ENPCOMMAALIGN => ENPCOMMAALIGN_ipd, GREFCLK => GREFCLK_ipd, GSR => GSR_ipd, LOOPBACK => LOOPBACK_ipd, POWERDOWN => POWERDOWN_ipd, REFCLK1 => REFCLK1_ipd, REFCLK2 => REFCLK2_ipd, RX1N => RX1N_ipd, RX1P => RX1P_ipd, RXBLOCKSYNC64B66BUSE => RXBLOCKSYNC64B66BUSE_ipd, RXCLKSTABLE => RXCLKSTABLE_ipd, RXCOMMADETUSE => RXCOMMADETUSE_ipd, RXCRCCLK => RXCRCCLK_ipd, RXCRCDATAVALID => RXCRCDATAVALID_ipd, RXCRCDATAWIDTH => RXCRCDATAWIDTH_ipd, RXCRCIN => RXCRCIN_ipd, RXCRCINIT => RXCRCINIT_ipd, RXCRCINTCLK => RXCRCINTCLK_ipd, RXCRCPD => RXCRCPD_ipd, RXCRCRESET => RXCRCRESET_ipd, RXDATAWIDTH => RXDATAWIDTH_ipd, RXDEC8B10BUSE => RXDEC8B10BUSE_ipd, RXDEC64B66BUSE => RXDEC64B66BUSE_ipd, RXDESCRAM64B66BUSE => RXDESCRAM64B66BUSE_ipd, RXIGNOREBTF => RXIGNOREBTF_ipd, RXINTDATAWIDTH => RXINTDATAWIDTH_ipd, RXPMARESET => RXPMARESET_ipd, RXPOLARITY => RXPOLARITY_ipd, RXRESET => RXRESET_ipd, RXSLIDE => RXSLIDE_ipd, RXSYNC => RXSYNC_ipd, RXUSRCLK => RXUSRCLK_ipd, RXUSRCLK2 => RXUSRCLK2_ipd, TXBYPASS8B10B => TXBYPASS8B10B_ipd, TXCHARDISPMODE => TXCHARDISPMODE_ipd, TXCHARDISPVAL => TXCHARDISPVAL_ipd, TXCHARISK => TXCHARISK_ipd, TXCLKSTABLE => TXCLKSTABLE_ipd, TXCRCCLK => TXCRCCLK_ipd, TXCRCDATAVALID => TXCRCDATAVALID_ipd, TXCRCDATAWIDTH => TXCRCDATAWIDTH_ipd, TXCRCIN => TXCRCIN_ipd, TXCRCINIT => TXCRCINIT_ipd, TXCRCINTCLK => TXCRCINTCLK_ipd, TXCRCPD => TXCRCPD_ipd, TXCRCRESET => TXCRCRESET_ipd, TXDATA => TXDATA_ipd, TXDATAWIDTH => TXDATAWIDTH_ipd, TXENC8B10BUSE => TXENC8B10BUSE_ipd, TXENC64B66BUSE => TXENC64B66BUSE_ipd, TXENOOB => TXENOOB_ipd, TXGEARBOX64B66BUSE => TXGEARBOX64B66BUSE_ipd, TXINHIBIT => TXINHIBIT_ipd, TXINTDATAWIDTH => TXINTDATAWIDTH_ipd, TXPMARESET => TXPMARESET_ipd, TXPOLARITY => TXPOLARITY_ipd, TXRESET => TXRESET_ipd, TXSCRAM64B66BUSE => TXSCRAM64B66BUSE_ipd, TXSYNC => TXSYNC_ipd, TXUSRCLK => TXUSRCLK_ipd, TXUSRCLK2 => TXUSRCLK2_ipd ); INIPROC : process variable CHAN_BOND_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1); variable CHAN_BOND_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2); variable CHAN_BOND_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3); variable CHAN_BOND_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4); variable CHAN_BOND_SEQ_1_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_MASK); variable CHAN_BOND_LIMIT_BINARY : std_logic_vector(5 downto 0); variable CHAN_BOND_MODE_BINARY : std_logic_vector(1 downto 0); variable CHAN_BOND_ONE_SHOT_BINARY : std_ulogic; variable CHAN_BOND_SEQ_2_USE_BINARY : std_ulogic; variable CHAN_BOND_SEQ_LEN_BINARY : std_logic_vector(2 downto 0); variable RX_BUFFER_USE_BINARY : std_ulogic; variable TX_BUFFER_USE_BINARY : std_ulogic; variable CHAN_BOND_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1); variable CHAN_BOND_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2); variable CHAN_BOND_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3); variable CHAN_BOND_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4); variable CHAN_BOND_SEQ_2_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_MASK); variable POWER_ENABLE_BINARY : std_ulogic; variable OPPOSITE_SELECT_BINARY : std_ulogic; variable CCCB_ARBITRATOR_DISABLE_BINARY : std_ulogic; variable CLK_COR_SEQ_1_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1); variable CLK_COR_SEQ_1_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2); variable CLK_COR_SEQ_1_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3); variable CLK_COR_SEQ_1_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4); variable CLK_COR_SEQ_1_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_MASK); variable DIGRX_SYNC_MODE_BINARY : std_ulogic; variable DIGRX_FWDCLK_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(DIGRX_FWDCLK); variable PCS_BIT_SLIP_BINARY : std_ulogic; variable CLK_COR_MIN_LAT_BINARY : std_logic_vector(5 downto 0); variable TXDATA_SEL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(TXDATA_SEL); variable RXDATA_SEL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXDATA_SEL); variable CLK_COR_SEQ_2_1_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1); variable CLK_COR_SEQ_2_2_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2); variable CLK_COR_SEQ_2_3_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3); variable CLK_COR_SEQ_2_4_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4); variable CLK_COR_SEQ_2_MASK_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_MASK); variable CLK_COR_MAX_LAT_BINARY : std_logic_vector(5 downto 0); variable CLK_COR_SEQ_2_USE_BINARY : std_ulogic; variable CLK_COR_SEQ_DROP_BINARY : std_ulogic; variable CLK_COR_SEQ_LEN_BINARY : std_logic_vector(2 downto 0); variable CLK_CORRECT_USE_BINARY : std_ulogic; variable CLK_COR_8B10B_DE_BINARY : std_ulogic; variable SH_CNT_MAX_BINARY : std_logic_vector(7 downto 0); variable SH_INVALID_CNT_MAX_BINARY : std_logic_vector(7 downto 0); variable ALIGN_COMMA_WORD_BINARY : std_logic_vector(1 downto 0); variable DEC_MCOMMA_DETECT_BINARY : std_ulogic; variable DEC_PCOMMA_DETECT_BINARY : std_ulogic; variable DEC_VALID_COMMA_ONLY_BINARY : std_ulogic; variable MCOMMA_DETECT_BINARY : std_ulogic; variable PCOMMA_DETECT_BINARY : std_ulogic; variable COMMA32_BINARY : std_ulogic; variable COMMA_10B_MASK_BINARY : std_logic_vector(9 downto 0) := (To_StdLogicVector(COMMA_10B_MASK)(9 downto 0)); variable MCOMMA_32B_VALUE_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(MCOMMA_32B_VALUE); variable PCOMMA_32B_VALUE_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PCOMMA_32B_VALUE); variable RXUSRDIVISOR_BINARY : std_logic_vector(4 downto 0); variable DCDR_FILTER_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(DCDR_FILTER); variable SAMPLE_8X_BINARY : std_ulogic; variable ENABLE_DCDR_BINARY : std_ulogic; variable REPEATER_BINARY : std_ulogic; variable RXBY_32_BINARY : std_ulogic; variable TXFDCAL_CLOCK_DIVIDE_BINARY : std_logic_vector(1 downto 0); variable RXFDCAL_CLOCK_DIVIDE_BINARY : std_logic_vector(1 downto 0); variable RXCYCLE_LIMIT_SEL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXCYCLE_LIMIT_SEL); variable RXVCO_CTRL_ENABLE_BINARY : std_ulogic; variable RXFDET_LCK_SEL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXFDET_LCK_SEL); variable RXFDET_HYS_SEL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXFDET_HYS_SEL); variable RXFDET_LCK_CAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXFDET_LCK_CAL); variable RXFDET_HYS_CAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXFDET_HYS_CAL); variable RXLOOPCAL_WAIT_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXLOOPCAL_WAIT); variable RXSLOWDOWN_CAL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXSLOWDOWN_CAL); variable RXVCODAC_INIT_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(RXVCODAC_INIT); variable CYCLE_LIMIT_SEL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(CYCLE_LIMIT_SEL); variable VCO_CTRL_ENABLE_BINARY : std_ulogic; variable FDET_LCK_SEL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(FDET_LCK_SEL); variable FDET_HYS_SEL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(FDET_HYS_SEL); variable FDET_LCK_CAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(FDET_LCK_CAL); variable FDET_HYS_CAL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(FDET_HYS_CAL); variable LOOPCAL_WAIT_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(LOOPCAL_WAIT); variable SLOWDOWN_CAL_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(SLOWDOWN_CAL); variable VCODAC_INIT_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(VCODAC_INIT); variable RXCRCCLOCKDOUBLE_BINARY : std_ulogic; variable RXCRCINVERTGEN_BINARY : std_ulogic; variable RXCRCSAMECLOCK_BINARY : std_ulogic; variable RXCRCENABLE_BINARY : std_ulogic; variable RXCRCINITVAL_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(RXCRCINITVAL); variable TXCRCCLOCKDOUBLE_BINARY : std_ulogic; variable TXCRCINVERTGEN_BINARY : std_ulogic; variable TXCRCSAMECLOCK_BINARY : std_ulogic; variable TXCRCINITVAL_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(TXCRCINITVAL); variable TXCRCENABLE_BINARY : std_ulogic; variable RX_CLOCK_DIVIDER_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RX_CLOCK_DIVIDER); variable TX_CLOCK_DIVIDER_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(TX_CLOCK_DIVIDER); variable RXCLK0_FORCE_PMACLK_BINARY : std_ulogic; variable TXCLK0_FORCE_PMACLK_BINARY : std_ulogic; variable TXOUTCLK1_USE_SYNC_BINARY : std_ulogic; variable RXRECCLK1_USE_SYNC_BINARY : std_ulogic; variable RXPMACLKSEL_BINARY : std_logic_vector(1 downto 0); variable TXABPMACLKSEL_BINARY : std_logic_vector(1 downto 0); variable RXAREGCTRL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXAREGCTRL); variable PMAVBGCTRL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(PMAVBGCTRL); variable BANDGAPSEL_BINARY : std_ulogic; variable PMAIREFTRIM_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(PMAIREFTRIM); variable IREFBIASMODE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(IREFBIASMODE); variable BIASRESSEL_BINARY : std_ulogic; variable PMAVREFTRIM_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(PMAVREFTRIM); variable VREFBIASMODE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(VREFBIASMODE); variable TXPHASESEL_BINARY : std_ulogic; variable PMACLKENABLE_BINARY : std_ulogic; variable PMACOREPWRENABLE_BINARY : std_ulogic; variable RXMODE_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RXMODE); variable PMA_BIT_SLIP_BINARY : std_ulogic; variable RXASYNCDIVIDE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXASYNCDIVIDE); variable RXCLKMODE_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RXCLKMODE); variable RXLB_BINARY : std_ulogic; variable RXFETUNE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXFETUNE); variable RXRCPADJ_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXRCPADJ); variable RXRIBADJ_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXRIBADJ); variable RXAFEEQ_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(RXAFEEQ); variable RXCMADJ_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXCMADJ); variable RXCDRLOS_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(RXCDRLOS); variable RXDCCOUPLE_BINARY : std_ulogic; variable RXLKADJ_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(RXLKADJ); variable RXDIGRESET_BINARY : std_ulogic; variable RXFECONTROL2_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(RXFECONTROL2); variable RXCPTST_BINARY : std_ulogic; variable RXPDDTST_BINARY : std_ulogic; variable RXACTST_BINARY : std_ulogic; variable RXAFETST_BINARY : std_ulogic; variable RXFECONTROL1_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXFECONTROL1); variable RXLKAPD_BINARY : std_ulogic; variable RXRSDPD_BINARY : std_ulogic; variable RXRCPPD_BINARY : std_ulogic; variable RXRPDPD_BINARY : std_ulogic; variable RXAFEPD_BINARY : std_ulogic; variable RXPD_BINARY : std_ulogic; variable RXEQ_BINARY : std_logic_vector(63 downto 0) := To_StdLogicVector(RXEQ); variable TXOUTDIV2SEL_BINARY : std_logic_vector(3 downto 0); variable TXPLLNDIVSEL_BINARY : std_logic_vector(3 downto 0); variable TXCLMODE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(TXCLMODE); variable TXLOOPFILT_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(TXLOOPFILT); variable TXTUNE_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(TXTUNE)(12 downto 0); variable TXCPSEL_BINARY : std_ulogic; variable TXCTRL1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(TXCTRL1)(9 downto 0); variable TXAPD_BINARY : std_ulogic; variable TXLVLSHFTPD_BINARY : std_ulogic; variable TXPRE_PRDRV_DAC_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXPRE_PRDRV_DAC); variable TXPRE_TAP_PD_BINARY : std_ulogic; variable TXPRE_TAP_DAC_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXPRE_TAP_DAC); variable TXDIGPD_BINARY : std_ulogic; variable TXCLKMODE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(TXCLKMODE); variable TXHIGHSIGNALEN_BINARY : std_ulogic; variable TXAREFBIASSEL_BINARY : std_ulogic; variable TXTERMTRIM_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(TXTERMTRIM); variable TXASYNCDIVIDE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(TXASYNCDIVIDE); variable TXSLEWRATE_BINARY : std_ulogic; variable TXPOST_PRDRV_DAC_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXPOST_PRDRV_DAC); variable TXDAT_PRDRV_DAC_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXDAT_PRDRV_DAC); variable TXPOST_TAP_PD_BINARY : std_ulogic; variable TXPOST_TAP_DAC_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXPOST_TAP_DAC); variable TXDAT_TAP_DAC_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXDAT_TAP_DAC); variable TXPD_BINARY : std_ulogic; variable RXOUTDIV2SEL_BINARY : std_logic_vector(7 downto 0); variable RXPLLNDIVSEL_BINARY : std_logic_vector(3 downto 0); variable RXCLMODE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(RXCLMODE); variable RXLOOPFILT_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RXLOOPFILT); variable RXDIGRX_BINARY : std_ulogic; variable RXTUNE_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(RXTUNE)(12 downto 0); variable RXCPSEL_BINARY : std_ulogic; variable RXCTRL1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(RXCTRL1)(9 downto 0); variable RXAPD_BINARY : std_ulogic; begin -- case GT11_MODE is if((GT11_MODE = "B") or (GT11_MODE = "b")) then GT11_MODE_BINARY <= "00"; elsif((GT11_MODE = "A") or (GT11_MODE = "a")) then GT11_MODE_BINARY <= "01"; elsif((GT11_MODE = "DONT_CARE") or (GT11_MODE = "dont_care")) then GT11_MODE_BINARY <= "10"; elsif((GT11_MODE = "SINGLE") or (GT11_MODE = "single")) then GT11_MODE_BINARY <= "11"; else assert FALSE report "Error : GT11_MODE = is not DONT_CARE, A, B, SINGLE." severity error; end if; -- end case; case CHAN_BOND_LIMIT is when 0 => CHAN_BOND_LIMIT_BINARY := "000000"; when 1 => CHAN_BOND_LIMIT_BINARY := "000001"; when 2 => CHAN_BOND_LIMIT_BINARY := "000010"; when 3 => CHAN_BOND_LIMIT_BINARY := "000011"; when 4 => CHAN_BOND_LIMIT_BINARY := "000100"; when 5 => CHAN_BOND_LIMIT_BINARY := "000101"; when 6 => CHAN_BOND_LIMIT_BINARY := "000110"; when 7 => CHAN_BOND_LIMIT_BINARY := "000111"; when 8 => CHAN_BOND_LIMIT_BINARY := "001000"; when 9 => CHAN_BOND_LIMIT_BINARY := "001001"; when 10 => CHAN_BOND_LIMIT_BINARY := "001010"; when 11 => CHAN_BOND_LIMIT_BINARY := "001011"; when 12 => CHAN_BOND_LIMIT_BINARY := "001100"; when 13 => CHAN_BOND_LIMIT_BINARY := "001101"; when 14 => CHAN_BOND_LIMIT_BINARY := "001110"; when 15 => CHAN_BOND_LIMIT_BINARY := "001111"; when 16 => CHAN_BOND_LIMIT_BINARY := "010000"; when 17 => CHAN_BOND_LIMIT_BINARY := "010001"; when 18 => CHAN_BOND_LIMIT_BINARY := "010010"; when 19 => CHAN_BOND_LIMIT_BINARY := "010011"; when 20 => CHAN_BOND_LIMIT_BINARY := "010100"; when 21 => CHAN_BOND_LIMIT_BINARY := "010101"; when 22 => CHAN_BOND_LIMIT_BINARY := "010110"; when 23 => CHAN_BOND_LIMIT_BINARY := "010111"; when 24 => CHAN_BOND_LIMIT_BINARY := "011000"; when 25 => CHAN_BOND_LIMIT_BINARY := "011001"; when 26 => CHAN_BOND_LIMIT_BINARY := "011010"; when 27 => CHAN_BOND_LIMIT_BINARY := "011011"; when 28 => CHAN_BOND_LIMIT_BINARY := "011100"; when 29 => CHAN_BOND_LIMIT_BINARY := "011101"; when 30 => CHAN_BOND_LIMIT_BINARY := "011110"; when 31 => CHAN_BOND_LIMIT_BINARY := "011111"; when others => assert FALSE report "Error : CHAN_BOND_LIMIT is not in range 0...31." severity error; end case; -- case CHAN_BOND_MODE is if((CHAN_BOND_MODE = "NONE") or (CHAN_BOND_MODE = "none")) then CHAN_BOND_MODE_BINARY := "00"; elsif((CHAN_BOND_MODE = "MASTER") or (CHAN_BOND_MODE = "master")) then CHAN_BOND_MODE_BINARY := "01"; elsif((CHAN_BOND_MODE = "SLAVE_1_HOP") or (CHAN_BOND_MODE = "slave_1_hop")) then CHAN_BOND_MODE_BINARY := "10"; elsif((CHAN_BOND_MODE = "SLAVE_2_HOPS") or (CHAN_BOND_MODE = "slave_2_hops")) then CHAN_BOND_MODE_BINARY := "11"; else assert FALSE report "Error : CHAN_BOND_MODE = is not NONE, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS." severity error; end if; -- end case; case CHAN_BOND_ONE_SHOT is when FALSE => CHAN_BOND_ONE_SHOT_BINARY := '0'; when TRUE => CHAN_BOND_ONE_SHOT_BINARY := '1'; when others => assert FALSE report "Error : CHAN_BOND_ONE_SHOT is neither TRUE nor FALSE." severity error; end case; case CHAN_BOND_SEQ_2_USE is when FALSE => CHAN_BOND_SEQ_2_USE_BINARY := '0'; when TRUE => CHAN_BOND_SEQ_2_USE_BINARY := '1'; when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE is neither TRUE nor FALSE." severity error; end case; case CHAN_BOND_SEQ_LEN is when 1 => CHAN_BOND_SEQ_LEN_BINARY := "000"; when 2 => CHAN_BOND_SEQ_LEN_BINARY := "001"; when 3 => CHAN_BOND_SEQ_LEN_BINARY := "010"; when 4 => CHAN_BOND_SEQ_LEN_BINARY := "011"; when 8 => CHAN_BOND_SEQ_LEN_BINARY := "111"; when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN is not in 1, 2, 3, 4, 8." severity error; end case; case RX_BUFFER_USE is when FALSE => RX_BUFFER_USE_BINARY := '0'; when TRUE => RX_BUFFER_USE_BINARY := '1'; when others => assert FALSE report "Error : RX_BUFFER_USE is neither TRUE nor FALSE." severity error; end case; case TX_BUFFER_USE is when FALSE => TX_BUFFER_USE_BINARY := '0'; when TRUE => TX_BUFFER_USE_BINARY := '1'; when others => assert FALSE report "Error : TX_BUFFER_USE is neither TRUE nor FALSE." severity error; end case; case POWER_ENABLE is when FALSE => POWER_ENABLE_BINARY := '0'; when TRUE => POWER_ENABLE_BINARY := '1'; when others => assert FALSE report "Error : POWER_ENABLE is neither TRUE nor FALSE." severity error; end case; case OPPOSITE_SELECT is when FALSE => OPPOSITE_SELECT_BINARY := '0'; when TRUE => OPPOSITE_SELECT_BINARY := '1'; when others => assert FALSE report "Error : OPPOSITE_SELECT is neither TRUE nor FALSE." severity error; end case; case CCCB_ARBITRATOR_DISABLE is when FALSE => CCCB_ARBITRATOR_DISABLE_BINARY := '0'; when TRUE => CCCB_ARBITRATOR_DISABLE_BINARY := '1'; when others => assert FALSE report "Error : CCCB_ARBITRATOR_DISABLE is neither TRUE nor FALSE." severity error; end case; case DIGRX_SYNC_MODE is when FALSE => DIGRX_SYNC_MODE_BINARY := '0'; when TRUE => DIGRX_SYNC_MODE_BINARY := '1'; when others => assert FALSE report "Error : DIGRX_SYNC_MODE is neither TRUE nor FALSE." severity error; end case; case PCS_BIT_SLIP is when FALSE => PCS_BIT_SLIP_BINARY := '0'; when TRUE => PCS_BIT_SLIP_BINARY := '1'; when others => assert FALSE report "Error : PCS_BIT_SLIP is neither TRUE nor FALSE." severity error; end case; case CLK_COR_MIN_LAT is when 0 => CLK_COR_MIN_LAT_BINARY := "000000"; when 1 => CLK_COR_MIN_LAT_BINARY := "000001"; when 2 => CLK_COR_MIN_LAT_BINARY := "000010"; when 3 => CLK_COR_MIN_LAT_BINARY := "000011"; when 4 => CLK_COR_MIN_LAT_BINARY := "000100"; when 5 => CLK_COR_MIN_LAT_BINARY := "000101"; when 6 => CLK_COR_MIN_LAT_BINARY := "000110"; when 7 => CLK_COR_MIN_LAT_BINARY := "000111"; when 8 => CLK_COR_MIN_LAT_BINARY := "001000"; when 9 => CLK_COR_MIN_LAT_BINARY := "001001"; when 10 => CLK_COR_MIN_LAT_BINARY := "001010"; when 11 => CLK_COR_MIN_LAT_BINARY := "001011"; when 12 => CLK_COR_MIN_LAT_BINARY := "001100"; when 13 => CLK_COR_MIN_LAT_BINARY := "001101"; when 14 => CLK_COR_MIN_LAT_BINARY := "001110"; when 15 => CLK_COR_MIN_LAT_BINARY := "001111"; when 16 => CLK_COR_MIN_LAT_BINARY := "010000"; when 17 => CLK_COR_MIN_LAT_BINARY := "010001"; when 18 => CLK_COR_MIN_LAT_BINARY := "010010"; when 19 => CLK_COR_MIN_LAT_BINARY := "010011"; when 20 => CLK_COR_MIN_LAT_BINARY := "010100"; when 21 => CLK_COR_MIN_LAT_BINARY := "010101"; when 22 => CLK_COR_MIN_LAT_BINARY := "010110"; when 23 => CLK_COR_MIN_LAT_BINARY := "010111"; when 24 => CLK_COR_MIN_LAT_BINARY := "011000"; when 25 => CLK_COR_MIN_LAT_BINARY := "011001"; when 26 => CLK_COR_MIN_LAT_BINARY := "011010"; when 27 => CLK_COR_MIN_LAT_BINARY := "011011"; when 28 => CLK_COR_MIN_LAT_BINARY := "011100"; when 29 => CLK_COR_MIN_LAT_BINARY := "011101"; when 30 => CLK_COR_MIN_LAT_BINARY := "011110"; when 31 => CLK_COR_MIN_LAT_BINARY := "011111"; when 32 => CLK_COR_MIN_LAT_BINARY := "100000"; when 33 => CLK_COR_MIN_LAT_BINARY := "100001"; when 34 => CLK_COR_MIN_LAT_BINARY := "100010"; when 35 => CLK_COR_MIN_LAT_BINARY := "100011"; when 36 => CLK_COR_MIN_LAT_BINARY := "100100"; when 37 => CLK_COR_MIN_LAT_BINARY := "100101"; when 38 => CLK_COR_MIN_LAT_BINARY := "100110"; when 39 => CLK_COR_MIN_LAT_BINARY := "100111"; when 40 => CLK_COR_MIN_LAT_BINARY := "101000"; when 41 => CLK_COR_MIN_LAT_BINARY := "101001"; when 42 => CLK_COR_MIN_LAT_BINARY := "101010"; when 43 => CLK_COR_MIN_LAT_BINARY := "101011"; when 44 => CLK_COR_MIN_LAT_BINARY := "101100"; when 45 => CLK_COR_MIN_LAT_BINARY := "101101"; when 46 => CLK_COR_MIN_LAT_BINARY := "101110"; when 47 => CLK_COR_MIN_LAT_BINARY := "101111"; when 48 => CLK_COR_MIN_LAT_BINARY := "110000"; when 49 => CLK_COR_MIN_LAT_BINARY := "110001"; when 50 => CLK_COR_MIN_LAT_BINARY := "110010"; when 51 => CLK_COR_MIN_LAT_BINARY := "110011"; when 52 => CLK_COR_MIN_LAT_BINARY := "110100"; when 53 => CLK_COR_MIN_LAT_BINARY := "110101"; when 54 => CLK_COR_MIN_LAT_BINARY := "110110"; when 55 => CLK_COR_MIN_LAT_BINARY := "110111"; when 56 => CLK_COR_MIN_LAT_BINARY := "111000"; when 57 => CLK_COR_MIN_LAT_BINARY := "111001"; when 58 => CLK_COR_MIN_LAT_BINARY := "111010"; when 59 => CLK_COR_MIN_LAT_BINARY := "111011"; when 60 => CLK_COR_MIN_LAT_BINARY := "111100"; when 61 => CLK_COR_MIN_LAT_BINARY := "111101"; when 62 => CLK_COR_MIN_LAT_BINARY := "111110"; when 63 => CLK_COR_MIN_LAT_BINARY := "111111"; when others => assert FALSE report "Error : CLK_COR_MIN_LAT is not in range 0...63." severity error; end case; case CLK_COR_MAX_LAT is when 0 => CLK_COR_MAX_LAT_BINARY := "000000"; when 1 => CLK_COR_MAX_LAT_BINARY := "000001"; when 2 => CLK_COR_MAX_LAT_BINARY := "000010"; when 3 => CLK_COR_MAX_LAT_BINARY := "000011"; when 4 => CLK_COR_MAX_LAT_BINARY := "000100"; when 5 => CLK_COR_MAX_LAT_BINARY := "000101"; when 6 => CLK_COR_MAX_LAT_BINARY := "000110"; when 7 => CLK_COR_MAX_LAT_BINARY := "000111"; when 8 => CLK_COR_MAX_LAT_BINARY := "001000"; when 9 => CLK_COR_MAX_LAT_BINARY := "001001"; when 10 => CLK_COR_MAX_LAT_BINARY := "001010"; when 11 => CLK_COR_MAX_LAT_BINARY := "001011"; when 12 => CLK_COR_MAX_LAT_BINARY := "001100"; when 13 => CLK_COR_MAX_LAT_BINARY := "001101"; when 14 => CLK_COR_MAX_LAT_BINARY := "001110"; when 15 => CLK_COR_MAX_LAT_BINARY := "001111"; when 16 => CLK_COR_MAX_LAT_BINARY := "010000"; when 17 => CLK_COR_MAX_LAT_BINARY := "010001"; when 18 => CLK_COR_MAX_LAT_BINARY := "010010"; when 19 => CLK_COR_MAX_LAT_BINARY := "010011"; when 20 => CLK_COR_MAX_LAT_BINARY := "010100"; when 21 => CLK_COR_MAX_LAT_BINARY := "010101"; when 22 => CLK_COR_MAX_LAT_BINARY := "010110"; when 23 => CLK_COR_MAX_LAT_BINARY := "010111"; when 24 => CLK_COR_MAX_LAT_BINARY := "011000"; when 25 => CLK_COR_MAX_LAT_BINARY := "011001"; when 26 => CLK_COR_MAX_LAT_BINARY := "011010"; when 27 => CLK_COR_MAX_LAT_BINARY := "011011"; when 28 => CLK_COR_MAX_LAT_BINARY := "011100"; when 29 => CLK_COR_MAX_LAT_BINARY := "011101"; when 30 => CLK_COR_MAX_LAT_BINARY := "011110"; when 31 => CLK_COR_MAX_LAT_BINARY := "011111"; when 32 => CLK_COR_MAX_LAT_BINARY := "100000"; when 33 => CLK_COR_MAX_LAT_BINARY := "100001"; when 34 => CLK_COR_MAX_LAT_BINARY := "100010"; when 35 => CLK_COR_MAX_LAT_BINARY := "100011"; when 36 => CLK_COR_MAX_LAT_BINARY := "100100"; when 37 => CLK_COR_MAX_LAT_BINARY := "100101"; when 38 => CLK_COR_MAX_LAT_BINARY := "100110"; when 39 => CLK_COR_MAX_LAT_BINARY := "100111"; when 40 => CLK_COR_MAX_LAT_BINARY := "101000"; when 41 => CLK_COR_MAX_LAT_BINARY := "101001"; when 42 => CLK_COR_MAX_LAT_BINARY := "101010"; when 43 => CLK_COR_MAX_LAT_BINARY := "101011"; when 44 => CLK_COR_MAX_LAT_BINARY := "101100"; when 45 => CLK_COR_MAX_LAT_BINARY := "101101"; when 46 => CLK_COR_MAX_LAT_BINARY := "101110"; when 47 => CLK_COR_MAX_LAT_BINARY := "101111"; when 48 => CLK_COR_MAX_LAT_BINARY := "110000"; when 49 => CLK_COR_MAX_LAT_BINARY := "110001"; when 50 => CLK_COR_MAX_LAT_BINARY := "110010"; when 51 => CLK_COR_MAX_LAT_BINARY := "110011"; when 52 => CLK_COR_MAX_LAT_BINARY := "110100"; when 53 => CLK_COR_MAX_LAT_BINARY := "110101"; when 54 => CLK_COR_MAX_LAT_BINARY := "110110"; when 55 => CLK_COR_MAX_LAT_BINARY := "110111"; when 56 => CLK_COR_MAX_LAT_BINARY := "111000"; when 57 => CLK_COR_MAX_LAT_BINARY := "111001"; when 58 => CLK_COR_MAX_LAT_BINARY := "111010"; when 59 => CLK_COR_MAX_LAT_BINARY := "111011"; when 60 => CLK_COR_MAX_LAT_BINARY := "111100"; when 61 => CLK_COR_MAX_LAT_BINARY := "111101"; when 62 => CLK_COR_MAX_LAT_BINARY := "111110"; when 63 => CLK_COR_MAX_LAT_BINARY := "111111"; when others => assert FALSE report "Error : CLK_COR_MAX_LAT is not in range 0...63." severity error; end case; case CLK_COR_SEQ_2_USE is when FALSE => CLK_COR_SEQ_2_USE_BINARY := '0'; when TRUE => CLK_COR_SEQ_2_USE_BINARY := '1'; when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE is neither TRUE nor FALSE." severity error; end case; case CLK_COR_SEQ_DROP is when FALSE => CLK_COR_SEQ_DROP_BINARY := '0'; when TRUE => CLK_COR_SEQ_DROP_BINARY := '1'; when others => assert FALSE report "Error : CLK_COR_SEQ_DROP is neither TRUE nor FALSE." severity error; end case; case CLK_COR_SEQ_LEN is when 1 => CLK_COR_SEQ_LEN_BINARY := "000"; when 2 => CLK_COR_SEQ_LEN_BINARY := "001"; when 3 => CLK_COR_SEQ_LEN_BINARY := "010"; when 4 => CLK_COR_SEQ_LEN_BINARY := "011"; when 8 => CLK_COR_SEQ_LEN_BINARY := "111"; when others => assert FALSE report "Error : CLK_COR_SEQ_LEN is not in 1, 2, 3, 4, 8." severity error; end case; case CLK_CORRECT_USE is when FALSE => CLK_CORRECT_USE_BINARY := '0'; when TRUE => CLK_CORRECT_USE_BINARY := '1'; when others => assert FALSE report "Error : CLK_CORRECT_USE is neither TRUE nor FALSE." severity error; end case; case CLK_COR_8B10B_DE is when FALSE => CLK_COR_8B10B_DE_BINARY := '0'; when TRUE => CLK_COR_8B10B_DE_BINARY := '1'; when others => assert FALSE report "Error : CLK_COR_8B10B_DE is neither TRUE nor FALSE." severity error; end case; case SH_CNT_MAX is when 0 => SH_CNT_MAX_BINARY := "00000000"; when 1 => SH_CNT_MAX_BINARY := "00000001"; when 2 => SH_CNT_MAX_BINARY := "00000010"; when 3 => SH_CNT_MAX_BINARY := "00000011"; when 4 => SH_CNT_MAX_BINARY := "00000100"; when 5 => SH_CNT_MAX_BINARY := "00000101"; when 6 => SH_CNT_MAX_BINARY := "00000110"; when 7 => SH_CNT_MAX_BINARY := "00000111"; when 8 => SH_CNT_MAX_BINARY := "00001000"; when 9 => SH_CNT_MAX_BINARY := "00001001"; when 10 => SH_CNT_MAX_BINARY := "00001010"; when 11 => SH_CNT_MAX_BINARY := "00001011"; when 12 => SH_CNT_MAX_BINARY := "00001100"; when 13 => SH_CNT_MAX_BINARY := "00001101"; when 14 => SH_CNT_MAX_BINARY := "00001110"; when 15 => SH_CNT_MAX_BINARY := "00001111"; when 16 => SH_CNT_MAX_BINARY := "00010000"; when 17 => SH_CNT_MAX_BINARY := "00010001"; when 18 => SH_CNT_MAX_BINARY := "00010010"; when 19 => SH_CNT_MAX_BINARY := "00010011"; when 20 => SH_CNT_MAX_BINARY := "00010100"; when 21 => SH_CNT_MAX_BINARY := "00010101"; when 22 => SH_CNT_MAX_BINARY := "00010110"; when 23 => SH_CNT_MAX_BINARY := "00010111"; when 24 => SH_CNT_MAX_BINARY := "00011000"; when 25 => SH_CNT_MAX_BINARY := "00011001"; when 26 => SH_CNT_MAX_BINARY := "00011010"; when 27 => SH_CNT_MAX_BINARY := "00011011"; when 28 => SH_CNT_MAX_BINARY := "00011100"; when 29 => SH_CNT_MAX_BINARY := "00011101"; when 30 => SH_CNT_MAX_BINARY := "00011110"; when 31 => SH_CNT_MAX_BINARY := "00011111"; when 32 => SH_CNT_MAX_BINARY := "00100000"; when 33 => SH_CNT_MAX_BINARY := "00100001"; when 34 => SH_CNT_MAX_BINARY := "00100010"; when 35 => SH_CNT_MAX_BINARY := "00100011"; when 36 => SH_CNT_MAX_BINARY := "00100100"; when 37 => SH_CNT_MAX_BINARY := "00100101"; when 38 => SH_CNT_MAX_BINARY := "00100110"; when 39 => SH_CNT_MAX_BINARY := "00100111"; when 40 => SH_CNT_MAX_BINARY := "00101000"; when 41 => SH_CNT_MAX_BINARY := "00101001"; when 42 => SH_CNT_MAX_BINARY := "00101010"; when 43 => SH_CNT_MAX_BINARY := "00101011"; when 44 => SH_CNT_MAX_BINARY := "00101100"; when 45 => SH_CNT_MAX_BINARY := "00101101"; when 46 => SH_CNT_MAX_BINARY := "00101110"; when 47 => SH_CNT_MAX_BINARY := "00101111"; when 48 => SH_CNT_MAX_BINARY := "00110000"; when 49 => SH_CNT_MAX_BINARY := "00110001"; when 50 => SH_CNT_MAX_BINARY := "00110010"; when 51 => SH_CNT_MAX_BINARY := "00110011"; when 52 => SH_CNT_MAX_BINARY := "00110100"; when 53 => SH_CNT_MAX_BINARY := "00110101"; when 54 => SH_CNT_MAX_BINARY := "00110110"; when 55 => SH_CNT_MAX_BINARY := "00110111"; when 56 => SH_CNT_MAX_BINARY := "00111000"; when 57 => SH_CNT_MAX_BINARY := "00111001"; when 58 => SH_CNT_MAX_BINARY := "00111010"; when 59 => SH_CNT_MAX_BINARY := "00111011"; when 60 => SH_CNT_MAX_BINARY := "00111100"; when 61 => SH_CNT_MAX_BINARY := "00111101"; when 62 => SH_CNT_MAX_BINARY := "00111110"; when 63 => SH_CNT_MAX_BINARY := "00111111"; when 64 => SH_CNT_MAX_BINARY := "01000000"; when 65 => SH_CNT_MAX_BINARY := "01000001"; when 66 => SH_CNT_MAX_BINARY := "01000010"; when 67 => SH_CNT_MAX_BINARY := "01000011"; when 68 => SH_CNT_MAX_BINARY := "01000100"; when 69 => SH_CNT_MAX_BINARY := "01000101"; when 70 => SH_CNT_MAX_BINARY := "01000110"; when 71 => SH_CNT_MAX_BINARY := "01000111"; when 72 => SH_CNT_MAX_BINARY := "01001000"; when 73 => SH_CNT_MAX_BINARY := "01001001"; when 74 => SH_CNT_MAX_BINARY := "01001010"; when 75 => SH_CNT_MAX_BINARY := "01001011"; when 76 => SH_CNT_MAX_BINARY := "01001100"; when 77 => SH_CNT_MAX_BINARY := "01001101"; when 78 => SH_CNT_MAX_BINARY := "01001110"; when 79 => SH_CNT_MAX_BINARY := "01001111"; when 80 => SH_CNT_MAX_BINARY := "01010000"; when 81 => SH_CNT_MAX_BINARY := "01010001"; when 82 => SH_CNT_MAX_BINARY := "01010010"; when 83 => SH_CNT_MAX_BINARY := "01010011"; when 84 => SH_CNT_MAX_BINARY := "01010100"; when 85 => SH_CNT_MAX_BINARY := "01010101"; when 86 => SH_CNT_MAX_BINARY := "01010110"; when 87 => SH_CNT_MAX_BINARY := "01010111"; when 88 => SH_CNT_MAX_BINARY := "01011000"; when 89 => SH_CNT_MAX_BINARY := "01011001"; when 90 => SH_CNT_MAX_BINARY := "01011010"; when 91 => SH_CNT_MAX_BINARY := "01011011"; when 92 => SH_CNT_MAX_BINARY := "01011100"; when 93 => SH_CNT_MAX_BINARY := "01011101"; when 94 => SH_CNT_MAX_BINARY := "01011110"; when 95 => SH_CNT_MAX_BINARY := "01011111"; when 96 => SH_CNT_MAX_BINARY := "01100000"; when 97 => SH_CNT_MAX_BINARY := "01100001"; when 98 => SH_CNT_MAX_BINARY := "01100010"; when 99 => SH_CNT_MAX_BINARY := "01100011"; when 100 => SH_CNT_MAX_BINARY := "01100100"; when 101 => SH_CNT_MAX_BINARY := "01100101"; when 102 => SH_CNT_MAX_BINARY := "01100110"; when 103 => SH_CNT_MAX_BINARY := "01100111"; when 104 => SH_CNT_MAX_BINARY := "01101000"; when 105 => SH_CNT_MAX_BINARY := "01101001"; when 106 => SH_CNT_MAX_BINARY := "01101010"; when 107 => SH_CNT_MAX_BINARY := "01101011"; when 108 => SH_CNT_MAX_BINARY := "01101100"; when 109 => SH_CNT_MAX_BINARY := "01101101"; when 110 => SH_CNT_MAX_BINARY := "01101110"; when 111 => SH_CNT_MAX_BINARY := "01101111"; when 112 => SH_CNT_MAX_BINARY := "01110000"; when 113 => SH_CNT_MAX_BINARY := "01110001"; when 114 => SH_CNT_MAX_BINARY := "01110010"; when 115 => SH_CNT_MAX_BINARY := "01110011"; when 116 => SH_CNT_MAX_BINARY := "01110100"; when 117 => SH_CNT_MAX_BINARY := "01110101"; when 118 => SH_CNT_MAX_BINARY := "01110110"; when 119 => SH_CNT_MAX_BINARY := "01110111"; when 120 => SH_CNT_MAX_BINARY := "01111000"; when 121 => SH_CNT_MAX_BINARY := "01111001"; when 122 => SH_CNT_MAX_BINARY := "01111010"; when 123 => SH_CNT_MAX_BINARY := "01111011"; when 124 => SH_CNT_MAX_BINARY := "01111100"; when 125 => SH_CNT_MAX_BINARY := "01111101"; when 126 => SH_CNT_MAX_BINARY := "01111110"; when 127 => SH_CNT_MAX_BINARY := "01111111"; when 128 => SH_CNT_MAX_BINARY := "10000000"; when 129 => SH_CNT_MAX_BINARY := "10000001"; when 130 => SH_CNT_MAX_BINARY := "10000010"; when 131 => SH_CNT_MAX_BINARY := "10000011"; when 132 => SH_CNT_MAX_BINARY := "10000100"; when 133 => SH_CNT_MAX_BINARY := "10000101"; when 134 => SH_CNT_MAX_BINARY := "10000110"; when 135 => SH_CNT_MAX_BINARY := "10000111"; when 136 => SH_CNT_MAX_BINARY := "10001000"; when 137 => SH_CNT_MAX_BINARY := "10001001"; when 138 => SH_CNT_MAX_BINARY := "10001010"; when 139 => SH_CNT_MAX_BINARY := "10001011"; when 140 => SH_CNT_MAX_BINARY := "10001100"; when 141 => SH_CNT_MAX_BINARY := "10001101"; when 142 => SH_CNT_MAX_BINARY := "10001110"; when 143 => SH_CNT_MAX_BINARY := "10001111"; when 144 => SH_CNT_MAX_BINARY := "10010000"; when 145 => SH_CNT_MAX_BINARY := "10010001"; when 146 => SH_CNT_MAX_BINARY := "10010010"; when 147 => SH_CNT_MAX_BINARY := "10010011"; when 148 => SH_CNT_MAX_BINARY := "10010100"; when 149 => SH_CNT_MAX_BINARY := "10010101"; when 150 => SH_CNT_MAX_BINARY := "10010110"; when 151 => SH_CNT_MAX_BINARY := "10010111"; when 152 => SH_CNT_MAX_BINARY := "10011000"; when 153 => SH_CNT_MAX_BINARY := "10011001"; when 154 => SH_CNT_MAX_BINARY := "10011010"; when 155 => SH_CNT_MAX_BINARY := "10011011"; when 156 => SH_CNT_MAX_BINARY := "10011100"; when 157 => SH_CNT_MAX_BINARY := "10011101"; when 158 => SH_CNT_MAX_BINARY := "10011110"; when 159 => SH_CNT_MAX_BINARY := "10011111"; when 160 => SH_CNT_MAX_BINARY := "10100000"; when 161 => SH_CNT_MAX_BINARY := "10100001"; when 162 => SH_CNT_MAX_BINARY := "10100010"; when 163 => SH_CNT_MAX_BINARY := "10100011"; when 164 => SH_CNT_MAX_BINARY := "10100100"; when 165 => SH_CNT_MAX_BINARY := "10100101"; when 166 => SH_CNT_MAX_BINARY := "10100110"; when 167 => SH_CNT_MAX_BINARY := "10100111"; when 168 => SH_CNT_MAX_BINARY := "10101000"; when 169 => SH_CNT_MAX_BINARY := "10101001"; when 170 => SH_CNT_MAX_BINARY := "10101010"; when 171 => SH_CNT_MAX_BINARY := "10101011"; when 172 => SH_CNT_MAX_BINARY := "10101100"; when 173 => SH_CNT_MAX_BINARY := "10101101"; when 174 => SH_CNT_MAX_BINARY := "10101110"; when 175 => SH_CNT_MAX_BINARY := "10101111"; when 176 => SH_CNT_MAX_BINARY := "10110000"; when 177 => SH_CNT_MAX_BINARY := "10110001"; when 178 => SH_CNT_MAX_BINARY := "10110010"; when 179 => SH_CNT_MAX_BINARY := "10110011"; when 180 => SH_CNT_MAX_BINARY := "10110100"; when 181 => SH_CNT_MAX_BINARY := "10110101"; when 182 => SH_CNT_MAX_BINARY := "10110110"; when 183 => SH_CNT_MAX_BINARY := "10110111"; when 184 => SH_CNT_MAX_BINARY := "10111000"; when 185 => SH_CNT_MAX_BINARY := "10111001"; when 186 => SH_CNT_MAX_BINARY := "10111010"; when 187 => SH_CNT_MAX_BINARY := "10111011"; when 188 => SH_CNT_MAX_BINARY := "10111100"; when 189 => SH_CNT_MAX_BINARY := "10111101"; when 190 => SH_CNT_MAX_BINARY := "10111110"; when 191 => SH_CNT_MAX_BINARY := "10111111"; when 192 => SH_CNT_MAX_BINARY := "11000000"; when 193 => SH_CNT_MAX_BINARY := "11000001"; when 194 => SH_CNT_MAX_BINARY := "11000010"; when 195 => SH_CNT_MAX_BINARY := "11000011"; when 196 => SH_CNT_MAX_BINARY := "11000100"; when 197 => SH_CNT_MAX_BINARY := "11000101"; when 198 => SH_CNT_MAX_BINARY := "11000110"; when 199 => SH_CNT_MAX_BINARY := "11000111"; when 200 => SH_CNT_MAX_BINARY := "11001000"; when 201 => SH_CNT_MAX_BINARY := "11001001"; when 202 => SH_CNT_MAX_BINARY := "11001010"; when 203 => SH_CNT_MAX_BINARY := "11001011"; when 204 => SH_CNT_MAX_BINARY := "11001100"; when 205 => SH_CNT_MAX_BINARY := "11001101"; when 206 => SH_CNT_MAX_BINARY := "11001110"; when 207 => SH_CNT_MAX_BINARY := "11001111"; when 208 => SH_CNT_MAX_BINARY := "11010000"; when 209 => SH_CNT_MAX_BINARY := "11010001"; when 210 => SH_CNT_MAX_BINARY := "11010010"; when 211 => SH_CNT_MAX_BINARY := "11010011"; when 212 => SH_CNT_MAX_BINARY := "11010100"; when 213 => SH_CNT_MAX_BINARY := "11010101"; when 214 => SH_CNT_MAX_BINARY := "11010110"; when 215 => SH_CNT_MAX_BINARY := "11010111"; when 216 => SH_CNT_MAX_BINARY := "11011000"; when 217 => SH_CNT_MAX_BINARY := "11011001"; when 218 => SH_CNT_MAX_BINARY := "11011010"; when 219 => SH_CNT_MAX_BINARY := "11011011"; when 220 => SH_CNT_MAX_BINARY := "11011100"; when 221 => SH_CNT_MAX_BINARY := "11011101"; when 222 => SH_CNT_MAX_BINARY := "11011110"; when 223 => SH_CNT_MAX_BINARY := "11011111"; when 224 => SH_CNT_MAX_BINARY := "11100000"; when 225 => SH_CNT_MAX_BINARY := "11100001"; when 226 => SH_CNT_MAX_BINARY := "11100010"; when 227 => SH_CNT_MAX_BINARY := "11100011"; when 228 => SH_CNT_MAX_BINARY := "11100100"; when 229 => SH_CNT_MAX_BINARY := "11100101"; when 230 => SH_CNT_MAX_BINARY := "11100110"; when 231 => SH_CNT_MAX_BINARY := "11100111"; when 232 => SH_CNT_MAX_BINARY := "11101000"; when 233 => SH_CNT_MAX_BINARY := "11101001"; when 234 => SH_CNT_MAX_BINARY := "11101010"; when 235 => SH_CNT_MAX_BINARY := "11101011"; when 236 => SH_CNT_MAX_BINARY := "11101100"; when 237 => SH_CNT_MAX_BINARY := "11101101"; when 238 => SH_CNT_MAX_BINARY := "11101110"; when 239 => SH_CNT_MAX_BINARY := "11101111"; when 240 => SH_CNT_MAX_BINARY := "11110000"; when 241 => SH_CNT_MAX_BINARY := "11110001"; when 242 => SH_CNT_MAX_BINARY := "11110010"; when 243 => SH_CNT_MAX_BINARY := "11110011"; when 244 => SH_CNT_MAX_BINARY := "11110100"; when 245 => SH_CNT_MAX_BINARY := "11110101"; when 246 => SH_CNT_MAX_BINARY := "11110110"; when 247 => SH_CNT_MAX_BINARY := "11110111"; when 248 => SH_CNT_MAX_BINARY := "11111000"; when 249 => SH_CNT_MAX_BINARY := "11111001"; when 250 => SH_CNT_MAX_BINARY := "11111010"; when 251 => SH_CNT_MAX_BINARY := "11111011"; when 252 => SH_CNT_MAX_BINARY := "11111100"; when 253 => SH_CNT_MAX_BINARY := "11111101"; when 254 => SH_CNT_MAX_BINARY := "11111110"; when 255 => SH_CNT_MAX_BINARY := "11111111"; when others => assert FALSE report "Error : SH_CNT_MAX is not in range 0...255." severity error; end case; case SH_INVALID_CNT_MAX is when 0 => SH_INVALID_CNT_MAX_BINARY := "00000000"; when 1 => SH_INVALID_CNT_MAX_BINARY := "00000001"; when 2 => SH_INVALID_CNT_MAX_BINARY := "00000010"; when 3 => SH_INVALID_CNT_MAX_BINARY := "00000011"; when 4 => SH_INVALID_CNT_MAX_BINARY := "00000100"; when 5 => SH_INVALID_CNT_MAX_BINARY := "00000101"; when 6 => SH_INVALID_CNT_MAX_BINARY := "00000110"; when 7 => SH_INVALID_CNT_MAX_BINARY := "00000111"; when 8 => SH_INVALID_CNT_MAX_BINARY := "00001000"; when 9 => SH_INVALID_CNT_MAX_BINARY := "00001001"; when 10 => SH_INVALID_CNT_MAX_BINARY := "00001010"; when 11 => SH_INVALID_CNT_MAX_BINARY := "00001011"; when 12 => SH_INVALID_CNT_MAX_BINARY := "00001100"; when 13 => SH_INVALID_CNT_MAX_BINARY := "00001101"; when 14 => SH_INVALID_CNT_MAX_BINARY := "00001110"; when 15 => SH_INVALID_CNT_MAX_BINARY := "00001111"; when 16 => SH_INVALID_CNT_MAX_BINARY := "00010000"; when 17 => SH_INVALID_CNT_MAX_BINARY := "00010001"; when 18 => SH_INVALID_CNT_MAX_BINARY := "00010010"; when 19 => SH_INVALID_CNT_MAX_BINARY := "00010011"; when 20 => SH_INVALID_CNT_MAX_BINARY := "00010100"; when 21 => SH_INVALID_CNT_MAX_BINARY := "00010101"; when 22 => SH_INVALID_CNT_MAX_BINARY := "00010110"; when 23 => SH_INVALID_CNT_MAX_BINARY := "00010111"; when 24 => SH_INVALID_CNT_MAX_BINARY := "00011000"; when 25 => SH_INVALID_CNT_MAX_BINARY := "00011001"; when 26 => SH_INVALID_CNT_MAX_BINARY := "00011010"; when 27 => SH_INVALID_CNT_MAX_BINARY := "00011011"; when 28 => SH_INVALID_CNT_MAX_BINARY := "00011100"; when 29 => SH_INVALID_CNT_MAX_BINARY := "00011101"; when 30 => SH_INVALID_CNT_MAX_BINARY := "00011110"; when 31 => SH_INVALID_CNT_MAX_BINARY := "00011111"; when 32 => SH_INVALID_CNT_MAX_BINARY := "00100000"; when 33 => SH_INVALID_CNT_MAX_BINARY := "00100001"; when 34 => SH_INVALID_CNT_MAX_BINARY := "00100010"; when 35 => SH_INVALID_CNT_MAX_BINARY := "00100011"; when 36 => SH_INVALID_CNT_MAX_BINARY := "00100100"; when 37 => SH_INVALID_CNT_MAX_BINARY := "00100101"; when 38 => SH_INVALID_CNT_MAX_BINARY := "00100110"; when 39 => SH_INVALID_CNT_MAX_BINARY := "00100111"; when 40 => SH_INVALID_CNT_MAX_BINARY := "00101000"; when 41 => SH_INVALID_CNT_MAX_BINARY := "00101001"; when 42 => SH_INVALID_CNT_MAX_BINARY := "00101010"; when 43 => SH_INVALID_CNT_MAX_BINARY := "00101011"; when 44 => SH_INVALID_CNT_MAX_BINARY := "00101100"; when 45 => SH_INVALID_CNT_MAX_BINARY := "00101101"; when 46 => SH_INVALID_CNT_MAX_BINARY := "00101110"; when 47 => SH_INVALID_CNT_MAX_BINARY := "00101111"; when 48 => SH_INVALID_CNT_MAX_BINARY := "00110000"; when 49 => SH_INVALID_CNT_MAX_BINARY := "00110001"; when 50 => SH_INVALID_CNT_MAX_BINARY := "00110010"; when 51 => SH_INVALID_CNT_MAX_BINARY := "00110011"; when 52 => SH_INVALID_CNT_MAX_BINARY := "00110100"; when 53 => SH_INVALID_CNT_MAX_BINARY := "00110101"; when 54 => SH_INVALID_CNT_MAX_BINARY := "00110110"; when 55 => SH_INVALID_CNT_MAX_BINARY := "00110111"; when 56 => SH_INVALID_CNT_MAX_BINARY := "00111000"; when 57 => SH_INVALID_CNT_MAX_BINARY := "00111001"; when 58 => SH_INVALID_CNT_MAX_BINARY := "00111010"; when 59 => SH_INVALID_CNT_MAX_BINARY := "00111011"; when 60 => SH_INVALID_CNT_MAX_BINARY := "00111100"; when 61 => SH_INVALID_CNT_MAX_BINARY := "00111101"; when 62 => SH_INVALID_CNT_MAX_BINARY := "00111110"; when 63 => SH_INVALID_CNT_MAX_BINARY := "00111111"; when 64 => SH_INVALID_CNT_MAX_BINARY := "01000000"; when 65 => SH_INVALID_CNT_MAX_BINARY := "01000001"; when 66 => SH_INVALID_CNT_MAX_BINARY := "01000010"; when 67 => SH_INVALID_CNT_MAX_BINARY := "01000011"; when 68 => SH_INVALID_CNT_MAX_BINARY := "01000100"; when 69 => SH_INVALID_CNT_MAX_BINARY := "01000101"; when 70 => SH_INVALID_CNT_MAX_BINARY := "01000110"; when 71 => SH_INVALID_CNT_MAX_BINARY := "01000111"; when 72 => SH_INVALID_CNT_MAX_BINARY := "01001000"; when 73 => SH_INVALID_CNT_MAX_BINARY := "01001001"; when 74 => SH_INVALID_CNT_MAX_BINARY := "01001010"; when 75 => SH_INVALID_CNT_MAX_BINARY := "01001011"; when 76 => SH_INVALID_CNT_MAX_BINARY := "01001100"; when 77 => SH_INVALID_CNT_MAX_BINARY := "01001101"; when 78 => SH_INVALID_CNT_MAX_BINARY := "01001110"; when 79 => SH_INVALID_CNT_MAX_BINARY := "01001111"; when 80 => SH_INVALID_CNT_MAX_BINARY := "01010000"; when 81 => SH_INVALID_CNT_MAX_BINARY := "01010001"; when 82 => SH_INVALID_CNT_MAX_BINARY := "01010010"; when 83 => SH_INVALID_CNT_MAX_BINARY := "01010011"; when 84 => SH_INVALID_CNT_MAX_BINARY := "01010100"; when 85 => SH_INVALID_CNT_MAX_BINARY := "01010101"; when 86 => SH_INVALID_CNT_MAX_BINARY := "01010110"; when 87 => SH_INVALID_CNT_MAX_BINARY := "01010111"; when 88 => SH_INVALID_CNT_MAX_BINARY := "01011000"; when 89 => SH_INVALID_CNT_MAX_BINARY := "01011001"; when 90 => SH_INVALID_CNT_MAX_BINARY := "01011010"; when 91 => SH_INVALID_CNT_MAX_BINARY := "01011011"; when 92 => SH_INVALID_CNT_MAX_BINARY := "01011100"; when 93 => SH_INVALID_CNT_MAX_BINARY := "01011101"; when 94 => SH_INVALID_CNT_MAX_BINARY := "01011110"; when 95 => SH_INVALID_CNT_MAX_BINARY := "01011111"; when 96 => SH_INVALID_CNT_MAX_BINARY := "01100000"; when 97 => SH_INVALID_CNT_MAX_BINARY := "01100001"; when 98 => SH_INVALID_CNT_MAX_BINARY := "01100010"; when 99 => SH_INVALID_CNT_MAX_BINARY := "01100011"; when 100 => SH_INVALID_CNT_MAX_BINARY := "01100100"; when 101 => SH_INVALID_CNT_MAX_BINARY := "01100101"; when 102 => SH_INVALID_CNT_MAX_BINARY := "01100110"; when 103 => SH_INVALID_CNT_MAX_BINARY := "01100111"; when 104 => SH_INVALID_CNT_MAX_BINARY := "01101000"; when 105 => SH_INVALID_CNT_MAX_BINARY := "01101001"; when 106 => SH_INVALID_CNT_MAX_BINARY := "01101010"; when 107 => SH_INVALID_CNT_MAX_BINARY := "01101011"; when 108 => SH_INVALID_CNT_MAX_BINARY := "01101100"; when 109 => SH_INVALID_CNT_MAX_BINARY := "01101101"; when 110 => SH_INVALID_CNT_MAX_BINARY := "01101110"; when 111 => SH_INVALID_CNT_MAX_BINARY := "01101111"; when 112 => SH_INVALID_CNT_MAX_BINARY := "01110000"; when 113 => SH_INVALID_CNT_MAX_BINARY := "01110001"; when 114 => SH_INVALID_CNT_MAX_BINARY := "01110010"; when 115 => SH_INVALID_CNT_MAX_BINARY := "01110011"; when 116 => SH_INVALID_CNT_MAX_BINARY := "01110100"; when 117 => SH_INVALID_CNT_MAX_BINARY := "01110101"; when 118 => SH_INVALID_CNT_MAX_BINARY := "01110110"; when 119 => SH_INVALID_CNT_MAX_BINARY := "01110111"; when 120 => SH_INVALID_CNT_MAX_BINARY := "01111000"; when 121 => SH_INVALID_CNT_MAX_BINARY := "01111001"; when 122 => SH_INVALID_CNT_MAX_BINARY := "01111010"; when 123 => SH_INVALID_CNT_MAX_BINARY := "01111011"; when 124 => SH_INVALID_CNT_MAX_BINARY := "01111100"; when 125 => SH_INVALID_CNT_MAX_BINARY := "01111101"; when 126 => SH_INVALID_CNT_MAX_BINARY := "01111110"; when 127 => SH_INVALID_CNT_MAX_BINARY := "01111111"; when 128 => SH_INVALID_CNT_MAX_BINARY := "10000000"; when 129 => SH_INVALID_CNT_MAX_BINARY := "10000001"; when 130 => SH_INVALID_CNT_MAX_BINARY := "10000010"; when 131 => SH_INVALID_CNT_MAX_BINARY := "10000011"; when 132 => SH_INVALID_CNT_MAX_BINARY := "10000100"; when 133 => SH_INVALID_CNT_MAX_BINARY := "10000101"; when 134 => SH_INVALID_CNT_MAX_BINARY := "10000110"; when 135 => SH_INVALID_CNT_MAX_BINARY := "10000111"; when 136 => SH_INVALID_CNT_MAX_BINARY := "10001000"; when 137 => SH_INVALID_CNT_MAX_BINARY := "10001001"; when 138 => SH_INVALID_CNT_MAX_BINARY := "10001010"; when 139 => SH_INVALID_CNT_MAX_BINARY := "10001011"; when 140 => SH_INVALID_CNT_MAX_BINARY := "10001100"; when 141 => SH_INVALID_CNT_MAX_BINARY := "10001101"; when 142 => SH_INVALID_CNT_MAX_BINARY := "10001110"; when 143 => SH_INVALID_CNT_MAX_BINARY := "10001111"; when 144 => SH_INVALID_CNT_MAX_BINARY := "10010000"; when 145 => SH_INVALID_CNT_MAX_BINARY := "10010001"; when 146 => SH_INVALID_CNT_MAX_BINARY := "10010010"; when 147 => SH_INVALID_CNT_MAX_BINARY := "10010011"; when 148 => SH_INVALID_CNT_MAX_BINARY := "10010100"; when 149 => SH_INVALID_CNT_MAX_BINARY := "10010101"; when 150 => SH_INVALID_CNT_MAX_BINARY := "10010110"; when 151 => SH_INVALID_CNT_MAX_BINARY := "10010111"; when 152 => SH_INVALID_CNT_MAX_BINARY := "10011000"; when 153 => SH_INVALID_CNT_MAX_BINARY := "10011001"; when 154 => SH_INVALID_CNT_MAX_BINARY := "10011010"; when 155 => SH_INVALID_CNT_MAX_BINARY := "10011011"; when 156 => SH_INVALID_CNT_MAX_BINARY := "10011100"; when 157 => SH_INVALID_CNT_MAX_BINARY := "10011101"; when 158 => SH_INVALID_CNT_MAX_BINARY := "10011110"; when 159 => SH_INVALID_CNT_MAX_BINARY := "10011111"; when 160 => SH_INVALID_CNT_MAX_BINARY := "10100000"; when 161 => SH_INVALID_CNT_MAX_BINARY := "10100001"; when 162 => SH_INVALID_CNT_MAX_BINARY := "10100010"; when 163 => SH_INVALID_CNT_MAX_BINARY := "10100011"; when 164 => SH_INVALID_CNT_MAX_BINARY := "10100100"; when 165 => SH_INVALID_CNT_MAX_BINARY := "10100101"; when 166 => SH_INVALID_CNT_MAX_BINARY := "10100110"; when 167 => SH_INVALID_CNT_MAX_BINARY := "10100111"; when 168 => SH_INVALID_CNT_MAX_BINARY := "10101000"; when 169 => SH_INVALID_CNT_MAX_BINARY := "10101001"; when 170 => SH_INVALID_CNT_MAX_BINARY := "10101010"; when 171 => SH_INVALID_CNT_MAX_BINARY := "10101011"; when 172 => SH_INVALID_CNT_MAX_BINARY := "10101100"; when 173 => SH_INVALID_CNT_MAX_BINARY := "10101101"; when 174 => SH_INVALID_CNT_MAX_BINARY := "10101110"; when 175 => SH_INVALID_CNT_MAX_BINARY := "10101111"; when 176 => SH_INVALID_CNT_MAX_BINARY := "10110000"; when 177 => SH_INVALID_CNT_MAX_BINARY := "10110001"; when 178 => SH_INVALID_CNT_MAX_BINARY := "10110010"; when 179 => SH_INVALID_CNT_MAX_BINARY := "10110011"; when 180 => SH_INVALID_CNT_MAX_BINARY := "10110100"; when 181 => SH_INVALID_CNT_MAX_BINARY := "10110101"; when 182 => SH_INVALID_CNT_MAX_BINARY := "10110110"; when 183 => SH_INVALID_CNT_MAX_BINARY := "10110111"; when 184 => SH_INVALID_CNT_MAX_BINARY := "10111000"; when 185 => SH_INVALID_CNT_MAX_BINARY := "10111001"; when 186 => SH_INVALID_CNT_MAX_BINARY := "10111010"; when 187 => SH_INVALID_CNT_MAX_BINARY := "10111011"; when 188 => SH_INVALID_CNT_MAX_BINARY := "10111100"; when 189 => SH_INVALID_CNT_MAX_BINARY := "10111101"; when 190 => SH_INVALID_CNT_MAX_BINARY := "10111110"; when 191 => SH_INVALID_CNT_MAX_BINARY := "10111111"; when 192 => SH_INVALID_CNT_MAX_BINARY := "11000000"; when 193 => SH_INVALID_CNT_MAX_BINARY := "11000001"; when 194 => SH_INVALID_CNT_MAX_BINARY := "11000010"; when 195 => SH_INVALID_CNT_MAX_BINARY := "11000011"; when 196 => SH_INVALID_CNT_MAX_BINARY := "11000100"; when 197 => SH_INVALID_CNT_MAX_BINARY := "11000101"; when 198 => SH_INVALID_CNT_MAX_BINARY := "11000110"; when 199 => SH_INVALID_CNT_MAX_BINARY := "11000111"; when 200 => SH_INVALID_CNT_MAX_BINARY := "11001000"; when 201 => SH_INVALID_CNT_MAX_BINARY := "11001001"; when 202 => SH_INVALID_CNT_MAX_BINARY := "11001010"; when 203 => SH_INVALID_CNT_MAX_BINARY := "11001011"; when 204 => SH_INVALID_CNT_MAX_BINARY := "11001100"; when 205 => SH_INVALID_CNT_MAX_BINARY := "11001101"; when 206 => SH_INVALID_CNT_MAX_BINARY := "11001110"; when 207 => SH_INVALID_CNT_MAX_BINARY := "11001111"; when 208 => SH_INVALID_CNT_MAX_BINARY := "11010000"; when 209 => SH_INVALID_CNT_MAX_BINARY := "11010001"; when 210 => SH_INVALID_CNT_MAX_BINARY := "11010010"; when 211 => SH_INVALID_CNT_MAX_BINARY := "11010011"; when 212 => SH_INVALID_CNT_MAX_BINARY := "11010100"; when 213 => SH_INVALID_CNT_MAX_BINARY := "11010101"; when 214 => SH_INVALID_CNT_MAX_BINARY := "11010110"; when 215 => SH_INVALID_CNT_MAX_BINARY := "11010111"; when 216 => SH_INVALID_CNT_MAX_BINARY := "11011000"; when 217 => SH_INVALID_CNT_MAX_BINARY := "11011001"; when 218 => SH_INVALID_CNT_MAX_BINARY := "11011010"; when 219 => SH_INVALID_CNT_MAX_BINARY := "11011011"; when 220 => SH_INVALID_CNT_MAX_BINARY := "11011100"; when 221 => SH_INVALID_CNT_MAX_BINARY := "11011101"; when 222 => SH_INVALID_CNT_MAX_BINARY := "11011110"; when 223 => SH_INVALID_CNT_MAX_BINARY := "11011111"; when 224 => SH_INVALID_CNT_MAX_BINARY := "11100000"; when 225 => SH_INVALID_CNT_MAX_BINARY := "11100001"; when 226 => SH_INVALID_CNT_MAX_BINARY := "11100010"; when 227 => SH_INVALID_CNT_MAX_BINARY := "11100011"; when 228 => SH_INVALID_CNT_MAX_BINARY := "11100100"; when 229 => SH_INVALID_CNT_MAX_BINARY := "11100101"; when 230 => SH_INVALID_CNT_MAX_BINARY := "11100110"; when 231 => SH_INVALID_CNT_MAX_BINARY := "11100111"; when 232 => SH_INVALID_CNT_MAX_BINARY := "11101000"; when 233 => SH_INVALID_CNT_MAX_BINARY := "11101001"; when 234 => SH_INVALID_CNT_MAX_BINARY := "11101010"; when 235 => SH_INVALID_CNT_MAX_BINARY := "11101011"; when 236 => SH_INVALID_CNT_MAX_BINARY := "11101100"; when 237 => SH_INVALID_CNT_MAX_BINARY := "11101101"; when 238 => SH_INVALID_CNT_MAX_BINARY := "11101110"; when 239 => SH_INVALID_CNT_MAX_BINARY := "11101111"; when 240 => SH_INVALID_CNT_MAX_BINARY := "11110000"; when 241 => SH_INVALID_CNT_MAX_BINARY := "11110001"; when 242 => SH_INVALID_CNT_MAX_BINARY := "11110010"; when 243 => SH_INVALID_CNT_MAX_BINARY := "11110011"; when 244 => SH_INVALID_CNT_MAX_BINARY := "11110100"; when 245 => SH_INVALID_CNT_MAX_BINARY := "11110101"; when 246 => SH_INVALID_CNT_MAX_BINARY := "11110110"; when 247 => SH_INVALID_CNT_MAX_BINARY := "11110111"; when 248 => SH_INVALID_CNT_MAX_BINARY := "11111000"; when 249 => SH_INVALID_CNT_MAX_BINARY := "11111001"; when 250 => SH_INVALID_CNT_MAX_BINARY := "11111010"; when 251 => SH_INVALID_CNT_MAX_BINARY := "11111011"; when 252 => SH_INVALID_CNT_MAX_BINARY := "11111100"; when 253 => SH_INVALID_CNT_MAX_BINARY := "11111101"; when 254 => SH_INVALID_CNT_MAX_BINARY := "11111110"; when 255 => SH_INVALID_CNT_MAX_BINARY := "11111111"; when others => assert FALSE report "Error : SH_INVALID_CNT_MAX is not in range 0...255." severity error; end case; case ALIGN_COMMA_WORD is when 1 => ALIGN_COMMA_WORD_BINARY := "00"; when 2 => ALIGN_COMMA_WORD_BINARY := "01"; when 4 => ALIGN_COMMA_WORD_BINARY := "10"; when others => assert FALSE report "Error : ALIGN_COMMA_WORD is not in 1, 2, 4." severity error; end case; case DEC_MCOMMA_DETECT is when FALSE => DEC_MCOMMA_DETECT_BINARY := '0'; when TRUE => DEC_MCOMMA_DETECT_BINARY := '1'; when others => assert FALSE report "Error : DEC_MCOMMA_DETECT is neither TRUE nor FALSE." severity error; end case; case DEC_PCOMMA_DETECT is when FALSE => DEC_PCOMMA_DETECT_BINARY := '0'; when TRUE => DEC_PCOMMA_DETECT_BINARY := '1'; when others => assert FALSE report "Error : DEC_PCOMMA_DETECT is neither TRUE nor FALSE." severity error; end case; case DEC_VALID_COMMA_ONLY is when FALSE => DEC_VALID_COMMA_ONLY_BINARY := '0'; when TRUE => DEC_VALID_COMMA_ONLY_BINARY := '1'; when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY is neither TRUE nor FALSE." severity error; end case; case MCOMMA_DETECT is when FALSE => MCOMMA_DETECT_BINARY := '0'; when TRUE => MCOMMA_DETECT_BINARY := '1'; when others => assert FALSE report "Error : MCOMMA_DETECT is neither TRUE nor FALSE." severity error; end case; case PCOMMA_DETECT is when FALSE => PCOMMA_DETECT_BINARY := '0'; when TRUE => PCOMMA_DETECT_BINARY := '1'; when others => assert FALSE report "Error : PCOMMA_DETECT is neither TRUE nor FALSE." severity error; end case; case COMMA32 is when FALSE => COMMA32_BINARY := '0'; when TRUE => COMMA32_BINARY := '1'; when others => assert FALSE report "Error : COMMA32 is neither TRUE nor FALSE." severity error; end case; case RXUSRDIVISOR is when 1 => RXUSRDIVISOR_BINARY := "00001"; when 2 => RXUSRDIVISOR_BINARY := "00010"; when 4 => RXUSRDIVISOR_BINARY := "00100"; when 8 => RXUSRDIVISOR_BINARY := "01000"; when 16 => RXUSRDIVISOR_BINARY := "10000"; when others => assert FALSE report "Error : RXUSRDIVISOR is not in 1, 2, 4, 8, 16." severity error; end case; case SAMPLE_8X is when FALSE => SAMPLE_8X_BINARY := '0'; when TRUE => SAMPLE_8X_BINARY := '1'; when others => assert FALSE report "Error : SAMPLE_8X is neither TRUE nor FALSE." severity error; end case; case ENABLE_DCDR is when FALSE => ENABLE_DCDR_BINARY := '0'; when TRUE => ENABLE_DCDR_BINARY := '1'; when others => assert FALSE report "Error : ENABLE_DCDR is neither TRUE nor FALSE." severity error; end case; case REPEATER is when FALSE => REPEATER_BINARY := '0'; when TRUE => REPEATER_BINARY := '1'; when others => assert FALSE report "Error : REPEATER is neither TRUE nor FALSE." severity error; end case; case RXBY_32 is when FALSE => RXBY_32_BINARY := '0'; when TRUE => RXBY_32_BINARY := '1'; when others => assert FALSE report "Error : RXBY_32 is neither TRUE nor FALSE." severity error; end case; -- case TXFDCAL_CLOCK_DIVIDE is if((TXFDCAL_CLOCK_DIVIDE = "NONE") or (TXFDCAL_CLOCK_DIVIDE = "none")) then TXFDCAL_CLOCK_DIVIDE_BINARY := "00"; elsif((TXFDCAL_CLOCK_DIVIDE = "TWO") or (TXFDCAL_CLOCK_DIVIDE = "two")) then TXFDCAL_CLOCK_DIVIDE_BINARY := "01"; elsif((TXFDCAL_CLOCK_DIVIDE = "FOUR") or (TXFDCAL_CLOCK_DIVIDE = "four")) then TXFDCAL_CLOCK_DIVIDE_BINARY := "10"; else assert FALSE report "Error : TXFDCAL_CLOCK_DIVIDE = is not NONE, TWO, FOUR." severity error; end if; -- end case; -- case RXFDCAL_CLOCK_DIVIDE is if((RXFDCAL_CLOCK_DIVIDE = "NONE") or (RXFDCAL_CLOCK_DIVIDE = "none")) then RXFDCAL_CLOCK_DIVIDE_BINARY := "00"; elsif((RXFDCAL_CLOCK_DIVIDE = "TWO") or (RXFDCAL_CLOCK_DIVIDE = "two")) then RXFDCAL_CLOCK_DIVIDE_BINARY := "01"; elsif((RXFDCAL_CLOCK_DIVIDE = "FOUR") or (RXFDCAL_CLOCK_DIVIDE = "four")) then RXFDCAL_CLOCK_DIVIDE_BINARY := "10"; else assert FALSE report "Error : RXFDCAL_CLOCK_DIVIDE = is not NONE, TWO, FOUR." severity error; end if; -- end case; case RXVCO_CTRL_ENABLE is when FALSE => RXVCO_CTRL_ENABLE_BINARY := '0'; when TRUE => RXVCO_CTRL_ENABLE_BINARY := '1'; when others => assert FALSE report "Error : RXVCO_CTRL_ENABLE is neither TRUE nor FALSE." severity error; end case; case VCO_CTRL_ENABLE is when FALSE => VCO_CTRL_ENABLE_BINARY := '0'; when TRUE => VCO_CTRL_ENABLE_BINARY := '1'; when others => assert FALSE report "Error : VCO_CTRL_ENABLE is neither TRUE nor FALSE." severity error; end case; case RXCRCCLOCKDOUBLE is when FALSE => RXCRCCLOCKDOUBLE_BINARY := '0'; when TRUE => RXCRCCLOCKDOUBLE_BINARY := '1'; when others => assert FALSE report "Error : RXCRCCLOCKDOUBLE is neither TRUE nor FALSE." severity error; end case; case RXCRCINVERTGEN is when FALSE => RXCRCINVERTGEN_BINARY := '0'; when TRUE => RXCRCINVERTGEN_BINARY := '1'; when others => assert FALSE report "Error : RXCRCINVERTGEN is neither TRUE nor FALSE." severity error; end case; case RXCRCSAMECLOCK is when FALSE => RXCRCSAMECLOCK_BINARY := '0'; when TRUE => RXCRCSAMECLOCK_BINARY := '1'; when others => assert FALSE report "Error : RXCRCSAMECLOCK is neither TRUE nor FALSE." severity error; end case; case RXCRCENABLE is when FALSE => RXCRCENABLE_BINARY := '0'; when TRUE => RXCRCENABLE_BINARY := '1'; when others => assert FALSE report "Error : RXCRCENABLE is neither TRUE nor FALSE." severity error; end case; case TXCRCCLOCKDOUBLE is when FALSE => TXCRCCLOCKDOUBLE_BINARY := '0'; when TRUE => TXCRCCLOCKDOUBLE_BINARY := '1'; when others => assert FALSE report "Error : TXCRCCLOCKDOUBLE is neither TRUE nor FALSE." severity error; end case; case TXCRCINVERTGEN is when FALSE => TXCRCINVERTGEN_BINARY := '0'; when TRUE => TXCRCINVERTGEN_BINARY := '1'; when others => assert FALSE report "Error : TXCRCINVERTGEN is neither TRUE nor FALSE." severity error; end case; case TXCRCSAMECLOCK is when FALSE => TXCRCSAMECLOCK_BINARY := '0'; when TRUE => TXCRCSAMECLOCK_BINARY := '1'; when others => assert FALSE report "Error : TXCRCSAMECLOCK is neither TRUE nor FALSE." severity error; end case; case TXCRCENABLE is when FALSE => TXCRCENABLE_BINARY := '0'; when TRUE => TXCRCENABLE_BINARY := '1'; when others => assert FALSE report "Error : TXCRCENABLE is neither TRUE nor FALSE." severity error; end case; case RXCLK0_FORCE_PMACLK is when FALSE => RXCLK0_FORCE_PMACLK_BINARY := '0'; when TRUE => RXCLK0_FORCE_PMACLK_BINARY := '1'; when others => assert FALSE report "Error : RXCLK0_FORCE_PMACLK is neither TRUE nor FALSE." severity error; end case; case TXCLK0_FORCE_PMACLK is when FALSE => TXCLK0_FORCE_PMACLK_BINARY := '0'; when TRUE => TXCLK0_FORCE_PMACLK_BINARY := '1'; when others => assert FALSE report "Error : TXCLK0_FORCE_PMACLK is neither TRUE nor FALSE." severity error; end case; case TXOUTCLK1_USE_SYNC is when FALSE => TXOUTCLK1_USE_SYNC_BINARY := '0'; when TRUE => TXOUTCLK1_USE_SYNC_BINARY := '1'; when others => assert FALSE report "Error : TXOUTCLK1_USE_SYNC is neither TRUE nor FALSE." severity error; end case; case RXRECCLK1_USE_SYNC is when FALSE => RXRECCLK1_USE_SYNC_BINARY := '0'; when TRUE => RXRECCLK1_USE_SYNC_BINARY := '1'; when others => assert FALSE report "Error : RXRECCLK1_USE_SYNC is neither TRUE nor FALSE." severity error; end case; -- case RXPMACLKSEL is if((RXPMACLKSEL = "REFCLK1") or (RXPMACLKSEL = "refclk1")) then RXPMACLKSEL_BINARY := "00"; elsif((RXPMACLKSEL = "REFCLK2") or (RXPMACLKSEL = "refclk2")) then RXPMACLKSEL_BINARY := "01"; elsif((RXPMACLKSEL = "GREFCLK") or (RXPMACLKSEL = "grefclk")) then RXPMACLKSEL_BINARY := "10"; else assert FALSE report "Error : RXPMACLKSEL = is not REFCLK1, REFCLK2, GREFCLK." severity error; end if; -- end case; -- case TXABPMACLKSEL is if((TXABPMACLKSEL = "REFCLK1") or (TXABPMACLKSEL = "refclk1")) then TXABPMACLKSEL_BINARY := "00"; elsif((TXABPMACLKSEL = "REFCLK2") or (TXABPMACLKSEL = "refclk2")) then TXABPMACLKSEL_BINARY := "01"; elsif((TXABPMACLKSEL = "GREFCLK") or (TXABPMACLKSEL = "grefclk")) then TXABPMACLKSEL_BINARY := "10"; else assert FALSE report "Error : TXABPMACLKSEL = is not REFCLK1, REFCLK2, GREFCLK." severity error; end if; -- end case; case BANDGAPSEL is when FALSE => BANDGAPSEL_BINARY := '0'; when TRUE => BANDGAPSEL_BINARY := '1'; when others => assert FALSE report "Error : BANDGAPSEL is neither TRUE nor FALSE." severity error; end case; case BIASRESSEL is when FALSE => BIASRESSEL_BINARY := '0'; when TRUE => BIASRESSEL_BINARY := '1'; when others => assert FALSE report "Error : BIASRESSEL is neither TRUE nor FALSE." severity error; end case; case TXPHASESEL is when FALSE => TXPHASESEL_BINARY := '0'; when TRUE => TXPHASESEL_BINARY := '1'; when others => assert FALSE report "Error : TXPHASESEL is neither TRUE nor FALSE." severity error; end case; case PMACLKENABLE is when FALSE => PMACLKENABLE_BINARY := '0'; when TRUE => PMACLKENABLE_BINARY := '1'; when others => assert FALSE report "Error : PMACLKENABLE is neither TRUE nor FALSE." severity error; end case; case PMACOREPWRENABLE is when FALSE => PMACOREPWRENABLE_BINARY := '0'; when TRUE => PMACOREPWRENABLE_BINARY := '1'; when others => assert FALSE report "Error : PMACOREPWRENABLE is neither TRUE nor FALSE." severity error; end case; case PMA_BIT_SLIP is when FALSE => PMA_BIT_SLIP_BINARY := '0'; when TRUE => PMA_BIT_SLIP_BINARY := '1'; when others => assert FALSE report "Error : PMA_BIT_SLIP is neither TRUE nor FALSE." severity error; end case; case RXLB is when FALSE => RXLB_BINARY := '0'; when TRUE => RXLB_BINARY := '1'; when others => assert FALSE report "Error : RXLB is neither TRUE nor FALSE." severity error; end case; case RXDCCOUPLE is when FALSE => RXDCCOUPLE_BINARY := '0'; when TRUE => RXDCCOUPLE_BINARY := '1'; when others => assert FALSE report "Error : RXDCCOUPLE is neither TRUE nor FALSE." severity error; end case; case RXDIGRESET is when FALSE => RXDIGRESET_BINARY := '0'; when TRUE => RXDIGRESET_BINARY := '1'; when others => assert FALSE report "Error : RXDIGRESET is neither TRUE nor FALSE." severity error; end case; case RXCPTST is when FALSE => RXCPTST_BINARY := '0'; when TRUE => RXCPTST_BINARY := '1'; when others => assert FALSE report "Error : RXCPTST is neither TRUE nor FALSE." severity error; end case; case RXPDDTST is when FALSE => RXPDDTST_BINARY := '0'; when TRUE => RXPDDTST_BINARY := '1'; when others => assert FALSE report "Error : RXPDDTST is neither TRUE nor FALSE." severity error; end case; case RXACTST is when FALSE => RXACTST_BINARY := '0'; when TRUE => RXACTST_BINARY := '1'; when others => assert FALSE report "Error : RXACTST is neither TRUE nor FALSE." severity error; end case; case RXAFETST is when FALSE => RXAFETST_BINARY := '0'; when TRUE => RXAFETST_BINARY := '1'; when others => assert FALSE report "Error : RXAFETST is neither TRUE nor FALSE." severity error; end case; case RXLKAPD is when FALSE => RXLKAPD_BINARY := '0'; when TRUE => RXLKAPD_BINARY := '1'; when others => assert FALSE report "Error : RXLKAPD is neither TRUE nor FALSE." severity error; end case; case RXRSDPD is when FALSE => RXRSDPD_BINARY := '0'; when TRUE => RXRSDPD_BINARY := '1'; when others => assert FALSE report "Error : RXRSDPD is neither TRUE nor FALSE." severity error; end case; case RXRCPPD is when FALSE => RXRCPPD_BINARY := '0'; when TRUE => RXRCPPD_BINARY := '1'; when others => assert FALSE report "Error : RXRCPPD is neither TRUE nor FALSE." severity error; end case; case RXRPDPD is when FALSE => RXRPDPD_BINARY := '0'; when TRUE => RXRPDPD_BINARY := '1'; when others => assert FALSE report "Error : RXRPDPD is neither TRUE nor FALSE." severity error; end case; case RXAFEPD is when FALSE => RXAFEPD_BINARY := '0'; when TRUE => RXAFEPD_BINARY := '1'; when others => assert FALSE report "Error : RXAFEPD is neither TRUE nor FALSE." severity error; end case; case RXPD is when FALSE => RXPD_BINARY := '0'; when TRUE => RXPD_BINARY := '1'; when others => assert FALSE report "Error : RXPD is neither TRUE nor FALSE." severity error; end case; case TXOUTDIV2SEL is when 1 => TXOUTDIV2SEL_BINARY := "0001"; when 2 => TXOUTDIV2SEL_BINARY := "0010"; when 4 => TXOUTDIV2SEL_BINARY := "0011"; when 8 => TXOUTDIV2SEL_BINARY := "0100"; when 16 => TXOUTDIV2SEL_BINARY := "0101"; when 32 => TXOUTDIV2SEL_BINARY := "0110"; when others => assert FALSE report "Error : TXOUTDIV2SEL is not in 1, 2, 4, 8, 16, 32." severity error; end case; case TXPLLNDIVSEL is when 8 => TXPLLNDIVSEL_BINARY := "0000"; when 10 => TXPLLNDIVSEL_BINARY := "0010"; when 16 => TXPLLNDIVSEL_BINARY := "0100"; when 20 => TXPLLNDIVSEL_BINARY := "0110"; when 32 => TXPLLNDIVSEL_BINARY := "1000"; when 40 => TXPLLNDIVSEL_BINARY := "1010"; when others => assert FALSE report "Error : TXPLLNDIVSEL is not in 8, 10, 16, 20, 32, 40." severity error; end case; case TXCPSEL is when FALSE => TXCPSEL_BINARY := '0'; when TRUE => TXCPSEL_BINARY := '1'; when others => assert FALSE report "Error : TXCPSEL is neither TRUE nor FALSE." severity error; end case; case TXAPD is when FALSE => TXAPD_BINARY := '0'; when TRUE => TXAPD_BINARY := '1'; when others => assert FALSE report "Error : TXAPD is neither TRUE nor FALSE." severity error; end case; case TXLVLSHFTPD is when FALSE => TXLVLSHFTPD_BINARY := '0'; when TRUE => TXLVLSHFTPD_BINARY := '1'; when others => assert FALSE report "Error : TXLVLSHFTPD is neither TRUE nor FALSE." severity error; end case; case TXPRE_TAP_PD is when FALSE => TXPRE_TAP_PD_BINARY := '0'; when TRUE => TXPRE_TAP_PD_BINARY := '1'; when others => assert FALSE report "Error : TXPRE_TAP_PD is neither TRUE nor FALSE." severity error; end case; case TXDIGPD is when FALSE => TXDIGPD_BINARY := '0'; when TRUE => TXDIGPD_BINARY := '1'; when others => assert FALSE report "Error : TXDIGPD is neither TRUE nor FALSE." severity error; end case; case TXHIGHSIGNALEN is when FALSE => TXHIGHSIGNALEN_BINARY := '0'; when TRUE => TXHIGHSIGNALEN_BINARY := '1'; when others => assert FALSE report "Error : TXHIGHSIGNALEN is neither TRUE nor FALSE." severity error; end case; case TXAREFBIASSEL is when FALSE => TXAREFBIASSEL_BINARY := '0'; when TRUE => TXAREFBIASSEL_BINARY := '1'; when others => assert FALSE report "Error : TXAREFBIASSEL is neither TRUE nor FALSE." severity error; end case; case TXSLEWRATE is when FALSE => TXSLEWRATE_BINARY := '0'; when TRUE => TXSLEWRATE_BINARY := '1'; when others => assert FALSE report "Error : TXSLEWRATE is neither TRUE nor FALSE." severity error; end case; case TXPOST_TAP_PD is when FALSE => TXPOST_TAP_PD_BINARY := '0'; when TRUE => TXPOST_TAP_PD_BINARY := '1'; when others => assert FALSE report "Error : TXPOST_TAP_PD is neither TRUE nor FALSE." severity error; end case; case TXPD is when FALSE => TXPD_BINARY := '0'; when TRUE => TXPD_BINARY := '1'; when others => assert FALSE report "Error : TXPD is neither TRUE nor FALSE." severity error; end case; case RXOUTDIV2SEL is when 1 => RXOUTDIV2SEL_BINARY := "00010001"; when 2 => RXOUTDIV2SEL_BINARY := "00100010"; when 4 => RXOUTDIV2SEL_BINARY := "00110011"; when 8 => RXOUTDIV2SEL_BINARY := "01000100"; when 16 => RXOUTDIV2SEL_BINARY := "01010101"; when 32 => RXOUTDIV2SEL_BINARY := "01100110"; when others => assert FALSE report "Error : RXOUTDIV2SEL is not in 1, 2, 4, 8, 16, 32." severity error; end case; case RXPLLNDIVSEL is when 8 => RXPLLNDIVSEL_BINARY := "0000"; when 10 => RXPLLNDIVSEL_BINARY := "0010"; when 16 => RXPLLNDIVSEL_BINARY := "0100"; when 20 => RXPLLNDIVSEL_BINARY := "0110"; when 32 => RXPLLNDIVSEL_BINARY := "1000"; when 40 => RXPLLNDIVSEL_BINARY := "1010"; when others => assert FALSE report "Error : RXPLLNDIVSEL is not in 8, 10, 16, 20, 32, 40." severity error; end case; case RXDIGRX is when FALSE => RXDIGRX_BINARY := '0'; when TRUE => RXDIGRX_BINARY := '1'; when others => assert FALSE report "Error : RXDIGRX is neither TRUE nor FALSE." severity error; end case; case RXCPSEL is when FALSE => RXCPSEL_BINARY := '0'; when TRUE => RXCPSEL_BINARY := '1'; when others => assert FALSE report "Error : RXCPSEL is neither TRUE nor FALSE." severity error; end case; case RXAPD is when FALSE => RXAPD_BINARY := '0'; when TRUE => RXAPD_BINARY := '1'; when others => assert FALSE report "Error : RXAPD is neither TRUE nor FALSE." severity error; end case; synDigCfgChnBnd1(63) <= '0';--RESERVED_CB1; synDigCfgChnBnd1(62) <= TX_BUFFER_USE_BINARY; synDigCfgChnBnd1(61) <= RX_BUFFER_USE_BINARY; synDigCfgChnBnd1(60 downto 58) <= CHAN_BOND_SEQ_LEN_BINARY; synDigCfgChnBnd1(57) <= CHAN_BOND_SEQ_2_USE_BINARY; synDigCfgChnBnd1(56) <= CHAN_BOND_ONE_SHOT_BINARY; synDigCfgChnBnd1(55 downto 54) <= CHAN_BOND_MODE_BINARY; synDigCfgChnBnd1(53 downto 48) <= CHAN_BOND_LIMIT_BINARY; synDigCfgChnBnd1(47 downto 44) <= CHAN_BOND_SEQ_1_MASK_BINARY; synDigCfgChnBnd1(43 downto 33) <= CHAN_BOND_SEQ_1_4_BINARY; synDigCfgChnBnd1(32 downto 22) <= CHAN_BOND_SEQ_1_3_BINARY; synDigCfgChnBnd1(21 downto 11) <= CHAN_BOND_SEQ_1_2_BINARY; synDigCfgChnBnd1(10 downto 0) <= CHAN_BOND_SEQ_1_1_BINARY; synDigCfgChnBnd2(63 downto 56) <= "00000000";-- CHAN_BOND_TUNE; synDigCfgChnBnd2(55) <= '0'; -- unused synDigCfgChnBnd2(54) <= '0'; -- unused synDigCfgChnBnd2(53) <= CCCB_ARBITRATOR_DISABLE_BINARY; synDigCfgChnBnd2(52) <= OPPOSITE_SELECT_BINARY; synDigCfgChnBnd2(51) <= POWER_ENABLE_BINARY; synDigCfgChnBnd2(50 downto 48) <= "000"; synDigCfgChnBnd2(47 downto 44) <= CHAN_BOND_SEQ_2_MASK_BINARY; synDigCfgChnBnd2(43 downto 33) <= CHAN_BOND_SEQ_2_4_BINARY; synDigCfgChnBnd2(32 downto 22) <= CHAN_BOND_SEQ_2_3_BINARY; synDigCfgChnBnd2(21 downto 11) <= CHAN_BOND_SEQ_2_2_BINARY; synDigCfgChnBnd2(10 downto 0) <= CHAN_BOND_SEQ_2_1_BINARY; synDigCfgClkCor1(63 downto 62) <= RXDATA_SEL_BINARY; synDigCfgClkCor1(61 downto 60) <= TXDATA_SEL_BINARY; synDigCfgClkCor1(59) <= '0';--RESERVED_CCB; synDigCfgClkCor1(58 downto 53) <= CLK_COR_MIN_LAT_BINARY; synDigCfgClkCor1(52) <= '0';--RESERVED_CCA; synDigCfgClkCor1(51) <= PCS_BIT_SLIP_BINARY; synDigCfgClkCor1(50) <= DIGRX_SYNC_MODE_BINARY; synDigCfgClkCor1(49 downto 48) <= DIGRX_FWDCLK_BINARY; synDigCfgClkCor1(47 downto 44) <= CLK_COR_SEQ_1_MASK_BINARY; synDigCfgClkCor1(43 downto 33) <= CLK_COR_SEQ_1_4_BINARY; synDigCfgClkCor1(32 downto 22) <= CLK_COR_SEQ_1_3_BINARY; synDigCfgClkCor1(21 downto 11) <= CLK_COR_SEQ_1_2_BINARY; synDigCfgClkCor1(10 downto 0) <= CLK_COR_SEQ_1_1_BINARY; synDigCfgClkCor2(63 downto 56) <= "00000000"; --RX_LOS_THRESHOLD_BINARY; synDigCfgClkCor2(55 downto 48) <= "00000000"; --RX_LOS_INVALID_INCR_BINARY; synDigCfgClkCor2(47 downto 44) <= CLK_COR_SEQ_2_MASK_BINARY; synDigCfgClkCor2(43 downto 33) <= CLK_COR_SEQ_2_4_BINARY; synDigCfgClkCor2(32 downto 22) <= CLK_COR_SEQ_2_3_BINARY; synDigCfgClkCor2(21 downto 11) <= CLK_COR_SEQ_2_2_BINARY; synDigCfgClkCor2(10 downto 0) <= CLK_COR_SEQ_2_1_BINARY; synDigCfgMisc(63) <= RXRECCLK1_USE_SYNC_BINARY; synDigCfgMisc(62) <= TXOUTCLK1_USE_SYNC_BINARY; synDigCfgMisc(61) <= TXCLK0_FORCE_PMACLK_BINARY; synDigCfgMisc(60) <= RXCLK0_FORCE_PMACLK_BINARY; synDigCfgMisc(59 downto 58) <= TX_CLOCK_DIVIDER_BINARY; synDigCfgMisc(57 downto 56) <= RX_CLOCK_DIVIDER_BINARY; synDigCfgMisc(55) <= TXCRCENABLE_BINARY; synDigCfgMisc(54) <= TXCRCSAMECLOCK_BINARY; synDigCfgMisc(53) <= TXCRCINVERTGEN_BINARY; synDigCfgMisc(52) <= TXCRCCLOCKDOUBLE_BINARY; synDigCfgMisc(51) <= RXCRCENABLE_BINARY; synDigCfgMisc(50) <= RXCRCSAMECLOCK_BINARY; synDigCfgMisc(49) <= RXCRCINVERTGEN_BINARY; synDigCfgMisc(48) <= RXCRCCLOCKDOUBLE_BINARY; synDigCfgMisc(47 downto 46) <= RXFDCAL_CLOCK_DIVIDE_BINARY; synDigCfgMisc(45 downto 44) <= TXFDCAL_CLOCK_DIVIDE_BINARY; synDigCfgMisc(43) <= RXBY_32_BINARY; synDigCfgMisc(42) <= REPEATER_BINARY; synDigCfgMisc(41) <= ENABLE_DCDR_BINARY; synDigCfgMisc(40) <= SAMPLE_8X_BINARY; synDigCfgMisc(39 downto 37) <= DCDR_FILTER_BINARY; synDigCfgMisc(36 downto 32) <= RXUSRDIVISOR_BINARY; synDigCfgMisc(31 downto 24) <= SH_INVALID_CNT_MAX_BINARY; synDigCfgMisc(23 downto 16) <= SH_CNT_MAX_BINARY; synDigCfgMisc(15) <= '0';--RESERVED_M2; synDigCfgMisc(14) <= CLK_COR_8B10B_DE_BINARY; synDigCfgMisc(13) <= CLK_CORRECT_USE_BINARY; synDigCfgMisc(12 downto 10) <= CLK_COR_SEQ_LEN_BINARY; synDigCfgMisc(9) <= CLK_COR_SEQ_DROP_BINARY; synDigCfgMisc(8) <= CLK_COR_SEQ_2_USE_BINARY; synDigCfgMisc(7) <= '0';--TXCLK0_INVERT_PMALEAF; synDigCfgMisc(6) <= '0';--RXCLK0_INVERT_PMALEAF; synDigCfgMisc(5 downto 0) <= CLK_COR_MAX_LAT_BINARY; synDigCfgComma1(63 downto 42) <= "0000000000000000000000";--COMMA_32B_MASK; synDigCfgComma1(41 downto 32) <= COMMA_10B_MASK_BINARY; synDigCfgComma1(31 downto 8) <= "000000000000000000000000";--RESERVED_CM; synDigCfgComma1(7) <= COMMA32_BINARY; synDigCfgComma1(6) <= PCOMMA_DETECT_BINARY; synDigCfgComma1(5) <= MCOMMA_DETECT_BINARY; synDigCfgComma1(4) <= DEC_VALID_COMMA_ONLY_BINARY; synDigCfgComma1(3) <= DEC_PCOMMA_DETECT_BINARY; synDigCfgComma1(2) <= DEC_MCOMMA_DETECT_BINARY; synDigCfgComma1(1 downto 0) <= ALIGN_COMMA_WORD_BINARY; synDigCfgComma2(63 downto 32) <= PCOMMA_32B_VALUE_BINARY; synDigCfgComma2(31 downto 0) <= MCOMMA_32B_VALUE_BINARY; synDigCfgSynPmaFD(63) <= '1';-- AUTO_CAL; synDigCfgSynPmaFD(62 downto 53) <= VCODAC_INIT_BINARY; synDigCfgSynPmaFD(52 downto 51) <= "00";--SLOWDOWN_CAL; synDigCfgSynPmaFD(50) <= '0';-- BYPASS_FDET; synDigCfgSynPmaFD(49 downto 48) <= LOOPCAL_WAIT_BINARY; synDigCfgSynPmaFD(47) <= '0';-- BYPASS_CAL; synDigCfgSynPmaFD(46 downto 44) <= FDET_HYS_CAL_BINARY; synDigCfgSynPmaFD(43 downto 41) <= FDET_LCK_CAL_BINARY; synDigCfgSynPmaFD(40 downto 38) <= FDET_HYS_SEL_BINARY; synDigCfgSynPmaFD(37 downto 35) <= FDET_LCK_SEL_BINARY; synDigCfgSynPmaFD(34) <= VCO_CTRL_ENABLE_BINARY; synDigCfgSynPmaFD(33 downto 32) <= CYCLE_LIMIT_SEL_BINARY; synDigCfgSynPmaFD(31) <= '1';-- RXAUTO_CAL; synDigCfgSynPmaFD(30 downto 21) <= RXVCODAC_INIT_BINARY; synDigCfgSynPmaFD(20 downto 19) <= RXSLOWDOWN_CAL_BINARY; synDigCfgSynPmaFD(18) <= '0';-- RXBYPASS_FDET; synDigCfgSynPmaFD(17 downto 16) <= RXLOOPCAL_WAIT_BINARY; synDigCfgSynPmaFD(15) <= '0';-- RXBYPASS_CAL; synDigCfgSynPmaFD(14 downto 12) <= RXFDET_HYS_CAL_BINARY; synDigCfgSynPmaFD(11 downto 9) <= RXFDET_LCK_CAL_BINARY; synDigCfgSynPmaFD(8 downto 6) <= RXFDET_HYS_SEL_BINARY; synDigCfgSynPmaFD(5 downto 3) <= RXFDET_LCK_SEL_BINARY; synDigCfgSynPmaFD(2) <= RXVCO_CTRL_ENABLE_BINARY; synDigCfgSynPmaFD(1 downto 0) <= RXCYCLE_LIMIT_SEL_BINARY; synDigCfgCrc(63 downto 32) <= TXCRCINITVAL_BINARY; synDigCfgCrc(31 downto 0) <= RXCRCINITVAL_BINARY; PMACFG(63 downto 62) <= "00"; PMACFG(61 downto 60) <= RXPMACLKSEL_BINARY; PMACFG(59 downto 58) <= RXPMACLKSEL_BINARY; PMACFG(57 downto 56) <= TXABPMACLKSEL_BINARY; PMACFG(55 downto 48) <= "00000000"; PMACFG(47) <= '0';-- PMATUNE; PMACFG(46 downto 42) <= "00000";-- TXREGCTRL; PMACFG(41 downto 37) <= RXAREGCTRL_BINARY; PMACFG(36 downto 32) <= PMAVBGCTRL_BINARY; PMACFG(31) <= BANDGAPSEL_BINARY; PMACFG(30 downto 27) <= PMAIREFTRIM_BINARY; PMACFG(26 downto 25) <= IREFBIASMODE_BINARY; PMACFG(24) <= BIASRESSEL_BINARY; PMACFG(23 downto 20) <= PMAVREFTRIM_BINARY; PMACFG(19) <= '0';--VREFSELECT; PMACFG(18 downto 17) <= VREFBIASMODE_BINARY; PMACFG(16) <= '0';-- PMABIASPD; PMACFG(15 downto 14) <= "00"; PMACFG(13) <= '0'; PMACFG(12) <= '0';-- ATBBUMPEN; PMACFG(11) <= '0';-- NATBENABLE; PMACFG(10 downto 5) <= "000000"; PMACFG(4) <= TXPHASESEL_BINARY; PMACFG(3) <= '0'; --UNUSED PMACFG(2) <= '0';-- PMACTRL; PMACFG(1) <= PMACLKENABLE_BINARY;--'0';-- PMACLKENABLEPD; PMACFG(0) <= PMACOREPWRENABLE_BINARY; PMACFG2(63 downto 18) <= "0000000000000000000000000000000000000000000000"; PMACFG2(17 downto 0) <= "000000000000000000"; RXAFECFG(63 downto 58) <= RXMODE_BINARY; RXAFECFG(57) <= PMA_BIT_SLIP_BINARY; RXAFECFG(56 downto 55) <= RXASYNCDIVIDE_BINARY; RXAFECFG(54 downto 49) <= RXCLKMODE_BINARY; RXAFECFG(48) <= RXLB_BINARY; RXAFECFG(47 downto 46) <= RXFETUNE_BINARY; RXAFECFG(45 downto 43) <= RXRCPADJ_BINARY;--"00";-- RXRCPADJ; RXAFECFG(42 downto 41) <= RXRIBADJ_BINARY; RXAFECFG(40 downto 32) <= RXAFEEQ_BINARY; RXAFECFG(31 downto 30) <= RXCMADJ_BINARY; RXAFECFG(29 downto 24) <= RXCDRLOS_BINARY; RXAFECFG(23) <= '0'; RXAFECFG(22) <= RXDCCOUPLE_BINARY; RXAFECFG(21) <= '0'; RXAFECFG(20 downto 16) <= RXLKADJ_BINARY; RXAFECFG(15) <= RXDIGRESET_BINARY; RXAFECFG(14 downto 12) <= RXFECONTROL2_BINARY; RXAFECFG(11) <= RXCPTST_BINARY; RXAFECFG(10) <= RXPDDTST_BINARY; RXAFECFG(9) <= RXACTST_BINARY; RXAFECFG(8) <= RXAFETST_BINARY; RXAFECFG(7 downto 6) <= RXFECONTROL1_BINARY; RXAFECFG(5) <= RXLKAPD_BINARY; RXAFECFG(4) <= RXRSDPD_BINARY; RXAFECFG(3) <= RXRCPPD_BINARY; RXAFECFG(2) <= RXRPDPD_BINARY; RXAFECFG(1) <= RXAFEPD_BINARY; RXAFECFG(0) <= RXPD_BINARY; RXAEQCFG(63 downto 0) <= RXEQ_BINARY; TXCLCFG(63 downto 60) <= TXOUTDIV2SEL_BINARY; TXCLCFG(59 downto 56) <= TXPLLNDIVSEL_BINARY; TXCLCFG(55 downto 54) <= TXCLMODE_BINARY; TXCLCFG(53 downto 50) <= TXLOOPFILT_BINARY; TXCLCFG(49) <= '0';-- UNUSED; TXCLCFG(48) <= '0';-- UNUSED; TXCLCFG(47 downto 35) <= TXTUNE_BINARY; TXCLCFG(34) <= '0';-- UNUSED; TXCLCFG(33) <= '0';-- --UNUSED; TXCLCFG(32) <= TXCPSEL_BINARY; TXCLCFG(31) <= '0'; --TXDACTST TXCLCFG(30 downto 27) <= TXOUTDIV2SEL_BINARY; TXCLCFG(26 downto 17) <= TXCTRL1_BINARY; TXCLCFG(16) <= '0';-- TXQPPD; TXCLCFG(15) <= '0';-- TXCMFPD; TXCLCFG(14) <= '0';-- TXVCOPD; TXCLCFG(13) <= '0';-- TXADCADJPD; TXCLCFG(12) <= '0';-- TXDIVPD; TXCLCFG(11) <= '0';-- TXBIASPD; TXCLCFG(10) <= '0';-- TXDIVBUFPD; TXCLCFG(9) <= '0';-- TXVCOBUFPD; TXCLCFG(8) <= TXAPD_BINARY; TXCLCFG(7) <= '0';-- TXAPTST; TXCLCFG(6) <= '0';-- TXCMFTST; TXCLCFG(5) <= '0';-- TXFILTTST; TXCLCFG(4) <= '0';-- TXDIVTST; TXCLCFG(3) <= '0';-- TXPFDTST; TXCLCFG(2) <= '0';-- TXVCOBUFTST; TXCLCFG(1) <= '0';-- TXDIVBUFTST; TXCLCFG(0) <= '0';-- TXVCOTST; TXACFG(63 downto 60) <= "0000"; TXACFG(59) <= TXLVLSHFTPD_BINARY; TXACFG(58 downto 56) <= TXPRE_PRDRV_DAC_BINARY; TXACFG(55) <= TXPRE_TAP_PD_BINARY; TXACFG(54 downto 53) <= TXPRE_TAP_DAC_BINARY(4 downto 3); TXACFG(52) <= TXDIGPD_BINARY; TXACFG(51 downto 48) <= TXCLKMODE_BINARY; TXACFG(47 downto 45) <= TXPRE_TAP_DAC_BINARY(2 downto 0); TXACFG(44) <= '0'; TXACFG(43) <= TXHIGHSIGNALEN_BINARY; TXACFG(42) <= TXAREFBIASSEL_BINARY; TXACFG(41 downto 38) <= TXTERMTRIM_BINARY; TXACFG(37) <= TXASYNCDIVIDE_BINARY(1); TXACFG(36) <= TXSLEWRATE_BINARY; TXACFG(35 downto 33) <= TXPOST_PRDRV_DAC_BINARY; TXACFG(32 downto 30) <= TXDAT_PRDRV_DAC_BINARY; TXACFG(29) <= TXASYNCDIVIDE_BINARY(0); TXACFG(28) <= TXPOST_TAP_PD_BINARY; TXACFG(27 downto 23) <= TXPOST_TAP_DAC_BINARY; TXACFG(22 downto 21) <= "00";-- TXTUNE1; TXACFG(20 downto 16) <= TXDAT_TAP_DAC_BINARY; TXACFG(15 downto 1) <= "000000000000000";-- TXDIG_TST; TXACFG(0) <= TXPD_BINARY; RXACLCFG(63 downto 60) <= RXOUTDIV2SEL_BINARY(7 downto 4); RXACLCFG(59 downto 56) <= RXPLLNDIVSEL_BINARY; RXACLCFG(55 downto 54) <= RXCLMODE_BINARY; RXACLCFG(53 downto 50) <= RXLOOPFILT_BINARY; RXACLCFG(49) <= RXDIGRX_BINARY; RXACLCFG(48) <= '0';-- RXPFDTX; RXACLCFG(47 downto 35) <= RXTUNE_BINARY; RXACLCFG(34) <= '0';-- RXSLOSEL; RXACLCFG(33) <= '0';-- RXDACSEL; RXACLCFG(32) <= RXCPSEL_BINARY; RXACLCFG(31) <= '0';-- RXDACTST; RXACLCFG(30 downto 27) <= RXOUTDIV2SEL_BINARY(3 downto 0); RXACLCFG(26 downto 17) <= RXCTRL1_BINARY; RXACLCFG(16) <= '0';-- RXQPPD; RXACLCFG(15) <= '1';-- RXCMFPD; RXACLCFG(14) <= '0';-- RXVCOPD; RXACLCFG(13) <= '0';-- RXADCADJPD; RXACLCFG(12) <= '0';-- RXDIVPD; RXACLCFG(11) <= '0';-- RXBIASPD; RXACLCFG(10) <= '0';-- RXVCOBUFPD; RXACLCFG(9) <= '0';-- RXDIVBUFPD; RXACLCFG(8) <= RXAPD_BINARY; RXACLCFG(7) <= '0';-- RXAPTST; RXACLCFG(6) <= '0';-- RXCMFTST; RXACLCFG(5) <= '0';-- RXFILTTST; RXACLCFG(4) <= '0';-- RXDIVTST; RXACLCFG(3) <= '0';-- RXPFDTST; RXACLCFG(2) <= '0';-- RXVCOBUFTST; RXACLCFG(1) <= '0';-- RXDIVBUFTST; RXACLCFG(0) <= '0';-- RXVCOTST wait; end process INIPROC; TIMING : process -- Pin timing violations (clock input pins) -- Pin Timing Violations (all input pins) -- Output Pin glitch declaration variable CHBONDO0_GlitchData : VitalGlitchDataType; variable CHBONDO1_GlitchData : VitalGlitchDataType; variable CHBONDO2_GlitchData : VitalGlitchDataType; variable CHBONDO3_GlitchData : VitalGlitchDataType; variable CHBONDO4_GlitchData : VitalGlitchDataType; variable RXSTATUS0_GlitchData : VitalGlitchDataType; variable RXSTATUS1_GlitchData : VitalGlitchDataType; variable RXSTATUS2_GlitchData : VitalGlitchDataType; variable RXSTATUS3_GlitchData : VitalGlitchDataType; variable RXSTATUS4_GlitchData : VitalGlitchDataType; variable RXSTATUS5_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA0_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA1_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA2_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA3_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA4_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA5_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA6_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA7_GlitchData : VitalGlitchDataType; variable RXCHARISK0_GlitchData : VitalGlitchDataType; variable RXCHARISK1_GlitchData : VitalGlitchDataType; variable RXCHARISK2_GlitchData : VitalGlitchDataType; variable RXCHARISK3_GlitchData : VitalGlitchDataType; variable RXCHARISK4_GlitchData : VitalGlitchDataType; variable RXCHARISK5_GlitchData : VitalGlitchDataType; variable RXCHARISK6_GlitchData : VitalGlitchDataType; variable RXCHARISK7_GlitchData : VitalGlitchDataType; variable RXCOMMADET_GlitchData : VitalGlitchDataType; variable RXDATA0_GlitchData : VitalGlitchDataType; variable RXDATA1_GlitchData : VitalGlitchDataType; variable RXDATA2_GlitchData : VitalGlitchDataType; variable RXDATA3_GlitchData : VitalGlitchDataType; variable RXDATA4_GlitchData : VitalGlitchDataType; variable RXDATA5_GlitchData : VitalGlitchDataType; variable RXDATA6_GlitchData : VitalGlitchDataType; variable RXDATA7_GlitchData : VitalGlitchDataType; variable RXDATA8_GlitchData : VitalGlitchDataType; variable RXDATA9_GlitchData : VitalGlitchDataType; variable RXDATA10_GlitchData : VitalGlitchDataType; variable RXDATA11_GlitchData : VitalGlitchDataType; variable RXDATA12_GlitchData : VitalGlitchDataType; variable RXDATA13_GlitchData : VitalGlitchDataType; variable RXDATA14_GlitchData : VitalGlitchDataType; variable RXDATA15_GlitchData : VitalGlitchDataType; variable RXDATA16_GlitchData : VitalGlitchDataType; variable RXDATA17_GlitchData : VitalGlitchDataType; variable RXDATA18_GlitchData : VitalGlitchDataType; variable RXDATA19_GlitchData : VitalGlitchDataType; variable RXDATA20_GlitchData : VitalGlitchDataType; variable RXDATA21_GlitchData : VitalGlitchDataType; variable RXDATA22_GlitchData : VitalGlitchDataType; variable RXDATA23_GlitchData : VitalGlitchDataType; variable RXDATA24_GlitchData : VitalGlitchDataType; variable RXDATA25_GlitchData : VitalGlitchDataType; variable RXDATA26_GlitchData : VitalGlitchDataType; variable RXDATA27_GlitchData : VitalGlitchDataType; variable RXDATA28_GlitchData : VitalGlitchDataType; variable RXDATA29_GlitchData : VitalGlitchDataType; variable RXDATA30_GlitchData : VitalGlitchDataType; variable RXDATA31_GlitchData : VitalGlitchDataType; variable RXDATA32_GlitchData : VitalGlitchDataType; variable RXDATA33_GlitchData : VitalGlitchDataType; variable RXDATA34_GlitchData : VitalGlitchDataType; variable RXDATA35_GlitchData : VitalGlitchDataType; variable RXDATA36_GlitchData : VitalGlitchDataType; variable RXDATA37_GlitchData : VitalGlitchDataType; variable RXDATA38_GlitchData : VitalGlitchDataType; variable RXDATA39_GlitchData : VitalGlitchDataType; variable RXDATA40_GlitchData : VitalGlitchDataType; variable RXDATA41_GlitchData : VitalGlitchDataType; variable RXDATA42_GlitchData : VitalGlitchDataType; variable RXDATA43_GlitchData : VitalGlitchDataType; variable RXDATA44_GlitchData : VitalGlitchDataType; variable RXDATA45_GlitchData : VitalGlitchDataType; variable RXDATA46_GlitchData : VitalGlitchDataType; variable RXDATA47_GlitchData : VitalGlitchDataType; variable RXDATA48_GlitchData : VitalGlitchDataType; variable RXDATA49_GlitchData : VitalGlitchDataType; variable RXDATA50_GlitchData : VitalGlitchDataType; variable RXDATA51_GlitchData : VitalGlitchDataType; variable RXDATA52_GlitchData : VitalGlitchDataType; variable RXDATA53_GlitchData : VitalGlitchDataType; variable RXDATA54_GlitchData : VitalGlitchDataType; variable RXDATA55_GlitchData : VitalGlitchDataType; variable RXDATA56_GlitchData : VitalGlitchDataType; variable RXDATA57_GlitchData : VitalGlitchDataType; variable RXDATA58_GlitchData : VitalGlitchDataType; variable RXDATA59_GlitchData : VitalGlitchDataType; variable RXDATA60_GlitchData : VitalGlitchDataType; variable RXDATA61_GlitchData : VitalGlitchDataType; variable RXDATA62_GlitchData : VitalGlitchDataType; variable RXDATA63_GlitchData : VitalGlitchDataType; variable RXDISPERR0_GlitchData : VitalGlitchDataType; variable RXDISPERR1_GlitchData : VitalGlitchDataType; variable RXDISPERR2_GlitchData : VitalGlitchDataType; variable RXDISPERR3_GlitchData : VitalGlitchDataType; variable RXDISPERR4_GlitchData : VitalGlitchDataType; variable RXDISPERR5_GlitchData : VitalGlitchDataType; variable RXDISPERR6_GlitchData : VitalGlitchDataType; variable RXDISPERR7_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC0_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC1_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE0_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE1_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE2_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE3_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE4_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE5_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE6_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE7_GlitchData : VitalGlitchDataType; variable RXREALIGN_GlitchData : VitalGlitchDataType; variable RXRUNDISP0_GlitchData : VitalGlitchDataType; variable RXRUNDISP1_GlitchData : VitalGlitchDataType; variable RXRUNDISP2_GlitchData : VitalGlitchDataType; variable RXRUNDISP3_GlitchData : VitalGlitchDataType; variable RXRUNDISP4_GlitchData : VitalGlitchDataType; variable RXRUNDISP5_GlitchData : VitalGlitchDataType; variable RXRUNDISP6_GlitchData : VitalGlitchDataType; variable RXRUNDISP7_GlitchData : VitalGlitchDataType; variable RXBUFERR_GlitchData : VitalGlitchDataType; variable TXBUFERR_GlitchData : VitalGlitchDataType; variable TXKERR0_GlitchData : VitalGlitchDataType; variable TXKERR1_GlitchData : VitalGlitchDataType; variable TXKERR2_GlitchData : VitalGlitchDataType; variable TXKERR3_GlitchData : VitalGlitchDataType; variable TXKERR4_GlitchData : VitalGlitchDataType; variable TXKERR5_GlitchData : VitalGlitchDataType; variable TXKERR6_GlitchData : VitalGlitchDataType; variable TXKERR7_GlitchData : VitalGlitchDataType; variable TXRUNDISP0_GlitchData : VitalGlitchDataType; variable TXRUNDISP1_GlitchData : VitalGlitchDataType; variable TXRUNDISP2_GlitchData : VitalGlitchDataType; variable TXRUNDISP3_GlitchData : VitalGlitchDataType; variable TXRUNDISP4_GlitchData : VitalGlitchDataType; variable TXRUNDISP5_GlitchData : VitalGlitchDataType; variable TXRUNDISP6_GlitchData : VitalGlitchDataType; variable TXRUNDISP7_GlitchData : VitalGlitchDataType; variable RXRECCLK1_GlitchData : VitalGlitchDataType; variable RXRECCLK2_GlitchData : VitalGlitchDataType; variable TXOUTCLK1_GlitchData : VitalGlitchDataType; variable TXOUTCLK2_GlitchData : VitalGlitchDataType; variable RXLOCK_GlitchData : VitalGlitchDataType; variable TXLOCK_GlitchData : VitalGlitchDataType; variable RXCYCLELIMIT_GlitchData : VitalGlitchDataType; variable TXCYCLELIMIT_GlitchData : VitalGlitchDataType; variable RXCALFAIL_GlitchData : VitalGlitchDataType; variable TXCALFAIL_GlitchData : VitalGlitchDataType; variable RXCRCOUT0_GlitchData : VitalGlitchDataType; variable RXCRCOUT1_GlitchData : VitalGlitchDataType; variable RXCRCOUT2_GlitchData : VitalGlitchDataType; variable RXCRCOUT3_GlitchData : VitalGlitchDataType; variable RXCRCOUT4_GlitchData : VitalGlitchDataType; variable RXCRCOUT5_GlitchData : VitalGlitchDataType; variable RXCRCOUT6_GlitchData : VitalGlitchDataType; variable RXCRCOUT7_GlitchData : VitalGlitchDataType; variable RXCRCOUT8_GlitchData : VitalGlitchDataType; variable RXCRCOUT9_GlitchData : VitalGlitchDataType; variable RXCRCOUT10_GlitchData : VitalGlitchDataType; variable RXCRCOUT11_GlitchData : VitalGlitchDataType; variable RXCRCOUT12_GlitchData : VitalGlitchDataType; variable RXCRCOUT13_GlitchData : VitalGlitchDataType; variable RXCRCOUT14_GlitchData : VitalGlitchDataType; variable RXCRCOUT15_GlitchData : VitalGlitchDataType; variable RXCRCOUT16_GlitchData : VitalGlitchDataType; variable RXCRCOUT17_GlitchData : VitalGlitchDataType; variable RXCRCOUT18_GlitchData : VitalGlitchDataType; variable RXCRCOUT19_GlitchData : VitalGlitchDataType; variable RXCRCOUT20_GlitchData : VitalGlitchDataType; variable RXCRCOUT21_GlitchData : VitalGlitchDataType; variable RXCRCOUT22_GlitchData : VitalGlitchDataType; variable RXCRCOUT23_GlitchData : VitalGlitchDataType; variable RXCRCOUT24_GlitchData : VitalGlitchDataType; variable RXCRCOUT25_GlitchData : VitalGlitchDataType; variable RXCRCOUT26_GlitchData : VitalGlitchDataType; variable RXCRCOUT27_GlitchData : VitalGlitchDataType; variable RXCRCOUT28_GlitchData : VitalGlitchDataType; variable RXCRCOUT29_GlitchData : VitalGlitchDataType; variable RXCRCOUT30_GlitchData : VitalGlitchDataType; variable RXCRCOUT31_GlitchData : VitalGlitchDataType; variable TXCRCOUT0_GlitchData : VitalGlitchDataType; variable TXCRCOUT1_GlitchData : VitalGlitchDataType; variable TXCRCOUT2_GlitchData : VitalGlitchDataType; variable TXCRCOUT3_GlitchData : VitalGlitchDataType; variable TXCRCOUT4_GlitchData : VitalGlitchDataType; variable TXCRCOUT5_GlitchData : VitalGlitchDataType; variable TXCRCOUT6_GlitchData : VitalGlitchDataType; variable TXCRCOUT7_GlitchData : VitalGlitchDataType; variable TXCRCOUT8_GlitchData : VitalGlitchDataType; variable TXCRCOUT9_GlitchData : VitalGlitchDataType; variable TXCRCOUT10_GlitchData : VitalGlitchDataType; variable TXCRCOUT11_GlitchData : VitalGlitchDataType; variable TXCRCOUT12_GlitchData : VitalGlitchDataType; variable TXCRCOUT13_GlitchData : VitalGlitchDataType; variable TXCRCOUT14_GlitchData : VitalGlitchDataType; variable TXCRCOUT15_GlitchData : VitalGlitchDataType; variable TXCRCOUT16_GlitchData : VitalGlitchDataType; variable TXCRCOUT17_GlitchData : VitalGlitchDataType; variable TXCRCOUT18_GlitchData : VitalGlitchDataType; variable TXCRCOUT19_GlitchData : VitalGlitchDataType; variable TXCRCOUT20_GlitchData : VitalGlitchDataType; variable TXCRCOUT21_GlitchData : VitalGlitchDataType; variable TXCRCOUT22_GlitchData : VitalGlitchDataType; variable TXCRCOUT23_GlitchData : VitalGlitchDataType; variable TXCRCOUT24_GlitchData : VitalGlitchDataType; variable TXCRCOUT25_GlitchData : VitalGlitchDataType; variable TXCRCOUT26_GlitchData : VitalGlitchDataType; variable TXCRCOUT27_GlitchData : VitalGlitchDataType; variable TXCRCOUT28_GlitchData : VitalGlitchDataType; variable TXCRCOUT29_GlitchData : VitalGlitchDataType; variable TXCRCOUT30_GlitchData : VitalGlitchDataType; variable TXCRCOUT31_GlitchData : VitalGlitchDataType; variable RXSIGDET_GlitchData : VitalGlitchDataType; variable DRDY_GlitchData : VitalGlitchDataType; variable DO0_GlitchData : VitalGlitchDataType; variable DO1_GlitchData : VitalGlitchDataType; variable DO2_GlitchData : VitalGlitchDataType; variable DO3_GlitchData : VitalGlitchDataType; variable DO4_GlitchData : VitalGlitchDataType; variable DO5_GlitchData : VitalGlitchDataType; variable DO6_GlitchData : VitalGlitchDataType; variable DO7_GlitchData : VitalGlitchDataType; variable DO8_GlitchData : VitalGlitchDataType; variable DO9_GlitchData : VitalGlitchDataType; variable DO10_GlitchData : VitalGlitchDataType; variable DO11_GlitchData : VitalGlitchDataType; variable DO12_GlitchData : VitalGlitchDataType; variable DO13_GlitchData : VitalGlitchDataType; variable DO14_GlitchData : VitalGlitchDataType; variable DO15_GlitchData : VitalGlitchDataType; variable RXMCLK_GlitchData : VitalGlitchDataType; variable TX1P_GlitchData : VitalGlitchDataType; variable TX1N_GlitchData : VitalGlitchDataType; variable TXPCSHCLKOUT_GlitchData : VitalGlitchDataType; variable RXPCSHCLKOUT_GlitchData : VitalGlitchDataType; variable COMBUSOUT0_GlitchData : VitalGlitchDataType; variable COMBUSOUT1_GlitchData : VitalGlitchDataType; variable COMBUSOUT2_GlitchData : VitalGlitchDataType; variable COMBUSOUT3_GlitchData : VitalGlitchDataType; variable COMBUSOUT4_GlitchData : VitalGlitchDataType; variable COMBUSOUT5_GlitchData : VitalGlitchDataType; variable COMBUSOUT6_GlitchData : VitalGlitchDataType; variable COMBUSOUT7_GlitchData : VitalGlitchDataType; variable COMBUSOUT8_GlitchData : VitalGlitchDataType; variable COMBUSOUT9_GlitchData : VitalGlitchDataType; variable COMBUSOUT10_GlitchData : VitalGlitchDataType; variable COMBUSOUT11_GlitchData : VitalGlitchDataType; variable COMBUSOUT12_GlitchData : VitalGlitchDataType; variable COMBUSOUT13_GlitchData : VitalGlitchDataType; variable COMBUSOUT14_GlitchData : VitalGlitchDataType; variable COMBUSOUT15_GlitchData : VitalGlitchDataType; begin -- Output-to-Clock path delay VitalPathDelay01 ( OutSignal => CHBONDO(0), GlitchData => CHBONDO0_GlitchData, OutSignalName => "CHBONDO(0)", OutTemp => CHBONDO_OUT(0), Paths => (0 => (RXUSRCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(1), GlitchData => CHBONDO1_GlitchData, OutSignalName => "CHBONDO(1)", OutTemp => CHBONDO_OUT(1), Paths => (0 => (RXUSRCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(2), GlitchData => CHBONDO2_GlitchData, OutSignalName => "CHBONDO(2)", OutTemp => CHBONDO_OUT(2), Paths => (0 => (RXUSRCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(3), GlitchData => CHBONDO3_GlitchData, OutSignalName => "CHBONDO(3)", OutTemp => CHBONDO_OUT(3), Paths => (0 => (RXUSRCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CHBONDO(4), GlitchData => CHBONDO4_GlitchData, OutSignalName => "CHBONDO(4)", OutTemp => CHBONDO_OUT(4), Paths => (0 => (RXUSRCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS(0), GlitchData => RXSTATUS0_GlitchData, OutSignalName => "RXSTATUS(0)", OutTemp => RXSTATUS_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS(1), GlitchData => RXSTATUS1_GlitchData, OutSignalName => "RXSTATUS(1)", OutTemp => RXSTATUS_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS(2), GlitchData => RXSTATUS2_GlitchData, OutSignalName => "RXSTATUS(2)", OutTemp => RXSTATUS_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS(3), GlitchData => RXSTATUS3_GlitchData, OutSignalName => "RXSTATUS(3)", OutTemp => RXSTATUS_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS(4), GlitchData => RXSTATUS4_GlitchData, OutSignalName => "RXSTATUS(4)", OutTemp => RXSTATUS_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS(5), GlitchData => RXSTATUS5_GlitchData, OutSignalName => "RXSTATUS(5)", OutTemp => RXSTATUS_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(0), GlitchData => RXCHARISCOMMA0_GlitchData, OutSignalName => "RXCHARISCOMMA(0)", OutTemp => RXCHARISCOMMA_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(1), GlitchData => RXCHARISCOMMA1_GlitchData, OutSignalName => "RXCHARISCOMMA(1)", OutTemp => RXCHARISCOMMA_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(2), GlitchData => RXCHARISCOMMA2_GlitchData, OutSignalName => "RXCHARISCOMMA(2)", OutTemp => RXCHARISCOMMA_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(3), GlitchData => RXCHARISCOMMA3_GlitchData, OutSignalName => "RXCHARISCOMMA(3)", OutTemp => RXCHARISCOMMA_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(4), GlitchData => RXCHARISCOMMA4_GlitchData, OutSignalName => "RXCHARISCOMMA(4)", OutTemp => RXCHARISCOMMA_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(5), GlitchData => RXCHARISCOMMA5_GlitchData, OutSignalName => "RXCHARISCOMMA(5)", OutTemp => RXCHARISCOMMA_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(6), GlitchData => RXCHARISCOMMA6_GlitchData, OutSignalName => "RXCHARISCOMMA(6)", OutTemp => RXCHARISCOMMA_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA(7), GlitchData => RXCHARISCOMMA7_GlitchData, OutSignalName => "RXCHARISCOMMA(7)", OutTemp => RXCHARISCOMMA_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(0), GlitchData => RXCHARISK0_GlitchData, OutSignalName => "RXCHARISK(0)", OutTemp => RXCHARISK_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(1), GlitchData => RXCHARISK1_GlitchData, OutSignalName => "RXCHARISK(1)", OutTemp => RXCHARISK_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(2), GlitchData => RXCHARISK2_GlitchData, OutSignalName => "RXCHARISK(2)", OutTemp => RXCHARISK_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(3), GlitchData => RXCHARISK3_GlitchData, OutSignalName => "RXCHARISK(3)", OutTemp => RXCHARISK_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(4), GlitchData => RXCHARISK4_GlitchData, OutSignalName => "RXCHARISK(4)", OutTemp => RXCHARISK_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(5), GlitchData => RXCHARISK5_GlitchData, OutSignalName => "RXCHARISK(5)", OutTemp => RXCHARISK_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(6), GlitchData => RXCHARISK6_GlitchData, OutSignalName => "RXCHARISK(6)", OutTemp => RXCHARISK_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK(7), GlitchData => RXCHARISK7_GlitchData, OutSignalName => "RXCHARISK(7)", OutTemp => RXCHARISK_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCOMMADET, GlitchData => RXCOMMADET_GlitchData, OutSignalName => "RXCOMMADET", OutTemp => RXCOMMADET_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(0), GlitchData => RXDATA0_GlitchData, OutSignalName => "RXDATA(0)", OutTemp => RXDATA_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(1), GlitchData => RXDATA1_GlitchData, OutSignalName => "RXDATA(1)", OutTemp => RXDATA_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(2), GlitchData => RXDATA2_GlitchData, OutSignalName => "RXDATA(2)", OutTemp => RXDATA_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(3), GlitchData => RXDATA3_GlitchData, OutSignalName => "RXDATA(3)", OutTemp => RXDATA_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(4), GlitchData => RXDATA4_GlitchData, OutSignalName => "RXDATA(4)", OutTemp => RXDATA_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(5), GlitchData => RXDATA5_GlitchData, OutSignalName => "RXDATA(5)", OutTemp => RXDATA_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(6), GlitchData => RXDATA6_GlitchData, OutSignalName => "RXDATA(6)", OutTemp => RXDATA_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(7), GlitchData => RXDATA7_GlitchData, OutSignalName => "RXDATA(7)", OutTemp => RXDATA_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(8), GlitchData => RXDATA8_GlitchData, OutSignalName => "RXDATA(8)", OutTemp => RXDATA_OUT(8), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(9), GlitchData => RXDATA9_GlitchData, OutSignalName => "RXDATA(9)", OutTemp => RXDATA_OUT(9), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(10), GlitchData => RXDATA10_GlitchData, OutSignalName => "RXDATA(10)", OutTemp => RXDATA_OUT(10), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(11), GlitchData => RXDATA11_GlitchData, OutSignalName => "RXDATA(11)", OutTemp => RXDATA_OUT(11), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(12), GlitchData => RXDATA12_GlitchData, OutSignalName => "RXDATA(12)", OutTemp => RXDATA_OUT(12), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(13), GlitchData => RXDATA13_GlitchData, OutSignalName => "RXDATA(13)", OutTemp => RXDATA_OUT(13), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(14), GlitchData => RXDATA14_GlitchData, OutSignalName => "RXDATA(14)", OutTemp => RXDATA_OUT(14), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(15), GlitchData => RXDATA15_GlitchData, OutSignalName => "RXDATA(15)", OutTemp => RXDATA_OUT(15), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(16), GlitchData => RXDATA16_GlitchData, OutSignalName => "RXDATA(16)", OutTemp => RXDATA_OUT(16), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(17), GlitchData => RXDATA17_GlitchData, OutSignalName => "RXDATA(17)", OutTemp => RXDATA_OUT(17), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(18), GlitchData => RXDATA18_GlitchData, OutSignalName => "RXDATA(18)", OutTemp => RXDATA_OUT(18), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(19), GlitchData => RXDATA19_GlitchData, OutSignalName => "RXDATA(19)", OutTemp => RXDATA_OUT(19), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(20), GlitchData => RXDATA20_GlitchData, OutSignalName => "RXDATA(20)", OutTemp => RXDATA_OUT(20), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(21), GlitchData => RXDATA21_GlitchData, OutSignalName => "RXDATA(21)", OutTemp => RXDATA_OUT(21), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(22), GlitchData => RXDATA22_GlitchData, OutSignalName => "RXDATA(22)", OutTemp => RXDATA_OUT(22), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(23), GlitchData => RXDATA23_GlitchData, OutSignalName => "RXDATA(23)", OutTemp => RXDATA_OUT(23), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(24), GlitchData => RXDATA24_GlitchData, OutSignalName => "RXDATA(24)", OutTemp => RXDATA_OUT(24), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(25), GlitchData => RXDATA25_GlitchData, OutSignalName => "RXDATA(25)", OutTemp => RXDATA_OUT(25), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(26), GlitchData => RXDATA26_GlitchData, OutSignalName => "RXDATA(26)", OutTemp => RXDATA_OUT(26), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(27), GlitchData => RXDATA27_GlitchData, OutSignalName => "RXDATA(27)", OutTemp => RXDATA_OUT(27), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(28), GlitchData => RXDATA28_GlitchData, OutSignalName => "RXDATA(28)", OutTemp => RXDATA_OUT(28), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(29), GlitchData => RXDATA29_GlitchData, OutSignalName => "RXDATA(29)", OutTemp => RXDATA_OUT(29), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(30), GlitchData => RXDATA30_GlitchData, OutSignalName => "RXDATA(30)", OutTemp => RXDATA_OUT(30), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(31), GlitchData => RXDATA31_GlitchData, OutSignalName => "RXDATA(31)", OutTemp => RXDATA_OUT(31), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(32), GlitchData => RXDATA32_GlitchData, OutSignalName => "RXDATA(32)", OutTemp => RXDATA_OUT(32), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(33), GlitchData => RXDATA33_GlitchData, OutSignalName => "RXDATA(33)", OutTemp => RXDATA_OUT(33), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(34), GlitchData => RXDATA34_GlitchData, OutSignalName => "RXDATA(34)", OutTemp => RXDATA_OUT(34), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(35), GlitchData => RXDATA35_GlitchData, OutSignalName => "RXDATA(35)", OutTemp => RXDATA_OUT(35), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(36), GlitchData => RXDATA36_GlitchData, OutSignalName => "RXDATA(36)", OutTemp => RXDATA_OUT(36), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(37), GlitchData => RXDATA37_GlitchData, OutSignalName => "RXDATA(37)", OutTemp => RXDATA_OUT(37), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(38), GlitchData => RXDATA38_GlitchData, OutSignalName => "RXDATA(38)", OutTemp => RXDATA_OUT(38), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(39), GlitchData => RXDATA39_GlitchData, OutSignalName => "RXDATA(39)", OutTemp => RXDATA_OUT(39), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(40), GlitchData => RXDATA40_GlitchData, OutSignalName => "RXDATA(40)", OutTemp => RXDATA_OUT(40), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(41), GlitchData => RXDATA41_GlitchData, OutSignalName => "RXDATA(41)", OutTemp => RXDATA_OUT(41), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(42), GlitchData => RXDATA42_GlitchData, OutSignalName => "RXDATA(42)", OutTemp => RXDATA_OUT(42), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(43), GlitchData => RXDATA43_GlitchData, OutSignalName => "RXDATA(43)", OutTemp => RXDATA_OUT(43), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(44), GlitchData => RXDATA44_GlitchData, OutSignalName => "RXDATA(44)", OutTemp => RXDATA_OUT(44), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(45), GlitchData => RXDATA45_GlitchData, OutSignalName => "RXDATA(45)", OutTemp => RXDATA_OUT(45), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(46), GlitchData => RXDATA46_GlitchData, OutSignalName => "RXDATA(46)", OutTemp => RXDATA_OUT(46), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(47), GlitchData => RXDATA47_GlitchData, OutSignalName => "RXDATA(47)", OutTemp => RXDATA_OUT(47), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(48), GlitchData => RXDATA48_GlitchData, OutSignalName => "RXDATA(48)", OutTemp => RXDATA_OUT(48), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(49), GlitchData => RXDATA49_GlitchData, OutSignalName => "RXDATA(49)", OutTemp => RXDATA_OUT(49), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(50), GlitchData => RXDATA50_GlitchData, OutSignalName => "RXDATA(50)", OutTemp => RXDATA_OUT(50), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(51), GlitchData => RXDATA51_GlitchData, OutSignalName => "RXDATA(51)", OutTemp => RXDATA_OUT(51), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(52), GlitchData => RXDATA52_GlitchData, OutSignalName => "RXDATA(52)", OutTemp => RXDATA_OUT(52), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(53), GlitchData => RXDATA53_GlitchData, OutSignalName => "RXDATA(53)", OutTemp => RXDATA_OUT(53), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(54), GlitchData => RXDATA54_GlitchData, OutSignalName => "RXDATA(54)", OutTemp => RXDATA_OUT(54), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(55), GlitchData => RXDATA55_GlitchData, OutSignalName => "RXDATA(55)", OutTemp => RXDATA_OUT(55), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(56), GlitchData => RXDATA56_GlitchData, OutSignalName => "RXDATA(56)", OutTemp => RXDATA_OUT(56), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(57), GlitchData => RXDATA57_GlitchData, OutSignalName => "RXDATA(57)", OutTemp => RXDATA_OUT(57), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(58), GlitchData => RXDATA58_GlitchData, OutSignalName => "RXDATA(58)", OutTemp => RXDATA_OUT(58), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(59), GlitchData => RXDATA59_GlitchData, OutSignalName => "RXDATA(59)", OutTemp => RXDATA_OUT(59), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(60), GlitchData => RXDATA60_GlitchData, OutSignalName => "RXDATA(60)", OutTemp => RXDATA_OUT(60), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(61), GlitchData => RXDATA61_GlitchData, OutSignalName => "RXDATA(61)", OutTemp => RXDATA_OUT(61), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(62), GlitchData => RXDATA62_GlitchData, OutSignalName => "RXDATA(62)", OutTemp => RXDATA_OUT(62), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA(63), GlitchData => RXDATA63_GlitchData, OutSignalName => "RXDATA(63)", OutTemp => RXDATA_OUT(63), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(0), GlitchData => RXDISPERR0_GlitchData, OutSignalName => "RXDISPERR(0)", OutTemp => RXDISPERR_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(1), GlitchData => RXDISPERR1_GlitchData, OutSignalName => "RXDISPERR(1)", OutTemp => RXDISPERR_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(2), GlitchData => RXDISPERR2_GlitchData, OutSignalName => "RXDISPERR(2)", OutTemp => RXDISPERR_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(3), GlitchData => RXDISPERR3_GlitchData, OutSignalName => "RXDISPERR(3)", OutTemp => RXDISPERR_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(4), GlitchData => RXDISPERR4_GlitchData, OutSignalName => "RXDISPERR(4)", OutTemp => RXDISPERR_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(5), GlitchData => RXDISPERR5_GlitchData, OutSignalName => "RXDISPERR(5)", OutTemp => RXDISPERR_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(6), GlitchData => RXDISPERR6_GlitchData, OutSignalName => "RXDISPERR(6)", OutTemp => RXDISPERR_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR(7), GlitchData => RXDISPERR7_GlitchData, OutSignalName => "RXDISPERR(7)", OutTemp => RXDISPERR_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC(0), GlitchData => RXLOSSOFSYNC0_GlitchData, OutSignalName => "RXLOSSOFSYNC(0)", OutTemp => RXLOSSOFSYNC_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC(1), GlitchData => RXLOSSOFSYNC1_GlitchData, OutSignalName => "RXLOSSOFSYNC(1)", OutTemp => RXLOSSOFSYNC_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(0), GlitchData => RXNOTINTABLE0_GlitchData, OutSignalName => "RXNOTINTABLE(0)", OutTemp => RXNOTINTABLE_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(1), GlitchData => RXNOTINTABLE1_GlitchData, OutSignalName => "RXNOTINTABLE(1)", OutTemp => RXNOTINTABLE_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(2), GlitchData => RXNOTINTABLE2_GlitchData, OutSignalName => "RXNOTINTABLE(2)", OutTemp => RXNOTINTABLE_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(3), GlitchData => RXNOTINTABLE3_GlitchData, OutSignalName => "RXNOTINTABLE(3)", OutTemp => RXNOTINTABLE_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(4), GlitchData => RXNOTINTABLE4_GlitchData, OutSignalName => "RXNOTINTABLE(4)", OutTemp => RXNOTINTABLE_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(5), GlitchData => RXNOTINTABLE5_GlitchData, OutSignalName => "RXNOTINTABLE(5)", OutTemp => RXNOTINTABLE_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(6), GlitchData => RXNOTINTABLE6_GlitchData, OutSignalName => "RXNOTINTABLE(6)", OutTemp => RXNOTINTABLE_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE(7), GlitchData => RXNOTINTABLE7_GlitchData, OutSignalName => "RXNOTINTABLE(7)", OutTemp => RXNOTINTABLE_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXREALIGN, GlitchData => RXREALIGN_GlitchData, OutSignalName => "RXREALIGN", OutTemp => RXREALIGN_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(0), GlitchData => RXRUNDISP0_GlitchData, OutSignalName => "RXRUNDISP(0)", OutTemp => RXRUNDISP_OUT(0), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(1), GlitchData => RXRUNDISP1_GlitchData, OutSignalName => "RXRUNDISP(1)", OutTemp => RXRUNDISP_OUT(1), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(2), GlitchData => RXRUNDISP2_GlitchData, OutSignalName => "RXRUNDISP(2)", OutTemp => RXRUNDISP_OUT(2), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(3), GlitchData => RXRUNDISP3_GlitchData, OutSignalName => "RXRUNDISP(3)", OutTemp => RXRUNDISP_OUT(3), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(4), GlitchData => RXRUNDISP4_GlitchData, OutSignalName => "RXRUNDISP(4)", OutTemp => RXRUNDISP_OUT(4), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(5), GlitchData => RXRUNDISP5_GlitchData, OutSignalName => "RXRUNDISP(5)", OutTemp => RXRUNDISP_OUT(5), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(6), GlitchData => RXRUNDISP6_GlitchData, OutSignalName => "RXRUNDISP(6)", OutTemp => RXRUNDISP_OUT(6), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP(7), GlitchData => RXRUNDISP7_GlitchData, OutSignalName => "RXRUNDISP(7)", OutTemp => RXRUNDISP_OUT(7), Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFERR, GlitchData => RXBUFERR_GlitchData, OutSignalName => "RXBUFERR", OutTemp => RXBUFERR_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXBUFERR, GlitchData => TXBUFERR_GlitchData, OutSignalName => "TXBUFERR", OutTemp => TXBUFERR_OUT, Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(0), GlitchData => TXKERR0_GlitchData, OutSignalName => "TXKERR(0)", OutTemp => TXKERR_OUT(0), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(1), GlitchData => TXKERR1_GlitchData, OutSignalName => "TXKERR(1)", OutTemp => TXKERR_OUT(1), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(2), GlitchData => TXKERR2_GlitchData, OutSignalName => "TXKERR(2)", OutTemp => TXKERR_OUT(2), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(3), GlitchData => TXKERR3_GlitchData, OutSignalName => "TXKERR(3)", OutTemp => TXKERR_OUT(3), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(4), GlitchData => TXKERR4_GlitchData, OutSignalName => "TXKERR(4)", OutTemp => TXKERR_OUT(4), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(5), GlitchData => TXKERR5_GlitchData, OutSignalName => "TXKERR(5)", OutTemp => TXKERR_OUT(5), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(6), GlitchData => TXKERR6_GlitchData, OutSignalName => "TXKERR(6)", OutTemp => TXKERR_OUT(6), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR(7), GlitchData => TXKERR7_GlitchData, OutSignalName => "TXKERR(7)", OutTemp => TXKERR_OUT(7), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(0), GlitchData => TXRUNDISP0_GlitchData, OutSignalName => "TXRUNDISP(0)", OutTemp => TXRUNDISP_OUT(0), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(1), GlitchData => TXRUNDISP1_GlitchData, OutSignalName => "TXRUNDISP(1)", OutTemp => TXRUNDISP_OUT(1), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(2), GlitchData => TXRUNDISP2_GlitchData, OutSignalName => "TXRUNDISP(2)", OutTemp => TXRUNDISP_OUT(2), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(3), GlitchData => TXRUNDISP3_GlitchData, OutSignalName => "TXRUNDISP(3)", OutTemp => TXRUNDISP_OUT(3), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(4), GlitchData => TXRUNDISP4_GlitchData, OutSignalName => "TXRUNDISP(4)", OutTemp => TXRUNDISP_OUT(4), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(5), GlitchData => TXRUNDISP5_GlitchData, OutSignalName => "TXRUNDISP(5)", OutTemp => TXRUNDISP_OUT(5), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(6), GlitchData => TXRUNDISP6_GlitchData, OutSignalName => "TXRUNDISP(6)", OutTemp => TXRUNDISP_OUT(6), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP(7), GlitchData => TXRUNDISP7_GlitchData, OutSignalName => "TXRUNDISP(7)", OutTemp => TXRUNDISP_OUT(7), Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOCK, GlitchData => RXLOCK_GlitchData, OutSignalName => "RXLOCK", OutTemp => RXLOCK_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXLOCK, GlitchData => TXLOCK_GlitchData, OutSignalName => "TXLOCK", OutTemp => TXLOCK_OUT, Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCYCLELIMIT, GlitchData => RXCYCLELIMIT_GlitchData, OutSignalName => "RXCYCLELIMIT", OutTemp => RXCYCLELIMIT_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCYCLELIMIT, GlitchData => TXCYCLELIMIT_GlitchData, OutSignalName => "TXCYCLELIMIT", OutTemp => TXCYCLELIMIT_OUT, Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCALFAIL, GlitchData => RXCALFAIL_GlitchData, OutSignalName => "RXCALFAIL", OutTemp => RXCALFAIL_OUT, Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCALFAIL, GlitchData => TXCALFAIL_GlitchData, OutSignalName => "TXCALFAIL", OutTemp => TXCALFAIL_OUT, Paths => (0 => (TXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(0), GlitchData => RXCRCOUT0_GlitchData, OutSignalName => "RXCRCOUT(0)", OutTemp => RXCRCOUT_OUT(0), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(1), GlitchData => RXCRCOUT1_GlitchData, OutSignalName => "RXCRCOUT(1)", OutTemp => RXCRCOUT_OUT(1), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(2), GlitchData => RXCRCOUT2_GlitchData, OutSignalName => "RXCRCOUT(2)", OutTemp => RXCRCOUT_OUT(2), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(3), GlitchData => RXCRCOUT3_GlitchData, OutSignalName => "RXCRCOUT(3)", OutTemp => RXCRCOUT_OUT(3), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(4), GlitchData => RXCRCOUT4_GlitchData, OutSignalName => "RXCRCOUT(4)", OutTemp => RXCRCOUT_OUT(4), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(5), GlitchData => RXCRCOUT5_GlitchData, OutSignalName => "RXCRCOUT(5)", OutTemp => RXCRCOUT_OUT(5), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(6), GlitchData => RXCRCOUT6_GlitchData, OutSignalName => "RXCRCOUT(6)", OutTemp => RXCRCOUT_OUT(6), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(7), GlitchData => RXCRCOUT7_GlitchData, OutSignalName => "RXCRCOUT(7)", OutTemp => RXCRCOUT_OUT(7), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(8), GlitchData => RXCRCOUT8_GlitchData, OutSignalName => "RXCRCOUT(8)", OutTemp => RXCRCOUT_OUT(8), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(9), GlitchData => RXCRCOUT9_GlitchData, OutSignalName => "RXCRCOUT(9)", OutTemp => RXCRCOUT_OUT(9), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(10), GlitchData => RXCRCOUT10_GlitchData, OutSignalName => "RXCRCOUT(10)", OutTemp => RXCRCOUT_OUT(10), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(11), GlitchData => RXCRCOUT11_GlitchData, OutSignalName => "RXCRCOUT(11)", OutTemp => RXCRCOUT_OUT(11), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(12), GlitchData => RXCRCOUT12_GlitchData, OutSignalName => "RXCRCOUT(12)", OutTemp => RXCRCOUT_OUT(12), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(13), GlitchData => RXCRCOUT13_GlitchData, OutSignalName => "RXCRCOUT(13)", OutTemp => RXCRCOUT_OUT(13), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(14), GlitchData => RXCRCOUT14_GlitchData, OutSignalName => "RXCRCOUT(14)", OutTemp => RXCRCOUT_OUT(14), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(15), GlitchData => RXCRCOUT15_GlitchData, OutSignalName => "RXCRCOUT(15)", OutTemp => RXCRCOUT_OUT(15), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(16), GlitchData => RXCRCOUT16_GlitchData, OutSignalName => "RXCRCOUT(16)", OutTemp => RXCRCOUT_OUT(16), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(17), GlitchData => RXCRCOUT17_GlitchData, OutSignalName => "RXCRCOUT(17)", OutTemp => RXCRCOUT_OUT(17), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(18), GlitchData => RXCRCOUT18_GlitchData, OutSignalName => "RXCRCOUT(18)", OutTemp => RXCRCOUT_OUT(18), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(19), GlitchData => RXCRCOUT19_GlitchData, OutSignalName => "RXCRCOUT(19)", OutTemp => RXCRCOUT_OUT(19), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(20), GlitchData => RXCRCOUT20_GlitchData, OutSignalName => "RXCRCOUT(20)", OutTemp => RXCRCOUT_OUT(20), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(21), GlitchData => RXCRCOUT21_GlitchData, OutSignalName => "RXCRCOUT(21)", OutTemp => RXCRCOUT_OUT(21), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(22), GlitchData => RXCRCOUT22_GlitchData, OutSignalName => "RXCRCOUT(22)", OutTemp => RXCRCOUT_OUT(22), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(23), GlitchData => RXCRCOUT23_GlitchData, OutSignalName => "RXCRCOUT(23)", OutTemp => RXCRCOUT_OUT(23), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(24), GlitchData => RXCRCOUT24_GlitchData, OutSignalName => "RXCRCOUT(24)", OutTemp => RXCRCOUT_OUT(24), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(25), GlitchData => RXCRCOUT25_GlitchData, OutSignalName => "RXCRCOUT(25)", OutTemp => RXCRCOUT_OUT(25), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(26), GlitchData => RXCRCOUT26_GlitchData, OutSignalName => "RXCRCOUT(26)", OutTemp => RXCRCOUT_OUT(26), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(27), GlitchData => RXCRCOUT27_GlitchData, OutSignalName => "RXCRCOUT(27)", OutTemp => RXCRCOUT_OUT(27), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(28), GlitchData => RXCRCOUT28_GlitchData, OutSignalName => "RXCRCOUT(28)", OutTemp => RXCRCOUT_OUT(28), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(29), GlitchData => RXCRCOUT29_GlitchData, OutSignalName => "RXCRCOUT(29)", OutTemp => RXCRCOUT_OUT(29), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(30), GlitchData => RXCRCOUT30_GlitchData, OutSignalName => "RXCRCOUT(30)", OutTemp => RXCRCOUT_OUT(30), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCRCOUT(31), GlitchData => RXCRCOUT31_GlitchData, OutSignalName => "RXCRCOUT(31)", OutTemp => RXCRCOUT_OUT(31), Paths => (0 => (RXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(0), GlitchData => TXCRCOUT0_GlitchData, OutSignalName => "TXCRCOUT(0)", OutTemp => TXCRCOUT_OUT(0), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(1), GlitchData => TXCRCOUT1_GlitchData, OutSignalName => "TXCRCOUT(1)", OutTemp => TXCRCOUT_OUT(1), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(2), GlitchData => TXCRCOUT2_GlitchData, OutSignalName => "TXCRCOUT(2)", OutTemp => TXCRCOUT_OUT(2), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(3), GlitchData => TXCRCOUT3_GlitchData, OutSignalName => "TXCRCOUT(3)", OutTemp => TXCRCOUT_OUT(3), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(4), GlitchData => TXCRCOUT4_GlitchData, OutSignalName => "TXCRCOUT(4)", OutTemp => TXCRCOUT_OUT(4), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(5), GlitchData => TXCRCOUT5_GlitchData, OutSignalName => "TXCRCOUT(5)", OutTemp => TXCRCOUT_OUT(5), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(6), GlitchData => TXCRCOUT6_GlitchData, OutSignalName => "TXCRCOUT(6)", OutTemp => TXCRCOUT_OUT(6), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(7), GlitchData => TXCRCOUT7_GlitchData, OutSignalName => "TXCRCOUT(7)", OutTemp => TXCRCOUT_OUT(7), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(8), GlitchData => TXCRCOUT8_GlitchData, OutSignalName => "TXCRCOUT(8)", OutTemp => TXCRCOUT_OUT(8), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(9), GlitchData => TXCRCOUT9_GlitchData, OutSignalName => "TXCRCOUT(9)", OutTemp => TXCRCOUT_OUT(9), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(10), GlitchData => TXCRCOUT10_GlitchData, OutSignalName => "TXCRCOUT(10)", OutTemp => TXCRCOUT_OUT(10), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(11), GlitchData => TXCRCOUT11_GlitchData, OutSignalName => "TXCRCOUT(11)", OutTemp => TXCRCOUT_OUT(11), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(12), GlitchData => TXCRCOUT12_GlitchData, OutSignalName => "TXCRCOUT(12)", OutTemp => TXCRCOUT_OUT(12), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(13), GlitchData => TXCRCOUT13_GlitchData, OutSignalName => "TXCRCOUT(13)", OutTemp => TXCRCOUT_OUT(13), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(14), GlitchData => TXCRCOUT14_GlitchData, OutSignalName => "TXCRCOUT(14)", OutTemp => TXCRCOUT_OUT(14), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(15), GlitchData => TXCRCOUT15_GlitchData, OutSignalName => "TXCRCOUT(15)", OutTemp => TXCRCOUT_OUT(15), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(16), GlitchData => TXCRCOUT16_GlitchData, OutSignalName => "TXCRCOUT(16)", OutTemp => TXCRCOUT_OUT(16), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(17), GlitchData => TXCRCOUT17_GlitchData, OutSignalName => "TXCRCOUT(17)", OutTemp => TXCRCOUT_OUT(17), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(18), GlitchData => TXCRCOUT18_GlitchData, OutSignalName => "TXCRCOUT(18)", OutTemp => TXCRCOUT_OUT(18), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(19), GlitchData => TXCRCOUT19_GlitchData, OutSignalName => "TXCRCOUT(19)", OutTemp => TXCRCOUT_OUT(19), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(20), GlitchData => TXCRCOUT20_GlitchData, OutSignalName => "TXCRCOUT(20)", OutTemp => TXCRCOUT_OUT(20), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(21), GlitchData => TXCRCOUT21_GlitchData, OutSignalName => "TXCRCOUT(21)", OutTemp => TXCRCOUT_OUT(21), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(22), GlitchData => TXCRCOUT22_GlitchData, OutSignalName => "TXCRCOUT(22)", OutTemp => TXCRCOUT_OUT(22), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(23), GlitchData => TXCRCOUT23_GlitchData, OutSignalName => "TXCRCOUT(23)", OutTemp => TXCRCOUT_OUT(23), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(24), GlitchData => TXCRCOUT24_GlitchData, OutSignalName => "TXCRCOUT(24)", OutTemp => TXCRCOUT_OUT(24), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(25), GlitchData => TXCRCOUT25_GlitchData, OutSignalName => "TXCRCOUT(25)", OutTemp => TXCRCOUT_OUT(25), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(26), GlitchData => TXCRCOUT26_GlitchData, OutSignalName => "TXCRCOUT(26)", OutTemp => TXCRCOUT_OUT(26), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(27), GlitchData => TXCRCOUT27_GlitchData, OutSignalName => "TXCRCOUT(27)", OutTemp => TXCRCOUT_OUT(27), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(28), GlitchData => TXCRCOUT28_GlitchData, OutSignalName => "TXCRCOUT(28)", OutTemp => TXCRCOUT_OUT(28), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(29), GlitchData => TXCRCOUT29_GlitchData, OutSignalName => "TXCRCOUT(29)", OutTemp => TXCRCOUT_OUT(29), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(30), GlitchData => TXCRCOUT30_GlitchData, OutSignalName => "TXCRCOUT(30)", OutTemp => TXCRCOUT_OUT(30), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXCRCOUT(31), GlitchData => TXCRCOUT31_GlitchData, OutSignalName => "TXCRCOUT(31)", OutTemp => TXCRCOUT_OUT(31), Paths => (0 => (TXCRCINTCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSIGDET, GlitchData => RXSIGDET_GlitchData, OutSignalName => "RXSIGDET", OutTemp => RXSIGDET_OUT, Paths => (0 => (RXUSRCLK2_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DRDY, GlitchData => DRDY_GlitchData, OutSignalName => "DRDY", OutTemp => DRDY_OUT, Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(0), GlitchData => DO0_GlitchData, OutSignalName => "DO(0)", OutTemp => DO_OUT(0), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(1), GlitchData => DO1_GlitchData, OutSignalName => "DO(1)", OutTemp => DO_OUT(1), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(2), GlitchData => DO2_GlitchData, OutSignalName => "DO(2)", OutTemp => DO_OUT(2), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(3), GlitchData => DO3_GlitchData, OutSignalName => "DO(3)", OutTemp => DO_OUT(3), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(4), GlitchData => DO4_GlitchData, OutSignalName => "DO(4)", OutTemp => DO_OUT(4), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(5), GlitchData => DO5_GlitchData, OutSignalName => "DO(5)", OutTemp => DO_OUT(5), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(6), GlitchData => DO6_GlitchData, OutSignalName => "DO(6)", OutTemp => DO_OUT(6), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(7), GlitchData => DO7_GlitchData, OutSignalName => "DO(7)", OutTemp => DO_OUT(7), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(8), GlitchData => DO8_GlitchData, OutSignalName => "DO(8)", OutTemp => DO_OUT(8), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(9), GlitchData => DO9_GlitchData, OutSignalName => "DO(9)", OutTemp => DO_OUT(9), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(10), GlitchData => DO10_GlitchData, OutSignalName => "DO(10)", OutTemp => DO_OUT(10), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(11), GlitchData => DO11_GlitchData, OutSignalName => "DO(11)", OutTemp => DO_OUT(11), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(12), GlitchData => DO12_GlitchData, OutSignalName => "DO(12)", OutTemp => DO_OUT(12), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(13), GlitchData => DO13_GlitchData, OutSignalName => "DO(13)", OutTemp => DO_OUT(13), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(14), GlitchData => DO14_GlitchData, OutSignalName => "DO(14)", OutTemp => DO_OUT(14), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(15), GlitchData => DO15_GlitchData, OutSignalName => "DO(15)", OutTemp => DO_OUT(15), Paths => (0 => (DCLK_ipd'last_event, OUT_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); -- Wait signal (input/output pins) wait on CHBONDO_OUT, RXSTATUS_OUT, RXCHARISCOMMA_OUT, RXCHARISK_OUT, RXCOMMADET_OUT, RXDATA_OUT, RXDISPERR_OUT, RXLOSSOFSYNC_OUT, RXNOTINTABLE_OUT, RXREALIGN_OUT, RXRUNDISP_OUT, RXBUFERR_OUT, TXBUFERR_OUT, TXKERR_OUT, TXRUNDISP_OUT, RXLOCK_OUT, TXLOCK_OUT, RXCYCLELIMIT_OUT, TXCYCLELIMIT_OUT, RXCALFAIL_OUT, TXCALFAIL_OUT, RXCRCOUT_OUT, TXCRCOUT_OUT, RXSIGDET_OUT, DRDY_OUT, DO_OUT, CHBONDI_ipd, ENCHANSYNC_ipd, ENMCOMMAALIGN_ipd, ENPCOMMAALIGN_ipd, LOOPBACK_ipd, POWERDOWN_ipd, RXBLOCKSYNC64B66BUSE_ipd, RXCOMMADETUSE_ipd, RXDATAWIDTH_ipd, RXDEC64B66BUSE_ipd, RXDEC8B10BUSE_ipd, RXDESCRAM64B66BUSE_ipd, RXIGNOREBTF_ipd, RXINTDATAWIDTH_ipd, RXPOLARITY_ipd, RXRESET_ipd, RXSLIDE_ipd, RXUSRCLK_ipd, RXUSRCLK2_ipd, TXBYPASS8B10B_ipd, TXCHARDISPMODE_ipd, TXCHARDISPVAL_ipd, TXCHARISK_ipd, TXDATA_ipd, TXDATAWIDTH_ipd, TXENC64B66BUSE_ipd, TXENC8B10BUSE_ipd, TXGEARBOX64B66BUSE_ipd, TXINHIBIT_ipd, TXINTDATAWIDTH_ipd, TXPOLARITY_ipd, TXRESET_ipd, TXSCRAM64B66BUSE_ipd, TXUSRCLK_ipd, TXUSRCLK2_ipd, RXCLKSTABLE_ipd, RXPMARESET_ipd, TXCLKSTABLE_ipd, TXPMARESET_ipd, RXCRCIN_ipd, RXCRCDATAWIDTH_ipd, RXCRCDATAVALID_ipd, RXCRCINIT_ipd, RXCRCRESET_ipd, RXCRCPD_ipd, RXCRCCLK_ipd, RXCRCINTCLK_ipd, TXCRCIN_ipd, TXCRCDATAWIDTH_ipd, TXCRCDATAVALID_ipd, TXCRCINIT_ipd, TXCRCRESET_ipd, TXCRCPD_ipd, TXCRCCLK_ipd, TXCRCINTCLK_ipd, TXSYNC_ipd, RXSYNC_ipd, TXENOOB_ipd, DCLK_ipd, DADDR_ipd, DEN_ipd, DWE_ipd, DI_ipd, RX1P_ipd, RX1N_ipd, GREFCLK_ipd, REFCLK1_ipd, REFCLK2_ipd, COMBUSIN_ipd; end process TIMING; RXPCSHCLKOUT <= RXPCSHCLKOUT_OUT; TXPCSHCLKOUT <= TXPCSHCLKOUT_OUT; RXMCLK <= RXMCLK_OUT; RXRECCLK1 <= RXRECCLK1_OUT; RXRECCLK2 <= RXRECCLK2_OUT; TXOUTCLK1 <= TXOUTCLK1_OUT; TXOUTCLK2 <= TXOUTCLK2_OUT; TX1N <= TX1N_OUT; TX1P <= TX1P_OUT; COMBUSOUT <= COMBUSOUT_OUT; end GT11_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex4/SMODEL/Attic/ppc405_adv.vhd,v 1.13 2007/09/13 23:04:05 vandanad Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Power PC Core -- /___/ /\ Filename : PPC405_ADV.vhd -- \ \ / \ Timestamp : Fri Jun 18 10:57:02 PDT 2004 -- \___\/\___\ -- -- Revision: -- 03/23/04 - Initial version. ------------------------------------------------------------------------------- -- Model for fpga_startup_virtex4 (for simulation only) ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; entity fpga_startup_virtex4 is port ( bus_reset : out std_ulogic; ghigh_b : out std_ulogic; done : out std_ulogic; gsr : out std_ulogic; gwe : out std_ulogic; gts_b : out std_ulogic; shutdown : in std_ulogic; cclk : in std_ulogic; por : in std_ulogic ); end fpga_startup_virtex4; architecture fpga_startup_virtex4_v of fpga_startup_virtex4 is signal count_changed : boolean := false; begin set_output:process(cclk, por) variable abus_reset : std_ulogic := '0'; variable aghigh_b : std_ulogic := '0'; variable agsr : std_ulogic := '0'; variable adone : std_ulogic := '0'; variable agwe : std_ulogic := '0'; variable agts_b : std_ulogic := '0'; variable count : integer := 0; variable count_last_value : integer := 0; begin if (((cclk'event) and (cclk = '1') and (cclk'last_value = '0')) or ((por'event) and (por = '1') and (por'last_value = '0')))then count_last_value := count; if (por = '1') then count := 0; elsif ((shutdown ='1') and (count > 0)) then count := count - 1; elsif ((shutdown ='0') and (count < 255)) then count := count + 1; end if; if(count_last_value /= count) then count_changed <= true; end if; if (por = '1') then bus_reset <= '0'; ghigh_b <= '0'; gsr <= '0'; done <= '0'; gwe <= '0'; gts_b <= '0'; else bus_reset <= abus_reset; ghigh_b <= aghigh_b; gsr <= agsr; done <= adone; gwe <= agwe; gts_b <= agts_b; end if; end if; if(count_last_value /= count) then abus_reset := '1'; aghigh_b := '0'; agsr := '0'; adone := '0'; agwe := '0'; agts_b := '0'; if (count >= 02) then abus_reset := '0'; end if; if ((count = 23) or (count = 24)) then agsr := '1'; end if; if (count > 39) then aghigh_b := '1'; end if; if (count > 49) then adone := '1'; end if; if ((count = 51) or (count = 52)) then agsr := '1'; end if; if (count > 54) then agwe := '1'; end if; if (count > 55) then agts_b := '1'; end if; end if; end process set_output; end fpga_startup_virtex4_v; ----- CELL PPC405_ADV ----- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; entity PPC405_ADV is generic ( in_delay : time := 1 ps; out_delay : VitalDelayType01 := (100 ps, 100 ps) -- clk-to-output path delays ); port ( APUFCMDECODED : out std_ulogic; APUFCMDECUDI : out std_logic_vector(0 to 2); APUFCMDECUDIVALID : out std_ulogic; APUFCMENDIAN : out std_ulogic; APUFCMFLUSH : out std_ulogic; APUFCMINSTRUCTION : out std_logic_vector(0 to 31); APUFCMINSTRVALID : out std_ulogic; APUFCMLOADBYTEEN : out std_logic_vector(0 to 3); APUFCMLOADDATA : out std_logic_vector(0 to 31); APUFCMLOADDVALID : out std_ulogic; APUFCMOPERANDVALID : out std_ulogic; APUFCMRADATA : out std_logic_vector(0 to 31); APUFCMRBDATA : out std_logic_vector(0 to 31); APUFCMWRITEBACKOK : out std_ulogic; APUFCMXERCA : out std_ulogic; C405CPMCORESLEEPREQ : out std_ulogic; C405CPMMSRCE : out std_ulogic; C405CPMMSREE : out std_ulogic; C405CPMTIMERIRQ : out std_ulogic; C405CPMTIMERRESETREQ : out std_ulogic; C405DBGLOADDATAONAPUDBUS : out std_ulogic; C405DBGMSRWE : out std_ulogic; C405DBGSTOPACK : out std_ulogic; C405DBGWBCOMPLETE : out std_ulogic; C405DBGWBFULL : out std_ulogic; C405DBGWBIAR : out std_logic_vector(0 to 29); C405JTGCAPTUREDR : out std_ulogic; C405JTGEXTEST : out std_ulogic; C405JTGPGMOUT : out std_ulogic; C405JTGSHIFTDR : out std_ulogic; C405JTGTDO : out std_ulogic; C405JTGTDOEN : out std_ulogic; C405JTGUPDATEDR : out std_ulogic; C405PLBDCUABORT : out std_ulogic; C405PLBDCUABUS : out std_logic_vector(0 to 31); C405PLBDCUBE : out std_logic_vector(0 to 7); C405PLBDCUCACHEABLE : out std_ulogic; C405PLBDCUGUARDED : out std_ulogic; C405PLBDCUPRIORITY : out std_logic_vector(0 to 1); C405PLBDCUREQUEST : out std_ulogic; C405PLBDCURNW : out std_ulogic; C405PLBDCUSIZE2 : out std_ulogic; C405PLBDCUU0ATTR : out std_ulogic; C405PLBDCUWRDBUS : out std_logic_vector(0 to 63); C405PLBDCUWRITETHRU : out std_ulogic; C405PLBICUABORT : out std_ulogic; C405PLBICUABUS : out std_logic_vector(0 to 29); C405PLBICUCACHEABLE : out std_ulogic; C405PLBICUPRIORITY : out std_logic_vector(0 to 1); C405PLBICUREQUEST : out std_ulogic; C405PLBICUSIZE : out std_logic_vector(2 to 3); C405PLBICUU0ATTR : out std_ulogic; C405RSTCHIPRESETREQ : out std_ulogic; C405RSTCORERESETREQ : out std_ulogic; C405RSTSYSRESETREQ : out std_ulogic; C405TRCCYCLE : out std_ulogic; C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 to 1); C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 to 1); C405TRCTRACESTATUS : out std_logic_vector(0 to 3); C405TRCTRIGGEREVENTOUT : out std_ulogic; C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 10); C405XXXMACHINECHECK : out std_ulogic; DCREMACABUS : out std_logic_vector(8 to 9); DCREMACCLK : out std_ulogic; DCREMACDBUS : out std_logic_vector(0 to 31); DCREMACENABLER : out std_ulogic; DCREMACREAD : out std_ulogic; DCREMACWRITE : out std_ulogic; DSOCMBRAMABUS : out std_logic_vector(8 to 29); DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3); DSOCMBRAMEN : out std_ulogic; DSOCMBRAMWRDBUS : out std_logic_vector(0 to 31); DSOCMBUSY : out std_ulogic; DSOCMRDADDRVALID : out std_ulogic; DSOCMWRADDRVALID : out std_ulogic; EXTDCRABUS : out std_logic_vector(0 to 9); EXTDCRDBUSOUT : out std_logic_vector(0 to 31); EXTDCRREAD : out std_ulogic; EXTDCRWRITE : out std_ulogic; ISOCMBRAMEN : out std_ulogic; ISOCMBRAMEVENWRITEEN : out std_ulogic; ISOCMBRAMODDWRITEEN : out std_ulogic; ISOCMBRAMRDABUS : out std_logic_vector(8 to 28); ISOCMBRAMWRABUS : out std_logic_vector(8 to 28); ISOCMBRAMWRDBUS : out std_logic_vector(0 to 31); ISOCMDCRBRAMEVENEN : out std_ulogic; ISOCMDCRBRAMODDEN : out std_ulogic; ISOCMDCRBRAMRDSELECT : out std_ulogic; BRAMDSOCMCLK : in std_ulogic; BRAMDSOCMRDDBUS : in std_logic_vector(0 to 31); BRAMISOCMCLK : in std_ulogic; BRAMISOCMDCRRDDBUS : in std_logic_vector(0 to 31); BRAMISOCMRDDBUS : in std_logic_vector(0 to 63); CPMC405CLOCK : in std_ulogic; CPMC405CORECLKINACTIVE : in std_ulogic; CPMC405CPUCLKEN : in std_ulogic; CPMC405JTAGCLKEN : in std_ulogic; CPMC405SYNCBYPASS : in std_ulogic; CPMC405TIMERCLKEN : in std_ulogic; CPMC405TIMERTICK : in std_ulogic; CPMDCRCLK : in std_ulogic; CPMFCMCLK : in std_ulogic; DBGC405DEBUGHALT : in std_ulogic; DBGC405EXTBUSHOLDACK : in std_ulogic; DBGC405UNCONDDEBUGEVENT : in std_ulogic; DSARCVALUE : in std_logic_vector(0 to 7); DSCNTLVALUE : in std_logic_vector(0 to 7); DSOCMRWCOMPLETE : in std_ulogic; EICC405CRITINPUTIRQ : in std_ulogic; EICC405EXTINPUTIRQ : in std_ulogic; EMACDCRACK : in std_ulogic; EMACDCRDBUS : in std_logic_vector(0 to 31); EXTDCRACK : in std_ulogic; EXTDCRDBUSIN : in std_logic_vector(0 to 31); FCMAPUCR : in std_logic_vector(0 to 3); FCMAPUDCDCREN : in std_ulogic; FCMAPUDCDFORCEALIGN : in std_ulogic; FCMAPUDCDFORCEBESTEERING : in std_ulogic; FCMAPUDCDFPUOP : in std_ulogic; FCMAPUDCDGPRWRITE : in std_ulogic; FCMAPUDCDLDSTBYTE : in std_ulogic; FCMAPUDCDLDSTDW : in std_ulogic; FCMAPUDCDLDSTHW : in std_ulogic; FCMAPUDCDLDSTQW : in std_ulogic; FCMAPUDCDLDSTWD : in std_ulogic; FCMAPUDCDLOAD : in std_ulogic; FCMAPUDCDPRIVOP : in std_ulogic; FCMAPUDCDRAEN : in std_ulogic; FCMAPUDCDRBEN : in std_ulogic; FCMAPUDCDSTORE : in std_ulogic; FCMAPUDCDTRAPBE : in std_ulogic; FCMAPUDCDTRAPLE : in std_ulogic; FCMAPUDCDUPDATE : in std_ulogic; FCMAPUDCDXERCAEN : in std_ulogic; FCMAPUDCDXEROVEN : in std_ulogic; FCMAPUDECODEBUSY : in std_ulogic; FCMAPUDONE : in std_ulogic; FCMAPUEXCEPTION : in std_ulogic; FCMAPUEXEBLOCKINGMCO : in std_ulogic; FCMAPUEXECRFIELD : in std_logic_vector(0 to 2); FCMAPUEXENONBLOCKINGMCO : in std_ulogic; FCMAPUINSTRACK : in std_ulogic; FCMAPULOADWAIT : in std_ulogic; FCMAPURESULT : in std_logic_vector(0 to 31); FCMAPURESULTVALID : in std_ulogic; FCMAPUSLEEPNOTREADY : in std_ulogic; FCMAPUXERCA : in std_ulogic; FCMAPUXEROV : in std_ulogic; ISARCVALUE : in std_logic_vector(0 to 7); ISCNTLVALUE : in std_logic_vector(0 to 7); JTGC405BNDSCANTDO : in std_ulogic; JTGC405TCK : in std_ulogic; JTGC405TDI : in std_ulogic; JTGC405TMS : in std_ulogic; JTGC405TRSTNEG : in std_ulogic; MCBCPUCLKEN : in std_ulogic; MCBJTAGEN : in std_ulogic; MCBTIMEREN : in std_ulogic; MCPPCRST : in std_ulogic; PLBC405DCUADDRACK : in std_ulogic; PLBC405DCUBUSY : in std_ulogic; PLBC405DCUERR : in std_ulogic; PLBC405DCURDDACK : in std_ulogic; PLBC405DCURDDBUS : in std_logic_vector(0 to 63); PLBC405DCURDWDADDR : in std_logic_vector(1 to 3); PLBC405DCUSSIZE1 : in std_ulogic; PLBC405DCUWRDACK : in std_ulogic; PLBC405ICUADDRACK : in std_ulogic; PLBC405ICUBUSY : in std_ulogic; PLBC405ICUERR : in std_ulogic; PLBC405ICURDDACK : in std_ulogic; PLBC405ICURDDBUS : in std_logic_vector(0 to 63); PLBC405ICURDWDADDR : in std_logic_vector(1 to 3); PLBC405ICUSSIZE1 : in std_ulogic; PLBCLK : in std_ulogic; RSTC405RESETCHIP : in std_ulogic; RSTC405RESETCORE : in std_ulogic; RSTC405RESETSYS : in std_ulogic; TIEAPUCONTROL : in std_logic_vector(0 to 15); TIEAPUUDI1 : in std_logic_vector(0 to 23); TIEAPUUDI2 : in std_logic_vector(0 to 23); TIEAPUUDI3 : in std_logic_vector(0 to 23); TIEAPUUDI4 : in std_logic_vector(0 to 23); TIEAPUUDI5 : in std_logic_vector(0 to 23); TIEAPUUDI6 : in std_logic_vector(0 to 23); TIEAPUUDI7 : in std_logic_vector(0 to 23); TIEAPUUDI8 : in std_logic_vector(0 to 23); TIEC405DETERMINISTICMULT : in std_ulogic; TIEC405DISOPERANDFWD : in std_ulogic; TIEC405MMUEN : in std_ulogic; TIEDCRADDR : in std_logic_vector(0 to 5); TIEPVRBIT10 : in std_ulogic; TIEPVRBIT11 : in std_ulogic; TIEPVRBIT28 : in std_ulogic; TIEPVRBIT29 : in std_ulogic; TIEPVRBIT30 : in std_ulogic; TIEPVRBIT31 : in std_ulogic; TIEPVRBIT8 : in std_ulogic; TIEPVRBIT9 : in std_ulogic; TRCC405TRACEDISABLE : in std_ulogic; TRCC405TRIGGEREVENTIN : in std_ulogic ); end PPC405_ADV; architecture PPC405_ADV_V of PPC405_ADV is component PPC405_ADV_SWIFT_BUS port ( CFG_MCLK : in std_logic; BUS_RESET : in std_logic; GSR : in std_logic; GWE : in std_logic; GHIGHB : in std_logic; CPMC405CPUCLKEN : in std_logic; CPMC405JTAGCLKEN : in std_logic; CPMC405TIMERCLKEN : in std_logic; C405JTGPGMOUT : out std_logic; MCBCPUCLKEN : in std_logic; MCBJTAGEN : in std_logic; MCBTIMEREN : in std_logic; MCPPCRST : in std_logic; C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 to 1); C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 to 1); CPMC405CLOCK : in std_logic; CPMC405CORECLKINACTIVE : in std_logic; PLBCLK : in std_logic; CPMFCMCLK : in std_logic; CPMDCRCLK : in std_logic; CPMC405SYNCBYPASS : in std_logic; CPMC405TIMERTICK : in std_logic; C405CPMMSREE : out std_logic; C405CPMMSRCE : out std_logic; C405CPMTIMERIRQ : out std_logic; C405CPMTIMERRESETREQ : out std_logic; C405CPMCORESLEEPREQ : out std_logic; TIEC405DISOPERANDFWD : in std_logic; TIEC405DETERMINISTICMULT : in std_logic; TIEC405MMUEN : in std_logic; TIEPVRBIT8 : in std_logic; TIEPVRBIT9 : in std_logic; TIEPVRBIT10 : in std_logic; TIEPVRBIT11 : in std_logic; TIEPVRBIT28 : in std_logic; TIEPVRBIT29 : in std_logic; TIEPVRBIT30 : in std_logic; TIEPVRBIT31 : in std_logic; C405XXXMACHINECHECK : out std_logic; DCREMACENABLER : out std_logic; DCREMACCLK : out std_logic; DCREMACWRITE : out std_logic; DCREMACREAD : out std_logic; DCREMACDBUS : out std_logic_vector(0 to 31); DCREMACABUS : out std_logic_vector(8 to 9); EMACDCRDBUS : in std_logic_vector(0 to 31); EMACDCRACK : in std_logic; C405RSTCHIPRESETREQ : out std_logic; C405RSTCORERESETREQ : out std_logic; C405RSTSYSRESETREQ : out std_logic; RSTC405RESETCHIP : in std_logic; RSTC405RESETCORE : in std_logic; RSTC405RESETSYS : in std_logic; C405PLBICUREQUEST : out std_logic; C405PLBICUPRIORITY : out std_logic_vector(0 to 1); C405PLBICUCACHEABLE : out std_logic; C405PLBICUABUS : out std_logic_vector(0 to 29); C405PLBICUSIZE : out std_logic_vector(2 to 3); C405PLBICUABORT : out std_logic; C405PLBICUU0ATTR : out std_logic; PLBC405ICUADDRACK : in std_logic; PLBC405ICUBUSY : in std_logic; PLBC405ICUERR : in std_logic; PLBC405ICURDDACK : in std_logic; PLBC405ICURDDBUS :in std_logic_vector(0 to 63); PLBC405ICUSSIZE1 : in std_logic; PLBC405ICURDWDADDR : in std_logic_vector(1 to 3); C405PLBDCUREQUEST : out std_logic; C405PLBDCURNW : out std_logic; C405PLBDCUABUS : out std_logic_vector(0 to 31); C405PLBDCUBE : out std_logic_vector(0 to 7); C405PLBDCUCACHEABLE : out std_logic; C405PLBDCUGUARDED : out std_logic; C405PLBDCUPRIORITY : out std_logic_vector(0 to 1); C405PLBDCUSIZE2 : out std_logic; C405PLBDCUABORT : out std_logic; C405PLBDCUWRDBUS : out std_logic_vector(0 to 63); C405PLBDCUU0ATTR : out std_logic; C405PLBDCUWRITETHRU : out std_logic; PLBC405DCUADDRACK : in std_logic; PLBC405DCUBUSY : in std_logic; PLBC405DCUERR : in std_logic; PLBC405DCURDDACK : in std_logic; PLBC405DCURDDBUS : in std_logic_vector(0 to 63); PLBC405DCURDWDADDR : in std_logic_vector(1 to 3); PLBC405DCUSSIZE1 : in std_logic; PLBC405DCUWRDACK : in std_logic; ISOCMBRAMRDABUS : out std_logic_vector(8 to 28); ISOCMBRAMWRABUS : out std_logic_vector(8 to 28); ISOCMBRAMEN : out std_logic; ISOCMBRAMODDWRITEEN : out std_logic; ISOCMBRAMEVENWRITEEN : out std_logic; ISOCMBRAMWRDBUS : out std_logic_vector(0 to 31); ISOCMDCRBRAMEVENEN : out std_logic; ISOCMDCRBRAMODDEN : out std_logic; ISOCMDCRBRAMRDSELECT : out std_logic; BRAMISOCMDCRRDDBUS : in std_logic_vector(0 to 31); BRAMISOCMRDDBUS : in std_logic_vector(0 to 63); ISARCVALUE : in std_logic_vector(0 to 7); ISCNTLVALUE : in std_logic_vector(0 to 7); BRAMISOCMCLK : in std_logic; DSOCMBRAMABUS : out std_logic_vector(8 to 29); DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3); DSOCMBRAMEN : out std_logic; DSOCMBRAMWRDBUS : out std_logic_vector(0 to 31); BRAMDSOCMRDDBUS : in std_logic_vector(0 to 31); DSOCMRWCOMPLETE : in std_logic; DSOCMBUSY : out std_logic; DSOCMWRADDRVALID : out std_logic; DSOCMRDADDRVALID : out std_logic; TIEDCRADDR : in std_logic_vector(0 to 5); DSARCVALUE : in std_logic_vector(0 to 7); DSCNTLVALUE : in std_logic_vector(0 to 7); BRAMDSOCMCLK : in std_logic; EXTDCRREAD : out std_logic; EXTDCRWRITE : out std_logic; EXTDCRABUS : out std_logic_vector(0 to 9); EXTDCRDBUSOUT : out std_logic_vector(0 to 31); EXTDCRACK : in std_logic; EXTDCRDBUSIN : in std_logic_vector(0 to 31); EICC405EXTINPUTIRQ : in std_logic; EICC405CRITINPUTIRQ : in std_logic; JTGC405BNDSCANTDO : in std_logic; JTGC405TCK : in std_logic; JTGC405TDI : in std_logic; JTGC405TMS : in std_logic; JTGC405TRSTNEG : in std_logic; C405JTGTDO : out std_logic; C405JTGTDOEN : out std_logic; C405JTGEXTEST : out std_logic; C405JTGCAPTUREDR : out std_logic; C405JTGSHIFTDR : out std_logic; C405JTGUPDATEDR : out std_logic; DBGC405DEBUGHALT : in std_logic; DBGC405UNCONDDEBUGEVENT : in std_logic; DBGC405EXTBUSHOLDACK : in std_logic; C405DBGMSRWE : out std_logic; C405DBGSTOPACK : out std_logic; C405DBGWBCOMPLETE : out std_logic; C405DBGWBFULL : out std_logic; C405DBGWBIAR : out std_logic_vector(0 to 29); C405TRCTRIGGEREVENTOUT : out std_logic; C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 10); C405TRCCYCLE : out std_logic; C405TRCTRACESTATUS : out std_logic_vector(0 to 3); TRCC405TRACEDISABLE : in std_logic; TRCC405TRIGGEREVENTIN : in std_logic; C405DBGLOADDATAONAPUDBUS : out std_logic; APUFCMINSTRUCTION : out std_logic_vector(0 to 31); APUFCMRADATA : out std_logic_vector(0 to 31); APUFCMRBDATA : out std_logic_vector(0 to 31); APUFCMINSTRVALID : out std_logic; APUFCMLOADDATA : out std_logic_vector(0 to 31); APUFCMOPERANDVALID : out std_logic; APUFCMLOADDVALID : out std_logic; APUFCMFLUSH : out std_logic; APUFCMWRITEBACKOK : out std_logic; APUFCMLOADBYTEEN : out std_logic_vector(0 to 3); APUFCMENDIAN : out std_logic; APUFCMXERCA : out std_logic; APUFCMDECODED : out std_logic; APUFCMDECUDI : out std_logic_vector(0 to 2); APUFCMDECUDIVALID : out std_logic; FCMAPUDONE : in std_logic; FCMAPURESULT : in std_logic_vector(0 to 31); FCMAPURESULTVALID : in std_logic; FCMAPUINSTRACK : in std_logic; FCMAPUEXCEPTION : in std_logic; FCMAPUXERCA : in std_logic; FCMAPUXEROV : in std_logic; FCMAPUCR : in std_logic_vector(0 to 3); FCMAPUDCDFPUOP : in std_logic; FCMAPUDCDGPRWRITE : in std_logic; FCMAPUDCDRAEN : in std_logic; FCMAPUDCDRBEN : in std_logic; FCMAPUDCDLOAD : in std_logic; FCMAPUDCDSTORE : in std_logic; FCMAPUDCDXERCAEN : in std_logic; FCMAPUDCDXEROVEN : in std_logic; FCMAPUDCDPRIVOP : in std_logic; FCMAPUDCDCREN : in std_logic; FCMAPUEXECRFIELD : in std_logic_vector(0 to 2); FCMAPUDCDUPDATE : in std_logic; FCMAPUDCDFORCEALIGN : in std_logic; FCMAPUDCDFORCEBESTEERING : in std_logic; FCMAPUDCDLDSTBYTE : in std_logic; FCMAPUDCDLDSTHW : in std_logic; FCMAPUDCDLDSTWD : in std_logic; FCMAPUDCDLDSTDW : in std_logic; FCMAPUDCDLDSTQW : in std_logic; FCMAPUDCDTRAPBE : in std_logic; FCMAPUDCDTRAPLE : in std_logic; FCMAPUEXEBLOCKINGMCO : in std_logic; FCMAPUEXENONBLOCKINGMCO : in std_logic; FCMAPUSLEEPNOTREADY : in std_logic; FCMAPULOADWAIT : in std_logic; FCMAPUDECODEBUSY : in std_logic; TIEAPUCONTROL : in std_logic_vector(0 to 15); TIEAPUUDI1 : in std_logic_vector(0 to 23); TIEAPUUDI2 : in std_logic_vector(0 to 23); TIEAPUUDI3 : in std_logic_vector(0 to 23); TIEAPUUDI4 : in std_logic_vector(0 to 23); TIEAPUUDI5 : in std_logic_vector(0 to 23); TIEAPUUDI6 : in std_logic_vector(0 to 23); TIEAPUUDI7 : in std_logic_vector(0 to 23); TIEAPUUDI8 : in std_logic_vector(0 to 23) ); end component; ----- component fpga_startup_virtex4 ----- component fpga_startup_virtex4 port ( bus_reset : out std_ulogic; done : out std_ulogic; ghigh_b : out std_ulogic; gsr : out std_ulogic; gts_b : out std_ulogic; gwe : out std_ulogic; cclk : in std_ulogic; por : in std_ulogic; shutdown : in std_ulogic ); end component; signal APUFCMDECODED_out : std_ulogic; signal APUFCMDECUDI_out : std_logic_vector(0 to 2); signal APUFCMDECUDIVALID_out : std_ulogic; signal APUFCMENDIAN_out : std_ulogic; signal APUFCMFLUSH_out : std_ulogic; signal APUFCMINSTRUCTION_out : std_logic_vector(0 to 31); signal APUFCMINSTRVALID_out : std_ulogic; signal APUFCMLOADBYTEEN_out : std_logic_vector(0 to 3); signal APUFCMLOADDATA_out : std_logic_vector(0 to 31); signal APUFCMLOADDVALID_out : std_ulogic; signal APUFCMOPERANDVALID_out : std_ulogic; signal APUFCMRADATA_out : std_logic_vector(0 to 31); signal APUFCMRBDATA_out : std_logic_vector(0 to 31); signal APUFCMWRITEBACKOK_out : std_ulogic; signal APUFCMXERCA_out : std_ulogic; signal C405CPMCORESLEEPREQ_out : std_ulogic; signal C405CPMMSRCE_out : std_ulogic; signal C405CPMMSREE_out : std_ulogic; signal C405CPMTIMERIRQ_out : std_ulogic; signal C405CPMTIMERRESETREQ_out : std_ulogic; signal C405DBGLOADDATAONAPUDBUS_out : std_ulogic; signal C405DBGMSRWE_out : std_ulogic; signal C405DBGSTOPACK_out : std_ulogic; signal C405DBGWBCOMPLETE_out : std_ulogic; signal C405DBGWBFULL_out : std_ulogic; signal C405DBGWBIAR_out : std_logic_vector(0 to 29); signal C405JTGCAPTUREDR_out : std_ulogic; signal C405JTGEXTEST_out : std_ulogic; signal C405JTGPGMOUT_out : std_ulogic; signal C405JTGSHIFTDR_out : std_ulogic; signal C405JTGTDO_out : std_ulogic; signal C405JTGTDOEN_out : std_ulogic; signal C405JTGUPDATEDR_out : std_ulogic; signal C405PLBDCUABORT_out : std_ulogic; signal C405PLBDCUABUS_out : std_logic_vector(0 to 31); signal C405PLBDCUBE_out : std_logic_vector(0 to 7); signal C405PLBDCUCACHEABLE_out : std_ulogic; signal C405PLBDCUGUARDED_out : std_ulogic; signal C405PLBDCUPRIORITY_out : std_logic_vector(0 to 1); signal C405PLBDCUREQUEST_out : std_ulogic; signal C405PLBDCURNW_out : std_ulogic; signal C405PLBDCUSIZE2_out : std_ulogic; signal C405PLBDCUU0ATTR_out : std_ulogic; signal C405PLBDCUWRDBUS_out : std_logic_vector(0 to 63); signal C405PLBDCUWRITETHRU_out : std_ulogic; signal C405PLBICUABORT_out : std_ulogic; signal C405PLBICUABUS_out : std_logic_vector(0 to 29); signal C405PLBICUCACHEABLE_out : std_ulogic; signal C405PLBICUPRIORITY_out : std_logic_vector(0 to 1); signal C405PLBICUREQUEST_out : std_ulogic; signal C405PLBICUSIZE_out : std_logic_vector(2 to 3); signal C405PLBICUU0ATTR_out : std_ulogic; signal C405RSTCHIPRESETREQ_out : std_ulogic; signal C405RSTCORERESETREQ_out : std_ulogic; signal C405RSTSYSRESETREQ_out : std_ulogic; signal C405TRCCYCLE_out : std_ulogic; signal C405TRCEVENEXECUTIONSTATUS_out : std_logic_vector(0 to 1); signal C405TRCODDEXECUTIONSTATUS_out : std_logic_vector(0 to 1); signal C405TRCTRACESTATUS_out : std_logic_vector(0 to 3); signal C405TRCTRIGGEREVENTOUT_out : std_ulogic; signal C405TRCTRIGGEREVENTTYPE_out : std_logic_vector(0 to 10); signal C405XXXMACHINECHECK_out : std_ulogic; signal DCREMACENABLER_out : std_ulogic; signal DSOCMBRAMABUS_out : std_logic_vector(8 to 29); signal DSOCMBRAMBYTEWRITE_out : std_logic_vector(0 to 3); signal DSOCMBRAMEN_out : std_ulogic; signal DSOCMBRAMWRDBUS_out : std_logic_vector(0 to 31); signal DSOCMBUSY_out : std_ulogic; signal DSOCMRDADDRVALID_out : std_ulogic; signal DSOCMWRADDRVALID_out : std_ulogic; signal EXTDCRABUS_out : std_logic_vector(0 to 9); signal EXTDCRDBUSOUT_out : std_logic_vector(0 to 31); signal EXTDCRREAD_out : std_ulogic; signal EXTDCRWRITE_out : std_ulogic; signal ISOCMBRAMEN_out : std_ulogic; signal ISOCMBRAMEVENWRITEEN_out : std_ulogic; signal ISOCMBRAMODDWRITEEN_out : std_ulogic; signal ISOCMBRAMRDABUS_out : std_logic_vector(8 to 28); signal ISOCMBRAMWRABUS_out : std_logic_vector(8 to 28); signal ISOCMBRAMWRDBUS_out : std_logic_vector(0 to 31); signal ISOCMDCRBRAMEVENEN_out : std_ulogic; signal ISOCMDCRBRAMODDEN_out : std_ulogic; signal ISOCMDCRBRAMRDSELECT_out : std_ulogic; signal DCREMACWRITE_out : std_ulogic; signal DCREMACREAD_out : std_ulogic; signal DCREMACDBUS_out : std_logic_vector(0 to 31); signal DCREMACABUS_out : std_logic_vector(8 to 9); signal DCREMACCLK_out : std_ulogic; signal GSR_ipd : std_ulogic; signal BRAMDSOCMCLK_ipd : std_ulogic; signal BRAMDSOCMRDDBUS_ipd : std_logic_vector(0 to 31); signal BRAMISOCMCLK_ipd : std_ulogic; signal BRAMISOCMDCRRDDBUS_ipd : std_logic_vector(0 to 31); signal BRAMISOCMRDDBUS_ipd : std_logic_vector(0 to 63); signal CPMC405CLOCK_ipd : std_ulogic; signal CPMC405CORECLKINACTIVE_ipd : std_ulogic; signal CPMC405CPUCLKEN_ipd : std_ulogic; signal CPMC405JTAGCLKEN_ipd : std_ulogic; signal CPMC405SYNCBYPASS_ipd : std_ulogic; signal CPMC405TIMERCLKEN_ipd : std_ulogic; signal CPMC405TIMERTICK_ipd : std_ulogic; signal CPMDCRCLK_ipd : std_ulogic; signal CPMFCMCLK_ipd : std_ulogic; signal DBGC405DEBUGHALT_ipd : std_ulogic; signal DBGC405EXTBUSHOLDACK_ipd : std_ulogic; signal DBGC405UNCONDDEBUGEVENT_ipd : std_ulogic; signal DSARCVALUE_ipd : std_logic_vector(0 to 7); signal DSCNTLVALUE_ipd : std_logic_vector(0 to 7); signal DSOCMRWCOMPLETE_ipd : std_ulogic; signal EICC405CRITINPUTIRQ_ipd : std_ulogic; signal EICC405EXTINPUTIRQ_ipd : std_ulogic; signal EXTDCRACK_ipd : std_ulogic; signal EXTDCRDBUSIN_ipd : std_logic_vector(0 to 31); signal FCMAPUCR_ipd : std_logic_vector(0 to 3); signal FCMAPUDCDCREN_ipd : std_ulogic; signal FCMAPUDCDFORCEALIGN_ipd : std_ulogic; signal FCMAPUDCDFORCEBESTEERING_ipd : std_ulogic; signal FCMAPUDCDFPUOP_ipd : std_ulogic; signal FCMAPUDCDGPRWRITE_ipd : std_ulogic; signal FCMAPUDCDLDSTBYTE_ipd : std_ulogic; signal FCMAPUDCDLDSTDW_ipd : std_ulogic; signal FCMAPUDCDLDSTHW_ipd : std_ulogic; signal FCMAPUDCDLDSTQW_ipd : std_ulogic; signal FCMAPUDCDLDSTWD_ipd : std_ulogic; signal FCMAPUDCDLOAD_ipd : std_ulogic; signal FCMAPUDCDPRIVOP_ipd : std_ulogic; signal FCMAPUDCDRAEN_ipd : std_ulogic; signal FCMAPUDCDRBEN_ipd : std_ulogic; signal FCMAPUDCDSTORE_ipd : std_ulogic; signal FCMAPUDCDTRAPBE_ipd : std_ulogic; signal FCMAPUDCDTRAPLE_ipd : std_ulogic; signal FCMAPUDCDUPDATE_ipd : std_ulogic; signal FCMAPUDCDXERCAEN_ipd : std_ulogic; signal FCMAPUDCDXEROVEN_ipd : std_ulogic; signal FCMAPUDECODEBUSY_ipd : std_ulogic; signal FCMAPUDONE_ipd : std_ulogic; signal FCMAPUEXCEPTION_ipd : std_ulogic; signal FCMAPUEXEBLOCKINGMCO_ipd : std_ulogic; signal FCMAPUEXECRFIELD_ipd : std_logic_vector(0 to 2); signal FCMAPUEXENONBLOCKINGMCO_ipd : std_ulogic; signal FCMAPUINSTRACK_ipd : std_ulogic; signal FCMAPULOADWAIT_ipd : std_ulogic; signal FCMAPURESULT_ipd : std_logic_vector(0 to 31); signal FCMAPURESULTVALID_ipd : std_ulogic; signal FCMAPUSLEEPNOTREADY_ipd : std_ulogic; signal FCMAPUXERCA_ipd : std_ulogic; signal FCMAPUXEROV_ipd : std_ulogic; signal ISARCVALUE_ipd : std_logic_vector(0 to 7); signal ISCNTLVALUE_ipd : std_logic_vector(0 to 7); signal JTGC405BNDSCANTDO_ipd : std_ulogic; signal JTGC405TCK_ipd : std_ulogic; signal JTGC405TDI_ipd : std_ulogic; signal JTGC405TMS_ipd : std_ulogic; signal JTGC405TRSTNEG_ipd : std_ulogic; signal MCBCPUCLKEN_ipd : std_ulogic; signal MCBJTAGEN_ipd : std_ulogic; signal MCBTIMEREN_ipd : std_ulogic; signal MCPPCRST_ipd : std_ulogic; signal PLBC405DCUADDRACK_ipd : std_ulogic; signal PLBC405DCUBUSY_ipd : std_ulogic; signal PLBC405DCUERR_ipd : std_ulogic; signal PLBC405DCURDDACK_ipd : std_ulogic; signal PLBC405DCURDDBUS_ipd : std_logic_vector(0 to 63); signal PLBC405DCURDWDADDR_ipd : std_logic_vector(1 to 3); signal PLBC405DCUSSIZE1_ipd : std_ulogic; signal PLBC405DCUWRDACK_ipd : std_ulogic; signal PLBC405ICUADDRACK_ipd : std_ulogic; signal PLBC405ICUBUSY_ipd : std_ulogic; signal PLBC405ICUERR_ipd : std_ulogic; signal PLBC405ICURDDACK_ipd : std_ulogic; signal PLBC405ICURDDBUS_ipd : std_logic_vector(0 to 63); signal PLBC405ICURDWDADDR_ipd : std_logic_vector(1 to 3); signal PLBC405ICUSSIZE1_ipd : std_ulogic; signal PLBCLK_ipd : std_ulogic; signal RSTC405RESETCHIP_ipd : std_ulogic; signal RSTC405RESETCORE_ipd : std_ulogic; signal RSTC405RESETSYS_ipd : std_ulogic; signal TIEAPUCONTROL_ipd : std_logic_vector(0 to 15); signal TIEAPUUDI1_ipd : std_logic_vector(0 to 23); signal TIEAPUUDI2_ipd : std_logic_vector(0 to 23); signal TIEAPUUDI3_ipd : std_logic_vector(0 to 23); signal TIEAPUUDI4_ipd : std_logic_vector(0 to 23); signal TIEAPUUDI5_ipd : std_logic_vector(0 to 23); signal TIEAPUUDI6_ipd : std_logic_vector(0 to 23); signal TIEAPUUDI7_ipd : std_logic_vector(0 to 23); signal TIEAPUUDI8_ipd : std_logic_vector(0 to 23); signal TIEC405DETERMINISTICMULT_ipd : std_ulogic; signal TIEC405DISOPERANDFWD_ipd : std_ulogic; signal TIEC405MMUEN_ipd : std_ulogic; signal TIEDCRADDR_ipd : std_logic_vector(0 to 5); signal TIEPVRBIT10_ipd : std_ulogic; signal TIEPVRBIT11_ipd : std_ulogic; signal TIEPVRBIT28_ipd : std_ulogic; signal TIEPVRBIT29_ipd : std_ulogic; signal TIEPVRBIT30_ipd : std_ulogic; signal TIEPVRBIT31_ipd : std_ulogic; signal TIEPVRBIT8_ipd : std_ulogic; signal TIEPVRBIT9_ipd : std_ulogic; signal TRCC405TRACEDISABLE_ipd : std_ulogic; signal TRCC405TRIGGEREVENTIN_ipd : std_ulogic; signal EMACDCRDBUS_ipd : std_logic_vector(0 to 31); signal EMACDCRACK_ipd : std_ulogic; signal GSR_ipd_1 : std_ulogic; signal BRAMDSOCMCLK_ipd_1 : std_ulogic; signal BRAMDSOCMRDDBUS_ipd_1 : std_logic_vector(0 to 31); signal BRAMISOCMCLK_ipd_1 : std_ulogic; signal BRAMISOCMDCRRDDBUS_ipd_1 : std_logic_vector(0 to 31); signal BRAMISOCMRDDBUS_ipd_1 : std_logic_vector(0 to 63); signal CPMC405CLOCK_ipd_1 : std_ulogic; signal CPMC405CORECLKINACTIVE_ipd_1 : std_ulogic; signal CPMC405CPUCLKEN_ipd_1 : std_ulogic; signal CPMC405JTAGCLKEN_ipd_1 : std_ulogic; signal CPMC405SYNCBYPASS_ipd_1 : std_ulogic; signal CPMC405TIMERCLKEN_ipd_1 : std_ulogic; signal CPMC405TIMERTICK_ipd_1 : std_ulogic; signal CPMDCRCLK_ipd_1 : std_ulogic; signal CPMFCMCLK_ipd_1 : std_ulogic; signal DBGC405DEBUGHALT_ipd_1 : std_ulogic; signal DBGC405EXTBUSHOLDACK_ipd_1 : std_ulogic; signal DBGC405UNCONDDEBUGEVENT_ipd_1 : std_ulogic; signal DSARCVALUE_ipd_1 : std_logic_vector(0 to 7); signal DSCNTLVALUE_ipd_1 : std_logic_vector(0 to 7); signal DSOCMRWCOMPLETE_ipd_1 : std_ulogic; signal EICC405CRITINPUTIRQ_ipd_1 : std_ulogic; signal EICC405EXTINPUTIRQ_ipd_1 : std_ulogic; signal EXTDCRACK_ipd_1 : std_ulogic; signal EXTDCRDBUSIN_ipd_1 : std_logic_vector(0 to 31); signal FCMAPUCR_ipd_1 : std_logic_vector(0 to 3); signal FCMAPUDCDCREN_ipd_1 : std_ulogic; signal FCMAPUDCDFORCEALIGN_ipd_1 : std_ulogic; signal FCMAPUDCDFORCEBESTEERING_ipd_1 : std_ulogic; signal FCMAPUDCDFPUOP_ipd_1 : std_ulogic; signal FCMAPUDCDGPRWRITE_ipd_1 : std_ulogic; signal FCMAPUDCDLDSTBYTE_ipd_1 : std_ulogic; signal FCMAPUDCDLDSTDW_ipd_1 : std_ulogic; signal FCMAPUDCDLDSTHW_ipd_1 : std_ulogic; signal FCMAPUDCDLDSTQW_ipd_1 : std_ulogic; signal FCMAPUDCDLDSTWD_ipd_1 : std_ulogic; signal FCMAPUDCDLOAD_ipd_1 : std_ulogic; signal FCMAPUDCDPRIVOP_ipd_1 : std_ulogic; signal FCMAPUDCDRAEN_ipd_1 : std_ulogic; signal FCMAPUDCDRBEN_ipd_1 : std_ulogic; signal FCMAPUDCDSTORE_ipd_1 : std_ulogic; signal FCMAPUDCDTRAPBE_ipd_1 : std_ulogic; signal FCMAPUDCDTRAPLE_ipd_1 : std_ulogic; signal FCMAPUDCDUPDATE_ipd_1 : std_ulogic; signal FCMAPUDCDXERCAEN_ipd_1 : std_ulogic; signal FCMAPUDCDXEROVEN_ipd_1 : std_ulogic; signal FCMAPUDECODEBUSY_ipd_1 : std_ulogic; signal FCMAPUDONE_ipd_1 : std_ulogic; signal FCMAPUEXCEPTION_ipd_1 : std_ulogic; signal FCMAPUEXEBLOCKINGMCO_ipd_1 : std_ulogic; signal FCMAPUEXECRFIELD_ipd_1 : std_logic_vector(0 to 2); signal FCMAPUEXENONBLOCKINGMCO_ipd_1 : std_ulogic; signal FCMAPUINSTRACK_ipd_1 : std_ulogic; signal FCMAPULOADWAIT_ipd_1 : std_ulogic; signal FCMAPURESULT_ipd_1 : std_logic_vector(0 to 31); signal FCMAPURESULTVALID_ipd_1 : std_ulogic; signal FCMAPUSLEEPNOTREADY_ipd_1 : std_ulogic; signal FCMAPUXERCA_ipd_1 : std_ulogic; signal FCMAPUXEROV_ipd_1 : std_ulogic; signal ISARCVALUE_ipd_1 : std_logic_vector(0 to 7); signal ISCNTLVALUE_ipd_1 : std_logic_vector(0 to 7); signal JTGC405BNDSCANTDO_ipd_1 : std_ulogic; signal JTGC405TCK_ipd_1 : std_ulogic; signal JTGC405TDI_ipd_1 : std_ulogic; signal JTGC405TMS_ipd_1 : std_ulogic; signal JTGC405TRSTNEG_ipd_1 : std_ulogic; signal MCBCPUCLKEN_ipd_1 : std_ulogic; signal MCBJTAGEN_ipd_1 : std_ulogic; signal MCBTIMEREN_ipd_1 : std_ulogic; signal MCPPCRST_ipd_1 : std_ulogic; signal PLBC405DCUADDRACK_ipd_1 : std_ulogic; signal PLBC405DCUBUSY_ipd_1 : std_ulogic; signal PLBC405DCUERR_ipd_1 : std_ulogic; signal PLBC405DCURDDACK_ipd_1 : std_ulogic; signal PLBC405DCURDDBUS_ipd_1 : std_logic_vector(0 to 63); signal PLBC405DCURDWDADDR_ipd_1 : std_logic_vector(1 to 3); signal PLBC405DCUSSIZE1_ipd_1 : std_ulogic; signal PLBC405DCUWRDACK_ipd_1 : std_ulogic; signal PLBC405ICUADDRACK_ipd_1 : std_ulogic; signal PLBC405ICUBUSY_ipd_1 : std_ulogic; signal PLBC405ICUERR_ipd_1 : std_ulogic; signal PLBC405ICURDDACK_ipd_1 : std_ulogic; signal PLBC405ICURDDBUS_ipd_1 : std_logic_vector(0 to 63); signal PLBC405ICURDWDADDR_ipd_1 : std_logic_vector(1 to 3); signal PLBC405ICUSSIZE1_ipd_1 : std_ulogic; signal PLBCLK_ipd_1 : std_ulogic; signal RSTC405RESETCHIP_ipd_1 : std_ulogic; signal RSTC405RESETCORE_ipd_1 : std_ulogic; signal RSTC405RESETSYS_ipd_1 : std_ulogic; signal TIEAPUCONTROL_ipd_1 : std_logic_vector(0 to 15); signal TIEAPUUDI1_ipd_1 : std_logic_vector(0 to 23); signal TIEAPUUDI2_ipd_1 : std_logic_vector(0 to 23); signal TIEAPUUDI3_ipd_1 : std_logic_vector(0 to 23); signal TIEAPUUDI4_ipd_1 : std_logic_vector(0 to 23); signal TIEAPUUDI5_ipd_1 : std_logic_vector(0 to 23); signal TIEAPUUDI6_ipd_1 : std_logic_vector(0 to 23); signal TIEAPUUDI7_ipd_1 : std_logic_vector(0 to 23); signal TIEAPUUDI8_ipd_1 : std_logic_vector(0 to 23); signal TIEC405DETERMINISTICMULT_ipd_1 : std_ulogic; signal TIEC405DISOPERANDFWD_ipd_1 : std_ulogic; signal TIEC405MMUEN_ipd_1 : std_ulogic; signal TIEDCRADDR_ipd_1 : std_logic_vector(0 to 5); signal TIEPVRBIT10_ipd_1 : std_ulogic; signal TIEPVRBIT11_ipd_1 : std_ulogic; signal TIEPVRBIT28_ipd_1 : std_ulogic; signal TIEPVRBIT29_ipd_1 : std_ulogic; signal TIEPVRBIT30_ipd_1 : std_ulogic; signal TIEPVRBIT31_ipd_1 : std_ulogic; signal TIEPVRBIT8_ipd_1 : std_ulogic; signal TIEPVRBIT9_ipd_1 : std_ulogic; signal TRCC405TRACEDISABLE_ipd_1 : std_ulogic; signal TRCC405TRIGGEREVENTIN_ipd_1 : std_ulogic; signal EMACDCRDBUS_ipd_1 : std_logic_vector(0 to 31); signal EMACDCRACK_ipd_1 : std_ulogic; signal open_sig : std_ulogic; signal VCC_sig : std_ulogic := '1'; signal GND_sig : std_ulogic := '0'; signal FPGA_CCLK : std_ulogic := '0'; signal FPGA_POR : std_ulogic := '1'; signal FPGA_BUS_RESET : std_ulogic := '0'; signal FPGA_GWE : std_ulogic := '0'; signal FPGA_GHIGHB : std_ulogic := '0'; signal FPGA_GSR : std_ulogic := '0'; signal GSR_OR : std_ulogic := '0'; signal GSR : std_ulogic := '0'; signal FPGA_SHUTDOWN : std_ulogic := '0'; signal FPGA_CCLK_delay : std_ulogic := '0'; signal FPGA_BUS_RESET_delay : std_ulogic := '0'; signal GSR_delay : std_ulogic := '0'; signal FPGA_GWE_delay : std_ulogic := '0'; signal FPGA_GHIGHB_delay : std_ulogic := '0'; signal FPGA_CCLK_reg : std_ulogic := '0'; -- signal ppcuser_binary : std_logic_vector(0 to 3) := PPCUSER; begin BRAMDSOCMCLK_ipd <= BRAMDSOCMCLK; BRAMDSOCMRDDBUS_ipd <= BRAMDSOCMRDDBUS after 0 ps; BRAMISOCMCLK_ipd <= BRAMISOCMCLK; BRAMISOCMDCRRDDBUS_ipd <= BRAMISOCMDCRRDDBUS after 0 ps; BRAMISOCMRDDBUS_ipd <= BRAMISOCMRDDBUS after 0 ps; CPMC405CLOCK_ipd <= CPMC405CLOCK; CPMC405CORECLKINACTIVE_ipd <= CPMC405CORECLKINACTIVE after 0 ps; CPMC405CPUCLKEN_ipd <= CPMC405CPUCLKEN after 0 ps; CPMC405JTAGCLKEN_ipd <= CPMC405JTAGCLKEN after 0 ps; CPMC405SYNCBYPASS_ipd <= CPMC405SYNCBYPASS after 0 ps; CPMC405TIMERCLKEN_ipd <= CPMC405TIMERCLKEN after 0 ps; CPMC405TIMERTICK_ipd <= CPMC405TIMERTICK after 0 ps; CPMDCRCLK_ipd <= CPMDCRCLK; CPMFCMCLK_ipd <= CPMFCMCLK; DBGC405DEBUGHALT_ipd <= DBGC405DEBUGHALT after 0 ps; DBGC405EXTBUSHOLDACK_ipd <= DBGC405EXTBUSHOLDACK after 0 ps; DBGC405UNCONDDEBUGEVENT_ipd <= DBGC405UNCONDDEBUGEVENT after 0 ps; DSARCVALUE_ipd <= DSARCVALUE after 0 ps; DSCNTLVALUE_ipd <= DSCNTLVALUE after 0 ps; DSOCMRWCOMPLETE_ipd <= DSOCMRWCOMPLETE after 0 ps; EICC405CRITINPUTIRQ_ipd <= EICC405CRITINPUTIRQ after 0 ps; EICC405EXTINPUTIRQ_ipd <= EICC405EXTINPUTIRQ after 0 ps; EMACDCRACK_ipd <= EMACDCRACK after 0 ps; EMACDCRDBUS_ipd <= EMACDCRDBUS after 0 ps; EXTDCRACK_ipd <= EXTDCRACK after 0 ps; EXTDCRDBUSIN_ipd <= EXTDCRDBUSIN after 0 ps; FCMAPUCR_ipd <= FCMAPUCR after 0 ps; FCMAPUDCDCREN_ipd <= FCMAPUDCDCREN after 0 ps; FCMAPUDCDFORCEALIGN_ipd <= FCMAPUDCDFORCEALIGN after 0 ps; FCMAPUDCDFORCEBESTEERING_ipd <= FCMAPUDCDFORCEBESTEERING after 0 ps; FCMAPUDCDFPUOP_ipd <= FCMAPUDCDFPUOP after 0 ps; FCMAPUDCDGPRWRITE_ipd <= FCMAPUDCDGPRWRITE after 0 ps; FCMAPUDCDLDSTBYTE_ipd <= FCMAPUDCDLDSTBYTE after 0 ps; FCMAPUDCDLDSTDW_ipd <= FCMAPUDCDLDSTDW after 0 ps; FCMAPUDCDLDSTHW_ipd <= FCMAPUDCDLDSTHW after 0 ps; FCMAPUDCDLDSTQW_ipd <= FCMAPUDCDLDSTQW after 0 ps; FCMAPUDCDLDSTWD_ipd <= FCMAPUDCDLDSTWD after 0 ps; FCMAPUDCDLOAD_ipd <= FCMAPUDCDLOAD after 0 ps; FCMAPUDCDPRIVOP_ipd <= FCMAPUDCDPRIVOP after 0 ps; FCMAPUDCDRAEN_ipd <= FCMAPUDCDRAEN after 0 ps; FCMAPUDCDRBEN_ipd <= FCMAPUDCDRBEN after 0 ps; FCMAPUDCDSTORE_ipd <= FCMAPUDCDSTORE after 0 ps; FCMAPUDCDTRAPBE_ipd <= FCMAPUDCDTRAPBE after 0 ps; FCMAPUDCDTRAPLE_ipd <= FCMAPUDCDTRAPLE after 0 ps; FCMAPUDCDUPDATE_ipd <= FCMAPUDCDUPDATE after 0 ps; FCMAPUDCDXERCAEN_ipd <= FCMAPUDCDXERCAEN after 0 ps; FCMAPUDCDXEROVEN_ipd <= FCMAPUDCDXEROVEN after 0 ps; FCMAPUDECODEBUSY_ipd <= FCMAPUDECODEBUSY after 0 ps; FCMAPUDONE_ipd <= FCMAPUDONE after 0 ps; FCMAPUEXCEPTION_ipd <= FCMAPUEXCEPTION after 0 ps; FCMAPUEXEBLOCKINGMCO_ipd <= FCMAPUEXEBLOCKINGMCO after 0 ps; FCMAPUEXECRFIELD_ipd <= FCMAPUEXECRFIELD after 0 ps; FCMAPUEXENONBLOCKINGMCO_ipd <= FCMAPUEXENONBLOCKINGMCO after 0 ps; FCMAPUINSTRACK_ipd <= FCMAPUINSTRACK after 0 ps; FCMAPULOADWAIT_ipd <= FCMAPULOADWAIT after 0 ps; FCMAPURESULT_ipd <= FCMAPURESULT after 0 ps; FCMAPURESULTVALID_ipd <= FCMAPURESULTVALID after 0 ps; FCMAPUSLEEPNOTREADY_ipd <= FCMAPUSLEEPNOTREADY after 0 ps; FCMAPUXERCA_ipd <= FCMAPUXERCA after 0 ps; FCMAPUXEROV_ipd <= FCMAPUXEROV after 0 ps; ISARCVALUE_ipd <= ISARCVALUE after 0 ps; ISCNTLVALUE_ipd <= ISCNTLVALUE after 0 ps; JTGC405BNDSCANTDO_ipd <= JTGC405BNDSCANTDO after 0 ps; JTGC405TCK_ipd <= JTGC405TCK; JTGC405TDI_ipd <= JTGC405TDI after 0 ps; JTGC405TMS_ipd <= JTGC405TMS after 0 ps; JTGC405TRSTNEG_ipd <= JTGC405TRSTNEG after 0 ps; MCBCPUCLKEN_ipd <= MCBCPUCLKEN after 0 ps; MCBJTAGEN_ipd <= MCBJTAGEN after 0 ps; MCBTIMEREN_ipd <= MCBTIMEREN after 0 ps; MCPPCRST_ipd <= MCPPCRST after 0 ps; PLBC405DCUADDRACK_ipd <= PLBC405DCUADDRACK after 0 ps; PLBC405DCUBUSY_ipd <= PLBC405DCUBUSY after 0 ps; PLBC405DCUERR_ipd <= PLBC405DCUERR after 0 ps; PLBC405DCURDDACK_ipd <= PLBC405DCURDDACK after 0 ps; PLBC405DCURDDBUS_ipd <= PLBC405DCURDDBUS after 0 ps; PLBC405DCURDWDADDR_ipd <= PLBC405DCURDWDADDR after 0 ps; PLBC405DCUSSIZE1_ipd <= PLBC405DCUSSIZE1 after 0 ps; PLBC405DCUWRDACK_ipd <= PLBC405DCUWRDACK after 0 ps; PLBC405ICUADDRACK_ipd <= PLBC405ICUADDRACK after 0 ps; PLBC405ICUBUSY_ipd <= PLBC405ICUBUSY after 0 ps; PLBC405ICUERR_ipd <= PLBC405ICUERR after 0 ps; PLBC405ICURDDACK_ipd <= PLBC405ICURDDACK after 0 ps; PLBC405ICURDDBUS_ipd <= PLBC405ICURDDBUS after 0 ps; PLBC405ICURDWDADDR_ipd <= PLBC405ICURDWDADDR after 0 ps; PLBC405ICUSSIZE1_ipd <= PLBC405ICUSSIZE1 after 0 ps; PLBCLK_ipd <= PLBCLK; RSTC405RESETCHIP_ipd <= RSTC405RESETCHIP after 0 ps; RSTC405RESETCORE_ipd <= RSTC405RESETCORE after 0 ps; RSTC405RESETSYS_ipd <= RSTC405RESETSYS after 0 ps; TIEAPUCONTROL_ipd <= TIEAPUCONTROL after 0 ps; TIEAPUUDI1_ipd <= TIEAPUUDI1 after 0 ps; TIEAPUUDI2_ipd <= TIEAPUUDI2 after 0 ps; TIEAPUUDI3_ipd <= TIEAPUUDI3 after 0 ps; TIEAPUUDI4_ipd <= TIEAPUUDI4 after 0 ps; TIEAPUUDI5_ipd <= TIEAPUUDI5 after 0 ps; TIEAPUUDI6_ipd <= TIEAPUUDI6 after 0 ps; TIEAPUUDI7_ipd <= TIEAPUUDI7 after 0 ps; TIEAPUUDI8_ipd <= TIEAPUUDI8 after 0 ps; TIEC405DETERMINISTICMULT_ipd <= TIEC405DETERMINISTICMULT after 0 ps; TIEC405DISOPERANDFWD_ipd <= TIEC405DISOPERANDFWD after 0 ps; TIEC405MMUEN_ipd <= TIEC405MMUEN after 0 ps; TIEDCRADDR_ipd <= TIEDCRADDR after 0 ps; TIEPVRBIT10_ipd <= TIEPVRBIT10 after 0 ps; TIEPVRBIT11_ipd <= TIEPVRBIT11 after 0 ps; TIEPVRBIT28_ipd <= TIEPVRBIT28 after 0 ps; TIEPVRBIT29_ipd <= TIEPVRBIT29 after 0 ps; TIEPVRBIT30_ipd <= TIEPVRBIT30 after 0 ps; TIEPVRBIT31_ipd <= TIEPVRBIT31 after 0 ps; TIEPVRBIT8_ipd <= TIEPVRBIT8 after 0 ps; TIEPVRBIT9_ipd <= TIEPVRBIT9 after 0 ps; TRCC405TRACEDISABLE_ipd <= TRCC405TRACEDISABLE after 0 ps; TRCC405TRIGGEREVENTIN_ipd <= TRCC405TRIGGEREVENTIN after 0 ps; BRAMDSOCMCLK_ipd_1 <= BRAMDSOCMCLK_ipd; BRAMDSOCMRDDBUS_ipd_1 <= BRAMDSOCMRDDBUS_ipd after in_delay; BRAMISOCMCLK_ipd_1 <= BRAMISOCMCLK_ipd; BRAMISOCMDCRRDDBUS_ipd_1 <= BRAMISOCMDCRRDDBUS_ipd after in_delay; BRAMISOCMRDDBUS_ipd_1 <= BRAMISOCMRDDBUS_ipd after in_delay; CPMC405CLOCK_ipd_1 <= CPMC405CLOCK_ipd; CPMC405CORECLKINACTIVE_ipd_1 <= CPMC405CORECLKINACTIVE_ipd after in_delay; CPMC405CPUCLKEN_ipd_1 <= CPMC405CPUCLKEN_ipd after in_delay; CPMC405JTAGCLKEN_ipd_1 <= CPMC405JTAGCLKEN_ipd after in_delay; CPMC405SYNCBYPASS_ipd_1 <= CPMC405SYNCBYPASS_ipd after in_delay; CPMC405TIMERCLKEN_ipd_1 <= CPMC405TIMERCLKEN_ipd after in_delay; CPMC405TIMERTICK_ipd_1 <= CPMC405TIMERTICK_ipd after in_delay; CPMDCRCLK_ipd_1 <= CPMDCRCLK_ipd; CPMFCMCLK_ipd_1 <= CPMFCMCLK_ipd; DBGC405DEBUGHALT_ipd_1 <= DBGC405DEBUGHALT_ipd after in_delay; DBGC405EXTBUSHOLDACK_ipd_1 <= DBGC405EXTBUSHOLDACK_ipd after in_delay; DBGC405UNCONDDEBUGEVENT_ipd_1 <= DBGC405UNCONDDEBUGEVENT_ipd after in_delay; DSARCVALUE_ipd_1 <= DSARCVALUE_ipd after in_delay; DSCNTLVALUE_ipd_1 <= DSCNTLVALUE_ipd after in_delay; DSOCMRWCOMPLETE_ipd_1 <= DSOCMRWCOMPLETE_ipd after in_delay; EICC405CRITINPUTIRQ_ipd_1 <= EICC405CRITINPUTIRQ_ipd after in_delay; EICC405EXTINPUTIRQ_ipd_1 <= EICC405EXTINPUTIRQ_ipd after in_delay; EMACDCRACK_ipd_1 <= EMACDCRACK_ipd after in_delay; EMACDCRDBUS_ipd_1 <= EMACDCRDBUS_ipd after in_delay; EXTDCRACK_ipd_1 <= EXTDCRACK_ipd after in_delay; EXTDCRDBUSIN_ipd_1 <= EXTDCRDBUSIN_ipd after in_delay; FCMAPUCR_ipd_1 <= FCMAPUCR_ipd after in_delay; FCMAPUDCDCREN_ipd_1 <= FCMAPUDCDCREN_ipd after in_delay; FCMAPUDCDFORCEALIGN_ipd_1 <= FCMAPUDCDFORCEALIGN_ipd after in_delay; FCMAPUDCDFORCEBESTEERING_ipd_1 <= FCMAPUDCDFORCEBESTEERING_ipd after in_delay; FCMAPUDCDFPUOP_ipd_1 <= FCMAPUDCDFPUOP_ipd after in_delay; FCMAPUDCDGPRWRITE_ipd_1 <= FCMAPUDCDGPRWRITE_ipd after in_delay; FCMAPUDCDLDSTBYTE_ipd_1 <= FCMAPUDCDLDSTBYTE_ipd after in_delay; FCMAPUDCDLDSTDW_ipd_1 <= FCMAPUDCDLDSTDW_ipd after in_delay; FCMAPUDCDLDSTHW_ipd_1 <= FCMAPUDCDLDSTHW_ipd after in_delay; FCMAPUDCDLDSTQW_ipd_1 <= FCMAPUDCDLDSTQW_ipd after in_delay; FCMAPUDCDLDSTWD_ipd_1 <= FCMAPUDCDLDSTWD_ipd after in_delay; FCMAPUDCDLOAD_ipd_1 <= FCMAPUDCDLOAD_ipd after in_delay; FCMAPUDCDPRIVOP_ipd_1 <= FCMAPUDCDPRIVOP_ipd after in_delay; FCMAPUDCDRAEN_ipd_1 <= FCMAPUDCDRAEN_ipd after in_delay; FCMAPUDCDRBEN_ipd_1 <= FCMAPUDCDRBEN_ipd after in_delay; FCMAPUDCDSTORE_ipd_1 <= FCMAPUDCDSTORE_ipd after in_delay; FCMAPUDCDTRAPBE_ipd_1 <= FCMAPUDCDTRAPBE_ipd after in_delay; FCMAPUDCDTRAPLE_ipd_1 <= FCMAPUDCDTRAPLE_ipd after in_delay; FCMAPUDCDUPDATE_ipd_1 <= FCMAPUDCDUPDATE_ipd after in_delay; FCMAPUDCDXERCAEN_ipd_1 <= FCMAPUDCDXERCAEN_ipd after in_delay; FCMAPUDCDXEROVEN_ipd_1 <= FCMAPUDCDXEROVEN_ipd after in_delay; FCMAPUDECODEBUSY_ipd_1 <= FCMAPUDECODEBUSY_ipd after in_delay; FCMAPUDONE_ipd_1 <= FCMAPUDONE_ipd after in_delay; FCMAPUEXCEPTION_ipd_1 <= FCMAPUEXCEPTION_ipd after in_delay; FCMAPUEXEBLOCKINGMCO_ipd_1 <= FCMAPUEXEBLOCKINGMCO_ipd after in_delay; FCMAPUEXECRFIELD_ipd_1 <= FCMAPUEXECRFIELD_ipd after in_delay; FCMAPUEXENONBLOCKINGMCO_ipd_1 <= FCMAPUEXENONBLOCKINGMCO_ipd after in_delay; FCMAPUINSTRACK_ipd_1 <= FCMAPUINSTRACK_ipd after in_delay; FCMAPULOADWAIT_ipd_1 <= FCMAPULOADWAIT_ipd after in_delay; FCMAPURESULT_ipd_1 <= FCMAPURESULT_ipd after in_delay; FCMAPURESULTVALID_ipd_1 <= FCMAPURESULTVALID_ipd after in_delay; FCMAPUSLEEPNOTREADY_ipd_1 <= FCMAPUSLEEPNOTREADY_ipd after in_delay; FCMAPUXERCA_ipd_1 <= FCMAPUXERCA_ipd after in_delay; FCMAPUXEROV_ipd_1 <= FCMAPUXEROV_ipd after in_delay; ISARCVALUE_ipd_1 <= ISARCVALUE_ipd after in_delay; ISCNTLVALUE_ipd_1 <= ISCNTLVALUE_ipd after in_delay; JTGC405BNDSCANTDO_ipd_1 <= JTGC405BNDSCANTDO_ipd after in_delay; JTGC405TCK_ipd_1 <= JTGC405TCK_ipd; JTGC405TDI_ipd_1 <= JTGC405TDI_ipd after in_delay; JTGC405TMS_ipd_1 <= JTGC405TMS_ipd after in_delay; JTGC405TRSTNEG_ipd_1 <= JTGC405TRSTNEG_ipd after in_delay; MCBCPUCLKEN_ipd_1 <= MCBCPUCLKEN_ipd after in_delay; MCBJTAGEN_ipd_1 <= MCBJTAGEN_ipd after in_delay; MCBTIMEREN_ipd_1 <= MCBTIMEREN_ipd after in_delay; MCPPCRST_ipd_1 <= MCPPCRST_ipd after in_delay; PLBC405DCUADDRACK_ipd_1 <= PLBC405DCUADDRACK_ipd after in_delay; PLBC405DCUBUSY_ipd_1 <= PLBC405DCUBUSY_ipd after in_delay; PLBC405DCUERR_ipd_1 <= PLBC405DCUERR_ipd after in_delay; PLBC405DCURDDACK_ipd_1 <= PLBC405DCURDDACK_ipd after in_delay; PLBC405DCURDDBUS_ipd_1 <= PLBC405DCURDDBUS_ipd after in_delay; PLBC405DCURDWDADDR_ipd_1 <= PLBC405DCURDWDADDR_ipd after in_delay; PLBC405DCUSSIZE1_ipd_1 <= PLBC405DCUSSIZE1_ipd after in_delay; PLBC405DCUWRDACK_ipd_1 <= PLBC405DCUWRDACK_ipd after in_delay; PLBC405ICUADDRACK_ipd_1 <= PLBC405ICUADDRACK_ipd after in_delay; PLBC405ICUBUSY_ipd_1 <= PLBC405ICUBUSY_ipd after in_delay; PLBC405ICUERR_ipd_1 <= PLBC405ICUERR_ipd after in_delay; PLBC405ICURDDACK_ipd_1 <= PLBC405ICURDDACK_ipd after in_delay; PLBC405ICURDDBUS_ipd_1 <= PLBC405ICURDDBUS_ipd after in_delay; PLBC405ICURDWDADDR_ipd_1 <= PLBC405ICURDWDADDR_ipd after in_delay; PLBC405ICUSSIZE1_ipd_1 <= PLBC405ICUSSIZE1_ipd after in_delay; PLBCLK_ipd_1 <= PLBCLK_ipd; RSTC405RESETCHIP_ipd_1 <= RSTC405RESETCHIP_ipd after in_delay; RSTC405RESETCORE_ipd_1 <= RSTC405RESETCORE_ipd after in_delay; RSTC405RESETSYS_ipd_1 <= RSTC405RESETSYS_ipd after in_delay; TIEAPUCONTROL_ipd_1 <= TIEAPUCONTROL_ipd after in_delay; TIEAPUUDI1_ipd_1 <= TIEAPUUDI1_ipd after in_delay; TIEAPUUDI2_ipd_1 <= TIEAPUUDI2_ipd after in_delay; TIEAPUUDI3_ipd_1 <= TIEAPUUDI3_ipd after in_delay; TIEAPUUDI4_ipd_1 <= TIEAPUUDI4_ipd after in_delay; TIEAPUUDI5_ipd_1 <= TIEAPUUDI5_ipd after in_delay; TIEAPUUDI6_ipd_1 <= TIEAPUUDI6_ipd after in_delay; TIEAPUUDI7_ipd_1 <= TIEAPUUDI7_ipd after in_delay; TIEAPUUDI8_ipd_1 <= TIEAPUUDI8_ipd after in_delay; TIEC405DETERMINISTICMULT_ipd_1 <= TIEC405DETERMINISTICMULT_ipd after in_delay; TIEC405DISOPERANDFWD_ipd_1 <= TIEC405DISOPERANDFWD_ipd after in_delay; TIEC405MMUEN_ipd_1 <= TIEC405MMUEN_ipd after in_delay; TIEDCRADDR_ipd_1 <= TIEDCRADDR_ipd after in_delay; TIEPVRBIT10_ipd_1 <= TIEPVRBIT10_ipd after in_delay; TIEPVRBIT11_ipd_1 <= TIEPVRBIT11_ipd after in_delay; TIEPVRBIT28_ipd_1 <= TIEPVRBIT28_ipd after in_delay; TIEPVRBIT29_ipd_1 <= TIEPVRBIT29_ipd after in_delay; TIEPVRBIT30_ipd_1 <= TIEPVRBIT30_ipd after in_delay; TIEPVRBIT31_ipd_1 <= TIEPVRBIT31_ipd after in_delay; TIEPVRBIT8_ipd_1 <= TIEPVRBIT8_ipd after in_delay; TIEPVRBIT9_ipd_1 <= TIEPVRBIT9_ipd after in_delay; TRCC405TRACEDISABLE_ipd_1 <= TRCC405TRACEDISABLE_ipd after in_delay; TRCC405TRIGGEREVENTIN_ipd_1 <= TRCC405TRIGGEREVENTIN_ipd after in_delay; ppc405_adv_swift_bw_1 : PPC405_ADV_SWIFT_BUS port map ( CFG_MCLK => FPGA_CCLK, BUS_RESET => FPGA_BUS_RESET_delay, GSR => GSR_delay, GWE => FPGA_GWE_delay, GHIGHB => FPGA_GHIGHB_delay, CPMC405CPUCLKEN => CPMC405CPUCLKEN_ipd_1, CPMC405JTAGCLKEN => CPMC405JTAGCLKEN_ipd_1, CPMC405TIMERCLKEN => CPMC405TIMERCLKEN_ipd_1, C405JTGPGMOUT => C405JTGPGMOUT_out, MCBCPUCLKEN => MCBCPUCLKEN_ipd_1, MCBJTAGEN => MCBJTAGEN_ipd_1, MCBTIMEREN => MCBTIMEREN_ipd_1, MCPPCRST => MCPPCRST_ipd_1, C405TRCODDEXECUTIONSTATUS => C405TRCODDEXECUTIONSTATUS_out, C405TRCEVENEXECUTIONSTATUS => C405TRCEVENEXECUTIONSTATUS_out, CPMC405CLOCK => CPMC405CLOCK_ipd_1, CPMC405CORECLKINACTIVE => CPMC405CORECLKINACTIVE_ipd_1, PLBCLK => PLBCLK_ipd_1, CPMFCMCLK => CPMFCMCLK_ipd_1, CPMDCRCLK => CPMDCRCLK_ipd_1, CPMC405SYNCBYPASS => CPMC405SYNCBYPASS_ipd_1, CPMC405TIMERTICK => CPMC405TIMERTICK_ipd_1, C405CPMMSREE => C405CPMMSREE_out, C405CPMMSRCE => C405CPMMSRCE_out, C405CPMTIMERIRQ => C405CPMTIMERIRQ_out, C405CPMTIMERRESETREQ => C405CPMTIMERRESETREQ_out, C405CPMCORESLEEPREQ => C405CPMCORESLEEPREQ_out, TIEC405DISOPERANDFWD => TIEC405DISOPERANDFWD_ipd_1, TIEC405DETERMINISTICMULT => TIEC405DETERMINISTICMULT_ipd_1, TIEC405MMUEN => TIEC405MMUEN_ipd_1, TIEPVRBIT8 => TIEPVRBIT8_ipd_1, TIEPVRBIT9 => TIEPVRBIT9_ipd_1, TIEPVRBIT10 => TIEPVRBIT10_ipd_1, TIEPVRBIT11 => TIEPVRBIT11_ipd_1, TIEPVRBIT28 => TIEPVRBIT28_ipd_1, TIEPVRBIT29 => TIEPVRBIT29_ipd_1, TIEPVRBIT30 => TIEPVRBIT30_ipd_1, TIEPVRBIT31 => TIEPVRBIT31_ipd_1, C405XXXMACHINECHECK => C405XXXMACHINECHECK_out, DCREMACENABLER => DCREMACENABLER_out, DCREMACCLK => DCREMACCLK_out, DCREMACWRITE => DCREMACWRITE_out, DCREMACREAD => DCREMACREAD_out, DCREMACDBUS => DCREMACDBUS_out, DCREMACABUS => DCREMACABUS_out, EMACDCRDBUS => EMACDCRDBUS_ipd_1, EMACDCRACK => EMACDCRACK_ipd_1, C405RSTCHIPRESETREQ => C405RSTCHIPRESETREQ_out, C405RSTCORERESETREQ => C405RSTCORERESETREQ_out, C405RSTSYSRESETREQ => C405RSTSYSRESETREQ_out, RSTC405RESETCHIP => RSTC405RESETCHIP_ipd_1, RSTC405RESETCORE => RSTC405RESETCORE_ipd_1, RSTC405RESETSYS => RSTC405RESETSYS_ipd_1, C405PLBICUREQUEST => C405PLBICUREQUEST_out, C405PLBICUPRIORITY => C405PLBICUPRIORITY_out, C405PLBICUCACHEABLE => C405PLBICUCACHEABLE_out, C405PLBICUABUS => C405PLBICUABUS_out, C405PLBICUSIZE => C405PLBICUSIZE_out, C405PLBICUABORT => C405PLBICUABORT_out, C405PLBICUU0ATTR => C405PLBICUU0ATTR_out, PLBC405ICUADDRACK => PLBC405ICUADDRACK_ipd_1, PLBC405ICUBUSY => PLBC405ICUBUSY_ipd_1, PLBC405ICUERR => PLBC405ICUERR_ipd_1, PLBC405ICURDDACK => PLBC405ICURDDACK_ipd_1, PLBC405ICURDDBUS => PLBC405ICURDDBUS_ipd_1, PLBC405ICUSSIZE1 => PLBC405ICUSSIZE1_ipd_1, PLBC405ICURDWDADDR => PLBC405ICURDWDADDR_ipd_1, C405PLBDCUREQUEST => C405PLBDCUREQUEST_out, C405PLBDCURNW => C405PLBDCURNW_out, C405PLBDCUABUS => C405PLBDCUABUS_out, C405PLBDCUBE => C405PLBDCUBE_out, C405PLBDCUCACHEABLE => C405PLBDCUCACHEABLE_out, C405PLBDCUGUARDED => C405PLBDCUGUARDED_out, C405PLBDCUPRIORITY => C405PLBDCUPRIORITY_out, C405PLBDCUSIZE2 => C405PLBDCUSIZE2_out, C405PLBDCUABORT => C405PLBDCUABORT_out, C405PLBDCUWRDBUS => C405PLBDCUWRDBUS_out, C405PLBDCUU0ATTR => C405PLBDCUU0ATTR_out, C405PLBDCUWRITETHRU => C405PLBDCUWRITETHRU_out, PLBC405DCUADDRACK => PLBC405DCUADDRACK_ipd_1, PLBC405DCUBUSY => PLBC405DCUBUSY_ipd_1, PLBC405DCUERR => PLBC405DCUERR_ipd_1, PLBC405DCURDDACK => PLBC405DCURDDACK_ipd_1, PLBC405DCURDDBUS => PLBC405DCURDDBUS_ipd_1, PLBC405DCURDWDADDR => PLBC405DCURDWDADDR_ipd_1, PLBC405DCUSSIZE1 => PLBC405DCUSSIZE1_ipd_1, PLBC405DCUWRDACK => PLBC405DCUWRDACK_ipd_1, ISOCMBRAMRDABUS => ISOCMBRAMRDABUS_out, ISOCMBRAMWRABUS => ISOCMBRAMWRABUS_out, ISOCMBRAMEN => ISOCMBRAMEN_out, ISOCMBRAMODDWRITEEN => ISOCMBRAMODDWRITEEN_out, ISOCMBRAMEVENWRITEEN => ISOCMBRAMEVENWRITEEN_out, ISOCMBRAMWRDBUS => ISOCMBRAMWRDBUS_out, ISOCMDCRBRAMEVENEN => ISOCMDCRBRAMEVENEN_out, ISOCMDCRBRAMODDEN => ISOCMDCRBRAMODDEN_out, ISOCMDCRBRAMRDSELECT => ISOCMDCRBRAMRDSELECT_out, BRAMISOCMDCRRDDBUS => BRAMISOCMDCRRDDBUS_ipd_1, BRAMISOCMRDDBUS => BRAMISOCMRDDBUS_ipd_1, ISARCVALUE => ISARCVALUE_ipd_1, ISCNTLVALUE => ISCNTLVALUE_ipd_1, BRAMISOCMCLK => BRAMISOCMCLK_ipd_1, DSOCMBRAMABUS => DSOCMBRAMABUS_out, DSOCMBRAMBYTEWRITE => DSOCMBRAMBYTEWRITE_out, DSOCMBRAMEN => DSOCMBRAMEN_out, DSOCMBRAMWRDBUS => DSOCMBRAMWRDBUS_out, BRAMDSOCMRDDBUS => BRAMDSOCMRDDBUS_ipd_1, DSOCMRWCOMPLETE => DSOCMRWCOMPLETE_ipd_1, DSOCMBUSY => DSOCMBUSY_out, DSOCMWRADDRVALID => DSOCMWRADDRVALID_out, DSOCMRDADDRVALID => DSOCMRDADDRVALID_out, TIEDCRADDR => TIEDCRADDR_ipd_1, DSARCVALUE => DSARCVALUE_ipd_1, DSCNTLVALUE => DSCNTLVALUE_ipd_1, BRAMDSOCMCLK => BRAMDSOCMCLK_ipd_1, EXTDCRREAD => EXTDCRREAD_out, EXTDCRWRITE => EXTDCRWRITE_out, EXTDCRABUS => EXTDCRABUS_out, EXTDCRDBUSOUT => EXTDCRDBUSOUT_out, EXTDCRACK => EXTDCRACK_ipd_1, EXTDCRDBUSIN => EXTDCRDBUSIN_ipd_1, EICC405EXTINPUTIRQ => EICC405EXTINPUTIRQ_ipd_1, EICC405CRITINPUTIRQ => EICC405CRITINPUTIRQ_ipd_1, JTGC405BNDSCANTDO => JTGC405BNDSCANTDO_ipd_1, JTGC405TCK => JTGC405TCK_ipd_1, JTGC405TDI => JTGC405TDI_ipd_1, JTGC405TMS => JTGC405TMS, JTGC405TRSTNEG => JTGC405TRSTNEG_ipd_1, C405JTGTDO => C405JTGTDO_out, C405JTGTDOEN => C405JTGTDOEN_out, C405JTGEXTEST => C405JTGEXTEST_out, C405JTGCAPTUREDR => C405JTGCAPTUREDR_out, C405JTGSHIFTDR => C405JTGSHIFTDR_out, C405JTGUPDATEDR => C405JTGUPDATEDR_out, DBGC405DEBUGHALT => DBGC405DEBUGHALT_ipd_1, DBGC405UNCONDDEBUGEVENT => DBGC405UNCONDDEBUGEVENT_ipd_1, DBGC405EXTBUSHOLDACK => DBGC405EXTBUSHOLDACK_ipd_1, C405DBGMSRWE => C405DBGMSRWE_out, C405DBGSTOPACK => C405DBGSTOPACK_out, C405DBGWBCOMPLETE => C405DBGWBCOMPLETE_out, C405DBGWBFULL => C405DBGWBFULL_out, C405DBGWBIAR => C405DBGWBIAR_out, C405TRCTRIGGEREVENTOUT => C405TRCTRIGGEREVENTOUT_out, C405TRCTRIGGEREVENTTYPE => C405TRCTRIGGEREVENTTYPE_out, C405TRCCYCLE => C405TRCCYCLE_out, C405TRCTRACESTATUS => C405TRCTRACESTATUS_out, TRCC405TRACEDISABLE => TRCC405TRACEDISABLE_ipd_1, TRCC405TRIGGEREVENTIN => TRCC405TRIGGEREVENTIN_ipd_1, C405DBGLOADDATAONAPUDBUS => C405DBGLOADDATAONAPUDBUS_out, APUFCMINSTRUCTION => APUFCMINSTRUCTION_out, APUFCMRADATA => APUFCMRADATA_out, APUFCMRBDATA => APUFCMRBDATA_out, APUFCMINSTRVALID => APUFCMINSTRVALID_out, APUFCMLOADDATA => APUFCMLOADDATA_out, APUFCMOPERANDVALID => APUFCMOPERANDVALID_out, APUFCMLOADDVALID => APUFCMLOADDVALID_out, APUFCMFLUSH => APUFCMFLUSH_out, APUFCMWRITEBACKOK => APUFCMWRITEBACKOK_out, APUFCMLOADBYTEEN => APUFCMLOADBYTEEN_out, APUFCMENDIAN => APUFCMENDIAN_out, APUFCMXERCA => APUFCMXERCA_out, APUFCMDECODED => APUFCMDECODED_out, APUFCMDECUDI => APUFCMDECUDI_out, APUFCMDECUDIVALID => APUFCMDECUDIVALID_out, FCMAPUDONE => FCMAPUDONE_ipd_1, FCMAPURESULT => FCMAPURESULT_ipd_1, FCMAPURESULTVALID => FCMAPURESULTVALID_ipd_1, FCMAPUINSTRACK => FCMAPUINSTRACK_ipd_1, FCMAPUEXCEPTION => FCMAPUEXCEPTION_ipd_1, FCMAPUXERCA => FCMAPUXERCA_ipd_1, FCMAPUXEROV => FCMAPUXEROV_ipd_1, FCMAPUCR => FCMAPUCR_ipd_1, FCMAPUDCDFPUOP => FCMAPUDCDFPUOP_ipd_1, FCMAPUDCDGPRWRITE => FCMAPUDCDGPRWRITE_ipd_1, FCMAPUDCDRAEN => FCMAPUDCDRAEN_ipd_1, FCMAPUDCDRBEN => FCMAPUDCDRBEN_ipd_1, FCMAPUDCDLOAD => FCMAPUDCDLOAD_ipd_1, FCMAPUDCDSTORE => FCMAPUDCDSTORE_ipd_1, FCMAPUDCDXERCAEN => FCMAPUDCDXERCAEN_ipd_1, FCMAPUDCDXEROVEN => FCMAPUDCDXEROVEN_ipd_1, FCMAPUDCDPRIVOP => FCMAPUDCDPRIVOP_ipd_1, FCMAPUDCDCREN => FCMAPUDCDCREN_ipd_1, FCMAPUEXECRFIELD => FCMAPUEXECRFIELD_ipd_1, FCMAPUDCDUPDATE => FCMAPUDCDUPDATE_ipd_1, FCMAPUDCDFORCEALIGN => FCMAPUDCDFORCEALIGN_ipd_1, FCMAPUDCDFORCEBESTEERING => FCMAPUDCDFORCEBESTEERING_ipd_1, FCMAPUDCDLDSTBYTE => FCMAPUDCDLDSTBYTE_ipd_1, FCMAPUDCDLDSTHW => FCMAPUDCDLDSTHW_ipd_1, FCMAPUDCDLDSTWD => FCMAPUDCDLDSTWD_ipd_1, FCMAPUDCDLDSTDW => FCMAPUDCDLDSTDW_ipd_1, FCMAPUDCDLDSTQW => FCMAPUDCDLDSTQW_ipd_1, FCMAPUDCDTRAPBE => FCMAPUDCDTRAPBE_ipd_1, FCMAPUDCDTRAPLE => FCMAPUDCDTRAPLE_ipd_1, FCMAPUEXEBLOCKINGMCO => FCMAPUEXEBLOCKINGMCO_ipd_1, FCMAPUEXENONBLOCKINGMCO => FCMAPUEXENONBLOCKINGMCO_ipd_1, FCMAPUSLEEPNOTREADY => FCMAPUSLEEPNOTREADY_ipd_1, FCMAPULOADWAIT => FCMAPULOADWAIT_ipd_1, FCMAPUDECODEBUSY => FCMAPUDECODEBUSY_ipd_1, TIEAPUCONTROL => TIEAPUCONTROL_ipd_1, TIEAPUUDI1 => TIEAPUUDI1_ipd_1, TIEAPUUDI2 => TIEAPUUDI2_ipd_1, TIEAPUUDI3 => TIEAPUUDI3_ipd_1, TIEAPUUDI4 => TIEAPUUDI4_ipd_1, TIEAPUUDI5 => TIEAPUUDI5_ipd_1, TIEAPUUDI6 => TIEAPUUDI6_ipd_1, TIEAPUUDI7 => TIEAPUUDI7_ipd_1, TIEAPUUDI8 => TIEAPUUDI8_ipd_1 ); start_blk : fpga_startup_virtex4 port map ( bus_reset => FPGA_BUS_RESET, ghigh_b => FPGA_GHIGHB, gsr => FPGA_GSR, gwe => FPGA_GWE, shutdown => FPGA_SHUTDOWN, cclk => FPGA_CCLK, por => FPGA_POR); GSR_OR <= FPGA_GSR or GSR; FPGA_POR <= '0' after 1000 ps; FPGA_CCLK <= NOT(FPGA_CCLK) after 5000 ps; FPGA_BUS_RESET_delay <= FPGA_BUS_RESET after 10 ps ; GSR_delay <= GSR_OR after 10 ps; FPGA_GWE_delay <= FPGA_GWE after 10 ps; FPGA_GHIGHB_delay <= FPGA_GHIGHB after 10 ps; TIMING : process variable APUFCMDECODED_GlitchData : VitalGlitchDataType; variable APUFCMDECUDI0_GlitchData : VitalGlitchDataType; variable APUFCMDECUDI1_GlitchData : VitalGlitchDataType; variable APUFCMDECUDI2_GlitchData : VitalGlitchDataType; variable APUFCMDECUDIVALID_GlitchData : VitalGlitchDataType; variable APUFCMENDIAN_GlitchData : VitalGlitchDataType; variable APUFCMFLUSH_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION0_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION1_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION2_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION3_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION4_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION5_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION6_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION7_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION8_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION9_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION10_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION11_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION12_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION13_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION14_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION15_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION16_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION17_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION18_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION19_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION20_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION21_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION22_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION23_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION24_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION25_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION26_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION27_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION28_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION29_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION30_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION31_GlitchData : VitalGlitchDataType; variable APUFCMINSTRVALID_GlitchData : VitalGlitchDataType; variable APUFCMLOADBYTEEN0_GlitchData : VitalGlitchDataType; variable APUFCMLOADBYTEEN1_GlitchData : VitalGlitchDataType; variable APUFCMLOADBYTEEN2_GlitchData : VitalGlitchDataType; variable APUFCMLOADBYTEEN3_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA0_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA1_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA2_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA3_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA4_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA5_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA6_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA7_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA8_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA9_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA10_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA11_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA12_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA13_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA14_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA15_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA16_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA17_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA18_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA19_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA20_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA21_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA22_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA23_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA24_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA25_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA26_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA27_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA28_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA29_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA30_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA31_GlitchData : VitalGlitchDataType; variable APUFCMLOADDVALID_GlitchData : VitalGlitchDataType; variable APUFCMOPERANDVALID_GlitchData : VitalGlitchDataType; variable APUFCMRADATA0_GlitchData : VitalGlitchDataType; variable APUFCMRADATA1_GlitchData : VitalGlitchDataType; variable APUFCMRADATA2_GlitchData : VitalGlitchDataType; variable APUFCMRADATA3_GlitchData : VitalGlitchDataType; variable APUFCMRADATA4_GlitchData : VitalGlitchDataType; variable APUFCMRADATA5_GlitchData : VitalGlitchDataType; variable APUFCMRADATA6_GlitchData : VitalGlitchDataType; variable APUFCMRADATA7_GlitchData : VitalGlitchDataType; variable APUFCMRADATA8_GlitchData : VitalGlitchDataType; variable APUFCMRADATA9_GlitchData : VitalGlitchDataType; variable APUFCMRADATA10_GlitchData : VitalGlitchDataType; variable APUFCMRADATA11_GlitchData : VitalGlitchDataType; variable APUFCMRADATA12_GlitchData : VitalGlitchDataType; variable APUFCMRADATA13_GlitchData : VitalGlitchDataType; variable APUFCMRADATA14_GlitchData : VitalGlitchDataType; variable APUFCMRADATA15_GlitchData : VitalGlitchDataType; variable APUFCMRADATA16_GlitchData : VitalGlitchDataType; variable APUFCMRADATA17_GlitchData : VitalGlitchDataType; variable APUFCMRADATA18_GlitchData : VitalGlitchDataType; variable APUFCMRADATA19_GlitchData : VitalGlitchDataType; variable APUFCMRADATA20_GlitchData : VitalGlitchDataType; variable APUFCMRADATA21_GlitchData : VitalGlitchDataType; variable APUFCMRADATA22_GlitchData : VitalGlitchDataType; variable APUFCMRADATA23_GlitchData : VitalGlitchDataType; variable APUFCMRADATA24_GlitchData : VitalGlitchDataType; variable APUFCMRADATA25_GlitchData : VitalGlitchDataType; variable APUFCMRADATA26_GlitchData : VitalGlitchDataType; variable APUFCMRADATA27_GlitchData : VitalGlitchDataType; variable APUFCMRADATA28_GlitchData : VitalGlitchDataType; variable APUFCMRADATA29_GlitchData : VitalGlitchDataType; variable APUFCMRADATA30_GlitchData : VitalGlitchDataType; variable APUFCMRADATA31_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA0_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA1_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA2_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA3_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA4_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA5_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA6_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA7_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA8_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA9_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA10_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA11_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA12_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA13_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA14_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA15_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA16_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA17_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA18_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA19_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA20_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA21_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA22_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA23_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA24_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA25_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA26_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA27_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA28_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA29_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA30_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA31_GlitchData : VitalGlitchDataType; variable APUFCMWRITEBACKOK_GlitchData : VitalGlitchDataType; variable APUFCMXERCA_GlitchData : VitalGlitchDataType; variable C405CPMCORESLEEPREQ_GlitchData : VitalGlitchDataType; variable C405CPMMSRCE_GlitchData : VitalGlitchDataType; variable C405CPMMSREE_GlitchData : VitalGlitchDataType; variable C405CPMTIMERIRQ_GlitchData : VitalGlitchDataType; variable C405CPMTIMERRESETREQ_GlitchData : VitalGlitchDataType; variable C405DBGLOADDATAONAPUDBUS_GlitchData : VitalGlitchDataType; variable C405DBGMSRWE_GlitchData : VitalGlitchDataType; variable C405DBGSTOPACK_GlitchData : VitalGlitchDataType; variable C405DBGWBCOMPLETE_GlitchData : VitalGlitchDataType; variable C405DBGWBFULL_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR0_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR1_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR2_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR3_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR4_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR5_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR6_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR7_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR8_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR9_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR10_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR11_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR12_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR13_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR14_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR15_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR16_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR17_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR18_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR19_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR20_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR21_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR22_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR23_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR24_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR25_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR26_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR27_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR28_GlitchData : VitalGlitchDataType; variable C405DBGWBIAR29_GlitchData : VitalGlitchDataType; variable C405JTGCAPTUREDR_GlitchData : VitalGlitchDataType; variable C405JTGEXTEST_GlitchData : VitalGlitchDataType; variable C405JTGPGMOUT_GlitchData : VitalGlitchDataType; variable C405JTGSHIFTDR_GlitchData : VitalGlitchDataType; variable C405JTGTDO_GlitchData : VitalGlitchDataType; variable C405JTGTDOEN_GlitchData : VitalGlitchDataType; variable C405JTGUPDATEDR_GlitchData : VitalGlitchDataType; variable C405PLBDCUABORT_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS0_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS1_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS2_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS3_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS4_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS5_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS6_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS7_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS8_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS9_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS10_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS11_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS12_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS13_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS14_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS15_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS16_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS17_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS18_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS19_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS20_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS21_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS22_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS23_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS24_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS25_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS26_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS27_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS28_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS29_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS30_GlitchData : VitalGlitchDataType; variable C405PLBDCUABUS31_GlitchData : VitalGlitchDataType; variable C405PLBDCUBE0_GlitchData : VitalGlitchDataType; variable C405PLBDCUBE1_GlitchData : VitalGlitchDataType; variable C405PLBDCUBE2_GlitchData : VitalGlitchDataType; variable C405PLBDCUBE3_GlitchData : VitalGlitchDataType; variable C405PLBDCUBE4_GlitchData : VitalGlitchDataType; variable C405PLBDCUBE5_GlitchData : VitalGlitchDataType; variable C405PLBDCUBE6_GlitchData : VitalGlitchDataType; variable C405PLBDCUBE7_GlitchData : VitalGlitchDataType; variable C405PLBDCUCACHEABLE_GlitchData : VitalGlitchDataType; variable C405PLBDCUGUARDED_GlitchData : VitalGlitchDataType; variable C405PLBDCUPRIORITY0_GlitchData : VitalGlitchDataType; variable C405PLBDCUPRIORITY1_GlitchData : VitalGlitchDataType; variable C405PLBDCUREQUEST_GlitchData : VitalGlitchDataType; variable C405PLBDCURNW_GlitchData : VitalGlitchDataType; variable C405PLBDCUSIZE2_GlitchData : VitalGlitchDataType; variable C405PLBDCUU0ATTR_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS0_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS1_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS2_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS3_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS4_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS5_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS6_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS7_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS8_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS9_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS10_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS11_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS12_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS13_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS14_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS15_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS16_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS17_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS18_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS19_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS20_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS21_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS22_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS23_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS24_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS25_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS26_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS27_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS28_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS29_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS30_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS31_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS32_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS33_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS34_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS35_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS36_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS37_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS38_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS39_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS40_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS41_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS42_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS43_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS44_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS45_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS46_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS47_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS48_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS49_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS50_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS51_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS52_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS53_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS54_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS55_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS56_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS57_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS58_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS59_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS60_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS61_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS62_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRDBUS63_GlitchData : VitalGlitchDataType; variable C405PLBDCUWRITETHRU_GlitchData : VitalGlitchDataType; variable C405PLBICUABORT_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS0_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS1_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS2_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS3_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS4_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS5_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS6_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS7_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS8_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS9_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS10_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS11_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS12_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS13_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS14_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS15_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS16_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS17_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS18_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS19_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS20_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS21_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS22_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS23_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS24_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS25_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS26_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS27_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS28_GlitchData : VitalGlitchDataType; variable C405PLBICUABUS29_GlitchData : VitalGlitchDataType; variable C405PLBICUCACHEABLE_GlitchData : VitalGlitchDataType; variable C405PLBICUPRIORITY0_GlitchData : VitalGlitchDataType; variable C405PLBICUPRIORITY1_GlitchData : VitalGlitchDataType; variable C405PLBICUREQUEST_GlitchData : VitalGlitchDataType; variable C405PLBICUSIZE2_GlitchData : VitalGlitchDataType; variable C405PLBICUSIZE3_GlitchData : VitalGlitchDataType; variable C405PLBICUU0ATTR_GlitchData : VitalGlitchDataType; variable C405RSTCHIPRESETREQ_GlitchData : VitalGlitchDataType; variable C405RSTCORERESETREQ_GlitchData : VitalGlitchDataType; variable C405RSTSYSRESETREQ_GlitchData : VitalGlitchDataType; variable C405TRCCYCLE_GlitchData : VitalGlitchDataType; variable C405TRCEVENEXECUTIONSTATUS0_GlitchData : VitalGlitchDataType; variable C405TRCEVENEXECUTIONSTATUS1_GlitchData : VitalGlitchDataType; variable C405TRCODDEXECUTIONSTATUS0_GlitchData : VitalGlitchDataType; variable C405TRCODDEXECUTIONSTATUS1_GlitchData : VitalGlitchDataType; variable C405TRCTRACESTATUS0_GlitchData : VitalGlitchDataType; variable C405TRCTRACESTATUS1_GlitchData : VitalGlitchDataType; variable C405TRCTRACESTATUS2_GlitchData : VitalGlitchDataType; variable C405TRCTRACESTATUS3_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTOUT_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTTYPE0_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTTYPE1_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTTYPE2_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTTYPE3_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTTYPE4_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTTYPE5_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTTYPE6_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTTYPE7_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTTYPE8_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTTYPE9_GlitchData : VitalGlitchDataType; variable C405TRCTRIGGEREVENTTYPE10_GlitchData : VitalGlitchDataType; variable C405XXXMACHINECHECK_GlitchData : VitalGlitchDataType; variable DCREMACENABLER_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS8_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS9_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS10_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS11_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS12_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS13_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS14_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS15_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS16_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS17_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS18_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS19_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS20_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS21_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS22_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS23_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS24_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS25_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS26_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS27_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS28_GlitchData : VitalGlitchDataType; variable DSOCMBRAMABUS29_GlitchData : VitalGlitchDataType; variable DSOCMBRAMBYTEWRITE0_GlitchData : VitalGlitchDataType; variable DSOCMBRAMBYTEWRITE1_GlitchData : VitalGlitchDataType; variable DSOCMBRAMBYTEWRITE2_GlitchData : VitalGlitchDataType; variable DSOCMBRAMBYTEWRITE3_GlitchData : VitalGlitchDataType; variable DSOCMBRAMEN_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS0_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS1_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS2_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS3_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS4_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS5_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS6_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS7_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS8_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS9_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS10_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS11_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS12_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS13_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS14_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS15_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS16_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS17_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS18_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS19_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS20_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS21_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS22_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS23_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS24_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS25_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS26_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS27_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS28_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS29_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS30_GlitchData : VitalGlitchDataType; variable DSOCMBRAMWRDBUS31_GlitchData : VitalGlitchDataType; variable DSOCMBUSY_GlitchData : VitalGlitchDataType; variable DSOCMRDADDRVALID_GlitchData : VitalGlitchDataType; variable DSOCMWRADDRVALID_GlitchData : VitalGlitchDataType; variable EXTDCRABUS0_GlitchData : VitalGlitchDataType; variable EXTDCRABUS1_GlitchData : VitalGlitchDataType; variable EXTDCRABUS2_GlitchData : VitalGlitchDataType; variable EXTDCRABUS3_GlitchData : VitalGlitchDataType; variable EXTDCRABUS4_GlitchData : VitalGlitchDataType; variable EXTDCRABUS5_GlitchData : VitalGlitchDataType; variable EXTDCRABUS6_GlitchData : VitalGlitchDataType; variable EXTDCRABUS7_GlitchData : VitalGlitchDataType; variable EXTDCRABUS8_GlitchData : VitalGlitchDataType; variable EXTDCRABUS9_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT0_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT1_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT2_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT3_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT4_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT5_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT6_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT7_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT8_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT9_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT10_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT11_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT12_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT13_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT14_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT15_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT16_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT17_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT18_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT19_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT20_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT21_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT22_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT23_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT24_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT25_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT26_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT27_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT28_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT29_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT30_GlitchData : VitalGlitchDataType; variable EXTDCRDBUSOUT31_GlitchData : VitalGlitchDataType; variable EXTDCRREAD_GlitchData : VitalGlitchDataType; variable EXTDCRWRITE_GlitchData : VitalGlitchDataType; variable ISOCMBRAMEN_GlitchData : VitalGlitchDataType; variable ISOCMBRAMEVENWRITEEN_GlitchData : VitalGlitchDataType; variable ISOCMBRAMODDWRITEEN_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS8_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS9_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS10_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS11_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS12_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS13_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS14_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS15_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS16_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS17_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS18_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS19_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS20_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS21_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS22_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS23_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS24_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS25_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS26_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS27_GlitchData : VitalGlitchDataType; variable ISOCMBRAMRDABUS28_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS8_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS9_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS10_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS11_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS12_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS13_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS14_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS15_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS16_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS17_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS18_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS19_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS20_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS21_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS22_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS23_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS24_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS25_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS26_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS27_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRABUS28_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS0_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS1_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS2_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS3_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS4_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS5_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS6_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS7_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS8_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS9_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS10_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS11_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS12_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS13_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS14_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS15_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS16_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS17_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS18_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS19_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS20_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS21_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS22_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS23_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS24_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS25_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS26_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS27_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS28_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS29_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS30_GlitchData : VitalGlitchDataType; variable ISOCMBRAMWRDBUS31_GlitchData : VitalGlitchDataType; variable ISOCMDCRBRAMEVENEN_GlitchData : VitalGlitchDataType; variable ISOCMDCRBRAMODDEN_GlitchData : VitalGlitchDataType; variable ISOCMDCRBRAMRDSELECT_GlitchData : VitalGlitchDataType; variable DCREMACWRITE_GlitchData : VitalGlitchDataType; variable DCREMACREAD_GlitchData : VitalGlitchDataType; variable DCREMACDBUS0_GlitchData : VitalGlitchDataType; variable DCREMACDBUS1_GlitchData : VitalGlitchDataType; variable DCREMACDBUS2_GlitchData : VitalGlitchDataType; variable DCREMACDBUS3_GlitchData : VitalGlitchDataType; variable DCREMACDBUS4_GlitchData : VitalGlitchDataType; variable DCREMACDBUS5_GlitchData : VitalGlitchDataType; variable DCREMACDBUS6_GlitchData : VitalGlitchDataType; variable DCREMACDBUS7_GlitchData : VitalGlitchDataType; variable DCREMACDBUS8_GlitchData : VitalGlitchDataType; variable DCREMACDBUS9_GlitchData : VitalGlitchDataType; variable DCREMACDBUS10_GlitchData : VitalGlitchDataType; variable DCREMACDBUS11_GlitchData : VitalGlitchDataType; variable DCREMACDBUS12_GlitchData : VitalGlitchDataType; variable DCREMACDBUS13_GlitchData : VitalGlitchDataType; variable DCREMACDBUS14_GlitchData : VitalGlitchDataType; variable DCREMACDBUS15_GlitchData : VitalGlitchDataType; variable DCREMACDBUS16_GlitchData : VitalGlitchDataType; variable DCREMACDBUS17_GlitchData : VitalGlitchDataType; variable DCREMACDBUS18_GlitchData : VitalGlitchDataType; variable DCREMACDBUS19_GlitchData : VitalGlitchDataType; variable DCREMACDBUS20_GlitchData : VitalGlitchDataType; variable DCREMACDBUS21_GlitchData : VitalGlitchDataType; variable DCREMACDBUS22_GlitchData : VitalGlitchDataType; variable DCREMACDBUS23_GlitchData : VitalGlitchDataType; variable DCREMACDBUS24_GlitchData : VitalGlitchDataType; variable DCREMACDBUS25_GlitchData : VitalGlitchDataType; variable DCREMACDBUS26_GlitchData : VitalGlitchDataType; variable DCREMACDBUS27_GlitchData : VitalGlitchDataType; variable DCREMACDBUS28_GlitchData : VitalGlitchDataType; variable DCREMACDBUS29_GlitchData : VitalGlitchDataType; variable DCREMACDBUS30_GlitchData : VitalGlitchDataType; variable DCREMACDBUS31_GlitchData : VitalGlitchDataType; variable DCREMACABUS8_GlitchData : VitalGlitchDataType; variable DCREMACABUS9_GlitchData : VitalGlitchDataType; variable DCREMACCLK_GlitchData : VitalGlitchDataType; begin -- Output-to-Clock path delay VitalPathDelay01 ( OutSignal => APUFCMDECODED, GlitchData => APUFCMDECODED_GlitchData, OutSignalName => "APUFCMDECODED", OutTemp => APUFCMDECODED_OUT, Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECUDIVALID, GlitchData => APUFCMDECUDIVALID_GlitchData, OutSignalName => "APUFCMDECUDIVALID", OutTemp => APUFCMDECUDIVALID_OUT, Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMENDIAN, GlitchData => APUFCMENDIAN_GlitchData, OutSignalName => "APUFCMENDIAN", OutTemp => APUFCMENDIAN_OUT, Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMFLUSH, GlitchData => APUFCMFLUSH_GlitchData, OutSignalName => "APUFCMFLUSH", OutTemp => APUFCMFLUSH_OUT, Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRVALID, GlitchData => APUFCMINSTRVALID_GlitchData, OutSignalName => "APUFCMINSTRVALID", OutTemp => APUFCMINSTRVALID_OUT, Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDVALID, GlitchData => APUFCMLOADDVALID_GlitchData, OutSignalName => "APUFCMLOADDVALID", OutTemp => APUFCMLOADDVALID_OUT, Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMOPERANDVALID, GlitchData => APUFCMOPERANDVALID_GlitchData, OutSignalName => "APUFCMOPERANDVALID", OutTemp => APUFCMOPERANDVALID_OUT, Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMWRITEBACKOK, GlitchData => APUFCMWRITEBACKOK_GlitchData, OutSignalName => "APUFCMWRITEBACKOK", OutTemp => APUFCMWRITEBACKOK_OUT, Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMXERCA, GlitchData => APUFCMXERCA_GlitchData, OutSignalName => "APUFCMXERCA", OutTemp => APUFCMXERCA_OUT, Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405CPMCORESLEEPREQ, GlitchData => C405CPMCORESLEEPREQ_GlitchData, OutSignalName => "C405CPMCORESLEEPREQ", OutTemp => C405CPMCORESLEEPREQ_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405CPMMSRCE, GlitchData => C405CPMMSRCE_GlitchData, OutSignalName => "C405CPMMSRCE", OutTemp => C405CPMMSRCE_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405CPMMSREE, GlitchData => C405CPMMSREE_GlitchData, OutSignalName => "C405CPMMSREE", OutTemp => C405CPMMSREE_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405CPMTIMERIRQ, GlitchData => C405CPMTIMERIRQ_GlitchData, OutSignalName => "C405CPMTIMERIRQ", OutTemp => C405CPMTIMERIRQ_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405CPMTIMERRESETREQ, GlitchData => C405CPMTIMERRESETREQ_GlitchData, OutSignalName => "C405CPMTIMERRESETREQ", OutTemp => C405CPMTIMERRESETREQ_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGLOADDATAONAPUDBUS, GlitchData => C405DBGLOADDATAONAPUDBUS_GlitchData, OutSignalName => "C405DBGLOADDATAONAPUDBUS", OutTemp => C405DBGLOADDATAONAPUDBUS_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGMSRWE, GlitchData => C405DBGMSRWE_GlitchData, OutSignalName => "C405DBGMSRWE", OutTemp => C405DBGMSRWE_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGSTOPACK, GlitchData => C405DBGSTOPACK_GlitchData, OutSignalName => "C405DBGSTOPACK", OutTemp => C405DBGSTOPACK_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBCOMPLETE, GlitchData => C405DBGWBCOMPLETE_GlitchData, OutSignalName => "C405DBGWBCOMPLETE", OutTemp => C405DBGWBCOMPLETE_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBFULL, GlitchData => C405DBGWBFULL_GlitchData, OutSignalName => "C405DBGWBFULL", OutTemp => C405DBGWBFULL_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405JTGCAPTUREDR, GlitchData => C405JTGCAPTUREDR_GlitchData, OutSignalName => "C405JTGCAPTUREDR", OutTemp => C405JTGCAPTUREDR_OUT, Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405JTGEXTEST, GlitchData => C405JTGEXTEST_GlitchData, OutSignalName => "C405JTGEXTEST", OutTemp => C405JTGEXTEST_OUT, Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405JTGPGMOUT, GlitchData => C405JTGPGMOUT_GlitchData, OutSignalName => "C405JTGPGMOUT", OutTemp => C405JTGPGMOUT_OUT, Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405JTGSHIFTDR, GlitchData => C405JTGSHIFTDR_GlitchData, OutSignalName => "C405JTGSHIFTDR", OutTemp => C405JTGSHIFTDR_OUT, Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405JTGTDO, GlitchData => C405JTGTDO_GlitchData, OutSignalName => "C405JTGTDO", OutTemp => C405JTGTDO_OUT, Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405JTGTDOEN, GlitchData => C405JTGTDOEN_GlitchData, OutSignalName => "C405JTGTDOEN", OutTemp => C405JTGTDOEN_OUT, Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405JTGUPDATEDR, GlitchData => C405JTGUPDATEDR_GlitchData, OutSignalName => "C405JTGUPDATEDR", OutTemp => C405JTGUPDATEDR_OUT, Paths => (0 => (JTGC405TCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABORT, GlitchData => C405PLBDCUABORT_GlitchData, OutSignalName => "C405PLBDCUABORT", OutTemp => C405PLBDCUABORT_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUCACHEABLE, GlitchData => C405PLBDCUCACHEABLE_GlitchData, OutSignalName => "C405PLBDCUCACHEABLE", OutTemp => C405PLBDCUCACHEABLE_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUGUARDED, GlitchData => C405PLBDCUGUARDED_GlitchData, OutSignalName => "C405PLBDCUGUARDED", OutTemp => C405PLBDCUGUARDED_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUREQUEST, GlitchData => C405PLBDCUREQUEST_GlitchData, OutSignalName => "C405PLBDCUREQUEST", OutTemp => C405PLBDCUREQUEST_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCURNW, GlitchData => C405PLBDCURNW_GlitchData, OutSignalName => "C405PLBDCURNW", OutTemp => C405PLBDCURNW_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUSIZE2, GlitchData => C405PLBDCUSIZE2_GlitchData, OutSignalName => "C405PLBDCUSIZE2", OutTemp => C405PLBDCUSIZE2_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUU0ATTR, GlitchData => C405PLBDCUU0ATTR_GlitchData, OutSignalName => "C405PLBDCUU0ATTR", OutTemp => C405PLBDCUU0ATTR_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRITETHRU, GlitchData => C405PLBDCUWRITETHRU_GlitchData, OutSignalName => "C405PLBDCUWRITETHRU", OutTemp => C405PLBDCUWRITETHRU_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABORT, GlitchData => C405PLBICUABORT_GlitchData, OutSignalName => "C405PLBICUABORT", OutTemp => C405PLBICUABORT_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUCACHEABLE, GlitchData => C405PLBICUCACHEABLE_GlitchData, OutSignalName => "C405PLBICUCACHEABLE", OutTemp => C405PLBICUCACHEABLE_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUREQUEST, GlitchData => C405PLBICUREQUEST_GlitchData, OutSignalName => "C405PLBICUREQUEST", OutTemp => C405PLBICUREQUEST_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUU0ATTR, GlitchData => C405PLBICUU0ATTR_GlitchData, OutSignalName => "C405PLBICUU0ATTR", OutTemp => C405PLBICUU0ATTR_OUT, Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405RSTCHIPRESETREQ, GlitchData => C405RSTCHIPRESETREQ_GlitchData, OutSignalName => "C405RSTCHIPRESETREQ", OutTemp => C405RSTCHIPRESETREQ_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405RSTCORERESETREQ, GlitchData => C405RSTCORERESETREQ_GlitchData, OutSignalName => "C405RSTCORERESETREQ", OutTemp => C405RSTCORERESETREQ_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405RSTSYSRESETREQ, GlitchData => C405RSTSYSRESETREQ_GlitchData, OutSignalName => "C405RSTSYSRESETREQ", OutTemp => C405RSTSYSRESETREQ_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCCYCLE, GlitchData => C405TRCCYCLE_GlitchData, OutSignalName => "C405TRCCYCLE", OutTemp => C405TRCCYCLE_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTOUT, GlitchData => C405TRCTRIGGEREVENTOUT_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTOUT", OutTemp => C405TRCTRIGGEREVENTOUT_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405XXXMACHINECHECK, GlitchData => C405XXXMACHINECHECK_GlitchData, OutSignalName => "C405XXXMACHINECHECK", OutTemp => C405XXXMACHINECHECK_OUT, Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMEN, GlitchData => DSOCMBRAMEN_GlitchData, OutSignalName => "DSOCMBRAMEN", OutTemp => DSOCMBRAMEN_OUT, Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBUSY, GlitchData => DSOCMBUSY_GlitchData, OutSignalName => "DSOCMBUSY", OutTemp => DSOCMBUSY_OUT, Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMRDADDRVALID, GlitchData => DSOCMRDADDRVALID_GlitchData, OutSignalName => "DSOCMRDADDRVALID", OutTemp => DSOCMRDADDRVALID_OUT, Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMWRADDRVALID, GlitchData => DSOCMWRADDRVALID_GlitchData, OutSignalName => "DSOCMWRADDRVALID", OutTemp => DSOCMWRADDRVALID_OUT, Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRREAD, GlitchData => EXTDCRREAD_GlitchData, OutSignalName => "EXTDCRREAD", OutTemp => EXTDCRREAD_OUT, Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRWRITE, GlitchData => EXTDCRWRITE_GlitchData, OutSignalName => "EXTDCRWRITE", OutTemp => EXTDCRWRITE_OUT, Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMEN, GlitchData => ISOCMBRAMEN_GlitchData, OutSignalName => "ISOCMBRAMEN", OutTemp => ISOCMBRAMEN_OUT, Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMEVENWRITEEN, GlitchData => ISOCMBRAMEVENWRITEEN_GlitchData, OutSignalName => "ISOCMBRAMEVENWRITEEN", OutTemp => ISOCMBRAMEVENWRITEEN_OUT, Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMODDWRITEEN, GlitchData => ISOCMBRAMODDWRITEEN_GlitchData, OutSignalName => "ISOCMBRAMODDWRITEEN", OutTemp => ISOCMBRAMODDWRITEEN_OUT, Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMDCRBRAMEVENEN, GlitchData => ISOCMDCRBRAMEVENEN_GlitchData, OutSignalName => "ISOCMDCRBRAMEVENEN", OutTemp => ISOCMDCRBRAMEVENEN_OUT, Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMDCRBRAMODDEN, GlitchData => ISOCMDCRBRAMODDEN_GlitchData, OutSignalName => "ISOCMDCRBRAMODDEN", OutTemp => ISOCMDCRBRAMODDEN_OUT, Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMDCRBRAMRDSELECT, GlitchData => ISOCMDCRBRAMRDSELECT_GlitchData, OutSignalName => "ISOCMDCRBRAMRDSELECT", OutTemp => ISOCMDCRBRAMRDSELECT_OUT, Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); ----- bused outputs VitalPathDelay01 ( OutSignal => APUFCMDECUDI(0), GlitchData => APUFCMDECUDI0_GlitchData, OutSignalName => "APUFCMDECUDI(0)", OutTemp => APUFCMDECUDI_OUT(0), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECUDI(1), GlitchData => APUFCMDECUDI1_GlitchData, OutSignalName => "APUFCMDECUDI(1)", OutTemp => APUFCMDECUDI_OUT(1), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECUDI(2), GlitchData => APUFCMDECUDI2_GlitchData, OutSignalName => "APUFCMDECUDI(2)", OutTemp => APUFCMDECUDI_OUT(2), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(0), GlitchData => APUFCMINSTRUCTION0_GlitchData, OutSignalName => "APUFCMINSTRUCTION(0)", OutTemp => APUFCMINSTRUCTION_OUT(0), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(1), GlitchData => APUFCMINSTRUCTION1_GlitchData, OutSignalName => "APUFCMINSTRUCTION(1)", OutTemp => APUFCMINSTRUCTION_OUT(1), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(2), GlitchData => APUFCMINSTRUCTION2_GlitchData, OutSignalName => "APUFCMINSTRUCTION(2)", OutTemp => APUFCMINSTRUCTION_OUT(2), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(3), GlitchData => APUFCMINSTRUCTION3_GlitchData, OutSignalName => "APUFCMINSTRUCTION(3)", OutTemp => APUFCMINSTRUCTION_OUT(3), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(4), GlitchData => APUFCMINSTRUCTION4_GlitchData, OutSignalName => "APUFCMINSTRUCTION(4)", OutTemp => APUFCMINSTRUCTION_OUT(4), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(5), GlitchData => APUFCMINSTRUCTION5_GlitchData, OutSignalName => "APUFCMINSTRUCTION(5)", OutTemp => APUFCMINSTRUCTION_OUT(5), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(6), GlitchData => APUFCMINSTRUCTION6_GlitchData, OutSignalName => "APUFCMINSTRUCTION(6)", OutTemp => APUFCMINSTRUCTION_OUT(6), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(7), GlitchData => APUFCMINSTRUCTION7_GlitchData, OutSignalName => "APUFCMINSTRUCTION(7)", OutTemp => APUFCMINSTRUCTION_OUT(7), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(8), GlitchData => APUFCMINSTRUCTION8_GlitchData, OutSignalName => "APUFCMINSTRUCTION(8)", OutTemp => APUFCMINSTRUCTION_OUT(8), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(9), GlitchData => APUFCMINSTRUCTION9_GlitchData, OutSignalName => "APUFCMINSTRUCTION(9)", OutTemp => APUFCMINSTRUCTION_OUT(9), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(10), GlitchData => APUFCMINSTRUCTION10_GlitchData, OutSignalName => "APUFCMINSTRUCTION(10)", OutTemp => APUFCMINSTRUCTION_OUT(10), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(11), GlitchData => APUFCMINSTRUCTION11_GlitchData, OutSignalName => "APUFCMINSTRUCTION(11)", OutTemp => APUFCMINSTRUCTION_OUT(11), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(12), GlitchData => APUFCMINSTRUCTION12_GlitchData, OutSignalName => "APUFCMINSTRUCTION(12)", OutTemp => APUFCMINSTRUCTION_OUT(12), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(13), GlitchData => APUFCMINSTRUCTION13_GlitchData, OutSignalName => "APUFCMINSTRUCTION(13)", OutTemp => APUFCMINSTRUCTION_OUT(13), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(14), GlitchData => APUFCMINSTRUCTION14_GlitchData, OutSignalName => "APUFCMINSTRUCTION(14)", OutTemp => APUFCMINSTRUCTION_OUT(14), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(15), GlitchData => APUFCMINSTRUCTION15_GlitchData, OutSignalName => "APUFCMINSTRUCTION(15)", OutTemp => APUFCMINSTRUCTION_OUT(15), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(16), GlitchData => APUFCMINSTRUCTION16_GlitchData, OutSignalName => "APUFCMINSTRUCTION(16)", OutTemp => APUFCMINSTRUCTION_OUT(16), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(17), GlitchData => APUFCMINSTRUCTION17_GlitchData, OutSignalName => "APUFCMINSTRUCTION(17)", OutTemp => APUFCMINSTRUCTION_OUT(17), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(18), GlitchData => APUFCMINSTRUCTION18_GlitchData, OutSignalName => "APUFCMINSTRUCTION(18)", OutTemp => APUFCMINSTRUCTION_OUT(18), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(19), GlitchData => APUFCMINSTRUCTION19_GlitchData, OutSignalName => "APUFCMINSTRUCTION(19)", OutTemp => APUFCMINSTRUCTION_OUT(19), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(20), GlitchData => APUFCMINSTRUCTION20_GlitchData, OutSignalName => "APUFCMINSTRUCTION(20)", OutTemp => APUFCMINSTRUCTION_OUT(20), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(21), GlitchData => APUFCMINSTRUCTION21_GlitchData, OutSignalName => "APUFCMINSTRUCTION(21)", OutTemp => APUFCMINSTRUCTION_OUT(21), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(22), GlitchData => APUFCMINSTRUCTION22_GlitchData, OutSignalName => "APUFCMINSTRUCTION(22)", OutTemp => APUFCMINSTRUCTION_OUT(22), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(23), GlitchData => APUFCMINSTRUCTION23_GlitchData, OutSignalName => "APUFCMINSTRUCTION(23)", OutTemp => APUFCMINSTRUCTION_OUT(23), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(24), GlitchData => APUFCMINSTRUCTION24_GlitchData, OutSignalName => "APUFCMINSTRUCTION(24)", OutTemp => APUFCMINSTRUCTION_OUT(24), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(25), GlitchData => APUFCMINSTRUCTION25_GlitchData, OutSignalName => "APUFCMINSTRUCTION(25)", OutTemp => APUFCMINSTRUCTION_OUT(25), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(26), GlitchData => APUFCMINSTRUCTION26_GlitchData, OutSignalName => "APUFCMINSTRUCTION(26)", OutTemp => APUFCMINSTRUCTION_OUT(26), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(27), GlitchData => APUFCMINSTRUCTION27_GlitchData, OutSignalName => "APUFCMINSTRUCTION(27)", OutTemp => APUFCMINSTRUCTION_OUT(27), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(28), GlitchData => APUFCMINSTRUCTION28_GlitchData, OutSignalName => "APUFCMINSTRUCTION(28)", OutTemp => APUFCMINSTRUCTION_OUT(28), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(29), GlitchData => APUFCMINSTRUCTION29_GlitchData, OutSignalName => "APUFCMINSTRUCTION(29)", OutTemp => APUFCMINSTRUCTION_OUT(29), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(30), GlitchData => APUFCMINSTRUCTION30_GlitchData, OutSignalName => "APUFCMINSTRUCTION(30)", OutTemp => APUFCMINSTRUCTION_OUT(30), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(31), GlitchData => APUFCMINSTRUCTION31_GlitchData, OutSignalName => "APUFCMINSTRUCTION(31)", OutTemp => APUFCMINSTRUCTION_OUT(31), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADBYTEEN(0), GlitchData => APUFCMLOADBYTEEN0_GlitchData, OutSignalName => "APUFCMLOADBYTEEN(0)", OutTemp => APUFCMLOADBYTEEN_OUT(0), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADBYTEEN(1), GlitchData => APUFCMLOADBYTEEN1_GlitchData, OutSignalName => "APUFCMLOADBYTEEN(1)", OutTemp => APUFCMLOADBYTEEN_OUT(1), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADBYTEEN(2), GlitchData => APUFCMLOADBYTEEN2_GlitchData, OutSignalName => "APUFCMLOADBYTEEN(2)", OutTemp => APUFCMLOADBYTEEN_OUT(2), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADBYTEEN(3), GlitchData => APUFCMLOADBYTEEN3_GlitchData, OutSignalName => "APUFCMLOADBYTEEN(3)", OutTemp => APUFCMLOADBYTEEN_OUT(3), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(0), GlitchData => APUFCMLOADDATA0_GlitchData, OutSignalName => "APUFCMLOADDATA(0)", OutTemp => APUFCMLOADDATA_OUT(0), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(1), GlitchData => APUFCMLOADDATA1_GlitchData, OutSignalName => "APUFCMLOADDATA(1)", OutTemp => APUFCMLOADDATA_OUT(1), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(2), GlitchData => APUFCMLOADDATA2_GlitchData, OutSignalName => "APUFCMLOADDATA(2)", OutTemp => APUFCMLOADDATA_OUT(2), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(3), GlitchData => APUFCMLOADDATA3_GlitchData, OutSignalName => "APUFCMLOADDATA(3)", OutTemp => APUFCMLOADDATA_OUT(3), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(4), GlitchData => APUFCMLOADDATA4_GlitchData, OutSignalName => "APUFCMLOADDATA(4)", OutTemp => APUFCMLOADDATA_OUT(4), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(5), GlitchData => APUFCMLOADDATA5_GlitchData, OutSignalName => "APUFCMLOADDATA(5)", OutTemp => APUFCMLOADDATA_OUT(5), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(6), GlitchData => APUFCMLOADDATA6_GlitchData, OutSignalName => "APUFCMLOADDATA(6)", OutTemp => APUFCMLOADDATA_OUT(6), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(7), GlitchData => APUFCMLOADDATA7_GlitchData, OutSignalName => "APUFCMLOADDATA(7)", OutTemp => APUFCMLOADDATA_OUT(7), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(8), GlitchData => APUFCMLOADDATA8_GlitchData, OutSignalName => "APUFCMLOADDATA(8)", OutTemp => APUFCMLOADDATA_OUT(8), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(9), GlitchData => APUFCMLOADDATA9_GlitchData, OutSignalName => "APUFCMLOADDATA(9)", OutTemp => APUFCMLOADDATA_OUT(9), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(10), GlitchData => APUFCMLOADDATA10_GlitchData, OutSignalName => "APUFCMLOADDATA(10)", OutTemp => APUFCMLOADDATA_OUT(10), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(11), GlitchData => APUFCMLOADDATA11_GlitchData, OutSignalName => "APUFCMLOADDATA(11)", OutTemp => APUFCMLOADDATA_OUT(11), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(12), GlitchData => APUFCMLOADDATA12_GlitchData, OutSignalName => "APUFCMLOADDATA(12)", OutTemp => APUFCMLOADDATA_OUT(12), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(13), GlitchData => APUFCMLOADDATA13_GlitchData, OutSignalName => "APUFCMLOADDATA(13)", OutTemp => APUFCMLOADDATA_OUT(13), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(14), GlitchData => APUFCMLOADDATA14_GlitchData, OutSignalName => "APUFCMLOADDATA(14)", OutTemp => APUFCMLOADDATA_OUT(14), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(15), GlitchData => APUFCMLOADDATA15_GlitchData, OutSignalName => "APUFCMLOADDATA(15)", OutTemp => APUFCMLOADDATA_OUT(15), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(16), GlitchData => APUFCMLOADDATA16_GlitchData, OutSignalName => "APUFCMLOADDATA(16)", OutTemp => APUFCMLOADDATA_OUT(16), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(17), GlitchData => APUFCMLOADDATA17_GlitchData, OutSignalName => "APUFCMLOADDATA(17)", OutTemp => APUFCMLOADDATA_OUT(17), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(18), GlitchData => APUFCMLOADDATA18_GlitchData, OutSignalName => "APUFCMLOADDATA(18)", OutTemp => APUFCMLOADDATA_OUT(18), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(19), GlitchData => APUFCMLOADDATA19_GlitchData, OutSignalName => "APUFCMLOADDATA(19)", OutTemp => APUFCMLOADDATA_OUT(19), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(20), GlitchData => APUFCMLOADDATA20_GlitchData, OutSignalName => "APUFCMLOADDATA(20)", OutTemp => APUFCMLOADDATA_OUT(20), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(21), GlitchData => APUFCMLOADDATA21_GlitchData, OutSignalName => "APUFCMLOADDATA(21)", OutTemp => APUFCMLOADDATA_OUT(21), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(22), GlitchData => APUFCMLOADDATA22_GlitchData, OutSignalName => "APUFCMLOADDATA(22)", OutTemp => APUFCMLOADDATA_OUT(22), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(23), GlitchData => APUFCMLOADDATA23_GlitchData, OutSignalName => "APUFCMLOADDATA(23)", OutTemp => APUFCMLOADDATA_OUT(23), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(24), GlitchData => APUFCMLOADDATA24_GlitchData, OutSignalName => "APUFCMLOADDATA(24)", OutTemp => APUFCMLOADDATA_OUT(24), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(25), GlitchData => APUFCMLOADDATA25_GlitchData, OutSignalName => "APUFCMLOADDATA(25)", OutTemp => APUFCMLOADDATA_OUT(25), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(26), GlitchData => APUFCMLOADDATA26_GlitchData, OutSignalName => "APUFCMLOADDATA(26)", OutTemp => APUFCMLOADDATA_OUT(26), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(27), GlitchData => APUFCMLOADDATA27_GlitchData, OutSignalName => "APUFCMLOADDATA(27)", OutTemp => APUFCMLOADDATA_OUT(27), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(28), GlitchData => APUFCMLOADDATA28_GlitchData, OutSignalName => "APUFCMLOADDATA(28)", OutTemp => APUFCMLOADDATA_OUT(28), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(29), GlitchData => APUFCMLOADDATA29_GlitchData, OutSignalName => "APUFCMLOADDATA(29)", OutTemp => APUFCMLOADDATA_OUT(29), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(30), GlitchData => APUFCMLOADDATA30_GlitchData, OutSignalName => "APUFCMLOADDATA(30)", OutTemp => APUFCMLOADDATA_OUT(30), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(31), GlitchData => APUFCMLOADDATA31_GlitchData, OutSignalName => "APUFCMLOADDATA(31)", OutTemp => APUFCMLOADDATA_OUT(31), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(0), GlitchData => APUFCMRADATA0_GlitchData, OutSignalName => "APUFCMRADATA(0)", OutTemp => APUFCMRADATA_OUT(0), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(1), GlitchData => APUFCMRADATA1_GlitchData, OutSignalName => "APUFCMRADATA(1)", OutTemp => APUFCMRADATA_OUT(1), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(2), GlitchData => APUFCMRADATA2_GlitchData, OutSignalName => "APUFCMRADATA(2)", OutTemp => APUFCMRADATA_OUT(2), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(3), GlitchData => APUFCMRADATA3_GlitchData, OutSignalName => "APUFCMRADATA(3)", OutTemp => APUFCMRADATA_OUT(3), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(4), GlitchData => APUFCMRADATA4_GlitchData, OutSignalName => "APUFCMRADATA(4)", OutTemp => APUFCMRADATA_OUT(4), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(5), GlitchData => APUFCMRADATA5_GlitchData, OutSignalName => "APUFCMRADATA(5)", OutTemp => APUFCMRADATA_OUT(5), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(6), GlitchData => APUFCMRADATA6_GlitchData, OutSignalName => "APUFCMRADATA(6)", OutTemp => APUFCMRADATA_OUT(6), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(7), GlitchData => APUFCMRADATA7_GlitchData, OutSignalName => "APUFCMRADATA(7)", OutTemp => APUFCMRADATA_OUT(7), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(8), GlitchData => APUFCMRADATA8_GlitchData, OutSignalName => "APUFCMRADATA(8)", OutTemp => APUFCMRADATA_OUT(8), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(9), GlitchData => APUFCMRADATA9_GlitchData, OutSignalName => "APUFCMRADATA(9)", OutTemp => APUFCMRADATA_OUT(9), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(10), GlitchData => APUFCMRADATA10_GlitchData, OutSignalName => "APUFCMRADATA(10)", OutTemp => APUFCMRADATA_OUT(10), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(11), GlitchData => APUFCMRADATA11_GlitchData, OutSignalName => "APUFCMRADATA(11)", OutTemp => APUFCMRADATA_OUT(11), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(12), GlitchData => APUFCMRADATA12_GlitchData, OutSignalName => "APUFCMRADATA(12)", OutTemp => APUFCMRADATA_OUT(12), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(13), GlitchData => APUFCMRADATA13_GlitchData, OutSignalName => "APUFCMRADATA(13)", OutTemp => APUFCMRADATA_OUT(13), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(14), GlitchData => APUFCMRADATA14_GlitchData, OutSignalName => "APUFCMRADATA(14)", OutTemp => APUFCMRADATA_OUT(14), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(15), GlitchData => APUFCMRADATA15_GlitchData, OutSignalName => "APUFCMRADATA(15)", OutTemp => APUFCMRADATA_OUT(15), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(16), GlitchData => APUFCMRADATA16_GlitchData, OutSignalName => "APUFCMRADATA(16)", OutTemp => APUFCMRADATA_OUT(16), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(17), GlitchData => APUFCMRADATA17_GlitchData, OutSignalName => "APUFCMRADATA(17)", OutTemp => APUFCMRADATA_OUT(17), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(18), GlitchData => APUFCMRADATA18_GlitchData, OutSignalName => "APUFCMRADATA(18)", OutTemp => APUFCMRADATA_OUT(18), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(19), GlitchData => APUFCMRADATA19_GlitchData, OutSignalName => "APUFCMRADATA(19)", OutTemp => APUFCMRADATA_OUT(19), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(20), GlitchData => APUFCMRADATA20_GlitchData, OutSignalName => "APUFCMRADATA(20)", OutTemp => APUFCMRADATA_OUT(20), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(21), GlitchData => APUFCMRADATA21_GlitchData, OutSignalName => "APUFCMRADATA(21)", OutTemp => APUFCMRADATA_OUT(21), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(22), GlitchData => APUFCMRADATA22_GlitchData, OutSignalName => "APUFCMRADATA(22)", OutTemp => APUFCMRADATA_OUT(22), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(23), GlitchData => APUFCMRADATA23_GlitchData, OutSignalName => "APUFCMRADATA(23)", OutTemp => APUFCMRADATA_OUT(23), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(24), GlitchData => APUFCMRADATA24_GlitchData, OutSignalName => "APUFCMRADATA(24)", OutTemp => APUFCMRADATA_OUT(24), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(25), GlitchData => APUFCMRADATA25_GlitchData, OutSignalName => "APUFCMRADATA(25)", OutTemp => APUFCMRADATA_OUT(25), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(26), GlitchData => APUFCMRADATA26_GlitchData, OutSignalName => "APUFCMRADATA(26)", OutTemp => APUFCMRADATA_OUT(26), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(27), GlitchData => APUFCMRADATA27_GlitchData, OutSignalName => "APUFCMRADATA(27)", OutTemp => APUFCMRADATA_OUT(27), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(28), GlitchData => APUFCMRADATA28_GlitchData, OutSignalName => "APUFCMRADATA(28)", OutTemp => APUFCMRADATA_OUT(28), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(29), GlitchData => APUFCMRADATA29_GlitchData, OutSignalName => "APUFCMRADATA(29)", OutTemp => APUFCMRADATA_OUT(29), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(30), GlitchData => APUFCMRADATA30_GlitchData, OutSignalName => "APUFCMRADATA(30)", OutTemp => APUFCMRADATA_OUT(30), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(31), GlitchData => APUFCMRADATA31_GlitchData, OutSignalName => "APUFCMRADATA(31)", OutTemp => APUFCMRADATA_OUT(31), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(0), GlitchData => APUFCMRBDATA0_GlitchData, OutSignalName => "APUFCMRBDATA(0)", OutTemp => APUFCMRBDATA_OUT(0), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(1), GlitchData => APUFCMRBDATA1_GlitchData, OutSignalName => "APUFCMRBDATA(1)", OutTemp => APUFCMRBDATA_OUT(1), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(2), GlitchData => APUFCMRBDATA2_GlitchData, OutSignalName => "APUFCMRBDATA(2)", OutTemp => APUFCMRBDATA_OUT(2), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(3), GlitchData => APUFCMRBDATA3_GlitchData, OutSignalName => "APUFCMRBDATA(3)", OutTemp => APUFCMRBDATA_OUT(3), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(4), GlitchData => APUFCMRBDATA4_GlitchData, OutSignalName => "APUFCMRBDATA(4)", OutTemp => APUFCMRBDATA_OUT(4), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(5), GlitchData => APUFCMRBDATA5_GlitchData, OutSignalName => "APUFCMRBDATA(5)", OutTemp => APUFCMRBDATA_OUT(5), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(6), GlitchData => APUFCMRBDATA6_GlitchData, OutSignalName => "APUFCMRBDATA(6)", OutTemp => APUFCMRBDATA_OUT(6), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(7), GlitchData => APUFCMRBDATA7_GlitchData, OutSignalName => "APUFCMRBDATA(7)", OutTemp => APUFCMRBDATA_OUT(7), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(8), GlitchData => APUFCMRBDATA8_GlitchData, OutSignalName => "APUFCMRBDATA(8)", OutTemp => APUFCMRBDATA_OUT(8), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(9), GlitchData => APUFCMRBDATA9_GlitchData, OutSignalName => "APUFCMRBDATA(9)", OutTemp => APUFCMRBDATA_OUT(9), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(10), GlitchData => APUFCMRBDATA10_GlitchData, OutSignalName => "APUFCMRBDATA(10)", OutTemp => APUFCMRBDATA_OUT(10), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(11), GlitchData => APUFCMRBDATA11_GlitchData, OutSignalName => "APUFCMRBDATA(11)", OutTemp => APUFCMRBDATA_OUT(11), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(12), GlitchData => APUFCMRBDATA12_GlitchData, OutSignalName => "APUFCMRBDATA(12)", OutTemp => APUFCMRBDATA_OUT(12), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(13), GlitchData => APUFCMRBDATA13_GlitchData, OutSignalName => "APUFCMRBDATA(13)", OutTemp => APUFCMRBDATA_OUT(13), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(14), GlitchData => APUFCMRBDATA14_GlitchData, OutSignalName => "APUFCMRBDATA(14)", OutTemp => APUFCMRBDATA_OUT(14), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(15), GlitchData => APUFCMRBDATA15_GlitchData, OutSignalName => "APUFCMRBDATA(15)", OutTemp => APUFCMRBDATA_OUT(15), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(16), GlitchData => APUFCMRBDATA16_GlitchData, OutSignalName => "APUFCMRBDATA(16)", OutTemp => APUFCMRBDATA_OUT(16), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(17), GlitchData => APUFCMRBDATA17_GlitchData, OutSignalName => "APUFCMRBDATA(17)", OutTemp => APUFCMRBDATA_OUT(17), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(18), GlitchData => APUFCMRBDATA18_GlitchData, OutSignalName => "APUFCMRBDATA(18)", OutTemp => APUFCMRBDATA_OUT(18), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(19), GlitchData => APUFCMRBDATA19_GlitchData, OutSignalName => "APUFCMRBDATA(19)", OutTemp => APUFCMRBDATA_OUT(19), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(20), GlitchData => APUFCMRBDATA20_GlitchData, OutSignalName => "APUFCMRBDATA(20)", OutTemp => APUFCMRBDATA_OUT(20), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(21), GlitchData => APUFCMRBDATA21_GlitchData, OutSignalName => "APUFCMRBDATA(21)", OutTemp => APUFCMRBDATA_OUT(21), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(22), GlitchData => APUFCMRBDATA22_GlitchData, OutSignalName => "APUFCMRBDATA(22)", OutTemp => APUFCMRBDATA_OUT(22), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(23), GlitchData => APUFCMRBDATA23_GlitchData, OutSignalName => "APUFCMRBDATA(23)", OutTemp => APUFCMRBDATA_OUT(23), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(24), GlitchData => APUFCMRBDATA24_GlitchData, OutSignalName => "APUFCMRBDATA(24)", OutTemp => APUFCMRBDATA_OUT(24), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(25), GlitchData => APUFCMRBDATA25_GlitchData, OutSignalName => "APUFCMRBDATA(25)", OutTemp => APUFCMRBDATA_OUT(25), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(26), GlitchData => APUFCMRBDATA26_GlitchData, OutSignalName => "APUFCMRBDATA(26)", OutTemp => APUFCMRBDATA_OUT(26), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(27), GlitchData => APUFCMRBDATA27_GlitchData, OutSignalName => "APUFCMRBDATA(27)", OutTemp => APUFCMRBDATA_OUT(27), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(28), GlitchData => APUFCMRBDATA28_GlitchData, OutSignalName => "APUFCMRBDATA(28)", OutTemp => APUFCMRBDATA_OUT(28), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(29), GlitchData => APUFCMRBDATA29_GlitchData, OutSignalName => "APUFCMRBDATA(29)", OutTemp => APUFCMRBDATA_OUT(29), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(30), GlitchData => APUFCMRBDATA30_GlitchData, OutSignalName => "APUFCMRBDATA(30)", OutTemp => APUFCMRBDATA_OUT(30), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(31), GlitchData => APUFCMRBDATA31_GlitchData, OutSignalName => "APUFCMRBDATA(31)", OutTemp => APUFCMRBDATA_OUT(31), Paths => (0 => (CPMFCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(0), GlitchData => C405DBGWBIAR0_GlitchData, OutSignalName => "C405DBGWBIAR(0)", OutTemp => C405DBGWBIAR_OUT(0), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(1), GlitchData => C405DBGWBIAR1_GlitchData, OutSignalName => "C405DBGWBIAR(1)", OutTemp => C405DBGWBIAR_OUT(1), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(2), GlitchData => C405DBGWBIAR2_GlitchData, OutSignalName => "C405DBGWBIAR(2)", OutTemp => C405DBGWBIAR_OUT(2), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(3), GlitchData => C405DBGWBIAR3_GlitchData, OutSignalName => "C405DBGWBIAR(3)", OutTemp => C405DBGWBIAR_OUT(3), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(4), GlitchData => C405DBGWBIAR4_GlitchData, OutSignalName => "C405DBGWBIAR(4)", OutTemp => C405DBGWBIAR_OUT(4), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(5), GlitchData => C405DBGWBIAR5_GlitchData, OutSignalName => "C405DBGWBIAR(5)", OutTemp => C405DBGWBIAR_OUT(5), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(6), GlitchData => C405DBGWBIAR6_GlitchData, OutSignalName => "C405DBGWBIAR(6)", OutTemp => C405DBGWBIAR_OUT(6), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(7), GlitchData => C405DBGWBIAR7_GlitchData, OutSignalName => "C405DBGWBIAR(7)", OutTemp => C405DBGWBIAR_OUT(7), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(8), GlitchData => C405DBGWBIAR8_GlitchData, OutSignalName => "C405DBGWBIAR(8)", OutTemp => C405DBGWBIAR_OUT(8), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(9), GlitchData => C405DBGWBIAR9_GlitchData, OutSignalName => "C405DBGWBIAR(9)", OutTemp => C405DBGWBIAR_OUT(9), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(10), GlitchData => C405DBGWBIAR10_GlitchData, OutSignalName => "C405DBGWBIAR(10)", OutTemp => C405DBGWBIAR_OUT(10), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(11), GlitchData => C405DBGWBIAR11_GlitchData, OutSignalName => "C405DBGWBIAR(11)", OutTemp => C405DBGWBIAR_OUT(11), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(12), GlitchData => C405DBGWBIAR12_GlitchData, OutSignalName => "C405DBGWBIAR(12)", OutTemp => C405DBGWBIAR_OUT(12), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(13), GlitchData => C405DBGWBIAR13_GlitchData, OutSignalName => "C405DBGWBIAR(13)", OutTemp => C405DBGWBIAR_OUT(13), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(14), GlitchData => C405DBGWBIAR14_GlitchData, OutSignalName => "C405DBGWBIAR(14)", OutTemp => C405DBGWBIAR_OUT(14), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(15), GlitchData => C405DBGWBIAR15_GlitchData, OutSignalName => "C405DBGWBIAR(15)", OutTemp => C405DBGWBIAR_OUT(15), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(16), GlitchData => C405DBGWBIAR16_GlitchData, OutSignalName => "C405DBGWBIAR(16)", OutTemp => C405DBGWBIAR_OUT(16), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(17), GlitchData => C405DBGWBIAR17_GlitchData, OutSignalName => "C405DBGWBIAR(17)", OutTemp => C405DBGWBIAR_OUT(17), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(18), GlitchData => C405DBGWBIAR18_GlitchData, OutSignalName => "C405DBGWBIAR(18)", OutTemp => C405DBGWBIAR_OUT(18), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(19), GlitchData => C405DBGWBIAR19_GlitchData, OutSignalName => "C405DBGWBIAR(19)", OutTemp => C405DBGWBIAR_OUT(19), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(20), GlitchData => C405DBGWBIAR20_GlitchData, OutSignalName => "C405DBGWBIAR(20)", OutTemp => C405DBGWBIAR_OUT(20), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(21), GlitchData => C405DBGWBIAR21_GlitchData, OutSignalName => "C405DBGWBIAR(21)", OutTemp => C405DBGWBIAR_OUT(21), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(22), GlitchData => C405DBGWBIAR22_GlitchData, OutSignalName => "C405DBGWBIAR(22)", OutTemp => C405DBGWBIAR_OUT(22), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(23), GlitchData => C405DBGWBIAR23_GlitchData, OutSignalName => "C405DBGWBIAR(23)", OutTemp => C405DBGWBIAR_OUT(23), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(24), GlitchData => C405DBGWBIAR24_GlitchData, OutSignalName => "C405DBGWBIAR(24)", OutTemp => C405DBGWBIAR_OUT(24), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(25), GlitchData => C405DBGWBIAR25_GlitchData, OutSignalName => "C405DBGWBIAR(25)", OutTemp => C405DBGWBIAR_OUT(25), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(26), GlitchData => C405DBGWBIAR26_GlitchData, OutSignalName => "C405DBGWBIAR(26)", OutTemp => C405DBGWBIAR_OUT(26), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(27), GlitchData => C405DBGWBIAR27_GlitchData, OutSignalName => "C405DBGWBIAR(27)", OutTemp => C405DBGWBIAR_OUT(27), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(28), GlitchData => C405DBGWBIAR28_GlitchData, OutSignalName => "C405DBGWBIAR(28)", OutTemp => C405DBGWBIAR_OUT(28), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405DBGWBIAR(29), GlitchData => C405DBGWBIAR29_GlitchData, OutSignalName => "C405DBGWBIAR(29)", OutTemp => C405DBGWBIAR_OUT(29), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(0), GlitchData => C405PLBDCUABUS0_GlitchData, OutSignalName => "C405PLBDCUABUS(0)", OutTemp => C405PLBDCUABUS_OUT(0), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(1), GlitchData => C405PLBDCUABUS1_GlitchData, OutSignalName => "C405PLBDCUABUS(1)", OutTemp => C405PLBDCUABUS_OUT(1), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(2), GlitchData => C405PLBDCUABUS2_GlitchData, OutSignalName => "C405PLBDCUABUS(2)", OutTemp => C405PLBDCUABUS_OUT(2), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(3), GlitchData => C405PLBDCUABUS3_GlitchData, OutSignalName => "C405PLBDCUABUS(3)", OutTemp => C405PLBDCUABUS_OUT(3), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(4), GlitchData => C405PLBDCUABUS4_GlitchData, OutSignalName => "C405PLBDCUABUS(4)", OutTemp => C405PLBDCUABUS_OUT(4), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(5), GlitchData => C405PLBDCUABUS5_GlitchData, OutSignalName => "C405PLBDCUABUS(5)", OutTemp => C405PLBDCUABUS_OUT(5), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(6), GlitchData => C405PLBDCUABUS6_GlitchData, OutSignalName => "C405PLBDCUABUS(6)", OutTemp => C405PLBDCUABUS_OUT(6), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(7), GlitchData => C405PLBDCUABUS7_GlitchData, OutSignalName => "C405PLBDCUABUS(7)", OutTemp => C405PLBDCUABUS_OUT(7), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(8), GlitchData => C405PLBDCUABUS8_GlitchData, OutSignalName => "C405PLBDCUABUS(8)", OutTemp => C405PLBDCUABUS_OUT(8), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(9), GlitchData => C405PLBDCUABUS9_GlitchData, OutSignalName => "C405PLBDCUABUS(9)", OutTemp => C405PLBDCUABUS_OUT(9), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(10), GlitchData => C405PLBDCUABUS10_GlitchData, OutSignalName => "C405PLBDCUABUS(10)", OutTemp => C405PLBDCUABUS_OUT(10), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(11), GlitchData => C405PLBDCUABUS11_GlitchData, OutSignalName => "C405PLBDCUABUS(11)", OutTemp => C405PLBDCUABUS_OUT(11), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(12), GlitchData => C405PLBDCUABUS12_GlitchData, OutSignalName => "C405PLBDCUABUS(12)", OutTemp => C405PLBDCUABUS_OUT(12), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(13), GlitchData => C405PLBDCUABUS13_GlitchData, OutSignalName => "C405PLBDCUABUS(13)", OutTemp => C405PLBDCUABUS_OUT(13), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(14), GlitchData => C405PLBDCUABUS14_GlitchData, OutSignalName => "C405PLBDCUABUS(14)", OutTemp => C405PLBDCUABUS_OUT(14), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(15), GlitchData => C405PLBDCUABUS15_GlitchData, OutSignalName => "C405PLBDCUABUS(15)", OutTemp => C405PLBDCUABUS_OUT(15), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(16), GlitchData => C405PLBDCUABUS16_GlitchData, OutSignalName => "C405PLBDCUABUS(16)", OutTemp => C405PLBDCUABUS_OUT(16), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(17), GlitchData => C405PLBDCUABUS17_GlitchData, OutSignalName => "C405PLBDCUABUS(17)", OutTemp => C405PLBDCUABUS_OUT(17), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(18), GlitchData => C405PLBDCUABUS18_GlitchData, OutSignalName => "C405PLBDCUABUS(18)", OutTemp => C405PLBDCUABUS_OUT(18), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(19), GlitchData => C405PLBDCUABUS19_GlitchData, OutSignalName => "C405PLBDCUABUS(19)", OutTemp => C405PLBDCUABUS_OUT(19), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(20), GlitchData => C405PLBDCUABUS20_GlitchData, OutSignalName => "C405PLBDCUABUS(20)", OutTemp => C405PLBDCUABUS_OUT(20), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(21), GlitchData => C405PLBDCUABUS21_GlitchData, OutSignalName => "C405PLBDCUABUS(21)", OutTemp => C405PLBDCUABUS_OUT(21), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(22), GlitchData => C405PLBDCUABUS22_GlitchData, OutSignalName => "C405PLBDCUABUS(22)", OutTemp => C405PLBDCUABUS_OUT(22), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(23), GlitchData => C405PLBDCUABUS23_GlitchData, OutSignalName => "C405PLBDCUABUS(23)", OutTemp => C405PLBDCUABUS_OUT(23), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(24), GlitchData => C405PLBDCUABUS24_GlitchData, OutSignalName => "C405PLBDCUABUS(24)", OutTemp => C405PLBDCUABUS_OUT(24), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(25), GlitchData => C405PLBDCUABUS25_GlitchData, OutSignalName => "C405PLBDCUABUS(25)", OutTemp => C405PLBDCUABUS_OUT(25), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(26), GlitchData => C405PLBDCUABUS26_GlitchData, OutSignalName => "C405PLBDCUABUS(26)", OutTemp => C405PLBDCUABUS_OUT(26), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(27), GlitchData => C405PLBDCUABUS27_GlitchData, OutSignalName => "C405PLBDCUABUS(27)", OutTemp => C405PLBDCUABUS_OUT(27), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(28), GlitchData => C405PLBDCUABUS28_GlitchData, OutSignalName => "C405PLBDCUABUS(28)", OutTemp => C405PLBDCUABUS_OUT(28), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(29), GlitchData => C405PLBDCUABUS29_GlitchData, OutSignalName => "C405PLBDCUABUS(29)", OutTemp => C405PLBDCUABUS_OUT(29), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(30), GlitchData => C405PLBDCUABUS30_GlitchData, OutSignalName => "C405PLBDCUABUS(30)", OutTemp => C405PLBDCUABUS_OUT(30), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUABUS(31), GlitchData => C405PLBDCUABUS31_GlitchData, OutSignalName => "C405PLBDCUABUS(31)", OutTemp => C405PLBDCUABUS_OUT(31), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(0), GlitchData => C405PLBDCUBE0_GlitchData, OutSignalName => "C405PLBDCUBE(0)", OutTemp => C405PLBDCUBE_OUT(0), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(1), GlitchData => C405PLBDCUBE1_GlitchData, OutSignalName => "C405PLBDCUBE(1)", OutTemp => C405PLBDCUBE_OUT(1), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(2), GlitchData => C405PLBDCUBE2_GlitchData, OutSignalName => "C405PLBDCUBE(2)", OutTemp => C405PLBDCUBE_OUT(2), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(3), GlitchData => C405PLBDCUBE3_GlitchData, OutSignalName => "C405PLBDCUBE(3)", OutTemp => C405PLBDCUBE_OUT(3), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(4), GlitchData => C405PLBDCUBE4_GlitchData, OutSignalName => "C405PLBDCUBE(4)", OutTemp => C405PLBDCUBE_OUT(4), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(5), GlitchData => C405PLBDCUBE5_GlitchData, OutSignalName => "C405PLBDCUBE(5)", OutTemp => C405PLBDCUBE_OUT(5), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(6), GlitchData => C405PLBDCUBE6_GlitchData, OutSignalName => "C405PLBDCUBE(6)", OutTemp => C405PLBDCUBE_OUT(6), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUBE(7), GlitchData => C405PLBDCUBE7_GlitchData, OutSignalName => "C405PLBDCUBE(7)", OutTemp => C405PLBDCUBE_OUT(7), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUPRIORITY(0), GlitchData => C405PLBDCUPRIORITY0_GlitchData, OutSignalName => "C405PLBDCUPRIORITY(0)", OutTemp => C405PLBDCUPRIORITY_OUT(0), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUPRIORITY(1), GlitchData => C405PLBDCUPRIORITY1_GlitchData, OutSignalName => "C405PLBDCUPRIORITY(1)", OutTemp => C405PLBDCUPRIORITY_OUT(1), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(0), GlitchData => C405PLBDCUWRDBUS0_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(0)", OutTemp => C405PLBDCUWRDBUS_OUT(0), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(1), GlitchData => C405PLBDCUWRDBUS1_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(1)", OutTemp => C405PLBDCUWRDBUS_OUT(1), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(2), GlitchData => C405PLBDCUWRDBUS2_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(2)", OutTemp => C405PLBDCUWRDBUS_OUT(2), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(3), GlitchData => C405PLBDCUWRDBUS3_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(3)", OutTemp => C405PLBDCUWRDBUS_OUT(3), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(4), GlitchData => C405PLBDCUWRDBUS4_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(4)", OutTemp => C405PLBDCUWRDBUS_OUT(4), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(5), GlitchData => C405PLBDCUWRDBUS5_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(5)", OutTemp => C405PLBDCUWRDBUS_OUT(5), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(6), GlitchData => C405PLBDCUWRDBUS6_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(6)", OutTemp => C405PLBDCUWRDBUS_OUT(6), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(7), GlitchData => C405PLBDCUWRDBUS7_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(7)", OutTemp => C405PLBDCUWRDBUS_OUT(7), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(8), GlitchData => C405PLBDCUWRDBUS8_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(8)", OutTemp => C405PLBDCUWRDBUS_OUT(8), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(9), GlitchData => C405PLBDCUWRDBUS9_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(9)", OutTemp => C405PLBDCUWRDBUS_OUT(9), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(10), GlitchData => C405PLBDCUWRDBUS10_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(10)", OutTemp => C405PLBDCUWRDBUS_OUT(10), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(11), GlitchData => C405PLBDCUWRDBUS11_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(11)", OutTemp => C405PLBDCUWRDBUS_OUT(11), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(12), GlitchData => C405PLBDCUWRDBUS12_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(12)", OutTemp => C405PLBDCUWRDBUS_OUT(12), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(13), GlitchData => C405PLBDCUWRDBUS13_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(13)", OutTemp => C405PLBDCUWRDBUS_OUT(13), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(14), GlitchData => C405PLBDCUWRDBUS14_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(14)", OutTemp => C405PLBDCUWRDBUS_OUT(14), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(15), GlitchData => C405PLBDCUWRDBUS15_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(15)", OutTemp => C405PLBDCUWRDBUS_OUT(15), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(16), GlitchData => C405PLBDCUWRDBUS16_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(16)", OutTemp => C405PLBDCUWRDBUS_OUT(16), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(17), GlitchData => C405PLBDCUWRDBUS17_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(17)", OutTemp => C405PLBDCUWRDBUS_OUT(17), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(18), GlitchData => C405PLBDCUWRDBUS18_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(18)", OutTemp => C405PLBDCUWRDBUS_OUT(18), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(19), GlitchData => C405PLBDCUWRDBUS19_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(19)", OutTemp => C405PLBDCUWRDBUS_OUT(19), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(20), GlitchData => C405PLBDCUWRDBUS20_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(20)", OutTemp => C405PLBDCUWRDBUS_OUT(20), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(21), GlitchData => C405PLBDCUWRDBUS21_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(21)", OutTemp => C405PLBDCUWRDBUS_OUT(21), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(22), GlitchData => C405PLBDCUWRDBUS22_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(22)", OutTemp => C405PLBDCUWRDBUS_OUT(22), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(23), GlitchData => C405PLBDCUWRDBUS23_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(23)", OutTemp => C405PLBDCUWRDBUS_OUT(23), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(24), GlitchData => C405PLBDCUWRDBUS24_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(24)", OutTemp => C405PLBDCUWRDBUS_OUT(24), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(25), GlitchData => C405PLBDCUWRDBUS25_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(25)", OutTemp => C405PLBDCUWRDBUS_OUT(25), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(26), GlitchData => C405PLBDCUWRDBUS26_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(26)", OutTemp => C405PLBDCUWRDBUS_OUT(26), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(27), GlitchData => C405PLBDCUWRDBUS27_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(27)", OutTemp => C405PLBDCUWRDBUS_OUT(27), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(28), GlitchData => C405PLBDCUWRDBUS28_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(28)", OutTemp => C405PLBDCUWRDBUS_OUT(28), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(29), GlitchData => C405PLBDCUWRDBUS29_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(29)", OutTemp => C405PLBDCUWRDBUS_OUT(29), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(30), GlitchData => C405PLBDCUWRDBUS30_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(30)", OutTemp => C405PLBDCUWRDBUS_OUT(30), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(31), GlitchData => C405PLBDCUWRDBUS31_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(31)", OutTemp => C405PLBDCUWRDBUS_OUT(31), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(32), GlitchData => C405PLBDCUWRDBUS32_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(32)", OutTemp => C405PLBDCUWRDBUS_OUT(32), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(33), GlitchData => C405PLBDCUWRDBUS33_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(33)", OutTemp => C405PLBDCUWRDBUS_OUT(33), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(34), GlitchData => C405PLBDCUWRDBUS34_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(34)", OutTemp => C405PLBDCUWRDBUS_OUT(34), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(35), GlitchData => C405PLBDCUWRDBUS35_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(35)", OutTemp => C405PLBDCUWRDBUS_OUT(35), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(36), GlitchData => C405PLBDCUWRDBUS36_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(36)", OutTemp => C405PLBDCUWRDBUS_OUT(36), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(37), GlitchData => C405PLBDCUWRDBUS37_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(37)", OutTemp => C405PLBDCUWRDBUS_OUT(37), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(38), GlitchData => C405PLBDCUWRDBUS38_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(38)", OutTemp => C405PLBDCUWRDBUS_OUT(38), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(39), GlitchData => C405PLBDCUWRDBUS39_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(39)", OutTemp => C405PLBDCUWRDBUS_OUT(39), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(40), GlitchData => C405PLBDCUWRDBUS40_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(40)", OutTemp => C405PLBDCUWRDBUS_OUT(40), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(41), GlitchData => C405PLBDCUWRDBUS41_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(41)", OutTemp => C405PLBDCUWRDBUS_OUT(41), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(42), GlitchData => C405PLBDCUWRDBUS42_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(42)", OutTemp => C405PLBDCUWRDBUS_OUT(42), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(43), GlitchData => C405PLBDCUWRDBUS43_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(43)", OutTemp => C405PLBDCUWRDBUS_OUT(43), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(44), GlitchData => C405PLBDCUWRDBUS44_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(44)", OutTemp => C405PLBDCUWRDBUS_OUT(44), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(45), GlitchData => C405PLBDCUWRDBUS45_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(45)", OutTemp => C405PLBDCUWRDBUS_OUT(45), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(46), GlitchData => C405PLBDCUWRDBUS46_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(46)", OutTemp => C405PLBDCUWRDBUS_OUT(46), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(47), GlitchData => C405PLBDCUWRDBUS47_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(47)", OutTemp => C405PLBDCUWRDBUS_OUT(47), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(48), GlitchData => C405PLBDCUWRDBUS48_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(48)", OutTemp => C405PLBDCUWRDBUS_OUT(48), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(49), GlitchData => C405PLBDCUWRDBUS49_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(49)", OutTemp => C405PLBDCUWRDBUS_OUT(49), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(50), GlitchData => C405PLBDCUWRDBUS50_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(50)", OutTemp => C405PLBDCUWRDBUS_OUT(50), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(51), GlitchData => C405PLBDCUWRDBUS51_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(51)", OutTemp => C405PLBDCUWRDBUS_OUT(51), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(52), GlitchData => C405PLBDCUWRDBUS52_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(52)", OutTemp => C405PLBDCUWRDBUS_OUT(52), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(53), GlitchData => C405PLBDCUWRDBUS53_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(53)", OutTemp => C405PLBDCUWRDBUS_OUT(53), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(54), GlitchData => C405PLBDCUWRDBUS54_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(54)", OutTemp => C405PLBDCUWRDBUS_OUT(54), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(55), GlitchData => C405PLBDCUWRDBUS55_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(55)", OutTemp => C405PLBDCUWRDBUS_OUT(55), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(56), GlitchData => C405PLBDCUWRDBUS56_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(56)", OutTemp => C405PLBDCUWRDBUS_OUT(56), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(57), GlitchData => C405PLBDCUWRDBUS57_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(57)", OutTemp => C405PLBDCUWRDBUS_OUT(57), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(58), GlitchData => C405PLBDCUWRDBUS58_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(58)", OutTemp => C405PLBDCUWRDBUS_OUT(58), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(59), GlitchData => C405PLBDCUWRDBUS59_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(59)", OutTemp => C405PLBDCUWRDBUS_OUT(59), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(60), GlitchData => C405PLBDCUWRDBUS60_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(60)", OutTemp => C405PLBDCUWRDBUS_OUT(60), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(61), GlitchData => C405PLBDCUWRDBUS61_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(61)", OutTemp => C405PLBDCUWRDBUS_OUT(61), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(62), GlitchData => C405PLBDCUWRDBUS62_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(62)", OutTemp => C405PLBDCUWRDBUS_OUT(62), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBDCUWRDBUS(63), GlitchData => C405PLBDCUWRDBUS63_GlitchData, OutSignalName => "C405PLBDCUWRDBUS(63)", OutTemp => C405PLBDCUWRDBUS_OUT(63), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(0), GlitchData => C405PLBICUABUS0_GlitchData, OutSignalName => "C405PLBICUABUS(0)", OutTemp => C405PLBICUABUS_OUT(0), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(1), GlitchData => C405PLBICUABUS1_GlitchData, OutSignalName => "C405PLBICUABUS(1)", OutTemp => C405PLBICUABUS_OUT(1), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(2), GlitchData => C405PLBICUABUS2_GlitchData, OutSignalName => "C405PLBICUABUS(2)", OutTemp => C405PLBICUABUS_OUT(2), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(3), GlitchData => C405PLBICUABUS3_GlitchData, OutSignalName => "C405PLBICUABUS(3)", OutTemp => C405PLBICUABUS_OUT(3), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(4), GlitchData => C405PLBICUABUS4_GlitchData, OutSignalName => "C405PLBICUABUS(4)", OutTemp => C405PLBICUABUS_OUT(4), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(5), GlitchData => C405PLBICUABUS5_GlitchData, OutSignalName => "C405PLBICUABUS(5)", OutTemp => C405PLBICUABUS_OUT(5), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(6), GlitchData => C405PLBICUABUS6_GlitchData, OutSignalName => "C405PLBICUABUS(6)", OutTemp => C405PLBICUABUS_OUT(6), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(7), GlitchData => C405PLBICUABUS7_GlitchData, OutSignalName => "C405PLBICUABUS(7)", OutTemp => C405PLBICUABUS_OUT(7), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(8), GlitchData => C405PLBICUABUS8_GlitchData, OutSignalName => "C405PLBICUABUS(8)", OutTemp => C405PLBICUABUS_OUT(8), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(9), GlitchData => C405PLBICUABUS9_GlitchData, OutSignalName => "C405PLBICUABUS(9)", OutTemp => C405PLBICUABUS_OUT(9), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(10), GlitchData => C405PLBICUABUS10_GlitchData, OutSignalName => "C405PLBICUABUS(10)", OutTemp => C405PLBICUABUS_OUT(10), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(11), GlitchData => C405PLBICUABUS11_GlitchData, OutSignalName => "C405PLBICUABUS(11)", OutTemp => C405PLBICUABUS_OUT(11), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(12), GlitchData => C405PLBICUABUS12_GlitchData, OutSignalName => "C405PLBICUABUS(12)", OutTemp => C405PLBICUABUS_OUT(12), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(13), GlitchData => C405PLBICUABUS13_GlitchData, OutSignalName => "C405PLBICUABUS(13)", OutTemp => C405PLBICUABUS_OUT(13), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(14), GlitchData => C405PLBICUABUS14_GlitchData, OutSignalName => "C405PLBICUABUS(14)", OutTemp => C405PLBICUABUS_OUT(14), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(15), GlitchData => C405PLBICUABUS15_GlitchData, OutSignalName => "C405PLBICUABUS(15)", OutTemp => C405PLBICUABUS_OUT(15), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(16), GlitchData => C405PLBICUABUS16_GlitchData, OutSignalName => "C405PLBICUABUS(16)", OutTemp => C405PLBICUABUS_OUT(16), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(17), GlitchData => C405PLBICUABUS17_GlitchData, OutSignalName => "C405PLBICUABUS(17)", OutTemp => C405PLBICUABUS_OUT(17), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(18), GlitchData => C405PLBICUABUS18_GlitchData, OutSignalName => "C405PLBICUABUS(18)", OutTemp => C405PLBICUABUS_OUT(18), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(19), GlitchData => C405PLBICUABUS19_GlitchData, OutSignalName => "C405PLBICUABUS(19)", OutTemp => C405PLBICUABUS_OUT(19), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(20), GlitchData => C405PLBICUABUS20_GlitchData, OutSignalName => "C405PLBICUABUS(20)", OutTemp => C405PLBICUABUS_OUT(20), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(21), GlitchData => C405PLBICUABUS21_GlitchData, OutSignalName => "C405PLBICUABUS(21)", OutTemp => C405PLBICUABUS_OUT(21), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(22), GlitchData => C405PLBICUABUS22_GlitchData, OutSignalName => "C405PLBICUABUS(22)", OutTemp => C405PLBICUABUS_OUT(22), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(23), GlitchData => C405PLBICUABUS23_GlitchData, OutSignalName => "C405PLBICUABUS(23)", OutTemp => C405PLBICUABUS_OUT(23), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(24), GlitchData => C405PLBICUABUS24_GlitchData, OutSignalName => "C405PLBICUABUS(24)", OutTemp => C405PLBICUABUS_OUT(24), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(25), GlitchData => C405PLBICUABUS25_GlitchData, OutSignalName => "C405PLBICUABUS(25)", OutTemp => C405PLBICUABUS_OUT(25), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(26), GlitchData => C405PLBICUABUS26_GlitchData, OutSignalName => "C405PLBICUABUS(26)", OutTemp => C405PLBICUABUS_OUT(26), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(27), GlitchData => C405PLBICUABUS27_GlitchData, OutSignalName => "C405PLBICUABUS(27)", OutTemp => C405PLBICUABUS_OUT(27), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(28), GlitchData => C405PLBICUABUS28_GlitchData, OutSignalName => "C405PLBICUABUS(28)", OutTemp => C405PLBICUABUS_OUT(28), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUABUS(29), GlitchData => C405PLBICUABUS29_GlitchData, OutSignalName => "C405PLBICUABUS(29)", OutTemp => C405PLBICUABUS_OUT(29), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUPRIORITY(0), GlitchData => C405PLBICUPRIORITY0_GlitchData, OutSignalName => "C405PLBICUPRIORITY(0)", OutTemp => C405PLBICUPRIORITY_OUT(0), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUPRIORITY(1), GlitchData => C405PLBICUPRIORITY1_GlitchData, OutSignalName => "C405PLBICUPRIORITY(1)", OutTemp => C405PLBICUPRIORITY_OUT(1), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUSIZE(2), GlitchData => C405PLBICUSIZE2_GlitchData, OutSignalName => "C405PLBICUSIZE(2)", OutTemp => C405PLBICUSIZE_OUT(2), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405PLBICUSIZE(3), GlitchData => C405PLBICUSIZE3_GlitchData, OutSignalName => "C405PLBICUSIZE(3)", OutTemp => C405PLBICUSIZE_OUT(3), Paths => (0 => (PLBCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCEVENEXECUTIONSTATUS(0), GlitchData => C405TRCEVENEXECUTIONSTATUS0_GlitchData, OutSignalName => "C405TRCEVENEXECUTIONSTATUS(0)", OutTemp => C405TRCEVENEXECUTIONSTATUS_OUT(0), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCEVENEXECUTIONSTATUS(1), GlitchData => C405TRCEVENEXECUTIONSTATUS1_GlitchData, OutSignalName => "C405TRCEVENEXECUTIONSTATUS(1)", OutTemp => C405TRCEVENEXECUTIONSTATUS_OUT(1), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCODDEXECUTIONSTATUS(0), GlitchData => C405TRCODDEXECUTIONSTATUS0_GlitchData, OutSignalName => "C405TRCODDEXECUTIONSTATUS(0)", OutTemp => C405TRCODDEXECUTIONSTATUS_OUT(0), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCODDEXECUTIONSTATUS(1), GlitchData => C405TRCODDEXECUTIONSTATUS1_GlitchData, OutSignalName => "C405TRCODDEXECUTIONSTATUS(1)", OutTemp => C405TRCODDEXECUTIONSTATUS_OUT(1), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRACESTATUS(0), GlitchData => C405TRCTRACESTATUS0_GlitchData, OutSignalName => "C405TRCTRACESTATUS(0)", OutTemp => C405TRCTRACESTATUS_OUT(0), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRACESTATUS(1), GlitchData => C405TRCTRACESTATUS1_GlitchData, OutSignalName => "C405TRCTRACESTATUS(1)", OutTemp => C405TRCTRACESTATUS_OUT(1), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRACESTATUS(2), GlitchData => C405TRCTRACESTATUS2_GlitchData, OutSignalName => "C405TRCTRACESTATUS(2)", OutTemp => C405TRCTRACESTATUS_OUT(2), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRACESTATUS(3), GlitchData => C405TRCTRACESTATUS3_GlitchData, OutSignalName => "C405TRCTRACESTATUS(3)", OutTemp => C405TRCTRACESTATUS_OUT(3), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(0), GlitchData => C405TRCTRIGGEREVENTTYPE0_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(0)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(0), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(1), GlitchData => C405TRCTRIGGEREVENTTYPE1_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(1)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(1), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(2), GlitchData => C405TRCTRIGGEREVENTTYPE2_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(2)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(2), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(3), GlitchData => C405TRCTRIGGEREVENTTYPE3_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(3)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(3), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(4), GlitchData => C405TRCTRIGGEREVENTTYPE4_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(4)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(4), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(5), GlitchData => C405TRCTRIGGEREVENTTYPE5_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(5)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(5), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(6), GlitchData => C405TRCTRIGGEREVENTTYPE6_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(6)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(6), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(7), GlitchData => C405TRCTRIGGEREVENTTYPE7_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(7)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(7), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(8), GlitchData => C405TRCTRIGGEREVENTTYPE8_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(8)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(8), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(9), GlitchData => C405TRCTRIGGEREVENTTYPE9_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(9)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(9), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C405TRCTRIGGEREVENTTYPE(10), GlitchData => C405TRCTRIGGEREVENTTYPE10_GlitchData, OutSignalName => "C405TRCTRIGGEREVENTTYPE(10)", OutTemp => C405TRCTRIGGEREVENTTYPE_OUT(10), Paths => (0 => (CPMC405CLOCK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(8), GlitchData => DSOCMBRAMABUS8_GlitchData, OutSignalName => "DSOCMBRAMABUS(8)", OutTemp => DSOCMBRAMABUS_OUT(8), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(9), GlitchData => DSOCMBRAMABUS9_GlitchData, OutSignalName => "DSOCMBRAMABUS(9)", OutTemp => DSOCMBRAMABUS_OUT(9), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(10), GlitchData => DSOCMBRAMABUS10_GlitchData, OutSignalName => "DSOCMBRAMABUS(10)", OutTemp => DSOCMBRAMABUS_OUT(10), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(11), GlitchData => DSOCMBRAMABUS11_GlitchData, OutSignalName => "DSOCMBRAMABUS(11)", OutTemp => DSOCMBRAMABUS_OUT(11), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(12), GlitchData => DSOCMBRAMABUS12_GlitchData, OutSignalName => "DSOCMBRAMABUS(12)", OutTemp => DSOCMBRAMABUS_OUT(12), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(13), GlitchData => DSOCMBRAMABUS13_GlitchData, OutSignalName => "DSOCMBRAMABUS(13)", OutTemp => DSOCMBRAMABUS_OUT(13), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(14), GlitchData => DSOCMBRAMABUS14_GlitchData, OutSignalName => "DSOCMBRAMABUS(14)", OutTemp => DSOCMBRAMABUS_OUT(14), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(15), GlitchData => DSOCMBRAMABUS15_GlitchData, OutSignalName => "DSOCMBRAMABUS(15)", OutTemp => DSOCMBRAMABUS_OUT(15), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(16), GlitchData => DSOCMBRAMABUS16_GlitchData, OutSignalName => "DSOCMBRAMABUS(16)", OutTemp => DSOCMBRAMABUS_OUT(16), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(17), GlitchData => DSOCMBRAMABUS17_GlitchData, OutSignalName => "DSOCMBRAMABUS(17)", OutTemp => DSOCMBRAMABUS_OUT(17), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(18), GlitchData => DSOCMBRAMABUS18_GlitchData, OutSignalName => "DSOCMBRAMABUS(18)", OutTemp => DSOCMBRAMABUS_OUT(18), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(19), GlitchData => DSOCMBRAMABUS19_GlitchData, OutSignalName => "DSOCMBRAMABUS(19)", OutTemp => DSOCMBRAMABUS_OUT(19), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(20), GlitchData => DSOCMBRAMABUS20_GlitchData, OutSignalName => "DSOCMBRAMABUS(20)", OutTemp => DSOCMBRAMABUS_OUT(20), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(21), GlitchData => DSOCMBRAMABUS21_GlitchData, OutSignalName => "DSOCMBRAMABUS(21)", OutTemp => DSOCMBRAMABUS_OUT(21), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(22), GlitchData => DSOCMBRAMABUS22_GlitchData, OutSignalName => "DSOCMBRAMABUS(22)", OutTemp => DSOCMBRAMABUS_OUT(22), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(23), GlitchData => DSOCMBRAMABUS23_GlitchData, OutSignalName => "DSOCMBRAMABUS(23)", OutTemp => DSOCMBRAMABUS_OUT(23), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(24), GlitchData => DSOCMBRAMABUS24_GlitchData, OutSignalName => "DSOCMBRAMABUS(24)", OutTemp => DSOCMBRAMABUS_OUT(24), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(25), GlitchData => DSOCMBRAMABUS25_GlitchData, OutSignalName => "DSOCMBRAMABUS(25)", OutTemp => DSOCMBRAMABUS_OUT(25), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(26), GlitchData => DSOCMBRAMABUS26_GlitchData, OutSignalName => "DSOCMBRAMABUS(26)", OutTemp => DSOCMBRAMABUS_OUT(26), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(27), GlitchData => DSOCMBRAMABUS27_GlitchData, OutSignalName => "DSOCMBRAMABUS(27)", OutTemp => DSOCMBRAMABUS_OUT(27), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(28), GlitchData => DSOCMBRAMABUS28_GlitchData, OutSignalName => "DSOCMBRAMABUS(28)", OutTemp => DSOCMBRAMABUS_OUT(28), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMABUS(29), GlitchData => DSOCMBRAMABUS29_GlitchData, OutSignalName => "DSOCMBRAMABUS(29)", OutTemp => DSOCMBRAMABUS_OUT(29), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMBYTEWRITE(0), GlitchData => DSOCMBRAMBYTEWRITE0_GlitchData, OutSignalName => "DSOCMBRAMBYTEWRITE(0)", OutTemp => DSOCMBRAMBYTEWRITE_OUT(0), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMBYTEWRITE(1), GlitchData => DSOCMBRAMBYTEWRITE1_GlitchData, OutSignalName => "DSOCMBRAMBYTEWRITE(1)", OutTemp => DSOCMBRAMBYTEWRITE_OUT(1), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMBYTEWRITE(2), GlitchData => DSOCMBRAMBYTEWRITE2_GlitchData, OutSignalName => "DSOCMBRAMBYTEWRITE(2)", OutTemp => DSOCMBRAMBYTEWRITE_OUT(2), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMBYTEWRITE(3), GlitchData => DSOCMBRAMBYTEWRITE3_GlitchData, OutSignalName => "DSOCMBRAMBYTEWRITE(3)", OutTemp => DSOCMBRAMBYTEWRITE_OUT(3), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(0), GlitchData => DSOCMBRAMWRDBUS0_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(0)", OutTemp => DSOCMBRAMWRDBUS_OUT(0), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(1), GlitchData => DSOCMBRAMWRDBUS1_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(1)", OutTemp => DSOCMBRAMWRDBUS_OUT(1), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(2), GlitchData => DSOCMBRAMWRDBUS2_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(2)", OutTemp => DSOCMBRAMWRDBUS_OUT(2), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(3), GlitchData => DSOCMBRAMWRDBUS3_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(3)", OutTemp => DSOCMBRAMWRDBUS_OUT(3), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(4), GlitchData => DSOCMBRAMWRDBUS4_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(4)", OutTemp => DSOCMBRAMWRDBUS_OUT(4), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(5), GlitchData => DSOCMBRAMWRDBUS5_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(5)", OutTemp => DSOCMBRAMWRDBUS_OUT(5), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(6), GlitchData => DSOCMBRAMWRDBUS6_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(6)", OutTemp => DSOCMBRAMWRDBUS_OUT(6), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(7), GlitchData => DSOCMBRAMWRDBUS7_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(7)", OutTemp => DSOCMBRAMWRDBUS_OUT(7), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(8), GlitchData => DSOCMBRAMWRDBUS8_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(8)", OutTemp => DSOCMBRAMWRDBUS_OUT(8), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(9), GlitchData => DSOCMBRAMWRDBUS9_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(9)", OutTemp => DSOCMBRAMWRDBUS_OUT(9), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(10), GlitchData => DSOCMBRAMWRDBUS10_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(10)", OutTemp => DSOCMBRAMWRDBUS_OUT(10), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(11), GlitchData => DSOCMBRAMWRDBUS11_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(11)", OutTemp => DSOCMBRAMWRDBUS_OUT(11), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(12), GlitchData => DSOCMBRAMWRDBUS12_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(12)", OutTemp => DSOCMBRAMWRDBUS_OUT(12), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(13), GlitchData => DSOCMBRAMWRDBUS13_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(13)", OutTemp => DSOCMBRAMWRDBUS_OUT(13), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(14), GlitchData => DSOCMBRAMWRDBUS14_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(14)", OutTemp => DSOCMBRAMWRDBUS_OUT(14), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(15), GlitchData => DSOCMBRAMWRDBUS15_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(15)", OutTemp => DSOCMBRAMWRDBUS_OUT(15), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(16), GlitchData => DSOCMBRAMWRDBUS16_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(16)", OutTemp => DSOCMBRAMWRDBUS_OUT(16), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(17), GlitchData => DSOCMBRAMWRDBUS17_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(17)", OutTemp => DSOCMBRAMWRDBUS_OUT(17), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(18), GlitchData => DSOCMBRAMWRDBUS18_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(18)", OutTemp => DSOCMBRAMWRDBUS_OUT(18), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(19), GlitchData => DSOCMBRAMWRDBUS19_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(19)", OutTemp => DSOCMBRAMWRDBUS_OUT(19), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(20), GlitchData => DSOCMBRAMWRDBUS20_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(20)", OutTemp => DSOCMBRAMWRDBUS_OUT(20), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(21), GlitchData => DSOCMBRAMWRDBUS21_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(21)", OutTemp => DSOCMBRAMWRDBUS_OUT(21), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(22), GlitchData => DSOCMBRAMWRDBUS22_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(22)", OutTemp => DSOCMBRAMWRDBUS_OUT(22), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(23), GlitchData => DSOCMBRAMWRDBUS23_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(23)", OutTemp => DSOCMBRAMWRDBUS_OUT(23), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(24), GlitchData => DSOCMBRAMWRDBUS24_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(24)", OutTemp => DSOCMBRAMWRDBUS_OUT(24), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(25), GlitchData => DSOCMBRAMWRDBUS25_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(25)", OutTemp => DSOCMBRAMWRDBUS_OUT(25), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(26), GlitchData => DSOCMBRAMWRDBUS26_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(26)", OutTemp => DSOCMBRAMWRDBUS_OUT(26), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(27), GlitchData => DSOCMBRAMWRDBUS27_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(27)", OutTemp => DSOCMBRAMWRDBUS_OUT(27), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(28), GlitchData => DSOCMBRAMWRDBUS28_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(28)", OutTemp => DSOCMBRAMWRDBUS_OUT(28), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(29), GlitchData => DSOCMBRAMWRDBUS29_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(29)", OutTemp => DSOCMBRAMWRDBUS_OUT(29), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(30), GlitchData => DSOCMBRAMWRDBUS30_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(30)", OutTemp => DSOCMBRAMWRDBUS_OUT(30), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DSOCMBRAMWRDBUS(31), GlitchData => DSOCMBRAMWRDBUS31_GlitchData, OutSignalName => "DSOCMBRAMWRDBUS(31)", OutTemp => DSOCMBRAMWRDBUS_OUT(31), Paths => (0 => (BRAMDSOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRABUS(0), GlitchData => EXTDCRABUS0_GlitchData, OutSignalName => "EXTDCRABUS(0)", OutTemp => EXTDCRABUS_OUT(0), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRABUS(1), GlitchData => EXTDCRABUS1_GlitchData, OutSignalName => "EXTDCRABUS(1)", OutTemp => EXTDCRABUS_OUT(1), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRABUS(2), GlitchData => EXTDCRABUS2_GlitchData, OutSignalName => "EXTDCRABUS(2)", OutTemp => EXTDCRABUS_OUT(2), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRABUS(3), GlitchData => EXTDCRABUS3_GlitchData, OutSignalName => "EXTDCRABUS(3)", OutTemp => EXTDCRABUS_OUT(3), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRABUS(4), GlitchData => EXTDCRABUS4_GlitchData, OutSignalName => "EXTDCRABUS(4)", OutTemp => EXTDCRABUS_OUT(4), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRABUS(5), GlitchData => EXTDCRABUS5_GlitchData, OutSignalName => "EXTDCRABUS(5)", OutTemp => EXTDCRABUS_OUT(5), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRABUS(6), GlitchData => EXTDCRABUS6_GlitchData, OutSignalName => "EXTDCRABUS(6)", OutTemp => EXTDCRABUS_OUT(6), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRABUS(7), GlitchData => EXTDCRABUS7_GlitchData, OutSignalName => "EXTDCRABUS(7)", OutTemp => EXTDCRABUS_OUT(7), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRABUS(8), GlitchData => EXTDCRABUS8_GlitchData, OutSignalName => "EXTDCRABUS(8)", OutTemp => EXTDCRABUS_OUT(8), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRABUS(9), GlitchData => EXTDCRABUS9_GlitchData, OutSignalName => "EXTDCRABUS(9)", OutTemp => EXTDCRABUS_OUT(9), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(0), GlitchData => EXTDCRDBUSOUT0_GlitchData, OutSignalName => "EXTDCRDBUSOUT(0)", OutTemp => EXTDCRDBUSOUT_OUT(0), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(1), GlitchData => EXTDCRDBUSOUT1_GlitchData, OutSignalName => "EXTDCRDBUSOUT(1)", OutTemp => EXTDCRDBUSOUT_OUT(1), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(2), GlitchData => EXTDCRDBUSOUT2_GlitchData, OutSignalName => "EXTDCRDBUSOUT(2)", OutTemp => EXTDCRDBUSOUT_OUT(2), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(3), GlitchData => EXTDCRDBUSOUT3_GlitchData, OutSignalName => "EXTDCRDBUSOUT(3)", OutTemp => EXTDCRDBUSOUT_OUT(3), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(4), GlitchData => EXTDCRDBUSOUT4_GlitchData, OutSignalName => "EXTDCRDBUSOUT(4)", OutTemp => EXTDCRDBUSOUT_OUT(4), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(5), GlitchData => EXTDCRDBUSOUT5_GlitchData, OutSignalName => "EXTDCRDBUSOUT(5)", OutTemp => EXTDCRDBUSOUT_OUT(5), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(6), GlitchData => EXTDCRDBUSOUT6_GlitchData, OutSignalName => "EXTDCRDBUSOUT(6)", OutTemp => EXTDCRDBUSOUT_OUT(6), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(7), GlitchData => EXTDCRDBUSOUT7_GlitchData, OutSignalName => "EXTDCRDBUSOUT(7)", OutTemp => EXTDCRDBUSOUT_OUT(7), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(8), GlitchData => EXTDCRDBUSOUT8_GlitchData, OutSignalName => "EXTDCRDBUSOUT(8)", OutTemp => EXTDCRDBUSOUT_OUT(8), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(9), GlitchData => EXTDCRDBUSOUT9_GlitchData, OutSignalName => "EXTDCRDBUSOUT(9)", OutTemp => EXTDCRDBUSOUT_OUT(9), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(10), GlitchData => EXTDCRDBUSOUT10_GlitchData, OutSignalName => "EXTDCRDBUSOUT(10)", OutTemp => EXTDCRDBUSOUT_OUT(10), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(11), GlitchData => EXTDCRDBUSOUT11_GlitchData, OutSignalName => "EXTDCRDBUSOUT(11)", OutTemp => EXTDCRDBUSOUT_OUT(11), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(12), GlitchData => EXTDCRDBUSOUT12_GlitchData, OutSignalName => "EXTDCRDBUSOUT(12)", OutTemp => EXTDCRDBUSOUT_OUT(12), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(13), GlitchData => EXTDCRDBUSOUT13_GlitchData, OutSignalName => "EXTDCRDBUSOUT(13)", OutTemp => EXTDCRDBUSOUT_OUT(13), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(14), GlitchData => EXTDCRDBUSOUT14_GlitchData, OutSignalName => "EXTDCRDBUSOUT(14)", OutTemp => EXTDCRDBUSOUT_OUT(14), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(15), GlitchData => EXTDCRDBUSOUT15_GlitchData, OutSignalName => "EXTDCRDBUSOUT(15)", OutTemp => EXTDCRDBUSOUT_OUT(15), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(16), GlitchData => EXTDCRDBUSOUT16_GlitchData, OutSignalName => "EXTDCRDBUSOUT(16)", OutTemp => EXTDCRDBUSOUT_OUT(16), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(17), GlitchData => EXTDCRDBUSOUT17_GlitchData, OutSignalName => "EXTDCRDBUSOUT(17)", OutTemp => EXTDCRDBUSOUT_OUT(17), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(18), GlitchData => EXTDCRDBUSOUT18_GlitchData, OutSignalName => "EXTDCRDBUSOUT(18)", OutTemp => EXTDCRDBUSOUT_OUT(18), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(19), GlitchData => EXTDCRDBUSOUT19_GlitchData, OutSignalName => "EXTDCRDBUSOUT(19)", OutTemp => EXTDCRDBUSOUT_OUT(19), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(20), GlitchData => EXTDCRDBUSOUT20_GlitchData, OutSignalName => "EXTDCRDBUSOUT(20)", OutTemp => EXTDCRDBUSOUT_OUT(20), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(21), GlitchData => EXTDCRDBUSOUT21_GlitchData, OutSignalName => "EXTDCRDBUSOUT(21)", OutTemp => EXTDCRDBUSOUT_OUT(21), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(22), GlitchData => EXTDCRDBUSOUT22_GlitchData, OutSignalName => "EXTDCRDBUSOUT(22)", OutTemp => EXTDCRDBUSOUT_OUT(22), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(23), GlitchData => EXTDCRDBUSOUT23_GlitchData, OutSignalName => "EXTDCRDBUSOUT(23)", OutTemp => EXTDCRDBUSOUT_OUT(23), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(24), GlitchData => EXTDCRDBUSOUT24_GlitchData, OutSignalName => "EXTDCRDBUSOUT(24)", OutTemp => EXTDCRDBUSOUT_OUT(24), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(25), GlitchData => EXTDCRDBUSOUT25_GlitchData, OutSignalName => "EXTDCRDBUSOUT(25)", OutTemp => EXTDCRDBUSOUT_OUT(25), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(26), GlitchData => EXTDCRDBUSOUT26_GlitchData, OutSignalName => "EXTDCRDBUSOUT(26)", OutTemp => EXTDCRDBUSOUT_OUT(26), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(27), GlitchData => EXTDCRDBUSOUT27_GlitchData, OutSignalName => "EXTDCRDBUSOUT(27)", OutTemp => EXTDCRDBUSOUT_OUT(27), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(28), GlitchData => EXTDCRDBUSOUT28_GlitchData, OutSignalName => "EXTDCRDBUSOUT(28)", OutTemp => EXTDCRDBUSOUT_OUT(28), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(29), GlitchData => EXTDCRDBUSOUT29_GlitchData, OutSignalName => "EXTDCRDBUSOUT(29)", OutTemp => EXTDCRDBUSOUT_OUT(29), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(30), GlitchData => EXTDCRDBUSOUT30_GlitchData, OutSignalName => "EXTDCRDBUSOUT(30)", OutTemp => EXTDCRDBUSOUT_OUT(30), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EXTDCRDBUSOUT(31), GlitchData => EXTDCRDBUSOUT31_GlitchData, OutSignalName => "EXTDCRDBUSOUT(31)", OutTemp => EXTDCRDBUSOUT_OUT(31), Paths => (0 => (CPMDCRCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(8), GlitchData => ISOCMBRAMRDABUS8_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(8)", OutTemp => ISOCMBRAMRDABUS_OUT(8), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(9), GlitchData => ISOCMBRAMRDABUS9_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(9)", OutTemp => ISOCMBRAMRDABUS_OUT(9), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(10), GlitchData => ISOCMBRAMRDABUS10_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(10)", OutTemp => ISOCMBRAMRDABUS_OUT(10), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(11), GlitchData => ISOCMBRAMRDABUS11_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(11)", OutTemp => ISOCMBRAMRDABUS_OUT(11), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(12), GlitchData => ISOCMBRAMRDABUS12_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(12)", OutTemp => ISOCMBRAMRDABUS_OUT(12), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(13), GlitchData => ISOCMBRAMRDABUS13_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(13)", OutTemp => ISOCMBRAMRDABUS_OUT(13), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(14), GlitchData => ISOCMBRAMRDABUS14_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(14)", OutTemp => ISOCMBRAMRDABUS_OUT(14), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(15), GlitchData => ISOCMBRAMRDABUS15_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(15)", OutTemp => ISOCMBRAMRDABUS_OUT(15), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(16), GlitchData => ISOCMBRAMRDABUS16_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(16)", OutTemp => ISOCMBRAMRDABUS_OUT(16), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(17), GlitchData => ISOCMBRAMRDABUS17_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(17)", OutTemp => ISOCMBRAMRDABUS_OUT(17), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(18), GlitchData => ISOCMBRAMRDABUS18_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(18)", OutTemp => ISOCMBRAMRDABUS_OUT(18), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(19), GlitchData => ISOCMBRAMRDABUS19_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(19)", OutTemp => ISOCMBRAMRDABUS_OUT(19), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(20), GlitchData => ISOCMBRAMRDABUS20_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(20)", OutTemp => ISOCMBRAMRDABUS_OUT(20), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(21), GlitchData => ISOCMBRAMRDABUS21_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(21)", OutTemp => ISOCMBRAMRDABUS_OUT(21), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(22), GlitchData => ISOCMBRAMRDABUS22_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(22)", OutTemp => ISOCMBRAMRDABUS_OUT(22), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(23), GlitchData => ISOCMBRAMRDABUS23_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(23)", OutTemp => ISOCMBRAMRDABUS_OUT(23), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(24), GlitchData => ISOCMBRAMRDABUS24_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(24)", OutTemp => ISOCMBRAMRDABUS_OUT(24), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(25), GlitchData => ISOCMBRAMRDABUS25_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(25)", OutTemp => ISOCMBRAMRDABUS_OUT(25), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(26), GlitchData => ISOCMBRAMRDABUS26_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(26)", OutTemp => ISOCMBRAMRDABUS_OUT(26), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(27), GlitchData => ISOCMBRAMRDABUS27_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(27)", OutTemp => ISOCMBRAMRDABUS_OUT(27), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMRDABUS(28), GlitchData => ISOCMBRAMRDABUS28_GlitchData, OutSignalName => "ISOCMBRAMRDABUS(28)", OutTemp => ISOCMBRAMRDABUS_OUT(28), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(8), GlitchData => ISOCMBRAMWRABUS8_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(8)", OutTemp => ISOCMBRAMWRABUS_OUT(8), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(9), GlitchData => ISOCMBRAMWRABUS9_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(9)", OutTemp => ISOCMBRAMWRABUS_OUT(9), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(10), GlitchData => ISOCMBRAMWRABUS10_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(10)", OutTemp => ISOCMBRAMWRABUS_OUT(10), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(11), GlitchData => ISOCMBRAMWRABUS11_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(11)", OutTemp => ISOCMBRAMWRABUS_OUT(11), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(12), GlitchData => ISOCMBRAMWRABUS12_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(12)", OutTemp => ISOCMBRAMWRABUS_OUT(12), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(13), GlitchData => ISOCMBRAMWRABUS13_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(13)", OutTemp => ISOCMBRAMWRABUS_OUT(13), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(14), GlitchData => ISOCMBRAMWRABUS14_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(14)", OutTemp => ISOCMBRAMWRABUS_OUT(14), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(15), GlitchData => ISOCMBRAMWRABUS15_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(15)", OutTemp => ISOCMBRAMWRABUS_OUT(15), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(16), GlitchData => ISOCMBRAMWRABUS16_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(16)", OutTemp => ISOCMBRAMWRABUS_OUT(16), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(17), GlitchData => ISOCMBRAMWRABUS17_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(17)", OutTemp => ISOCMBRAMWRABUS_OUT(17), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(18), GlitchData => ISOCMBRAMWRABUS18_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(18)", OutTemp => ISOCMBRAMWRABUS_OUT(18), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(19), GlitchData => ISOCMBRAMWRABUS19_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(19)", OutTemp => ISOCMBRAMWRABUS_OUT(19), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(20), GlitchData => ISOCMBRAMWRABUS20_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(20)", OutTemp => ISOCMBRAMWRABUS_OUT(20), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(21), GlitchData => ISOCMBRAMWRABUS21_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(21)", OutTemp => ISOCMBRAMWRABUS_OUT(21), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(22), GlitchData => ISOCMBRAMWRABUS22_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(22)", OutTemp => ISOCMBRAMWRABUS_OUT(22), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(23), GlitchData => ISOCMBRAMWRABUS23_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(23)", OutTemp => ISOCMBRAMWRABUS_OUT(23), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(24), GlitchData => ISOCMBRAMWRABUS24_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(24)", OutTemp => ISOCMBRAMWRABUS_OUT(24), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(25), GlitchData => ISOCMBRAMWRABUS25_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(25)", OutTemp => ISOCMBRAMWRABUS_OUT(25), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(26), GlitchData => ISOCMBRAMWRABUS26_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(26)", OutTemp => ISOCMBRAMWRABUS_OUT(26), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(27), GlitchData => ISOCMBRAMWRABUS27_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(27)", OutTemp => ISOCMBRAMWRABUS_OUT(27), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRABUS(28), GlitchData => ISOCMBRAMWRABUS28_GlitchData, OutSignalName => "ISOCMBRAMWRABUS(28)", OutTemp => ISOCMBRAMWRABUS_OUT(28), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(0), GlitchData => ISOCMBRAMWRDBUS0_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(0)", OutTemp => ISOCMBRAMWRDBUS_OUT(0), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(1), GlitchData => ISOCMBRAMWRDBUS1_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(1)", OutTemp => ISOCMBRAMWRDBUS_OUT(1), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(2), GlitchData => ISOCMBRAMWRDBUS2_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(2)", OutTemp => ISOCMBRAMWRDBUS_OUT(2), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(3), GlitchData => ISOCMBRAMWRDBUS3_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(3)", OutTemp => ISOCMBRAMWRDBUS_OUT(3), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(4), GlitchData => ISOCMBRAMWRDBUS4_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(4)", OutTemp => ISOCMBRAMWRDBUS_OUT(4), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(5), GlitchData => ISOCMBRAMWRDBUS5_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(5)", OutTemp => ISOCMBRAMWRDBUS_OUT(5), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(6), GlitchData => ISOCMBRAMWRDBUS6_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(6)", OutTemp => ISOCMBRAMWRDBUS_OUT(6), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(7), GlitchData => ISOCMBRAMWRDBUS7_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(7)", OutTemp => ISOCMBRAMWRDBUS_OUT(7), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(8), GlitchData => ISOCMBRAMWRDBUS8_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(8)", OutTemp => ISOCMBRAMWRDBUS_OUT(8), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(9), GlitchData => ISOCMBRAMWRDBUS9_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(9)", OutTemp => ISOCMBRAMWRDBUS_OUT(9), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(10), GlitchData => ISOCMBRAMWRDBUS10_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(10)", OutTemp => ISOCMBRAMWRDBUS_OUT(10), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(11), GlitchData => ISOCMBRAMWRDBUS11_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(11)", OutTemp => ISOCMBRAMWRDBUS_OUT(11), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(12), GlitchData => ISOCMBRAMWRDBUS12_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(12)", OutTemp => ISOCMBRAMWRDBUS_OUT(12), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(13), GlitchData => ISOCMBRAMWRDBUS13_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(13)", OutTemp => ISOCMBRAMWRDBUS_OUT(13), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(14), GlitchData => ISOCMBRAMWRDBUS14_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(14)", OutTemp => ISOCMBRAMWRDBUS_OUT(14), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(15), GlitchData => ISOCMBRAMWRDBUS15_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(15)", OutTemp => ISOCMBRAMWRDBUS_OUT(15), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(16), GlitchData => ISOCMBRAMWRDBUS16_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(16)", OutTemp => ISOCMBRAMWRDBUS_OUT(16), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(17), GlitchData => ISOCMBRAMWRDBUS17_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(17)", OutTemp => ISOCMBRAMWRDBUS_OUT(17), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(18), GlitchData => ISOCMBRAMWRDBUS18_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(18)", OutTemp => ISOCMBRAMWRDBUS_OUT(18), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(19), GlitchData => ISOCMBRAMWRDBUS19_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(19)", OutTemp => ISOCMBRAMWRDBUS_OUT(19), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(20), GlitchData => ISOCMBRAMWRDBUS20_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(20)", OutTemp => ISOCMBRAMWRDBUS_OUT(20), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(21), GlitchData => ISOCMBRAMWRDBUS21_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(21)", OutTemp => ISOCMBRAMWRDBUS_OUT(21), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(22), GlitchData => ISOCMBRAMWRDBUS22_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(22)", OutTemp => ISOCMBRAMWRDBUS_OUT(22), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(23), GlitchData => ISOCMBRAMWRDBUS23_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(23)", OutTemp => ISOCMBRAMWRDBUS_OUT(23), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(24), GlitchData => ISOCMBRAMWRDBUS24_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(24)", OutTemp => ISOCMBRAMWRDBUS_OUT(24), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(25), GlitchData => ISOCMBRAMWRDBUS25_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(25)", OutTemp => ISOCMBRAMWRDBUS_OUT(25), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(26), GlitchData => ISOCMBRAMWRDBUS26_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(26)", OutTemp => ISOCMBRAMWRDBUS_OUT(26), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(27), GlitchData => ISOCMBRAMWRDBUS27_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(27)", OutTemp => ISOCMBRAMWRDBUS_OUT(27), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(28), GlitchData => ISOCMBRAMWRDBUS28_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(28)", OutTemp => ISOCMBRAMWRDBUS_OUT(28), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(29), GlitchData => ISOCMBRAMWRDBUS29_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(29)", OutTemp => ISOCMBRAMWRDBUS_OUT(29), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(30), GlitchData => ISOCMBRAMWRDBUS30_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(30)", OutTemp => ISOCMBRAMWRDBUS_OUT(30), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => ISOCMBRAMWRDBUS(31), GlitchData => ISOCMBRAMWRDBUS31_GlitchData, OutSignalName => "ISOCMBRAMWRDBUS(31)", OutTemp => ISOCMBRAMWRDBUS_OUT(31), Paths => (0 => (BRAMISOCMCLK_ipd_1'last_event, OUT_DELAY,TRUE)), DefaultDelay => OUT_DELAY, Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); -- Wait signal (input/output pins) wait on APUFCMDECODED_OUT, APUFCMDECUDI_OUT, APUFCMDECUDIVALID_OUT, APUFCMENDIAN_OUT, APUFCMFLUSH_OUT, APUFCMINSTRUCTION_OUT, APUFCMINSTRVALID_OUT, APUFCMLOADBYTEEN_OUT, APUFCMLOADDATA_OUT, APUFCMLOADDVALID_OUT, APUFCMOPERANDVALID_OUT, APUFCMRADATA_OUT, APUFCMRBDATA_OUT, APUFCMWRITEBACKOK_OUT, APUFCMXERCA_OUT, BRAMDSOCMCLK_ipd_1, BRAMDSOCMRDDBUS_ipd_1, BRAMISOCMCLK_ipd_1, BRAMISOCMDCRRDDBUS_ipd_1, BRAMISOCMRDDBUS_ipd_1, C405CPMCORESLEEPREQ_OUT, C405CPMMSRCE_OUT, C405CPMMSREE_OUT, C405CPMTIMERIRQ_OUT, C405CPMTIMERRESETREQ_OUT, C405DBGLOADDATAONAPUDBUS_OUT, C405DBGMSRWE_OUT, C405DBGSTOPACK_OUT, C405DBGWBCOMPLETE_OUT, C405DBGWBFULL_OUT, C405DBGWBIAR_OUT, C405JTGCAPTUREDR_OUT, C405JTGEXTEST_OUT, C405JTGPGMOUT_OUT, C405JTGSHIFTDR_OUT, C405JTGTDO_OUT, C405JTGTDOEN_OUT, C405JTGUPDATEDR_OUT, C405PLBDCUABORT_OUT, C405PLBDCUABUS_OUT, C405PLBDCUBE_OUT, C405PLBDCUCACHEABLE_OUT, C405PLBDCUGUARDED_OUT, C405PLBDCUPRIORITY_OUT, C405PLBDCUREQUEST_OUT, C405PLBDCURNW_OUT, C405PLBDCUSIZE2_OUT, C405PLBDCUU0ATTR_OUT, C405PLBDCUWRDBUS_OUT, C405PLBDCUWRITETHRU_OUT, C405PLBICUABORT_OUT, C405PLBICUABUS_OUT, C405PLBICUCACHEABLE_OUT, C405PLBICUPRIORITY_OUT, C405PLBICUREQUEST_OUT, C405PLBICUSIZE_OUT, C405PLBICUU0ATTR_OUT, C405RSTCHIPRESETREQ_OUT, C405RSTCORERESETREQ_OUT, C405RSTSYSRESETREQ_OUT, C405TRCCYCLE_OUT, C405TRCEVENEXECUTIONSTATUS_OUT, C405TRCODDEXECUTIONSTATUS_OUT, C405TRCTRACESTATUS_OUT, C405TRCTRIGGEREVENTOUT_OUT, C405TRCTRIGGEREVENTTYPE_OUT, C405XXXMACHINECHECK_OUT, CPMC405CLOCK_ipd_1, CPMC405CORECLKINACTIVE_ipd_1, CPMC405CPUCLKEN_ipd_1, CPMC405JTAGCLKEN_ipd_1, CPMC405SYNCBYPASS_ipd_1, CPMC405TIMERCLKEN_ipd_1, CPMC405TIMERTICK_ipd_1, CPMDCRCLK_ipd_1, CPMFCMCLK_ipd_1, DBGC405DEBUGHALT_ipd_1, DBGC405EXTBUSHOLDACK_ipd_1, DBGC405UNCONDDEBUGEVENT_ipd_1, DCREMACENABLER_OUT, DSARCVALUE_ipd_1, DSCNTLVALUE_ipd_1, DSOCMBRAMABUS_OUT, DSOCMBRAMBYTEWRITE_OUT, DSOCMBRAMEN_OUT, DSOCMBRAMWRDBUS_OUT, DSOCMBUSY_OUT, DSOCMRDADDRVALID_OUT, DSOCMRWCOMPLETE_ipd_1, DSOCMWRADDRVALID_OUT, EICC405CRITINPUTIRQ_ipd_1, EICC405EXTINPUTIRQ_ipd_1, EXTDCRABUS_OUT, EXTDCRACK_ipd_1, EXTDCRDBUSIN_ipd_1, EXTDCRDBUSOUT_OUT, EXTDCRREAD_OUT, EXTDCRWRITE_OUT, FCMAPUCR_ipd_1, FCMAPUDCDCREN_ipd_1, FCMAPUDCDFORCEALIGN_ipd_1, FCMAPUDCDFORCEBESTEERING_ipd_1, FCMAPUDCDFPUOP_ipd_1, FCMAPUDCDGPRWRITE_ipd_1, FCMAPUDCDLDSTBYTE_ipd_1, FCMAPUDCDLDSTDW_ipd_1, FCMAPUDCDLDSTHW_ipd_1, FCMAPUDCDLDSTQW_ipd_1, FCMAPUDCDLDSTWD_ipd_1, FCMAPUDCDLOAD_ipd_1, FCMAPUDCDPRIVOP_ipd_1, FCMAPUDCDRAEN_ipd_1, FCMAPUDCDRBEN_ipd_1, FCMAPUDCDSTORE_ipd_1, FCMAPUDCDTRAPBE_ipd_1, FCMAPUDCDTRAPLE_ipd_1, FCMAPUDCDUPDATE_ipd_1, FCMAPUDCDXERCAEN_ipd_1, FCMAPUDCDXEROVEN_ipd_1, FCMAPUDECODEBUSY_ipd_1, FCMAPUDONE_ipd_1, FCMAPUEXCEPTION_ipd_1, FCMAPUEXEBLOCKINGMCO_ipd_1, FCMAPUEXECRFIELD_ipd_1, FCMAPUEXENONBLOCKINGMCO_ipd_1, FCMAPUINSTRACK_ipd_1, FCMAPULOADWAIT_ipd_1, FCMAPURESULT_ipd_1, FCMAPURESULTVALID_ipd_1, FCMAPUSLEEPNOTREADY_ipd_1, FCMAPUXERCA_ipd_1, FCMAPUXEROV_ipd_1, ISARCVALUE_ipd_1, ISCNTLVALUE_ipd_1, ISOCMBRAMEN_OUT, ISOCMBRAMEVENWRITEEN_OUT, ISOCMBRAMODDWRITEEN_OUT, ISOCMBRAMRDABUS_OUT, ISOCMBRAMWRABUS_OUT, ISOCMBRAMWRDBUS_OUT, ISOCMDCRBRAMEVENEN_OUT, ISOCMDCRBRAMODDEN_OUT, ISOCMDCRBRAMRDSELECT_OUT, JTGC405BNDSCANTDO_ipd_1, JTGC405TCK_ipd_1, JTGC405TDI_ipd_1, JTGC405TMS_ipd_1, JTGC405TRSTNEG_ipd_1, MCBCPUCLKEN_ipd_1, MCBJTAGEN_ipd_1, MCBTIMEREN_ipd_1, MCPPCRST_ipd_1, PLBC405DCUADDRACK_ipd_1, PLBC405DCUBUSY_ipd_1, PLBC405DCUERR_ipd_1, PLBC405DCURDDACK_ipd_1, PLBC405DCURDDBUS_ipd_1, PLBC405DCURDWDADDR_ipd_1, PLBC405DCUSSIZE1_ipd_1, PLBC405DCUWRDACK_ipd_1, PLBC405ICUADDRACK_ipd_1, PLBC405ICUBUSY_ipd_1, PLBC405ICUERR_ipd_1, PLBC405ICURDDACK_ipd_1, PLBC405ICURDDBUS_ipd_1, PLBC405ICURDWDADDR_ipd_1, PLBC405ICUSSIZE1_ipd_1, PLBCLK_ipd_1, RSTC405RESETCHIP_ipd_1, RSTC405RESETCORE_ipd_1, RSTC405RESETSYS_ipd_1, TIEAPUCONTROL_ipd_1, TIEAPUUDI1_ipd_1, TIEAPUUDI2_ipd_1, TIEAPUUDI3_ipd_1, TIEAPUUDI4_ipd_1, TIEAPUUDI5_ipd_1, TIEAPUUDI6_ipd_1, TIEAPUUDI7_ipd_1, TIEAPUUDI8_ipd_1, TIEC405DETERMINISTICMULT_ipd_1, TIEC405DISOPERANDFWD_ipd_1, TIEC405MMUEN_ipd_1, TIEDCRADDR_ipd_1, TIEPVRBIT10_ipd_1, TIEPVRBIT11_ipd_1, TIEPVRBIT28_ipd_1, TIEPVRBIT29_ipd_1, TIEPVRBIT30_ipd_1, TIEPVRBIT31_ipd_1, TIEPVRBIT8_ipd_1, TIEPVRBIT9_ipd_1, TRCC405TRACEDISABLE_ipd_1, TRCC405TRIGGEREVENTIN_ipd_1, DCREMACWRITE_OUT, DCREMACREAD_OUT, DCREMACDBUS_OUT, DCREMACABUS_OUT, DCREMACCLK_OUT, EMACDCRDBUS_ipd_1, EMACDCRACK_ipd_1; end process TIMING; --C405PLBICUSIZE <= C405PLBICUSIZE_OUT after OUT_DELAY(tr01); DCREMACABUS <= DCREMACABUS_OUT; DCREMACCLK <= DCREMACCLK_OUT; DCREMACDBUS <= DCREMACDBUS_OUT; DCREMACENABLER <= DCREMACENABLER_OUT; DCREMACREAD <= DCREMACREAD_OUT; DCREMACWRITE <= DCREMACWRITE_OUT; --DSOCMBRAMABUS <= DSOCMBRAMABUS_OUT after OUT_DELAY(tr01); --ISOCMBRAMRDABUS <= ISOCMBRAMRDABUS_OUT after OUT_DELAY(tr01); --ISOCMBRAMWRABUS <= ISOCMBRAMWRABUS_OUT after OUT_DELAY(tr01); end PPC405_ADV_V;