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-- Company: 
-- Engineer:
--
-- Create Date:   20:01:25 05/22/2007
-- Design Name:   eval_fixed_ja
-- Module Name:   H:/vhdl/projects/eval_fixed_ja/ise/tb_eval_fixed_ja.vhd
-- Project Name:  eval_fixed
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: eval_fixed_ja
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_eval_fixed_ja_vhd IS
END tb_eval_fixed_ja_vhd;

ARCHITECTURE behavior OF tb_eval_fixed_ja_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT eval_fixed_ja
	PORT(
		srst : IN std_logic;
		clk : IN std_logic;
		di1 : IN std_logic_vector(7 downto 0);
		di2 : IN std_logic_vector(7 downto 0);
		in_valid : IN std_logic;          
		do : OUT std_logic_vector(7 downto 0);
		out_valid : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL srst :  std_logic := '1';
	SIGNAL clk :  std_logic := '0';
	SIGNAL in_valid :  std_logic := '0';
	SIGNAL di1 :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL di2 :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL do :  std_logic_vector(7 downto 0);
	SIGNAL out_valid :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: eval_fixed_ja PORT MAP(
		srst => srst,
		clk => clk,
		di1 => di1,
		di2 => di2,
		in_valid => in_valid,
		do => do,
		out_valid => out_valid
	);

	clk_gen : PROCESS
	BEGIN
		wait for 10 ns;
		clk <= not clk;
	END PROCESS;	

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;
		srst <= '0';
		di1 <= X"40";
		di2 <= X"20";
		
		wait for 20 ns;
		wait until rising_edge(clk);
		in_valid <= '1';
		wait until rising_edge(clk);
		in_valid <= '0';
		wait for 20 ns;
		

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;