include $(VHDL_MAKE_HOME)/defs.mk

MOD_PATH := $(LIB_PATH)/JBUS/memory

SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
SRCS += $(LIB_PATH)/rams/sim/src/dpram_1w1r1c_ra.vhd
SRCS += $(MOD_PATH)/src/ram_wb.vhd
SRCS += $(MOD_PATH)/src/tb_ram_wb.vhd

# Compile
TARGET := tb_ram_wb
ENTITY := tb_ram_wb
RUN_TIME := 1500ns
WAVE_FORMAT := vcd

include $(VHDL_MAKE_HOME)/ghdl.mk