------------------------------------------------------------------------- -- Project: SDRAM controller -- This file: Clock generator (Virtex-4 specific) -- -- Copyright (C) 2007 J. Ahrensfeld -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . -- -- For questions and ideas, please contact the author at jens@jayfield.org -- -------------------------------------------------------------------------- library ieee, work; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; USE WORK.utils_pkg.ALL; Library UNISIM; use UNISIM.vcomponents.all; entity clockgen is generic ( clk_in_freq : real := 100.0; cpu_clk_out_freq : real := 100.0; vga_clk_out_freq : real := 100.0; sdr0_clk_out_phaseshift : integer := 0; sdr1_clk_out_phaseshift : integer := 0 ); port ( -- Clocks and Reset rst_in : in std_logic; -- external async reset, low active clk_in : in std_logic; -- system clock (e.g. 100MHz), from board sys_clk_out : out std_logic; cpu_clk_out : out std_logic; vga_clk_out : out std_logic; sdr0_clk_fb_in : in std_logic; -- feedback clock sdr0_clk0_out : out std_logic; -- System clock #0, dcm#0 output 0° sdr0_clk270_out : out std_logic; -- System clock #0, dcm#0 output 270° sdr1_clk0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° sdr1_clk270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° sys_rst_out : out std_logic -- DCM locked status ); end; architecture tech of clockgen is signal dcm_rst : unsigned(2 downto 0); signal vga_clk0 : std_logic; signal vga_clkfx : std_logic; signal vga_clk0_bufg : std_logic; signal sys_clk0 : std_logic; signal sys_clk0_bufg : std_logic; signal cpu_clkfx : std_logic; signal cpu_clkfx_bufg : std_logic; signal sdr0_clk0 : std_logic; signal sdr0_clk270 : std_logic; signal sdr1_clk0 : std_logic; signal sdr1_clk270 : std_logic; signal sdr1_clk0_bufg : std_logic; signal reset_cnt : unsigned(4 downto 0); signal reset_pipe0 : unsigned(19 downto 0); signal reset_pipe1 : unsigned(19 downto 0); signal reset_pipe2 : unsigned(19 downto 0); signal vga_fx_lock : std_logic; signal sys_fx_lock : std_logic; signal sdr0_lock : std_logic; signal sdr1_lock : std_logic; begin ------------------------------------------------------------------------------------------------------- -- Clock generation ------------------------------------------------------------------------------------------------------- -- Compnent instantiation inst_DCM_VGA_FX : DCM_BASE generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, vga_clk_out_freq), -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, vga_clk_out_freq), -- Can be any integer from 2 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE ) port map ( CLK0 => vga_clk0, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => vga_clkfx, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => vga_fx_lock, -- DCM LOCK status output CLKFB => vga_clk0_bufg, -- DCM clock feedback CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM) RST => dcm_rst(0) -- DCM asynchronous reset input ); BUFG_vga_clk0 : BUFG port map ( O => vga_clk0_bufg, -- Clock buffer output I => vga_clk0 -- Clock buffer input ); BUFG_vga_clkfx : BUFG port map ( O => vga_clk_out, -- Clock buffer output I => vga_clkfx -- Clock buffer input ); -- Compnent instantiation inst_DCM_CPU_FX : DCM_BASE generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, cpu_clk_out_freq), -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, cpu_clk_out_freq), -- Can be any integer from 2 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE ) port map ( CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => cpu_clkfx, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => sys_fx_lock, -- DCM LOCK status output CLKFB => sys_clk0_bufg, -- DCM clock feedback CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM) RST => dcm_rst(0) -- DCM asynchronous reset input ); BUFG_sys_clk0 : BUFG port map ( O => sys_clk0_bufg, -- Clock buffer output I => sys_clk0 -- Clock buffer input ); BUFG_sys_clkfx : BUFG port map ( O => cpu_clkfx_bufg, -- Clock buffer output I => cpu_clkfx -- Clock buffer input ); sys_clk_out <= sys_clk0_bufg; cpu_clk_out <= cpu_clkfx_bufg; inst_DCM_SDRCLK_0 : DCM_BASE generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" PHASE_SHIFT => sdr0_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE ) port map ( CLK0 => sdr0_clk0, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => sdr0_clk270, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => sdr0_lock, -- DCM LOCK status output CLKFB => sdr0_clk_fb_in, -- DCM clock feedback CLKIN => sys_clk0_bufg, -- Clock input (from IBUFG, BUFG or DCM) RST => dcm_rst(1) -- DCM asynchronous reset input ); bufg_sdr0_clk0: bufg port map ( o => sdr0_clk0_out, i => sdr0_clk0 ); bufg_sdr0_clk270: bufg port map ( o => sdr0_clk270_out, i => sdr0_clk270 ); inst_DCM_SDRCLK_1 : DCM_BASE generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" PHASE_SHIFT => sdr1_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023 STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE ) port map ( CLK0 => sdr1_clk0, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => sdr1_clk270, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => sdr1_lock, -- DCM LOCK status output CLKFB => sdr1_clk0_bufg, -- DCM clock feedback CLKIN => sdr0_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) RST => dcm_rst(2) -- DCM asynchronous reset input ); sdr1_clk0_out <= sdr1_clk0_bufg; bufg_sdr1_clk0: bufg port map ( o => sdr1_clk0_bufg, i => sdr1_clk0 ); bufg_sdr1_clk270: bufg port map ( o => sdr1_clk270_out, i => sdr1_clk270 ); dcm_rst(0) <= reset_pipe0(reset_pipe0'left); dcm_reset0: process(rst_in, clk_in) begin if rst_in = '1' then reset_pipe0 <= (others => '1'); elsif rising_edge(clk_in) then reset_pipe0 <= reset_pipe0(reset_pipe0'left-1 downto 0) & '0'; end if; end process; dcm_rst(1) <= reset_pipe1(reset_pipe1'left); dcm_reset1: process(vga_fx_lock, clk_in) begin if vga_fx_lock = '0' then reset_pipe1 <= (others => '1'); elsif rising_edge(clk_in) then reset_pipe1 <= reset_pipe1(reset_pipe1'left-1 downto 0) & '0'; end if; end process; dcm_rst(2) <= reset_pipe2(reset_pipe2'left); dcm_reset2: process(sdr0_lock, clk_in) begin if sdr0_lock = '0' then reset_pipe2 <= (others => '1'); elsif rising_edge(clk_in) then reset_pipe2 <= reset_pipe2(reset_pipe2'left-1 downto 0) & '0'; end if; end process; reset_out_logic: process(rst_in, clk_in, sdr0_lock, sdr1_lock, sys_fx_lock, vga_fx_lock) begin if rst_in = '1' or sdr0_lock = '0' or sdr1_lock = '0' or sys_fx_lock = '0' or vga_fx_lock = '0' then sys_rst_out <= '1'; reset_cnt <= (reset_cnt'left downto reset_cnt'right => '1'); elsif rising_edge(clk_in) then if reset_cnt /= (reset_cnt'left downto reset_cnt'right => '0') then reset_cnt <= reset_cnt - 1; else sys_rst_out <= '0'; end if; end if; end process; end architecture tech;