$ version 1.1

# Signals in packages :

# Signals in entities :
/tb_mips_top/debug
/tb_mips_top/nmi
/tb_mips_top/rst
/tb_mips_top/clk
/tb_mips_top/eb
/tb_mips_top/ack_i
/tb_mips_top/srdy_i
/tb_mips_top/addr_o
/tb_mips_top/dat_i
/tb_mips_top/dat_o
/tb_mips_top/we_o
/tb_mips_top/sel_o
/tb_mips_top/cyc_o
/tb_mips_top/stb_o
/tb_mips_top/mrdy_o
/tb_mips_top/int
/tb_mips_top/cyc_i_rom
/tb_mips_top/ack_o_rom
/tb_mips_top/srdy_o_rom
/tb_mips_top/dat_o_rom
/tb_mips_top/cyc_i_flash
/tb_mips_top/ack_o_flash
/tb_mips_top/srdy_o_flash
/tb_mips_top/dat_o_flash
/tb_mips_top/cyc_i_sram
/tb_mips_top/ack_o_sram
/tb_mips_top/srdy_o_sram
/tb_mips_top/dat_o_sram
/tb_mips_top/cyc_i_gpio
/tb_mips_top/ack_o_gpio
/tb_mips_top/srdy_o_gpio
/tb_mips_top/dat_o_gpio
/tb_mips_top/cyc_i_uart
/tb_mips_top/ack_o_uart
/tb_mips_top/srdy_o_uart
/tb_mips_top/dat_o_uart
/tb_mips_top/flash_cs_n
/tb_mips_top/flash_we_n
/tb_mips_top/flash_oe_n
/tb_mips_top/flash_be_n
/tb_mips_top/sram_cs_n
/tb_mips_top/sram_be_n
/tb_mips_top/sram_wr_n
/tb_mips_top/sram_oe_n
/tb_mips_top/sram_a
/tb_mips_top/sram_d
/tb_mips_top/flash_a
/tb_mips_top/flash_d
/tb_mips_top/flash_page_mode_en
/tb_mips_top/gpi_0
/tb_mips_top/gpo_0
/tb_mips_top/int_timer
/tb_mips_top/int_uart
/tb_mips_top/rx
/tb_mips_top/tx
/tb_mips_top/mem_area
/tb_mips_top/sram_memory_content
/tb_mips_top/flash_memory_content
/tb_mips_top/uut/debug
/tb_mips_top/uut/eb
/tb_mips_top/uut/nmi
/tb_mips_top/uut/cpu_clk
/tb_mips_top/uut/rst_i
/tb_mips_top/uut/clk_i
/tb_mips_top/uut/ack_i
/tb_mips_top/uut/srdy_i
/tb_mips_top/uut/addr_o
/tb_mips_top/uut/dat_i
/tb_mips_top/uut/dat_o
/tb_mips_top/uut/we_o
/tb_mips_top/uut/sel_o
/tb_mips_top/uut/cyc_o
/tb_mips_top/uut/stb_o
/tb_mips_top/uut/mrdy_o
/tb_mips_top/uut/int
/tb_mips_top/uut/imem_err
/tb_mips_top/uut/imem_rdy
/tb_mips_top/uut/imem_en
/tb_mips_top/uut/imem_addr
/tb_mips_top/uut/imem_din
/tb_mips_top/uut/dmem_err
/tb_mips_top/uut/dmem_rdy
/tb_mips_top/uut/dmem_en
/tb_mips_top/uut/dmem_we
/tb_mips_top/uut/dmem_addr
/tb_mips_top/uut/dmem_dout
/tb_mips_top/uut/dmem_din
/tb_mips_top/uut/dmem_be
/tb_mips_top/uut/biu_rst
/tb_mips_top/uut/cpu_rst
/tb_mips_top/uut/cpu_run
/tb_mips_top/uut/pipe_cop_ir
/tb_mips_top/uut/pipe_cop_ir_en
/tb_mips_top/uut/pipe_cop_din
/tb_mips_top/uut/pipe_cop_dout
/tb_mips_top/uut/pipe_c0_ctrl_out
/tb_mips_top/uut/pipe_c0_ctrl_in
/tb_mips_top/uut/inst_pipeline/rst
/tb_mips_top/uut/inst_pipeline/clk
/tb_mips_top/uut/inst_pipeline/ce
/tb_mips_top/uut/inst_pipeline/imem_rdy
/tb_mips_top/uut/inst_pipeline/imem_en
/tb_mips_top/uut/inst_pipeline/imem_addr
/tb_mips_top/uut/inst_pipeline/imem_data
/tb_mips_top/uut/inst_pipeline/dmem_rdy
/tb_mips_top/uut/inst_pipeline/dmem_en
/tb_mips_top/uut/inst_pipeline/dmem_we
/tb_mips_top/uut/inst_pipeline/dmem_be
/tb_mips_top/uut/inst_pipeline/dmem_addr
/tb_mips_top/uut/inst_pipeline/dmem_din
/tb_mips_top/uut/inst_pipeline/dmem_dout
/tb_mips_top/uut/inst_pipeline/cop_ir
/tb_mips_top/uut/inst_pipeline/cop_ir_en
/tb_mips_top/uut/inst_pipeline/cop_din
/tb_mips_top/uut/inst_pipeline/cop_dout
/tb_mips_top/uut/inst_pipeline/c0_ctrl_out
/tb_mips_top/uut/inst_pipeline/c0_ctrl_in
/tb_mips_top/uut/inst_pipeline/id_stage
/tb_mips_top/uut/inst_pipeline/ex_stage
/tb_mips_top/uut/inst_pipeline/mem_stage
/tb_mips_top/uut/inst_pipeline/wb_stage
/tb_mips_top/uut/inst_pipeline/hdu
/tb_mips_top/uut/inst_pipeline/sdu
/tb_mips_top/uut/inst_pipeline/reg_a
/tb_mips_top/uut/inst_pipeline/reg_b
/tb_mips_top/uut/inst_pipeline/branch_taken
/tb_mips_top/uut/inst_pipeline/alu_result
/tb_mips_top/uut/inst_pipeline/mul_result
/tb_mips_top/uut/inst_pipeline/mul_busy
/tb_mips_top/uut/inst_pipeline/ex_events_instr
/tb_mips_top/uut/inst_pipeline/ex_events_alu
/tb_mips_top/uut/inst_pipeline/ex_events_mem
/tb_mips_top/uut/inst_pipeline/ex_events
/tb_mips_top/uut/inst_pipeline/mem_events
/tb_mips_top/uut/inst_pipeline/bcu_op_a
/tb_mips_top/uut/inst_pipeline/bcu_op_b
/tb_mips_top/uut/inst_pipeline/bcu_flags
/tb_mips_top/uut/inst_pipeline/vaddr
/tb_mips_top/uut/inst_pipeline/dmem_src
/tb_mips_top/uut/inst_pipeline/pc
/tb_mips_top/uut/inst_pipeline/pc_branch
/tb_mips_top/uut/inst_pipeline/pc_curr
/tb_mips_top/uut/inst_pipeline/pc_last
/tb_mips_top/uut/inst_pipeline/pc_nxt
/tb_mips_top/uut/inst_pipeline/pc_branch_take
/tb_mips_top/uut/inst_pipeline/id_ctrl_branch
/tb_mips_top/uut/inst_pipeline/ex_ctrl_branch
/tb_mips_top/uut/inst_pipeline/mem_ctrl_branch
/tb_mips_top/uut/inst_pipeline/sdu_id_stall
/tb_mips_top/uut/inst_pipeline/sdu_id_nop
/tb_mips_top/uut/inst_pipeline/c0_ctrl_in_exc_pending
/tb_mips_top/uut/inst_pipeline/c0_ctrl_in_exc_inject
/tb_mips_top/uut/inst_pipeline/inst_muldiv/rst
/tb_mips_top/uut/inst_pipeline/inst_muldiv/clk
/tb_mips_top/uut/inst_pipeline/inst_muldiv/hilo_we
/tb_mips_top/uut/inst_pipeline/inst_muldiv/din_hi
/tb_mips_top/uut/inst_pipeline/inst_muldiv/din_lo
/tb_mips_top/uut/inst_pipeline/inst_muldiv/mul_divn
/tb_mips_top/uut/inst_pipeline/inst_muldiv/start
/tb_mips_top/uut/inst_pipeline/inst_muldiv/s_un
/tb_mips_top/uut/inst_pipeline/inst_muldiv/hilo_sel
/tb_mips_top/uut/inst_pipeline/inst_muldiv/busy
/tb_mips_top/uut/inst_pipeline/inst_muldiv/dout
/tb_mips_top/uut/inst_pipeline/inst_muldiv/pprod
/tb_mips_top/uut/inst_pipeline/inst_muldiv/sign1
/tb_mips_top/uut/inst_pipeline/inst_muldiv/sign2
/tb_mips_top/uut/inst_pipeline/inst_muldiv/s1_r
/tb_mips_top/uut/inst_pipeline/inst_muldiv/s2_r
/tb_mips_top/uut/inst_pipeline/inst_muldiv/sr_r
/tb_mips_top/uut/inst_pipeline/inst_muldiv/cy
/tb_mips_top/uut/inst_pipeline/inst_muldiv/mul_start
/tb_mips_top/uut/inst_pipeline/inst_muldiv/mul_en
/tb_mips_top/uut/inst_pipeline/inst_muldiv/sum_en
/tb_mips_top/uut/inst_pipeline/inst_muldiv/pre_sum_vld
/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_reg
/tb_mips_top/uut/inst_pipeline/inst_muldiv/pre_const
/tb_mips_top/uut/inst_pipeline/inst_muldiv/result
/tb_mips_top/uut/inst_pipeline/inst_muldiv/add_op1
/tb_mips_top/uut/inst_pipeline/inst_muldiv/add_op2
/tb_mips_top/uut/inst_pipeline/inst_muldiv/add_res
/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_op1
/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_op2
/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_res
/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_cyi
/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_cyo
/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op1_r
/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op1
/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op2
/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op2_r
/tb_mips_top/uut/inst_pipeline/inst_muldiv/bsy
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_res
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_op1
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_op2
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_cyi
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_qbit
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_start
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_en
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_a
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_m
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_m_n
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_q
/tb_mips_top/uut/inst_pipeline/inst_muldiv/s
/tb_mips_top/uut/inst_pipeline/inst_muldiv/sn
/tb_mips_top/uut/inst_pipeline/inst_muldiv/cycle_cnt
/tb_mips_top/uut/inst_pipeline/inst_muldiv/cycle_cnt_preset
/tb_mips_top/uut/inst_pipeline/inst_muldiv/cycle_cnt_load
/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_fin_en
/tb_mips_top/uut/inst_pipeline/inst_reg_dual/clk_w
/tb_mips_top/uut/inst_pipeline/inst_reg_dual/we
/tb_mips_top/uut/inst_pipeline/inst_reg_dual/en
/tb_mips_top/uut/inst_pipeline/inst_reg_dual/wptr
/tb_mips_top/uut/inst_pipeline/inst_reg_dual/din
/tb_mips_top/uut/inst_pipeline/inst_reg_dual/rptr_a
/tb_mips_top/uut/inst_pipeline/inst_reg_dual/rptr_b
/tb_mips_top/uut/inst_pipeline/inst_reg_dual/dout_a
/tb_mips_top/uut/inst_pipeline/inst_reg_dual/dout_b
/tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem
/tb_mips_top/uut/inst_pipeline/inst_shifter/shift_ctrl
/tb_mips_top/uut/inst_pipeline/inst_shifter/din
/tb_mips_top/uut/inst_pipeline/inst_shifter/dout
/tb_mips_top/uut/inst_pipeline/inst_shifter/rot_data
/tb_mips_top/uut/inst_pipeline/inst_shifter/sa_rnd
/tb_mips_top/uut/inst_pipeline/inst_shifter/fill
/tb_mips_top/uut/inst_pipeline/inst_shifter/fill_mask
/tb_mips_top/uut/inst_pipeline/inst_shifter/fill_mask_addr
/tb_mips_top/uut/inst_pipeline/inst_shifter/dout_filled
/tb_mips_top/uut/inst_pipeline/inst_alu/op1_in
/tb_mips_top/uut/inst_pipeline/inst_alu/op2_in
/tb_mips_top/uut/inst_pipeline/inst_alu/op2_shifted
/tb_mips_top/uut/inst_pipeline/inst_alu/ctrl
/tb_mips_top/uut/inst_pipeline/inst_alu/result
/tb_mips_top/uut/inst_pipeline/inst_alu/flags
/tb_mips_top/uut/inst_pipeline/inst_alu/sum_res
/tb_mips_top/uut/inst_pipeline/inst_alu/and_res
/tb_mips_top/uut/inst_pipeline/inst_alu/xor_res
/tb_mips_top/uut/inst_pipeline/inst_alu/nor_res
/tb_mips_top/uut/inst_pipeline/inst_alu/or_res
/tb_mips_top/uut/inst_pipeline/inst_alu/eq
/tb_mips_top/uut/inst_pipeline/inst_alu/sa
/tb_mips_top/uut/inst_pipeline/inst_alu/sb
/tb_mips_top/uut/inst_pipeline/inst_alu/sr
/tb_mips_top/uut/inst_pipeline/inst_alu/c
/tb_mips_top/uut/inst_pipeline/inst_alu/lts
/tb_mips_top/uut/inst_pipeline/inst_alu/ltu
/tb_mips_top/uut/inst_pipeline/inst_bcu/op1_in
/tb_mips_top/uut/inst_pipeline/inst_bcu/op2_in
/tb_mips_top/uut/inst_pipeline/inst_bcu/flags
/tb_mips_top/uut/inst_cop/rst
/tb_mips_top/uut/inst_cop/clk
/tb_mips_top/uut/inst_cop/eb
/tb_mips_top/uut/inst_cop/int
/tb_mips_top/uut/inst_cop/nmi
/tb_mips_top/uut/inst_cop/ir_en
/tb_mips_top/uut/inst_cop/ir
/tb_mips_top/uut/inst_cop/ctrl_in
/tb_mips_top/uut/inst_cop/ctrl_out
/tb_mips_top/uut/inst_cop/din
/tb_mips_top/uut/inst_cop/dout
/tb_mips_top/uut/inst_cop/epc
/tb_mips_top/uut/inst_cop/cause
/tb_mips_top/uut/inst_cop/status
/tb_mips_top/uut/inst_cop/imem_addr
/tb_mips_top/uut/inst_cop/imem_addr_we
/tb_mips_top/uut/inst_cop/badvaddr
/tb_mips_top/uut/inst_cop/exc_code
/tb_mips_top/uut/inst_cop/test_reg
/tb_mips_top/uut/inst_cop/test_reg_we
/tb_mips_top/uut/inst_cop/stat_reg_we
/tb_mips_top/uut/inst_cop/epc_reg_we
/tb_mips_top/uut/inst_cop/code_reg_we
/tb_mips_top/uut/inst_cop/ip_reg_we
/tb_mips_top/uut/inst_cop/bd
/tb_mips_top/uut/inst_cop/sw_int
/tb_mips_top/uut/inst_cop/ip
/tb_mips_top/uut/inst_cop/im
/tb_mips_top/uut/inst_cop/status_save
/tb_mips_top/uut/inst_cop/status_rest
/tb_mips_top/uut/inst_cop/eflags
/tb_mips_top/uut/inst_cop/eb_reg
/tb_mips_top/uut/inst_cop/icache_info
/tb_mips_top/uut/inst_cop/dcache_info
/tb_mips_top/uut/inst_cop/reg_rptr
/tb_mips_top/uut/inst_cop/reg_wptr
/tb_mips_top/uut/inst_cop/inject_exc
/tb_mips_top/uut/inst_cop/latch_vect_en
/tb_mips_top/uut/inst_cop/int_nmi
/tb_mips_top/uut/inst_cop/nmi_asserted
/tb_mips_top/uut/inst_cop/cop_pipe_id
/tb_mips_top/uut/inst_cop/cop_pipe_ex
/tb_mips_top/uut/inst_cop/exc_state
/tb_mips_top/uut/inst_cop/exc_staten
/tb_mips_top/uut/inst_biu/rst_i
/tb_mips_top/uut/inst_biu/clk_i
/tb_mips_top/uut/inst_biu/ack_i
/tb_mips_top/uut/inst_biu/srdy_i
/tb_mips_top/uut/inst_biu/addr_o
/tb_mips_top/uut/inst_biu/dat_i
/tb_mips_top/uut/inst_biu/dat_o
/tb_mips_top/uut/inst_biu/we_o
/tb_mips_top/uut/inst_biu/sel_o
/tb_mips_top/uut/inst_biu/cyc_o
/tb_mips_top/uut/inst_biu/stb_o
/tb_mips_top/uut/inst_biu/mrdy_o
/tb_mips_top/uut/inst_biu/cop0_ctrl_in
/tb_mips_top/uut/inst_biu/cpu_clk
/tb_mips_top/uut/inst_biu/cpu_imem_err
/tb_mips_top/uut/inst_biu/cpu_imem_rdy
/tb_mips_top/uut/inst_biu/cpu_imem_en
/tb_mips_top/uut/inst_biu/cpu_imem_addr
/tb_mips_top/uut/inst_biu/cpu_imem_din
/tb_mips_top/uut/inst_biu/cpu_dmem_err
/tb_mips_top/uut/inst_biu/cpu_dmem_rdy
/tb_mips_top/uut/inst_biu/cpu_dmem_en
/tb_mips_top/uut/inst_biu/cpu_dmem_we
/tb_mips_top/uut/inst_biu/cpu_dmem_be
/tb_mips_top/uut/inst_biu/cpu_dmem_dout
/tb_mips_top/uut/inst_biu/cpu_dmem_din
/tb_mips_top/uut/inst_biu/cpu_dmem_addr
/tb_mips_top/uut/inst_biu/s
/tb_mips_top/uut/inst_biu/sn
/tb_mips_top/uut/inst_biu/bus_idle
/tb_mips_top/uut/inst_biu/busy
/tb_mips_top/uut/inst_biu/dmem_be
/tb_mips_top/uut/inst_biu/dcache_dout
/tb_mips_top/uut/inst_biu/dcache_mem_gnt
/tb_mips_top/uut/inst_biu/icache_mem_gnt
/tb_mips_top/uut/inst_biu/dmem_mem_wr_gnt
/tb_mips_top/uut/inst_biu/dmem_mem_rd_gnt
/tb_mips_top/uut/inst_biu/dcache_busy
/tb_mips_top/uut/inst_biu/icache_busy
/tb_mips_top/uut/inst_biu/cyc_o_icache
/tb_mips_top/uut/inst_biu/cyc_o_dcache
/tb_mips_top/uut/inst_biu/cyc_o_dmem_rd
/tb_mips_top/uut/inst_biu/cyc_o_dmem_wr
/tb_mips_top/uut/inst_biu/srdy_i_icache
/tb_mips_top/uut/inst_biu/srdy_i_dcache
/tb_mips_top/uut/inst_biu/mrdy_o_icache
/tb_mips_top/uut/inst_biu/mrdy_o_dcache
/tb_mips_top/uut/inst_biu/addr_o_icache
/tb_mips_top/uut/inst_biu/addr_o_dcache
/tb_mips_top/uut/inst_biu/addr_o_dmem_rd
/tb_mips_top/uut/inst_biu/addr_o_dmem_wr
/tb_mips_top/uut/inst_biu/stb_o_icache
/tb_mips_top/uut/inst_biu/stb_o_dcache
/tb_mips_top/uut/inst_biu/stb_o_dmem_rd
/tb_mips_top/uut/inst_biu/stb_o_dmem_wr
/tb_mips_top/uut/inst_biu/dat_i_dmem_rd
/tb_mips_top/uut/inst_biu/dat_o_dmem_wr
/tb_mips_top/uut/inst_biu/sel_o_dmem_wr
/tb_mips_top/uut/inst_biu/sel_o_dmem_rd
/tb_mips_top/uut/inst_biu/dcached
/tb_mips_top/uut/inst_biu/dcache_en2
/tb_mips_top/uut/inst_biu/dcache_en
/tb_mips_top/uut/inst_biu/uncached_access
/tb_mips_top/uut/inst_biu/ack
/tb_mips_top/uut/inst_biu/dat
/tb_mips_top/uut/inst_biu/bus_timeout_cnt
/tb_mips_top/uut/inst_biu/bus_timeout
/tb_mips_top/uut/inst_biu/bout_fifo_din
/tb_mips_top/uut/inst_biu/bout_fifo_dout
/tb_mips_top/uut/inst_biu/bout_fifo_re
/tb_mips_top/uut/inst_biu/bout_fifo_we
/tb_mips_top/uut/inst_biu/bout_fifo_full
/tb_mips_top/uut/inst_biu/bout_fifo_empty
/tb_mips_top/uut/inst_biu/bout_rdy
/tb_mips_top/uut/inst_biu/bin_fifo_din
/tb_mips_top/uut/inst_biu/bin_fifo_dout
/tb_mips_top/uut/inst_biu/bin_fifo_re
/tb_mips_top/uut/inst_biu/bin_fifo_we
/tb_mips_top/uut/inst_biu/bin_fifo_full
/tb_mips_top/uut/inst_biu/bin_fifo_empty
/tb_mips_top/uut/inst_biu/write_fifo_din
/tb_mips_top/uut/inst_biu/write_fifo_dout
/tb_mips_top/uut/inst_biu/write_fifo_re
/tb_mips_top/uut/inst_biu/write_fifo_we
/tb_mips_top/uut/inst_biu/write_fifo_full
/tb_mips_top/uut/inst_biu/write_fifo_empty
/tb_mips_top/uut/inst_biu/read_cycle
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