#
#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
#     FOR A PARTICULAR PURPOSE.
#     
#     (c) Copyright 2005 Xilinx, Inc.
#     All rights reserved.
#

# Bus clock nets
NET sys_clk_in TNM_NET = "sys_clk_in";
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;

NET sys_clk_in LOC = AE14;
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET sys_rst_in LOC = D6;
NET sys_rst_in PULLUP;
NET sys_rst_in TIG;

////////////////////////////////////////////////////////////////////////////
// Buttons, LEDs, and DIP Switches 
////////////////////////////////////////////////////////////////////////////

# North-East-South-West-Center LEDs
NET led<0>  LOC = C6;  # C LED
NET led<1>  LOC = F9;  # W LED
NET led<2>  LOC = A5;  # S LED
NET led<3>  LOC = E10; # E LED
NET led<4>  LOC = E2;  # N LED
# North-East-South-West-Center Buttons
NET btn<0>  LOC = B6;  # C Button
NET btn<1> LOC = E9;  # W Button
NET btn<2> LOC = A6;  # S Button
NET btn<3> LOC = F10; # E Button
NET btn<4> LOC = E7;  # N Button

NET "led<*>" TIG;
NET "led<*>" SLEW = SLOW;
NET "led<*>" DRIVE = 2;

NET "btn<*>" TIG;
NET "btn<*>" SLEW = SLOW;