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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:29:16 02/12/2010 
-- Design Name: 
-- Module Name:    eval_asyn_fifo - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity eval_asyn_fifo is
    Port (
    		din : in  unsigned (31 downto 0);
           dout : out  unsigned (31 downto 0);
           rst : in  STD_LOGIC;
           clk_w : in  STD_LOGIC;
           clk_r : in  STD_LOGIC;
           full : out  STD_LOGIC;
           empty : out  STD_LOGIC;
           read : in  STD_LOGIC;
           write : in  STD_LOGIC);
end eval_asyn_fifo;

architecture Behavioral of eval_asyn_fifo is

	signal read0	: std_logic;
	signal empty0	: std_logic;
	signal write1	: std_logic;
	signal full1	: std_logic;
	signal dout0	: unsigned (31 downto 0);

begin

	read0	<= not full1;
	write1	<= not empty0;
	
	uut0: entity work.fifo_async
	GENERIC MAP
	(
		addr_width			=> 4,
		data_width			=> 32,
		almost_full_thresh	=> 6,
		almost_empty_thresh	=> 2,
		allow_full_writes	=> false,
		allow_empty_reads	=> false,
		do_last_read_update	=> true
	)
	PORT MAP
	(
		rst			=>	rst,
		clk_w		=>	clk_w,
		clk_r		=>	clk_r,
		we			=>	write,
		re			=>	read0,
		data_w		=>	din,
		data_r		=>	dout0,
		fifo_full	=>	full,
		fifo_empty	=>	empty0,
		fifo_afull	=>	open,
		fifo_aempty	=>	open

	);

	uut1: entity work.fifo_sync
	GENERIC MAP
	(
		addr_width			=> 10,
		data_width			=> 32,
		almost_full_thresh	=> 6,
		almost_empty_thresh	=> 2,
		allow_full_writes	=> false,
		allow_empty_reads	=> false,
		do_last_read_update	=> true
	)
	PORT MAP
	(
		rst			=>	rst,
		clk			=>	clk_r,
		we			=>	write1,
		re			=>	read,
		data_w		=>	dout0,
		data_r		=>	dout,
		fifo_full	=>	full1,
		fifo_empty	=>	empty,
		fifo_afull	=>	open,
		fifo_aempty	=>	open

	);

end Behavioral;