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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:55:59 09/18/2007 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

LIBRARY WORK;
USE WORK.FIFO_CTRL_PKG.ALL;

entity top is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           ce : in  STD_LOGIC;
           gcnt : out  unsigned (13 downto 0);
           bcnt : out  unsigned (13 downto 0);
           gnxt : out  unsigned (13 downto 0);
           bnxt : out  unsigned (13 downto 0)
		  );
end top;

architecture Behavioral of top is

begin
		
inst_gray_counter : entity work.gray_counter
	generic map (width => 14)
	port map (
		rst			=> rst,
		clk			=> clk,
		ce			=> ce, 
		bcnt		=> bcnt,
		bnxt		=> bnxt,
		gcnt		=> gcnt,
		gnxt		=> gnxt
	);
		
end Behavioral;