--------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: JIPS top file 
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

library work;
use work.mips_types.all;

entity mips_top_netlist is
	Generic
	(
		icache_size			: natural := 8192;	-- words
		icache_line			: natural := 8;		-- words
		dcache_size			: natural := 4096;	-- words
		dcache_line			: natural := 8;		-- words
		WITH_TLB			: boolean := true;
		TRANSLATE_KSEG0_1	: boolean := true
	);
	Port
	(
		debug		: out unsigned(1 downto 0);
		eb			: in  STD_LOGIC;
		nmi			: in  STD_LOGIC;
		cpu_clk		: in  STD_LOGIC;
		RST_I		: in  STD_LOGIC;
		CLK_I		: in  STD_LOGIC;
		ACK_I		: in  STD_LOGIC;
		SRDY_I		: in  STD_LOGIC;
		ADDR_O		: out unsigned(31 downto 0);
		DAT_I		: in  unsigned(31 downto 0);
		DAT_O		: out unsigned(31 downto 0);
		WE_O		: out STD_LOGIC;
		SEL_O		: out unsigned(3 downto 0);
		CYC_O		: out STD_LOGIC;
		STB_O		: out STD_LOGIC;
		MRDY_O		: out STD_LOGIC;
		INT			: in  unsigned (5 downto 0)
	);
	
end mips_top_netlist;

architecture rtl of mips_top_netlist is

	signal chip_debug					: chip_debug_t;
	
begin

	debug(0)	<= chip_debug.imem_err;
	debug(1)	<= chip_debug.dmem_err;
	
inst_mips_top: entity work.mips_top
	GENERIC MAP
	(
		icache_size			=> icache_size,		-- words
		icache_line			=> icache_line,		-- words
		dcache_size			=> dcache_size,		-- words
		dcache_line			=> dcache_line,		-- words
		WITH_TLB			=> WITH_TLB,
		TRANSLATE_KSEG0_1	=> TRANSLATE_KSEG0_1
	)
	PORT MAP
	(
		debug			=> chip_debug,
		eb				=> eb,
		cpu_clk			=> cpu_clk,
		RST_I			=> RST_I,
		CLK_I			=> CLK_I,
		ACK_I			=> ACK_I,
		SRDY_I			=> SRDY_I,
		ADDR_O			=> ADDR_O,
		DAT_I			=> DAT_I,
		DAT_O			=> DAT_O,
		WE_O			=> WE_O,
		SEL_O			=> SEL_O,
		CYC_O			=> CYC_O,
		STB_O			=> STB_O,
		MRDY_O			=> MRDY_O,
		INT				=> INT,
		nmi				=> nmi
	);

end rtl;