## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model
vcom -explicit  -93 "../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
vcom -explicit  -93 "../src/systest/ddr_sdr_conf_pkg.vhd"
vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_2/src/mt46v16m16.vhd"
vcom   -93 "../ise91/systest/netgen/translate/systest_translate.vhd"
vcom   -93 "../src/systest/tb_systest.vhd"
vsim -t 1ps  -lib work tb_systest
#do {tb_systest.wdo}
view wave
add wave *
view structure
view signals
run 5us
## End