-------------------------------------------------------------------------
-- Project: Dual-Port RAM with 1 clock latency for simulation
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address

-- Copyright (C) 2007 J. Ahrensfeld

-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.

-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- Lesser General Public License for more details.

-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA

-- For questions and ideas, please contact the author at jens@jayfield.org

-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
-----------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

entity dpram_1w1r1c_ra is
	Generic
	(
		addr_width : integer := 3;
		data_width : integer := 8
	);
	Port 
	(
		clk		: in  STD_LOGIC;
		we_a		: in  STD_LOGIC;
		re_b		: in  STD_LOGIC;
		addr_a	: in  unsigned (addr_width-1 downto 0);
		addr_b	: in  unsigned (addr_width-1 downto 0);
		din_a		: in  unsigned (data_width-1 downto 0);
		dout_b	: out unsigned (data_width-1 downto 0)
	);
end dpram_1w1r1c_ra;

architecture Behavioral of dpram_1w1r1c_ra is


TYPE MEM IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
SIGNAL ram_block: MEM;

BEGIN
	PROCESS (clk)
	BEGIN
	IF (clk'event AND clk = '1') THEN
		IF (we_a = '1') THEN
			ram_block(to_integer(addr_a)) <= din_a;
		END IF;
		IF (re_b = '1') THEN
			dout_b <= ram_block(to_integer(addr_b));
		END IF;
		-- VHDL semantics imply that q doesn't get data
		-- in this clock cycle
		END IF;
	END PROCESS;

end Behavioral;