library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main_top is
    Port ( res : in std_logic;
	        clki : in std_logic;
			  clko : out std_logic;
           di : in std_logic;
           do : out std_logic);
end main_top;

architecture Behavioral of main_top is

type state_type is (idle, active, release);
signal state, nextstate : state_type;
signal clk : std_logic;
shared variable test : std_logic;

   component BUFG
         port (I: in std_logic; O: out std_logic);
   end component;   
    
--**Insert the following after the 'begin' keyword**   
 

begin
--U1:  BUFG port map (I => clki, O => clk);

clk <= clki;

process (res, clk, di, state)
begin
  if (res = '1') then
  clko <= '0';
  else
  	 clko <= '1';
    case state is

	 when idle =>
	   if (di = '1') then
		  nextstate <= active;
		else
		  nextstate <= idle;
		end if;

	 when active =>
	   if (di = '1') then
		  nextstate <= active;
		else
		  nextstate <= idle;
		end if;

	 when release =>
		  nextstate <= idle;

	 end case;
  end if;
end process;

process (res, clk, state)
begin
  if (res = '1') then
    do   <= '0';
  else

    do   <= '0';
    case state is
	 when active =>
      do   <= '1';

	 when others =>
    end case;
  end if;
end process;

process (res, clk)
begin
  if (res = '1') then
    state <= idle;
  elsif clk'event and clk = '1' then
    state <= nextstate;
  end if;
end process;

end Behavioral;