#
#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
#     FOR A PARTICULAR PURPOSE.
#
#     (c) Copyright 2005 Xilinx, Inc.
#     All rights reserved.
#

CONFIG STEPPING = "ES";

# Bus clock nets
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %;

NET "inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;

NET "sys_clk_in" LOC = "AE14";
#NET sys_clk_in IOSTANDARD = LVCMOS33;
NET "sys_rst_n_in" LOC = "D6";
NET sys_rst_n_in PULLUP;
NET "sys_rst_n_in" TIG;
NET "rst" TIG;

# Locate DCM/BUFG - Tools can probably figure them out automatically
#                   but just LOC them down to be safe
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;

////////////////////////////////////////////////////////////////////////////
// Misc Board Signals
////////////////////////////////////////////////////////////////////////////

NET sys_error<0> LOC = V6;
NET sys_error<1> LOC = L24;
#NET sys_error<*> IOSTANDARD = LVCMOS33;
NET sys_error<*> DRIVE = 2;
NET sys_error<*> TIG;

////////////////////////////////////////////////////////////////////////////
// RS-232
////////////////////////////////////////////////////////////////////////////
NET sys_rx LOC = W2;
#NET sys_rx IOSTANDARD = LVCMOS33;
NET sys_rx TIG;
NET "sys_tx" LOC = "W1";
#NET sys_tx IOSTANDARD = LVCMOS33;
NET "sys_tx" TIG;

////////////////////////////////////////////////////////////////////////////
// Buttons, LEDs, and DIP Switches
////////////////////////////////////////////////////////////////////////////
# GPLED 0-3
NET "sys_led<0>" LOC = "G5"; #GPLED0
NET "sys_led<1>" LOC = "G6"; #GPLED1
NET "sys_led<2>" LOC = "A11"; #GPLED2
NET "sys_led<3>" LOC = "A12"; #GPLED3
# North-East-South-West-Center LEDs
NET "sys_led<4>" LOC = "F9"; # W LED
NET "sys_led<5>" LOC = "E2"; # N LED
NET "sys_led<6>" LOC = "E10"; # E LED
NET "sys_led<7>" LOC = "A5"; # S LED
NET "sys_led<8>" LOC = "C6"; # C LED
NET "sys_led<*>" TIG;
NET "sys_led<*>" SLEW = SLOW;
NET "sys_led<*>" DRIVE = 2;
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
# North-East-South-West-Center Buttons
NET "sys_btn<0>" LOC = "E9"; # W Button
NET "sys_btn<1>" LOC = "E7"; # N Button
NET "sys_btn<2>" LOC = "F10"; # E Button
NET "sys_btn<3>" LOC = "A6"; # S Button
NET "sys_btn<4>" LOC = "B6"; # C Button
NET "sys_btn<*>" TIG;
NET "sys_btn<*>" PULLDOWN;
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
# Dip Switches 1-8
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
NET "sys_dip<*>" PULLDOWN;
#NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
NET "sys_dip<*>" TIG;
////////////////////////////////////////////////////////////////////////////
// LCD
////////////////////////////////////////////////////////////////////////////
NET sys_lcd_e LOC = AE13; # LCD_E
#NET sys_lcd_e IOSTANDARD = LVCMOS33;
NET sys_lcd_e SLEW = SLOW;
NET sys_lcd_e DRIVE = 2;
NET sys_lcd_e TIG;
NET sys_lcd_rs LOC = AC17; # LCD_RS
#NET sys_lcd_rs IOSTANDARD = LVCMOS33;
NET sys_lcd_rs SLEW = SLOW;
NET sys_lcd_rs DRIVE = 2;
NET sys_lcd_rs TIG;
NET sys_lcd_rw LOC = AB17; # LCD_RW
#NET sys_lcd_rw IOSTANDARD = LVCMOS33;
NET sys_lcd_rw SLEW = SLOW;
NET sys_lcd_rw DRIVE = 2;
NET sys_lcd_rw TIG;
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
#NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
NET sys_lcd_d<*> SLEW = SLOW;
NET sys_lcd_d<*> DRIVE = 2;
NET sys_lcd_d<*> PULLDOWN;
NET sys_lcd_d<*> TIG;

#------------------------------------------------------------------------------
# IO Pad Location Constraints / Properties for DDR Controllers
#------------------------------------------------------------------------------

NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N

NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N

NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3

NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3

NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
NET sys_sdr_data<10>	LOC = C23; # DDR_D10
NET sys_sdr_data<11>	LOC = C24; # DDR_D11
NET sys_sdr_data<12>	LOC = A20; # DDR_D12
NET sys_sdr_data<13>	LOC = A21; # DDR_D13
NET sys_sdr_data<14>	LOC = D24; # DDR_D14
NET sys_sdr_data<15>	LOC = E18; # DDR_D15
NET sys_sdr_data<16>	LOC = F18; # DDR_D16
NET sys_sdr_data<17>	LOC = A19; # DDR_D17
NET sys_sdr_data<18>	LOC = F19; # DDR_D18
NET sys_sdr_data<19>	LOC = B23; # DDR_D19
NET sys_sdr_data<20>	LOC = E21; # DDR_D20
NET sys_sdr_data<21>	LOC = D22; # DDR_D21
NET sys_sdr_data<22>	LOC = D23; # DDR_D22
NET sys_sdr_data<23>	LOC = B24; # DDR_D23
NET sys_sdr_data<24>	LOC = E22; # DDR_D24
NET sys_sdr_data<25>	LOC = F20; # DDR_D25
NET sys_sdr_data<26>	LOC = H23; # DDR_D26
NET sys_sdr_data<27>	LOC = G25; # DDR_D27
NET sys_sdr_data<28>	LOC = G26; # DDR_D28
NET sys_sdr_data<29>	LOC = H25; # DDR_D29
NET sys_sdr_data<30>	LOC = H24; # DDR_D30
NET sys_sdr_data<31>	LOC = H21; # DDR_D31

NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
NET sys_sdr_a_q<*>	FAST; 

NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
NET sys_sdr_ba_q<*>	FAST; 

NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
NET sys_sdr_cas_qn	FAST; 

NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
NET sys_sdr_cke_q		FAST; 

NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
NET sys_sdr_clk_p		FAST; 
NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
NET sys_sdr_clk_fb	IOBDELAY = NONE; 
NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
NET sys_sdr_clk_n		FAST; 

NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
NET sys_sdr_cas_qn	FAST; 

NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
NET sys_sdr_cs_qn		FAST; 

NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
NET sys_sdr_ras_qn	FAST; 

NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
NET sys_sdr_we_qn		FAST; 

NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
NET sys_sdr_dqs_q<*>	FAST; 

NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
NET sys_sdr_dm_q<*>	FAST; 

NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
NET sys_sdr_data<*>	IOBDELAY = NONE; 
NET sys_sdr_data<*>	FAST; 

#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";


# Timing Constraint for DDR Feedback Clock
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;

#------------------------------------------------------------------------------
# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
#------------------------------------------------------------------------------

NET sys_vga_blue<0> LOC = M21; # VGA_B0
NET sys_vga_blue<1> LOC = M26; # VGA_B1
NET sys_vga_blue<2> LOC = L26; # VGA_B2
NET sys_vga_blue<3> LOC = C5;  # VGA_B3
NET sys_vga_blue<4> LOC = C7;  # VGA_B4
NET sys_vga_blue<5> LOC = B7;  # VGA_B5
NET sys_vga_blue<6> LOC = G8;  # VGA_B6
NET sys_vga_blue<7> LOC = F8;  # VGA_B7
#NET sys_vga_blue<*> IOSTANDARD = LVCMOS33;
NET sys_vga_blue<*> SLEW = FAST;
NET sys_vga_blue<*> DRIVE = 8;

NET sys_vga_clk  LOC = AF8;
NET sys_vga_clk  IOSTANDARD = LVDCI_25;
NET sys_vga_clk  SLEW = FAST;
NET sys_vga_clk  DRIVE = 8;

NET sys_vga_green<0> LOC = M22; # VGA_G0
NET sys_vga_green<1> LOC = M23; # VGA_G1
NET sys_vga_green<2> LOC = M20; # VGA_G2
NET sys_vga_green<3> LOC = E4;  # VGA_G3
NET sys_vga_green<4> LOC = D3;  # VGA_G4
NET sys_vga_green<5> LOC = H7;  # VGA_G5
NET sys_vga_green<6> LOC = H8;  # VGA_G6
NET sys_vga_green<7> LOC = C1;  # VGA_G7
#NET sys_vga_green<*> IOSTANDARD = LVCMOS33;
NET sys_vga_green<*> SLEW = FAST;
NET sys_vga_green<*> DRIVE = 8;

NET sys_vga_hsync LOC = C10;
NET sys_vga_hsync SLEW = FAST;
NET sys_vga_hsync DRIVE = 8;
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;

NET sys_vga_red<0> LOC = N23; #VGA_R0
NET sys_vga_red<1> LOC = N24; #VGA_R1
NET sys_vga_red<2> LOC = N25; #VGA_R2
NET sys_vga_red<3> LOC = C2;  #VGA_R3
NET sys_vga_red<4> LOC = G7;  #VGA_R4
NET sys_vga_red<5> LOC = F7;  #VGA_R5
NET sys_vga_red<6> LOC = E5;  #VGA_R6
NET sys_vga_red<7> LOC = E6;  #VGA_R7
#NET sys_vga_red<*> IOSTANDARD = LVCMOS33;
NET sys_vga_red<*> SLEW = FAST;
NET sys_vga_red<*> DRIVE = 8;

NET sys_vga_vsync LOC = A8;
NET sys_vga_vsync SLEW = FAST;
NET sys_vga_vsync DRIVE = 8;
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;

NET sys_vga_blank_n LOC = M24;
NET sys_vga_blank_n SLEW = FAST;
NET sys_vga_blank_n DRIVE = 8;
#NET sys_vga_blank_n IOSTANDARD = LVCMOS33;

NET sys_vga_sync_n LOC = L23;
NET sys_vga_sync_n SLEW = FAST;
NET sys_vga_sync_n DRIVE = 8;
#NET sys_vga_sync_n IOSTANDARD = LVCMOS33;

#------------------------------------------------------------------------------
# IO Pad Location Constraints / Properties for PS/2 Ports
#------------------------------------------------------------------------------

#Keyboard
NET sys_keyb_clk  LOC = D2;
NET sys_keyb_clk  SLEW = SLOW;
NET sys_keyb_clk  DRIVE = 2;
NET sys_keyb_clk  TIG;
NET sys_keyb_data LOC = G9;
NET sys_keyb_data SLEW = SLOW;
NET sys_keyb_data DRIVE = 2;
NET sys_keyb_data TIG;

#Mouse
NET sys_mouse_clk  LOC = B14;
NET sys_mouse_clk  SLEW = SLOW;
NET sys_mouse_clk  DRIVE = 2;
NET sys_mouse_clk  TIG;
NET sys_mouse_data LOC = C14;
NET sys_mouse_data SLEW = SLOW;
NET sys_mouse_data DRIVE = 2;
NET sys_mouse_data TIG;