------------------------------------------------------------------------------- -- Copyright (c) 1995/2006 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Multi-Gigabit Transceiver -- /___/ /\ Filename : gtp_dual.vhd -- \ \ / \ Timestamp : Thu Dec 8 2005 -- \___\/\___\ -- -- Revision: -- 12/08/05 - Initial version. -- 01/09/06 - Added architecture -- 01/27/06 - Updated ONE_UI[10:0] to ONE_UI[31:0] -- CR#22431 - Remove GSR pin -- 02/23/06 - Updated Header -- 03/29/06 - CR#226744 - Fixed output connectivity. -- 03/29/06 - CR#225541 - Updated GTP_DUAL smartmodel version to 0.006 for following updates -- - GTP_DUAL smartmodel not generating DO output on the DRP port properly -- - Renamed some of the ports. -- - Removed some of the attributes. -- - Renamed some of the attributes. -- 04/24/06 - CR#230306 - CLKIN => REFCLKOUT delay added -- 04/27/06 - CR#230648 - REFCLKOUT removed from wait on -- - CR#230642 - Spreadsheet updates for I.31 -- 05/22/06 - CR#231412 - SIM_RECEIVER_DETECT_PASS0/1 attributes added -- 05/23/06 - CR#231962 - Add buffers for connectivity -- 10/26/06 - - replaced ZERO_DELAY with CLK_DELAY to be consistent with writers (PPC440 update) -- - PBS_ERR_THRESHOLD_0 default value X"11111111" to X"00000001 -- 05/23/07 - CR#439780 - Default attribute value change - PMA_CDR_SCAN0/1, PMA_RX_CFG_0/1, TX_DIFF_BOOST_0/1 -- - PCS_COM_CFG is a user visible attribute -- 05/23/07 - CR#440008 - Specify block timing update - RXCHBONDO0/1 synchronous to RXUSRCLK0, RXCHBONDI0/1 synchronous to RXUSRCLK1 -- 02/21/08 - CR#467686 - Add SIM_MODE attribute with values LEGACY & FAST model -- 06/24/08 - CR472608, CR472665 - Update SIM_MODE default to FAST -- End Revision ----- CELL GTP_DUAL ----- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; library secureip; use secureip.all; entity GTP_DUAL is generic ( AC_CAP_DIS_0 : boolean := TRUE; AC_CAP_DIS_1 : boolean := TRUE; ALIGN_COMMA_WORD_0 : integer := 1; ALIGN_COMMA_WORD_1 : integer := 1; CHAN_BOND_1_MAX_SKEW_0 : integer := 7; CHAN_BOND_1_MAX_SKEW_1 : integer := 7; CHAN_BOND_2_MAX_SKEW_0 : integer := 1; CHAN_BOND_2_MAX_SKEW_1 : integer := 1; CHAN_BOND_LEVEL_0 : integer := 0; CHAN_BOND_LEVEL_1 : integer := 0; CHAN_BOND_MODE_0 : string := "OFF"; CHAN_BOND_MODE_1 : string := "OFF"; CHAN_BOND_SEQ_1_1_0 : bit_vector := "0001001010"; CHAN_BOND_SEQ_1_1_1 : bit_vector := "0001001010"; CHAN_BOND_SEQ_1_2_0 : bit_vector := "0001001010"; CHAN_BOND_SEQ_1_2_1 : bit_vector := "0001001010"; CHAN_BOND_SEQ_1_3_0 : bit_vector := "0001001010"; CHAN_BOND_SEQ_1_3_1 : bit_vector := "0001001010"; CHAN_BOND_SEQ_1_4_0 : bit_vector := "0110111100"; CHAN_BOND_SEQ_1_4_1 : bit_vector := "0110111100"; CHAN_BOND_SEQ_1_ENABLE_0 : bit_vector := "1111"; CHAN_BOND_SEQ_1_ENABLE_1 : bit_vector := "1111"; CHAN_BOND_SEQ_2_1_0 : bit_vector := "0110111100"; CHAN_BOND_SEQ_2_1_1 : bit_vector := "0110111100"; CHAN_BOND_SEQ_2_2_0 : bit_vector := "0100111100"; CHAN_BOND_SEQ_2_2_1 : bit_vector := "0100111100"; CHAN_BOND_SEQ_2_3_0 : bit_vector := "0100111100"; CHAN_BOND_SEQ_2_3_1 : bit_vector := "0100111100"; CHAN_BOND_SEQ_2_4_0 : bit_vector := "0100111100"; CHAN_BOND_SEQ_2_4_1 : bit_vector := "0100111100"; CHAN_BOND_SEQ_2_ENABLE_0 : bit_vector := "1111"; CHAN_BOND_SEQ_2_ENABLE_1 : bit_vector := "1111"; CHAN_BOND_SEQ_2_USE_0 : boolean := TRUE; CHAN_BOND_SEQ_2_USE_1 : boolean := TRUE; CHAN_BOND_SEQ_LEN_0 : integer := 4; CHAN_BOND_SEQ_LEN_1 : integer := 4; CLK25_DIVIDER : integer := 4; CLKINDC_B : boolean := TRUE; CLK_CORRECT_USE_0 : boolean := TRUE; CLK_CORRECT_USE_1 : boolean := TRUE; CLK_COR_ADJ_LEN_0 : integer := 1; CLK_COR_ADJ_LEN_1 : integer := 1; CLK_COR_DET_LEN_0 : integer := 1; CLK_COR_DET_LEN_1 : integer := 1; CLK_COR_INSERT_IDLE_FLAG_0 : boolean := FALSE; CLK_COR_INSERT_IDLE_FLAG_1 : boolean := FALSE; CLK_COR_KEEP_IDLE_0 : boolean := FALSE; CLK_COR_KEEP_IDLE_1 : boolean := FALSE; CLK_COR_MAX_LAT_0 : integer := 18; CLK_COR_MAX_LAT_1 : integer := 18; CLK_COR_MIN_LAT_0 : integer := 16; CLK_COR_MIN_LAT_1 : integer := 16; CLK_COR_PRECEDENCE_0 : boolean := TRUE; CLK_COR_PRECEDENCE_1 : boolean := TRUE; CLK_COR_REPEAT_WAIT_0 : integer := 5; CLK_COR_REPEAT_WAIT_1 : integer := 5; CLK_COR_SEQ_1_1_0 : bit_vector := "0100011100"; CLK_COR_SEQ_1_1_1 : bit_vector := "0100011100"; CLK_COR_SEQ_1_2_0 : bit_vector := "0000000000"; CLK_COR_SEQ_1_2_1 : bit_vector := "0000000000"; CLK_COR_SEQ_1_3_0 : bit_vector := "0000000000"; CLK_COR_SEQ_1_3_1 : bit_vector := "0000000000"; CLK_COR_SEQ_1_4_0 : bit_vector := "0000000000"; CLK_COR_SEQ_1_4_1 : bit_vector := "0000000000"; CLK_COR_SEQ_1_ENABLE_0 : bit_vector := "1111"; CLK_COR_SEQ_1_ENABLE_1 : bit_vector := "1111"; CLK_COR_SEQ_2_1_0 : bit_vector := "0000000000"; CLK_COR_SEQ_2_1_1 : bit_vector := "0000000000"; CLK_COR_SEQ_2_2_0 : bit_vector := "0000000000"; CLK_COR_SEQ_2_2_1 : bit_vector := "0000000000"; CLK_COR_SEQ_2_3_0 : bit_vector := "0000000000"; CLK_COR_SEQ_2_3_1 : bit_vector := "0000000000"; CLK_COR_SEQ_2_4_0 : bit_vector := "0000000000"; CLK_COR_SEQ_2_4_1 : bit_vector := "0000000000"; CLK_COR_SEQ_2_ENABLE_0 : bit_vector := "1111"; CLK_COR_SEQ_2_ENABLE_1 : bit_vector := "1111"; CLK_COR_SEQ_2_USE_0 : boolean := FALSE; CLK_COR_SEQ_2_USE_1 : boolean := FALSE; COMMA_10B_ENABLE_0 : bit_vector := "1111111111"; COMMA_10B_ENABLE_1 : bit_vector := "1111111111"; COMMA_DOUBLE_0 : boolean := FALSE; COMMA_DOUBLE_1 : boolean := FALSE; COM_BURST_VAL_0 : bit_vector := "1111"; COM_BURST_VAL_1 : bit_vector := "1111"; DEC_MCOMMA_DETECT_0 : boolean := TRUE; DEC_MCOMMA_DETECT_1 : boolean := TRUE; DEC_PCOMMA_DETECT_0 : boolean := TRUE; DEC_PCOMMA_DETECT_1 : boolean := TRUE; DEC_VALID_COMMA_ONLY_0 : boolean := TRUE; DEC_VALID_COMMA_ONLY_1 : boolean := TRUE; MCOMMA_10B_VALUE_0 : bit_vector := "1010000011"; MCOMMA_10B_VALUE_1 : bit_vector := "1010000011"; MCOMMA_DETECT_0 : boolean := TRUE; MCOMMA_DETECT_1 : boolean := TRUE; OOBDETECT_THRESHOLD_0 : bit_vector := "001"; OOBDETECT_THRESHOLD_1 : bit_vector := "001"; OOB_CLK_DIVIDER : integer := 4; OVERSAMPLE_MODE : boolean := FALSE; PCI_EXPRESS_MODE_0 : boolean := TRUE; PCI_EXPRESS_MODE_1 : boolean := TRUE; PCOMMA_10B_VALUE_0 : bit_vector := "0101111100"; PCOMMA_10B_VALUE_1 : bit_vector := "0101111100"; PCOMMA_DETECT_0 : boolean := TRUE; PCOMMA_DETECT_1 : boolean := TRUE; PCS_COM_CFG : bit_vector := X"1680a0e"; PLL_DIVSEL_FB : integer := 5; PLL_DIVSEL_REF : integer := 2; PLL_RXDIVSEL_OUT_0 : integer := 1; PLL_RXDIVSEL_OUT_1 : integer := 1; PLL_SATA_0 : boolean := FALSE; PLL_SATA_1 : boolean := FALSE; PLL_TXDIVSEL_COMM_OUT : integer := 1; PLL_TXDIVSEL_OUT_0 : integer := 1; PLL_TXDIVSEL_OUT_1 : integer := 1; PMA_CDR_SCAN_0 : bit_vector := X"6c07640"; PMA_CDR_SCAN_1 : bit_vector := X"6c07640"; PMA_RX_CFG_0 : bit_vector := X"09f0089"; PMA_RX_CFG_1 : bit_vector := X"09f0089"; PRBS_ERR_THRESHOLD_0 : bit_vector := X"00000001"; PRBS_ERR_THRESHOLD_1 : bit_vector := X"00000001"; RCV_TERM_GND_0 : boolean := TRUE; RCV_TERM_GND_1 : boolean := TRUE; RCV_TERM_MID_0 : boolean := FALSE; RCV_TERM_MID_1 : boolean := FALSE; RCV_TERM_VTTRX_0 : boolean := FALSE; RCV_TERM_VTTRX_1 : boolean := FALSE; RX_BUFFER_USE_0 : boolean := TRUE; RX_BUFFER_USE_1 : boolean := TRUE; RX_DECODE_SEQ_MATCH_0 : boolean := TRUE; RX_DECODE_SEQ_MATCH_1 : boolean := TRUE; RX_LOSS_OF_SYNC_FSM_0 : boolean := FALSE; RX_LOSS_OF_SYNC_FSM_1 : boolean := FALSE; RX_LOS_INVALID_INCR_0 : integer := 8; RX_LOS_INVALID_INCR_1 : integer := 8; RX_LOS_THRESHOLD_0 : integer := 128; RX_LOS_THRESHOLD_1 : integer := 128; RX_SLIDE_MODE_0 : string := "PCS"; RX_SLIDE_MODE_1 : string := "PCS"; RX_STATUS_FMT_0 : string := "PCIE"; RX_STATUS_FMT_1 : string := "PCIE"; RX_XCLK_SEL_0 : string := "RXREC"; RX_XCLK_SEL_1 : string := "RXREC"; SATA_BURST_VAL_0 : bit_vector := "100"; SATA_BURST_VAL_1 : bit_vector := "100"; SATA_IDLE_VAL_0 : bit_vector := "011"; SATA_IDLE_VAL_1 : bit_vector := "011"; SATA_MAX_BURST_0 : integer := 7; SATA_MAX_BURST_1 : integer := 7; SATA_MAX_INIT_0 : integer := 22; SATA_MAX_INIT_1 : integer := 22; SATA_MAX_WAKE_0 : integer := 7; SATA_MAX_WAKE_1 : integer := 7; SATA_MIN_BURST_0 : integer := 4; SATA_MIN_BURST_1 : integer := 4; SATA_MIN_INIT_0 : integer := 12; SATA_MIN_INIT_1 : integer := 12; SATA_MIN_WAKE_0 : integer := 4; SATA_MIN_WAKE_1 : integer := 4; SIM_GTPRESET_SPEEDUP : integer := 0; SIM_MODE : string := "FAST"; SIM_PLL_PERDIV2 : bit_vector := X"190"; SIM_RECEIVER_DETECT_PASS0 : boolean := FALSE; SIM_RECEIVER_DETECT_PASS1 : boolean := FALSE; TERMINATION_CTRL : bit_vector := "10100"; TERMINATION_IMP_0 : integer := 50; TERMINATION_IMP_1 : integer := 50; TERMINATION_OVRD : boolean := FALSE; TRANS_TIME_FROM_P2_0 : bit_vector := X"003c"; TRANS_TIME_FROM_P2_1 : bit_vector := X"003c"; TRANS_TIME_NON_P2_0 : bit_vector := X"0019"; TRANS_TIME_NON_P2_1 : bit_vector := X"0019"; TRANS_TIME_TO_P2_0 : bit_vector := X"0064"; TRANS_TIME_TO_P2_1 : bit_vector := X"0064"; TXRX_INVERT_0 : bit_vector := "00000"; TXRX_INVERT_1 : bit_vector := "00000"; TX_BUFFER_USE_0 : boolean := TRUE; TX_BUFFER_USE_1 : boolean := TRUE; TX_DIFF_BOOST_0 : boolean := TRUE; TX_DIFF_BOOST_1 : boolean := TRUE; TX_SYNC_FILTERB : integer := 1; TX_XCLK_SEL_0 : string := "TXUSR"; TX_XCLK_SEL_1 : string := "TXUSR" ); port ( DO : out std_logic_vector(15 downto 0); DRDY : out std_ulogic; PHYSTATUS0 : out std_ulogic; PHYSTATUS1 : out std_ulogic; PLLLKDET : out std_ulogic; REFCLKOUT : out std_ulogic; RESETDONE0 : out std_ulogic; RESETDONE1 : out std_ulogic; RXBUFSTATUS0 : out std_logic_vector(2 downto 0); RXBUFSTATUS1 : out std_logic_vector(2 downto 0); RXBYTEISALIGNED0 : out std_ulogic; RXBYTEISALIGNED1 : out std_ulogic; RXBYTEREALIGN0 : out std_ulogic; RXBYTEREALIGN1 : out std_ulogic; RXCHANBONDSEQ0 : out std_ulogic; RXCHANBONDSEQ1 : out std_ulogic; RXCHANISALIGNED0 : out std_ulogic; RXCHANISALIGNED1 : out std_ulogic; RXCHANREALIGN0 : out std_ulogic; RXCHANREALIGN1 : out std_ulogic; RXCHARISCOMMA0 : out std_logic_vector(1 downto 0); RXCHARISCOMMA1 : out std_logic_vector(1 downto 0); RXCHARISK0 : out std_logic_vector(1 downto 0); RXCHARISK1 : out std_logic_vector(1 downto 0); RXCHBONDO0 : out std_logic_vector(2 downto 0); RXCHBONDO1 : out std_logic_vector(2 downto 0); RXCLKCORCNT0 : out std_logic_vector(2 downto 0); RXCLKCORCNT1 : out std_logic_vector(2 downto 0); RXCOMMADET0 : out std_ulogic; RXCOMMADET1 : out std_ulogic; RXDATA0 : out std_logic_vector(15 downto 0); RXDATA1 : out std_logic_vector(15 downto 0); RXDISPERR0 : out std_logic_vector(1 downto 0); RXDISPERR1 : out std_logic_vector(1 downto 0); RXELECIDLE0 : out std_ulogic; RXELECIDLE1 : out std_ulogic; RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); RXNOTINTABLE0 : out std_logic_vector(1 downto 0); RXNOTINTABLE1 : out std_logic_vector(1 downto 0); RXOVERSAMPLEERR0 : out std_ulogic; RXOVERSAMPLEERR1 : out std_ulogic; RXPRBSERR0 : out std_ulogic; RXPRBSERR1 : out std_ulogic; RXRECCLK0 : out std_ulogic; RXRECCLK1 : out std_ulogic; RXRUNDISP0 : out std_logic_vector(1 downto 0); RXRUNDISP1 : out std_logic_vector(1 downto 0); RXSTATUS0 : out std_logic_vector(2 downto 0); RXSTATUS1 : out std_logic_vector(2 downto 0); RXVALID0 : out std_ulogic; RXVALID1 : out std_ulogic; TXBUFSTATUS0 : out std_logic_vector(1 downto 0); TXBUFSTATUS1 : out std_logic_vector(1 downto 0); TXKERR0 : out std_logic_vector(1 downto 0); TXKERR1 : out std_logic_vector(1 downto 0); TXN0 : out std_ulogic; TXN1 : out std_ulogic; TXOUTCLK0 : out std_ulogic; TXOUTCLK1 : out std_ulogic; TXP0 : out std_ulogic; TXP1 : out std_ulogic; TXRUNDISP0 : out std_logic_vector(1 downto 0); TXRUNDISP1 : out std_logic_vector(1 downto 0); CLKIN : in std_ulogic; DADDR : in std_logic_vector(6 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; GTPRESET : in std_ulogic; GTPTEST : in std_logic_vector(3 downto 0); INTDATAWIDTH : in std_ulogic; LOOPBACK0 : in std_logic_vector(2 downto 0); LOOPBACK1 : in std_logic_vector(2 downto 0); PLLLKDETEN : in std_ulogic; PLLPOWERDOWN : in std_ulogic; PRBSCNTRESET0 : in std_ulogic; PRBSCNTRESET1 : in std_ulogic; REFCLKPWRDNB : in std_ulogic; RXBUFRESET0 : in std_ulogic; RXBUFRESET1 : in std_ulogic; RXCDRRESET0 : in std_ulogic; RXCDRRESET1 : in std_ulogic; RXCHBONDI0 : in std_logic_vector(2 downto 0); RXCHBONDI1 : in std_logic_vector(2 downto 0); RXCOMMADETUSE0 : in std_ulogic; RXCOMMADETUSE1 : in std_ulogic; RXDATAWIDTH0 : in std_ulogic; RXDATAWIDTH1 : in std_ulogic; RXDEC8B10BUSE0 : in std_ulogic; RXDEC8B10BUSE1 : in std_ulogic; RXELECIDLERESET0 : in std_ulogic; RXELECIDLERESET1 : in std_ulogic; RXENCHANSYNC0 : in std_ulogic; RXENCHANSYNC1 : in std_ulogic; RXENELECIDLERESETB : in std_ulogic; RXENEQB0 : in std_ulogic; RXENEQB1 : in std_ulogic; RXENMCOMMAALIGN0 : in std_ulogic; RXENMCOMMAALIGN1 : in std_ulogic; RXENPCOMMAALIGN0 : in std_ulogic; RXENPCOMMAALIGN1 : in std_ulogic; RXENPRBSTST0 : in std_logic_vector(1 downto 0); RXENPRBSTST1 : in std_logic_vector(1 downto 0); RXENSAMPLEALIGN0 : in std_ulogic; RXENSAMPLEALIGN1 : in std_ulogic; RXEQMIX0 : in std_logic_vector(1 downto 0); RXEQMIX1 : in std_logic_vector(1 downto 0); RXEQPOLE0 : in std_logic_vector(3 downto 0); RXEQPOLE1 : in std_logic_vector(3 downto 0); RXN0 : in std_ulogic; RXN1 : in std_ulogic; RXP0 : in std_ulogic; RXP1 : in std_ulogic; RXPMASETPHASE0 : in std_ulogic; RXPMASETPHASE1 : in std_ulogic; RXPOLARITY0 : in std_ulogic; RXPOLARITY1 : in std_ulogic; RXPOWERDOWN0 : in std_logic_vector(1 downto 0); RXPOWERDOWN1 : in std_logic_vector(1 downto 0); RXRESET0 : in std_ulogic; RXRESET1 : in std_ulogic; RXSLIDE0 : in std_ulogic; RXSLIDE1 : in std_ulogic; RXUSRCLK0 : in std_ulogic; RXUSRCLK1 : in std_ulogic; RXUSRCLK20 : in std_ulogic; RXUSRCLK21 : in std_ulogic; TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); TXBYPASS8B10B0 : in std_logic_vector(1 downto 0); TXBYPASS8B10B1 : in std_logic_vector(1 downto 0); TXCHARDISPMODE0 : in std_logic_vector(1 downto 0); TXCHARDISPMODE1 : in std_logic_vector(1 downto 0); TXCHARDISPVAL0 : in std_logic_vector(1 downto 0); TXCHARDISPVAL1 : in std_logic_vector(1 downto 0); TXCHARISK0 : in std_logic_vector(1 downto 0); TXCHARISK1 : in std_logic_vector(1 downto 0); TXCOMSTART0 : in std_ulogic; TXCOMSTART1 : in std_ulogic; TXCOMTYPE0 : in std_ulogic; TXCOMTYPE1 : in std_ulogic; TXDATA0 : in std_logic_vector(15 downto 0); TXDATA1 : in std_logic_vector(15 downto 0); TXDATAWIDTH0 : in std_ulogic; TXDATAWIDTH1 : in std_ulogic; TXDETECTRX0 : in std_ulogic; TXDETECTRX1 : in std_ulogic; TXDIFFCTRL0 : in std_logic_vector(2 downto 0); TXDIFFCTRL1 : in std_logic_vector(2 downto 0); TXELECIDLE0 : in std_ulogic; TXELECIDLE1 : in std_ulogic; TXENC8B10BUSE0 : in std_ulogic; TXENC8B10BUSE1 : in std_ulogic; TXENPMAPHASEALIGN : in std_ulogic; TXENPRBSTST0 : in std_logic_vector(1 downto 0); TXENPRBSTST1 : in std_logic_vector(1 downto 0); TXINHIBIT0 : in std_ulogic; TXINHIBIT1 : in std_ulogic; TXPMASETPHASE : in std_ulogic; TXPOLARITY0 : in std_ulogic; TXPOLARITY1 : in std_ulogic; TXPOWERDOWN0 : in std_logic_vector(1 downto 0); TXPOWERDOWN1 : in std_logic_vector(1 downto 0); TXPREEMPHASIS0 : in std_logic_vector(2 downto 0); TXPREEMPHASIS1 : in std_logic_vector(2 downto 0); TXRESET0 : in std_ulogic; TXRESET1 : in std_ulogic; TXUSRCLK0 : in std_ulogic; TXUSRCLK1 : in std_ulogic; TXUSRCLK20 : in std_ulogic; TXUSRCLK21 : in std_ulogic ); end GTP_DUAL; architecture GTP_DUAL_V of GTP_DUAL is component GTP_DUAL_SWIFT port ( DO : out std_logic_vector(15 downto 0); DRDY : out std_ulogic; PHYSTATUS0 : out std_ulogic; PHYSTATUS1 : out std_ulogic; PLLLKDET : out std_ulogic; REFCLKOUT : out std_ulogic; RESETDONE0 : out std_ulogic; RESETDONE1 : out std_ulogic; RXBUFSTATUS0 : out std_logic_vector(2 downto 0); RXBUFSTATUS1 : out std_logic_vector(2 downto 0); RXBYTEISALIGNED0 : out std_ulogic; RXBYTEISALIGNED1 : out std_ulogic; RXBYTEREALIGN0 : out std_ulogic; RXBYTEREALIGN1 : out std_ulogic; RXCHANBONDSEQ0 : out std_ulogic; RXCHANBONDSEQ1 : out std_ulogic; RXCHANISALIGNED0 : out std_ulogic; RXCHANISALIGNED1 : out std_ulogic; RXCHANREALIGN0 : out std_ulogic; RXCHANREALIGN1 : out std_ulogic; RXCHARISCOMMA0 : out std_logic_vector(1 downto 0); RXCHARISCOMMA1 : out std_logic_vector(1 downto 0); RXCHARISK0 : out std_logic_vector(1 downto 0); RXCHARISK1 : out std_logic_vector(1 downto 0); RXCHBONDO0 : out std_logic_vector(2 downto 0); RXCHBONDO1 : out std_logic_vector(2 downto 0); RXCLKCORCNT0 : out std_logic_vector(2 downto 0); RXCLKCORCNT1 : out std_logic_vector(2 downto 0); RXCOMMADET0 : out std_ulogic; RXCOMMADET1 : out std_ulogic; RXDATA0 : out std_logic_vector(15 downto 0); RXDATA1 : out std_logic_vector(15 downto 0); RXDISPERR0 : out std_logic_vector(1 downto 0); RXDISPERR1 : out std_logic_vector(1 downto 0); RXELECIDLE0 : out std_ulogic; RXELECIDLE1 : out std_ulogic; RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); RXNOTINTABLE0 : out std_logic_vector(1 downto 0); RXNOTINTABLE1 : out std_logic_vector(1 downto 0); RXOVERSAMPLEERR0 : out std_ulogic; RXOVERSAMPLEERR1 : out std_ulogic; RXPRBSERR0 : out std_ulogic; RXPRBSERR1 : out std_ulogic; RXRECCLK0 : out std_ulogic; RXRECCLK1 : out std_ulogic; RXRUNDISP0 : out std_logic_vector(1 downto 0); RXRUNDISP1 : out std_logic_vector(1 downto 0); RXSTATUS0 : out std_logic_vector(2 downto 0); RXSTATUS1 : out std_logic_vector(2 downto 0); RXVALID0 : out std_ulogic; RXVALID1 : out std_ulogic; TXBUFSTATUS0 : out std_logic_vector(1 downto 0); TXBUFSTATUS1 : out std_logic_vector(1 downto 0); TXKERR0 : out std_logic_vector(1 downto 0); TXKERR1 : out std_logic_vector(1 downto 0); TXN0 : out std_ulogic; TXN1 : out std_ulogic; TXOUTCLK0 : out std_ulogic; TXOUTCLK1 : out std_ulogic; TXP0 : out std_ulogic; TXP1 : out std_ulogic; TXRUNDISP0 : out std_logic_vector(1 downto 0); TXRUNDISP1 : out std_logic_vector(1 downto 0); CLKIN : in std_ulogic; DADDR : in std_logic_vector(6 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; GSR : in std_ulogic; GTPRESET : in std_ulogic; GTPTEST : in std_logic_vector(3 downto 0); INTDATAWIDTH : in std_ulogic; LOOPBACK0 : in std_logic_vector(2 downto 0); LOOPBACK1 : in std_logic_vector(2 downto 0); PLLLKDETEN : in std_ulogic; PLLPOWERDOWN : in std_ulogic; PRBSCNTRESET0 : in std_ulogic; PRBSCNTRESET1 : in std_ulogic; REFCLKPWRDNB : in std_ulogic; RXBUFRESET0 : in std_ulogic; RXBUFRESET1 : in std_ulogic; RXCDRRESET0 : in std_ulogic; RXCDRRESET1 : in std_ulogic; RXCHBONDI0 : in std_logic_vector(2 downto 0); RXCHBONDI1 : in std_logic_vector(2 downto 0); RXCOMMADETUSE0 : in std_ulogic; RXCOMMADETUSE1 : in std_ulogic; RXDATAWIDTH0 : in std_ulogic; RXDATAWIDTH1 : in std_ulogic; RXDEC8B10BUSE0 : in std_ulogic; RXDEC8B10BUSE1 : in std_ulogic; RXELECIDLERESET0 : in std_ulogic; RXELECIDLERESET1 : in std_ulogic; RXENCHANSYNC0 : in std_ulogic; RXENCHANSYNC1 : in std_ulogic; RXENELECIDLERESETB : in std_ulogic; RXENEQB0 : in std_ulogic; RXENEQB1 : in std_ulogic; RXENMCOMMAALIGN0 : in std_ulogic; RXENMCOMMAALIGN1 : in std_ulogic; RXENPCOMMAALIGN0 : in std_ulogic; RXENPCOMMAALIGN1 : in std_ulogic; RXENPRBSTST0 : in std_logic_vector(1 downto 0); RXENPRBSTST1 : in std_logic_vector(1 downto 0); RXENSAMPLEALIGN0 : in std_ulogic; RXENSAMPLEALIGN1 : in std_ulogic; RXEQMIX0 : in std_logic_vector(1 downto 0); RXEQMIX1 : in std_logic_vector(1 downto 0); RXEQPOLE0 : in std_logic_vector(3 downto 0); RXEQPOLE1 : in std_logic_vector(3 downto 0); RXN0 : in std_ulogic; RXN1 : in std_ulogic; RXP0 : in std_ulogic; RXP1 : in std_ulogic; RXPMASETPHASE0 : in std_ulogic; RXPMASETPHASE1 : in std_ulogic; RXPOLARITY0 : in std_ulogic; RXPOLARITY1 : in std_ulogic; RXPOWERDOWN0 : in std_logic_vector(1 downto 0); RXPOWERDOWN1 : in std_logic_vector(1 downto 0); RXRESET0 : in std_ulogic; RXRESET1 : in std_ulogic; RXSLIDE0 : in std_ulogic; RXSLIDE1 : in std_ulogic; RXUSRCLK0 : in std_ulogic; RXUSRCLK1 : in std_ulogic; RXUSRCLK20 : in std_ulogic; RXUSRCLK21 : in std_ulogic; TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); TXBYPASS8B10B0 : in std_logic_vector(1 downto 0); TXBYPASS8B10B1 : in std_logic_vector(1 downto 0); TXCHARDISPMODE0 : in std_logic_vector(1 downto 0); TXCHARDISPMODE1 : in std_logic_vector(1 downto 0); TXCHARDISPVAL0 : in std_logic_vector(1 downto 0); TXCHARDISPVAL1 : in std_logic_vector(1 downto 0); TXCHARISK0 : in std_logic_vector(1 downto 0); TXCHARISK1 : in std_logic_vector(1 downto 0); TXCOMSTART0 : in std_ulogic; TXCOMSTART1 : in std_ulogic; TXCOMTYPE0 : in std_ulogic; TXCOMTYPE1 : in std_ulogic; TXDATA0 : in std_logic_vector(15 downto 0); TXDATA1 : in std_logic_vector(15 downto 0); TXDATAWIDTH0 : in std_ulogic; TXDATAWIDTH1 : in std_ulogic; TXDETECTRX0 : in std_ulogic; TXDETECTRX1 : in std_ulogic; TXDIFFCTRL0 : in std_logic_vector(2 downto 0); TXDIFFCTRL1 : in std_logic_vector(2 downto 0); TXELECIDLE0 : in std_ulogic; TXELECIDLE1 : in std_ulogic; TXENC8B10BUSE0 : in std_ulogic; TXENC8B10BUSE1 : in std_ulogic; TXENPMAPHASEALIGN : in std_ulogic; TXENPRBSTST0 : in std_logic_vector(1 downto 0); TXENPRBSTST1 : in std_logic_vector(1 downto 0); TXINHIBIT0 : in std_ulogic; TXINHIBIT1 : in std_ulogic; TXPMASETPHASE : in std_ulogic; TXPOLARITY0 : in std_ulogic; TXPOLARITY1 : in std_ulogic; TXPOWERDOWN0 : in std_logic_vector(1 downto 0); TXPOWERDOWN1 : in std_logic_vector(1 downto 0); TXPREEMPHASIS0 : in std_logic_vector(2 downto 0); TXPREEMPHASIS1 : in std_logic_vector(2 downto 0); TXRESET0 : in std_ulogic; TXRESET1 : in std_ulogic; TXUSRCLK0 : in std_ulogic; TXUSRCLK1 : in std_ulogic; TXUSRCLK20 : in std_ulogic; TXUSRCLK21 : in std_ulogic; AC_CAP_DIS_0 : in std_ulogic; AC_CAP_DIS_1 : in std_ulogic; ALIGN_COMMA_WORD_0 : in std_ulogic; ALIGN_COMMA_WORD_1 : in std_ulogic; CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); CLK25_DIVIDER : in std_logic_vector(2 downto 0); CLKINDC_B : in std_ulogic; CLK_CORRECT_USE_0 : in std_ulogic; CLK_CORRECT_USE_1 : in std_ulogic; CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; CLK_COR_KEEP_IDLE_0 : in std_ulogic; CLK_COR_KEEP_IDLE_1 : in std_ulogic; CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); CLK_COR_PRECEDENCE_0 : in std_ulogic; CLK_COR_PRECEDENCE_1 : in std_ulogic; CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_USE_0 : in std_ulogic; CLK_COR_SEQ_2_USE_1 : in std_ulogic; COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); COMMA_DOUBLE_0 : in std_ulogic; COMMA_DOUBLE_1 : in std_ulogic; COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); DEC_MCOMMA_DETECT_0 : in std_ulogic; DEC_MCOMMA_DETECT_1 : in std_ulogic; DEC_PCOMMA_DETECT_0 : in std_ulogic; DEC_PCOMMA_DETECT_1 : in std_ulogic; DEC_VALID_COMMA_ONLY_0 : in std_ulogic; DEC_VALID_COMMA_ONLY_1 : in std_ulogic; MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); MCOMMA_DETECT_0 : in std_ulogic; MCOMMA_DETECT_1 : in std_ulogic; OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); OVERSAMPLE_MODE : in std_ulogic; PCI_EXPRESS_MODE_0 : in std_ulogic; PCI_EXPRESS_MODE_1 : in std_ulogic; PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); PCOMMA_DETECT_0 : in std_ulogic; PCOMMA_DETECT_1 : in std_ulogic; PCS_COM_CFG : in std_logic_vector(27 downto 0); PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); PLL_SATA_0 : in std_ulogic; PLL_SATA_1 : in std_ulogic; PLL_TXDIVSEL_COMM_OUT : in std_logic_vector(1 downto 0); PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); RCV_TERM_GND_0 : in std_ulogic; RCV_TERM_GND_1 : in std_ulogic; RCV_TERM_MID_0 : in std_ulogic; RCV_TERM_MID_1 : in std_ulogic; RCV_TERM_VTTRX_0 : in std_ulogic; RCV_TERM_VTTRX_1 : in std_ulogic; RX_BUFFER_USE_0 : in std_ulogic; RX_BUFFER_USE_1 : in std_ulogic; RX_DECODE_SEQ_MATCH_0 : in std_ulogic; RX_DECODE_SEQ_MATCH_1 : in std_ulogic; RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); RX_SLIDE_MODE_0 : in std_ulogic; RX_SLIDE_MODE_1 : in std_ulogic; RX_STATUS_FMT_0 : in std_ulogic; RX_STATUS_FMT_1 : in std_ulogic; RX_XCLK_SEL_0 : in std_ulogic; RX_XCLK_SEL_1 : in std_ulogic; SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); SIM_GTPRESET_SPEEDUP : in std_ulogic; SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); SIM_RECEIVER_DETECT_PASS0 : in std_ulogic; SIM_RECEIVER_DETECT_PASS1 : in std_ulogic; TERMINATION_CTRL : in std_logic_vector(4 downto 0); TERMINATION_IMP_0 : in std_ulogic; TERMINATION_IMP_1 : in std_ulogic; TERMINATION_OVRD : in std_ulogic; TRANS_TIME_FROM_P2_0 : in std_logic_vector(15 downto 0); TRANS_TIME_FROM_P2_1 : in std_logic_vector(15 downto 0); TRANS_TIME_NON_P2_0 : in std_logic_vector(15 downto 0); TRANS_TIME_NON_P2_1 : in std_logic_vector(15 downto 0); TRANS_TIME_TO_P2_0 : in std_logic_vector(15 downto 0); TRANS_TIME_TO_P2_1 : in std_logic_vector(15 downto 0); TXRX_INVERT_0 : in std_logic_vector(4 downto 0); TXRX_INVERT_1 : in std_logic_vector(4 downto 0); TX_BUFFER_USE_0 : in std_ulogic; TX_BUFFER_USE_1 : in std_ulogic; TX_DIFF_BOOST_0 : in std_ulogic; TX_DIFF_BOOST_1 : in std_ulogic; TX_SYNC_FILTERB : in std_ulogic; TX_XCLK_SEL_0 : in std_ulogic; TX_XCLK_SEL_1 : in std_ulogic ); end component; component GTP_DUAL_FAST port ( DO : out std_logic_vector(15 downto 0); DRDY : out std_ulogic; PHYSTATUS0 : out std_ulogic; PHYSTATUS1 : out std_ulogic; PLLLKDET : out std_ulogic; REFCLKOUT : out std_ulogic; RESETDONE0 : out std_ulogic; RESETDONE1 : out std_ulogic; RXBUFSTATUS0 : out std_logic_vector(2 downto 0); RXBUFSTATUS1 : out std_logic_vector(2 downto 0); RXBYTEISALIGNED0 : out std_ulogic; RXBYTEISALIGNED1 : out std_ulogic; RXBYTEREALIGN0 : out std_ulogic; RXBYTEREALIGN1 : out std_ulogic; RXCHANBONDSEQ0 : out std_ulogic; RXCHANBONDSEQ1 : out std_ulogic; RXCHANISALIGNED0 : out std_ulogic; RXCHANISALIGNED1 : out std_ulogic; RXCHANREALIGN0 : out std_ulogic; RXCHANREALIGN1 : out std_ulogic; RXCHARISCOMMA0 : out std_logic_vector(1 downto 0); RXCHARISCOMMA1 : out std_logic_vector(1 downto 0); RXCHARISK0 : out std_logic_vector(1 downto 0); RXCHARISK1 : out std_logic_vector(1 downto 0); RXCHBONDO0 : out std_logic_vector(2 downto 0); RXCHBONDO1 : out std_logic_vector(2 downto 0); RXCLKCORCNT0 : out std_logic_vector(2 downto 0); RXCLKCORCNT1 : out std_logic_vector(2 downto 0); RXCOMMADET0 : out std_ulogic; RXCOMMADET1 : out std_ulogic; RXDATA0 : out std_logic_vector(15 downto 0); RXDATA1 : out std_logic_vector(15 downto 0); RXDISPERR0 : out std_logic_vector(1 downto 0); RXDISPERR1 : out std_logic_vector(1 downto 0); RXELECIDLE0 : out std_ulogic; RXELECIDLE1 : out std_ulogic; RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); RXNOTINTABLE0 : out std_logic_vector(1 downto 0); RXNOTINTABLE1 : out std_logic_vector(1 downto 0); RXOVERSAMPLEERR0 : out std_ulogic; RXOVERSAMPLEERR1 : out std_ulogic; RXPRBSERR0 : out std_ulogic; RXPRBSERR1 : out std_ulogic; RXRECCLK0 : out std_ulogic; RXRECCLK1 : out std_ulogic; RXRUNDISP0 : out std_logic_vector(1 downto 0); RXRUNDISP1 : out std_logic_vector(1 downto 0); RXSTATUS0 : out std_logic_vector(2 downto 0); RXSTATUS1 : out std_logic_vector(2 downto 0); RXVALID0 : out std_ulogic; RXVALID1 : out std_ulogic; TXBUFSTATUS0 : out std_logic_vector(1 downto 0); TXBUFSTATUS1 : out std_logic_vector(1 downto 0); TXKERR0 : out std_logic_vector(1 downto 0); TXKERR1 : out std_logic_vector(1 downto 0); TXN0 : out std_ulogic; TXN1 : out std_ulogic; TXOUTCLK0 : out std_ulogic; TXOUTCLK1 : out std_ulogic; TXP0 : out std_ulogic; TXP1 : out std_ulogic; TXRUNDISP0 : out std_logic_vector(1 downto 0); TXRUNDISP1 : out std_logic_vector(1 downto 0); CLKIN : in std_ulogic; DADDR : in std_logic_vector(6 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; GSR : in std_ulogic; GTPRESET : in std_ulogic; GTPTEST : in std_logic_vector(3 downto 0); INTDATAWIDTH : in std_ulogic; LOOPBACK0 : in std_logic_vector(2 downto 0); LOOPBACK1 : in std_logic_vector(2 downto 0); PLLLKDETEN : in std_ulogic; PLLPOWERDOWN : in std_ulogic; PRBSCNTRESET0 : in std_ulogic; PRBSCNTRESET1 : in std_ulogic; REFCLKPWRDNB : in std_ulogic; RXBUFRESET0 : in std_ulogic; RXBUFRESET1 : in std_ulogic; RXCDRRESET0 : in std_ulogic; RXCDRRESET1 : in std_ulogic; RXCHBONDI0 : in std_logic_vector(2 downto 0); RXCHBONDI1 : in std_logic_vector(2 downto 0); RXCOMMADETUSE0 : in std_ulogic; RXCOMMADETUSE1 : in std_ulogic; RXDATAWIDTH0 : in std_ulogic; RXDATAWIDTH1 : in std_ulogic; RXDEC8B10BUSE0 : in std_ulogic; RXDEC8B10BUSE1 : in std_ulogic; RXELECIDLERESET0 : in std_ulogic; RXELECIDLERESET1 : in std_ulogic; RXENCHANSYNC0 : in std_ulogic; RXENCHANSYNC1 : in std_ulogic; RXENELECIDLERESETB : in std_ulogic; RXENEQB0 : in std_ulogic; RXENEQB1 : in std_ulogic; RXENMCOMMAALIGN0 : in std_ulogic; RXENMCOMMAALIGN1 : in std_ulogic; RXENPCOMMAALIGN0 : in std_ulogic; RXENPCOMMAALIGN1 : in std_ulogic; RXENPRBSTST0 : in std_logic_vector(1 downto 0); RXENPRBSTST1 : in std_logic_vector(1 downto 0); RXENSAMPLEALIGN0 : in std_ulogic; RXENSAMPLEALIGN1 : in std_ulogic; RXEQMIX0 : in std_logic_vector(1 downto 0); RXEQMIX1 : in std_logic_vector(1 downto 0); RXEQPOLE0 : in std_logic_vector(3 downto 0); RXEQPOLE1 : in std_logic_vector(3 downto 0); RXN0 : in std_ulogic; RXN1 : in std_ulogic; RXP0 : in std_ulogic; RXP1 : in std_ulogic; RXPMASETPHASE0 : in std_ulogic; RXPMASETPHASE1 : in std_ulogic; RXPOLARITY0 : in std_ulogic; RXPOLARITY1 : in std_ulogic; RXPOWERDOWN0 : in std_logic_vector(1 downto 0); RXPOWERDOWN1 : in std_logic_vector(1 downto 0); RXRESET0 : in std_ulogic; RXRESET1 : in std_ulogic; RXSLIDE0 : in std_ulogic; RXSLIDE1 : in std_ulogic; RXUSRCLK0 : in std_ulogic; RXUSRCLK1 : in std_ulogic; RXUSRCLK20 : in std_ulogic; RXUSRCLK21 : in std_ulogic; TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); TXBYPASS8B10B0 : in std_logic_vector(1 downto 0); TXBYPASS8B10B1 : in std_logic_vector(1 downto 0); TXCHARDISPMODE0 : in std_logic_vector(1 downto 0); TXCHARDISPMODE1 : in std_logic_vector(1 downto 0); TXCHARDISPVAL0 : in std_logic_vector(1 downto 0); TXCHARDISPVAL1 : in std_logic_vector(1 downto 0); TXCHARISK0 : in std_logic_vector(1 downto 0); TXCHARISK1 : in std_logic_vector(1 downto 0); TXCOMSTART0 : in std_ulogic; TXCOMSTART1 : in std_ulogic; TXCOMTYPE0 : in std_ulogic; TXCOMTYPE1 : in std_ulogic; TXDATA0 : in std_logic_vector(15 downto 0); TXDATA1 : in std_logic_vector(15 downto 0); TXDATAWIDTH0 : in std_ulogic; TXDATAWIDTH1 : in std_ulogic; TXDETECTRX0 : in std_ulogic; TXDETECTRX1 : in std_ulogic; TXDIFFCTRL0 : in std_logic_vector(2 downto 0); TXDIFFCTRL1 : in std_logic_vector(2 downto 0); TXELECIDLE0 : in std_ulogic; TXELECIDLE1 : in std_ulogic; TXENC8B10BUSE0 : in std_ulogic; TXENC8B10BUSE1 : in std_ulogic; TXENPMAPHASEALIGN : in std_ulogic; TXENPRBSTST0 : in std_logic_vector(1 downto 0); TXENPRBSTST1 : in std_logic_vector(1 downto 0); TXINHIBIT0 : in std_ulogic; TXINHIBIT1 : in std_ulogic; TXPMASETPHASE : in std_ulogic; TXPOLARITY0 : in std_ulogic; TXPOLARITY1 : in std_ulogic; TXPOWERDOWN0 : in std_logic_vector(1 downto 0); TXPOWERDOWN1 : in std_logic_vector(1 downto 0); TXPREEMPHASIS0 : in std_logic_vector(2 downto 0); TXPREEMPHASIS1 : in std_logic_vector(2 downto 0); TXRESET0 : in std_ulogic; TXRESET1 : in std_ulogic; TXUSRCLK0 : in std_ulogic; TXUSRCLK1 : in std_ulogic; TXUSRCLK20 : in std_ulogic; TXUSRCLK21 : in std_ulogic; AC_CAP_DIS_0 : in std_ulogic; AC_CAP_DIS_1 : in std_ulogic; ALIGN_COMMA_WORD_0 : in std_ulogic; ALIGN_COMMA_WORD_1 : in std_ulogic; CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); CLK25_DIVIDER : in std_logic_vector(2 downto 0); CLKINDC_B : in std_ulogic; CLK_CORRECT_USE_0 : in std_ulogic; CLK_CORRECT_USE_1 : in std_ulogic; CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; CLK_COR_KEEP_IDLE_0 : in std_ulogic; CLK_COR_KEEP_IDLE_1 : in std_ulogic; CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); CLK_COR_PRECEDENCE_0 : in std_ulogic; CLK_COR_PRECEDENCE_1 : in std_ulogic; CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_USE_0 : in std_ulogic; CLK_COR_SEQ_2_USE_1 : in std_ulogic; COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); COMMA_DOUBLE_0 : in std_ulogic; COMMA_DOUBLE_1 : in std_ulogic; COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); DEC_MCOMMA_DETECT_0 : in std_ulogic; DEC_MCOMMA_DETECT_1 : in std_ulogic; DEC_PCOMMA_DETECT_0 : in std_ulogic; DEC_PCOMMA_DETECT_1 : in std_ulogic; DEC_VALID_COMMA_ONLY_0 : in std_ulogic; DEC_VALID_COMMA_ONLY_1 : in std_ulogic; MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); MCOMMA_DETECT_0 : in std_ulogic; MCOMMA_DETECT_1 : in std_ulogic; OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); OVERSAMPLE_MODE : in std_ulogic; PCI_EXPRESS_MODE_0 : in std_ulogic; PCI_EXPRESS_MODE_1 : in std_ulogic; PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); PCOMMA_DETECT_0 : in std_ulogic; PCOMMA_DETECT_1 : in std_ulogic; PCS_COM_CFG : in std_logic_vector(27 downto 0); PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); PLL_SATA_0 : in std_ulogic; PLL_SATA_1 : in std_ulogic; PLL_TXDIVSEL_COMM_OUT : in std_logic_vector(1 downto 0); PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); RCV_TERM_GND_0 : in std_ulogic; RCV_TERM_GND_1 : in std_ulogic; RCV_TERM_MID_0 : in std_ulogic; RCV_TERM_MID_1 : in std_ulogic; RCV_TERM_VTTRX_0 : in std_ulogic; RCV_TERM_VTTRX_1 : in std_ulogic; RX_BUFFER_USE_0 : in std_ulogic; RX_BUFFER_USE_1 : in std_ulogic; RX_DECODE_SEQ_MATCH_0 : in std_ulogic; RX_DECODE_SEQ_MATCH_1 : in std_ulogic; RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); RX_SLIDE_MODE_0 : in std_ulogic; RX_SLIDE_MODE_1 : in std_ulogic; RX_STATUS_FMT_0 : in std_ulogic; RX_STATUS_FMT_1 : in std_ulogic; RX_XCLK_SEL_0 : in std_ulogic; RX_XCLK_SEL_1 : in std_ulogic; SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); SIM_GTPRESET_SPEEDUP : in std_ulogic; SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); SIM_RECEIVER_DETECT_PASS0 : in std_ulogic; SIM_RECEIVER_DETECT_PASS1 : in std_ulogic; TERMINATION_CTRL : in std_logic_vector(4 downto 0); TERMINATION_IMP_0 : in std_ulogic; TERMINATION_IMP_1 : in std_ulogic; TERMINATION_OVRD : in std_ulogic; TRANS_TIME_FROM_P2_0 : in std_logic_vector(15 downto 0); TRANS_TIME_FROM_P2_1 : in std_logic_vector(15 downto 0); TRANS_TIME_NON_P2_0 : in std_logic_vector(15 downto 0); TRANS_TIME_NON_P2_1 : in std_logic_vector(15 downto 0); TRANS_TIME_TO_P2_0 : in std_logic_vector(15 downto 0); TRANS_TIME_TO_P2_1 : in std_logic_vector(15 downto 0); TXRX_INVERT_0 : in std_logic_vector(4 downto 0); TXRX_INVERT_1 : in std_logic_vector(4 downto 0); TX_BUFFER_USE_0 : in std_ulogic; TX_BUFFER_USE_1 : in std_ulogic; TX_DIFF_BOOST_0 : in std_ulogic; TX_DIFF_BOOST_1 : in std_ulogic; TX_SYNC_FILTERB : in std_ulogic; TX_XCLK_SEL_0 : in std_ulogic; TX_XCLK_SEL_1 : in std_ulogic ); end component; constant IN_DELAY : time := 0 ps; constant OUT_DELAY : time := 0 ps; constant CLK_DELAY : time := 0 ps; constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); signal PLL_TXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); signal PLL_RXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); signal PLL_TXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); signal PLL_RXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); signal PLL_DIVSEL_FB_BINARY : std_logic_vector(4 downto 0); signal PLL_DIVSEL_REF_BINARY : std_logic_vector(5 downto 0); signal PLL_TXDIVSEL_COMM_OUT_BINARY : std_logic_vector(1 downto 0); signal PLL_SATA_0_BINARY : std_ulogic; signal PLL_SATA_1_BINARY : std_ulogic; signal TX_DIFF_BOOST_0_BINARY : std_ulogic; signal OOBDETECT_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_0); signal TX_DIFF_BOOST_1_BINARY : std_ulogic; signal OOBDETECT_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_1); signal PMA_CDR_SCAN_0_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_0)(26 downto 0); signal PMA_CDR_SCAN_1_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_1)(26 downto 0); signal PMA_RX_CFG_0_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_0)(24 downto 0); signal PMA_RX_CFG_1_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_1)(24 downto 0); signal OOB_CLK_DIVIDER_BINARY : std_logic_vector(2 downto 0); signal TX_SYNC_FILTERB_BINARY : std_ulogic; signal AC_CAP_DIS_0_BINARY : std_ulogic; signal AC_CAP_DIS_1_BINARY : std_ulogic; signal RCV_TERM_GND_0_BINARY : std_ulogic; signal RCV_TERM_GND_1_BINARY : std_ulogic; signal RCV_TERM_MID_0_BINARY : std_ulogic; signal RCV_TERM_MID_1_BINARY : std_ulogic; signal TERMINATION_IMP_0_BINARY : std_ulogic; signal TERMINATION_IMP_1_BINARY : std_ulogic; signal TERMINATION_OVRD_BINARY : std_ulogic; signal TERMINATION_CTRL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TERMINATION_CTRL); signal RCV_TERM_VTTRX_0_BINARY : std_ulogic; signal RCV_TERM_VTTRX_1_BINARY : std_ulogic; signal TXRX_INVERT_0_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXRX_INVERT_0); signal TXRX_INVERT_1_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TXRX_INVERT_1); signal CLKINDC_B_BINARY : std_ulogic; signal PCOMMA_DETECT_0_BINARY : std_ulogic; signal MCOMMA_DETECT_0_BINARY : std_ulogic; signal PCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_0); signal MCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_0); signal COMMA_10B_ENABLE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_0); signal COMMA_DOUBLE_0_BINARY : std_ulogic; signal ALIGN_COMMA_WORD_0_BINARY : std_ulogic; signal DEC_PCOMMA_DETECT_0_BINARY : std_ulogic; signal DEC_MCOMMA_DETECT_0_BINARY : std_ulogic; signal DEC_VALID_COMMA_ONLY_0_BINARY : std_ulogic; signal PCOMMA_DETECT_1_BINARY : std_ulogic; signal MCOMMA_DETECT_1_BINARY : std_ulogic; signal PCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_1); signal MCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_1); signal COMMA_10B_ENABLE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_1); signal COMMA_DOUBLE_1_BINARY : std_ulogic; signal ALIGN_COMMA_WORD_1_BINARY : std_ulogic; signal DEC_PCOMMA_DETECT_1_BINARY : std_ulogic; signal DEC_MCOMMA_DETECT_1_BINARY : std_ulogic; signal DEC_VALID_COMMA_ONLY_1_BINARY : std_ulogic; signal RX_LOSS_OF_SYNC_FSM_0_BINARY : std_ulogic; signal RX_LOS_INVALID_INCR_0_BINARY : std_logic_vector(2 downto 0); signal RX_LOS_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0); signal RX_LOSS_OF_SYNC_FSM_1_BINARY : std_ulogic; signal RX_LOS_INVALID_INCR_1_BINARY : std_logic_vector(2 downto 0); signal RX_LOS_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0); signal RX_BUFFER_USE_0_BINARY : std_ulogic; signal RX_DECODE_SEQ_MATCH_0_BINARY : std_ulogic; signal RX_BUFFER_USE_1_BINARY : std_ulogic; signal RX_DECODE_SEQ_MATCH_1_BINARY : std_ulogic; signal CLK_COR_MIN_LAT_0_BINARY : std_logic_vector(5 downto 0); signal CLK_COR_MAX_LAT_0_BINARY : std_logic_vector(5 downto 0); signal CLK_CORRECT_USE_0_BINARY : std_ulogic; signal CLK_COR_PRECEDENCE_0_BINARY : std_ulogic; signal CLK_COR_DET_LEN_0_BINARY : std_logic_vector(1 downto 0); signal CLK_COR_ADJ_LEN_0_BINARY : std_logic_vector(1 downto 0); signal CLK_COR_KEEP_IDLE_0_BINARY : std_ulogic; signal CLK_COR_INSERT_IDLE_FLAG_0_BINARY : std_ulogic; signal CLK_COR_REPEAT_WAIT_0_BINARY : std_logic_vector(4 downto 0); signal CLK_COR_SEQ_2_USE_0_BINARY : std_ulogic; signal CLK_COR_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_0); signal CLK_COR_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_0); signal CLK_COR_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_0); signal CLK_COR_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_0); signal CLK_COR_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_0); signal CLK_COR_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_0); signal CLK_COR_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_0); signal CLK_COR_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_0); signal CLK_COR_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_0); signal CLK_COR_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_0); signal CLK_COR_MIN_LAT_1_BINARY : std_logic_vector(5 downto 0); signal CLK_COR_MAX_LAT_1_BINARY : std_logic_vector(5 downto 0); signal CLK_CORRECT_USE_1_BINARY : std_ulogic; signal CLK_COR_PRECEDENCE_1_BINARY : std_ulogic; signal CLK_COR_DET_LEN_1_BINARY : std_logic_vector(1 downto 0); signal CLK_COR_ADJ_LEN_1_BINARY : std_logic_vector(1 downto 0); signal CLK_COR_KEEP_IDLE_1_BINARY : std_ulogic; signal CLK_COR_INSERT_IDLE_FLAG_1_BINARY : std_ulogic; signal CLK_COR_REPEAT_WAIT_1_BINARY : std_logic_vector(4 downto 0); signal CLK_COR_SEQ_2_USE_1_BINARY : std_ulogic; signal CLK_COR_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_1); signal CLK_COR_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_1); signal CLK_COR_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_1); signal CLK_COR_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_1); signal CLK_COR_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_1); signal CLK_COR_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_1); signal CLK_COR_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_1); signal CLK_COR_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_1); signal CLK_COR_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_1); signal CLK_COR_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_1); signal CHAN_BOND_MODE_0_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_LEVEL_0_BINARY : std_logic_vector(2 downto 0); signal CHAN_BOND_SEQ_LEN_0_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_SEQ_2_USE_0_BINARY : std_ulogic; signal CHAN_BOND_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_0); signal CHAN_BOND_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_0); signal CHAN_BOND_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_0); signal CHAN_BOND_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_0); signal CHAN_BOND_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_0); signal CHAN_BOND_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_0); signal CHAN_BOND_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_0); signal CHAN_BOND_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_0); signal CHAN_BOND_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_0); signal CHAN_BOND_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_0); signal CHAN_BOND_1_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); signal CHAN_BOND_2_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); signal CHAN_BOND_MODE_1_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_LEVEL_1_BINARY : std_logic_vector(2 downto 0); signal CHAN_BOND_SEQ_LEN_1_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_SEQ_2_USE_1_BINARY : std_ulogic; signal CHAN_BOND_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_1); signal CHAN_BOND_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_1); signal CHAN_BOND_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_1); signal CHAN_BOND_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_1); signal CHAN_BOND_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_1); signal CHAN_BOND_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_1); signal CHAN_BOND_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_1); signal CHAN_BOND_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_1); signal CHAN_BOND_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_1); signal CHAN_BOND_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_1); signal CHAN_BOND_1_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); signal CHAN_BOND_2_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); signal PCI_EXPRESS_MODE_0_BINARY : std_ulogic; signal TRANS_TIME_FROM_P2_0_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_0); signal TRANS_TIME_NON_P2_0_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_0); signal TRANS_TIME_TO_P2_0_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_0); signal PCI_EXPRESS_MODE_1_BINARY : std_ulogic; signal TRANS_TIME_FROM_P2_1_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_1); signal TRANS_TIME_NON_P2_1_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_1); signal TRANS_TIME_TO_P2_1_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_1); signal RX_STATUS_FMT_0_BINARY : std_ulogic; signal TX_BUFFER_USE_0_BINARY : std_ulogic; signal TX_XCLK_SEL_0_BINARY : std_ulogic; signal RX_XCLK_SEL_0_BINARY : std_ulogic; signal RX_STATUS_FMT_1_BINARY : std_ulogic; signal TX_BUFFER_USE_1_BINARY : std_ulogic; signal TX_XCLK_SEL_1_BINARY : std_ulogic; signal RX_XCLK_SEL_1_BINARY : std_ulogic; signal PRBS_ERR_THRESHOLD_0_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_0); signal RX_SLIDE_MODE_0_BINARY : std_ulogic; signal PRBS_ERR_THRESHOLD_1_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_1); signal RX_SLIDE_MODE_1_BINARY : std_ulogic; signal SATA_MIN_BURST_0_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_BURST_0_BINARY : std_logic_vector(5 downto 0); signal SATA_MIN_INIT_0_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_INIT_0_BINARY : std_logic_vector(5 downto 0); signal SATA_MIN_WAKE_0_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_WAKE_0_BINARY : std_logic_vector(5 downto 0); signal SATA_BURST_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_0); signal SATA_IDLE_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_0); signal COM_BURST_VAL_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_0); signal SATA_MIN_BURST_1_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_BURST_1_BINARY : std_logic_vector(5 downto 0); signal SATA_MIN_INIT_1_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_INIT_1_BINARY : std_logic_vector(5 downto 0); signal SATA_MIN_WAKE_1_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_WAKE_1_BINARY : std_logic_vector(5 downto 0); signal SATA_BURST_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_1); signal SATA_IDLE_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_1); signal COM_BURST_VAL_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_1); signal CLK25_DIVIDER_BINARY : std_logic_vector(2 downto 0); signal PCS_COM_CFG_BINARY : std_logic_vector(27 downto 0) := To_StdLogicVector(PCS_COM_CFG); signal OVERSAMPLE_MODE_BINARY : std_ulogic; signal SIM_GTPRESET_SPEEDUP_BINARY : std_ulogic; signal SIM_MODE_BINARY : std_ulogic; signal SIM_PLL_PERDIV2_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(SIM_PLL_PERDIV2)(8 downto 0); signal SIM_RECEIVER_DETECT_PASS0_BINARY : std_ulogic; signal SIM_RECEIVER_DETECT_PASS1_BINARY : std_ulogic; signal REFCLKOUT_out : std_ulogic; signal RXRECCLK0_out : std_ulogic; signal TXOUTCLK0_out : std_ulogic; signal RXRECCLK1_out : std_ulogic; signal TXOUTCLK1_out : std_ulogic; signal TXP0_out : std_ulogic; signal TXN0_out : std_ulogic; signal TXP1_out : std_ulogic; signal TXN1_out : std_ulogic; signal RXDATA0_out : std_logic_vector(15 downto 0); signal RXNOTINTABLE0_out : std_logic_vector(1 downto 0); signal RXDISPERR0_out : std_logic_vector(1 downto 0); signal RXCHARISK0_out : std_logic_vector(1 downto 0); signal RXRUNDISP0_out : std_logic_vector(1 downto 0); signal RXCHARISCOMMA0_out : std_logic_vector(1 downto 0); signal RXVALID0_out : std_ulogic; signal RXDATA1_out : std_logic_vector(15 downto 0); signal RXNOTINTABLE1_out : std_logic_vector(1 downto 0); signal RXDISPERR1_out : std_logic_vector(1 downto 0); signal RXCHARISK1_out : std_logic_vector(1 downto 0); signal RXRUNDISP1_out : std_logic_vector(1 downto 0); signal RXCHARISCOMMA1_out : std_logic_vector(1 downto 0); signal RXVALID1_out : std_ulogic; signal RESETDONE0_out : std_ulogic; signal RESETDONE1_out : std_ulogic; signal TXKERR0_out : std_logic_vector(1 downto 0); signal TXRUNDISP0_out : std_logic_vector(1 downto 0); signal TXBUFSTATUS0_out : std_logic_vector(1 downto 0); signal TXKERR1_out : std_logic_vector(1 downto 0); signal TXRUNDISP1_out : std_logic_vector(1 downto 0); signal TXBUFSTATUS1_out : std_logic_vector(1 downto 0); signal RXCOMMADET0_out : std_ulogic; signal RXBYTEREALIGN0_out : std_ulogic; signal RXBYTEISALIGNED0_out : std_ulogic; signal RXLOSSOFSYNC0_out : std_logic_vector(1 downto 0); signal RXCHBONDO0_out : std_logic_vector(2 downto 0); signal RXCHANBONDSEQ0_out : std_ulogic; signal RXCHANREALIGN0_out : std_ulogic; signal RXCHANISALIGNED0_out : std_ulogic; signal RXBUFSTATUS0_out : std_logic_vector(2 downto 0); signal RXCOMMADET1_out : std_ulogic; signal RXBYTEREALIGN1_out : std_ulogic; signal RXBYTEISALIGNED1_out : std_ulogic; signal RXLOSSOFSYNC1_out : std_logic_vector(1 downto 0); signal RXCHBONDO1_out : std_logic_vector(2 downto 0); signal RXCHANBONDSEQ1_out : std_ulogic; signal RXCHANREALIGN1_out : std_ulogic; signal RXCHANISALIGNED1_out : std_ulogic; signal RXBUFSTATUS1_out : std_logic_vector(2 downto 0); signal PHYSTATUS0_out : std_ulogic; signal PHYSTATUS1_out : std_ulogic; signal RXELECIDLE0_out : std_ulogic; signal RXSTATUS0_out : std_logic_vector(2 downto 0); signal RXCLKCORCNT0_out : std_logic_vector(2 downto 0); signal RXELECIDLE1_out : std_ulogic; signal RXSTATUS1_out : std_logic_vector(2 downto 0); signal RXCLKCORCNT1_out : std_logic_vector(2 downto 0); signal PLLLKDET_out : std_ulogic; signal RXPRBSERR0_out : std_ulogic; signal RXPRBSERR1_out : std_ulogic; signal DO_out : std_logic_vector(15 downto 0); signal DRDY_out : std_ulogic; signal RXOVERSAMPLEERR0_out : std_ulogic; signal RXOVERSAMPLEERR1_out : std_ulogic; signal REFCLKOUT_outdelay : std_logic; signal RXRECCLK0_outdelay : std_logic; signal TXOUTCLK0_outdelay : std_logic; signal RXRECCLK1_outdelay : std_logic; signal TXOUTCLK1_outdelay : std_logic; signal RXCLKCORCNT0_outdelay : std_logic_vector(2 downto 0); signal RXCLKCORCNT1_outdelay : std_logic_vector(2 downto 0); signal TXP0_outdelay : std_logic; signal TXN0_outdelay : std_logic; signal TXP1_outdelay : std_logic; signal TXN1_outdelay : std_logic; signal RXDATA0_outdelay : std_logic_vector(15 downto 0); signal RXNOTINTABLE0_outdelay : std_logic_vector(1 downto 0); signal RXDISPERR0_outdelay : std_logic_vector(1 downto 0); signal RXCHARISK0_outdelay : std_logic_vector(1 downto 0); signal RXRUNDISP0_outdelay : std_logic_vector(1 downto 0); signal RXCHARISCOMMA0_outdelay : std_logic_vector(1 downto 0); signal RXVALID0_outdelay : std_logic; signal RXDATA1_outdelay : std_logic_vector(15 downto 0); signal RXNOTINTABLE1_outdelay : std_logic_vector(1 downto 0); signal RXDISPERR1_outdelay : std_logic_vector(1 downto 0); signal RXCHARISK1_outdelay : std_logic_vector(1 downto 0); signal RXRUNDISP1_outdelay : std_logic_vector(1 downto 0); signal RXCHARISCOMMA1_outdelay : std_logic_vector(1 downto 0); signal RXVALID1_outdelay : std_logic; signal RESETDONE0_outdelay : std_logic; signal RESETDONE1_outdelay : std_logic; signal TXKERR0_outdelay : std_logic_vector(1 downto 0); signal TXRUNDISP0_outdelay : std_logic_vector(1 downto 0); signal TXBUFSTATUS0_outdelay : std_logic_vector(1 downto 0); signal TXKERR1_outdelay : std_logic_vector(1 downto 0); signal TXRUNDISP1_outdelay : std_logic_vector(1 downto 0); signal TXBUFSTATUS1_outdelay : std_logic_vector(1 downto 0); signal RXCOMMADET0_outdelay : std_logic; signal RXBYTEREALIGN0_outdelay : std_logic; signal RXBYTEISALIGNED0_outdelay : std_logic; signal RXLOSSOFSYNC0_outdelay : std_logic_vector(1 downto 0); signal RXCHBONDO0_outdelay : std_logic_vector(2 downto 0); signal RXCHANBONDSEQ0_outdelay : std_logic; signal RXCHANREALIGN0_outdelay : std_logic; signal RXCHANISALIGNED0_outdelay : std_logic; signal RXBUFSTATUS0_outdelay : std_logic_vector(2 downto 0); signal RXCOMMADET1_outdelay : std_logic; signal RXBYTEREALIGN1_outdelay : std_logic; signal RXBYTEISALIGNED1_outdelay : std_logic; signal RXLOSSOFSYNC1_outdelay : std_logic_vector(1 downto 0); signal RXCHBONDO1_outdelay : std_logic_vector(2 downto 0); signal RXCHANBONDSEQ1_outdelay : std_logic; signal RXCHANREALIGN1_outdelay : std_logic; signal RXCHANISALIGNED1_outdelay : std_logic; signal RXBUFSTATUS1_outdelay : std_logic_vector(2 downto 0); signal PHYSTATUS0_outdelay : std_logic; signal PHYSTATUS1_outdelay : std_logic; signal RXELECIDLE0_outdelay : std_logic; signal RXSTATUS0_outdelay : std_logic_vector(2 downto 0); signal RXELECIDLE1_outdelay : std_logic; signal RXSTATUS1_outdelay : std_logic_vector(2 downto 0); signal PLLLKDET_outdelay : std_logic; signal RXPRBSERR0_outdelay : std_logic; signal RXPRBSERR1_outdelay : std_logic; signal DO_outdelay : std_logic_vector(15 downto 0); signal DRDY_outdelay : std_logic; signal RXOVERSAMPLEERR0_outdelay : std_logic; signal RXOVERSAMPLEERR1_outdelay : std_logic; signal CLKIN_ipd : std_ulogic; signal TXUSRCLK0_ipd : std_ulogic; signal TXUSRCLK20_ipd : std_ulogic; signal RXUSRCLK0_ipd : std_ulogic; signal RXUSRCLK20_ipd : std_ulogic; signal TXUSRCLK1_ipd : std_ulogic; signal TXUSRCLK21_ipd : std_ulogic; signal RXUSRCLK1_ipd : std_ulogic; signal RXUSRCLK21_ipd : std_ulogic; signal RXP0_ipd : std_ulogic; signal RXN0_ipd : std_ulogic; signal TXDATA0_ipd : std_logic_vector(15 downto 0); signal TXBYPASS8B10B0_ipd : std_logic_vector(1 downto 0); signal TXCHARISK0_ipd : std_logic_vector(1 downto 0); signal TXCHARDISPMODE0_ipd : std_logic_vector(1 downto 0); signal TXCHARDISPVAL0_ipd : std_logic_vector(1 downto 0); signal RXP1_ipd : std_ulogic; signal RXN1_ipd : std_ulogic; signal TXDATA1_ipd : std_logic_vector(15 downto 0); signal TXBYPASS8B10B1_ipd : std_logic_vector(1 downto 0); signal TXCHARISK1_ipd : std_logic_vector(1 downto 0); signal TXCHARDISPMODE1_ipd : std_logic_vector(1 downto 0); signal TXCHARDISPVAL1_ipd : std_logic_vector(1 downto 0); signal GTPRESET_ipd : std_ulogic; signal RXCDRRESET0_ipd : std_ulogic; signal TXRESET0_ipd : std_ulogic; signal RXRESET0_ipd : std_ulogic; signal RXBUFRESET0_ipd : std_ulogic; signal RXCDRRESET1_ipd : std_ulogic; signal TXRESET1_ipd : std_ulogic; signal RXRESET1_ipd : std_ulogic; signal RXBUFRESET1_ipd : std_ulogic; signal TXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); signal RXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); signal TXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); signal RXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); signal PLLPOWERDOWN_ipd : std_ulogic; signal REFCLKPWRDNB_ipd : std_ulogic; signal LOOPBACK0_ipd : std_logic_vector(2 downto 0); signal LOOPBACK1_ipd : std_logic_vector(2 downto 0); signal TXDIFFCTRL0_ipd : std_logic_vector(2 downto 0); signal TXBUFDIFFCTRL0_ipd : std_logic_vector(2 downto 0); signal TXPREEMPHASIS0_ipd : std_logic_vector(2 downto 0); signal TXDIFFCTRL1_ipd : std_logic_vector(2 downto 0); signal TXBUFDIFFCTRL1_ipd : std_logic_vector(2 downto 0); signal TXPREEMPHASIS1_ipd : std_logic_vector(2 downto 0); signal RXENEQB0_ipd : std_ulogic; signal RXEQMIX0_ipd : std_logic_vector(1 downto 0); signal RXEQPOLE0_ipd : std_logic_vector(3 downto 0); signal RXENEQB1_ipd : std_ulogic; signal RXEQMIX1_ipd : std_logic_vector(1 downto 0); signal RXEQPOLE1_ipd : std_logic_vector(3 downto 0); signal INTDATAWIDTH_ipd : std_ulogic; signal TXDATAWIDTH0_ipd : std_ulogic; signal TXDATAWIDTH1_ipd : std_ulogic; signal TXENPMAPHASEALIGN_ipd : std_ulogic; signal TXPMASETPHASE_ipd : std_ulogic; signal RXPMASETPHASE0_ipd : std_ulogic; signal RXPMASETPHASE1_ipd : std_ulogic; signal TXENC8B10BUSE0_ipd : std_ulogic; signal TXPOLARITY0_ipd : std_ulogic; signal TXINHIBIT0_ipd : std_ulogic; signal TXENC8B10BUSE1_ipd : std_ulogic; signal TXPOLARITY1_ipd : std_ulogic; signal TXINHIBIT1_ipd : std_ulogic; signal RXPOLARITY0_ipd : std_ulogic; signal RXENPCOMMAALIGN0_ipd : std_ulogic; signal RXENMCOMMAALIGN0_ipd : std_ulogic; signal RXSLIDE0_ipd : std_ulogic; signal RXCOMMADETUSE0_ipd : std_ulogic; signal RXDEC8B10BUSE0_ipd : std_ulogic; signal RXENCHANSYNC0_ipd : std_ulogic; signal RXCHBONDI0_ipd : std_logic_vector(2 downto 0); signal RXDATAWIDTH0_ipd : std_ulogic; signal RXPOLARITY1_ipd : std_ulogic; signal RXENPCOMMAALIGN1_ipd : std_ulogic; signal RXENMCOMMAALIGN1_ipd : std_ulogic; signal RXSLIDE1_ipd : std_ulogic; signal RXCOMMADETUSE1_ipd : std_ulogic; signal RXDEC8B10BUSE1_ipd : std_ulogic; signal RXENCHANSYNC1_ipd : std_ulogic; signal RXCHBONDI1_ipd : std_logic_vector(2 downto 0); signal RXDATAWIDTH1_ipd : std_ulogic; signal TXELECIDLE0_ipd : std_ulogic; signal TXDETECTRX0_ipd : std_ulogic; signal TXELECIDLE1_ipd : std_ulogic; signal TXDETECTRX1_ipd : std_ulogic; signal TXCOMSTART0_ipd : std_ulogic; signal TXCOMTYPE0_ipd : std_ulogic; signal TXCOMSTART1_ipd : std_ulogic; signal TXCOMTYPE1_ipd : std_ulogic; signal PLLLKDETEN_ipd : std_ulogic; signal TXENPRBSTST0_ipd : std_logic_vector(1 downto 0); signal RXENPRBSTST0_ipd : std_logic_vector(1 downto 0); signal PRBSCNTRESET0_ipd : std_ulogic; signal TXENPRBSTST1_ipd : std_logic_vector(1 downto 0); signal RXENPRBSTST1_ipd : std_logic_vector(1 downto 0); signal PRBSCNTRESET1_ipd : std_ulogic; signal DCLK_ipd : std_ulogic; signal DADDR_ipd : std_logic_vector(6 downto 0); signal DI_ipd : std_logic_vector(15 downto 0); signal DEN_ipd : std_ulogic; signal DWE_ipd : std_ulogic; signal RXENSAMPLEALIGN0_ipd : std_ulogic; signal RXENSAMPLEALIGN1_ipd : std_ulogic; signal RXELECIDLERESET0_ipd : std_ulogic; signal RXELECIDLERESET1_ipd : std_ulogic; signal RXENELECIDLERESETB_ipd : std_ulogic; signal GTPTEST_ipd : std_logic_vector(3 downto 0); signal CLKIN_indelay : std_ulogic; signal TXUSRCLK0_indelay : std_ulogic; signal TXUSRCLK20_indelay : std_ulogic; signal RXUSRCLK0_indelay : std_ulogic; signal RXUSRCLK20_indelay : std_ulogic; signal TXUSRCLK1_indelay : std_ulogic; signal TXUSRCLK21_indelay : std_ulogic; signal RXUSRCLK1_indelay : std_ulogic; signal RXUSRCLK21_indelay : std_ulogic; signal RXP0_indelay : std_ulogic; signal RXN0_indelay : std_ulogic; signal TXDATA0_indelay : std_logic_vector(15 downto 0); signal TXBYPASS8B10B0_indelay : std_logic_vector(1 downto 0); signal TXCHARISK0_indelay : std_logic_vector(1 downto 0); signal TXCHARDISPMODE0_indelay : std_logic_vector(1 downto 0); signal TXCHARDISPVAL0_indelay : std_logic_vector(1 downto 0); signal RXP1_indelay : std_ulogic; signal RXN1_indelay : std_ulogic; signal TXDATA1_indelay : std_logic_vector(15 downto 0); signal TXBYPASS8B10B1_indelay : std_logic_vector(1 downto 0); signal TXCHARISK1_indelay : std_logic_vector(1 downto 0); signal TXCHARDISPMODE1_indelay : std_logic_vector(1 downto 0); signal TXCHARDISPVAL1_indelay : std_logic_vector(1 downto 0); signal GTPRESET_indelay : std_ulogic; signal RXCDRRESET0_indelay : std_ulogic; signal TXRESET0_indelay : std_ulogic; signal RXRESET0_indelay : std_ulogic; signal RXBUFRESET0_indelay : std_ulogic; signal RXCDRRESET1_indelay : std_ulogic; signal TXRESET1_indelay : std_ulogic; signal RXRESET1_indelay : std_ulogic; signal RXBUFRESET1_indelay : std_ulogic; signal TXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); signal RXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); signal TXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); signal RXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); signal PLLPOWERDOWN_indelay : std_ulogic; signal REFCLKPWRDNB_indelay : std_ulogic; signal LOOPBACK0_indelay : std_logic_vector(2 downto 0); signal LOOPBACK1_indelay : std_logic_vector(2 downto 0); signal TXDIFFCTRL0_indelay : std_logic_vector(2 downto 0); signal TXBUFDIFFCTRL0_indelay : std_logic_vector(2 downto 0); signal TXPREEMPHASIS0_indelay : std_logic_vector(2 downto 0); signal TXDIFFCTRL1_indelay : std_logic_vector(2 downto 0); signal TXBUFDIFFCTRL1_indelay : std_logic_vector(2 downto 0); signal TXPREEMPHASIS1_indelay : std_logic_vector(2 downto 0); signal RXENEQB0_indelay : std_ulogic; signal RXEQMIX0_indelay : std_logic_vector(1 downto 0); signal RXEQPOLE0_indelay : std_logic_vector(3 downto 0); signal RXENEQB1_indelay : std_ulogic; signal RXEQMIX1_indelay : std_logic_vector(1 downto 0); signal RXEQPOLE1_indelay : std_logic_vector(3 downto 0); signal INTDATAWIDTH_indelay : std_ulogic; signal TXDATAWIDTH0_indelay : std_ulogic; signal TXDATAWIDTH1_indelay : std_ulogic; signal TXENPMAPHASEALIGN_indelay : std_ulogic; signal TXPMASETPHASE_indelay : std_ulogic; signal RXPMASETPHASE0_indelay : std_ulogic; signal RXPMASETPHASE1_indelay : std_ulogic; signal TXENC8B10BUSE0_indelay : std_ulogic; signal TXPOLARITY0_indelay : std_ulogic; signal TXINHIBIT0_indelay : std_ulogic; signal TXENC8B10BUSE1_indelay : std_ulogic; signal TXPOLARITY1_indelay : std_ulogic; signal TXINHIBIT1_indelay : std_ulogic; signal RXPOLARITY0_indelay : std_ulogic; signal RXENPCOMMAALIGN0_indelay : std_ulogic; signal RXENMCOMMAALIGN0_indelay : std_ulogic; signal RXSLIDE0_indelay : std_ulogic; signal RXCOMMADETUSE0_indelay : std_ulogic; signal RXDEC8B10BUSE0_indelay : std_ulogic; signal RXENCHANSYNC0_indelay : std_ulogic; signal RXCHBONDI0_indelay : std_logic_vector(2 downto 0); signal RXDATAWIDTH0_indelay : std_ulogic; signal RXPOLARITY1_indelay : std_ulogic; signal RXENPCOMMAALIGN1_indelay : std_ulogic; signal RXENMCOMMAALIGN1_indelay : std_ulogic; signal RXSLIDE1_indelay : std_ulogic; signal RXCOMMADETUSE1_indelay : std_ulogic; signal RXDEC8B10BUSE1_indelay : std_ulogic; signal RXENCHANSYNC1_indelay : std_ulogic; signal RXCHBONDI1_indelay : std_logic_vector(2 downto 0); signal RXDATAWIDTH1_indelay : std_ulogic; signal TXELECIDLE0_indelay : std_ulogic; signal TXDETECTRX0_indelay : std_ulogic; signal TXELECIDLE1_indelay : std_ulogic; signal TXDETECTRX1_indelay : std_ulogic; signal TXCOMSTART0_indelay : std_ulogic; signal TXCOMTYPE0_indelay : std_ulogic; signal TXCOMSTART1_indelay : std_ulogic; signal TXCOMTYPE1_indelay : std_ulogic; signal PLLLKDETEN_indelay : std_ulogic; signal TXENPRBSTST0_indelay : std_logic_vector(1 downto 0); signal RXENPRBSTST0_indelay : std_logic_vector(1 downto 0); signal PRBSCNTRESET0_indelay : std_ulogic; signal TXENPRBSTST1_indelay : std_logic_vector(1 downto 0); signal RXENPRBSTST1_indelay : std_logic_vector(1 downto 0); signal PRBSCNTRESET1_indelay : std_ulogic; signal DCLK_indelay : std_ulogic; signal DADDR_indelay : std_logic_vector(6 downto 0); signal DI_indelay : std_logic_vector(15 downto 0); signal DEN_indelay : std_ulogic; signal DWE_indelay : std_ulogic; signal RXENSAMPLEALIGN0_indelay : std_ulogic; signal RXENSAMPLEALIGN1_indelay : std_ulogic; signal RXELECIDLERESET0_indelay : std_ulogic; signal RXELECIDLERESET1_indelay : std_ulogic; signal RXENELECIDLERESETB_indelay : std_ulogic; signal GTPTEST_indelay : std_logic_vector(3 downto 0); begin REFCLKOUT_out <= REFCLKOUT_outdelay after CLK_DELAY; RXCLKCORCNT0_out <= RXCLKCORCNT0_outdelay after CLK_DELAY; RXCLKCORCNT1_out <= RXCLKCORCNT1_outdelay after CLK_DELAY; RXRECCLK0_out <= RXRECCLK0_outdelay after CLK_DELAY; RXRECCLK1_out <= RXRECCLK1_outdelay after CLK_DELAY; TXOUTCLK0_out <= TXOUTCLK0_outdelay after CLK_DELAY; TXOUTCLK1_out <= TXOUTCLK1_outdelay after CLK_DELAY; DO_out <= DO_outdelay after OUT_DELAY; DRDY_out <= DRDY_outdelay after OUT_DELAY; PHYSTATUS0_out <= PHYSTATUS0_outdelay after OUT_DELAY; PHYSTATUS1_out <= PHYSTATUS1_outdelay after OUT_DELAY; PLLLKDET_out <= PLLLKDET_outdelay after OUT_DELAY; RESETDONE0_out <= RESETDONE0_outdelay after OUT_DELAY; RESETDONE1_out <= RESETDONE1_outdelay after OUT_DELAY; RXBUFSTATUS0_out <= RXBUFSTATUS0_outdelay after OUT_DELAY; RXBUFSTATUS1_out <= RXBUFSTATUS1_outdelay after OUT_DELAY; RXBYTEISALIGNED0_out <= RXBYTEISALIGNED0_outdelay after OUT_DELAY; RXBYTEISALIGNED1_out <= RXBYTEISALIGNED1_outdelay after OUT_DELAY; RXBYTEREALIGN0_out <= RXBYTEREALIGN0_outdelay after OUT_DELAY; RXBYTEREALIGN1_out <= RXBYTEREALIGN1_outdelay after OUT_DELAY; RXCHANBONDSEQ0_out <= RXCHANBONDSEQ0_outdelay after OUT_DELAY; RXCHANBONDSEQ1_out <= RXCHANBONDSEQ1_outdelay after OUT_DELAY; RXCHANISALIGNED0_out <= RXCHANISALIGNED0_outdelay after OUT_DELAY; RXCHANISALIGNED1_out <= RXCHANISALIGNED1_outdelay after OUT_DELAY; RXCHANREALIGN0_out <= RXCHANREALIGN0_outdelay after OUT_DELAY; RXCHANREALIGN1_out <= RXCHANREALIGN1_outdelay after OUT_DELAY; RXCHARISCOMMA0_out <= RXCHARISCOMMA0_outdelay after OUT_DELAY; RXCHARISCOMMA1_out <= RXCHARISCOMMA1_outdelay after OUT_DELAY; RXCHARISK0_out <= RXCHARISK0_outdelay after OUT_DELAY; RXCHARISK1_out <= RXCHARISK1_outdelay after OUT_DELAY; RXCHBONDO0_out <= RXCHBONDO0_outdelay after OUT_DELAY; RXCHBONDO1_out <= RXCHBONDO1_outdelay after OUT_DELAY; RXCOMMADET0_out <= RXCOMMADET0_outdelay after OUT_DELAY; RXCOMMADET1_out <= RXCOMMADET1_outdelay after OUT_DELAY; RXDATA0_out <= RXDATA0_outdelay after OUT_DELAY; RXDATA1_out <= RXDATA1_outdelay after OUT_DELAY; RXDISPERR0_out <= RXDISPERR0_outdelay after OUT_DELAY; RXDISPERR1_out <= RXDISPERR1_outdelay after OUT_DELAY; RXELECIDLE0_out <= RXELECIDLE0_outdelay after OUT_DELAY; RXELECIDLE1_out <= RXELECIDLE1_outdelay after OUT_DELAY; RXLOSSOFSYNC0_out <= RXLOSSOFSYNC0_outdelay after OUT_DELAY; RXLOSSOFSYNC1_out <= RXLOSSOFSYNC1_outdelay after OUT_DELAY; RXNOTINTABLE0_out <= RXNOTINTABLE0_outdelay after OUT_DELAY; RXNOTINTABLE1_out <= RXNOTINTABLE1_outdelay after OUT_DELAY; RXOVERSAMPLEERR0_out <= RXOVERSAMPLEERR0_outdelay after OUT_DELAY; RXOVERSAMPLEERR1_out <= RXOVERSAMPLEERR1_outdelay after OUT_DELAY; RXPRBSERR0_out <= RXPRBSERR0_outdelay after OUT_DELAY; RXPRBSERR1_out <= RXPRBSERR1_outdelay after OUT_DELAY; RXRUNDISP0_out <= RXRUNDISP0_outdelay after OUT_DELAY; RXRUNDISP1_out <= RXRUNDISP1_outdelay after OUT_DELAY; RXSTATUS0_out <= RXSTATUS0_outdelay after OUT_DELAY; RXSTATUS1_out <= RXSTATUS1_outdelay after OUT_DELAY; RXVALID0_out <= RXVALID0_outdelay after OUT_DELAY; RXVALID1_out <= RXVALID1_outdelay after OUT_DELAY; TXBUFSTATUS0_out <= TXBUFSTATUS0_outdelay after OUT_DELAY; TXBUFSTATUS1_out <= TXBUFSTATUS1_outdelay after OUT_DELAY; TXKERR0_out <= TXKERR0_outdelay after OUT_DELAY; TXKERR1_out <= TXKERR1_outdelay after OUT_DELAY; TXN0_out <= TXN0_outdelay after OUT_DELAY; TXN1_out <= TXN1_outdelay after OUT_DELAY; TXP0_out <= TXP0_outdelay after OUT_DELAY; TXP1_out <= TXP1_outdelay after OUT_DELAY; TXRUNDISP0_out <= TXRUNDISP0_outdelay after OUT_DELAY; TXRUNDISP1_out <= TXRUNDISP1_outdelay after OUT_DELAY; CLKIN_ipd <= CLKIN after CLK_DELAY; DCLK_ipd <= DCLK after CLK_DELAY; RXUSRCLK0_ipd <= RXUSRCLK0 after CLK_DELAY; RXUSRCLK1_ipd <= RXUSRCLK1 after CLK_DELAY; RXUSRCLK20_ipd <= RXUSRCLK20 after CLK_DELAY; RXUSRCLK21_ipd <= RXUSRCLK21 after CLK_DELAY; TXUSRCLK0_ipd <= TXUSRCLK0 after CLK_DELAY; TXUSRCLK1_ipd <= TXUSRCLK1 after CLK_DELAY; TXUSRCLK20_ipd <= TXUSRCLK20 after CLK_DELAY; TXUSRCLK21_ipd <= TXUSRCLK21 after CLK_DELAY; DADDR_ipd <= DADDR after CLK_DELAY; DEN_ipd <= DEN after CLK_DELAY; DI_ipd <= DI after CLK_DELAY; DWE_ipd <= DWE after CLK_DELAY; GTPRESET_ipd <= GTPRESET after CLK_DELAY; GTPTEST_ipd <= GTPTEST after CLK_DELAY; INTDATAWIDTH_ipd <= INTDATAWIDTH after CLK_DELAY; LOOPBACK0_ipd <= LOOPBACK0 after CLK_DELAY; LOOPBACK1_ipd <= LOOPBACK1 after CLK_DELAY; PLLLKDETEN_ipd <= PLLLKDETEN after CLK_DELAY; PLLPOWERDOWN_ipd <= PLLPOWERDOWN after CLK_DELAY; PRBSCNTRESET0_ipd <= PRBSCNTRESET0 after CLK_DELAY; PRBSCNTRESET1_ipd <= PRBSCNTRESET1 after CLK_DELAY; REFCLKPWRDNB_ipd <= REFCLKPWRDNB after CLK_DELAY; RXBUFRESET0_ipd <= RXBUFRESET0 after CLK_DELAY; RXBUFRESET1_ipd <= RXBUFRESET1 after CLK_DELAY; RXCDRRESET0_ipd <= RXCDRRESET0 after CLK_DELAY; RXCDRRESET1_ipd <= RXCDRRESET1 after CLK_DELAY; RXCHBONDI0_ipd <= RXCHBONDI0 after CLK_DELAY; RXCHBONDI1_ipd <= RXCHBONDI1 after CLK_DELAY; RXCOMMADETUSE0_ipd <= RXCOMMADETUSE0 after CLK_DELAY; RXCOMMADETUSE1_ipd <= RXCOMMADETUSE1 after CLK_DELAY; RXDATAWIDTH0_ipd <= RXDATAWIDTH0 after CLK_DELAY; RXDATAWIDTH1_ipd <= RXDATAWIDTH1 after CLK_DELAY; RXDEC8B10BUSE0_ipd <= RXDEC8B10BUSE0 after CLK_DELAY; RXDEC8B10BUSE1_ipd <= RXDEC8B10BUSE1 after CLK_DELAY; RXELECIDLERESET0_ipd <= RXELECIDLERESET0 after CLK_DELAY; RXELECIDLERESET1_ipd <= RXELECIDLERESET1 after CLK_DELAY; RXENCHANSYNC0_ipd <= RXENCHANSYNC0 after CLK_DELAY; RXENCHANSYNC1_ipd <= RXENCHANSYNC1 after CLK_DELAY; RXENELECIDLERESETB_ipd <= RXENELECIDLERESETB after CLK_DELAY; RXENEQB0_ipd <= RXENEQB0 after CLK_DELAY; RXENEQB1_ipd <= RXENEQB1 after CLK_DELAY; RXENMCOMMAALIGN0_ipd <= RXENMCOMMAALIGN0 after CLK_DELAY; RXENMCOMMAALIGN1_ipd <= RXENMCOMMAALIGN1 after CLK_DELAY; RXENPCOMMAALIGN0_ipd <= RXENPCOMMAALIGN0 after CLK_DELAY; RXENPCOMMAALIGN1_ipd <= RXENPCOMMAALIGN1 after CLK_DELAY; RXENPRBSTST0_ipd <= RXENPRBSTST0 after CLK_DELAY; RXENPRBSTST1_ipd <= RXENPRBSTST1 after CLK_DELAY; RXENSAMPLEALIGN0_ipd <= RXENSAMPLEALIGN0 after CLK_DELAY; RXENSAMPLEALIGN1_ipd <= RXENSAMPLEALIGN1 after CLK_DELAY; RXEQMIX0_ipd <= RXEQMIX0 after CLK_DELAY; RXEQMIX1_ipd <= RXEQMIX1 after CLK_DELAY; RXEQPOLE0_ipd <= RXEQPOLE0 after CLK_DELAY; RXEQPOLE1_ipd <= RXEQPOLE1 after CLK_DELAY; RXN0_ipd <= RXN0 after CLK_DELAY; RXN1_ipd <= RXN1 after CLK_DELAY; RXP0_ipd <= RXP0 after CLK_DELAY; RXP1_ipd <= RXP1 after CLK_DELAY; RXPMASETPHASE0_ipd <= RXPMASETPHASE0 after CLK_DELAY; RXPMASETPHASE1_ipd <= RXPMASETPHASE1 after CLK_DELAY; RXPOLARITY0_ipd <= RXPOLARITY0 after CLK_DELAY; RXPOLARITY1_ipd <= RXPOLARITY1 after CLK_DELAY; RXPOWERDOWN0_ipd <= RXPOWERDOWN0 after CLK_DELAY; RXPOWERDOWN1_ipd <= RXPOWERDOWN1 after CLK_DELAY; RXRESET0_ipd <= RXRESET0 after CLK_DELAY; RXRESET1_ipd <= RXRESET1 after CLK_DELAY; RXSLIDE0_ipd <= RXSLIDE0 after CLK_DELAY; RXSLIDE1_ipd <= RXSLIDE1 after CLK_DELAY; TXBUFDIFFCTRL0_ipd <= TXBUFDIFFCTRL0 after CLK_DELAY; TXBUFDIFFCTRL1_ipd <= TXBUFDIFFCTRL1 after CLK_DELAY; TXBYPASS8B10B0_ipd <= TXBYPASS8B10B0 after CLK_DELAY; TXBYPASS8B10B1_ipd <= TXBYPASS8B10B1 after CLK_DELAY; TXCHARDISPMODE0_ipd <= TXCHARDISPMODE0 after CLK_DELAY; TXCHARDISPMODE1_ipd <= TXCHARDISPMODE1 after CLK_DELAY; TXCHARDISPVAL0_ipd <= TXCHARDISPVAL0 after CLK_DELAY; TXCHARDISPVAL1_ipd <= TXCHARDISPVAL1 after CLK_DELAY; TXCHARISK0_ipd <= TXCHARISK0 after CLK_DELAY; TXCHARISK1_ipd <= TXCHARISK1 after CLK_DELAY; TXCOMSTART0_ipd <= TXCOMSTART0 after CLK_DELAY; TXCOMSTART1_ipd <= TXCOMSTART1 after CLK_DELAY; TXCOMTYPE0_ipd <= TXCOMTYPE0 after CLK_DELAY; TXCOMTYPE1_ipd <= TXCOMTYPE1 after CLK_DELAY; TXDATA0_ipd <= TXDATA0 after CLK_DELAY; TXDATA1_ipd <= TXDATA1 after CLK_DELAY; TXDATAWIDTH0_ipd <= TXDATAWIDTH0 after CLK_DELAY; TXDATAWIDTH1_ipd <= TXDATAWIDTH1 after CLK_DELAY; TXDETECTRX0_ipd <= TXDETECTRX0 after CLK_DELAY; TXDETECTRX1_ipd <= TXDETECTRX1 after CLK_DELAY; TXDIFFCTRL0_ipd <= TXDIFFCTRL0 after CLK_DELAY; TXDIFFCTRL1_ipd <= TXDIFFCTRL1 after CLK_DELAY; TXELECIDLE0_ipd <= TXELECIDLE0 after CLK_DELAY; TXELECIDLE1_ipd <= TXELECIDLE1 after CLK_DELAY; TXENC8B10BUSE0_ipd <= TXENC8B10BUSE0 after CLK_DELAY; TXENC8B10BUSE1_ipd <= TXENC8B10BUSE1 after CLK_DELAY; TXENPMAPHASEALIGN_ipd <= TXENPMAPHASEALIGN after CLK_DELAY; TXENPRBSTST0_ipd <= TXENPRBSTST0 after CLK_DELAY; TXENPRBSTST1_ipd <= TXENPRBSTST1 after CLK_DELAY; TXINHIBIT0_ipd <= TXINHIBIT0 after CLK_DELAY; TXINHIBIT1_ipd <= TXINHIBIT1 after CLK_DELAY; TXPMASETPHASE_ipd <= TXPMASETPHASE after CLK_DELAY; TXPOLARITY0_ipd <= TXPOLARITY0 after CLK_DELAY; TXPOLARITY1_ipd <= TXPOLARITY1 after CLK_DELAY; TXPOWERDOWN0_ipd <= TXPOWERDOWN0 after CLK_DELAY; TXPOWERDOWN1_ipd <= TXPOWERDOWN1 after CLK_DELAY; TXPREEMPHASIS0_ipd <= TXPREEMPHASIS0 after CLK_DELAY; TXPREEMPHASIS1_ipd <= TXPREEMPHASIS1 after CLK_DELAY; TXRESET0_ipd <= TXRESET0 after CLK_DELAY; TXRESET1_ipd <= TXRESET1 after CLK_DELAY; CLKIN_indelay <= CLKIN_ipd after CLK_DELAY; DCLK_indelay <= DCLK_ipd after CLK_DELAY; RXUSRCLK0_indelay <= RXUSRCLK0_ipd after CLK_DELAY; RXUSRCLK1_indelay <= RXUSRCLK1_ipd after CLK_DELAY; RXUSRCLK20_indelay <= RXUSRCLK20_ipd after CLK_DELAY; RXUSRCLK21_indelay <= RXUSRCLK21_ipd after CLK_DELAY; TXUSRCLK0_indelay <= TXUSRCLK0_ipd after CLK_DELAY; TXUSRCLK1_indelay <= TXUSRCLK1_ipd after CLK_DELAY; TXUSRCLK20_indelay <= TXUSRCLK20_ipd after CLK_DELAY; TXUSRCLK21_indelay <= TXUSRCLK21_ipd after CLK_DELAY; DADDR_indelay <= DADDR_ipd after IN_DELAY; DEN_indelay <= DEN_ipd after IN_DELAY; DI_indelay <= DI_ipd after IN_DELAY; DWE_indelay <= DWE_ipd after IN_DELAY; GTPRESET_indelay <= GTPRESET_ipd after IN_DELAY; GTPTEST_indelay <= GTPTEST_ipd after IN_DELAY; INTDATAWIDTH_indelay <= INTDATAWIDTH_ipd after IN_DELAY; LOOPBACK0_indelay <= LOOPBACK0_ipd after IN_DELAY; LOOPBACK1_indelay <= LOOPBACK1_ipd after IN_DELAY; PLLLKDETEN_indelay <= PLLLKDETEN_ipd after IN_DELAY; PLLPOWERDOWN_indelay <= PLLPOWERDOWN_ipd after IN_DELAY; PRBSCNTRESET0_indelay <= PRBSCNTRESET0_ipd after IN_DELAY; PRBSCNTRESET1_indelay <= PRBSCNTRESET1_ipd after IN_DELAY; REFCLKPWRDNB_indelay <= REFCLKPWRDNB_ipd after IN_DELAY; RXBUFRESET0_indelay <= RXBUFRESET0_ipd after IN_DELAY; RXBUFRESET1_indelay <= RXBUFRESET1_ipd after IN_DELAY; RXCDRRESET0_indelay <= RXCDRRESET0_ipd after IN_DELAY; RXCDRRESET1_indelay <= RXCDRRESET1_ipd after IN_DELAY; RXCHBONDI0_indelay <= RXCHBONDI0_ipd after IN_DELAY; RXCHBONDI1_indelay <= RXCHBONDI1_ipd after IN_DELAY; RXCOMMADETUSE0_indelay <= RXCOMMADETUSE0_ipd after IN_DELAY; RXCOMMADETUSE1_indelay <= RXCOMMADETUSE1_ipd after IN_DELAY; RXDATAWIDTH0_indelay <= RXDATAWIDTH0_ipd after IN_DELAY; RXDATAWIDTH1_indelay <= RXDATAWIDTH1_ipd after IN_DELAY; RXDEC8B10BUSE0_indelay <= RXDEC8B10BUSE0_ipd after IN_DELAY; RXDEC8B10BUSE1_indelay <= RXDEC8B10BUSE1_ipd after IN_DELAY; RXELECIDLERESET0_indelay <= RXELECIDLERESET0_ipd after IN_DELAY; RXELECIDLERESET1_indelay <= RXELECIDLERESET1_ipd after IN_DELAY; RXENCHANSYNC0_indelay <= RXENCHANSYNC0_ipd after IN_DELAY; RXENCHANSYNC1_indelay <= RXENCHANSYNC1_ipd after IN_DELAY; RXENELECIDLERESETB_indelay <= RXENELECIDLERESETB_ipd after IN_DELAY; RXENEQB0_indelay <= RXENEQB0_ipd after IN_DELAY; RXENEQB1_indelay <= RXENEQB1_ipd after IN_DELAY; RXENMCOMMAALIGN0_indelay <= RXENMCOMMAALIGN0_ipd after IN_DELAY; RXENMCOMMAALIGN1_indelay <= RXENMCOMMAALIGN1_ipd after IN_DELAY; RXENPCOMMAALIGN0_indelay <= RXENPCOMMAALIGN0_ipd after IN_DELAY; RXENPCOMMAALIGN1_indelay <= RXENPCOMMAALIGN1_ipd after IN_DELAY; RXENPRBSTST0_indelay <= RXENPRBSTST0_ipd after IN_DELAY; RXENPRBSTST1_indelay <= RXENPRBSTST1_ipd after IN_DELAY; RXENSAMPLEALIGN0_indelay <= RXENSAMPLEALIGN0_ipd after IN_DELAY; RXENSAMPLEALIGN1_indelay <= RXENSAMPLEALIGN1_ipd after IN_DELAY; RXEQMIX0_indelay <= RXEQMIX0_ipd after IN_DELAY; RXEQMIX1_indelay <= RXEQMIX1_ipd after IN_DELAY; RXEQPOLE0_indelay <= RXEQPOLE0_ipd after IN_DELAY; RXEQPOLE1_indelay <= RXEQPOLE1_ipd after IN_DELAY; RXN0_indelay <= RXN0_ipd after IN_DELAY; RXN1_indelay <= RXN1_ipd after IN_DELAY; RXP0_indelay <= RXP0_ipd after IN_DELAY; RXP1_indelay <= RXP1_ipd after IN_DELAY; RXPMASETPHASE0_indelay <= RXPMASETPHASE0_ipd after IN_DELAY; RXPMASETPHASE1_indelay <= RXPMASETPHASE1_ipd after IN_DELAY; RXPOLARITY0_indelay <= RXPOLARITY0_ipd after IN_DELAY; RXPOLARITY1_indelay <= RXPOLARITY1_ipd after IN_DELAY; RXPOWERDOWN0_indelay <= RXPOWERDOWN0_ipd after IN_DELAY; RXPOWERDOWN1_indelay <= RXPOWERDOWN1_ipd after IN_DELAY; RXRESET0_indelay <= RXRESET0_ipd after IN_DELAY; RXRESET1_indelay <= RXRESET1_ipd after IN_DELAY; RXSLIDE0_indelay <= RXSLIDE0_ipd after IN_DELAY; RXSLIDE1_indelay <= RXSLIDE1_ipd after IN_DELAY; TXBUFDIFFCTRL0_indelay <= TXBUFDIFFCTRL0_ipd after IN_DELAY; TXBUFDIFFCTRL1_indelay <= TXBUFDIFFCTRL1_ipd after IN_DELAY; TXBYPASS8B10B0_indelay <= TXBYPASS8B10B0_ipd after IN_DELAY; TXBYPASS8B10B1_indelay <= TXBYPASS8B10B1_ipd after IN_DELAY; TXCHARDISPMODE0_indelay <= TXCHARDISPMODE0_ipd after IN_DELAY; TXCHARDISPMODE1_indelay <= TXCHARDISPMODE1_ipd after IN_DELAY; TXCHARDISPVAL0_indelay <= TXCHARDISPVAL0_ipd after IN_DELAY; TXCHARDISPVAL1_indelay <= TXCHARDISPVAL1_ipd after IN_DELAY; TXCHARISK0_indelay <= TXCHARISK0_ipd after IN_DELAY; TXCHARISK1_indelay <= TXCHARISK1_ipd after IN_DELAY; TXCOMSTART0_indelay <= TXCOMSTART0_ipd after IN_DELAY; TXCOMSTART1_indelay <= TXCOMSTART1_ipd after IN_DELAY; TXCOMTYPE0_indelay <= TXCOMTYPE0_ipd after IN_DELAY; TXCOMTYPE1_indelay <= TXCOMTYPE1_ipd after IN_DELAY; TXDATA0_indelay <= TXDATA0_ipd after IN_DELAY; TXDATA1_indelay <= TXDATA1_ipd after IN_DELAY; TXDATAWIDTH0_indelay <= TXDATAWIDTH0_ipd after IN_DELAY; TXDATAWIDTH1_indelay <= TXDATAWIDTH1_ipd after IN_DELAY; TXDETECTRX0_indelay <= TXDETECTRX0_ipd after IN_DELAY; TXDETECTRX1_indelay <= TXDETECTRX1_ipd after IN_DELAY; TXDIFFCTRL0_indelay <= TXDIFFCTRL0_ipd after IN_DELAY; TXDIFFCTRL1_indelay <= TXDIFFCTRL1_ipd after IN_DELAY; TXELECIDLE0_indelay <= TXELECIDLE0_ipd after IN_DELAY; TXELECIDLE1_indelay <= TXELECIDLE1_ipd after IN_DELAY; TXENC8B10BUSE0_indelay <= TXENC8B10BUSE0_ipd after IN_DELAY; TXENC8B10BUSE1_indelay <= TXENC8B10BUSE1_ipd after IN_DELAY; TXENPMAPHASEALIGN_indelay <= TXENPMAPHASEALIGN_ipd after IN_DELAY; TXENPRBSTST0_indelay <= TXENPRBSTST0_ipd after IN_DELAY; TXENPRBSTST1_indelay <= TXENPRBSTST1_ipd after IN_DELAY; TXINHIBIT0_indelay <= TXINHIBIT0_ipd after IN_DELAY; TXINHIBIT1_indelay <= TXINHIBIT1_ipd after IN_DELAY; TXPMASETPHASE_indelay <= TXPMASETPHASE_ipd after IN_DELAY; TXPOLARITY0_indelay <= TXPOLARITY0_ipd after IN_DELAY; TXPOLARITY1_indelay <= TXPOLARITY1_ipd after IN_DELAY; TXPOWERDOWN0_indelay <= TXPOWERDOWN0_ipd after IN_DELAY; TXPOWERDOWN1_indelay <= TXPOWERDOWN1_ipd after IN_DELAY; TXPREEMPHASIS0_indelay <= TXPREEMPHASIS0_ipd after IN_DELAY; TXPREEMPHASIS1_indelay <= TXPREEMPHASIS1_ipd after IN_DELAY; TXRESET0_indelay <= TXRESET0_ipd after IN_DELAY; TXRESET1_indelay <= TXRESET1_ipd after IN_DELAY; legacy_model: if SIM_MODE = "LEGACY" generate gtp_dual_swift_bw_1 : GTP_DUAL_SWIFT port map ( AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, CLK25_DIVIDER => CLK25_DIVIDER_BINARY, CLKINDC_B => CLKINDC_B_BINARY, CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, PCS_COM_CFG => PCS_COM_CFG_BINARY, PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, PLL_SATA_0 => PLL_SATA_0_BINARY, PLL_SATA_1 => PLL_SATA_1_BINARY, PLL_TXDIVSEL_COMM_OUT => PLL_TXDIVSEL_COMM_OUT_BINARY, PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, RCV_TERM_MID_0 => RCV_TERM_MID_0_BINARY, RCV_TERM_MID_1 => RCV_TERM_MID_1_BINARY, RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, SIM_GTPRESET_SPEEDUP => SIM_GTPRESET_SPEEDUP_BINARY, SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, SIM_RECEIVER_DETECT_PASS0 => SIM_RECEIVER_DETECT_PASS0_BINARY, SIM_RECEIVER_DETECT_PASS1 => SIM_RECEIVER_DETECT_PASS1_BINARY, TERMINATION_CTRL => TERMINATION_CTRL_BINARY, TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, TERMINATION_OVRD => TERMINATION_OVRD_BINARY, TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, TX_DIFF_BOOST_0 => TX_DIFF_BOOST_0_BINARY, TX_DIFF_BOOST_1 => TX_DIFF_BOOST_1_BINARY, TX_SYNC_FILTERB => TX_SYNC_FILTERB_BINARY, TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, DO => DO_outdelay, DRDY => DRDY_outdelay, PHYSTATUS0 => PHYSTATUS0_outdelay, PHYSTATUS1 => PHYSTATUS1_outdelay, PLLLKDET => PLLLKDET_outdelay, REFCLKOUT => REFCLKOUT_outdelay, RESETDONE0 => RESETDONE0_outdelay, RESETDONE1 => RESETDONE1_outdelay, RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, RXCHARISK0 => RXCHARISK0_outdelay, RXCHARISK1 => RXCHARISK1_outdelay, RXCHBONDO0 => RXCHBONDO0_outdelay, RXCHBONDO1 => RXCHBONDO1_outdelay, RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, RXCOMMADET0 => RXCOMMADET0_outdelay, RXCOMMADET1 => RXCOMMADET1_outdelay, RXDATA0 => RXDATA0_outdelay, RXDATA1 => RXDATA1_outdelay, RXDISPERR0 => RXDISPERR0_outdelay, RXDISPERR1 => RXDISPERR1_outdelay, RXELECIDLE0 => RXELECIDLE0_outdelay, RXELECIDLE1 => RXELECIDLE1_outdelay, RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, RXPRBSERR0 => RXPRBSERR0_outdelay, RXPRBSERR1 => RXPRBSERR1_outdelay, RXRECCLK0 => RXRECCLK0_outdelay, RXRECCLK1 => RXRECCLK1_outdelay, RXRUNDISP0 => RXRUNDISP0_outdelay, RXRUNDISP1 => RXRUNDISP1_outdelay, RXSTATUS0 => RXSTATUS0_outdelay, RXSTATUS1 => RXSTATUS1_outdelay, RXVALID0 => RXVALID0_outdelay, RXVALID1 => RXVALID1_outdelay, TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, TXKERR0 => TXKERR0_outdelay, TXKERR1 => TXKERR1_outdelay, TXN0 => TXN0_outdelay, TXN1 => TXN1_outdelay, TXOUTCLK0 => TXOUTCLK0_outdelay, TXOUTCLK1 => TXOUTCLK1_outdelay, TXP0 => TXP0_outdelay, TXP1 => TXP1_outdelay, TXRUNDISP0 => TXRUNDISP0_outdelay, TXRUNDISP1 => TXRUNDISP1_outdelay, CLKIN => CLKIN_indelay, DADDR => DADDR_indelay, DCLK => DCLK_indelay, DEN => DEN_indelay, DI => DI_indelay, DWE => DWE_indelay, GSR => GSR, GTPRESET => GTPRESET_indelay, GTPTEST => GTPTEST_indelay, INTDATAWIDTH => INTDATAWIDTH_indelay, LOOPBACK0 => LOOPBACK0_indelay, LOOPBACK1 => LOOPBACK1_indelay, PLLLKDETEN => PLLLKDETEN_indelay, PLLPOWERDOWN => PLLPOWERDOWN_indelay, PRBSCNTRESET0 => PRBSCNTRESET0_indelay, PRBSCNTRESET1 => PRBSCNTRESET1_indelay, REFCLKPWRDNB => REFCLKPWRDNB_indelay, RXBUFRESET0 => RXBUFRESET0_indelay, RXBUFRESET1 => RXBUFRESET1_indelay, RXCDRRESET0 => RXCDRRESET0_indelay, RXCDRRESET1 => RXCDRRESET1_indelay, RXCHBONDI0 => RXCHBONDI0_indelay, RXCHBONDI1 => RXCHBONDI1_indelay, RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, RXDATAWIDTH0 => RXDATAWIDTH0_indelay, RXDATAWIDTH1 => RXDATAWIDTH1_indelay, RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, RXELECIDLERESET0 => RXELECIDLERESET0_indelay, RXELECIDLERESET1 => RXELECIDLERESET1_indelay, RXENCHANSYNC0 => RXENCHANSYNC0_indelay, RXENCHANSYNC1 => RXENCHANSYNC1_indelay, RXENELECIDLERESETB => RXENELECIDLERESETB_indelay, RXENEQB0 => RXENEQB0_indelay, RXENEQB1 => RXENEQB1_indelay, RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, RXENPRBSTST0 => RXENPRBSTST0_indelay, RXENPRBSTST1 => RXENPRBSTST1_indelay, RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, RXEQMIX0 => RXEQMIX0_indelay, RXEQMIX1 => RXEQMIX1_indelay, RXEQPOLE0 => RXEQPOLE0_indelay, RXEQPOLE1 => RXEQPOLE1_indelay, RXN0 => RXN0_indelay, RXN1 => RXN1_indelay, RXP0 => RXP0_indelay, RXP1 => RXP1_indelay, RXPMASETPHASE0 => RXPMASETPHASE0_indelay, RXPMASETPHASE1 => RXPMASETPHASE1_indelay, RXPOLARITY0 => RXPOLARITY0_indelay, RXPOLARITY1 => RXPOLARITY1_indelay, RXPOWERDOWN0 => RXPOWERDOWN0_indelay, RXPOWERDOWN1 => RXPOWERDOWN1_indelay, RXRESET0 => RXRESET0_indelay, RXRESET1 => RXRESET1_indelay, RXSLIDE0 => RXSLIDE0_indelay, RXSLIDE1 => RXSLIDE1_indelay, RXUSRCLK0 => RXUSRCLK0_indelay, RXUSRCLK1 => RXUSRCLK1_indelay, RXUSRCLK20 => RXUSRCLK20_indelay, RXUSRCLK21 => RXUSRCLK21_indelay, TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, TXCHARISK0 => TXCHARISK0_indelay, TXCHARISK1 => TXCHARISK1_indelay, TXCOMSTART0 => TXCOMSTART0_indelay, TXCOMSTART1 => TXCOMSTART1_indelay, TXCOMTYPE0 => TXCOMTYPE0_indelay, TXCOMTYPE1 => TXCOMTYPE1_indelay, TXDATA0 => TXDATA0_indelay, TXDATA1 => TXDATA1_indelay, TXDATAWIDTH0 => TXDATAWIDTH0_indelay, TXDATAWIDTH1 => TXDATAWIDTH1_indelay, TXDETECTRX0 => TXDETECTRX0_indelay, TXDETECTRX1 => TXDETECTRX1_indelay, TXDIFFCTRL0 => TXDIFFCTRL0_indelay, TXDIFFCTRL1 => TXDIFFCTRL1_indelay, TXELECIDLE0 => TXELECIDLE0_indelay, TXELECIDLE1 => TXELECIDLE1_indelay, TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_indelay, TXENPRBSTST0 => TXENPRBSTST0_indelay, TXENPRBSTST1 => TXENPRBSTST1_indelay, TXINHIBIT0 => TXINHIBIT0_indelay, TXINHIBIT1 => TXINHIBIT1_indelay, TXPMASETPHASE => TXPMASETPHASE_indelay, TXPOLARITY0 => TXPOLARITY0_indelay, TXPOLARITY1 => TXPOLARITY1_indelay, TXPOWERDOWN0 => TXPOWERDOWN0_indelay, TXPOWERDOWN1 => TXPOWERDOWN1_indelay, TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, TXRESET0 => TXRESET0_indelay, TXRESET1 => TXRESET1_indelay, TXUSRCLK0 => TXUSRCLK0_indelay, TXUSRCLK1 => TXUSRCLK1_indelay, TXUSRCLK20 => TXUSRCLK20_indelay, TXUSRCLK21 => TXUSRCLK21_indelay ); end generate legacy_model; fast_model: if SIM_MODE = "FAST" generate gtp_dual_fast_bw_1 : GTP_DUAL_FAST port map ( AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, CLK25_DIVIDER => CLK25_DIVIDER_BINARY, CLKINDC_B => CLKINDC_B_BINARY, CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, PCS_COM_CFG => PCS_COM_CFG_BINARY, PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, PLL_SATA_0 => PLL_SATA_0_BINARY, PLL_SATA_1 => PLL_SATA_1_BINARY, PLL_TXDIVSEL_COMM_OUT => PLL_TXDIVSEL_COMM_OUT_BINARY, PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, RCV_TERM_MID_0 => RCV_TERM_MID_0_BINARY, RCV_TERM_MID_1 => RCV_TERM_MID_1_BINARY, RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, SIM_GTPRESET_SPEEDUP => SIM_GTPRESET_SPEEDUP_BINARY, SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, SIM_RECEIVER_DETECT_PASS0 => SIM_RECEIVER_DETECT_PASS0_BINARY, SIM_RECEIVER_DETECT_PASS1 => SIM_RECEIVER_DETECT_PASS1_BINARY, TERMINATION_CTRL => TERMINATION_CTRL_BINARY, TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, TERMINATION_OVRD => TERMINATION_OVRD_BINARY, TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, TX_DIFF_BOOST_0 => TX_DIFF_BOOST_0_BINARY, TX_DIFF_BOOST_1 => TX_DIFF_BOOST_1_BINARY, TX_SYNC_FILTERB => TX_SYNC_FILTERB_BINARY, TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, DO => DO_outdelay, DRDY => DRDY_outdelay, PHYSTATUS0 => PHYSTATUS0_outdelay, PHYSTATUS1 => PHYSTATUS1_outdelay, PLLLKDET => PLLLKDET_outdelay, REFCLKOUT => REFCLKOUT_outdelay, RESETDONE0 => RESETDONE0_outdelay, RESETDONE1 => RESETDONE1_outdelay, RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, RXCHARISK0 => RXCHARISK0_outdelay, RXCHARISK1 => RXCHARISK1_outdelay, RXCHBONDO0 => RXCHBONDO0_outdelay, RXCHBONDO1 => RXCHBONDO1_outdelay, RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, RXCOMMADET0 => RXCOMMADET0_outdelay, RXCOMMADET1 => RXCOMMADET1_outdelay, RXDATA0 => RXDATA0_outdelay, RXDATA1 => RXDATA1_outdelay, RXDISPERR0 => RXDISPERR0_outdelay, RXDISPERR1 => RXDISPERR1_outdelay, RXELECIDLE0 => RXELECIDLE0_outdelay, RXELECIDLE1 => RXELECIDLE1_outdelay, RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, RXPRBSERR0 => RXPRBSERR0_outdelay, RXPRBSERR1 => RXPRBSERR1_outdelay, RXRECCLK0 => RXRECCLK0_outdelay, RXRECCLK1 => RXRECCLK1_outdelay, RXRUNDISP0 => RXRUNDISP0_outdelay, RXRUNDISP1 => RXRUNDISP1_outdelay, RXSTATUS0 => RXSTATUS0_outdelay, RXSTATUS1 => RXSTATUS1_outdelay, RXVALID0 => RXVALID0_outdelay, RXVALID1 => RXVALID1_outdelay, TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, TXKERR0 => TXKERR0_outdelay, TXKERR1 => TXKERR1_outdelay, TXN0 => TXN0_outdelay, TXN1 => TXN1_outdelay, TXOUTCLK0 => TXOUTCLK0_outdelay, TXOUTCLK1 => TXOUTCLK1_outdelay, TXP0 => TXP0_outdelay, TXP1 => TXP1_outdelay, TXRUNDISP0 => TXRUNDISP0_outdelay, TXRUNDISP1 => TXRUNDISP1_outdelay, CLKIN => CLKIN_indelay, DADDR => DADDR_indelay, DCLK => DCLK_indelay, DEN => DEN_indelay, DI => DI_indelay, DWE => DWE_indelay, GSR => GSR, GTPRESET => GTPRESET_indelay, GTPTEST => GTPTEST_indelay, INTDATAWIDTH => INTDATAWIDTH_indelay, LOOPBACK0 => LOOPBACK0_indelay, LOOPBACK1 => LOOPBACK1_indelay, PLLLKDETEN => PLLLKDETEN_indelay, PLLPOWERDOWN => PLLPOWERDOWN_indelay, PRBSCNTRESET0 => PRBSCNTRESET0_indelay, PRBSCNTRESET1 => PRBSCNTRESET1_indelay, REFCLKPWRDNB => REFCLKPWRDNB_indelay, RXBUFRESET0 => RXBUFRESET0_indelay, RXBUFRESET1 => RXBUFRESET1_indelay, RXCDRRESET0 => RXCDRRESET0_indelay, RXCDRRESET1 => RXCDRRESET1_indelay, RXCHBONDI0 => RXCHBONDI0_indelay, RXCHBONDI1 => RXCHBONDI1_indelay, RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, RXDATAWIDTH0 => RXDATAWIDTH0_indelay, RXDATAWIDTH1 => RXDATAWIDTH1_indelay, RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, RXELECIDLERESET0 => RXELECIDLERESET0_indelay, RXELECIDLERESET1 => RXELECIDLERESET1_indelay, RXENCHANSYNC0 => RXENCHANSYNC0_indelay, RXENCHANSYNC1 => RXENCHANSYNC1_indelay, RXENELECIDLERESETB => RXENELECIDLERESETB_indelay, RXENEQB0 => RXENEQB0_indelay, RXENEQB1 => RXENEQB1_indelay, RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, RXENPRBSTST0 => RXENPRBSTST0_indelay, RXENPRBSTST1 => RXENPRBSTST1_indelay, RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, RXEQMIX0 => RXEQMIX0_indelay, RXEQMIX1 => RXEQMIX1_indelay, RXEQPOLE0 => RXEQPOLE0_indelay, RXEQPOLE1 => RXEQPOLE1_indelay, RXN0 => RXN0_indelay, RXN1 => RXN1_indelay, RXP0 => RXP0_indelay, RXP1 => RXP1_indelay, RXPMASETPHASE0 => RXPMASETPHASE0_indelay, RXPMASETPHASE1 => RXPMASETPHASE1_indelay, RXPOLARITY0 => RXPOLARITY0_indelay, RXPOLARITY1 => RXPOLARITY1_indelay, RXPOWERDOWN0 => RXPOWERDOWN0_indelay, RXPOWERDOWN1 => RXPOWERDOWN1_indelay, RXRESET0 => RXRESET0_indelay, RXRESET1 => RXRESET1_indelay, RXSLIDE0 => RXSLIDE0_indelay, RXSLIDE1 => RXSLIDE1_indelay, RXUSRCLK0 => RXUSRCLK0_indelay, RXUSRCLK1 => RXUSRCLK1_indelay, RXUSRCLK20 => RXUSRCLK20_indelay, RXUSRCLK21 => RXUSRCLK21_indelay, TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, TXCHARISK0 => TXCHARISK0_indelay, TXCHARISK1 => TXCHARISK1_indelay, TXCOMSTART0 => TXCOMSTART0_indelay, TXCOMSTART1 => TXCOMSTART1_indelay, TXCOMTYPE0 => TXCOMTYPE0_indelay, TXCOMTYPE1 => TXCOMTYPE1_indelay, TXDATA0 => TXDATA0_indelay, TXDATA1 => TXDATA1_indelay, TXDATAWIDTH0 => TXDATAWIDTH0_indelay, TXDATAWIDTH1 => TXDATAWIDTH1_indelay, TXDETECTRX0 => TXDETECTRX0_indelay, TXDETECTRX1 => TXDETECTRX1_indelay, TXDIFFCTRL0 => TXDIFFCTRL0_indelay, TXDIFFCTRL1 => TXDIFFCTRL1_indelay, TXELECIDLE0 => TXELECIDLE0_indelay, TXELECIDLE1 => TXELECIDLE1_indelay, TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_indelay, TXENPRBSTST0 => TXENPRBSTST0_indelay, TXENPRBSTST1 => TXENPRBSTST1_indelay, TXINHIBIT0 => TXINHIBIT0_indelay, TXINHIBIT1 => TXINHIBIT1_indelay, TXPMASETPHASE => TXPMASETPHASE_indelay, TXPOLARITY0 => TXPOLARITY0_indelay, TXPOLARITY1 => TXPOLARITY1_indelay, TXPOWERDOWN0 => TXPOWERDOWN0_indelay, TXPOWERDOWN1 => TXPOWERDOWN1_indelay, TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, TXRESET0 => TXRESET0_indelay, TXRESET1 => TXRESET1_indelay, TXUSRCLK0 => TXUSRCLK0_indelay, TXUSRCLK1 => TXUSRCLK1_indelay, TXUSRCLK20 => TXUSRCLK20_indelay, TXUSRCLK21 => TXUSRCLK21_indelay ); end generate fast_model; INIPROC : process begin case PLL_TXDIVSEL_OUT_0 is when 1 => PLL_TXDIVSEL_OUT_0_BINARY <= "00"; when 2 => PLL_TXDIVSEL_OUT_0_BINARY <= "01"; when 4 => PLL_TXDIVSEL_OUT_0_BINARY <= "10"; when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; end case; case PLL_RXDIVSEL_OUT_0 is when 1 => PLL_RXDIVSEL_OUT_0_BINARY <= "00"; when 2 => PLL_RXDIVSEL_OUT_0_BINARY <= "01"; when 4 => PLL_RXDIVSEL_OUT_0_BINARY <= "10"; when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; end case; case PLL_TXDIVSEL_OUT_1 is when 1 => PLL_TXDIVSEL_OUT_1_BINARY <= "00"; when 2 => PLL_TXDIVSEL_OUT_1_BINARY <= "01"; when 4 => PLL_TXDIVSEL_OUT_1_BINARY <= "10"; when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; end case; case PLL_RXDIVSEL_OUT_1 is when 1 => PLL_RXDIVSEL_OUT_1_BINARY <= "00"; when 2 => PLL_RXDIVSEL_OUT_1_BINARY <= "01"; when 4 => PLL_RXDIVSEL_OUT_1_BINARY <= "10"; when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; end case; case PLL_DIVSEL_FB is when 1 => PLL_DIVSEL_FB_BINARY <= "10000"; when 2 => PLL_DIVSEL_FB_BINARY <= "00000"; when 3 => PLL_DIVSEL_FB_BINARY <= "00001"; when 4 => PLL_DIVSEL_FB_BINARY <= "00010"; when 5 => PLL_DIVSEL_FB_BINARY <= "00011"; when 8 => PLL_DIVSEL_FB_BINARY <= "00110"; when 10 => PLL_DIVSEL_FB_BINARY <= "00111"; when others => assert FALSE report "Error : PLL_DIVSEL_FB is not in 1, 2, 3, 4, 5, 8, 10." severity error; end case; case PLL_DIVSEL_REF is when 1 => PLL_DIVSEL_REF_BINARY <= "010000"; when 2 => PLL_DIVSEL_REF_BINARY <= "000000"; when 3 => PLL_DIVSEL_REF_BINARY <= "000001"; when 4 => PLL_DIVSEL_REF_BINARY <= "000010"; when 5 => PLL_DIVSEL_REF_BINARY <= "000011"; when 6 => PLL_DIVSEL_REF_BINARY <= "000101"; when 8 => PLL_DIVSEL_REF_BINARY <= "000110"; when 10 => PLL_DIVSEL_REF_BINARY <= "000111"; when 12 => PLL_DIVSEL_REF_BINARY <= "001101"; when 16 => PLL_DIVSEL_REF_BINARY <= "001110"; when 20 => PLL_DIVSEL_REF_BINARY <= "001111"; when others => assert FALSE report "Error : PLL_DIVSEL_REF is not in 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20." severity error; end case; case PLL_TXDIVSEL_COMM_OUT is when 1 => PLL_TXDIVSEL_COMM_OUT_BINARY <= "00"; when 2 => PLL_TXDIVSEL_COMM_OUT_BINARY <= "01"; when 4 => PLL_TXDIVSEL_COMM_OUT_BINARY <= "10"; when others => assert FALSE report "Error : PLL_TXDIVSEL_COMM_OUT is not in 1, 2, 4." severity error; end case; case PLL_SATA_0 is when FALSE => PLL_SATA_0_BINARY <= '0'; when TRUE => PLL_SATA_0_BINARY <= '1'; when others => assert FALSE report "Error : PLL_SATA_0 is neither TRUE nor FALSE." severity error; end case; case PLL_SATA_1 is when FALSE => PLL_SATA_1_BINARY <= '0'; when TRUE => PLL_SATA_1_BINARY <= '1'; when others => assert FALSE report "Error : PLL_SATA_1 is neither TRUE nor FALSE." severity error; end case; case TX_DIFF_BOOST_0 is when FALSE => TX_DIFF_BOOST_0_BINARY <= '0'; when TRUE => TX_DIFF_BOOST_0_BINARY <= '1'; when others => assert FALSE report "Error : TX_DIFF_BOOST_0 is neither TRUE nor FALSE." severity error; end case; case TX_DIFF_BOOST_1 is when FALSE => TX_DIFF_BOOST_1_BINARY <= '0'; when TRUE => TX_DIFF_BOOST_1_BINARY <= '1'; when others => assert FALSE report "Error : TX_DIFF_BOOST_1 is neither TRUE nor FALSE." severity error; end case; case OOB_CLK_DIVIDER is when 1 => OOB_CLK_DIVIDER_BINARY <= "000"; when 2 => OOB_CLK_DIVIDER_BINARY <= "001"; when 4 => OOB_CLK_DIVIDER_BINARY <= "010"; when 6 => OOB_CLK_DIVIDER_BINARY <= "011"; when 8 => OOB_CLK_DIVIDER_BINARY <= "100"; when 10 => OOB_CLK_DIVIDER_BINARY <= "101"; when 12 => OOB_CLK_DIVIDER_BINARY <= "110"; when 14 => OOB_CLK_DIVIDER_BINARY <= "111"; when others => assert FALSE report "Error : OOB_CLK_DIVIDER is not in 1, 2, 4, 6, 8, 10, 12, 14." severity error; end case; case TX_SYNC_FILTERB is when 0 => TX_SYNC_FILTERB_BINARY <= '0'; when 1 => TX_SYNC_FILTERB_BINARY <= '1'; when others => assert FALSE report "Error : TX_SYNC_FILTERB is not in 0, 1." severity error; end case; case AC_CAP_DIS_0 is when FALSE => AC_CAP_DIS_0_BINARY <= '0'; when TRUE => AC_CAP_DIS_0_BINARY <= '1'; when others => assert FALSE report "Error : AC_CAP_DIS_0 is neither TRUE nor FALSE." severity error; end case; case AC_CAP_DIS_1 is when FALSE => AC_CAP_DIS_1_BINARY <= '0'; when TRUE => AC_CAP_DIS_1_BINARY <= '1'; when others => assert FALSE report "Error : AC_CAP_DIS_1 is neither TRUE nor FALSE." severity error; end case; case RCV_TERM_GND_0 is when FALSE => RCV_TERM_GND_0_BINARY <= '0'; when TRUE => RCV_TERM_GND_0_BINARY <= '1'; when others => assert FALSE report "Error : RCV_TERM_GND_0 is neither TRUE nor FALSE." severity error; end case; case RCV_TERM_GND_1 is when FALSE => RCV_TERM_GND_1_BINARY <= '0'; when TRUE => RCV_TERM_GND_1_BINARY <= '1'; when others => assert FALSE report "Error : RCV_TERM_GND_1 is neither TRUE nor FALSE." severity error; end case; case RCV_TERM_MID_0 is when FALSE => RCV_TERM_MID_0_BINARY <= '0'; when TRUE => RCV_TERM_MID_0_BINARY <= '1'; when others => assert FALSE report "Error : RCV_TERM_MID_0 is neither TRUE nor FALSE." severity error; end case; case RCV_TERM_MID_1 is when FALSE => RCV_TERM_MID_1_BINARY <= '0'; when TRUE => RCV_TERM_MID_1_BINARY <= '1'; when others => assert FALSE report "Error : RCV_TERM_MID_1 is neither TRUE nor FALSE." severity error; end case; case TERMINATION_IMP_0 is when 50 => TERMINATION_IMP_0_BINARY <= '0'; when 75 => TERMINATION_IMP_0_BINARY <= '1'; when others => assert FALSE report "Error : TERMINATION_IMP_0 is not in 50, 75." severity error; end case; case TERMINATION_IMP_1 is when 50 => TERMINATION_IMP_1_BINARY <= '0'; when 75 => TERMINATION_IMP_1_BINARY <= '1'; when others => assert FALSE report "Error : TERMINATION_IMP_1 is not in 50, 75." severity error; end case; case TERMINATION_OVRD is when FALSE => TERMINATION_OVRD_BINARY <= '0'; when TRUE => TERMINATION_OVRD_BINARY <= '1'; when others => assert FALSE report "Error : TERMINATION_OVRD is neither TRUE nor FALSE." severity error; end case; case RCV_TERM_VTTRX_0 is when FALSE => RCV_TERM_VTTRX_0_BINARY <= '0'; when TRUE => RCV_TERM_VTTRX_0_BINARY <= '1'; when others => assert FALSE report "Error : RCV_TERM_VTTRX_0 is neither TRUE nor FALSE." severity error; end case; case RCV_TERM_VTTRX_1 is when FALSE => RCV_TERM_VTTRX_1_BINARY <= '0'; when TRUE => RCV_TERM_VTTRX_1_BINARY <= '1'; when others => assert FALSE report "Error : RCV_TERM_VTTRX_1 is neither TRUE nor FALSE." severity error; end case; case CLKINDC_B is when FALSE => CLKINDC_B_BINARY <= '0'; when TRUE => CLKINDC_B_BINARY <= '1'; when others => assert FALSE report "Error : CLKINDC_B is neither TRUE nor FALSE." severity error; end case; case PCOMMA_DETECT_0 is when FALSE => PCOMMA_DETECT_0_BINARY <= '0'; when TRUE => PCOMMA_DETECT_0_BINARY <= '1'; when others => assert FALSE report "Error : PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; end case; case MCOMMA_DETECT_0 is when FALSE => MCOMMA_DETECT_0_BINARY <= '0'; when TRUE => MCOMMA_DETECT_0_BINARY <= '1'; when others => assert FALSE report "Error : MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; end case; case COMMA_DOUBLE_0 is when FALSE => COMMA_DOUBLE_0_BINARY <= '0'; when TRUE => COMMA_DOUBLE_0_BINARY <= '1'; when others => assert FALSE report "Error : COMMA_DOUBLE_0 is neither TRUE nor FALSE." severity error; end case; case ALIGN_COMMA_WORD_0 is when 1 => ALIGN_COMMA_WORD_0_BINARY <= '0'; when 2 => ALIGN_COMMA_WORD_0_BINARY <= '1'; when others => assert FALSE report "Error : ALIGN_COMMA_WORD_0 is not in 1, 2." severity error; end case; case DEC_PCOMMA_DETECT_0 is when FALSE => DEC_PCOMMA_DETECT_0_BINARY <= '0'; when TRUE => DEC_PCOMMA_DETECT_0_BINARY <= '1'; when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; end case; case DEC_MCOMMA_DETECT_0 is when FALSE => DEC_MCOMMA_DETECT_0_BINARY <= '0'; when TRUE => DEC_MCOMMA_DETECT_0_BINARY <= '1'; when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; end case; case DEC_VALID_COMMA_ONLY_0 is when FALSE => DEC_VALID_COMMA_ONLY_0_BINARY <= '0'; when TRUE => DEC_VALID_COMMA_ONLY_0_BINARY <= '1'; when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_0 is neither TRUE nor FALSE." severity error; end case; case PCOMMA_DETECT_1 is when FALSE => PCOMMA_DETECT_1_BINARY <= '0'; when TRUE => PCOMMA_DETECT_1_BINARY <= '1'; when others => assert FALSE report "Error : PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; end case; case MCOMMA_DETECT_1 is when FALSE => MCOMMA_DETECT_1_BINARY <= '0'; when TRUE => MCOMMA_DETECT_1_BINARY <= '1'; when others => assert FALSE report "Error : MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; end case; case COMMA_DOUBLE_1 is when FALSE => COMMA_DOUBLE_1_BINARY <= '0'; when TRUE => COMMA_DOUBLE_1_BINARY <= '1'; when others => assert FALSE report "Error : COMMA_DOUBLE_1 is neither TRUE nor FALSE." severity error; end case; case ALIGN_COMMA_WORD_1 is when 1 => ALIGN_COMMA_WORD_1_BINARY <= '0'; when 2 => ALIGN_COMMA_WORD_1_BINARY <= '1'; when others => assert FALSE report "Error : ALIGN_COMMA_WORD_1 is not in 1, 2." severity error; end case; case DEC_PCOMMA_DETECT_1 is when FALSE => DEC_PCOMMA_DETECT_1_BINARY <= '0'; when TRUE => DEC_PCOMMA_DETECT_1_BINARY <= '1'; when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; end case; case DEC_MCOMMA_DETECT_1 is when FALSE => DEC_MCOMMA_DETECT_1_BINARY <= '0'; when TRUE => DEC_MCOMMA_DETECT_1_BINARY <= '1'; when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; end case; case DEC_VALID_COMMA_ONLY_1 is when FALSE => DEC_VALID_COMMA_ONLY_1_BINARY <= '0'; when TRUE => DEC_VALID_COMMA_ONLY_1_BINARY <= '1'; when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_1 is neither TRUE nor FALSE." severity error; end case; case RX_LOSS_OF_SYNC_FSM_0 is when FALSE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '0'; when TRUE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '1'; when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_0 is neither TRUE nor FALSE." severity error; end case; case RX_LOS_INVALID_INCR_0 is when 1 => RX_LOS_INVALID_INCR_0_BINARY <= "000"; when 2 => RX_LOS_INVALID_INCR_0_BINARY <= "001"; when 4 => RX_LOS_INVALID_INCR_0_BINARY <= "010"; when 8 => RX_LOS_INVALID_INCR_0_BINARY <= "011"; when 16 => RX_LOS_INVALID_INCR_0_BINARY <= "100"; when 32 => RX_LOS_INVALID_INCR_0_BINARY <= "101"; when 64 => RX_LOS_INVALID_INCR_0_BINARY <= "110"; when 128 => RX_LOS_INVALID_INCR_0_BINARY <= "111"; when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_0 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; end case; case RX_LOS_THRESHOLD_0 is when 4 => RX_LOS_THRESHOLD_0_BINARY <= "000"; when 8 => RX_LOS_THRESHOLD_0_BINARY <= "001"; when 16 => RX_LOS_THRESHOLD_0_BINARY <= "010"; when 32 => RX_LOS_THRESHOLD_0_BINARY <= "011"; when 64 => RX_LOS_THRESHOLD_0_BINARY <= "100"; when 128 => RX_LOS_THRESHOLD_0_BINARY <= "101"; when 256 => RX_LOS_THRESHOLD_0_BINARY <= "110"; when 512 => RX_LOS_THRESHOLD_0_BINARY <= "111"; when others => assert FALSE report "Error : RX_LOS_THRESHOLD_0 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; end case; case RX_LOSS_OF_SYNC_FSM_1 is when FALSE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '0'; when TRUE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '1'; when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_1 is neither TRUE nor FALSE." severity error; end case; case RX_LOS_INVALID_INCR_1 is when 1 => RX_LOS_INVALID_INCR_1_BINARY <= "000"; when 2 => RX_LOS_INVALID_INCR_1_BINARY <= "001"; when 4 => RX_LOS_INVALID_INCR_1_BINARY <= "010"; when 8 => RX_LOS_INVALID_INCR_1_BINARY <= "011"; when 16 => RX_LOS_INVALID_INCR_1_BINARY <= "100"; when 32 => RX_LOS_INVALID_INCR_1_BINARY <= "101"; when 64 => RX_LOS_INVALID_INCR_1_BINARY <= "110"; when 128 => RX_LOS_INVALID_INCR_1_BINARY <= "111"; when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_1 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; end case; case RX_LOS_THRESHOLD_1 is when 4 => RX_LOS_THRESHOLD_1_BINARY <= "000"; when 8 => RX_LOS_THRESHOLD_1_BINARY <= "001"; when 16 => RX_LOS_THRESHOLD_1_BINARY <= "010"; when 32 => RX_LOS_THRESHOLD_1_BINARY <= "011"; when 64 => RX_LOS_THRESHOLD_1_BINARY <= "100"; when 128 => RX_LOS_THRESHOLD_1_BINARY <= "101"; when 256 => RX_LOS_THRESHOLD_1_BINARY <= "110"; when 512 => RX_LOS_THRESHOLD_1_BINARY <= "111"; when others => assert FALSE report "Error : RX_LOS_THRESHOLD_1 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; end case; case RX_BUFFER_USE_0 is when FALSE => RX_BUFFER_USE_0_BINARY <= '0'; when TRUE => RX_BUFFER_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : RX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; end case; case RX_DECODE_SEQ_MATCH_0 is when FALSE => RX_DECODE_SEQ_MATCH_0_BINARY <= '0'; when TRUE => RX_DECODE_SEQ_MATCH_0_BINARY <= '1'; when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_0 is neither TRUE nor FALSE." severity error; end case; case RX_BUFFER_USE_1 is when FALSE => RX_BUFFER_USE_1_BINARY <= '0'; when TRUE => RX_BUFFER_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : RX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; end case; case RX_DECODE_SEQ_MATCH_1 is when FALSE => RX_DECODE_SEQ_MATCH_1_BINARY <= '0'; when TRUE => RX_DECODE_SEQ_MATCH_1_BINARY <= '1'; when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_1 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_MIN_LAT_0 is when 3 => CLK_COR_MIN_LAT_0_BINARY <= "000011"; when 4 => CLK_COR_MIN_LAT_0_BINARY <= "000100"; when 5 => CLK_COR_MIN_LAT_0_BINARY <= "000101"; when 6 => CLK_COR_MIN_LAT_0_BINARY <= "000110"; when 7 => CLK_COR_MIN_LAT_0_BINARY <= "000111"; when 8 => CLK_COR_MIN_LAT_0_BINARY <= "001000"; when 9 => CLK_COR_MIN_LAT_0_BINARY <= "001001"; when 10 => CLK_COR_MIN_LAT_0_BINARY <= "001010"; when 11 => CLK_COR_MIN_LAT_0_BINARY <= "001011"; when 12 => CLK_COR_MIN_LAT_0_BINARY <= "001100"; when 13 => CLK_COR_MIN_LAT_0_BINARY <= "001101"; when 14 => CLK_COR_MIN_LAT_0_BINARY <= "001110"; when 15 => CLK_COR_MIN_LAT_0_BINARY <= "001111"; when 16 => CLK_COR_MIN_LAT_0_BINARY <= "010000"; when 17 => CLK_COR_MIN_LAT_0_BINARY <= "010001"; when 18 => CLK_COR_MIN_LAT_0_BINARY <= "010010"; when 19 => CLK_COR_MIN_LAT_0_BINARY <= "010011"; when 20 => CLK_COR_MIN_LAT_0_BINARY <= "010100"; when 21 => CLK_COR_MIN_LAT_0_BINARY <= "010101"; when 22 => CLK_COR_MIN_LAT_0_BINARY <= "010110"; when 23 => CLK_COR_MIN_LAT_0_BINARY <= "010111"; when 24 => CLK_COR_MIN_LAT_0_BINARY <= "011000"; when 25 => CLK_COR_MIN_LAT_0_BINARY <= "011001"; when 26 => CLK_COR_MIN_LAT_0_BINARY <= "011010"; when 27 => CLK_COR_MIN_LAT_0_BINARY <= "011011"; when 28 => CLK_COR_MIN_LAT_0_BINARY <= "011100"; when 29 => CLK_COR_MIN_LAT_0_BINARY <= "011101"; when 30 => CLK_COR_MIN_LAT_0_BINARY <= "011110"; when 31 => CLK_COR_MIN_LAT_0_BINARY <= "011111"; when 32 => CLK_COR_MIN_LAT_0_BINARY <= "100000"; when 33 => CLK_COR_MIN_LAT_0_BINARY <= "100001"; when 34 => CLK_COR_MIN_LAT_0_BINARY <= "100010"; when 35 => CLK_COR_MIN_LAT_0_BINARY <= "100011"; when 36 => CLK_COR_MIN_LAT_0_BINARY <= "100100"; when 37 => CLK_COR_MIN_LAT_0_BINARY <= "100101"; when 38 => CLK_COR_MIN_LAT_0_BINARY <= "100110"; when 39 => CLK_COR_MIN_LAT_0_BINARY <= "100111"; when 40 => CLK_COR_MIN_LAT_0_BINARY <= "101000"; when 41 => CLK_COR_MIN_LAT_0_BINARY <= "101001"; when 42 => CLK_COR_MIN_LAT_0_BINARY <= "101010"; when 43 => CLK_COR_MIN_LAT_0_BINARY <= "101011"; when 44 => CLK_COR_MIN_LAT_0_BINARY <= "101100"; when 45 => CLK_COR_MIN_LAT_0_BINARY <= "101101"; when 46 => CLK_COR_MIN_LAT_0_BINARY <= "101110"; when 47 => CLK_COR_MIN_LAT_0_BINARY <= "101111"; when 48 => CLK_COR_MIN_LAT_0_BINARY <= "110000"; when others => assert FALSE report "Error : CLK_COR_MIN_LAT_0 is not in range 3...48." severity error; end case; case CLK_COR_MAX_LAT_0 is when 3 => CLK_COR_MAX_LAT_0_BINARY <= "000011"; when 4 => CLK_COR_MAX_LAT_0_BINARY <= "000100"; when 5 => CLK_COR_MAX_LAT_0_BINARY <= "000101"; when 6 => CLK_COR_MAX_LAT_0_BINARY <= "000110"; when 7 => CLK_COR_MAX_LAT_0_BINARY <= "000111"; when 8 => CLK_COR_MAX_LAT_0_BINARY <= "001000"; when 9 => CLK_COR_MAX_LAT_0_BINARY <= "001001"; when 10 => CLK_COR_MAX_LAT_0_BINARY <= "001010"; when 11 => CLK_COR_MAX_LAT_0_BINARY <= "001011"; when 12 => CLK_COR_MAX_LAT_0_BINARY <= "001100"; when 13 => CLK_COR_MAX_LAT_0_BINARY <= "001101"; when 14 => CLK_COR_MAX_LAT_0_BINARY <= "001110"; when 15 => CLK_COR_MAX_LAT_0_BINARY <= "001111"; when 16 => CLK_COR_MAX_LAT_0_BINARY <= "010000"; when 17 => CLK_COR_MAX_LAT_0_BINARY <= "010001"; when 18 => CLK_COR_MAX_LAT_0_BINARY <= "010010"; when 19 => CLK_COR_MAX_LAT_0_BINARY <= "010011"; when 20 => CLK_COR_MAX_LAT_0_BINARY <= "010100"; when 21 => CLK_COR_MAX_LAT_0_BINARY <= "010101"; when 22 => CLK_COR_MAX_LAT_0_BINARY <= "010110"; when 23 => CLK_COR_MAX_LAT_0_BINARY <= "010111"; when 24 => CLK_COR_MAX_LAT_0_BINARY <= "011000"; when 25 => CLK_COR_MAX_LAT_0_BINARY <= "011001"; when 26 => CLK_COR_MAX_LAT_0_BINARY <= "011010"; when 27 => CLK_COR_MAX_LAT_0_BINARY <= "011011"; when 28 => CLK_COR_MAX_LAT_0_BINARY <= "011100"; when 29 => CLK_COR_MAX_LAT_0_BINARY <= "011101"; when 30 => CLK_COR_MAX_LAT_0_BINARY <= "011110"; when 31 => CLK_COR_MAX_LAT_0_BINARY <= "011111"; when 32 => CLK_COR_MAX_LAT_0_BINARY <= "100000"; when 33 => CLK_COR_MAX_LAT_0_BINARY <= "100001"; when 34 => CLK_COR_MAX_LAT_0_BINARY <= "100010"; when 35 => CLK_COR_MAX_LAT_0_BINARY <= "100011"; when 36 => CLK_COR_MAX_LAT_0_BINARY <= "100100"; when 37 => CLK_COR_MAX_LAT_0_BINARY <= "100101"; when 38 => CLK_COR_MAX_LAT_0_BINARY <= "100110"; when 39 => CLK_COR_MAX_LAT_0_BINARY <= "100111"; when 40 => CLK_COR_MAX_LAT_0_BINARY <= "101000"; when 41 => CLK_COR_MAX_LAT_0_BINARY <= "101001"; when 42 => CLK_COR_MAX_LAT_0_BINARY <= "101010"; when 43 => CLK_COR_MAX_LAT_0_BINARY <= "101011"; when 44 => CLK_COR_MAX_LAT_0_BINARY <= "101100"; when 45 => CLK_COR_MAX_LAT_0_BINARY <= "101101"; when 46 => CLK_COR_MAX_LAT_0_BINARY <= "101110"; when 47 => CLK_COR_MAX_LAT_0_BINARY <= "101111"; when 48 => CLK_COR_MAX_LAT_0_BINARY <= "110000"; when others => assert FALSE report "Error : CLK_COR_MAX_LAT_0 is not in range 3...48." severity error; end case; case CLK_CORRECT_USE_0 is when FALSE => CLK_CORRECT_USE_0_BINARY <= '0'; when TRUE => CLK_CORRECT_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : CLK_CORRECT_USE_0 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_PRECEDENCE_0 is when FALSE => CLK_COR_PRECEDENCE_0_BINARY <= '0'; when TRUE => CLK_COR_PRECEDENCE_0_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_0 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_DET_LEN_0 is when 1 => CLK_COR_DET_LEN_0_BINARY <= "00"; when 2 => CLK_COR_DET_LEN_0_BINARY <= "01"; when 3 => CLK_COR_DET_LEN_0_BINARY <= "10"; when 4 => CLK_COR_DET_LEN_0_BINARY <= "11"; when others => assert FALSE report "Error : CLK_COR_DET_LEN_0 is not in 1, 2, 3, 4." severity error; end case; case CLK_COR_ADJ_LEN_0 is when 1 => CLK_COR_ADJ_LEN_0_BINARY <= "00"; when 2 => CLK_COR_ADJ_LEN_0_BINARY <= "01"; when 3 => CLK_COR_ADJ_LEN_0_BINARY <= "10"; when 4 => CLK_COR_ADJ_LEN_0_BINARY <= "11"; when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_0 is not in 1, 2, 3, 4." severity error; end case; case CLK_COR_KEEP_IDLE_0 is when FALSE => CLK_COR_KEEP_IDLE_0_BINARY <= '0'; when TRUE => CLK_COR_KEEP_IDLE_0_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_0 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_INSERT_IDLE_FLAG_0 is when FALSE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '0'; when TRUE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_0 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_REPEAT_WAIT_0 is when 0 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00000"; when 1 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00001"; when 2 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00010"; when 3 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00011"; when 4 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00100"; when 5 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00101"; when 6 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00110"; when 7 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00111"; when 8 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01000"; when 9 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01001"; when 10 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01010"; when 11 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01011"; when 12 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01100"; when 13 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01101"; when 14 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01110"; when 15 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01111"; when 16 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10000"; when 17 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10001"; when 18 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10010"; when 19 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10011"; when 20 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10100"; when 21 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10101"; when 22 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10110"; when 23 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10111"; when 24 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11000"; when 25 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11001"; when 26 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11010"; when 27 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11011"; when 28 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11100"; when 29 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11101"; when 30 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11110"; when 31 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11111"; when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_0 is not in range 0...31." severity error; end case; case CLK_COR_SEQ_2_USE_0 is when FALSE => CLK_COR_SEQ_2_USE_0_BINARY <= '0'; when TRUE => CLK_COR_SEQ_2_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_MIN_LAT_1 is when 3 => CLK_COR_MIN_LAT_1_BINARY <= "000011"; when 4 => CLK_COR_MIN_LAT_1_BINARY <= "000100"; when 5 => CLK_COR_MIN_LAT_1_BINARY <= "000101"; when 6 => CLK_COR_MIN_LAT_1_BINARY <= "000110"; when 7 => CLK_COR_MIN_LAT_1_BINARY <= "000111"; when 8 => CLK_COR_MIN_LAT_1_BINARY <= "001000"; when 9 => CLK_COR_MIN_LAT_1_BINARY <= "001001"; when 10 => CLK_COR_MIN_LAT_1_BINARY <= "001010"; when 11 => CLK_COR_MIN_LAT_1_BINARY <= "001011"; when 12 => CLK_COR_MIN_LAT_1_BINARY <= "001100"; when 13 => CLK_COR_MIN_LAT_1_BINARY <= "001101"; when 14 => CLK_COR_MIN_LAT_1_BINARY <= "001110"; when 15 => CLK_COR_MIN_LAT_1_BINARY <= "001111"; when 16 => CLK_COR_MIN_LAT_1_BINARY <= "010000"; when 17 => CLK_COR_MIN_LAT_1_BINARY <= "010001"; when 18 => CLK_COR_MIN_LAT_1_BINARY <= "010010"; when 19 => CLK_COR_MIN_LAT_1_BINARY <= "010011"; when 20 => CLK_COR_MIN_LAT_1_BINARY <= "010100"; when 21 => CLK_COR_MIN_LAT_1_BINARY <= "010101"; when 22 => CLK_COR_MIN_LAT_1_BINARY <= "010110"; when 23 => CLK_COR_MIN_LAT_1_BINARY <= "010111"; when 24 => CLK_COR_MIN_LAT_1_BINARY <= "011000"; when 25 => CLK_COR_MIN_LAT_1_BINARY <= "011001"; when 26 => CLK_COR_MIN_LAT_1_BINARY <= "011010"; when 27 => CLK_COR_MIN_LAT_1_BINARY <= "011011"; when 28 => CLK_COR_MIN_LAT_1_BINARY <= "011100"; when 29 => CLK_COR_MIN_LAT_1_BINARY <= "011101"; when 30 => CLK_COR_MIN_LAT_1_BINARY <= "011110"; when 31 => CLK_COR_MIN_LAT_1_BINARY <= "011111"; when 32 => CLK_COR_MIN_LAT_1_BINARY <= "100000"; when 33 => CLK_COR_MIN_LAT_1_BINARY <= "100001"; when 34 => CLK_COR_MIN_LAT_1_BINARY <= "100010"; when 35 => CLK_COR_MIN_LAT_1_BINARY <= "100011"; when 36 => CLK_COR_MIN_LAT_1_BINARY <= "100100"; when 37 => CLK_COR_MIN_LAT_1_BINARY <= "100101"; when 38 => CLK_COR_MIN_LAT_1_BINARY <= "100110"; when 39 => CLK_COR_MIN_LAT_1_BINARY <= "100111"; when 40 => CLK_COR_MIN_LAT_1_BINARY <= "101000"; when 41 => CLK_COR_MIN_LAT_1_BINARY <= "101001"; when 42 => CLK_COR_MIN_LAT_1_BINARY <= "101010"; when 43 => CLK_COR_MIN_LAT_1_BINARY <= "101011"; when 44 => CLK_COR_MIN_LAT_1_BINARY <= "101100"; when 45 => CLK_COR_MIN_LAT_1_BINARY <= "101101"; when 46 => CLK_COR_MIN_LAT_1_BINARY <= "101110"; when 47 => CLK_COR_MIN_LAT_1_BINARY <= "101111"; when 48 => CLK_COR_MIN_LAT_1_BINARY <= "110000"; when others => assert FALSE report "Error : CLK_COR_MIN_LAT_1 is not in range 3...48." severity error; end case; case CLK_COR_MAX_LAT_1 is when 3 => CLK_COR_MAX_LAT_1_BINARY <= "000011"; when 4 => CLK_COR_MAX_LAT_1_BINARY <= "000100"; when 5 => CLK_COR_MAX_LAT_1_BINARY <= "000101"; when 6 => CLK_COR_MAX_LAT_1_BINARY <= "000110"; when 7 => CLK_COR_MAX_LAT_1_BINARY <= "000111"; when 8 => CLK_COR_MAX_LAT_1_BINARY <= "001000"; when 9 => CLK_COR_MAX_LAT_1_BINARY <= "001001"; when 10 => CLK_COR_MAX_LAT_1_BINARY <= "001010"; when 11 => CLK_COR_MAX_LAT_1_BINARY <= "001011"; when 12 => CLK_COR_MAX_LAT_1_BINARY <= "001100"; when 13 => CLK_COR_MAX_LAT_1_BINARY <= "001101"; when 14 => CLK_COR_MAX_LAT_1_BINARY <= "001110"; when 15 => CLK_COR_MAX_LAT_1_BINARY <= "001111"; when 16 => CLK_COR_MAX_LAT_1_BINARY <= "010000"; when 17 => CLK_COR_MAX_LAT_1_BINARY <= "010001"; when 18 => CLK_COR_MAX_LAT_1_BINARY <= "010010"; when 19 => CLK_COR_MAX_LAT_1_BINARY <= "010011"; when 20 => CLK_COR_MAX_LAT_1_BINARY <= "010100"; when 21 => CLK_COR_MAX_LAT_1_BINARY <= "010101"; when 22 => CLK_COR_MAX_LAT_1_BINARY <= "010110"; when 23 => CLK_COR_MAX_LAT_1_BINARY <= "010111"; when 24 => CLK_COR_MAX_LAT_1_BINARY <= "011000"; when 25 => CLK_COR_MAX_LAT_1_BINARY <= "011001"; when 26 => CLK_COR_MAX_LAT_1_BINARY <= "011010"; when 27 => CLK_COR_MAX_LAT_1_BINARY <= "011011"; when 28 => CLK_COR_MAX_LAT_1_BINARY <= "011100"; when 29 => CLK_COR_MAX_LAT_1_BINARY <= "011101"; when 30 => CLK_COR_MAX_LAT_1_BINARY <= "011110"; when 31 => CLK_COR_MAX_LAT_1_BINARY <= "011111"; when 32 => CLK_COR_MAX_LAT_1_BINARY <= "100000"; when 33 => CLK_COR_MAX_LAT_1_BINARY <= "100001"; when 34 => CLK_COR_MAX_LAT_1_BINARY <= "100010"; when 35 => CLK_COR_MAX_LAT_1_BINARY <= "100011"; when 36 => CLK_COR_MAX_LAT_1_BINARY <= "100100"; when 37 => CLK_COR_MAX_LAT_1_BINARY <= "100101"; when 38 => CLK_COR_MAX_LAT_1_BINARY <= "100110"; when 39 => CLK_COR_MAX_LAT_1_BINARY <= "100111"; when 40 => CLK_COR_MAX_LAT_1_BINARY <= "101000"; when 41 => CLK_COR_MAX_LAT_1_BINARY <= "101001"; when 42 => CLK_COR_MAX_LAT_1_BINARY <= "101010"; when 43 => CLK_COR_MAX_LAT_1_BINARY <= "101011"; when 44 => CLK_COR_MAX_LAT_1_BINARY <= "101100"; when 45 => CLK_COR_MAX_LAT_1_BINARY <= "101101"; when 46 => CLK_COR_MAX_LAT_1_BINARY <= "101110"; when 47 => CLK_COR_MAX_LAT_1_BINARY <= "101111"; when 48 => CLK_COR_MAX_LAT_1_BINARY <= "110000"; when others => assert FALSE report "Error : CLK_COR_MAX_LAT_1 is not in range 3...48." severity error; end case; case CLK_CORRECT_USE_1 is when FALSE => CLK_CORRECT_USE_1_BINARY <= '0'; when TRUE => CLK_CORRECT_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : CLK_CORRECT_USE_1 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_PRECEDENCE_1 is when FALSE => CLK_COR_PRECEDENCE_1_BINARY <= '0'; when TRUE => CLK_COR_PRECEDENCE_1_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_1 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_DET_LEN_1 is when 1 => CLK_COR_DET_LEN_1_BINARY <= "00"; when 2 => CLK_COR_DET_LEN_1_BINARY <= "01"; when 3 => CLK_COR_DET_LEN_1_BINARY <= "10"; when 4 => CLK_COR_DET_LEN_1_BINARY <= "11"; when others => assert FALSE report "Error : CLK_COR_DET_LEN_1 is not in 1, 2, 3, 4." severity error; end case; case CLK_COR_ADJ_LEN_1 is when 1 => CLK_COR_ADJ_LEN_1_BINARY <= "00"; when 2 => CLK_COR_ADJ_LEN_1_BINARY <= "01"; when 3 => CLK_COR_ADJ_LEN_1_BINARY <= "10"; when 4 => CLK_COR_ADJ_LEN_1_BINARY <= "11"; when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_1 is not in 1, 2, 3, 4." severity error; end case; case CLK_COR_KEEP_IDLE_1 is when FALSE => CLK_COR_KEEP_IDLE_1_BINARY <= '0'; when TRUE => CLK_COR_KEEP_IDLE_1_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_1 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_INSERT_IDLE_FLAG_1 is when FALSE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '0'; when TRUE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_1 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_REPEAT_WAIT_1 is when 0 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00000"; when 1 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00001"; when 2 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00010"; when 3 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00011"; when 4 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00100"; when 5 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00101"; when 6 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00110"; when 7 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00111"; when 8 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01000"; when 9 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01001"; when 10 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01010"; when 11 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01011"; when 12 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01100"; when 13 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01101"; when 14 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01110"; when 15 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01111"; when 16 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10000"; when 17 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10001"; when 18 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10010"; when 19 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10011"; when 20 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10100"; when 21 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10101"; when 22 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10110"; when 23 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10111"; when 24 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11000"; when 25 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11001"; when 26 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11010"; when 27 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11011"; when 28 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11100"; when 29 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11101"; when 30 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11110"; when 31 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11111"; when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_1 is not in range 0...31." severity error; end case; case CLK_COR_SEQ_2_USE_1 is when FALSE => CLK_COR_SEQ_2_USE_1_BINARY <= '0'; when TRUE => CLK_COR_SEQ_2_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; end case; -- case CHAN_BOND_MODE_0 is if((CHAN_BOND_MODE_0 = "OFF") or (CHAN_BOND_MODE_0 = "off")) then CHAN_BOND_MODE_0_BINARY <= "00"; elsif((CHAN_BOND_MODE_0 = "MASTER") or (CHAN_BOND_MODE_0 = "master")) then CHAN_BOND_MODE_0_BINARY <= "01"; elsif((CHAN_BOND_MODE_0 = "SLAVE") or (CHAN_BOND_MODE_0 = "slave")) then CHAN_BOND_MODE_0_BINARY <= "10"; else assert FALSE report "Error : CHAN_BOND_MODE_0 = is not OFF, MASTER, SLAVE." severity error; end if; -- end case; case CHAN_BOND_LEVEL_0 is when 0 => CHAN_BOND_LEVEL_0_BINARY <= "000"; when 1 => CHAN_BOND_LEVEL_0_BINARY <= "001"; when 2 => CHAN_BOND_LEVEL_0_BINARY <= "010"; when 3 => CHAN_BOND_LEVEL_0_BINARY <= "011"; when 4 => CHAN_BOND_LEVEL_0_BINARY <= "100"; when 5 => CHAN_BOND_LEVEL_0_BINARY <= "101"; when 6 => CHAN_BOND_LEVEL_0_BINARY <= "110"; when 7 => CHAN_BOND_LEVEL_0_BINARY <= "111"; when others => assert FALSE report "Error : CHAN_BOND_LEVEL_0 is not in range 0...7." severity error; end case; case CHAN_BOND_SEQ_LEN_0 is when 1 => CHAN_BOND_SEQ_LEN_0_BINARY <= "00"; when 2 => CHAN_BOND_SEQ_LEN_0_BINARY <= "01"; when 3 => CHAN_BOND_SEQ_LEN_0_BINARY <= "10"; when 4 => CHAN_BOND_SEQ_LEN_0_BINARY <= "11"; when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_0 is not in 1, 2, 3, 4." severity error; end case; case CHAN_BOND_SEQ_2_USE_0 is when FALSE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '0'; when TRUE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; end case; case CHAN_BOND_1_MAX_SKEW_0 is when 1 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0001"; when 2 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0010"; when 3 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0011"; when 4 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0100"; when 5 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0101"; when 6 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0110"; when 7 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0111"; when 8 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1000"; when 9 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1001"; when 10 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1010"; when 11 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1011"; when 12 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1100"; when 13 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1101"; when 14 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1110"; when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_0 is not in range 1...14." severity error; end case; case CHAN_BOND_2_MAX_SKEW_0 is when 1 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0001"; when 2 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0010"; when 3 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0011"; when 4 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0100"; when 5 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0101"; when 6 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0110"; when 7 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0111"; when 8 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1000"; when 9 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1001"; when 10 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1010"; when 11 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1011"; when 12 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1100"; when 13 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1101"; when 14 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1110"; when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_0 is not in range 1...14." severity error; end case; -- case CHAN_BOND_MODE_1 is if((CHAN_BOND_MODE_1 = "OFF") or (CHAN_BOND_MODE_1 = "off")) then CHAN_BOND_MODE_1_BINARY <= "00"; elsif((CHAN_BOND_MODE_1 = "MASTER") or (CHAN_BOND_MODE_1 = "master")) then CHAN_BOND_MODE_1_BINARY <= "01"; elsif((CHAN_BOND_MODE_1 = "SLAVE") or (CHAN_BOND_MODE_1 = "slave")) then CHAN_BOND_MODE_1_BINARY <= "10"; else assert FALSE report "Error : CHAN_BOND_MODE_1 = is not OFF, MASTER, SLAVE." severity error; end if; -- end case; case CHAN_BOND_LEVEL_1 is when 0 => CHAN_BOND_LEVEL_1_BINARY <= "000"; when 1 => CHAN_BOND_LEVEL_1_BINARY <= "001"; when 2 => CHAN_BOND_LEVEL_1_BINARY <= "010"; when 3 => CHAN_BOND_LEVEL_1_BINARY <= "011"; when 4 => CHAN_BOND_LEVEL_1_BINARY <= "100"; when 5 => CHAN_BOND_LEVEL_1_BINARY <= "101"; when 6 => CHAN_BOND_LEVEL_1_BINARY <= "110"; when 7 => CHAN_BOND_LEVEL_1_BINARY <= "111"; when others => assert FALSE report "Error : CHAN_BOND_LEVEL_1 is not in range 0...7." severity error; end case; case CHAN_BOND_SEQ_LEN_1 is when 1 => CHAN_BOND_SEQ_LEN_1_BINARY <= "00"; when 2 => CHAN_BOND_SEQ_LEN_1_BINARY <= "01"; when 3 => CHAN_BOND_SEQ_LEN_1_BINARY <= "10"; when 4 => CHAN_BOND_SEQ_LEN_1_BINARY <= "11"; when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_1 is not in 1, 2, 3, 4." severity error; end case; case CHAN_BOND_SEQ_2_USE_1 is when FALSE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '0'; when TRUE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; end case; case CHAN_BOND_1_MAX_SKEW_1 is when 1 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0001"; when 2 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0010"; when 3 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0011"; when 4 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0100"; when 5 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0101"; when 6 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0110"; when 7 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0111"; when 8 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1000"; when 9 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1001"; when 10 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1010"; when 11 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1011"; when 12 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1100"; when 13 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1101"; when 14 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1110"; when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_1 is not in range 1...14." severity error; end case; case CHAN_BOND_2_MAX_SKEW_1 is when 1 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0001"; when 2 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0010"; when 3 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0011"; when 4 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0100"; when 5 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0101"; when 6 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0110"; when 7 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0111"; when 8 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1000"; when 9 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1001"; when 10 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1010"; when 11 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1011"; when 12 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1100"; when 13 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1101"; when 14 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1110"; when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_1 is not in range 1...14." severity error; end case; case PCI_EXPRESS_MODE_0 is when FALSE => PCI_EXPRESS_MODE_0_BINARY <= '0'; when TRUE => PCI_EXPRESS_MODE_0_BINARY <= '1'; when others => assert FALSE report "Error : PCI_EXPRESS_MODE_0 is neither TRUE nor FALSE." severity error; end case; case PCI_EXPRESS_MODE_1 is when FALSE => PCI_EXPRESS_MODE_1_BINARY <= '0'; when TRUE => PCI_EXPRESS_MODE_1_BINARY <= '1'; when others => assert FALSE report "Error : PCI_EXPRESS_MODE_1 is neither TRUE nor FALSE." severity error; end case; -- case RX_STATUS_FMT_0 is if((RX_STATUS_FMT_0 = "PCIE") or (RX_STATUS_FMT_0 = "pcie")) then RX_STATUS_FMT_0_BINARY <= '0'; elsif((RX_STATUS_FMT_0 = "SATA") or (RX_STATUS_FMT_0 = "sata")) then RX_STATUS_FMT_0_BINARY <= '1'; else assert FALSE report "Error : RX_STATUS_FMT_0 = is not PCIE, SATA." severity error; end if; -- end case; case TX_BUFFER_USE_0 is when FALSE => TX_BUFFER_USE_0_BINARY <= '0'; when TRUE => TX_BUFFER_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : TX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; end case; -- case TX_XCLK_SEL_0 is if((TX_XCLK_SEL_0 = "TXUSR") or (TX_XCLK_SEL_0 = "txusr")) then TX_XCLK_SEL_0_BINARY <= '1'; elsif((TX_XCLK_SEL_0 = "TXOUT") or (TX_XCLK_SEL_0 = "txout")) then TX_XCLK_SEL_0_BINARY <= '0'; else assert FALSE report "Error : TX_XCLK_SEL_0 = is not TXUSR, TXOUT." severity error; end if; -- end case; -- case RX_XCLK_SEL_0 is if((RX_XCLK_SEL_0 = "RXREC") or (RX_XCLK_SEL_0 = "rxrec")) then RX_XCLK_SEL_0_BINARY <= '0'; elsif((RX_XCLK_SEL_0 = "RXUSR") or (RX_XCLK_SEL_0 = "rxusr")) then RX_XCLK_SEL_0_BINARY <= '1'; else assert FALSE report "Error : RX_XCLK_SEL_0 = is not RXREC, RXUSR." severity error; end if; -- end case; -- case RX_STATUS_FMT_1 is if((RX_STATUS_FMT_1 = "PCIE") or (RX_STATUS_FMT_1 = "pcie")) then RX_STATUS_FMT_1_BINARY <= '0'; elsif((RX_STATUS_FMT_1 = "SATA") or (RX_STATUS_FMT_1 = "sata")) then RX_STATUS_FMT_1_BINARY <= '1'; else assert FALSE report "Error : RX_STATUS_FMT_1 = is not PCIE, SATA." severity error; end if; -- end case; case TX_BUFFER_USE_1 is when FALSE => TX_BUFFER_USE_1_BINARY <= '0'; when TRUE => TX_BUFFER_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : TX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; end case; -- case TX_XCLK_SEL_1 is if((TX_XCLK_SEL_1 = "TXUSR") or (TX_XCLK_SEL_1 = "txusr")) then TX_XCLK_SEL_1_BINARY <= '1'; elsif((TX_XCLK_SEL_1 = "TXOUT") or (TX_XCLK_SEL_1 = "txout")) then TX_XCLK_SEL_1_BINARY <= '0'; else assert FALSE report "Error : TX_XCLK_SEL_1 = is not TXUSR, TXOUT." severity error; end if; -- end case; -- case RX_XCLK_SEL_1 is if((RX_XCLK_SEL_1 = "RXREC") or (RX_XCLK_SEL_1 = "rxrec")) then RX_XCLK_SEL_1_BINARY <= '0'; elsif((RX_XCLK_SEL_1 = "RXUSR") or (RX_XCLK_SEL_1 = "rxusr")) then RX_XCLK_SEL_1_BINARY <= '1'; else assert FALSE report "Error : RX_XCLK_SEL_1 = is not RXREC, RXUSR." severity error; end if; -- end case; -- case RX_SLIDE_MODE_0 is if((RX_SLIDE_MODE_0 = "PCS") or (RX_SLIDE_MODE_0 = "pcs")) then RX_SLIDE_MODE_0_BINARY <= '0'; elsif((RX_SLIDE_MODE_0 = "PMA") or (RX_SLIDE_MODE_0 = "pma")) then RX_SLIDE_MODE_0_BINARY <= '1'; else assert FALSE report "Error : RX_SLIDE_MODE_0 = is not PCS, PMA." severity error; end if; -- end case; -- case RX_SLIDE_MODE_1 is if((RX_SLIDE_MODE_1 = "PCS") or (RX_SLIDE_MODE_1 = "pcs")) then RX_SLIDE_MODE_1_BINARY <= '0'; elsif((RX_SLIDE_MODE_1 = "PMA") or (RX_SLIDE_MODE_1 = "pma")) then RX_SLIDE_MODE_1_BINARY <= '1'; else assert FALSE report "Error : RX_SLIDE_MODE_1 = is not PCS, PMA." severity error; end if; -- end case; case SATA_MIN_BURST_0 is when 1 => SATA_MIN_BURST_0_BINARY <= "000001"; when 2 => SATA_MIN_BURST_0_BINARY <= "000010"; when 3 => SATA_MIN_BURST_0_BINARY <= "000011"; when 4 => SATA_MIN_BURST_0_BINARY <= "000100"; when 5 => SATA_MIN_BURST_0_BINARY <= "000101"; when 6 => SATA_MIN_BURST_0_BINARY <= "000110"; when 7 => SATA_MIN_BURST_0_BINARY <= "000111"; when 8 => SATA_MIN_BURST_0_BINARY <= "001000"; when 9 => SATA_MIN_BURST_0_BINARY <= "001001"; when 10 => SATA_MIN_BURST_0_BINARY <= "001010"; when 11 => SATA_MIN_BURST_0_BINARY <= "001011"; when 12 => SATA_MIN_BURST_0_BINARY <= "001100"; when 13 => SATA_MIN_BURST_0_BINARY <= "001101"; when 14 => SATA_MIN_BURST_0_BINARY <= "001110"; when 15 => SATA_MIN_BURST_0_BINARY <= "001111"; when 16 => SATA_MIN_BURST_0_BINARY <= "010000"; when 17 => SATA_MIN_BURST_0_BINARY <= "010001"; when 18 => SATA_MIN_BURST_0_BINARY <= "010010"; when 19 => SATA_MIN_BURST_0_BINARY <= "010011"; when 20 => SATA_MIN_BURST_0_BINARY <= "010100"; when 21 => SATA_MIN_BURST_0_BINARY <= "010101"; when 22 => SATA_MIN_BURST_0_BINARY <= "010110"; when 23 => SATA_MIN_BURST_0_BINARY <= "010111"; when 24 => SATA_MIN_BURST_0_BINARY <= "011000"; when 25 => SATA_MIN_BURST_0_BINARY <= "011001"; when 26 => SATA_MIN_BURST_0_BINARY <= "011010"; when 27 => SATA_MIN_BURST_0_BINARY <= "011011"; when 28 => SATA_MIN_BURST_0_BINARY <= "011100"; when 29 => SATA_MIN_BURST_0_BINARY <= "011101"; when 30 => SATA_MIN_BURST_0_BINARY <= "011110"; when 31 => SATA_MIN_BURST_0_BINARY <= "011111"; when 32 => SATA_MIN_BURST_0_BINARY <= "100000"; when 33 => SATA_MIN_BURST_0_BINARY <= "100001"; when 34 => SATA_MIN_BURST_0_BINARY <= "100010"; when 35 => SATA_MIN_BURST_0_BINARY <= "100011"; when 36 => SATA_MIN_BURST_0_BINARY <= "100100"; when 37 => SATA_MIN_BURST_0_BINARY <= "100101"; when 38 => SATA_MIN_BURST_0_BINARY <= "100110"; when 39 => SATA_MIN_BURST_0_BINARY <= "100111"; when 40 => SATA_MIN_BURST_0_BINARY <= "101000"; when 41 => SATA_MIN_BURST_0_BINARY <= "101001"; when 42 => SATA_MIN_BURST_0_BINARY <= "101010"; when 43 => SATA_MIN_BURST_0_BINARY <= "101011"; when 44 => SATA_MIN_BURST_0_BINARY <= "101100"; when 45 => SATA_MIN_BURST_0_BINARY <= "101101"; when 46 => SATA_MIN_BURST_0_BINARY <= "101110"; when 47 => SATA_MIN_BURST_0_BINARY <= "101111"; when 48 => SATA_MIN_BURST_0_BINARY <= "110000"; when 49 => SATA_MIN_BURST_0_BINARY <= "110001"; when 50 => SATA_MIN_BURST_0_BINARY <= "110010"; when 51 => SATA_MIN_BURST_0_BINARY <= "110011"; when 52 => SATA_MIN_BURST_0_BINARY <= "110100"; when 53 => SATA_MIN_BURST_0_BINARY <= "110101"; when 54 => SATA_MIN_BURST_0_BINARY <= "110110"; when 55 => SATA_MIN_BURST_0_BINARY <= "110111"; when 56 => SATA_MIN_BURST_0_BINARY <= "111000"; when 57 => SATA_MIN_BURST_0_BINARY <= "111001"; when 58 => SATA_MIN_BURST_0_BINARY <= "111010"; when 59 => SATA_MIN_BURST_0_BINARY <= "111011"; when 60 => SATA_MIN_BURST_0_BINARY <= "111100"; when 61 => SATA_MIN_BURST_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_BURST_0 is not in range 1...61." severity error; end case; case SATA_MAX_BURST_0 is when 1 => SATA_MAX_BURST_0_BINARY <= "000001"; when 2 => SATA_MAX_BURST_0_BINARY <= "000010"; when 3 => SATA_MAX_BURST_0_BINARY <= "000011"; when 4 => SATA_MAX_BURST_0_BINARY <= "000100"; when 5 => SATA_MAX_BURST_0_BINARY <= "000101"; when 6 => SATA_MAX_BURST_0_BINARY <= "000110"; when 7 => SATA_MAX_BURST_0_BINARY <= "000111"; when 8 => SATA_MAX_BURST_0_BINARY <= "001000"; when 9 => SATA_MAX_BURST_0_BINARY <= "001001"; when 10 => SATA_MAX_BURST_0_BINARY <= "001010"; when 11 => SATA_MAX_BURST_0_BINARY <= "001011"; when 12 => SATA_MAX_BURST_0_BINARY <= "001100"; when 13 => SATA_MAX_BURST_0_BINARY <= "001101"; when 14 => SATA_MAX_BURST_0_BINARY <= "001110"; when 15 => SATA_MAX_BURST_0_BINARY <= "001111"; when 16 => SATA_MAX_BURST_0_BINARY <= "010000"; when 17 => SATA_MAX_BURST_0_BINARY <= "010001"; when 18 => SATA_MAX_BURST_0_BINARY <= "010010"; when 19 => SATA_MAX_BURST_0_BINARY <= "010011"; when 20 => SATA_MAX_BURST_0_BINARY <= "010100"; when 21 => SATA_MAX_BURST_0_BINARY <= "010101"; when 22 => SATA_MAX_BURST_0_BINARY <= "010110"; when 23 => SATA_MAX_BURST_0_BINARY <= "010111"; when 24 => SATA_MAX_BURST_0_BINARY <= "011000"; when 25 => SATA_MAX_BURST_0_BINARY <= "011001"; when 26 => SATA_MAX_BURST_0_BINARY <= "011010"; when 27 => SATA_MAX_BURST_0_BINARY <= "011011"; when 28 => SATA_MAX_BURST_0_BINARY <= "011100"; when 29 => SATA_MAX_BURST_0_BINARY <= "011101"; when 30 => SATA_MAX_BURST_0_BINARY <= "011110"; when 31 => SATA_MAX_BURST_0_BINARY <= "011111"; when 32 => SATA_MAX_BURST_0_BINARY <= "100000"; when 33 => SATA_MAX_BURST_0_BINARY <= "100001"; when 34 => SATA_MAX_BURST_0_BINARY <= "100010"; when 35 => SATA_MAX_BURST_0_BINARY <= "100011"; when 36 => SATA_MAX_BURST_0_BINARY <= "100100"; when 37 => SATA_MAX_BURST_0_BINARY <= "100101"; when 38 => SATA_MAX_BURST_0_BINARY <= "100110"; when 39 => SATA_MAX_BURST_0_BINARY <= "100111"; when 40 => SATA_MAX_BURST_0_BINARY <= "101000"; when 41 => SATA_MAX_BURST_0_BINARY <= "101001"; when 42 => SATA_MAX_BURST_0_BINARY <= "101010"; when 43 => SATA_MAX_BURST_0_BINARY <= "101011"; when 44 => SATA_MAX_BURST_0_BINARY <= "101100"; when 45 => SATA_MAX_BURST_0_BINARY <= "101101"; when 46 => SATA_MAX_BURST_0_BINARY <= "101110"; when 47 => SATA_MAX_BURST_0_BINARY <= "101111"; when 48 => SATA_MAX_BURST_0_BINARY <= "110000"; when 49 => SATA_MAX_BURST_0_BINARY <= "110001"; when 50 => SATA_MAX_BURST_0_BINARY <= "110010"; when 51 => SATA_MAX_BURST_0_BINARY <= "110011"; when 52 => SATA_MAX_BURST_0_BINARY <= "110100"; when 53 => SATA_MAX_BURST_0_BINARY <= "110101"; when 54 => SATA_MAX_BURST_0_BINARY <= "110110"; when 55 => SATA_MAX_BURST_0_BINARY <= "110111"; when 56 => SATA_MAX_BURST_0_BINARY <= "111000"; when 57 => SATA_MAX_BURST_0_BINARY <= "111001"; when 58 => SATA_MAX_BURST_0_BINARY <= "111010"; when 59 => SATA_MAX_BURST_0_BINARY <= "111011"; when 60 => SATA_MAX_BURST_0_BINARY <= "111100"; when 61 => SATA_MAX_BURST_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_BURST_0 is not in range 1...61." severity error; end case; case SATA_MIN_INIT_0 is when 1 => SATA_MIN_INIT_0_BINARY <= "000001"; when 2 => SATA_MIN_INIT_0_BINARY <= "000010"; when 3 => SATA_MIN_INIT_0_BINARY <= "000011"; when 4 => SATA_MIN_INIT_0_BINARY <= "000100"; when 5 => SATA_MIN_INIT_0_BINARY <= "000101"; when 6 => SATA_MIN_INIT_0_BINARY <= "000110"; when 7 => SATA_MIN_INIT_0_BINARY <= "000111"; when 8 => SATA_MIN_INIT_0_BINARY <= "001000"; when 9 => SATA_MIN_INIT_0_BINARY <= "001001"; when 10 => SATA_MIN_INIT_0_BINARY <= "001010"; when 11 => SATA_MIN_INIT_0_BINARY <= "001011"; when 12 => SATA_MIN_INIT_0_BINARY <= "001100"; when 13 => SATA_MIN_INIT_0_BINARY <= "001101"; when 14 => SATA_MIN_INIT_0_BINARY <= "001110"; when 15 => SATA_MIN_INIT_0_BINARY <= "001111"; when 16 => SATA_MIN_INIT_0_BINARY <= "010000"; when 17 => SATA_MIN_INIT_0_BINARY <= "010001"; when 18 => SATA_MIN_INIT_0_BINARY <= "010010"; when 19 => SATA_MIN_INIT_0_BINARY <= "010011"; when 20 => SATA_MIN_INIT_0_BINARY <= "010100"; when 21 => SATA_MIN_INIT_0_BINARY <= "010101"; when 22 => SATA_MIN_INIT_0_BINARY <= "010110"; when 23 => SATA_MIN_INIT_0_BINARY <= "010111"; when 24 => SATA_MIN_INIT_0_BINARY <= "011000"; when 25 => SATA_MIN_INIT_0_BINARY <= "011001"; when 26 => SATA_MIN_INIT_0_BINARY <= "011010"; when 27 => SATA_MIN_INIT_0_BINARY <= "011011"; when 28 => SATA_MIN_INIT_0_BINARY <= "011100"; when 29 => SATA_MIN_INIT_0_BINARY <= "011101"; when 30 => SATA_MIN_INIT_0_BINARY <= "011110"; when 31 => SATA_MIN_INIT_0_BINARY <= "011111"; when 32 => SATA_MIN_INIT_0_BINARY <= "100000"; when 33 => SATA_MIN_INIT_0_BINARY <= "100001"; when 34 => SATA_MIN_INIT_0_BINARY <= "100010"; when 35 => SATA_MIN_INIT_0_BINARY <= "100011"; when 36 => SATA_MIN_INIT_0_BINARY <= "100100"; when 37 => SATA_MIN_INIT_0_BINARY <= "100101"; when 38 => SATA_MIN_INIT_0_BINARY <= "100110"; when 39 => SATA_MIN_INIT_0_BINARY <= "100111"; when 40 => SATA_MIN_INIT_0_BINARY <= "101000"; when 41 => SATA_MIN_INIT_0_BINARY <= "101001"; when 42 => SATA_MIN_INIT_0_BINARY <= "101010"; when 43 => SATA_MIN_INIT_0_BINARY <= "101011"; when 44 => SATA_MIN_INIT_0_BINARY <= "101100"; when 45 => SATA_MIN_INIT_0_BINARY <= "101101"; when 46 => SATA_MIN_INIT_0_BINARY <= "101110"; when 47 => SATA_MIN_INIT_0_BINARY <= "101111"; when 48 => SATA_MIN_INIT_0_BINARY <= "110000"; when 49 => SATA_MIN_INIT_0_BINARY <= "110001"; when 50 => SATA_MIN_INIT_0_BINARY <= "110010"; when 51 => SATA_MIN_INIT_0_BINARY <= "110011"; when 52 => SATA_MIN_INIT_0_BINARY <= "110100"; when 53 => SATA_MIN_INIT_0_BINARY <= "110101"; when 54 => SATA_MIN_INIT_0_BINARY <= "110110"; when 55 => SATA_MIN_INIT_0_BINARY <= "110111"; when 56 => SATA_MIN_INIT_0_BINARY <= "111000"; when 57 => SATA_MIN_INIT_0_BINARY <= "111001"; when 58 => SATA_MIN_INIT_0_BINARY <= "111010"; when 59 => SATA_MIN_INIT_0_BINARY <= "111011"; when 60 => SATA_MIN_INIT_0_BINARY <= "111100"; when 61 => SATA_MIN_INIT_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_INIT_0 is not in range 1...61." severity error; end case; case SATA_MAX_INIT_0 is when 1 => SATA_MAX_INIT_0_BINARY <= "000001"; when 2 => SATA_MAX_INIT_0_BINARY <= "000010"; when 3 => SATA_MAX_INIT_0_BINARY <= "000011"; when 4 => SATA_MAX_INIT_0_BINARY <= "000100"; when 5 => SATA_MAX_INIT_0_BINARY <= "000101"; when 6 => SATA_MAX_INIT_0_BINARY <= "000110"; when 7 => SATA_MAX_INIT_0_BINARY <= "000111"; when 8 => SATA_MAX_INIT_0_BINARY <= "001000"; when 9 => SATA_MAX_INIT_0_BINARY <= "001001"; when 10 => SATA_MAX_INIT_0_BINARY <= "001010"; when 11 => SATA_MAX_INIT_0_BINARY <= "001011"; when 12 => SATA_MAX_INIT_0_BINARY <= "001100"; when 13 => SATA_MAX_INIT_0_BINARY <= "001101"; when 14 => SATA_MAX_INIT_0_BINARY <= "001110"; when 15 => SATA_MAX_INIT_0_BINARY <= "001111"; when 16 => SATA_MAX_INIT_0_BINARY <= "010000"; when 17 => SATA_MAX_INIT_0_BINARY <= "010001"; when 18 => SATA_MAX_INIT_0_BINARY <= "010010"; when 19 => SATA_MAX_INIT_0_BINARY <= "010011"; when 20 => SATA_MAX_INIT_0_BINARY <= "010100"; when 21 => SATA_MAX_INIT_0_BINARY <= "010101"; when 22 => SATA_MAX_INIT_0_BINARY <= "010110"; when 23 => SATA_MAX_INIT_0_BINARY <= "010111"; when 24 => SATA_MAX_INIT_0_BINARY <= "011000"; when 25 => SATA_MAX_INIT_0_BINARY <= "011001"; when 26 => SATA_MAX_INIT_0_BINARY <= "011010"; when 27 => SATA_MAX_INIT_0_BINARY <= "011011"; when 28 => SATA_MAX_INIT_0_BINARY <= "011100"; when 29 => SATA_MAX_INIT_0_BINARY <= "011101"; when 30 => SATA_MAX_INIT_0_BINARY <= "011110"; when 31 => SATA_MAX_INIT_0_BINARY <= "011111"; when 32 => SATA_MAX_INIT_0_BINARY <= "100000"; when 33 => SATA_MAX_INIT_0_BINARY <= "100001"; when 34 => SATA_MAX_INIT_0_BINARY <= "100010"; when 35 => SATA_MAX_INIT_0_BINARY <= "100011"; when 36 => SATA_MAX_INIT_0_BINARY <= "100100"; when 37 => SATA_MAX_INIT_0_BINARY <= "100101"; when 38 => SATA_MAX_INIT_0_BINARY <= "100110"; when 39 => SATA_MAX_INIT_0_BINARY <= "100111"; when 40 => SATA_MAX_INIT_0_BINARY <= "101000"; when 41 => SATA_MAX_INIT_0_BINARY <= "101001"; when 42 => SATA_MAX_INIT_0_BINARY <= "101010"; when 43 => SATA_MAX_INIT_0_BINARY <= "101011"; when 44 => SATA_MAX_INIT_0_BINARY <= "101100"; when 45 => SATA_MAX_INIT_0_BINARY <= "101101"; when 46 => SATA_MAX_INIT_0_BINARY <= "101110"; when 47 => SATA_MAX_INIT_0_BINARY <= "101111"; when 48 => SATA_MAX_INIT_0_BINARY <= "110000"; when 49 => SATA_MAX_INIT_0_BINARY <= "110001"; when 50 => SATA_MAX_INIT_0_BINARY <= "110010"; when 51 => SATA_MAX_INIT_0_BINARY <= "110011"; when 52 => SATA_MAX_INIT_0_BINARY <= "110100"; when 53 => SATA_MAX_INIT_0_BINARY <= "110101"; when 54 => SATA_MAX_INIT_0_BINARY <= "110110"; when 55 => SATA_MAX_INIT_0_BINARY <= "110111"; when 56 => SATA_MAX_INIT_0_BINARY <= "111000"; when 57 => SATA_MAX_INIT_0_BINARY <= "111001"; when 58 => SATA_MAX_INIT_0_BINARY <= "111010"; when 59 => SATA_MAX_INIT_0_BINARY <= "111011"; when 60 => SATA_MAX_INIT_0_BINARY <= "111100"; when 61 => SATA_MAX_INIT_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_INIT_0 is not in range 1...61." severity error; end case; case SATA_MIN_WAKE_0 is when 1 => SATA_MIN_WAKE_0_BINARY <= "000001"; when 2 => SATA_MIN_WAKE_0_BINARY <= "000010"; when 3 => SATA_MIN_WAKE_0_BINARY <= "000011"; when 4 => SATA_MIN_WAKE_0_BINARY <= "000100"; when 5 => SATA_MIN_WAKE_0_BINARY <= "000101"; when 6 => SATA_MIN_WAKE_0_BINARY <= "000110"; when 7 => SATA_MIN_WAKE_0_BINARY <= "000111"; when 8 => SATA_MIN_WAKE_0_BINARY <= "001000"; when 9 => SATA_MIN_WAKE_0_BINARY <= "001001"; when 10 => SATA_MIN_WAKE_0_BINARY <= "001010"; when 11 => SATA_MIN_WAKE_0_BINARY <= "001011"; when 12 => SATA_MIN_WAKE_0_BINARY <= "001100"; when 13 => SATA_MIN_WAKE_0_BINARY <= "001101"; when 14 => SATA_MIN_WAKE_0_BINARY <= "001110"; when 15 => SATA_MIN_WAKE_0_BINARY <= "001111"; when 16 => SATA_MIN_WAKE_0_BINARY <= "010000"; when 17 => SATA_MIN_WAKE_0_BINARY <= "010001"; when 18 => SATA_MIN_WAKE_0_BINARY <= "010010"; when 19 => SATA_MIN_WAKE_0_BINARY <= "010011"; when 20 => SATA_MIN_WAKE_0_BINARY <= "010100"; when 21 => SATA_MIN_WAKE_0_BINARY <= "010101"; when 22 => SATA_MIN_WAKE_0_BINARY <= "010110"; when 23 => SATA_MIN_WAKE_0_BINARY <= "010111"; when 24 => SATA_MIN_WAKE_0_BINARY <= "011000"; when 25 => SATA_MIN_WAKE_0_BINARY <= "011001"; when 26 => SATA_MIN_WAKE_0_BINARY <= "011010"; when 27 => SATA_MIN_WAKE_0_BINARY <= "011011"; when 28 => SATA_MIN_WAKE_0_BINARY <= "011100"; when 29 => SATA_MIN_WAKE_0_BINARY <= "011101"; when 30 => SATA_MIN_WAKE_0_BINARY <= "011110"; when 31 => SATA_MIN_WAKE_0_BINARY <= "011111"; when 32 => SATA_MIN_WAKE_0_BINARY <= "100000"; when 33 => SATA_MIN_WAKE_0_BINARY <= "100001"; when 34 => SATA_MIN_WAKE_0_BINARY <= "100010"; when 35 => SATA_MIN_WAKE_0_BINARY <= "100011"; when 36 => SATA_MIN_WAKE_0_BINARY <= "100100"; when 37 => SATA_MIN_WAKE_0_BINARY <= "100101"; when 38 => SATA_MIN_WAKE_0_BINARY <= "100110"; when 39 => SATA_MIN_WAKE_0_BINARY <= "100111"; when 40 => SATA_MIN_WAKE_0_BINARY <= "101000"; when 41 => SATA_MIN_WAKE_0_BINARY <= "101001"; when 42 => SATA_MIN_WAKE_0_BINARY <= "101010"; when 43 => SATA_MIN_WAKE_0_BINARY <= "101011"; when 44 => SATA_MIN_WAKE_0_BINARY <= "101100"; when 45 => SATA_MIN_WAKE_0_BINARY <= "101101"; when 46 => SATA_MIN_WAKE_0_BINARY <= "101110"; when 47 => SATA_MIN_WAKE_0_BINARY <= "101111"; when 48 => SATA_MIN_WAKE_0_BINARY <= "110000"; when 49 => SATA_MIN_WAKE_0_BINARY <= "110001"; when 50 => SATA_MIN_WAKE_0_BINARY <= "110010"; when 51 => SATA_MIN_WAKE_0_BINARY <= "110011"; when 52 => SATA_MIN_WAKE_0_BINARY <= "110100"; when 53 => SATA_MIN_WAKE_0_BINARY <= "110101"; when 54 => SATA_MIN_WAKE_0_BINARY <= "110110"; when 55 => SATA_MIN_WAKE_0_BINARY <= "110111"; when 56 => SATA_MIN_WAKE_0_BINARY <= "111000"; when 57 => SATA_MIN_WAKE_0_BINARY <= "111001"; when 58 => SATA_MIN_WAKE_0_BINARY <= "111010"; when 59 => SATA_MIN_WAKE_0_BINARY <= "111011"; when 60 => SATA_MIN_WAKE_0_BINARY <= "111100"; when 61 => SATA_MIN_WAKE_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_WAKE_0 is not in range 1...61." severity error; end case; case SATA_MAX_WAKE_0 is when 1 => SATA_MAX_WAKE_0_BINARY <= "000001"; when 2 => SATA_MAX_WAKE_0_BINARY <= "000010"; when 3 => SATA_MAX_WAKE_0_BINARY <= "000011"; when 4 => SATA_MAX_WAKE_0_BINARY <= "000100"; when 5 => SATA_MAX_WAKE_0_BINARY <= "000101"; when 6 => SATA_MAX_WAKE_0_BINARY <= "000110"; when 7 => SATA_MAX_WAKE_0_BINARY <= "000111"; when 8 => SATA_MAX_WAKE_0_BINARY <= "001000"; when 9 => SATA_MAX_WAKE_0_BINARY <= "001001"; when 10 => SATA_MAX_WAKE_0_BINARY <= "001010"; when 11 => SATA_MAX_WAKE_0_BINARY <= "001011"; when 12 => SATA_MAX_WAKE_0_BINARY <= "001100"; when 13 => SATA_MAX_WAKE_0_BINARY <= "001101"; when 14 => SATA_MAX_WAKE_0_BINARY <= "001110"; when 15 => SATA_MAX_WAKE_0_BINARY <= "001111"; when 16 => SATA_MAX_WAKE_0_BINARY <= "010000"; when 17 => SATA_MAX_WAKE_0_BINARY <= "010001"; when 18 => SATA_MAX_WAKE_0_BINARY <= "010010"; when 19 => SATA_MAX_WAKE_0_BINARY <= "010011"; when 20 => SATA_MAX_WAKE_0_BINARY <= "010100"; when 21 => SATA_MAX_WAKE_0_BINARY <= "010101"; when 22 => SATA_MAX_WAKE_0_BINARY <= "010110"; when 23 => SATA_MAX_WAKE_0_BINARY <= "010111"; when 24 => SATA_MAX_WAKE_0_BINARY <= "011000"; when 25 => SATA_MAX_WAKE_0_BINARY <= "011001"; when 26 => SATA_MAX_WAKE_0_BINARY <= "011010"; when 27 => SATA_MAX_WAKE_0_BINARY <= "011011"; when 28 => SATA_MAX_WAKE_0_BINARY <= "011100"; when 29 => SATA_MAX_WAKE_0_BINARY <= "011101"; when 30 => SATA_MAX_WAKE_0_BINARY <= "011110"; when 31 => SATA_MAX_WAKE_0_BINARY <= "011111"; when 32 => SATA_MAX_WAKE_0_BINARY <= "100000"; when 33 => SATA_MAX_WAKE_0_BINARY <= "100001"; when 34 => SATA_MAX_WAKE_0_BINARY <= "100010"; when 35 => SATA_MAX_WAKE_0_BINARY <= "100011"; when 36 => SATA_MAX_WAKE_0_BINARY <= "100100"; when 37 => SATA_MAX_WAKE_0_BINARY <= "100101"; when 38 => SATA_MAX_WAKE_0_BINARY <= "100110"; when 39 => SATA_MAX_WAKE_0_BINARY <= "100111"; when 40 => SATA_MAX_WAKE_0_BINARY <= "101000"; when 41 => SATA_MAX_WAKE_0_BINARY <= "101001"; when 42 => SATA_MAX_WAKE_0_BINARY <= "101010"; when 43 => SATA_MAX_WAKE_0_BINARY <= "101011"; when 44 => SATA_MAX_WAKE_0_BINARY <= "101100"; when 45 => SATA_MAX_WAKE_0_BINARY <= "101101"; when 46 => SATA_MAX_WAKE_0_BINARY <= "101110"; when 47 => SATA_MAX_WAKE_0_BINARY <= "101111"; when 48 => SATA_MAX_WAKE_0_BINARY <= "110000"; when 49 => SATA_MAX_WAKE_0_BINARY <= "110001"; when 50 => SATA_MAX_WAKE_0_BINARY <= "110010"; when 51 => SATA_MAX_WAKE_0_BINARY <= "110011"; when 52 => SATA_MAX_WAKE_0_BINARY <= "110100"; when 53 => SATA_MAX_WAKE_0_BINARY <= "110101"; when 54 => SATA_MAX_WAKE_0_BINARY <= "110110"; when 55 => SATA_MAX_WAKE_0_BINARY <= "110111"; when 56 => SATA_MAX_WAKE_0_BINARY <= "111000"; when 57 => SATA_MAX_WAKE_0_BINARY <= "111001"; when 58 => SATA_MAX_WAKE_0_BINARY <= "111010"; when 59 => SATA_MAX_WAKE_0_BINARY <= "111011"; when 60 => SATA_MAX_WAKE_0_BINARY <= "111100"; when 61 => SATA_MAX_WAKE_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_WAKE_0 is not in range 1...61." severity error; end case; case SATA_MIN_BURST_1 is when 1 => SATA_MIN_BURST_1_BINARY <= "000001"; when 2 => SATA_MIN_BURST_1_BINARY <= "000010"; when 3 => SATA_MIN_BURST_1_BINARY <= "000011"; when 4 => SATA_MIN_BURST_1_BINARY <= "000100"; when 5 => SATA_MIN_BURST_1_BINARY <= "000101"; when 6 => SATA_MIN_BURST_1_BINARY <= "000110"; when 7 => SATA_MIN_BURST_1_BINARY <= "000111"; when 8 => SATA_MIN_BURST_1_BINARY <= "001000"; when 9 => SATA_MIN_BURST_1_BINARY <= "001001"; when 10 => SATA_MIN_BURST_1_BINARY <= "001010"; when 11 => SATA_MIN_BURST_1_BINARY <= "001011"; when 12 => SATA_MIN_BURST_1_BINARY <= "001100"; when 13 => SATA_MIN_BURST_1_BINARY <= "001101"; when 14 => SATA_MIN_BURST_1_BINARY <= "001110"; when 15 => SATA_MIN_BURST_1_BINARY <= "001111"; when 16 => SATA_MIN_BURST_1_BINARY <= "010000"; when 17 => SATA_MIN_BURST_1_BINARY <= "010001"; when 18 => SATA_MIN_BURST_1_BINARY <= "010010"; when 19 => SATA_MIN_BURST_1_BINARY <= "010011"; when 20 => SATA_MIN_BURST_1_BINARY <= "010100"; when 21 => SATA_MIN_BURST_1_BINARY <= "010101"; when 22 => SATA_MIN_BURST_1_BINARY <= "010110"; when 23 => SATA_MIN_BURST_1_BINARY <= "010111"; when 24 => SATA_MIN_BURST_1_BINARY <= "011000"; when 25 => SATA_MIN_BURST_1_BINARY <= "011001"; when 26 => SATA_MIN_BURST_1_BINARY <= "011010"; when 27 => SATA_MIN_BURST_1_BINARY <= "011011"; when 28 => SATA_MIN_BURST_1_BINARY <= "011100"; when 29 => SATA_MIN_BURST_1_BINARY <= "011101"; when 30 => SATA_MIN_BURST_1_BINARY <= "011110"; when 31 => SATA_MIN_BURST_1_BINARY <= "011111"; when 32 => SATA_MIN_BURST_1_BINARY <= "100000"; when 33 => SATA_MIN_BURST_1_BINARY <= "100001"; when 34 => SATA_MIN_BURST_1_BINARY <= "100010"; when 35 => SATA_MIN_BURST_1_BINARY <= "100011"; when 36 => SATA_MIN_BURST_1_BINARY <= "100100"; when 37 => SATA_MIN_BURST_1_BINARY <= "100101"; when 38 => SATA_MIN_BURST_1_BINARY <= "100110"; when 39 => SATA_MIN_BURST_1_BINARY <= "100111"; when 40 => SATA_MIN_BURST_1_BINARY <= "101000"; when 41 => SATA_MIN_BURST_1_BINARY <= "101001"; when 42 => SATA_MIN_BURST_1_BINARY <= "101010"; when 43 => SATA_MIN_BURST_1_BINARY <= "101011"; when 44 => SATA_MIN_BURST_1_BINARY <= "101100"; when 45 => SATA_MIN_BURST_1_BINARY <= "101101"; when 46 => SATA_MIN_BURST_1_BINARY <= "101110"; when 47 => SATA_MIN_BURST_1_BINARY <= "101111"; when 48 => SATA_MIN_BURST_1_BINARY <= "110000"; when 49 => SATA_MIN_BURST_1_BINARY <= "110001"; when 50 => SATA_MIN_BURST_1_BINARY <= "110010"; when 51 => SATA_MIN_BURST_1_BINARY <= "110011"; when 52 => SATA_MIN_BURST_1_BINARY <= "110100"; when 53 => SATA_MIN_BURST_1_BINARY <= "110101"; when 54 => SATA_MIN_BURST_1_BINARY <= "110110"; when 55 => SATA_MIN_BURST_1_BINARY <= "110111"; when 56 => SATA_MIN_BURST_1_BINARY <= "111000"; when 57 => SATA_MIN_BURST_1_BINARY <= "111001"; when 58 => SATA_MIN_BURST_1_BINARY <= "111010"; when 59 => SATA_MIN_BURST_1_BINARY <= "111011"; when 60 => SATA_MIN_BURST_1_BINARY <= "111100"; when 61 => SATA_MIN_BURST_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_BURST_1 is not in range 1...61." severity error; end case; case SATA_MAX_BURST_1 is when 1 => SATA_MAX_BURST_1_BINARY <= "000001"; when 2 => SATA_MAX_BURST_1_BINARY <= "000010"; when 3 => SATA_MAX_BURST_1_BINARY <= "000011"; when 4 => SATA_MAX_BURST_1_BINARY <= "000100"; when 5 => SATA_MAX_BURST_1_BINARY <= "000101"; when 6 => SATA_MAX_BURST_1_BINARY <= "000110"; when 7 => SATA_MAX_BURST_1_BINARY <= "000111"; when 8 => SATA_MAX_BURST_1_BINARY <= "001000"; when 9 => SATA_MAX_BURST_1_BINARY <= "001001"; when 10 => SATA_MAX_BURST_1_BINARY <= "001010"; when 11 => SATA_MAX_BURST_1_BINARY <= "001011"; when 12 => SATA_MAX_BURST_1_BINARY <= "001100"; when 13 => SATA_MAX_BURST_1_BINARY <= "001101"; when 14 => SATA_MAX_BURST_1_BINARY <= "001110"; when 15 => SATA_MAX_BURST_1_BINARY <= "001111"; when 16 => SATA_MAX_BURST_1_BINARY <= "010000"; when 17 => SATA_MAX_BURST_1_BINARY <= "010001"; when 18 => SATA_MAX_BURST_1_BINARY <= "010010"; when 19 => SATA_MAX_BURST_1_BINARY <= "010011"; when 20 => SATA_MAX_BURST_1_BINARY <= "010100"; when 21 => SATA_MAX_BURST_1_BINARY <= "010101"; when 22 => SATA_MAX_BURST_1_BINARY <= "010110"; when 23 => SATA_MAX_BURST_1_BINARY <= "010111"; when 24 => SATA_MAX_BURST_1_BINARY <= "011000"; when 25 => SATA_MAX_BURST_1_BINARY <= "011001"; when 26 => SATA_MAX_BURST_1_BINARY <= "011010"; when 27 => SATA_MAX_BURST_1_BINARY <= "011011"; when 28 => SATA_MAX_BURST_1_BINARY <= "011100"; when 29 => SATA_MAX_BURST_1_BINARY <= "011101"; when 30 => SATA_MAX_BURST_1_BINARY <= "011110"; when 31 => SATA_MAX_BURST_1_BINARY <= "011111"; when 32 => SATA_MAX_BURST_1_BINARY <= "100000"; when 33 => SATA_MAX_BURST_1_BINARY <= "100001"; when 34 => SATA_MAX_BURST_1_BINARY <= "100010"; when 35 => SATA_MAX_BURST_1_BINARY <= "100011"; when 36 => SATA_MAX_BURST_1_BINARY <= "100100"; when 37 => SATA_MAX_BURST_1_BINARY <= "100101"; when 38 => SATA_MAX_BURST_1_BINARY <= "100110"; when 39 => SATA_MAX_BURST_1_BINARY <= "100111"; when 40 => SATA_MAX_BURST_1_BINARY <= "101000"; when 41 => SATA_MAX_BURST_1_BINARY <= "101001"; when 42 => SATA_MAX_BURST_1_BINARY <= "101010"; when 43 => SATA_MAX_BURST_1_BINARY <= "101011"; when 44 => SATA_MAX_BURST_1_BINARY <= "101100"; when 45 => SATA_MAX_BURST_1_BINARY <= "101101"; when 46 => SATA_MAX_BURST_1_BINARY <= "101110"; when 47 => SATA_MAX_BURST_1_BINARY <= "101111"; when 48 => SATA_MAX_BURST_1_BINARY <= "110000"; when 49 => SATA_MAX_BURST_1_BINARY <= "110001"; when 50 => SATA_MAX_BURST_1_BINARY <= "110010"; when 51 => SATA_MAX_BURST_1_BINARY <= "110011"; when 52 => SATA_MAX_BURST_1_BINARY <= "110100"; when 53 => SATA_MAX_BURST_1_BINARY <= "110101"; when 54 => SATA_MAX_BURST_1_BINARY <= "110110"; when 55 => SATA_MAX_BURST_1_BINARY <= "110111"; when 56 => SATA_MAX_BURST_1_BINARY <= "111000"; when 57 => SATA_MAX_BURST_1_BINARY <= "111001"; when 58 => SATA_MAX_BURST_1_BINARY <= "111010"; when 59 => SATA_MAX_BURST_1_BINARY <= "111011"; when 60 => SATA_MAX_BURST_1_BINARY <= "111100"; when 61 => SATA_MAX_BURST_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_BURST_1 is not in range 1...61." severity error; end case; case SATA_MIN_INIT_1 is when 1 => SATA_MIN_INIT_1_BINARY <= "000001"; when 2 => SATA_MIN_INIT_1_BINARY <= "000010"; when 3 => SATA_MIN_INIT_1_BINARY <= "000011"; when 4 => SATA_MIN_INIT_1_BINARY <= "000100"; when 5 => SATA_MIN_INIT_1_BINARY <= "000101"; when 6 => SATA_MIN_INIT_1_BINARY <= "000110"; when 7 => SATA_MIN_INIT_1_BINARY <= "000111"; when 8 => SATA_MIN_INIT_1_BINARY <= "001000"; when 9 => SATA_MIN_INIT_1_BINARY <= "001001"; when 10 => SATA_MIN_INIT_1_BINARY <= "001010"; when 11 => SATA_MIN_INIT_1_BINARY <= "001011"; when 12 => SATA_MIN_INIT_1_BINARY <= "001100"; when 13 => SATA_MIN_INIT_1_BINARY <= "001101"; when 14 => SATA_MIN_INIT_1_BINARY <= "001110"; when 15 => SATA_MIN_INIT_1_BINARY <= "001111"; when 16 => SATA_MIN_INIT_1_BINARY <= "010000"; when 17 => SATA_MIN_INIT_1_BINARY <= "010001"; when 18 => SATA_MIN_INIT_1_BINARY <= "010010"; when 19 => SATA_MIN_INIT_1_BINARY <= "010011"; when 20 => SATA_MIN_INIT_1_BINARY <= "010100"; when 21 => SATA_MIN_INIT_1_BINARY <= "010101"; when 22 => SATA_MIN_INIT_1_BINARY <= "010110"; when 23 => SATA_MIN_INIT_1_BINARY <= "010111"; when 24 => SATA_MIN_INIT_1_BINARY <= "011000"; when 25 => SATA_MIN_INIT_1_BINARY <= "011001"; when 26 => SATA_MIN_INIT_1_BINARY <= "011010"; when 27 => SATA_MIN_INIT_1_BINARY <= "011011"; when 28 => SATA_MIN_INIT_1_BINARY <= "011100"; when 29 => SATA_MIN_INIT_1_BINARY <= "011101"; when 30 => SATA_MIN_INIT_1_BINARY <= "011110"; when 31 => SATA_MIN_INIT_1_BINARY <= "011111"; when 32 => SATA_MIN_INIT_1_BINARY <= "100000"; when 33 => SATA_MIN_INIT_1_BINARY <= "100001"; when 34 => SATA_MIN_INIT_1_BINARY <= "100010"; when 35 => SATA_MIN_INIT_1_BINARY <= "100011"; when 36 => SATA_MIN_INIT_1_BINARY <= "100100"; when 37 => SATA_MIN_INIT_1_BINARY <= "100101"; when 38 => SATA_MIN_INIT_1_BINARY <= "100110"; when 39 => SATA_MIN_INIT_1_BINARY <= "100111"; when 40 => SATA_MIN_INIT_1_BINARY <= "101000"; when 41 => SATA_MIN_INIT_1_BINARY <= "101001"; when 42 => SATA_MIN_INIT_1_BINARY <= "101010"; when 43 => SATA_MIN_INIT_1_BINARY <= "101011"; when 44 => SATA_MIN_INIT_1_BINARY <= "101100"; when 45 => SATA_MIN_INIT_1_BINARY <= "101101"; when 46 => SATA_MIN_INIT_1_BINARY <= "101110"; when 47 => SATA_MIN_INIT_1_BINARY <= "101111"; when 48 => SATA_MIN_INIT_1_BINARY <= "110000"; when 49 => SATA_MIN_INIT_1_BINARY <= "110001"; when 50 => SATA_MIN_INIT_1_BINARY <= "110010"; when 51 => SATA_MIN_INIT_1_BINARY <= "110011"; when 52 => SATA_MIN_INIT_1_BINARY <= "110100"; when 53 => SATA_MIN_INIT_1_BINARY <= "110101"; when 54 => SATA_MIN_INIT_1_BINARY <= "110110"; when 55 => SATA_MIN_INIT_1_BINARY <= "110111"; when 56 => SATA_MIN_INIT_1_BINARY <= "111000"; when 57 => SATA_MIN_INIT_1_BINARY <= "111001"; when 58 => SATA_MIN_INIT_1_BINARY <= "111010"; when 59 => SATA_MIN_INIT_1_BINARY <= "111011"; when 60 => SATA_MIN_INIT_1_BINARY <= "111100"; when 61 => SATA_MIN_INIT_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_INIT_1 is not in range 1...61." severity error; end case; case SATA_MAX_INIT_1 is when 1 => SATA_MAX_INIT_1_BINARY <= "000001"; when 2 => SATA_MAX_INIT_1_BINARY <= "000010"; when 3 => SATA_MAX_INIT_1_BINARY <= "000011"; when 4 => SATA_MAX_INIT_1_BINARY <= "000100"; when 5 => SATA_MAX_INIT_1_BINARY <= "000101"; when 6 => SATA_MAX_INIT_1_BINARY <= "000110"; when 7 => SATA_MAX_INIT_1_BINARY <= "000111"; when 8 => SATA_MAX_INIT_1_BINARY <= "001000"; when 9 => SATA_MAX_INIT_1_BINARY <= "001001"; when 10 => SATA_MAX_INIT_1_BINARY <= "001010"; when 11 => SATA_MAX_INIT_1_BINARY <= "001011"; when 12 => SATA_MAX_INIT_1_BINARY <= "001100"; when 13 => SATA_MAX_INIT_1_BINARY <= "001101"; when 14 => SATA_MAX_INIT_1_BINARY <= "001110"; when 15 => SATA_MAX_INIT_1_BINARY <= "001111"; when 16 => SATA_MAX_INIT_1_BINARY <= "010000"; when 17 => SATA_MAX_INIT_1_BINARY <= "010001"; when 18 => SATA_MAX_INIT_1_BINARY <= "010010"; when 19 => SATA_MAX_INIT_1_BINARY <= "010011"; when 20 => SATA_MAX_INIT_1_BINARY <= "010100"; when 21 => SATA_MAX_INIT_1_BINARY <= "010101"; when 22 => SATA_MAX_INIT_1_BINARY <= "010110"; when 23 => SATA_MAX_INIT_1_BINARY <= "010111"; when 24 => SATA_MAX_INIT_1_BINARY <= "011000"; when 25 => SATA_MAX_INIT_1_BINARY <= "011001"; when 26 => SATA_MAX_INIT_1_BINARY <= "011010"; when 27 => SATA_MAX_INIT_1_BINARY <= "011011"; when 28 => SATA_MAX_INIT_1_BINARY <= "011100"; when 29 => SATA_MAX_INIT_1_BINARY <= "011101"; when 30 => SATA_MAX_INIT_1_BINARY <= "011110"; when 31 => SATA_MAX_INIT_1_BINARY <= "011111"; when 32 => SATA_MAX_INIT_1_BINARY <= "100000"; when 33 => SATA_MAX_INIT_1_BINARY <= "100001"; when 34 => SATA_MAX_INIT_1_BINARY <= "100010"; when 35 => SATA_MAX_INIT_1_BINARY <= "100011"; when 36 => SATA_MAX_INIT_1_BINARY <= "100100"; when 37 => SATA_MAX_INIT_1_BINARY <= "100101"; when 38 => SATA_MAX_INIT_1_BINARY <= "100110"; when 39 => SATA_MAX_INIT_1_BINARY <= "100111"; when 40 => SATA_MAX_INIT_1_BINARY <= "101000"; when 41 => SATA_MAX_INIT_1_BINARY <= "101001"; when 42 => SATA_MAX_INIT_1_BINARY <= "101010"; when 43 => SATA_MAX_INIT_1_BINARY <= "101011"; when 44 => SATA_MAX_INIT_1_BINARY <= "101100"; when 45 => SATA_MAX_INIT_1_BINARY <= "101101"; when 46 => SATA_MAX_INIT_1_BINARY <= "101110"; when 47 => SATA_MAX_INIT_1_BINARY <= "101111"; when 48 => SATA_MAX_INIT_1_BINARY <= "110000"; when 49 => SATA_MAX_INIT_1_BINARY <= "110001"; when 50 => SATA_MAX_INIT_1_BINARY <= "110010"; when 51 => SATA_MAX_INIT_1_BINARY <= "110011"; when 52 => SATA_MAX_INIT_1_BINARY <= "110100"; when 53 => SATA_MAX_INIT_1_BINARY <= "110101"; when 54 => SATA_MAX_INIT_1_BINARY <= "110110"; when 55 => SATA_MAX_INIT_1_BINARY <= "110111"; when 56 => SATA_MAX_INIT_1_BINARY <= "111000"; when 57 => SATA_MAX_INIT_1_BINARY <= "111001"; when 58 => SATA_MAX_INIT_1_BINARY <= "111010"; when 59 => SATA_MAX_INIT_1_BINARY <= "111011"; when 60 => SATA_MAX_INIT_1_BINARY <= "111100"; when 61 => SATA_MAX_INIT_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_INIT_1 is not in range 1...61." severity error; end case; case SATA_MIN_WAKE_1 is when 1 => SATA_MIN_WAKE_1_BINARY <= "000001"; when 2 => SATA_MIN_WAKE_1_BINARY <= "000010"; when 3 => SATA_MIN_WAKE_1_BINARY <= "000011"; when 4 => SATA_MIN_WAKE_1_BINARY <= "000100"; when 5 => SATA_MIN_WAKE_1_BINARY <= "000101"; when 6 => SATA_MIN_WAKE_1_BINARY <= "000110"; when 7 => SATA_MIN_WAKE_1_BINARY <= "000111"; when 8 => SATA_MIN_WAKE_1_BINARY <= "001000"; when 9 => SATA_MIN_WAKE_1_BINARY <= "001001"; when 10 => SATA_MIN_WAKE_1_BINARY <= "001010"; when 11 => SATA_MIN_WAKE_1_BINARY <= "001011"; when 12 => SATA_MIN_WAKE_1_BINARY <= "001100"; when 13 => SATA_MIN_WAKE_1_BINARY <= "001101"; when 14 => SATA_MIN_WAKE_1_BINARY <= "001110"; when 15 => SATA_MIN_WAKE_1_BINARY <= "001111"; when 16 => SATA_MIN_WAKE_1_BINARY <= "010000"; when 17 => SATA_MIN_WAKE_1_BINARY <= "010001"; when 18 => SATA_MIN_WAKE_1_BINARY <= "010010"; when 19 => SATA_MIN_WAKE_1_BINARY <= "010011"; when 20 => SATA_MIN_WAKE_1_BINARY <= "010100"; when 21 => SATA_MIN_WAKE_1_BINARY <= "010101"; when 22 => SATA_MIN_WAKE_1_BINARY <= "010110"; when 23 => SATA_MIN_WAKE_1_BINARY <= "010111"; when 24 => SATA_MIN_WAKE_1_BINARY <= "011000"; when 25 => SATA_MIN_WAKE_1_BINARY <= "011001"; when 26 => SATA_MIN_WAKE_1_BINARY <= "011010"; when 27 => SATA_MIN_WAKE_1_BINARY <= "011011"; when 28 => SATA_MIN_WAKE_1_BINARY <= "011100"; when 29 => SATA_MIN_WAKE_1_BINARY <= "011101"; when 30 => SATA_MIN_WAKE_1_BINARY <= "011110"; when 31 => SATA_MIN_WAKE_1_BINARY <= "011111"; when 32 => SATA_MIN_WAKE_1_BINARY <= "100000"; when 33 => SATA_MIN_WAKE_1_BINARY <= "100001"; when 34 => SATA_MIN_WAKE_1_BINARY <= "100010"; when 35 => SATA_MIN_WAKE_1_BINARY <= "100011"; when 36 => SATA_MIN_WAKE_1_BINARY <= "100100"; when 37 => SATA_MIN_WAKE_1_BINARY <= "100101"; when 38 => SATA_MIN_WAKE_1_BINARY <= "100110"; when 39 => SATA_MIN_WAKE_1_BINARY <= "100111"; when 40 => SATA_MIN_WAKE_1_BINARY <= "101000"; when 41 => SATA_MIN_WAKE_1_BINARY <= "101001"; when 42 => SATA_MIN_WAKE_1_BINARY <= "101010"; when 43 => SATA_MIN_WAKE_1_BINARY <= "101011"; when 44 => SATA_MIN_WAKE_1_BINARY <= "101100"; when 45 => SATA_MIN_WAKE_1_BINARY <= "101101"; when 46 => SATA_MIN_WAKE_1_BINARY <= "101110"; when 47 => SATA_MIN_WAKE_1_BINARY <= "101111"; when 48 => SATA_MIN_WAKE_1_BINARY <= "110000"; when 49 => SATA_MIN_WAKE_1_BINARY <= "110001"; when 50 => SATA_MIN_WAKE_1_BINARY <= "110010"; when 51 => SATA_MIN_WAKE_1_BINARY <= "110011"; when 52 => SATA_MIN_WAKE_1_BINARY <= "110100"; when 53 => SATA_MIN_WAKE_1_BINARY <= "110101"; when 54 => SATA_MIN_WAKE_1_BINARY <= "110110"; when 55 => SATA_MIN_WAKE_1_BINARY <= "110111"; when 56 => SATA_MIN_WAKE_1_BINARY <= "111000"; when 57 => SATA_MIN_WAKE_1_BINARY <= "111001"; when 58 => SATA_MIN_WAKE_1_BINARY <= "111010"; when 59 => SATA_MIN_WAKE_1_BINARY <= "111011"; when 60 => SATA_MIN_WAKE_1_BINARY <= "111100"; when 61 => SATA_MIN_WAKE_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_WAKE_1 is not in range 1...61." severity error; end case; case SATA_MAX_WAKE_1 is when 1 => SATA_MAX_WAKE_1_BINARY <= "000001"; when 2 => SATA_MAX_WAKE_1_BINARY <= "000010"; when 3 => SATA_MAX_WAKE_1_BINARY <= "000011"; when 4 => SATA_MAX_WAKE_1_BINARY <= "000100"; when 5 => SATA_MAX_WAKE_1_BINARY <= "000101"; when 6 => SATA_MAX_WAKE_1_BINARY <= "000110"; when 7 => SATA_MAX_WAKE_1_BINARY <= "000111"; when 8 => SATA_MAX_WAKE_1_BINARY <= "001000"; when 9 => SATA_MAX_WAKE_1_BINARY <= "001001"; when 10 => SATA_MAX_WAKE_1_BINARY <= "001010"; when 11 => SATA_MAX_WAKE_1_BINARY <= "001011"; when 12 => SATA_MAX_WAKE_1_BINARY <= "001100"; when 13 => SATA_MAX_WAKE_1_BINARY <= "001101"; when 14 => SATA_MAX_WAKE_1_BINARY <= "001110"; when 15 => SATA_MAX_WAKE_1_BINARY <= "001111"; when 16 => SATA_MAX_WAKE_1_BINARY <= "010000"; when 17 => SATA_MAX_WAKE_1_BINARY <= "010001"; when 18 => SATA_MAX_WAKE_1_BINARY <= "010010"; when 19 => SATA_MAX_WAKE_1_BINARY <= "010011"; when 20 => SATA_MAX_WAKE_1_BINARY <= "010100"; when 21 => SATA_MAX_WAKE_1_BINARY <= "010101"; when 22 => SATA_MAX_WAKE_1_BINARY <= "010110"; when 23 => SATA_MAX_WAKE_1_BINARY <= "010111"; when 24 => SATA_MAX_WAKE_1_BINARY <= "011000"; when 25 => SATA_MAX_WAKE_1_BINARY <= "011001"; when 26 => SATA_MAX_WAKE_1_BINARY <= "011010"; when 27 => SATA_MAX_WAKE_1_BINARY <= "011011"; when 28 => SATA_MAX_WAKE_1_BINARY <= "011100"; when 29 => SATA_MAX_WAKE_1_BINARY <= "011101"; when 30 => SATA_MAX_WAKE_1_BINARY <= "011110"; when 31 => SATA_MAX_WAKE_1_BINARY <= "011111"; when 32 => SATA_MAX_WAKE_1_BINARY <= "100000"; when 33 => SATA_MAX_WAKE_1_BINARY <= "100001"; when 34 => SATA_MAX_WAKE_1_BINARY <= "100010"; when 35 => SATA_MAX_WAKE_1_BINARY <= "100011"; when 36 => SATA_MAX_WAKE_1_BINARY <= "100100"; when 37 => SATA_MAX_WAKE_1_BINARY <= "100101"; when 38 => SATA_MAX_WAKE_1_BINARY <= "100110"; when 39 => SATA_MAX_WAKE_1_BINARY <= "100111"; when 40 => SATA_MAX_WAKE_1_BINARY <= "101000"; when 41 => SATA_MAX_WAKE_1_BINARY <= "101001"; when 42 => SATA_MAX_WAKE_1_BINARY <= "101010"; when 43 => SATA_MAX_WAKE_1_BINARY <= "101011"; when 44 => SATA_MAX_WAKE_1_BINARY <= "101100"; when 45 => SATA_MAX_WAKE_1_BINARY <= "101101"; when 46 => SATA_MAX_WAKE_1_BINARY <= "101110"; when 47 => SATA_MAX_WAKE_1_BINARY <= "101111"; when 48 => SATA_MAX_WAKE_1_BINARY <= "110000"; when 49 => SATA_MAX_WAKE_1_BINARY <= "110001"; when 50 => SATA_MAX_WAKE_1_BINARY <= "110010"; when 51 => SATA_MAX_WAKE_1_BINARY <= "110011"; when 52 => SATA_MAX_WAKE_1_BINARY <= "110100"; when 53 => SATA_MAX_WAKE_1_BINARY <= "110101"; when 54 => SATA_MAX_WAKE_1_BINARY <= "110110"; when 55 => SATA_MAX_WAKE_1_BINARY <= "110111"; when 56 => SATA_MAX_WAKE_1_BINARY <= "111000"; when 57 => SATA_MAX_WAKE_1_BINARY <= "111001"; when 58 => SATA_MAX_WAKE_1_BINARY <= "111010"; when 59 => SATA_MAX_WAKE_1_BINARY <= "111011"; when 60 => SATA_MAX_WAKE_1_BINARY <= "111100"; when 61 => SATA_MAX_WAKE_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_WAKE_1 is not in range 1...61." severity error; end case; case CLK25_DIVIDER is when 1 => CLK25_DIVIDER_BINARY <= "000"; when 2 => CLK25_DIVIDER_BINARY <= "001"; when 3 => CLK25_DIVIDER_BINARY <= "010"; when 4 => CLK25_DIVIDER_BINARY <= "011"; when 5 => CLK25_DIVIDER_BINARY <= "100"; when 6 => CLK25_DIVIDER_BINARY <= "101"; when 10 => CLK25_DIVIDER_BINARY <= "110"; when 12 => CLK25_DIVIDER_BINARY <= "111"; when others => assert FALSE report "Error : CLK25_DIVIDER is not in 1, 2, 3, 4, 5, 6, 10, 12." severity error; end case; case OVERSAMPLE_MODE is when FALSE => OVERSAMPLE_MODE_BINARY <= '0'; when TRUE => OVERSAMPLE_MODE_BINARY <= '1'; when others => assert FALSE report "Error : OVERSAMPLE_MODE is neither TRUE nor FALSE." severity error; end case; case SIM_GTPRESET_SPEEDUP is when 0 => SIM_GTPRESET_SPEEDUP_BINARY <= '0'; when 1 => SIM_GTPRESET_SPEEDUP_BINARY <= '1'; when others => assert FALSE report "Error : SIM_GTPRESET_SPEEDUP is not in 0, 1." severity error; end case; -- case SIM_MODE is if((SIM_MODE = "LEGACY") or (SIM_MODE = "legacy")) then SIM_MODE_BINARY <= '1'; elsif((SIM_MODE = "FAST") or (SIM_MODE = "fast")) then SIM_MODE_BINARY <= '0'; else assert FALSE report "Error : SIM_MODE = is not LEGACY, FAST." severity error; end if; -- end case; case SIM_RECEIVER_DETECT_PASS0 is when FALSE => SIM_RECEIVER_DETECT_PASS0_BINARY <= '0'; when TRUE => SIM_RECEIVER_DETECT_PASS0_BINARY <= '1'; when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS0 is neither TRUE nor FALSE." severity error; end case; case SIM_RECEIVER_DETECT_PASS1 is when FALSE => SIM_RECEIVER_DETECT_PASS1_BINARY <= '0'; when TRUE => SIM_RECEIVER_DETECT_PASS1_BINARY <= '1'; when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS1 is neither TRUE nor FALSE." severity error; end case; wait; end process INIPROC; TIMING : process -- Pin timing violations (clock input pins) -- Pin Timing Violations (all input pins) -- Output Pin glitch declaration variable REFCLKOUT_GlitchData : VitalGlitchDataType; variable RXRECCLK0_GlitchData : VitalGlitchDataType; variable TXOUTCLK0_GlitchData : VitalGlitchDataType; variable RXRECCLK1_GlitchData : VitalGlitchDataType; variable TXOUTCLK1_GlitchData : VitalGlitchDataType; variable TXP0_GlitchData : VitalGlitchDataType; variable TXN0_GlitchData : VitalGlitchDataType; variable TXP1_GlitchData : VitalGlitchDataType; variable TXN1_GlitchData : VitalGlitchDataType; variable RXDATA00_GlitchData : VitalGlitchDataType; variable RXDATA01_GlitchData : VitalGlitchDataType; variable RXDATA02_GlitchData : VitalGlitchDataType; variable RXDATA03_GlitchData : VitalGlitchDataType; variable RXDATA04_GlitchData : VitalGlitchDataType; variable RXDATA05_GlitchData : VitalGlitchDataType; variable RXDATA06_GlitchData : VitalGlitchDataType; variable RXDATA07_GlitchData : VitalGlitchDataType; variable RXDATA08_GlitchData : VitalGlitchDataType; variable RXDATA09_GlitchData : VitalGlitchDataType; variable RXDATA010_GlitchData : VitalGlitchDataType; variable RXDATA011_GlitchData : VitalGlitchDataType; variable RXDATA012_GlitchData : VitalGlitchDataType; variable RXDATA013_GlitchData : VitalGlitchDataType; variable RXDATA014_GlitchData : VitalGlitchDataType; variable RXDATA015_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE00_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE01_GlitchData : VitalGlitchDataType; variable RXDISPERR00_GlitchData : VitalGlitchDataType; variable RXDISPERR01_GlitchData : VitalGlitchDataType; variable RXCHARISK00_GlitchData : VitalGlitchDataType; variable RXCHARISK01_GlitchData : VitalGlitchDataType; variable RXRUNDISP00_GlitchData : VitalGlitchDataType; variable RXRUNDISP01_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA00_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA01_GlitchData : VitalGlitchDataType; variable RXVALID0_GlitchData : VitalGlitchDataType; variable RXDATA10_GlitchData : VitalGlitchDataType; variable RXDATA11_GlitchData : VitalGlitchDataType; variable RXDATA12_GlitchData : VitalGlitchDataType; variable RXDATA13_GlitchData : VitalGlitchDataType; variable RXDATA14_GlitchData : VitalGlitchDataType; variable RXDATA15_GlitchData : VitalGlitchDataType; variable RXDATA16_GlitchData : VitalGlitchDataType; variable RXDATA17_GlitchData : VitalGlitchDataType; variable RXDATA18_GlitchData : VitalGlitchDataType; variable RXDATA19_GlitchData : VitalGlitchDataType; variable RXDATA110_GlitchData : VitalGlitchDataType; variable RXDATA111_GlitchData : VitalGlitchDataType; variable RXDATA112_GlitchData : VitalGlitchDataType; variable RXDATA113_GlitchData : VitalGlitchDataType; variable RXDATA114_GlitchData : VitalGlitchDataType; variable RXDATA115_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE10_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE11_GlitchData : VitalGlitchDataType; variable RXDISPERR10_GlitchData : VitalGlitchDataType; variable RXDISPERR11_GlitchData : VitalGlitchDataType; variable RXCHARISK10_GlitchData : VitalGlitchDataType; variable RXCHARISK11_GlitchData : VitalGlitchDataType; variable RXRUNDISP10_GlitchData : VitalGlitchDataType; variable RXRUNDISP11_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA10_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA11_GlitchData : VitalGlitchDataType; variable RXVALID1_GlitchData : VitalGlitchDataType; variable RESETDONE0_GlitchData : VitalGlitchDataType; variable RESETDONE1_GlitchData : VitalGlitchDataType; variable TXKERR00_GlitchData : VitalGlitchDataType; variable TXKERR01_GlitchData : VitalGlitchDataType; variable TXRUNDISP00_GlitchData : VitalGlitchDataType; variable TXRUNDISP01_GlitchData : VitalGlitchDataType; variable TXBUFSTATUS00_GlitchData : VitalGlitchDataType; variable TXBUFSTATUS01_GlitchData : VitalGlitchDataType; variable TXKERR10_GlitchData : VitalGlitchDataType; variable TXKERR11_GlitchData : VitalGlitchDataType; variable TXRUNDISP10_GlitchData : VitalGlitchDataType; variable TXRUNDISP11_GlitchData : VitalGlitchDataType; variable TXBUFSTATUS10_GlitchData : VitalGlitchDataType; variable TXBUFSTATUS11_GlitchData : VitalGlitchDataType; variable RXCOMMADET0_GlitchData : VitalGlitchDataType; variable RXBYTEREALIGN0_GlitchData : VitalGlitchDataType; variable RXBYTEISALIGNED0_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC00_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC01_GlitchData : VitalGlitchDataType; variable RXCHBONDO00_GlitchData : VitalGlitchDataType; variable RXCHBONDO01_GlitchData : VitalGlitchDataType; variable RXCHBONDO02_GlitchData : VitalGlitchDataType; variable RXCHANBONDSEQ0_GlitchData : VitalGlitchDataType; variable RXCHANREALIGN0_GlitchData : VitalGlitchDataType; variable RXCHANISALIGNED0_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS00_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS01_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS02_GlitchData : VitalGlitchDataType; variable RXCOMMADET1_GlitchData : VitalGlitchDataType; variable RXBYTEREALIGN1_GlitchData : VitalGlitchDataType; variable RXBYTEISALIGNED1_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC10_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC11_GlitchData : VitalGlitchDataType; variable RXCHBONDO10_GlitchData : VitalGlitchDataType; variable RXCHBONDO11_GlitchData : VitalGlitchDataType; variable RXCHBONDO12_GlitchData : VitalGlitchDataType; variable RXCHANBONDSEQ1_GlitchData : VitalGlitchDataType; variable RXCHANREALIGN1_GlitchData : VitalGlitchDataType; variable RXCHANISALIGNED1_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS10_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS11_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS12_GlitchData : VitalGlitchDataType; variable PHYSTATUS0_GlitchData : VitalGlitchDataType; variable PHYSTATUS1_GlitchData : VitalGlitchDataType; variable RXELECIDLE0_GlitchData : VitalGlitchDataType; variable RXSTATUS00_GlitchData : VitalGlitchDataType; variable RXSTATUS01_GlitchData : VitalGlitchDataType; variable RXSTATUS02_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT00_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT01_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT02_GlitchData : VitalGlitchDataType; variable RXELECIDLE1_GlitchData : VitalGlitchDataType; variable RXSTATUS10_GlitchData : VitalGlitchDataType; variable RXSTATUS11_GlitchData : VitalGlitchDataType; variable RXSTATUS12_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT10_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT11_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT12_GlitchData : VitalGlitchDataType; variable PLLLKDET_GlitchData : VitalGlitchDataType; variable RXPRBSERR0_GlitchData : VitalGlitchDataType; variable RXPRBSERR1_GlitchData : VitalGlitchDataType; variable DO0_GlitchData : VitalGlitchDataType; variable DO1_GlitchData : VitalGlitchDataType; variable DO2_GlitchData : VitalGlitchDataType; variable DO3_GlitchData : VitalGlitchDataType; variable DO4_GlitchData : VitalGlitchDataType; variable DO5_GlitchData : VitalGlitchDataType; variable DO6_GlitchData : VitalGlitchDataType; variable DO7_GlitchData : VitalGlitchDataType; variable DO8_GlitchData : VitalGlitchDataType; variable DO9_GlitchData : VitalGlitchDataType; variable DO10_GlitchData : VitalGlitchDataType; variable DO11_GlitchData : VitalGlitchDataType; variable DO12_GlitchData : VitalGlitchDataType; variable DO13_GlitchData : VitalGlitchDataType; variable DO14_GlitchData : VitalGlitchDataType; variable DO15_GlitchData : VitalGlitchDataType; variable DRDY_GlitchData : VitalGlitchDataType; variable RXOVERSAMPLEERR0_GlitchData : VitalGlitchDataType; variable RXOVERSAMPLEERR1_GlitchData : VitalGlitchDataType; begin -- Output-to-Clock path delay VitalPathDelay01 ( OutSignal => REFCLKOUT, GlitchData => REFCLKOUT_GlitchData, OutSignalName => "REFCLKOUT", OutTemp => REFCLKOUT_OUT, Paths => (0 => (CLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(0), GlitchData => RXDATA00_GlitchData, OutSignalName => "RXDATA0(0)", OutTemp => RXDATA0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(1), GlitchData => RXDATA01_GlitchData, OutSignalName => "RXDATA0(1)", OutTemp => RXDATA0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(2), GlitchData => RXDATA02_GlitchData, OutSignalName => "RXDATA0(2)", OutTemp => RXDATA0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(3), GlitchData => RXDATA03_GlitchData, OutSignalName => "RXDATA0(3)", OutTemp => RXDATA0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(4), GlitchData => RXDATA04_GlitchData, OutSignalName => "RXDATA0(4)", OutTemp => RXDATA0_OUT(4), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(5), GlitchData => RXDATA05_GlitchData, OutSignalName => "RXDATA0(5)", OutTemp => RXDATA0_OUT(5), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(6), GlitchData => RXDATA06_GlitchData, OutSignalName => "RXDATA0(6)", OutTemp => RXDATA0_OUT(6), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(7), GlitchData => RXDATA07_GlitchData, OutSignalName => "RXDATA0(7)", OutTemp => RXDATA0_OUT(7), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(8), GlitchData => RXDATA08_GlitchData, OutSignalName => "RXDATA0(8)", OutTemp => RXDATA0_OUT(8), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(9), GlitchData => RXDATA09_GlitchData, OutSignalName => "RXDATA0(9)", OutTemp => RXDATA0_OUT(9), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(10), GlitchData => RXDATA010_GlitchData, OutSignalName => "RXDATA0(10)", OutTemp => RXDATA0_OUT(10), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(11), GlitchData => RXDATA011_GlitchData, OutSignalName => "RXDATA0(11)", OutTemp => RXDATA0_OUT(11), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(12), GlitchData => RXDATA012_GlitchData, OutSignalName => "RXDATA0(12)", OutTemp => RXDATA0_OUT(12), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(13), GlitchData => RXDATA013_GlitchData, OutSignalName => "RXDATA0(13)", OutTemp => RXDATA0_OUT(13), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(14), GlitchData => RXDATA014_GlitchData, OutSignalName => "RXDATA0(14)", OutTemp => RXDATA0_OUT(14), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(15), GlitchData => RXDATA015_GlitchData, OutSignalName => "RXDATA0(15)", OutTemp => RXDATA0_OUT(15), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE0(0), GlitchData => RXNOTINTABLE00_GlitchData, OutSignalName => "RXNOTINTABLE0(0)", OutTemp => RXNOTINTABLE0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE0(1), GlitchData => RXNOTINTABLE01_GlitchData, OutSignalName => "RXNOTINTABLE0(1)", OutTemp => RXNOTINTABLE0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR0(0), GlitchData => RXDISPERR00_GlitchData, OutSignalName => "RXDISPERR0(0)", OutTemp => RXDISPERR0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR0(1), GlitchData => RXDISPERR01_GlitchData, OutSignalName => "RXDISPERR0(1)", OutTemp => RXDISPERR0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK0(0), GlitchData => RXCHARISK00_GlitchData, OutSignalName => "RXCHARISK0(0)", OutTemp => RXCHARISK0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK0(1), GlitchData => RXCHARISK01_GlitchData, OutSignalName => "RXCHARISK0(1)", OutTemp => RXCHARISK0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP0(0), GlitchData => RXRUNDISP00_GlitchData, OutSignalName => "RXRUNDISP0(0)", OutTemp => RXRUNDISP0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP0(1), GlitchData => RXRUNDISP01_GlitchData, OutSignalName => "RXRUNDISP0(1)", OutTemp => RXRUNDISP0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA0(0), GlitchData => RXCHARISCOMMA00_GlitchData, OutSignalName => "RXCHARISCOMMA0(0)", OutTemp => RXCHARISCOMMA0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA0(1), GlitchData => RXCHARISCOMMA01_GlitchData, OutSignalName => "RXCHARISCOMMA0(1)", OutTemp => RXCHARISCOMMA0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXVALID0, GlitchData => RXVALID0_GlitchData, OutSignalName => "RXVALID0", OutTemp => RXVALID0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(0), GlitchData => RXDATA10_GlitchData, OutSignalName => "RXDATA1(0)", OutTemp => RXDATA1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(1), GlitchData => RXDATA11_GlitchData, OutSignalName => "RXDATA1(1)", OutTemp => RXDATA1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(2), GlitchData => RXDATA12_GlitchData, OutSignalName => "RXDATA1(2)", OutTemp => RXDATA1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(3), GlitchData => RXDATA13_GlitchData, OutSignalName => "RXDATA1(3)", OutTemp => RXDATA1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(4), GlitchData => RXDATA14_GlitchData, OutSignalName => "RXDATA1(4)", OutTemp => RXDATA1_OUT(4), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(5), GlitchData => RXDATA15_GlitchData, OutSignalName => "RXDATA1(5)", OutTemp => RXDATA1_OUT(5), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(6), GlitchData => RXDATA16_GlitchData, OutSignalName => "RXDATA1(6)", OutTemp => RXDATA1_OUT(6), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(7), GlitchData => RXDATA17_GlitchData, OutSignalName => "RXDATA1(7)", OutTemp => RXDATA1_OUT(7), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(8), GlitchData => RXDATA18_GlitchData, OutSignalName => "RXDATA1(8)", OutTemp => RXDATA1_OUT(8), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(9), GlitchData => RXDATA19_GlitchData, OutSignalName => "RXDATA1(9)", OutTemp => RXDATA1_OUT(9), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(10), GlitchData => RXDATA110_GlitchData, OutSignalName => "RXDATA1(10)", OutTemp => RXDATA1_OUT(10), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(11), GlitchData => RXDATA111_GlitchData, OutSignalName => "RXDATA1(11)", OutTemp => RXDATA1_OUT(11), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(12), GlitchData => RXDATA112_GlitchData, OutSignalName => "RXDATA1(12)", OutTemp => RXDATA1_OUT(12), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(13), GlitchData => RXDATA113_GlitchData, OutSignalName => "RXDATA1(13)", OutTemp => RXDATA1_OUT(13), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(14), GlitchData => RXDATA114_GlitchData, OutSignalName => "RXDATA1(14)", OutTemp => RXDATA1_OUT(14), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(15), GlitchData => RXDATA115_GlitchData, OutSignalName => "RXDATA1(15)", OutTemp => RXDATA1_OUT(15), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE1(0), GlitchData => RXNOTINTABLE10_GlitchData, OutSignalName => "RXNOTINTABLE1(0)", OutTemp => RXNOTINTABLE1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE1(1), GlitchData => RXNOTINTABLE11_GlitchData, OutSignalName => "RXNOTINTABLE1(1)", OutTemp => RXNOTINTABLE1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR1(0), GlitchData => RXDISPERR10_GlitchData, OutSignalName => "RXDISPERR1(0)", OutTemp => RXDISPERR1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR1(1), GlitchData => RXDISPERR11_GlitchData, OutSignalName => "RXDISPERR1(1)", OutTemp => RXDISPERR1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK1(0), GlitchData => RXCHARISK10_GlitchData, OutSignalName => "RXCHARISK1(0)", OutTemp => RXCHARISK1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK1(1), GlitchData => RXCHARISK11_GlitchData, OutSignalName => "RXCHARISK1(1)", OutTemp => RXCHARISK1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP1(0), GlitchData => RXRUNDISP10_GlitchData, OutSignalName => "RXRUNDISP1(0)", OutTemp => RXRUNDISP1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP1(1), GlitchData => RXRUNDISP11_GlitchData, OutSignalName => "RXRUNDISP1(1)", OutTemp => RXRUNDISP1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA1(0), GlitchData => RXCHARISCOMMA10_GlitchData, OutSignalName => "RXCHARISCOMMA1(0)", OutTemp => RXCHARISCOMMA1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA1(1), GlitchData => RXCHARISCOMMA11_GlitchData, OutSignalName => "RXCHARISCOMMA1(1)", OutTemp => RXCHARISCOMMA1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXVALID1, GlitchData => RXVALID1_GlitchData, OutSignalName => "RXVALID1", OutTemp => RXVALID1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR0(0), GlitchData => TXKERR00_GlitchData, OutSignalName => "TXKERR0(0)", OutTemp => TXKERR0_OUT(0), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR0(1), GlitchData => TXKERR01_GlitchData, OutSignalName => "TXKERR0(1)", OutTemp => TXKERR0_OUT(1), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP0(0), GlitchData => TXRUNDISP00_GlitchData, OutSignalName => "TXRUNDISP0(0)", OutTemp => TXRUNDISP0_OUT(0), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP0(1), GlitchData => TXRUNDISP01_GlitchData, OutSignalName => "TXRUNDISP0(1)", OutTemp => TXRUNDISP0_OUT(1), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXBUFSTATUS0(0), GlitchData => TXBUFSTATUS00_GlitchData, OutSignalName => "TXBUFSTATUS0(0)", OutTemp => TXBUFSTATUS0_OUT(0), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXBUFSTATUS0(1), GlitchData => TXBUFSTATUS01_GlitchData, OutSignalName => "TXBUFSTATUS0(1)", OutTemp => TXBUFSTATUS0_OUT(1), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR1(0), GlitchData => TXKERR10_GlitchData, OutSignalName => "TXKERR1(0)", OutTemp => TXKERR1_OUT(0), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR1(1), GlitchData => TXKERR11_GlitchData, OutSignalName => "TXKERR1(1)", OutTemp => TXKERR1_OUT(1), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP1(0), GlitchData => TXRUNDISP10_GlitchData, OutSignalName => "TXRUNDISP1(0)", OutTemp => TXRUNDISP1_OUT(0), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP1(1), GlitchData => TXRUNDISP11_GlitchData, OutSignalName => "TXRUNDISP1(1)", OutTemp => TXRUNDISP1_OUT(1), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXBUFSTATUS1(0), GlitchData => TXBUFSTATUS10_GlitchData, OutSignalName => "TXBUFSTATUS1(0)", OutTemp => TXBUFSTATUS1_OUT(0), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXBUFSTATUS1(1), GlitchData => TXBUFSTATUS11_GlitchData, OutSignalName => "TXBUFSTATUS1(1)", OutTemp => TXBUFSTATUS1_OUT(1), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCOMMADET0, GlitchData => RXCOMMADET0_GlitchData, OutSignalName => "RXCOMMADET0", OutTemp => RXCOMMADET0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBYTEREALIGN0, GlitchData => RXBYTEREALIGN0_GlitchData, OutSignalName => "RXBYTEREALIGN0", OutTemp => RXBYTEREALIGN0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBYTEISALIGNED0, GlitchData => RXBYTEISALIGNED0_GlitchData, OutSignalName => "RXBYTEISALIGNED0", OutTemp => RXBYTEISALIGNED0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC0(0), GlitchData => RXLOSSOFSYNC00_GlitchData, OutSignalName => "RXLOSSOFSYNC0(0)", OutTemp => RXLOSSOFSYNC0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC0(1), GlitchData => RXLOSSOFSYNC01_GlitchData, OutSignalName => "RXLOSSOFSYNC0(1)", OutTemp => RXLOSSOFSYNC0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO0(0), GlitchData => RXCHBONDO00_GlitchData, OutSignalName => "RXCHBONDO0(0)", OutTemp => RXCHBONDO0_OUT(0), Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO0(1), GlitchData => RXCHBONDO01_GlitchData, OutSignalName => "RXCHBONDO0(1)", OutTemp => RXCHBONDO0_OUT(1), Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO0(2), GlitchData => RXCHBONDO02_GlitchData, OutSignalName => "RXCHBONDO0(2)", OutTemp => RXCHBONDO0_OUT(2), Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANBONDSEQ0, GlitchData => RXCHANBONDSEQ0_GlitchData, OutSignalName => "RXCHANBONDSEQ0", OutTemp => RXCHANBONDSEQ0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANREALIGN0, GlitchData => RXCHANREALIGN0_GlitchData, OutSignalName => "RXCHANREALIGN0", OutTemp => RXCHANREALIGN0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANISALIGNED0, GlitchData => RXCHANISALIGNED0_GlitchData, OutSignalName => "RXCHANISALIGNED0", OutTemp => RXCHANISALIGNED0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS0(0), GlitchData => RXBUFSTATUS00_GlitchData, OutSignalName => "RXBUFSTATUS0(0)", OutTemp => RXBUFSTATUS0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS0(1), GlitchData => RXBUFSTATUS01_GlitchData, OutSignalName => "RXBUFSTATUS0(1)", OutTemp => RXBUFSTATUS0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS0(2), GlitchData => RXBUFSTATUS02_GlitchData, OutSignalName => "RXBUFSTATUS0(2)", OutTemp => RXBUFSTATUS0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCOMMADET1, GlitchData => RXCOMMADET1_GlitchData, OutSignalName => "RXCOMMADET1", OutTemp => RXCOMMADET1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBYTEREALIGN1, GlitchData => RXBYTEREALIGN1_GlitchData, OutSignalName => "RXBYTEREALIGN1", OutTemp => RXBYTEREALIGN1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBYTEISALIGNED1, GlitchData => RXBYTEISALIGNED1_GlitchData, OutSignalName => "RXBYTEISALIGNED1", OutTemp => RXBYTEISALIGNED1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC1(0), GlitchData => RXLOSSOFSYNC10_GlitchData, OutSignalName => "RXLOSSOFSYNC1(0)", OutTemp => RXLOSSOFSYNC1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC1(1), GlitchData => RXLOSSOFSYNC11_GlitchData, OutSignalName => "RXLOSSOFSYNC1(1)", OutTemp => RXLOSSOFSYNC1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO1(0), GlitchData => RXCHBONDO10_GlitchData, OutSignalName => "RXCHBONDO1(0)", OutTemp => RXCHBONDO1_OUT(0), Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO1(1), GlitchData => RXCHBONDO11_GlitchData, OutSignalName => "RXCHBONDO1(1)", OutTemp => RXCHBONDO1_OUT(1), Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO1(2), GlitchData => RXCHBONDO12_GlitchData, OutSignalName => "RXCHBONDO1(2)", OutTemp => RXCHBONDO1_OUT(2), Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANBONDSEQ1, GlitchData => RXCHANBONDSEQ1_GlitchData, OutSignalName => "RXCHANBONDSEQ1", OutTemp => RXCHANBONDSEQ1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANREALIGN1, GlitchData => RXCHANREALIGN1_GlitchData, OutSignalName => "RXCHANREALIGN1", OutTemp => RXCHANREALIGN1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANISALIGNED1, GlitchData => RXCHANISALIGNED1_GlitchData, OutSignalName => "RXCHANISALIGNED1", OutTemp => RXCHANISALIGNED1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS1(0), GlitchData => RXBUFSTATUS10_GlitchData, OutSignalName => "RXBUFSTATUS1(0)", OutTemp => RXBUFSTATUS1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS1(1), GlitchData => RXBUFSTATUS11_GlitchData, OutSignalName => "RXBUFSTATUS1(1)", OutTemp => RXBUFSTATUS1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS1(2), GlitchData => RXBUFSTATUS12_GlitchData, OutSignalName => "RXBUFSTATUS1(2)", OutTemp => RXBUFSTATUS1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS0(0), GlitchData => RXSTATUS00_GlitchData, OutSignalName => "RXSTATUS0(0)", OutTemp => RXSTATUS0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS0(1), GlitchData => RXSTATUS01_GlitchData, OutSignalName => "RXSTATUS0(1)", OutTemp => RXSTATUS0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS0(2), GlitchData => RXSTATUS02_GlitchData, OutSignalName => "RXSTATUS0(2)", OutTemp => RXSTATUS0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT0(0), GlitchData => RXCLKCORCNT00_GlitchData, OutSignalName => "RXCLKCORCNT0(0)", OutTemp => RXCLKCORCNT0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT0(1), GlitchData => RXCLKCORCNT01_GlitchData, OutSignalName => "RXCLKCORCNT0(1)", OutTemp => RXCLKCORCNT0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT0(2), GlitchData => RXCLKCORCNT02_GlitchData, OutSignalName => "RXCLKCORCNT0(2)", OutTemp => RXCLKCORCNT0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS1(0), GlitchData => RXSTATUS10_GlitchData, OutSignalName => "RXSTATUS1(0)", OutTemp => RXSTATUS1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS1(1), GlitchData => RXSTATUS11_GlitchData, OutSignalName => "RXSTATUS1(1)", OutTemp => RXSTATUS1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS1(2), GlitchData => RXSTATUS12_GlitchData, OutSignalName => "RXSTATUS1(2)", OutTemp => RXSTATUS1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT1(0), GlitchData => RXCLKCORCNT10_GlitchData, OutSignalName => "RXCLKCORCNT1(0)", OutTemp => RXCLKCORCNT1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT1(1), GlitchData => RXCLKCORCNT11_GlitchData, OutSignalName => "RXCLKCORCNT1(1)", OutTemp => RXCLKCORCNT1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT1(2), GlitchData => RXCLKCORCNT12_GlitchData, OutSignalName => "RXCLKCORCNT1(2)", OutTemp => RXCLKCORCNT1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXPRBSERR0, GlitchData => RXPRBSERR0_GlitchData, OutSignalName => "RXPRBSERR0", OutTemp => RXPRBSERR0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXPRBSERR1, GlitchData => RXPRBSERR1_GlitchData, OutSignalName => "RXPRBSERR1", OutTemp => RXPRBSERR1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(0), GlitchData => DO0_GlitchData, OutSignalName => "DO(0)", OutTemp => DO_OUT(0), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(1), GlitchData => DO1_GlitchData, OutSignalName => "DO(1)", OutTemp => DO_OUT(1), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(2), GlitchData => DO2_GlitchData, OutSignalName => "DO(2)", OutTemp => DO_OUT(2), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(3), GlitchData => DO3_GlitchData, OutSignalName => "DO(3)", OutTemp => DO_OUT(3), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(4), GlitchData => DO4_GlitchData, OutSignalName => "DO(4)", OutTemp => DO_OUT(4), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(5), GlitchData => DO5_GlitchData, OutSignalName => "DO(5)", OutTemp => DO_OUT(5), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(6), GlitchData => DO6_GlitchData, OutSignalName => "DO(6)", OutTemp => DO_OUT(6), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(7), GlitchData => DO7_GlitchData, OutSignalName => "DO(7)", OutTemp => DO_OUT(7), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(8), GlitchData => DO8_GlitchData, OutSignalName => "DO(8)", OutTemp => DO_OUT(8), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(9), GlitchData => DO9_GlitchData, OutSignalName => "DO(9)", OutTemp => DO_OUT(9), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(10), GlitchData => DO10_GlitchData, OutSignalName => "DO(10)", OutTemp => DO_OUT(10), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(11), GlitchData => DO11_GlitchData, OutSignalName => "DO(11)", OutTemp => DO_OUT(11), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(12), GlitchData => DO12_GlitchData, OutSignalName => "DO(12)", OutTemp => DO_OUT(12), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(13), GlitchData => DO13_GlitchData, OutSignalName => "DO(13)", OutTemp => DO_OUT(13), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(14), GlitchData => DO14_GlitchData, OutSignalName => "DO(14)", OutTemp => DO_OUT(14), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(15), GlitchData => DO15_GlitchData, OutSignalName => "DO(15)", OutTemp => DO_OUT(15), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DRDY, GlitchData => DRDY_GlitchData, OutSignalName => "DRDY", OutTemp => DRDY_OUT, Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXOVERSAMPLEERR0, GlitchData => RXOVERSAMPLEERR0_GlitchData, OutSignalName => "RXOVERSAMPLEERR0", OutTemp => RXOVERSAMPLEERR0_OUT, Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXOVERSAMPLEERR1, GlitchData => RXOVERSAMPLEERR1_GlitchData, OutSignalName => "RXOVERSAMPLEERR1", OutTemp => RXOVERSAMPLEERR1_OUT, Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); -- Wait signal (input/output pins) wait on DO_out, DRDY_out, REFCLKOUT_out, RXBUFSTATUS0_out, RXBUFSTATUS1_out, RXBYTEISALIGNED0_out, RXBYTEISALIGNED1_out, RXBYTEREALIGN0_out, RXBYTEREALIGN1_out, RXCHANBONDSEQ0_out, RXCHANBONDSEQ1_out, RXCHANISALIGNED0_out, RXCHANISALIGNED1_out, RXCHANREALIGN0_out, RXCHANREALIGN1_out, RXCHARISCOMMA0_out, RXCHARISCOMMA1_out, RXCHARISK0_out, RXCHARISK1_out, RXCHBONDO0_out, RXCHBONDO1_out, RXCLKCORCNT0_out, RXCLKCORCNT1_out, RXCOMMADET0_out, RXCOMMADET1_out, RXDATA0_out, RXDATA1_out, RXDISPERR0_out, RXDISPERR1_out, RXLOSSOFSYNC0_out, RXLOSSOFSYNC1_out, RXNOTINTABLE0_out, RXNOTINTABLE1_out, RXOVERSAMPLEERR0_out, RXOVERSAMPLEERR1_out, RXPRBSERR0_out, RXPRBSERR1_out, RXRUNDISP0_out, RXRUNDISP1_out, RXSTATUS0_out, RXSTATUS1_out, RXVALID0_out, RXVALID1_out, TXBUFSTATUS0_out, TXBUFSTATUS1_out, TXKERR0_out, TXKERR1_out, TXRUNDISP0_out, TXRUNDISP1_out, CLKIN_ipd, DADDR_ipd, DCLK_ipd, DEN_ipd, DI_ipd, DWE_ipd, GTPRESET_ipd, GTPTEST_ipd, INTDATAWIDTH_ipd, LOOPBACK0_ipd, LOOPBACK1_ipd, PLLLKDETEN_ipd, PLLPOWERDOWN_ipd, PRBSCNTRESET0_ipd, PRBSCNTRESET1_ipd, REFCLKPWRDNB_ipd, RXBUFRESET0_ipd, RXBUFRESET1_ipd, RXCDRRESET0_ipd, RXCDRRESET1_ipd, RXCHBONDI0_ipd, RXCHBONDI1_ipd, RXCOMMADETUSE0_ipd, RXCOMMADETUSE1_ipd, RXDATAWIDTH0_ipd, RXDATAWIDTH1_ipd, RXDEC8B10BUSE0_ipd, RXDEC8B10BUSE1_ipd, RXELECIDLERESET0_ipd, RXELECIDLERESET1_ipd, RXENCHANSYNC0_ipd, RXENCHANSYNC1_ipd, RXENELECIDLERESETB_ipd, RXENEQB0_ipd, RXENEQB1_ipd, RXENMCOMMAALIGN0_ipd, RXENMCOMMAALIGN1_ipd, RXENPCOMMAALIGN0_ipd, RXENPCOMMAALIGN1_ipd, RXENPRBSTST0_ipd, RXENPRBSTST1_ipd, RXENSAMPLEALIGN0_ipd, RXENSAMPLEALIGN1_ipd, RXEQMIX0_ipd, RXEQMIX1_ipd, RXEQPOLE0_ipd, RXEQPOLE1_ipd, RXN0_ipd, RXN1_ipd, RXP0_ipd, RXP1_ipd, RXPMASETPHASE0_ipd, RXPMASETPHASE1_ipd, RXPOLARITY0_ipd, RXPOLARITY1_ipd, RXPOWERDOWN0_ipd, RXPOWERDOWN1_ipd, RXRESET0_ipd, RXRESET1_ipd, RXSLIDE0_ipd, RXSLIDE1_ipd, RXUSRCLK0_ipd, RXUSRCLK1_ipd, RXUSRCLK20_ipd, RXUSRCLK21_ipd, TXBUFDIFFCTRL0_ipd, TXBUFDIFFCTRL1_ipd, TXBYPASS8B10B0_ipd, TXBYPASS8B10B1_ipd, TXCHARDISPMODE0_ipd, TXCHARDISPMODE1_ipd, TXCHARDISPVAL0_ipd, TXCHARDISPVAL1_ipd, TXCHARISK0_ipd, TXCHARISK1_ipd, TXCOMSTART0_ipd, TXCOMSTART1_ipd, TXCOMTYPE0_ipd, TXCOMTYPE1_ipd, TXDATA0_ipd, TXDATA1_ipd, TXDATAWIDTH0_ipd, TXDATAWIDTH1_ipd, TXDETECTRX0_ipd, TXDETECTRX1_ipd, TXDIFFCTRL0_ipd, TXDIFFCTRL1_ipd, TXELECIDLE0_ipd, TXELECIDLE1_ipd, TXENC8B10BUSE0_ipd, TXENC8B10BUSE1_ipd, TXENPMAPHASEALIGN_ipd, TXENPRBSTST0_ipd, TXENPRBSTST1_ipd, TXINHIBIT0_ipd, TXINHIBIT1_ipd, TXPMASETPHASE_ipd, TXPOLARITY0_ipd, TXPOLARITY1_ipd, TXPOWERDOWN0_ipd, TXPOWERDOWN1_ipd, TXPREEMPHASIS0_ipd, TXPREEMPHASIS1_ipd, TXRESET0_ipd, TXRESET1_ipd, TXUSRCLK0_ipd, TXUSRCLK1_ipd, TXUSRCLK20_ipd, TXUSRCLK21_ipd; end process TIMING; PHYSTATUS0 <= PHYSTATUS0_out; PHYSTATUS1 <= PHYSTATUS1_out; PLLLKDET <= PLLLKDET_out; RESETDONE0 <= RESETDONE0_out; RESETDONE1 <= RESETDONE1_out; RXELECIDLE0 <= RXELECIDLE0_out; RXELECIDLE1 <= RXELECIDLE1_out; RXRECCLK0 <= RXRECCLK0_out; RXRECCLK1 <= RXRECCLK1_out; TXN0 <= TXN0_out; TXN1 <= TXN1_out; TXOUTCLK0 <= TXOUTCLK0_out; TXOUTCLK1 <= TXOUTCLK1_out; TXP0 <= TXP0_out; TXP1 <= TXP1_out; end GTP_DUAL_V; ------------------------------------------------------------------------------- -- Copyright (c) 1995/2006 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / PCI Express -- /___/ /\ Filename : pcie_ep.vhd -- \ \ / \ Timestamp : Thu Dec 8 2005 -- \___\/\___\ -- -- Revision: -- 08/14/06 - CR#421379 - Initial version. -- 08/31/06 - BVT#1001 - Added PCIE_INTERNAL_1_1 component -- 08/13/06 - CR#423912 - Added zero vectors (std_logic_vector) -- 10/16/06 - CR#427095 - Modified generic map SWIFT instantiation to match spreadsheets -- 12/05/06 - CR#420518 - Added input pin LLKRXDSTCONTREQN -- 12/05/06 - CR#420518 - Added input pin LLKRXDSTCONTREQN -- 03/13/07 - CR#435993 - Add LLKTXCONFIGREADYN -- End Revision ----- CELL PCIE_EP ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; library secureip; use secureip.all; entity PCIE_EP is generic ( ACTIVELANESIN : bit_vector := X"01"; AERBASEPTR : bit_vector := X"110"; AERCAPABILITYNEXTPTR : bit_vector := X"138"; BAR0ADDRWIDTH : integer := 0; BAR0EXIST : boolean := TRUE; BAR0IOMEMN : integer := 0; BAR0MASKWIDTH : bit_vector := X"14"; BAR0PREFETCHABLE : boolean := TRUE; BAR1ADDRWIDTH : integer := 0; BAR1EXIST : boolean := FALSE; BAR1IOMEMN : integer := 0; BAR1MASKWIDTH : bit_vector := X"00"; BAR1PREFETCHABLE : boolean := FALSE; BAR2ADDRWIDTH : integer := 0; BAR2EXIST : boolean := FALSE; BAR2IOMEMN : integer := 0; BAR2MASKWIDTH : bit_vector := X"00"; BAR2PREFETCHABLE : boolean := FALSE; BAR3ADDRWIDTH : integer := 0; BAR3EXIST : boolean := FALSE; BAR3IOMEMN : integer := 0; BAR3MASKWIDTH : bit_vector := X"00"; BAR3PREFETCHABLE : boolean := FALSE; BAR4ADDRWIDTH : integer := 0; BAR4EXIST : boolean := FALSE; BAR4IOMEMN : integer := 0; BAR4MASKWIDTH : bit_vector := X"00"; BAR4PREFETCHABLE : boolean := FALSE; BAR5EXIST : boolean := FALSE; BAR5IOMEMN : integer := 0; BAR5MASKWIDTH : bit_vector := X"00"; BAR5PREFETCHABLE : boolean := FALSE; CAPABILITIESPOINTER : bit_vector := X"40"; CARDBUSCISPOINTER : bit_vector := X"00000000"; CLASSCODE : bit_vector := X"058000"; CLKDIVIDED : boolean := FALSE; DEVICECAPABILITYENDPOINTL0SLATENCY : bit_vector := X"0"; DEVICECAPABILITYENDPOINTL1LATENCY : bit_vector := X"0"; DEVICEID : bit_vector := X"5050"; DEVICESERIALNUMBER : bit_vector := X"E000000001000A35"; DSNBASEPTR : bit_vector := X"148"; DSNCAPABILITYNEXTPTR : bit_vector := X"154"; INFINITECOMPLETIONS : boolean := TRUE; INTERRUPTPIN : bit_vector := X"00"; L0SEXITLATENCY : integer := 7; L0SEXITLATENCYCOMCLK : integer := 7; L1EXITLATENCY : integer := 7; L1EXITLATENCYCOMCLK : integer := 7; LINKCAPABILITYASPMSUPPORT : bit_vector := X"1"; LINKCAPABILITYMAXLINKWIDTH : bit_vector := X"01"; LINKSTATUSSLOTCLOCKCONFIG : boolean := FALSE; LOWPRIORITYVCCOUNT : integer := 0; MSIBASEPTR : bit_vector := X"048"; MSICAPABILITYMULTIMSGCAP : bit_vector := X"0"; MSICAPABILITYNEXTPTR : bit_vector := X"60"; PBBASEPTR : bit_vector := X"138"; PBCAPABILITYDW0BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW0DATASCALE : bit_vector := X"0"; PBCAPABILITYDW0PMSTATE : bit_vector := X"0"; PBCAPABILITYDW0PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW0POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW0TYPE : bit_vector := X"0"; PBCAPABILITYDW1BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW1DATASCALE : bit_vector := X"0"; PBCAPABILITYDW1PMSTATE : bit_vector := X"0"; PBCAPABILITYDW1PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW1POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW1TYPE : bit_vector := X"0"; PBCAPABILITYDW2BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW2DATASCALE : bit_vector := X"0"; PBCAPABILITYDW2PMSTATE : bit_vector := X"0"; PBCAPABILITYDW2PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW2POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW2TYPE : bit_vector := X"0"; PBCAPABILITYDW3BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW3DATASCALE : bit_vector := X"0"; PBCAPABILITYDW3PMSTATE : bit_vector := X"0"; PBCAPABILITYDW3PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW3POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW3TYPE : bit_vector := X"0"; PBCAPABILITYNEXTPTR : bit_vector := X"148"; PBCAPABILITYSYSTEMALLOCATED : boolean := FALSE; PCIECAPABILITYNEXTPTR : bit_vector := X"00"; PMBASEPTR : bit_vector := X"040"; PMCAPABILITYAUXCURRENT : bit_vector := X"0"; PMCAPABILITYD1SUPPORT : boolean := FALSE; PMCAPABILITYD2SUPPORT : boolean := FALSE; PMCAPABILITYDSI : boolean := TRUE; PMCAPABILITYNEXTPTR : bit_vector := X"60"; PMCAPABILITYPMESUPPORT : bit_vector := X"00"; PMDATA0 : bit_vector := X"00"; PMDATA1 : bit_vector := X"00"; PMDATA2 : bit_vector := X"00"; PMDATA3 : bit_vector := X"00"; PMDATA4 : bit_vector := X"00"; PMDATA5 : bit_vector := X"00"; PMDATA6 : bit_vector := X"00"; PMDATA7 : bit_vector := X"00"; PMDATASCALE0 : integer := 0; PMDATASCALE1 : integer := 0; PMDATASCALE2 : integer := 0; PMDATASCALE3 : integer := 0; PMDATASCALE4 : integer := 0; PMDATASCALE5 : integer := 0; PMDATASCALE6 : integer := 0; PMDATASCALE7 : integer := 0; PORTVCCAPABILITYEXTENDEDVCCOUNT : bit_vector := X"0"; PORTVCCAPABILITYVCARBCAP : bit_vector := X"00"; PORTVCCAPABILITYVCARBTABLEOFFSET : bit_vector := X"00"; RESETMODE : boolean := FALSE; RETRYRAMREADLATENCY : integer := 3; RETRYRAMSIZE : bit_vector := X"009"; RETRYRAMWRITELATENCY : integer := 1; REVISIONID : bit_vector := X"00"; SUBSYSTEMID : bit_vector := X"5050"; SUBSYSTEMVENDORID : bit_vector := X"10EE"; TLRAMREADLATENCY : integer := 3; TLRAMWRITELATENCY : integer := 1; TXTSNFTS : integer := 255; TXTSNFTSCOMCLK : integer := 255; VC0RXFIFOBASEC : bit_vector := X"0098"; VC0RXFIFOBASENP : bit_vector := X"0080"; VC0RXFIFOBASEP : bit_vector := X"0000"; VC0RXFIFOLIMITC : bit_vector := X"0117"; VC0RXFIFOLIMITNP : bit_vector := X"0097"; VC0RXFIFOLIMITP : bit_vector := X"007f"; VC0TOTALCREDITSCD : bit_vector := X"000"; VC0TOTALCREDITSCH : bit_vector := X"00"; VC0TOTALCREDITSNPH : bit_vector := X"08"; VC0TOTALCREDITSPD : bit_vector := X"034"; VC0TOTALCREDITSPH : bit_vector := X"08"; VC0TXFIFOBASEC : bit_vector := X"0098"; VC0TXFIFOBASENP : bit_vector := X"0080"; VC0TXFIFOBASEP : bit_vector := X"0000"; VC0TXFIFOLIMITC : bit_vector := X"0117"; VC0TXFIFOLIMITNP : bit_vector := X"0097"; VC0TXFIFOLIMITP : bit_vector := X"007f"; VC1RXFIFOBASEC : bit_vector := X"0118"; VC1RXFIFOBASENP : bit_vector := X"0118"; VC1RXFIFOBASEP : bit_vector := X"0118"; VC1RXFIFOLIMITC : bit_vector := X"0118"; VC1RXFIFOLIMITNP : bit_vector := X"0118"; VC1RXFIFOLIMITP : bit_vector := X"0118"; VC1TOTALCREDITSCD : bit_vector := X"000"; VC1TOTALCREDITSCH : bit_vector := X"00"; VC1TOTALCREDITSNPH : bit_vector := X"00"; VC1TOTALCREDITSPD : bit_vector := X"000"; VC1TOTALCREDITSPH : bit_vector := X"00"; VC1TXFIFOBASEC : bit_vector := X"0118"; VC1TXFIFOBASENP : bit_vector := X"0118"; VC1TXFIFOBASEP : bit_vector := X"0118"; VC1TXFIFOLIMITC : bit_vector := X"0118"; VC1TXFIFOLIMITNP : bit_vector := X"0118"; VC1TXFIFOLIMITP : bit_vector := X"0118"; VCBASEPTR : bit_vector := X"154"; VCCAPABILITYNEXTPTR : bit_vector := X"000"; VENDORID : bit_vector := X"10EE"; XPBASEPTR : bit_vector := X"60"; XPDEVICEPORTTYPE : bit_vector := X"0"; XPMAXPAYLOAD : integer := 0 ); port ( BUSMASTERENABLE : out std_ulogic; CRMDOHOTRESETN : out std_ulogic; CRMPWRSOFTRESETN : out std_ulogic; DLLTXPMDLLPOUTSTANDING : out std_ulogic; INTERRUPTDISABLE : out std_ulogic; IOSPACEENABLE : out std_ulogic; L0CFGLOOPBACKACK : out std_ulogic; L0COMPLETERID : out std_logic_vector(12 downto 0); L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); L0DLLRXACKOUTSTANDING : out std_ulogic; L0DLLTXNONFCOUTSTANDING : out std_ulogic; L0DLLTXOUTSTANDING : out std_ulogic; L0DLLVCSTATUS : out std_logic_vector(7 downto 0); L0DLUPDOWN : out std_logic_vector(7 downto 0); L0FIRSTCFGWRITEOCCURRED : out std_ulogic; L0LTSSMSTATE : out std_logic_vector(3 downto 0); L0MACENTEREDL0 : out std_ulogic; L0MACLINKTRAINING : out std_ulogic; L0MACLINKUP : out std_ulogic; L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); L0MACNEWSTATEACK : out std_ulogic; L0MACRXL0SSTATE : out std_ulogic; L0MSIENABLE0 : out std_ulogic; L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); L0PMEACK : out std_ulogic; L0PMEEN : out std_ulogic; L0PMEREQOUT : out std_ulogic; L0PWRL1STATE : out std_ulogic; L0PWRL23READYSTATE : out std_ulogic; L0PWRSTATE0 : out std_logic_vector(1 downto 0); L0PWRTURNOFFREQ : out std_ulogic; L0PWRTXL0SSTATE : out std_ulogic; L0RXDLLPM : out std_ulogic; L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); L0RXMACLINKERROR : out std_logic_vector(1 downto 0); L0STATSCFGOTHERRECEIVED : out std_ulogic; L0STATSCFGOTHERTRANSMITTED : out std_ulogic; L0STATSCFGRECEIVED : out std_ulogic; L0STATSCFGTRANSMITTED : out std_ulogic; L0STATSDLLPRECEIVED : out std_ulogic; L0STATSDLLPTRANSMITTED : out std_ulogic; L0STATSOSRECEIVED : out std_ulogic; L0STATSOSTRANSMITTED : out std_ulogic; L0STATSTLPRECEIVED : out std_ulogic; L0STATSTLPTRANSMITTED : out std_ulogic; L0UNLOCKRECEIVED : out std_ulogic; LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXDATA : out std_logic_vector(63 downto 0); LLKRXEOFN : out std_ulogic; LLKRXEOPN : out std_ulogic; LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); LLKRXSOFN : out std_ulogic; LLKRXSOPN : out std_ulogic; LLKRXSRCLASTREQN : out std_ulogic; LLKRXSRCRDYN : out std_ulogic; LLKRXVALIDN : out std_logic_vector(1 downto 0); LLKTCSTATUS : out std_logic_vector(7 downto 0); LLKTXCHANSPACE : out std_logic_vector(9 downto 0); LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); LLKTXCONFIGREADYN : out std_ulogic; LLKTXDSTRDYN : out std_ulogic; MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); MEMSPACEENABLE : out std_ulogic; MGMTPSO : out std_logic_vector(16 downto 0); MGMTRDATA : out std_logic_vector(31 downto 0); MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); MIMDLLBRADD : out std_logic_vector(11 downto 0); MIMDLLBREN : out std_ulogic; MIMDLLBWADD : out std_logic_vector(11 downto 0); MIMDLLBWDATA : out std_logic_vector(63 downto 0); MIMDLLBWEN : out std_ulogic; MIMRXBRADD : out std_logic_vector(12 downto 0); MIMRXBREN : out std_ulogic; MIMRXBWADD : out std_logic_vector(12 downto 0); MIMRXBWDATA : out std_logic_vector(63 downto 0); MIMRXBWEN : out std_ulogic; MIMTXBRADD : out std_logic_vector(12 downto 0); MIMTXBREN : out std_ulogic; MIMTXBWADD : out std_logic_vector(12 downto 0); MIMTXBWDATA : out std_logic_vector(63 downto 0); MIMTXBWEN : out std_ulogic; PARITYERRORRESPONSE : out std_ulogic; PIPEDESKEWLANESL0 : out std_ulogic; PIPEDESKEWLANESL1 : out std_ulogic; PIPEDESKEWLANESL2 : out std_ulogic; PIPEDESKEWLANESL3 : out std_ulogic; PIPEDESKEWLANESL4 : out std_ulogic; PIPEDESKEWLANESL5 : out std_ulogic; PIPEDESKEWLANESL6 : out std_ulogic; PIPEDESKEWLANESL7 : out std_ulogic; PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); PIPERESETL0 : out std_ulogic; PIPERESETL1 : out std_ulogic; PIPERESETL2 : out std_ulogic; PIPERESETL3 : out std_ulogic; PIPERESETL4 : out std_ulogic; PIPERESETL5 : out std_ulogic; PIPERESETL6 : out std_ulogic; PIPERESETL7 : out std_ulogic; PIPERXPOLARITYL0 : out std_ulogic; PIPERXPOLARITYL1 : out std_ulogic; PIPERXPOLARITYL2 : out std_ulogic; PIPERXPOLARITYL3 : out std_ulogic; PIPERXPOLARITYL4 : out std_ulogic; PIPERXPOLARITYL5 : out std_ulogic; PIPERXPOLARITYL6 : out std_ulogic; PIPERXPOLARITYL7 : out std_ulogic; PIPETXCOMPLIANCEL0 : out std_ulogic; PIPETXCOMPLIANCEL1 : out std_ulogic; PIPETXCOMPLIANCEL2 : out std_ulogic; PIPETXCOMPLIANCEL3 : out std_ulogic; PIPETXCOMPLIANCEL4 : out std_ulogic; PIPETXCOMPLIANCEL5 : out std_ulogic; PIPETXCOMPLIANCEL6 : out std_ulogic; PIPETXCOMPLIANCEL7 : out std_ulogic; PIPETXDATAKL0 : out std_ulogic; PIPETXDATAKL1 : out std_ulogic; PIPETXDATAKL2 : out std_ulogic; PIPETXDATAKL3 : out std_ulogic; PIPETXDATAKL4 : out std_ulogic; PIPETXDATAKL5 : out std_ulogic; PIPETXDATAKL6 : out std_ulogic; PIPETXDATAKL7 : out std_ulogic; PIPETXDATAL0 : out std_logic_vector(7 downto 0); PIPETXDATAL1 : out std_logic_vector(7 downto 0); PIPETXDATAL2 : out std_logic_vector(7 downto 0); PIPETXDATAL3 : out std_logic_vector(7 downto 0); PIPETXDATAL4 : out std_logic_vector(7 downto 0); PIPETXDATAL5 : out std_logic_vector(7 downto 0); PIPETXDATAL6 : out std_logic_vector(7 downto 0); PIPETXDATAL7 : out std_logic_vector(7 downto 0); PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; PIPETXELECIDLEL0 : out std_ulogic; PIPETXELECIDLEL1 : out std_ulogic; PIPETXELECIDLEL2 : out std_ulogic; PIPETXELECIDLEL3 : out std_ulogic; PIPETXELECIDLEL4 : out std_ulogic; PIPETXELECIDLEL5 : out std_ulogic; PIPETXELECIDLEL6 : out std_ulogic; PIPETXELECIDLEL7 : out std_ulogic; SERRENABLE : out std_ulogic; URREPORTINGENABLE : out std_ulogic; AUXPOWER : in std_ulogic; COMPLIANCEAVOID : in std_ulogic; CRMCORECLK : in std_ulogic; CRMCORECLKDLO : in std_ulogic; CRMCORECLKRXO : in std_ulogic; CRMCORECLKTXO : in std_ulogic; CRMLINKRSTN : in std_ulogic; CRMMACRSTN : in std_ulogic; CRMMGMTRSTN : in std_ulogic; CRMNVRSTN : in std_ulogic; CRMURSTN : in std_ulogic; CRMUSERCFGRSTN : in std_ulogic; CRMUSERCLK : in std_ulogic; CRMUSERCLKRXO : in std_ulogic; CRMUSERCLKTXO : in std_ulogic; L0CFGDISABLESCRAMBLE : in std_ulogic; L0CFGLOOPBACKMASTER : in std_ulogic; L0LEGACYINTFUNCT0 : in std_ulogic; L0MSIREQUEST0 : in std_logic_vector(3 downto 0); L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); L0PMEREQIN : in std_ulogic; L0SETCOMPLETERABORTERROR : in std_ulogic; L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; L0SETDETECTEDCORRERROR : in std_ulogic; L0SETDETECTEDFATALERROR : in std_ulogic; L0SETDETECTEDNONFATALERROR : in std_ulogic; L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; L0SETUSERDETECTEDPARITYERROR : in std_ulogic; L0SETUSERMASTERDATAPARITY : in std_ulogic; L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; L0SETUSERSYSTEMERROR : in std_ulogic; L0TRANSACTIONSPENDING : in std_ulogic; LLKRXCHFIFO : in std_logic_vector(1 downto 0); LLKRXCHTC : in std_logic_vector(2 downto 0); LLKRXDSTCONTREQN : in std_ulogic; LLKRXDSTREQN : in std_ulogic; LLKTXCHFIFO : in std_logic_vector(1 downto 0); LLKTXCHTC : in std_logic_vector(2 downto 0); LLKTXDATA : in std_logic_vector(63 downto 0); LLKTXENABLEN : in std_logic_vector(1 downto 0); LLKTXEOFN : in std_ulogic; LLKTXEOPN : in std_ulogic; LLKTXSOFN : in std_ulogic; LLKTXSOPN : in std_ulogic; LLKTXSRCDSCN : in std_ulogic; LLKTXSRCRDYN : in std_ulogic; MGMTADDR : in std_logic_vector(10 downto 0); MGMTBWREN : in std_logic_vector(3 downto 0); MGMTRDEN : in std_ulogic; MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); MGMTWDATA : in std_logic_vector(31 downto 0); MGMTWREN : in std_ulogic; MIMDLLBRDATA : in std_logic_vector(63 downto 0); MIMRXBRDATA : in std_logic_vector(63 downto 0); MIMTXBRDATA : in std_logic_vector(63 downto 0); PIPEPHYSTATUSL0 : in std_ulogic; PIPEPHYSTATUSL1 : in std_ulogic; PIPEPHYSTATUSL2 : in std_ulogic; PIPEPHYSTATUSL3 : in std_ulogic; PIPEPHYSTATUSL4 : in std_ulogic; PIPEPHYSTATUSL5 : in std_ulogic; PIPEPHYSTATUSL6 : in std_ulogic; PIPEPHYSTATUSL7 : in std_ulogic; PIPERXCHANISALIGNEDL0 : in std_ulogic; PIPERXCHANISALIGNEDL1 : in std_ulogic; PIPERXCHANISALIGNEDL2 : in std_ulogic; PIPERXCHANISALIGNEDL3 : in std_ulogic; PIPERXCHANISALIGNEDL4 : in std_ulogic; PIPERXCHANISALIGNEDL5 : in std_ulogic; PIPERXCHANISALIGNEDL6 : in std_ulogic; PIPERXCHANISALIGNEDL7 : in std_ulogic; PIPERXDATAKL0 : in std_ulogic; PIPERXDATAKL1 : in std_ulogic; PIPERXDATAKL2 : in std_ulogic; PIPERXDATAKL3 : in std_ulogic; PIPERXDATAKL4 : in std_ulogic; PIPERXDATAKL5 : in std_ulogic; PIPERXDATAKL6 : in std_ulogic; PIPERXDATAKL7 : in std_ulogic; PIPERXDATAL0 : in std_logic_vector(7 downto 0); PIPERXDATAL1 : in std_logic_vector(7 downto 0); PIPERXDATAL2 : in std_logic_vector(7 downto 0); PIPERXDATAL3 : in std_logic_vector(7 downto 0); PIPERXDATAL4 : in std_logic_vector(7 downto 0); PIPERXDATAL5 : in std_logic_vector(7 downto 0); PIPERXDATAL6 : in std_logic_vector(7 downto 0); PIPERXDATAL7 : in std_logic_vector(7 downto 0); PIPERXELECIDLEL0 : in std_ulogic; PIPERXELECIDLEL1 : in std_ulogic; PIPERXELECIDLEL2 : in std_ulogic; PIPERXELECIDLEL3 : in std_ulogic; PIPERXELECIDLEL4 : in std_ulogic; PIPERXELECIDLEL5 : in std_ulogic; PIPERXELECIDLEL6 : in std_ulogic; PIPERXELECIDLEL7 : in std_ulogic; PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); PIPERXVALIDL0 : in std_ulogic; PIPERXVALIDL1 : in std_ulogic; PIPERXVALIDL2 : in std_ulogic; PIPERXVALIDL3 : in std_ulogic; PIPERXVALIDL4 : in std_ulogic; PIPERXVALIDL5 : in std_ulogic; PIPERXVALIDL6 : in std_ulogic; PIPERXVALIDL7 : in std_ulogic ); end PCIE_EP; architecture PCIE_EP_V of PCIE_EP is component PCIE_INTERNAL_1_1 generic ( ACTIVELANESIN : bit_vector := X"01"; AERBASEPTR : bit_vector := X"110"; AERCAPABILITYECRCCHECKCAPABLE : boolean := FALSE; AERCAPABILITYECRCGENCAPABLE : boolean := FALSE; AERCAPABILITYNEXTPTR : bit_vector := X"138"; BAR0ADDRWIDTH : integer := 0; BAR0EXIST : boolean := TRUE; BAR0IOMEMN : integer := 0; BAR0MASKWIDTH : bit_vector := X"14"; BAR0PREFETCHABLE : boolean := TRUE; BAR1ADDRWIDTH : integer := 0; BAR1EXIST : boolean := FALSE; BAR1IOMEMN : integer := 0; BAR1MASKWIDTH : bit_vector := X"00"; BAR1PREFETCHABLE : boolean := FALSE; BAR2ADDRWIDTH : integer := 0; BAR2EXIST : boolean := FALSE; BAR2IOMEMN : integer := 0; BAR2MASKWIDTH : bit_vector := X"00"; BAR2PREFETCHABLE : boolean := FALSE; BAR3ADDRWIDTH : integer := 0; BAR3EXIST : boolean := FALSE; BAR3IOMEMN : integer := 0; BAR3MASKWIDTH : bit_vector := X"00"; BAR3PREFETCHABLE : boolean := FALSE; BAR4ADDRWIDTH : integer := 0; BAR4EXIST : boolean := FALSE; BAR4IOMEMN : integer := 0; BAR4MASKWIDTH : bit_vector := X"00"; BAR4PREFETCHABLE : boolean := FALSE; BAR5EXIST : boolean := FALSE; BAR5IOMEMN : integer := 0; BAR5MASKWIDTH : bit_vector := X"00"; BAR5PREFETCHABLE : boolean := FALSE; CAPABILITIESPOINTER : bit_vector := X"40"; CARDBUSCISPOINTER : bit_vector := X"00000000"; CLASSCODE : bit_vector := X"058000"; CLKDIVIDED : boolean := FALSE; CONFIGROUTING : bit_vector := X"1"; DEVICECAPABILITYENDPOINTL0SLATENCY : bit_vector := X"0"; DEVICECAPABILITYENDPOINTL1LATENCY : bit_vector := X"0"; DEVICEID : bit_vector := X"5050"; DEVICESERIALNUMBER : bit_vector := X"E000000001000A35"; DSNBASEPTR : bit_vector := X"148"; DSNCAPABILITYNEXTPTR : bit_vector := X"154"; DUALCOREENABLE : boolean := FALSE; DUALCORESLAVE : boolean := FALSE; DUALROLECFGCNTRLROOTEPN : integer := 0; EXTCFGCAPPTR : bit_vector := X"00"; EXTCFGXPCAPPTR : bit_vector := X"000"; HEADERTYPE : bit_vector := X"00"; INFINITECOMPLETIONS : boolean := TRUE; INTERRUPTPIN : bit_vector := X"00"; ISSWITCH : boolean := FALSE; L0SEXITLATENCY : integer := 7; L0SEXITLATENCYCOMCLK : integer := 7; L1EXITLATENCY : integer := 7; L1EXITLATENCYCOMCLK : integer := 7; LINKCAPABILITYASPMSUPPORT : bit_vector := X"1"; LINKCAPABILITYMAXLINKWIDTH : bit_vector := X"01"; LINKSTATUSSLOTCLOCKCONFIG : boolean := FALSE; LLKBYPASS : boolean := FALSE; LOWPRIORITYVCCOUNT : integer := 0; MSIBASEPTR : bit_vector := X"048"; MSICAPABILITYMULTIMSGCAP : bit_vector := X"0"; MSICAPABILITYNEXTPTR : bit_vector := X"60"; PBBASEPTR : bit_vector := X"138"; PBCAPABILITYDW0BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW0DATASCALE : bit_vector := X"0"; PBCAPABILITYDW0PMSTATE : bit_vector := X"0"; PBCAPABILITYDW0PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW0POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW0TYPE : bit_vector := X"0"; PBCAPABILITYDW1BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW1DATASCALE : bit_vector := X"0"; PBCAPABILITYDW1PMSTATE : bit_vector := X"0"; PBCAPABILITYDW1PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW1POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW1TYPE : bit_vector := X"0"; PBCAPABILITYDW2BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW2DATASCALE : bit_vector := X"0"; PBCAPABILITYDW2PMSTATE : bit_vector := X"0"; PBCAPABILITYDW2PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW2POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW2TYPE : bit_vector := X"0"; PBCAPABILITYDW3BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW3DATASCALE : bit_vector := X"0"; PBCAPABILITYDW3PMSTATE : bit_vector := X"0"; PBCAPABILITYDW3PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW3POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW3TYPE : bit_vector := X"0"; PBCAPABILITYNEXTPTR : bit_vector := X"148"; PBCAPABILITYSYSTEMALLOCATED : boolean := FALSE; PCIECAPABILITYINTMSGNUM : bit_vector := X"00"; PCIECAPABILITYNEXTPTR : bit_vector := X"00"; PCIECAPABILITYSLOTIMPL : boolean := FALSE; PCIEREVISION : integer := 1; PMBASEPTR : bit_vector := X"040"; PMCAPABILITYAUXCURRENT : bit_vector := X"0"; PMCAPABILITYD1SUPPORT : boolean := FALSE; PMCAPABILITYD2SUPPORT : boolean := FALSE; PMCAPABILITYDSI : boolean := TRUE; PMCAPABILITYNEXTPTR : bit_vector := X"60"; PMCAPABILITYPMESUPPORT : bit_vector := X"00"; PMDATA0 : bit_vector := X"00"; PMDATA1 : bit_vector := X"00"; PMDATA2 : bit_vector := X"00"; PMDATA3 : bit_vector := X"00"; PMDATA4 : bit_vector := X"00"; PMDATA5 : bit_vector := X"00"; PMDATA6 : bit_vector := X"00"; PMDATA7 : bit_vector := X"00"; PMDATA8 : bit_vector := X"00"; PMDATASCALE0 : integer := 0; PMDATASCALE1 : integer := 0; PMDATASCALE2 : integer := 0; PMDATASCALE3 : integer := 0; PMDATASCALE4 : integer := 0; PMDATASCALE5 : integer := 0; PMDATASCALE6 : integer := 0; PMDATASCALE7 : integer := 0; PMDATASCALE8 : integer := 0; PMSTATUSCONTROLDATASCALE : bit_vector := X"0"; PORTVCCAPABILITYEXTENDEDVCCOUNT : bit_vector := X"0"; PORTVCCAPABILITYVCARBCAP : bit_vector := X"00"; PORTVCCAPABILITYVCARBTABLEOFFSET : bit_vector := X"00"; RAMSHARETXRX : boolean := FALSE; RESETMODE : boolean := FALSE; RETRYRAMREADLATENCY : integer := 3; RETRYRAMSIZE : bit_vector := X"009"; RETRYRAMWIDTH : integer := 0; RETRYRAMWRITELATENCY : integer := 1; RETRYREADADDRPIPE : boolean := FALSE; RETRYREADDATAPIPE : boolean := FALSE; RETRYWRITEPIPE : boolean := FALSE; REVISIONID : bit_vector := X"00"; RXREADADDRPIPE : boolean := FALSE; RXREADDATAPIPE : boolean := FALSE; RXWRITEPIPE : boolean := FALSE; SELECTASMODE : boolean := FALSE; SELECTDLLIF : boolean := FALSE; SLOTCAPABILITYATTBUTTONPRESENT : boolean := FALSE; SLOTCAPABILITYATTINDICATORPRESENT : boolean := FALSE; SLOTCAPABILITYHOTPLUGCAPABLE : boolean := FALSE; SLOTCAPABILITYHOTPLUGSURPRISE : boolean := FALSE; SLOTCAPABILITYMSLSENSORPRESENT : boolean := FALSE; SLOTCAPABILITYPHYSICALSLOTNUM : bit_vector := X"0000"; SLOTCAPABILITYPOWERCONTROLLERPRESENT : boolean := FALSE; SLOTCAPABILITYPOWERINDICATORPRESENT : boolean := FALSE; SLOTCAPABILITYSLOTPOWERLIMITSCALE : bit_vector := X"0"; SLOTCAPABILITYSLOTPOWERLIMITVALUE : bit_vector := X"00"; SLOTIMPLEMENTED : boolean := FALSE; SUBSYSTEMID : bit_vector := X"5050"; SUBSYSTEMVENDORID : bit_vector := X"10EE"; TLRAMREADLATENCY : integer := 3; TLRAMWIDTH : integer := 0; TLRAMWRITELATENCY : integer := 1; TXREADADDRPIPE : boolean := FALSE; TXREADDATAPIPE : boolean := FALSE; TXTSNFTS : integer := 255; TXTSNFTSCOMCLK : integer := 255; TXWRITEPIPE : boolean := FALSE; UPSTREAMFACING : boolean := TRUE; VC0RXFIFOBASEC : bit_vector := X"0098"; VC0RXFIFOBASENP : bit_vector := X"0080"; VC0RXFIFOBASEP : bit_vector := X"0000"; VC0RXFIFOLIMITC : bit_vector := X"0117"; VC0RXFIFOLIMITNP : bit_vector := X"0097"; VC0RXFIFOLIMITP : bit_vector := X"007f"; VC0TOTALCREDITSCD : bit_vector := X"000"; VC0TOTALCREDITSCH : bit_vector := X"00"; VC0TOTALCREDITSNPH : bit_vector := X"08"; VC0TOTALCREDITSPD : bit_vector := X"034"; VC0TOTALCREDITSPH : bit_vector := X"08"; VC0TXFIFOBASEC : bit_vector := X"0098"; VC0TXFIFOBASENP : bit_vector := X"0080"; VC0TXFIFOBASEP : bit_vector := X"0000"; VC0TXFIFOLIMITC : bit_vector := X"0117"; VC0TXFIFOLIMITNP : bit_vector := X"0097"; VC0TXFIFOLIMITP : bit_vector := X"007f"; VC1RXFIFOBASEC : bit_vector := X"0118"; VC1RXFIFOBASENP : bit_vector := X"0118"; VC1RXFIFOBASEP : bit_vector := X"0118"; VC1RXFIFOLIMITC : bit_vector := X"0118"; VC1RXFIFOLIMITNP : bit_vector := X"0118"; VC1RXFIFOLIMITP : bit_vector := X"0118"; VC1TOTALCREDITSCD : bit_vector := X"000"; VC1TOTALCREDITSCH : bit_vector := X"00"; VC1TOTALCREDITSNPH : bit_vector := X"00"; VC1TOTALCREDITSPD : bit_vector := X"000"; VC1TOTALCREDITSPH : bit_vector := X"00"; VC1TXFIFOBASEC : bit_vector := X"0118"; VC1TXFIFOBASENP : bit_vector := X"0118"; VC1TXFIFOBASEP : bit_vector := X"0118"; VC1TXFIFOLIMITC : bit_vector := X"0118"; VC1TXFIFOLIMITNP : bit_vector := X"0118"; VC1TXFIFOLIMITP : bit_vector := X"0118"; VCBASEPTR : bit_vector := X"154"; VCCAPABILITYNEXTPTR : bit_vector := X"000"; VENDORID : bit_vector := X"10EE"; XLINKSUPPORTED : boolean := FALSE; XPBASEPTR : bit_vector := X"60"; XPDEVICEPORTTYPE : bit_vector := X"0"; XPMAXPAYLOAD : integer := 0; XPRCBCONTROL : integer := 0 ); port ( BUSMASTERENABLE : out std_ulogic; CRMDOHOTRESETN : out std_ulogic; CRMPWRSOFTRESETN : out std_ulogic; CRMRXHOTRESETN : out std_ulogic; DLLTXPMDLLPOUTSTANDING : out std_ulogic; INTERRUPTDISABLE : out std_ulogic; IOSPACEENABLE : out std_ulogic; L0ASAUTONOMOUSINITCOMPLETED : out std_ulogic; L0ATTENTIONINDICATORCONTROL : out std_logic_vector(1 downto 0); L0CFGLOOPBACKACK : out std_ulogic; L0COMPLETERID : out std_logic_vector(12 downto 0); L0CORRERRMSGRCVD : out std_ulogic; L0DLLASRXSTATE : out std_logic_vector(1 downto 0); L0DLLASTXSTATE : out std_ulogic; L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); L0DLLRXACKOUTSTANDING : out std_ulogic; L0DLLTXNONFCOUTSTANDING : out std_ulogic; L0DLLTXOUTSTANDING : out std_ulogic; L0DLLVCSTATUS : out std_logic_vector(7 downto 0); L0DLUPDOWN : out std_logic_vector(7 downto 0); L0ERRMSGREQID : out std_logic_vector(15 downto 0); L0FATALERRMSGRCVD : out std_ulogic; L0FIRSTCFGWRITEOCCURRED : out std_ulogic; L0FWDCORRERROUT : out std_ulogic; L0FWDFATALERROUT : out std_ulogic; L0FWDNONFATALERROUT : out std_ulogic; L0LTSSMSTATE : out std_logic_vector(3 downto 0); L0MACENTEREDL0 : out std_ulogic; L0MACLINKTRAINING : out std_ulogic; L0MACLINKUP : out std_ulogic; L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); L0MACNEWSTATEACK : out std_ulogic; L0MACRXL0SSTATE : out std_ulogic; L0MACUPSTREAMDOWNSTREAM : out std_ulogic; L0MCFOUND : out std_logic_vector(2 downto 0); L0MSIENABLE0 : out std_ulogic; L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); L0NONFATALERRMSGRCVD : out std_ulogic; L0PMEACK : out std_ulogic; L0PMEEN : out std_ulogic; L0PMEREQOUT : out std_ulogic; L0POWERCONTROLLERCONTROL : out std_ulogic; L0POWERINDICATORCONTROL : out std_logic_vector(1 downto 0); L0PWRINHIBITTRANSFERS : out std_ulogic; L0PWRL1STATE : out std_ulogic; L0PWRL23READYDEVICE : out std_ulogic; L0PWRL23READYSTATE : out std_ulogic; L0PWRSTATE0 : out std_logic_vector(1 downto 0); L0PWRTURNOFFREQ : out std_ulogic; L0PWRTXL0SSTATE : out std_ulogic; L0RECEIVEDASSERTINTALEGACYINT : out std_ulogic; L0RECEIVEDASSERTINTBLEGACYINT : out std_ulogic; L0RECEIVEDASSERTINTCLEGACYINT : out std_ulogic; L0RECEIVEDASSERTINTDLEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTALEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTBLEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTCLEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTDLEGACYINT : out std_ulogic; L0RXBEACON : out std_ulogic; L0RXDLLFCCMPLMCCRED : out std_logic_vector(23 downto 0); L0RXDLLFCCMPLMCUPDATE : out std_logic_vector(7 downto 0); L0RXDLLFCNPOSTBYPCRED : out std_logic_vector(19 downto 0); L0RXDLLFCNPOSTBYPUPDATE : out std_logic_vector(7 downto 0); L0RXDLLFCPOSTORDCRED : out std_logic_vector(23 downto 0); L0RXDLLFCPOSTORDUPDATE : out std_logic_vector(7 downto 0); L0RXDLLPM : out std_ulogic; L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); L0RXDLLSBFCDATA : out std_logic_vector(18 downto 0); L0RXDLLSBFCUPDATE : out std_ulogic; L0RXDLLTLPECRCOK : out std_ulogic; L0RXDLLTLPEND : out std_logic_vector(1 downto 0); L0RXMACLINKERROR : out std_logic_vector(1 downto 0); L0STATSCFGOTHERRECEIVED : out std_ulogic; L0STATSCFGOTHERTRANSMITTED : out std_ulogic; L0STATSCFGRECEIVED : out std_ulogic; L0STATSCFGTRANSMITTED : out std_ulogic; L0STATSDLLPRECEIVED : out std_ulogic; L0STATSDLLPTRANSMITTED : out std_ulogic; L0STATSOSRECEIVED : out std_ulogic; L0STATSOSTRANSMITTED : out std_ulogic; L0STATSTLPRECEIVED : out std_ulogic; L0STATSTLPTRANSMITTED : out std_ulogic; L0TOGGLEELECTROMECHANICALINTERLOCK : out std_ulogic; L0TRANSFORMEDVC : out std_logic_vector(2 downto 0); L0TXDLLFCCMPLMCUPDATED : out std_logic_vector(7 downto 0); L0TXDLLFCNPOSTBYPUPDATED : out std_logic_vector(7 downto 0); L0TXDLLFCPOSTORDUPDATED : out std_logic_vector(7 downto 0); L0TXDLLPMUPDATED : out std_ulogic; L0TXDLLSBFCUPDATED : out std_ulogic; L0UCBYPFOUND : out std_logic_vector(3 downto 0); L0UCORDFOUND : out std_logic_vector(3 downto 0); L0UNLOCKRECEIVED : out std_ulogic; LLKRX4DWHEADERN : out std_ulogic; LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXCHCOMPLETIONPARTIALN : out std_logic_vector(7 downto 0); LLKRXCHCONFIGAVAILABLEN : out std_ulogic; LLKRXCHCONFIGPARTIALN : out std_ulogic; LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXCHNONPOSTEDPARTIALN : out std_logic_vector(7 downto 0); LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXCHPOSTEDPARTIALN : out std_logic_vector(7 downto 0); LLKRXDATA : out std_logic_vector(63 downto 0); LLKRXECRCBADN : out std_ulogic; LLKRXEOFN : out std_ulogic; LLKRXEOPN : out std_ulogic; LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); LLKRXSOFN : out std_ulogic; LLKRXSOPN : out std_ulogic; LLKRXSRCDSCN : out std_ulogic; LLKRXSRCLASTREQN : out std_ulogic; LLKRXSRCRDYN : out std_ulogic; LLKRXVALIDN : out std_logic_vector(1 downto 0); LLKTCSTATUS : out std_logic_vector(7 downto 0); LLKTXCHANSPACE : out std_logic_vector(9 downto 0); LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); LLKTXCONFIGREADYN : out std_ulogic; LLKTXDSTRDYN : out std_ulogic; MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); MEMSPACEENABLE : out std_ulogic; MGMTPSO : out std_logic_vector(16 downto 0); MGMTRDATA : out std_logic_vector(31 downto 0); MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); MIMDLLBRADD : out std_logic_vector(11 downto 0); MIMDLLBREN : out std_ulogic; MIMDLLBWADD : out std_logic_vector(11 downto 0); MIMDLLBWDATA : out std_logic_vector(63 downto 0); MIMDLLBWEN : out std_ulogic; MIMRXBRADD : out std_logic_vector(12 downto 0); MIMRXBREN : out std_ulogic; MIMRXBWADD : out std_logic_vector(12 downto 0); MIMRXBWDATA : out std_logic_vector(63 downto 0); MIMRXBWEN : out std_ulogic; MIMTXBRADD : out std_logic_vector(12 downto 0); MIMTXBREN : out std_ulogic; MIMTXBWADD : out std_logic_vector(12 downto 0); MIMTXBWDATA : out std_logic_vector(63 downto 0); MIMTXBWEN : out std_ulogic; PARITYERRORRESPONSE : out std_ulogic; PIPEDESKEWLANESL0 : out std_ulogic; PIPEDESKEWLANESL1 : out std_ulogic; PIPEDESKEWLANESL2 : out std_ulogic; PIPEDESKEWLANESL3 : out std_ulogic; PIPEDESKEWLANESL4 : out std_ulogic; PIPEDESKEWLANESL5 : out std_ulogic; PIPEDESKEWLANESL6 : out std_ulogic; PIPEDESKEWLANESL7 : out std_ulogic; PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); PIPERESETL0 : out std_ulogic; PIPERESETL1 : out std_ulogic; PIPERESETL2 : out std_ulogic; PIPERESETL3 : out std_ulogic; PIPERESETL4 : out std_ulogic; PIPERESETL5 : out std_ulogic; PIPERESETL6 : out std_ulogic; PIPERESETL7 : out std_ulogic; PIPERXPOLARITYL0 : out std_ulogic; PIPERXPOLARITYL1 : out std_ulogic; PIPERXPOLARITYL2 : out std_ulogic; PIPERXPOLARITYL3 : out std_ulogic; PIPERXPOLARITYL4 : out std_ulogic; PIPERXPOLARITYL5 : out std_ulogic; PIPERXPOLARITYL6 : out std_ulogic; PIPERXPOLARITYL7 : out std_ulogic; PIPETXCOMPLIANCEL0 : out std_ulogic; PIPETXCOMPLIANCEL1 : out std_ulogic; PIPETXCOMPLIANCEL2 : out std_ulogic; PIPETXCOMPLIANCEL3 : out std_ulogic; PIPETXCOMPLIANCEL4 : out std_ulogic; PIPETXCOMPLIANCEL5 : out std_ulogic; PIPETXCOMPLIANCEL6 : out std_ulogic; PIPETXCOMPLIANCEL7 : out std_ulogic; PIPETXDATAKL0 : out std_ulogic; PIPETXDATAKL1 : out std_ulogic; PIPETXDATAKL2 : out std_ulogic; PIPETXDATAKL3 : out std_ulogic; PIPETXDATAKL4 : out std_ulogic; PIPETXDATAKL5 : out std_ulogic; PIPETXDATAKL6 : out std_ulogic; PIPETXDATAKL7 : out std_ulogic; PIPETXDATAL0 : out std_logic_vector(7 downto 0); PIPETXDATAL1 : out std_logic_vector(7 downto 0); PIPETXDATAL2 : out std_logic_vector(7 downto 0); PIPETXDATAL3 : out std_logic_vector(7 downto 0); PIPETXDATAL4 : out std_logic_vector(7 downto 0); PIPETXDATAL5 : out std_logic_vector(7 downto 0); PIPETXDATAL6 : out std_logic_vector(7 downto 0); PIPETXDATAL7 : out std_logic_vector(7 downto 0); PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; PIPETXELECIDLEL0 : out std_ulogic; PIPETXELECIDLEL1 : out std_ulogic; PIPETXELECIDLEL2 : out std_ulogic; PIPETXELECIDLEL3 : out std_ulogic; PIPETXELECIDLEL4 : out std_ulogic; PIPETXELECIDLEL5 : out std_ulogic; PIPETXELECIDLEL6 : out std_ulogic; PIPETXELECIDLEL7 : out std_ulogic; SERRENABLE : out std_ulogic; URREPORTINGENABLE : out std_ulogic; AUXPOWER : in std_ulogic; CFGNEGOTIATEDLINKWIDTH : in std_logic_vector(5 downto 0); COMPLIANCEAVOID : in std_ulogic; CRMCFGBRIDGEHOTRESET : in std_ulogic; CRMCORECLK : in std_ulogic; CRMCORECLKDLO : in std_ulogic; CRMCORECLKRXO : in std_ulogic; CRMCORECLKTXO : in std_ulogic; CRMLINKRSTN : in std_ulogic; CRMMACRSTN : in std_ulogic; CRMMGMTRSTN : in std_ulogic; CRMNVRSTN : in std_ulogic; CRMTXHOTRESETN : in std_ulogic; CRMURSTN : in std_ulogic; CRMUSERCFGRSTN : in std_ulogic; CRMUSERCLK : in std_ulogic; CRMUSERCLKRXO : in std_ulogic; CRMUSERCLKTXO : in std_ulogic; CROSSLINKSEED : in std_ulogic; L0ACKNAKTIMERADJUSTMENT : in std_logic_vector(11 downto 0); L0ALLDOWNPORTSINL1 : in std_ulogic; L0ALLDOWNRXPORTSINL0S : in std_ulogic; L0ASE : in std_ulogic; L0ASPORTCOUNT : in std_logic_vector(7 downto 0); L0ASTURNPOOLBITSCONSUMED : in std_logic_vector(2 downto 0); L0ATTENTIONBUTTONPRESSED : in std_ulogic; L0CFGASSPANTREEOWNEDSTATE : in std_ulogic; L0CFGASSTATECHANGECMD : in std_logic_vector(3 downto 0); L0CFGDISABLESCRAMBLE : in std_ulogic; L0CFGEXTENDEDSYNC : in std_ulogic; L0CFGL0SENTRYENABLE : in std_ulogic; L0CFGL0SENTRYSUP : in std_ulogic; L0CFGL0SEXITLAT : in std_logic_vector(2 downto 0); L0CFGLINKDISABLE : in std_ulogic; L0CFGLOOPBACKMASTER : in std_ulogic; L0CFGNEGOTIATEDMAXP : in std_logic_vector(2 downto 0); L0CFGVCENABLE : in std_logic_vector(7 downto 0); L0CFGVCID : in std_logic_vector(23 downto 0); L0DLLHOLDLINKUP : in std_ulogic; L0ELECTROMECHANICALINTERLOCKENGAGED : in std_ulogic; L0FWDASSERTINTALEGACYINT : in std_ulogic; L0FWDASSERTINTBLEGACYINT : in std_ulogic; L0FWDASSERTINTCLEGACYINT : in std_ulogic; L0FWDASSERTINTDLEGACYINT : in std_ulogic; L0FWDCORRERRIN : in std_ulogic; L0FWDDEASSERTINTALEGACYINT : in std_ulogic; L0FWDDEASSERTINTBLEGACYINT : in std_ulogic; L0FWDDEASSERTINTCLEGACYINT : in std_ulogic; L0FWDDEASSERTINTDLEGACYINT : in std_ulogic; L0FWDFATALERRIN : in std_ulogic; L0FWDNONFATALERRIN : in std_ulogic; L0LEGACYINTFUNCT0 : in std_ulogic; L0MRLSENSORCLOSEDN : in std_ulogic; L0MSIREQUEST0 : in std_logic_vector(3 downto 0); L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); L0PMEREQIN : in std_ulogic; L0PORTNUMBER : in std_logic_vector(7 downto 0); L0POWERFAULTDETECTED : in std_ulogic; L0PRESENCEDETECTSLOTEMPTYN : in std_ulogic; L0PWRNEWSTATEREQ : in std_ulogic; L0PWRNEXTLINKSTATE : in std_logic_vector(1 downto 0); L0REPLAYTIMERADJUSTMENT : in std_logic_vector(11 downto 0); L0ROOTTURNOFFREQ : in std_ulogic; L0RXTLTLPNONINITIALIZEDVC : in std_logic_vector(7 downto 0); L0SENDUNLOCKMESSAGE : in std_ulogic; L0SETCOMPLETERABORTERROR : in std_ulogic; L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; L0SETDETECTEDCORRERROR : in std_ulogic; L0SETDETECTEDFATALERROR : in std_ulogic; L0SETDETECTEDNONFATALERROR : in std_ulogic; L0SETLINKDETECTEDPARITYERROR : in std_ulogic; L0SETLINKMASTERDATAPARITY : in std_ulogic; L0SETLINKRECEIVEDMASTERABORT : in std_ulogic; L0SETLINKRECEIVEDTARGETABORT : in std_ulogic; L0SETLINKSIGNALLEDTARGETABORT : in std_ulogic; L0SETLINKSYSTEMERROR : in std_ulogic; L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; L0SETUSERDETECTEDPARITYERROR : in std_ulogic; L0SETUSERMASTERDATAPARITY : in std_ulogic; L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; L0SETUSERSYSTEMERROR : in std_ulogic; L0TLASFCCREDSTARVATION : in std_ulogic; L0TLLINKRETRAIN : in std_ulogic; L0TRANSACTIONSPENDING : in std_ulogic; L0TXBEACON : in std_ulogic; L0TXCFGPM : in std_ulogic; L0TXCFGPMTYPE : in std_logic_vector(2 downto 0); L0TXTLFCCMPLMCCRED : in std_logic_vector(159 downto 0); L0TXTLFCCMPLMCUPDATE : in std_logic_vector(15 downto 0); L0TXTLFCNPOSTBYPCRED : in std_logic_vector(191 downto 0); L0TXTLFCNPOSTBYPUPDATE : in std_logic_vector(15 downto 0); L0TXTLFCPOSTORDCRED : in std_logic_vector(159 downto 0); L0TXTLFCPOSTORDUPDATE : in std_logic_vector(15 downto 0); L0TXTLSBFCDATA : in std_logic_vector(18 downto 0); L0TXTLSBFCUPDATE : in std_ulogic; L0TXTLTLPDATA : in std_logic_vector(63 downto 0); L0TXTLTLPEDB : in std_ulogic; L0TXTLTLPENABLE : in std_logic_vector(1 downto 0); L0TXTLTLPEND : in std_logic_vector(1 downto 0); L0TXTLTLPLATENCY : in std_logic_vector(3 downto 0); L0TXTLTLPREQ : in std_ulogic; L0TXTLTLPREQEND : in std_ulogic; L0TXTLTLPWIDTH : in std_ulogic; L0UPSTREAMRXPORTINL0S : in std_ulogic; L0VC0PREVIEWEXPAND : in std_ulogic; L0WAKEN : in std_ulogic; LLKRXCHFIFO : in std_logic_vector(1 downto 0); LLKRXCHTC : in std_logic_vector(2 downto 0); LLKRXDSTCONTREQN : in std_ulogic; LLKRXDSTREQN : in std_ulogic; LLKTX4DWHEADERN : in std_ulogic; LLKTXCHFIFO : in std_logic_vector(1 downto 0); LLKTXCHTC : in std_logic_vector(2 downto 0); LLKTXCOMPLETEN : in std_ulogic; LLKTXCREATEECRCN : in std_ulogic; LLKTXDATA : in std_logic_vector(63 downto 0); LLKTXENABLEN : in std_logic_vector(1 downto 0); LLKTXEOFN : in std_ulogic; LLKTXEOPN : in std_ulogic; LLKTXSOFN : in std_ulogic; LLKTXSOPN : in std_ulogic; LLKTXSRCDSCN : in std_ulogic; LLKTXSRCRDYN : in std_ulogic; MAINPOWER : in std_ulogic; MGMTADDR : in std_logic_vector(10 downto 0); MGMTBWREN : in std_logic_vector(3 downto 0); MGMTRDEN : in std_ulogic; MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); MGMTWDATA : in std_logic_vector(31 downto 0); MGMTWREN : in std_ulogic; MIMDLLBRDATA : in std_logic_vector(63 downto 0); MIMRXBRDATA : in std_logic_vector(63 downto 0); MIMTXBRDATA : in std_logic_vector(63 downto 0); PIPEPHYSTATUSL0 : in std_ulogic; PIPEPHYSTATUSL1 : in std_ulogic; PIPEPHYSTATUSL2 : in std_ulogic; PIPEPHYSTATUSL3 : in std_ulogic; PIPEPHYSTATUSL4 : in std_ulogic; PIPEPHYSTATUSL5 : in std_ulogic; PIPEPHYSTATUSL6 : in std_ulogic; PIPEPHYSTATUSL7 : in std_ulogic; PIPERXCHANISALIGNEDL0 : in std_ulogic; PIPERXCHANISALIGNEDL1 : in std_ulogic; PIPERXCHANISALIGNEDL2 : in std_ulogic; PIPERXCHANISALIGNEDL3 : in std_ulogic; PIPERXCHANISALIGNEDL4 : in std_ulogic; PIPERXCHANISALIGNEDL5 : in std_ulogic; PIPERXCHANISALIGNEDL6 : in std_ulogic; PIPERXCHANISALIGNEDL7 : in std_ulogic; PIPERXDATAKL0 : in std_ulogic; PIPERXDATAKL1 : in std_ulogic; PIPERXDATAKL2 : in std_ulogic; PIPERXDATAKL3 : in std_ulogic; PIPERXDATAKL4 : in std_ulogic; PIPERXDATAKL5 : in std_ulogic; PIPERXDATAKL6 : in std_ulogic; PIPERXDATAKL7 : in std_ulogic; PIPERXDATAL0 : in std_logic_vector(7 downto 0); PIPERXDATAL1 : in std_logic_vector(7 downto 0); PIPERXDATAL2 : in std_logic_vector(7 downto 0); PIPERXDATAL3 : in std_logic_vector(7 downto 0); PIPERXDATAL4 : in std_logic_vector(7 downto 0); PIPERXDATAL5 : in std_logic_vector(7 downto 0); PIPERXDATAL6 : in std_logic_vector(7 downto 0); PIPERXDATAL7 : in std_logic_vector(7 downto 0); PIPERXELECIDLEL0 : in std_ulogic; PIPERXELECIDLEL1 : in std_ulogic; PIPERXELECIDLEL2 : in std_ulogic; PIPERXELECIDLEL3 : in std_ulogic; PIPERXELECIDLEL4 : in std_ulogic; PIPERXELECIDLEL5 : in std_ulogic; PIPERXELECIDLEL6 : in std_ulogic; PIPERXELECIDLEL7 : in std_ulogic; PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); PIPERXVALIDL0 : in std_ulogic; PIPERXVALIDL1 : in std_ulogic; PIPERXVALIDL2 : in std_ulogic; PIPERXVALIDL3 : in std_ulogic; PIPERXVALIDL4 : in std_ulogic; PIPERXVALIDL5 : in std_ulogic; PIPERXVALIDL6 : in std_ulogic; PIPERXVALIDL7 : in std_ulogic ); end component; signal OPEN1 : std_logic; signal OPEN8 : std_logic_vector(7 downto 0); signal OPEN2 : std_logic_vector(1 downto 0); signal OPEN16 : std_logic_vector(15 downto 0); signal OPEN19 : std_logic_vector(18 downto 0); signal OPEN20 : std_logic_vector(19 downto 0); signal OPEN24 : std_logic_vector(23 downto 0); signal OPEN4 : std_logic_vector(3 downto 0); signal OPEN3 : std_logic_vector(2 downto 0); signal z1_0 : std_logic := '0'; signal z1_1 : std_logic := '1'; signal z2 : std_logic_vector(1 downto 0) := "00"; signal z3 : std_logic_vector(2 downto 0) := "000"; signal z4 : std_logic_vector(3 downto 0) := "0000"; signal z6 : std_logic_vector(5 downto 0) := "000000"; signal z8 : std_logic_vector(7 downto 0) := "00000000"; signal z12 : std_logic_vector(11 downto 0) := "000000000000"; signal z16 : std_logic_vector(15 downto 0) := "0000000000000000"; signal z19 : std_logic_vector(18 downto 0) := "0000000000000000000"; signal z24 : std_logic_vector(23 downto 0) := "000000000000000000000000"; signal z64 : std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; signal z160 : std_logic_vector(159 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; signal z192 : std_logic_vector(191 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; begin PCIE_INTERNAL_1_1_inst : PCIE_INTERNAL_1_1 generic map ( ACTIVELANESIN => ACTIVELANESIN, AERBASEPTR => AERBASEPTR, AERCAPABILITYECRCCHECKCAPABLE => FALSE, AERCAPABILITYECRCGENCAPABLE => FALSE, AERCAPABILITYNEXTPTR => AERCAPABILITYNEXTPTR, BAR0ADDRWIDTH => BAR0ADDRWIDTH, BAR0EXIST => BAR0EXIST, BAR0IOMEMN => BAR0IOMEMN, BAR0MASKWIDTH => BAR0MASKWIDTH, BAR0PREFETCHABLE => BAR0PREFETCHABLE, BAR1ADDRWIDTH => BAR1ADDRWIDTH, BAR1EXIST => BAR1EXIST, BAR1IOMEMN => BAR1IOMEMN, BAR1MASKWIDTH => BAR1MASKWIDTH, BAR1PREFETCHABLE => BAR1PREFETCHABLE, BAR2ADDRWIDTH => BAR2ADDRWIDTH, BAR2EXIST => BAR2EXIST, BAR2IOMEMN => BAR2IOMEMN, BAR2MASKWIDTH => BAR2MASKWIDTH, BAR2PREFETCHABLE => BAR2PREFETCHABLE, BAR3ADDRWIDTH => BAR3ADDRWIDTH, BAR3EXIST => BAR3EXIST, BAR3IOMEMN => BAR3IOMEMN, BAR3MASKWIDTH => BAR3MASKWIDTH, BAR3PREFETCHABLE => BAR3PREFETCHABLE, BAR4ADDRWIDTH => BAR4ADDRWIDTH, BAR4EXIST => BAR4EXIST, BAR4IOMEMN => BAR4IOMEMN, BAR4MASKWIDTH => BAR4MASKWIDTH, BAR4PREFETCHABLE => BAR4PREFETCHABLE, BAR5EXIST => BAR5EXIST, BAR5IOMEMN => BAR5IOMEMN, BAR5MASKWIDTH => BAR5MASKWIDTH, BAR5PREFETCHABLE => BAR5PREFETCHABLE, CAPABILITIESPOINTER => CAPABILITIESPOINTER, CARDBUSCISPOINTER => CARDBUSCISPOINTER, CLASSCODE => CLASSCODE, CLKDIVIDED => CLKDIVIDED, CONFIGROUTING => "001", DEVICECAPABILITYENDPOINTL0SLATENCY => DEVICECAPABILITYENDPOINTL0SLATENCY, DEVICECAPABILITYENDPOINTL1LATENCY => DEVICECAPABILITYENDPOINTL1LATENCY, DEVICEID => DEVICEID, DEVICESERIALNUMBER => DEVICESERIALNUMBER, DSNBASEPTR => DSNBASEPTR, DSNCAPABILITYNEXTPTR => DSNCAPABILITYNEXTPTR, DUALCOREENABLE => FALSE, DUALCORESLAVE => FALSE, DUALROLECFGCNTRLROOTEPN => 0, EXTCFGCAPPTR => X"00", EXTCFGXPCAPPTR => X"000", HEADERTYPE => X"00", INFINITECOMPLETIONS => INFINITECOMPLETIONS, INTERRUPTPIN => INTERRUPTPIN, ISSWITCH => FALSE, L0SEXITLATENCY => L0SEXITLATENCY, L0SEXITLATENCYCOMCLK => L0SEXITLATENCYCOMCLK, L1EXITLATENCY => L1EXITLATENCY, L1EXITLATENCYCOMCLK => L1EXITLATENCYCOMCLK, LINKCAPABILITYASPMSUPPORT => LINKCAPABILITYASPMSUPPORT, LINKCAPABILITYMAXLINKWIDTH => LINKCAPABILITYMAXLINKWIDTH, LINKSTATUSSLOTCLOCKCONFIG => LINKSTATUSSLOTCLOCKCONFIG, LLKBYPASS => FALSE, LOWPRIORITYVCCOUNT => LOWPRIORITYVCCOUNT, MSIBASEPTR => MSIBASEPTR, MSICAPABILITYMULTIMSGCAP => MSICAPABILITYMULTIMSGCAP, MSICAPABILITYNEXTPTR => MSICAPABILITYNEXTPTR, PBBASEPTR => PBBASEPTR, PBCAPABILITYDW0BASEPOWER => PBCAPABILITYDW0BASEPOWER, PBCAPABILITYDW0DATASCALE => PBCAPABILITYDW0DATASCALE, PBCAPABILITYDW0PMSTATE => PBCAPABILITYDW0PMSTATE, PBCAPABILITYDW0PMSUBSTATE => PBCAPABILITYDW0PMSUBSTATE, PBCAPABILITYDW0POWERRAIL => PBCAPABILITYDW0POWERRAIL, PBCAPABILITYDW0TYPE => PBCAPABILITYDW0TYPE, PBCAPABILITYDW1BASEPOWER => PBCAPABILITYDW1BASEPOWER, PBCAPABILITYDW1DATASCALE => PBCAPABILITYDW1DATASCALE, PBCAPABILITYDW1PMSTATE => PBCAPABILITYDW1PMSTATE, PBCAPABILITYDW1PMSUBSTATE => PBCAPABILITYDW1PMSUBSTATE, PBCAPABILITYDW1POWERRAIL => PBCAPABILITYDW1POWERRAIL, PBCAPABILITYDW1TYPE => PBCAPABILITYDW1TYPE, PBCAPABILITYDW2BASEPOWER => PBCAPABILITYDW2BASEPOWER, PBCAPABILITYDW2DATASCALE => PBCAPABILITYDW2DATASCALE, PBCAPABILITYDW2PMSTATE => PBCAPABILITYDW2PMSTATE, PBCAPABILITYDW2PMSUBSTATE => PBCAPABILITYDW2PMSUBSTATE, PBCAPABILITYDW2POWERRAIL => PBCAPABILITYDW2POWERRAIL, PBCAPABILITYDW2TYPE => PBCAPABILITYDW2TYPE, PBCAPABILITYDW3BASEPOWER => PBCAPABILITYDW3BASEPOWER, PBCAPABILITYDW3DATASCALE => PBCAPABILITYDW3DATASCALE, PBCAPABILITYDW3PMSTATE => PBCAPABILITYDW3PMSTATE, PBCAPABILITYDW3PMSUBSTATE => PBCAPABILITYDW3PMSUBSTATE, PBCAPABILITYDW3POWERRAIL => PBCAPABILITYDW3POWERRAIL, PBCAPABILITYDW3TYPE => PBCAPABILITYDW3TYPE, PBCAPABILITYNEXTPTR => PBCAPABILITYNEXTPTR, PBCAPABILITYSYSTEMALLOCATED => PBCAPABILITYSYSTEMALLOCATED, PCIECAPABILITYINTMSGNUM => "00000", PCIECAPABILITYNEXTPTR => PCIECAPABILITYNEXTPTR, PCIECAPABILITYSLOTIMPL => FALSE, PCIEREVISION => 1, PMBASEPTR => PMBASEPTR, PMCAPABILITYAUXCURRENT => PMCAPABILITYAUXCURRENT, PMCAPABILITYD1SUPPORT => PMCAPABILITYD1SUPPORT, PMCAPABILITYD2SUPPORT => PMCAPABILITYD2SUPPORT, PMCAPABILITYDSI => PMCAPABILITYDSI, PMCAPABILITYNEXTPTR => PMCAPABILITYNEXTPTR, PMCAPABILITYPMESUPPORT => PMCAPABILITYPMESUPPORT, PMDATA0 => PMDATA0, PMDATA1 => PMDATA1, PMDATA2 => PMDATA2, PMDATA3 => PMDATA3, PMDATA4 => PMDATA4, PMDATA5 => PMDATA5, PMDATA6 => PMDATA6, PMDATA7 => PMDATA7, PMDATA8 => X"00", PMDATASCALE0 => PMDATASCALE0, PMDATASCALE1 => PMDATASCALE1, PMDATASCALE2 => PMDATASCALE2, PMDATASCALE3 => PMDATASCALE3, PMDATASCALE4 => PMDATASCALE4, PMDATASCALE5 => PMDATASCALE5, PMDATASCALE6 => PMDATASCALE6, PMDATASCALE7 => PMDATASCALE7, PMDATASCALE8 => 0, PMSTATUSCONTROLDATASCALE => "00", PORTVCCAPABILITYEXTENDEDVCCOUNT => PORTVCCAPABILITYEXTENDEDVCCOUNT, PORTVCCAPABILITYVCARBCAP => PORTVCCAPABILITYVCARBCAP, PORTVCCAPABILITYVCARBTABLEOFFSET => PORTVCCAPABILITYVCARBTABLEOFFSET, RAMSHARETXRX => FALSE, RESETMODE => RESETMODE, RETRYRAMREADLATENCY => RETRYRAMREADLATENCY, RETRYRAMSIZE => RETRYRAMSIZE, RETRYRAMWIDTH => 0, RETRYRAMWRITELATENCY => RETRYRAMWRITELATENCY, RETRYREADADDRPIPE => FALSE, RETRYREADDATAPIPE => FALSE, RETRYWRITEPIPE => FALSE, REVISIONID => REVISIONID, RXREADADDRPIPE => FALSE, RXREADDATAPIPE => FALSE, RXWRITEPIPE => FALSE, SELECTASMODE => FALSE, SELECTDLLIF => FALSE, SLOTCAPABILITYATTBUTTONPRESENT => FALSE, SLOTCAPABILITYATTINDICATORPRESENT => FALSE, SLOTCAPABILITYHOTPLUGCAPABLE => FALSE, SLOTCAPABILITYHOTPLUGSURPRISE => FALSE, SLOTCAPABILITYMSLSENSORPRESENT => FALSE, SLOTCAPABILITYPHYSICALSLOTNUM => "0000000000000", SLOTCAPABILITYPOWERCONTROLLERPRESENT => FALSE, SLOTCAPABILITYPOWERINDICATORPRESENT => FALSE, SLOTCAPABILITYSLOTPOWERLIMITSCALE => "00", SLOTCAPABILITYSLOTPOWERLIMITVALUE => X"00", SLOTIMPLEMENTED => FALSE, SUBSYSTEMID => SUBSYSTEMID, SUBSYSTEMVENDORID => SUBSYSTEMVENDORID, TLRAMREADLATENCY => TLRAMREADLATENCY, TLRAMWIDTH => 0, TLRAMWRITELATENCY => TLRAMWRITELATENCY, TXREADADDRPIPE => FALSE, TXREADDATAPIPE => FALSE, TXTSNFTS => TXTSNFTS, TXTSNFTSCOMCLK => TXTSNFTSCOMCLK, TXWRITEPIPE => FALSE, UPSTREAMFACING => TRUE, VC0RXFIFOBASEC => VC0RXFIFOBASEC, VC0RXFIFOBASENP => VC0RXFIFOBASENP, VC0RXFIFOBASEP => VC0RXFIFOBASEP, VC0RXFIFOLIMITC => VC0RXFIFOLIMITC, VC0RXFIFOLIMITNP => VC0RXFIFOLIMITNP, VC0RXFIFOLIMITP => VC0RXFIFOLIMITP, VC0TOTALCREDITSCD => VC0TOTALCREDITSCD, VC0TOTALCREDITSCH => VC0TOTALCREDITSCH, VC0TOTALCREDITSNPH => VC0TOTALCREDITSNPH, VC0TOTALCREDITSPD => VC0TOTALCREDITSPD, VC0TOTALCREDITSPH => VC0TOTALCREDITSPH, VC0TXFIFOBASEC => VC0TXFIFOBASEC, VC0TXFIFOBASENP => VC0TXFIFOBASENP, VC0TXFIFOBASEP => VC0TXFIFOBASEP, VC0TXFIFOLIMITC => VC0TXFIFOLIMITC, VC0TXFIFOLIMITNP => VC0TXFIFOLIMITNP, VC0TXFIFOLIMITP => VC0TXFIFOLIMITP, VC1RXFIFOBASEC => VC1RXFIFOBASEC, VC1RXFIFOBASENP => VC1RXFIFOBASENP, VC1RXFIFOBASEP => VC1RXFIFOBASEP, VC1RXFIFOLIMITC => VC1RXFIFOLIMITC, VC1RXFIFOLIMITNP => VC1RXFIFOLIMITNP, VC1RXFIFOLIMITP => VC1RXFIFOLIMITP, VC1TOTALCREDITSCD => VC1TOTALCREDITSCD, VC1TOTALCREDITSCH => VC1TOTALCREDITSCH, VC1TOTALCREDITSNPH => VC1TOTALCREDITSNPH, VC1TOTALCREDITSPD => VC1TOTALCREDITSPD, VC1TOTALCREDITSPH => VC1TOTALCREDITSPH, VC1TXFIFOBASEC => VC1TXFIFOBASEC, VC1TXFIFOBASENP => VC1TXFIFOBASENP, VC1TXFIFOBASEP => VC1TXFIFOBASEP, VC1TXFIFOLIMITC => VC1TXFIFOLIMITC, VC1TXFIFOLIMITNP => VC1TXFIFOLIMITNP, VC1TXFIFOLIMITP => VC1TXFIFOLIMITP, VCBASEPTR => VCBASEPTR, VCCAPABILITYNEXTPTR => VCCAPABILITYNEXTPTR, VENDORID => VENDORID, XLINKSUPPORTED => FALSE, XPBASEPTR => XPBASEPTR, XPDEVICEPORTTYPE => XPDEVICEPORTTYPE, XPMAXPAYLOAD => XPMAXPAYLOAD, XPRCBCONTROL => 0 ) port map ( AUXPOWER => AUXPOWER, BUSMASTERENABLE => BUSMASTERENABLE, CFGNEGOTIATEDLINKWIDTH => z6, COMPLIANCEAVOID => COMPLIANCEAVOID, CRMCFGBRIDGEHOTRESET => z1_0, CRMCORECLK => CRMCORECLK, CRMCORECLKDLO => CRMCORECLKDLO, CRMCORECLKRXO => CRMCORECLKRXO, CRMCORECLKTXO => CRMCORECLKTXO, CRMDOHOTRESETN => CRMDOHOTRESETN, CRMLINKRSTN => CRMLINKRSTN, CRMMACRSTN => CRMMACRSTN, CRMMGMTRSTN => CRMMGMTRSTN, CRMNVRSTN => CRMNVRSTN, CRMPWRSOFTRESETN => CRMPWRSOFTRESETN, CRMRXHOTRESETN => OPEN1, CRMTXHOTRESETN => z1_1, CRMURSTN => CRMURSTN, CRMUSERCFGRSTN => CRMUSERCFGRSTN, CRMUSERCLK => CRMUSERCLK, CRMUSERCLKRXO => CRMUSERCLKRXO, CRMUSERCLKTXO => CRMUSERCLKTXO, CROSSLINKSEED => z1_1, DLLTXPMDLLPOUTSTANDING => DLLTXPMDLLPOUTSTANDING, INTERRUPTDISABLE => INTERRUPTDISABLE, IOSPACEENABLE => IOSPACEENABLE, L0ACKNAKTIMERADJUSTMENT => z12, L0ALLDOWNPORTSINL1 => z1_0, L0ALLDOWNRXPORTSINL0S => z1_0, L0ASAUTONOMOUSINITCOMPLETED => OPEN1, L0ASE => z1_0, L0ASPORTCOUNT => z8, L0ASTURNPOOLBITSCONSUMED => z3, L0ATTENTIONBUTTONPRESSED => z1_0, L0ATTENTIONINDICATORCONTROL => OPEN2, L0CFGASSPANTREEOWNEDSTATE => z1_0, L0CFGASSTATECHANGECMD => z4, L0CFGDISABLESCRAMBLE => L0CFGDISABLESCRAMBLE, L0CFGEXTENDEDSYNC => z1_0, L0CFGL0SENTRYENABLE => z1_0, L0CFGL0SENTRYSUP => z1_0, L0CFGL0SEXITLAT => z3, L0CFGLINKDISABLE => z1_0, L0CFGLOOPBACKACK => L0CFGLOOPBACKACK, L0CFGLOOPBACKMASTER => L0CFGLOOPBACKMASTER, L0CFGNEGOTIATEDMAXP => z3, L0CFGVCENABLE => z8, L0CFGVCID => z24, L0COMPLETERID => L0COMPLETERID, L0CORRERRMSGRCVD => OPEN1, L0DLLASRXSTATE => OPEN2, L0DLLASTXSTATE => OPEN1, L0DLLERRORVECTOR => L0DLLERRORVECTOR, L0DLLHOLDLINKUP => z1_0, L0DLLRXACKOUTSTANDING => L0DLLRXACKOUTSTANDING, L0DLLTXNONFCOUTSTANDING => L0DLLTXNONFCOUTSTANDING, L0DLLTXOUTSTANDING => L0DLLTXOUTSTANDING, L0DLLVCSTATUS => L0DLLVCSTATUS, L0DLUPDOWN => L0DLUPDOWN, L0ELECTROMECHANICALINTERLOCKENGAGED => z1_0, L0ERRMSGREQID => OPEN16, L0FATALERRMSGRCVD => OPEN1, L0FIRSTCFGWRITEOCCURRED => L0FIRSTCFGWRITEOCCURRED, L0FWDASSERTINTALEGACYINT => z1_0, L0FWDASSERTINTBLEGACYINT => z1_0, L0FWDASSERTINTCLEGACYINT => z1_0, L0FWDASSERTINTDLEGACYINT => z1_0, L0FWDCORRERRIN => z1_0, L0FWDCORRERROUT => OPEN1, L0FWDDEASSERTINTALEGACYINT => z1_0, L0FWDDEASSERTINTBLEGACYINT => z1_0, L0FWDDEASSERTINTCLEGACYINT => z1_0, L0FWDDEASSERTINTDLEGACYINT => z1_0, L0FWDFATALERRIN => z1_0, L0FWDFATALERROUT => OPEN1, L0FWDNONFATALERRIN => z1_0, L0FWDNONFATALERROUT => OPEN1, L0LEGACYINTFUNCT0 => L0LEGACYINTFUNCT0, L0LTSSMSTATE => L0LTSSMSTATE, L0MACENTEREDL0 => L0MACENTEREDL0, L0MACLINKTRAINING => L0MACLINKTRAINING, L0MACLINKUP => L0MACLINKUP, L0MACNEGOTIATEDLINKWIDTH => L0MACNEGOTIATEDLINKWIDTH, L0MACNEWSTATEACK => L0MACNEWSTATEACK, L0MACRXL0SSTATE => L0MACRXL0SSTATE, L0MACUPSTREAMDOWNSTREAM => OPEN1, L0MCFOUND => OPEN3, L0MRLSENSORCLOSEDN => z1_0, L0MSIENABLE0 => L0MSIENABLE0, L0MSIREQUEST0 => L0MSIREQUEST0, L0MULTIMSGEN0 => L0MULTIMSGEN0, L0NONFATALERRMSGRCVD => OPEN1, L0PACKETHEADERFROMUSER => L0PACKETHEADERFROMUSER, L0PMEACK => L0PMEACK, L0PMEEN => L0PMEEN, L0PMEREQIN => L0PMEREQIN, L0PMEREQOUT => L0PMEREQOUT, L0PORTNUMBER => z8, L0POWERCONTROLLERCONTROL => OPEN1, L0POWERFAULTDETECTED => z1_0, L0POWERINDICATORCONTROL => OPEN2, L0PRESENCEDETECTSLOTEMPTYN => z1_0, L0PWRINHIBITTRANSFERS => OPEN1, L0PWRL1STATE => L0PWRL1STATE, L0PWRL23READYDEVICE => OPEN1, L0PWRL23READYSTATE => L0PWRL23READYSTATE, L0PWRNEWSTATEREQ => z1_0, L0PWRNEXTLINKSTATE => z2, L0PWRSTATE0 => L0PWRSTATE0, L0PWRTURNOFFREQ => L0PWRTURNOFFREQ, L0PWRTXL0SSTATE => L0PWRTXL0SSTATE, L0RECEIVEDASSERTINTALEGACYINT => OPEN1, L0RECEIVEDASSERTINTBLEGACYINT => OPEN1, L0RECEIVEDASSERTINTCLEGACYINT => OPEN1, L0RECEIVEDASSERTINTDLEGACYINT => OPEN1, L0RECEIVEDDEASSERTINTALEGACYINT => OPEN1, L0RECEIVEDDEASSERTINTBLEGACYINT => OPEN1, L0RECEIVEDDEASSERTINTCLEGACYINT => OPEN1, L0RECEIVEDDEASSERTINTDLEGACYINT => OPEN1, L0REPLAYTIMERADJUSTMENT => z12, L0ROOTTURNOFFREQ => z1_0, L0RXBEACON => OPEN1, L0RXDLLFCCMPLMCCRED => OPEN24, L0RXDLLFCCMPLMCUPDATE => OPEN8, L0RXDLLFCNPOSTBYPCRED => OPEN20, L0RXDLLFCNPOSTBYPUPDATE => OPEN8, L0RXDLLFCPOSTORDCRED => OPEN24, L0RXDLLFCPOSTORDUPDATE => OPEN8, L0RXDLLPM => L0RXDLLPM, L0RXDLLPMTYPE => L0RXDLLPMTYPE, L0RXDLLSBFCDATA => OPEN19, L0RXDLLSBFCUPDATE => OPEN1, L0RXDLLTLPECRCOK => OPEN1, L0RXDLLTLPEND => OPEN2, L0RXMACLINKERROR => L0RXMACLINKERROR, L0RXTLTLPNONINITIALIZEDVC => z8, L0SENDUNLOCKMESSAGE => z1_0, L0SETCOMPLETERABORTERROR => L0SETCOMPLETERABORTERROR, L0SETCOMPLETIONTIMEOUTCORRERROR => L0SETCOMPLETIONTIMEOUTCORRERROR, L0SETCOMPLETIONTIMEOUTUNCORRERROR => L0SETCOMPLETIONTIMEOUTUNCORRERROR, L0SETDETECTEDCORRERROR => L0SETDETECTEDCORRERROR, L0SETDETECTEDFATALERROR => L0SETDETECTEDFATALERROR, L0SETDETECTEDNONFATALERROR => L0SETDETECTEDNONFATALERROR, L0SETLINKDETECTEDPARITYERROR => z1_0, L0SETLINKMASTERDATAPARITY => z1_0, L0SETLINKRECEIVEDMASTERABORT => z1_0, L0SETLINKRECEIVEDTARGETABORT => z1_0, L0SETLINKSIGNALLEDTARGETABORT => z1_0, L0SETLINKSYSTEMERROR => z1_0, L0SETUNEXPECTEDCOMPLETIONCORRERROR => L0SETUNEXPECTEDCOMPLETIONCORRERROR, L0SETUNEXPECTEDCOMPLETIONUNCORRERROR => L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR => L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR, L0SETUNSUPPORTEDREQUESTOTHERERROR => L0SETUNSUPPORTEDREQUESTOTHERERROR, L0SETUSERDETECTEDPARITYERROR => L0SETUSERDETECTEDPARITYERROR, L0SETUSERMASTERDATAPARITY => L0SETUSERMASTERDATAPARITY, L0SETUSERRECEIVEDMASTERABORT => L0SETUSERRECEIVEDMASTERABORT, L0SETUSERRECEIVEDTARGETABORT => L0SETUSERRECEIVEDTARGETABORT, L0SETUSERSIGNALLEDTARGETABORT => L0SETUSERSIGNALLEDTARGETABORT, L0SETUSERSYSTEMERROR => L0SETUSERSYSTEMERROR, L0STATSCFGOTHERRECEIVED => L0STATSCFGOTHERRECEIVED, L0STATSCFGOTHERTRANSMITTED => L0STATSCFGOTHERTRANSMITTED, L0STATSCFGRECEIVED => L0STATSCFGRECEIVED, L0STATSCFGTRANSMITTED => L0STATSCFGTRANSMITTED, L0STATSDLLPRECEIVED => L0STATSDLLPRECEIVED, L0STATSDLLPTRANSMITTED => L0STATSDLLPTRANSMITTED, L0STATSOSRECEIVED => L0STATSOSRECEIVED, L0STATSOSTRANSMITTED => L0STATSOSTRANSMITTED, L0STATSTLPRECEIVED => L0STATSTLPRECEIVED, L0STATSTLPTRANSMITTED => L0STATSTLPTRANSMITTED, L0TLASFCCREDSTARVATION => z1_0, L0TLLINKRETRAIN => z1_0, L0TOGGLEELECTROMECHANICALINTERLOCK => OPEN1, L0TRANSACTIONSPENDING => L0TRANSACTIONSPENDING, L0TRANSFORMEDVC => OPEN3, L0TXBEACON => z1_0, L0TXCFGPM => z1_0, L0TXCFGPMTYPE => z3, L0TXDLLFCCMPLMCUPDATED => OPEN8, L0TXDLLFCNPOSTBYPUPDATED => OPEN8, L0TXDLLFCPOSTORDUPDATED => OPEN8, L0TXDLLPMUPDATED => OPEN1, L0TXDLLSBFCUPDATED => OPEN1, L0TXTLFCCMPLMCCRED => z160, L0TXTLFCCMPLMCUPDATE => z16, L0TXTLFCNPOSTBYPCRED => z192, L0TXTLFCNPOSTBYPUPDATE => z16, L0TXTLFCPOSTORDCRED => z160, L0TXTLFCPOSTORDUPDATE => z16, L0TXTLSBFCDATA => z19, L0TXTLSBFCUPDATE => z1_0, L0TXTLTLPDATA => z64, L0TXTLTLPEDB => z1_0, L0TXTLTLPENABLE => z2, L0TXTLTLPEND => z2, L0TXTLTLPLATENCY => z4, L0TXTLTLPREQ => z1_0, L0TXTLTLPREQEND => z1_0, L0TXTLTLPWIDTH => z1_0, L0UCBYPFOUND => OPEN4, L0UCORDFOUND => OPEN4, L0UNLOCKRECEIVED => L0UNLOCKRECEIVED, L0UPSTREAMRXPORTINL0S => z1_0, L0VC0PREVIEWEXPAND => z1_0, L0WAKEN => z1_1, LLKRX4DWHEADERN => OPEN1, LLKRXCHCOMPLETIONAVAILABLEN => LLKRXCHCOMPLETIONAVAILABLEN, LLKRXCHCOMPLETIONPARTIALN => OPEN8, LLKRXCHCONFIGAVAILABLEN => OPEN1, LLKRXCHCONFIGPARTIALN => OPEN1, LLKRXCHFIFO => LLKRXCHFIFO, LLKRXCHNONPOSTEDAVAILABLEN => LLKRXCHNONPOSTEDAVAILABLEN, LLKRXCHNONPOSTEDPARTIALN => OPEN8, LLKRXCHPOSTEDAVAILABLEN => LLKRXCHPOSTEDAVAILABLEN, LLKRXCHPOSTEDPARTIALN => OPEN8, LLKRXCHTC => LLKRXCHTC, LLKRXDATA => LLKRXDATA, LLKRXDSTCONTREQN => LLKRXDSTCONTREQN, LLKRXDSTREQN => LLKRXDSTREQN, LLKRXECRCBADN => OPEN1, LLKRXEOFN => LLKRXEOFN, LLKRXEOPN => LLKRXEOPN, LLKRXPREFERREDTYPE => LLKRXPREFERREDTYPE, LLKRXSOFN => LLKRXSOFN, LLKRXSOPN => LLKRXSOPN, LLKRXSRCDSCN => OPEN1, LLKRXSRCLASTREQN => LLKRXSRCLASTREQN, LLKRXSRCRDYN => LLKRXSRCRDYN, LLKRXVALIDN => LLKRXVALIDN, LLKTCSTATUS => LLKTCSTATUS, LLKTX4DWHEADERN => z1_1, LLKTXCHANSPACE => LLKTXCHANSPACE, LLKTXCHCOMPLETIONREADYN => LLKTXCHCOMPLETIONREADYN, LLKTXCHFIFO => LLKTXCHFIFO, LLKTXCHNONPOSTEDREADYN => LLKTXCHNONPOSTEDREADYN, LLKTXCHPOSTEDREADYN => LLKTXCHPOSTEDREADYN, LLKTXCHTC => LLKTXCHTC, LLKTXCOMPLETEN => z1_1, LLKTXCONFIGREADYN => LLKTXCONFIGREADYN, LLKTXCREATEECRCN => z1_1, LLKTXDATA => LLKTXDATA, LLKTXDSTRDYN => LLKTXDSTRDYN, LLKTXENABLEN => LLKTXENABLEN, LLKTXEOFN => LLKTXEOFN, LLKTXEOPN => LLKTXEOPN, LLKTXSOFN => LLKTXSOFN, LLKTXSOPN => LLKTXSOPN, LLKTXSRCDSCN => LLKTXSRCDSCN, LLKTXSRCRDYN => LLKTXSRCRDYN, MAINPOWER => z1_1, MAXPAYLOADSIZE => MAXPAYLOADSIZE, MAXREADREQUESTSIZE => MAXREADREQUESTSIZE, MEMSPACEENABLE => MEMSPACEENABLE, MGMTADDR => MGMTADDR, MGMTBWREN => MGMTBWREN, MGMTPSO => MGMTPSO, MGMTRDATA => MGMTRDATA, MGMTRDEN => MGMTRDEN, MGMTSTATSCREDIT => MGMTSTATSCREDIT, MGMTSTATSCREDITSEL => MGMTSTATSCREDITSEL, MGMTWDATA => MGMTWDATA, MGMTWREN => MGMTWREN, MIMDLLBRADD => MIMDLLBRADD, MIMDLLBRDATA => MIMDLLBRDATA, MIMDLLBREN => MIMDLLBREN, MIMDLLBWADD => MIMDLLBWADD, MIMDLLBWDATA => MIMDLLBWDATA, MIMDLLBWEN => MIMDLLBWEN, MIMRXBRADD => MIMRXBRADD, MIMRXBRDATA => MIMRXBRDATA, MIMRXBREN => MIMRXBREN, MIMRXBWADD => MIMRXBWADD, MIMRXBWDATA => MIMRXBWDATA, MIMRXBWEN => MIMRXBWEN, MIMTXBRADD => MIMTXBRADD, MIMTXBRDATA => MIMTXBRDATA, MIMTXBREN => MIMTXBREN, MIMTXBWADD => MIMTXBWADD, MIMTXBWDATA => MIMTXBWDATA, MIMTXBWEN => MIMTXBWEN, PARITYERRORRESPONSE => PARITYERRORRESPONSE, PIPEDESKEWLANESL0 => PIPEDESKEWLANESL0, PIPEDESKEWLANESL1 => PIPEDESKEWLANESL1, PIPEDESKEWLANESL2 => PIPEDESKEWLANESL2, PIPEDESKEWLANESL3 => PIPEDESKEWLANESL3, PIPEDESKEWLANESL4 => PIPEDESKEWLANESL4, PIPEDESKEWLANESL5 => PIPEDESKEWLANESL5, PIPEDESKEWLANESL6 => PIPEDESKEWLANESL6, PIPEDESKEWLANESL7 => PIPEDESKEWLANESL7, PIPEPHYSTATUSL0 => PIPEPHYSTATUSL0, PIPEPHYSTATUSL1 => PIPEPHYSTATUSL1, PIPEPHYSTATUSL2 => PIPEPHYSTATUSL2, PIPEPHYSTATUSL3 => PIPEPHYSTATUSL3, PIPEPHYSTATUSL4 => PIPEPHYSTATUSL4, PIPEPHYSTATUSL5 => PIPEPHYSTATUSL5, PIPEPHYSTATUSL6 => PIPEPHYSTATUSL6, PIPEPHYSTATUSL7 => PIPEPHYSTATUSL7, PIPEPOWERDOWNL0 => PIPEPOWERDOWNL0, PIPEPOWERDOWNL1 => PIPEPOWERDOWNL1, PIPEPOWERDOWNL2 => PIPEPOWERDOWNL2, PIPEPOWERDOWNL3 => PIPEPOWERDOWNL3, PIPEPOWERDOWNL4 => PIPEPOWERDOWNL4, PIPEPOWERDOWNL5 => PIPEPOWERDOWNL5, PIPEPOWERDOWNL6 => PIPEPOWERDOWNL6, PIPEPOWERDOWNL7 => PIPEPOWERDOWNL7, PIPERESETL0 => PIPERESETL0, PIPERESETL1 => PIPERESETL1, PIPERESETL2 => PIPERESETL2, PIPERESETL3 => PIPERESETL3, PIPERESETL4 => PIPERESETL4, PIPERESETL5 => PIPERESETL5, PIPERESETL6 => PIPERESETL6, PIPERESETL7 => PIPERESETL7, PIPERXCHANISALIGNEDL0 => PIPERXCHANISALIGNEDL0, PIPERXCHANISALIGNEDL1 => PIPERXCHANISALIGNEDL1, PIPERXCHANISALIGNEDL2 => PIPERXCHANISALIGNEDL2, PIPERXCHANISALIGNEDL3 => PIPERXCHANISALIGNEDL3, PIPERXCHANISALIGNEDL4 => PIPERXCHANISALIGNEDL4, PIPERXCHANISALIGNEDL5 => PIPERXCHANISALIGNEDL5, PIPERXCHANISALIGNEDL6 => PIPERXCHANISALIGNEDL6, PIPERXCHANISALIGNEDL7 => PIPERXCHANISALIGNEDL7, PIPERXDATAKL0 => PIPERXDATAKL0, PIPERXDATAKL1 => PIPERXDATAKL1, PIPERXDATAKL2 => PIPERXDATAKL2, PIPERXDATAKL3 => PIPERXDATAKL3, PIPERXDATAKL4 => PIPERXDATAKL4, PIPERXDATAKL5 => PIPERXDATAKL5, PIPERXDATAKL6 => PIPERXDATAKL6, PIPERXDATAKL7 => PIPERXDATAKL7, PIPERXDATAL0 => PIPERXDATAL0, PIPERXDATAL1 => PIPERXDATAL1, PIPERXDATAL2 => PIPERXDATAL2, PIPERXDATAL3 => PIPERXDATAL3, PIPERXDATAL4 => PIPERXDATAL4, PIPERXDATAL5 => PIPERXDATAL5, PIPERXDATAL6 => PIPERXDATAL6, PIPERXDATAL7 => PIPERXDATAL7, PIPERXELECIDLEL0 => PIPERXELECIDLEL0, PIPERXELECIDLEL1 => PIPERXELECIDLEL1, PIPERXELECIDLEL2 => PIPERXELECIDLEL2, PIPERXELECIDLEL3 => PIPERXELECIDLEL3, PIPERXELECIDLEL4 => PIPERXELECIDLEL4, PIPERXELECIDLEL5 => PIPERXELECIDLEL5, PIPERXELECIDLEL6 => PIPERXELECIDLEL6, PIPERXELECIDLEL7 => PIPERXELECIDLEL7, PIPERXPOLARITYL0 => PIPERXPOLARITYL0, PIPERXPOLARITYL1 => PIPERXPOLARITYL1, PIPERXPOLARITYL2 => PIPERXPOLARITYL2, PIPERXPOLARITYL3 => PIPERXPOLARITYL3, PIPERXPOLARITYL4 => PIPERXPOLARITYL4, PIPERXPOLARITYL5 => PIPERXPOLARITYL5, PIPERXPOLARITYL6 => PIPERXPOLARITYL6, PIPERXPOLARITYL7 => PIPERXPOLARITYL7, PIPERXSTATUSL0 => PIPERXSTATUSL0, PIPERXSTATUSL1 => PIPERXSTATUSL1, PIPERXSTATUSL2 => PIPERXSTATUSL2, PIPERXSTATUSL3 => PIPERXSTATUSL3, PIPERXSTATUSL4 => PIPERXSTATUSL4, PIPERXSTATUSL5 => PIPERXSTATUSL5, PIPERXSTATUSL6 => PIPERXSTATUSL6, PIPERXSTATUSL7 => PIPERXSTATUSL7, PIPERXVALIDL0 => PIPERXVALIDL0, PIPERXVALIDL1 => PIPERXVALIDL1, PIPERXVALIDL2 => PIPERXVALIDL2, PIPERXVALIDL3 => PIPERXVALIDL3, PIPERXVALIDL4 => PIPERXVALIDL4, PIPERXVALIDL5 => PIPERXVALIDL5, PIPERXVALIDL6 => PIPERXVALIDL6, PIPERXVALIDL7 => PIPERXVALIDL7, PIPETXCOMPLIANCEL0 => PIPETXCOMPLIANCEL0, PIPETXCOMPLIANCEL1 => PIPETXCOMPLIANCEL1, PIPETXCOMPLIANCEL2 => PIPETXCOMPLIANCEL2, PIPETXCOMPLIANCEL3 => PIPETXCOMPLIANCEL3, PIPETXCOMPLIANCEL4 => PIPETXCOMPLIANCEL4, PIPETXCOMPLIANCEL5 => PIPETXCOMPLIANCEL5, PIPETXCOMPLIANCEL6 => PIPETXCOMPLIANCEL6, PIPETXCOMPLIANCEL7 => PIPETXCOMPLIANCEL7, PIPETXDATAKL0 => PIPETXDATAKL0, PIPETXDATAKL1 => PIPETXDATAKL1, PIPETXDATAKL2 => PIPETXDATAKL2, PIPETXDATAKL3 => PIPETXDATAKL3, PIPETXDATAKL4 => PIPETXDATAKL4, PIPETXDATAKL5 => PIPETXDATAKL5, PIPETXDATAKL6 => PIPETXDATAKL6, PIPETXDATAKL7 => PIPETXDATAKL7, PIPETXDATAL0 => PIPETXDATAL0, PIPETXDATAL1 => PIPETXDATAL1, PIPETXDATAL2 => PIPETXDATAL2, PIPETXDATAL3 => PIPETXDATAL3, PIPETXDATAL4 => PIPETXDATAL4, PIPETXDATAL5 => PIPETXDATAL5, PIPETXDATAL6 => PIPETXDATAL6, PIPETXDATAL7 => PIPETXDATAL7, PIPETXDETECTRXLOOPBACKL0 => PIPETXDETECTRXLOOPBACKL0, PIPETXDETECTRXLOOPBACKL1 => PIPETXDETECTRXLOOPBACKL1, PIPETXDETECTRXLOOPBACKL2 => PIPETXDETECTRXLOOPBACKL2, PIPETXDETECTRXLOOPBACKL3 => PIPETXDETECTRXLOOPBACKL3, PIPETXDETECTRXLOOPBACKL4 => PIPETXDETECTRXLOOPBACKL4, PIPETXDETECTRXLOOPBACKL5 => PIPETXDETECTRXLOOPBACKL5, PIPETXDETECTRXLOOPBACKL6 => PIPETXDETECTRXLOOPBACKL6, PIPETXDETECTRXLOOPBACKL7 => PIPETXDETECTRXLOOPBACKL7, PIPETXELECIDLEL0 => PIPETXELECIDLEL0, PIPETXELECIDLEL1 => PIPETXELECIDLEL1, PIPETXELECIDLEL2 => PIPETXELECIDLEL2, PIPETXELECIDLEL3 => PIPETXELECIDLEL3, PIPETXELECIDLEL4 => PIPETXELECIDLEL4, PIPETXELECIDLEL5 => PIPETXELECIDLEL5, PIPETXELECIDLEL6 => PIPETXELECIDLEL6, PIPETXELECIDLEL7 => PIPETXELECIDLEL7, SERRENABLE => SERRENABLE, URREPORTINGENABLE => URREPORTINGENABLE ); end PCIE_EP_V; ------------------------------------------------------------------------------- -- Copyright (c) 1995/2006 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / PCI Express -- /___/ /\ Filename : pcie_internal_1_1.vhd -- \ \ / \ Timestamp : Thu Dec 8 2005 -- \___\/\___\ -- -- Revision: -- 12/08/05 - Initial version. -- 01/09/06 - Added architecture -- 01/23/06 - Parameter MC updates CR#224562 -- 01/27/06 - CR#224810 Remove GSR pins -- 02/23/06 - Updated Header -- 04/24/06 - CR#230393 - Updated timing according to the spreadsheets -- 04/28/06 - CR#230712 - Spreadsheet update -- 05/23/06 - CR#231962 - Add buffers for connectivity -- 08/14/06 - CR#421379 - PCIE updated to PCIE_INTERNAL_1_1 -- - spreadsheet updates on parameter default values -- 10/26/06 - - replaced ZERO_DELAY with CLK_DELAY to be consistent with writers (PPC440 update) -- End Revision ----- CELL PCIE_INTERNAL_1_1 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; library secureip; use secureip.all; entity PCIE_INTERNAL_1_1 is generic ( ACTIVELANESIN : bit_vector := X"01"; AERBASEPTR : bit_vector := X"110"; AERCAPABILITYECRCCHECKCAPABLE : boolean := FALSE; AERCAPABILITYECRCGENCAPABLE : boolean := FALSE; AERCAPABILITYNEXTPTR : bit_vector := X"138"; BAR0ADDRWIDTH : integer := 0; BAR0EXIST : boolean := TRUE; BAR0IOMEMN : integer := 0; BAR0MASKWIDTH : bit_vector := X"14"; BAR0PREFETCHABLE : boolean := TRUE; BAR1ADDRWIDTH : integer := 0; BAR1EXIST : boolean := FALSE; BAR1IOMEMN : integer := 0; BAR1MASKWIDTH : bit_vector := X"00"; BAR1PREFETCHABLE : boolean := FALSE; BAR2ADDRWIDTH : integer := 0; BAR2EXIST : boolean := FALSE; BAR2IOMEMN : integer := 0; BAR2MASKWIDTH : bit_vector := X"00"; BAR2PREFETCHABLE : boolean := FALSE; BAR3ADDRWIDTH : integer := 0; BAR3EXIST : boolean := FALSE; BAR3IOMEMN : integer := 0; BAR3MASKWIDTH : bit_vector := X"00"; BAR3PREFETCHABLE : boolean := FALSE; BAR4ADDRWIDTH : integer := 0; BAR4EXIST : boolean := FALSE; BAR4IOMEMN : integer := 0; BAR4MASKWIDTH : bit_vector := X"00"; BAR4PREFETCHABLE : boolean := FALSE; BAR5EXIST : boolean := FALSE; BAR5IOMEMN : integer := 0; BAR5MASKWIDTH : bit_vector := X"00"; BAR5PREFETCHABLE : boolean := FALSE; CAPABILITIESPOINTER : bit_vector := X"40"; CARDBUSCISPOINTER : bit_vector := X"00000000"; CLASSCODE : bit_vector := X"058000"; CLKDIVIDED : boolean := FALSE; CONFIGROUTING : bit_vector := X"1"; DEVICECAPABILITYENDPOINTL0SLATENCY : bit_vector := X"0"; DEVICECAPABILITYENDPOINTL1LATENCY : bit_vector := X"0"; DEVICEID : bit_vector := X"5050"; DEVICESERIALNUMBER : bit_vector := X"E000000001000A35"; DSNBASEPTR : bit_vector := X"148"; DSNCAPABILITYNEXTPTR : bit_vector := X"154"; DUALCOREENABLE : boolean := FALSE; DUALCORESLAVE : boolean := FALSE; DUALROLECFGCNTRLROOTEPN : integer := 0; EXTCFGCAPPTR : bit_vector := X"00"; EXTCFGXPCAPPTR : bit_vector := X"000"; HEADERTYPE : bit_vector := X"00"; INFINITECOMPLETIONS : boolean := TRUE; INTERRUPTPIN : bit_vector := X"00"; ISSWITCH : boolean := FALSE; L0SEXITLATENCY : integer := 7; L0SEXITLATENCYCOMCLK : integer := 7; L1EXITLATENCY : integer := 7; L1EXITLATENCYCOMCLK : integer := 7; LINKCAPABILITYASPMSUPPORT : bit_vector := X"1"; LINKCAPABILITYMAXLINKWIDTH : bit_vector := X"01"; LINKSTATUSSLOTCLOCKCONFIG : boolean := FALSE; LLKBYPASS : boolean := FALSE; LOWPRIORITYVCCOUNT : integer := 0; MSIBASEPTR : bit_vector := X"048"; MSICAPABILITYMULTIMSGCAP : bit_vector := X"0"; MSICAPABILITYNEXTPTR : bit_vector := X"60"; PBBASEPTR : bit_vector := X"138"; PBCAPABILITYDW0BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW0DATASCALE : bit_vector := X"0"; PBCAPABILITYDW0PMSTATE : bit_vector := X"0"; PBCAPABILITYDW0PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW0POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW0TYPE : bit_vector := X"0"; PBCAPABILITYDW1BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW1DATASCALE : bit_vector := X"0"; PBCAPABILITYDW1PMSTATE : bit_vector := X"0"; PBCAPABILITYDW1PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW1POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW1TYPE : bit_vector := X"0"; PBCAPABILITYDW2BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW2DATASCALE : bit_vector := X"0"; PBCAPABILITYDW2PMSTATE : bit_vector := X"0"; PBCAPABILITYDW2PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW2POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW2TYPE : bit_vector := X"0"; PBCAPABILITYDW3BASEPOWER : bit_vector := X"00"; PBCAPABILITYDW3DATASCALE : bit_vector := X"0"; PBCAPABILITYDW3PMSTATE : bit_vector := X"0"; PBCAPABILITYDW3PMSUBSTATE : bit_vector := X"0"; PBCAPABILITYDW3POWERRAIL : bit_vector := X"0"; PBCAPABILITYDW3TYPE : bit_vector := X"0"; PBCAPABILITYNEXTPTR : bit_vector := X"148"; PBCAPABILITYSYSTEMALLOCATED : boolean := FALSE; PCIECAPABILITYINTMSGNUM : bit_vector := X"00"; PCIECAPABILITYNEXTPTR : bit_vector := X"00"; PCIECAPABILITYSLOTIMPL : boolean := FALSE; PCIEREVISION : integer := 1; PMBASEPTR : bit_vector := X"040"; PMCAPABILITYAUXCURRENT : bit_vector := X"0"; PMCAPABILITYD1SUPPORT : boolean := FALSE; PMCAPABILITYD2SUPPORT : boolean := FALSE; PMCAPABILITYDSI : boolean := TRUE; PMCAPABILITYNEXTPTR : bit_vector := X"60"; PMCAPABILITYPMESUPPORT : bit_vector := X"00"; PMDATA0 : bit_vector := X"00"; PMDATA1 : bit_vector := X"00"; PMDATA2 : bit_vector := X"00"; PMDATA3 : bit_vector := X"00"; PMDATA4 : bit_vector := X"00"; PMDATA5 : bit_vector := X"00"; PMDATA6 : bit_vector := X"00"; PMDATA7 : bit_vector := X"00"; PMDATA8 : bit_vector := X"00"; PMDATASCALE0 : integer := 0; PMDATASCALE1 : integer := 0; PMDATASCALE2 : integer := 0; PMDATASCALE3 : integer := 0; PMDATASCALE4 : integer := 0; PMDATASCALE5 : integer := 0; PMDATASCALE6 : integer := 0; PMDATASCALE7 : integer := 0; PMDATASCALE8 : integer := 0; PMSTATUSCONTROLDATASCALE : bit_vector := X"0"; PORTVCCAPABILITYEXTENDEDVCCOUNT : bit_vector := X"0"; PORTVCCAPABILITYVCARBCAP : bit_vector := X"00"; PORTVCCAPABILITYVCARBTABLEOFFSET : bit_vector := X"00"; RAMSHARETXRX : boolean := FALSE; RESETMODE : boolean := FALSE; RETRYRAMREADLATENCY : integer := 3; RETRYRAMSIZE : bit_vector := X"009"; RETRYRAMWIDTH : integer := 0; RETRYRAMWRITELATENCY : integer := 1; RETRYREADADDRPIPE : boolean := FALSE; RETRYREADDATAPIPE : boolean := FALSE; RETRYWRITEPIPE : boolean := FALSE; REVISIONID : bit_vector := X"00"; RXREADADDRPIPE : boolean := FALSE; RXREADDATAPIPE : boolean := FALSE; RXWRITEPIPE : boolean := FALSE; SELECTASMODE : boolean := FALSE; SELECTDLLIF : boolean := FALSE; SLOTCAPABILITYATTBUTTONPRESENT : boolean := FALSE; SLOTCAPABILITYATTINDICATORPRESENT : boolean := FALSE; SLOTCAPABILITYHOTPLUGCAPABLE : boolean := FALSE; SLOTCAPABILITYHOTPLUGSURPRISE : boolean := FALSE; SLOTCAPABILITYMSLSENSORPRESENT : boolean := FALSE; SLOTCAPABILITYPHYSICALSLOTNUM : bit_vector := X"0000"; SLOTCAPABILITYPOWERCONTROLLERPRESENT : boolean := FALSE; SLOTCAPABILITYPOWERINDICATORPRESENT : boolean := FALSE; SLOTCAPABILITYSLOTPOWERLIMITSCALE : bit_vector := X"0"; SLOTCAPABILITYSLOTPOWERLIMITVALUE : bit_vector := X"00"; SLOTIMPLEMENTED : boolean := FALSE; SUBSYSTEMID : bit_vector := X"5050"; SUBSYSTEMVENDORID : bit_vector := X"10EE"; TLRAMREADLATENCY : integer := 3; TLRAMWIDTH : integer := 0; TLRAMWRITELATENCY : integer := 1; TXREADADDRPIPE : boolean := FALSE; TXREADDATAPIPE : boolean := FALSE; TXTSNFTS : integer := 255; TXTSNFTSCOMCLK : integer := 255; TXWRITEPIPE : boolean := FALSE; UPSTREAMFACING : boolean := TRUE; VC0RXFIFOBASEC : bit_vector := X"0098"; VC0RXFIFOBASENP : bit_vector := X"0080"; VC0RXFIFOBASEP : bit_vector := X"0000"; VC0RXFIFOLIMITC : bit_vector := X"0117"; VC0RXFIFOLIMITNP : bit_vector := X"0097"; VC0RXFIFOLIMITP : bit_vector := X"007f"; VC0TOTALCREDITSCD : bit_vector := X"000"; VC0TOTALCREDITSCH : bit_vector := X"00"; VC0TOTALCREDITSNPH : bit_vector := X"08"; VC0TOTALCREDITSPD : bit_vector := X"034"; VC0TOTALCREDITSPH : bit_vector := X"08"; VC0TXFIFOBASEC : bit_vector := X"0098"; VC0TXFIFOBASENP : bit_vector := X"0080"; VC0TXFIFOBASEP : bit_vector := X"0000"; VC0TXFIFOLIMITC : bit_vector := X"0117"; VC0TXFIFOLIMITNP : bit_vector := X"0097"; VC0TXFIFOLIMITP : bit_vector := X"007f"; VC1RXFIFOBASEC : bit_vector := X"0118"; VC1RXFIFOBASENP : bit_vector := X"0118"; VC1RXFIFOBASEP : bit_vector := X"0118"; VC1RXFIFOLIMITC : bit_vector := X"0118"; VC1RXFIFOLIMITNP : bit_vector := X"0118"; VC1RXFIFOLIMITP : bit_vector := X"0118"; VC1TOTALCREDITSCD : bit_vector := X"000"; VC1TOTALCREDITSCH : bit_vector := X"00"; VC1TOTALCREDITSNPH : bit_vector := X"00"; VC1TOTALCREDITSPD : bit_vector := X"000"; VC1TOTALCREDITSPH : bit_vector := X"00"; VC1TXFIFOBASEC : bit_vector := X"0118"; VC1TXFIFOBASENP : bit_vector := X"0118"; VC1TXFIFOBASEP : bit_vector := X"0118"; VC1TXFIFOLIMITC : bit_vector := X"0118"; VC1TXFIFOLIMITNP : bit_vector := X"0118"; VC1TXFIFOLIMITP : bit_vector := X"0118"; VCBASEPTR : bit_vector := X"154"; VCCAPABILITYNEXTPTR : bit_vector := X"000"; VENDORID : bit_vector := X"10EE"; XLINKSUPPORTED : boolean := FALSE; XPBASEPTR : bit_vector := X"60"; XPDEVICEPORTTYPE : bit_vector := X"0"; XPMAXPAYLOAD : integer := 0; XPRCBCONTROL : integer := 0 ); port ( BUSMASTERENABLE : out std_ulogic; CRMDOHOTRESETN : out std_ulogic; CRMPWRSOFTRESETN : out std_ulogic; CRMRXHOTRESETN : out std_ulogic; DLLTXPMDLLPOUTSTANDING : out std_ulogic; INTERRUPTDISABLE : out std_ulogic; IOSPACEENABLE : out std_ulogic; L0ASAUTONOMOUSINITCOMPLETED : out std_ulogic; L0ATTENTIONINDICATORCONTROL : out std_logic_vector(1 downto 0); L0CFGLOOPBACKACK : out std_ulogic; L0COMPLETERID : out std_logic_vector(12 downto 0); L0CORRERRMSGRCVD : out std_ulogic; L0DLLASRXSTATE : out std_logic_vector(1 downto 0); L0DLLASTXSTATE : out std_ulogic; L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); L0DLLRXACKOUTSTANDING : out std_ulogic; L0DLLTXNONFCOUTSTANDING : out std_ulogic; L0DLLTXOUTSTANDING : out std_ulogic; L0DLLVCSTATUS : out std_logic_vector(7 downto 0); L0DLUPDOWN : out std_logic_vector(7 downto 0); L0ERRMSGREQID : out std_logic_vector(15 downto 0); L0FATALERRMSGRCVD : out std_ulogic; L0FIRSTCFGWRITEOCCURRED : out std_ulogic; L0FWDCORRERROUT : out std_ulogic; L0FWDFATALERROUT : out std_ulogic; L0FWDNONFATALERROUT : out std_ulogic; L0LTSSMSTATE : out std_logic_vector(3 downto 0); L0MACENTEREDL0 : out std_ulogic; L0MACLINKTRAINING : out std_ulogic; L0MACLINKUP : out std_ulogic; L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); L0MACNEWSTATEACK : out std_ulogic; L0MACRXL0SSTATE : out std_ulogic; L0MACUPSTREAMDOWNSTREAM : out std_ulogic; L0MCFOUND : out std_logic_vector(2 downto 0); L0MSIENABLE0 : out std_ulogic; L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); L0NONFATALERRMSGRCVD : out std_ulogic; L0PMEACK : out std_ulogic; L0PMEEN : out std_ulogic; L0PMEREQOUT : out std_ulogic; L0POWERCONTROLLERCONTROL : out std_ulogic; L0POWERINDICATORCONTROL : out std_logic_vector(1 downto 0); L0PWRINHIBITTRANSFERS : out std_ulogic; L0PWRL1STATE : out std_ulogic; L0PWRL23READYDEVICE : out std_ulogic; L0PWRL23READYSTATE : out std_ulogic; L0PWRSTATE0 : out std_logic_vector(1 downto 0); L0PWRTURNOFFREQ : out std_ulogic; L0PWRTXL0SSTATE : out std_ulogic; L0RECEIVEDASSERTINTALEGACYINT : out std_ulogic; L0RECEIVEDASSERTINTBLEGACYINT : out std_ulogic; L0RECEIVEDASSERTINTCLEGACYINT : out std_ulogic; L0RECEIVEDASSERTINTDLEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTALEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTBLEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTCLEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTDLEGACYINT : out std_ulogic; L0RXBEACON : out std_ulogic; L0RXDLLFCCMPLMCCRED : out std_logic_vector(23 downto 0); L0RXDLLFCCMPLMCUPDATE : out std_logic_vector(7 downto 0); L0RXDLLFCNPOSTBYPCRED : out std_logic_vector(19 downto 0); L0RXDLLFCNPOSTBYPUPDATE : out std_logic_vector(7 downto 0); L0RXDLLFCPOSTORDCRED : out std_logic_vector(23 downto 0); L0RXDLLFCPOSTORDUPDATE : out std_logic_vector(7 downto 0); L0RXDLLPM : out std_ulogic; L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); L0RXDLLSBFCDATA : out std_logic_vector(18 downto 0); L0RXDLLSBFCUPDATE : out std_ulogic; L0RXDLLTLPECRCOK : out std_ulogic; L0RXDLLTLPEND : out std_logic_vector(1 downto 0); L0RXMACLINKERROR : out std_logic_vector(1 downto 0); L0STATSCFGOTHERRECEIVED : out std_ulogic; L0STATSCFGOTHERTRANSMITTED : out std_ulogic; L0STATSCFGRECEIVED : out std_ulogic; L0STATSCFGTRANSMITTED : out std_ulogic; L0STATSDLLPRECEIVED : out std_ulogic; L0STATSDLLPTRANSMITTED : out std_ulogic; L0STATSOSRECEIVED : out std_ulogic; L0STATSOSTRANSMITTED : out std_ulogic; L0STATSTLPRECEIVED : out std_ulogic; L0STATSTLPTRANSMITTED : out std_ulogic; L0TOGGLEELECTROMECHANICALINTERLOCK : out std_ulogic; L0TRANSFORMEDVC : out std_logic_vector(2 downto 0); L0TXDLLFCCMPLMCUPDATED : out std_logic_vector(7 downto 0); L0TXDLLFCNPOSTBYPUPDATED : out std_logic_vector(7 downto 0); L0TXDLLFCPOSTORDUPDATED : out std_logic_vector(7 downto 0); L0TXDLLPMUPDATED : out std_ulogic; L0TXDLLSBFCUPDATED : out std_ulogic; L0UCBYPFOUND : out std_logic_vector(3 downto 0); L0UCORDFOUND : out std_logic_vector(3 downto 0); L0UNLOCKRECEIVED : out std_ulogic; LLKRX4DWHEADERN : out std_ulogic; LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXCHCOMPLETIONPARTIALN : out std_logic_vector(7 downto 0); LLKRXCHCONFIGAVAILABLEN : out std_ulogic; LLKRXCHCONFIGPARTIALN : out std_ulogic; LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXCHNONPOSTEDPARTIALN : out std_logic_vector(7 downto 0); LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXCHPOSTEDPARTIALN : out std_logic_vector(7 downto 0); LLKRXDATA : out std_logic_vector(63 downto 0); LLKRXECRCBADN : out std_ulogic; LLKRXEOFN : out std_ulogic; LLKRXEOPN : out std_ulogic; LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); LLKRXSOFN : out std_ulogic; LLKRXSOPN : out std_ulogic; LLKRXSRCDSCN : out std_ulogic; LLKRXSRCLASTREQN : out std_ulogic; LLKRXSRCRDYN : out std_ulogic; LLKRXVALIDN : out std_logic_vector(1 downto 0); LLKTCSTATUS : out std_logic_vector(7 downto 0); LLKTXCHANSPACE : out std_logic_vector(9 downto 0); LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); LLKTXCONFIGREADYN : out std_ulogic; LLKTXDSTRDYN : out std_ulogic; MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); MEMSPACEENABLE : out std_ulogic; MGMTPSO : out std_logic_vector(16 downto 0); MGMTRDATA : out std_logic_vector(31 downto 0); MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); MIMDLLBRADD : out std_logic_vector(11 downto 0); MIMDLLBREN : out std_ulogic; MIMDLLBWADD : out std_logic_vector(11 downto 0); MIMDLLBWDATA : out std_logic_vector(63 downto 0); MIMDLLBWEN : out std_ulogic; MIMRXBRADD : out std_logic_vector(12 downto 0); MIMRXBREN : out std_ulogic; MIMRXBWADD : out std_logic_vector(12 downto 0); MIMRXBWDATA : out std_logic_vector(63 downto 0); MIMRXBWEN : out std_ulogic; MIMTXBRADD : out std_logic_vector(12 downto 0); MIMTXBREN : out std_ulogic; MIMTXBWADD : out std_logic_vector(12 downto 0); MIMTXBWDATA : out std_logic_vector(63 downto 0); MIMTXBWEN : out std_ulogic; PARITYERRORRESPONSE : out std_ulogic; PIPEDESKEWLANESL0 : out std_ulogic; PIPEDESKEWLANESL1 : out std_ulogic; PIPEDESKEWLANESL2 : out std_ulogic; PIPEDESKEWLANESL3 : out std_ulogic; PIPEDESKEWLANESL4 : out std_ulogic; PIPEDESKEWLANESL5 : out std_ulogic; PIPEDESKEWLANESL6 : out std_ulogic; PIPEDESKEWLANESL7 : out std_ulogic; PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); PIPERESETL0 : out std_ulogic; PIPERESETL1 : out std_ulogic; PIPERESETL2 : out std_ulogic; PIPERESETL3 : out std_ulogic; PIPERESETL4 : out std_ulogic; PIPERESETL5 : out std_ulogic; PIPERESETL6 : out std_ulogic; PIPERESETL7 : out std_ulogic; PIPERXPOLARITYL0 : out std_ulogic; PIPERXPOLARITYL1 : out std_ulogic; PIPERXPOLARITYL2 : out std_ulogic; PIPERXPOLARITYL3 : out std_ulogic; PIPERXPOLARITYL4 : out std_ulogic; PIPERXPOLARITYL5 : out std_ulogic; PIPERXPOLARITYL6 : out std_ulogic; PIPERXPOLARITYL7 : out std_ulogic; PIPETXCOMPLIANCEL0 : out std_ulogic; PIPETXCOMPLIANCEL1 : out std_ulogic; PIPETXCOMPLIANCEL2 : out std_ulogic; PIPETXCOMPLIANCEL3 : out std_ulogic; PIPETXCOMPLIANCEL4 : out std_ulogic; PIPETXCOMPLIANCEL5 : out std_ulogic; PIPETXCOMPLIANCEL6 : out std_ulogic; PIPETXCOMPLIANCEL7 : out std_ulogic; PIPETXDATAKL0 : out std_ulogic; PIPETXDATAKL1 : out std_ulogic; PIPETXDATAKL2 : out std_ulogic; PIPETXDATAKL3 : out std_ulogic; PIPETXDATAKL4 : out std_ulogic; PIPETXDATAKL5 : out std_ulogic; PIPETXDATAKL6 : out std_ulogic; PIPETXDATAKL7 : out std_ulogic; PIPETXDATAL0 : out std_logic_vector(7 downto 0); PIPETXDATAL1 : out std_logic_vector(7 downto 0); PIPETXDATAL2 : out std_logic_vector(7 downto 0); PIPETXDATAL3 : out std_logic_vector(7 downto 0); PIPETXDATAL4 : out std_logic_vector(7 downto 0); PIPETXDATAL5 : out std_logic_vector(7 downto 0); PIPETXDATAL6 : out std_logic_vector(7 downto 0); PIPETXDATAL7 : out std_logic_vector(7 downto 0); PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; PIPETXELECIDLEL0 : out std_ulogic; PIPETXELECIDLEL1 : out std_ulogic; PIPETXELECIDLEL2 : out std_ulogic; PIPETXELECIDLEL3 : out std_ulogic; PIPETXELECIDLEL4 : out std_ulogic; PIPETXELECIDLEL5 : out std_ulogic; PIPETXELECIDLEL6 : out std_ulogic; PIPETXELECIDLEL7 : out std_ulogic; SERRENABLE : out std_ulogic; URREPORTINGENABLE : out std_ulogic; AUXPOWER : in std_ulogic; CFGNEGOTIATEDLINKWIDTH : in std_logic_vector(5 downto 0); COMPLIANCEAVOID : in std_ulogic; CRMCFGBRIDGEHOTRESET : in std_ulogic; CRMCORECLK : in std_ulogic; CRMCORECLKDLO : in std_ulogic; CRMCORECLKRXO : in std_ulogic; CRMCORECLKTXO : in std_ulogic; CRMLINKRSTN : in std_ulogic; CRMMACRSTN : in std_ulogic; CRMMGMTRSTN : in std_ulogic; CRMNVRSTN : in std_ulogic; CRMTXHOTRESETN : in std_ulogic; CRMURSTN : in std_ulogic; CRMUSERCFGRSTN : in std_ulogic; CRMUSERCLK : in std_ulogic; CRMUSERCLKRXO : in std_ulogic; CRMUSERCLKTXO : in std_ulogic; CROSSLINKSEED : in std_ulogic; L0ACKNAKTIMERADJUSTMENT : in std_logic_vector(11 downto 0); L0ALLDOWNPORTSINL1 : in std_ulogic; L0ALLDOWNRXPORTSINL0S : in std_ulogic; L0ASE : in std_ulogic; L0ASPORTCOUNT : in std_logic_vector(7 downto 0); L0ASTURNPOOLBITSCONSUMED : in std_logic_vector(2 downto 0); L0ATTENTIONBUTTONPRESSED : in std_ulogic; L0CFGASSPANTREEOWNEDSTATE : in std_ulogic; L0CFGASSTATECHANGECMD : in std_logic_vector(3 downto 0); L0CFGDISABLESCRAMBLE : in std_ulogic; L0CFGEXTENDEDSYNC : in std_ulogic; L0CFGL0SENTRYENABLE : in std_ulogic; L0CFGL0SENTRYSUP : in std_ulogic; L0CFGL0SEXITLAT : in std_logic_vector(2 downto 0); L0CFGLINKDISABLE : in std_ulogic; L0CFGLOOPBACKMASTER : in std_ulogic; L0CFGNEGOTIATEDMAXP : in std_logic_vector(2 downto 0); L0CFGVCENABLE : in std_logic_vector(7 downto 0); L0CFGVCID : in std_logic_vector(23 downto 0); L0DLLHOLDLINKUP : in std_ulogic; L0ELECTROMECHANICALINTERLOCKENGAGED : in std_ulogic; L0FWDASSERTINTALEGACYINT : in std_ulogic; L0FWDASSERTINTBLEGACYINT : in std_ulogic; L0FWDASSERTINTCLEGACYINT : in std_ulogic; L0FWDASSERTINTDLEGACYINT : in std_ulogic; L0FWDCORRERRIN : in std_ulogic; L0FWDDEASSERTINTALEGACYINT : in std_ulogic; L0FWDDEASSERTINTBLEGACYINT : in std_ulogic; L0FWDDEASSERTINTCLEGACYINT : in std_ulogic; L0FWDDEASSERTINTDLEGACYINT : in std_ulogic; L0FWDFATALERRIN : in std_ulogic; L0FWDNONFATALERRIN : in std_ulogic; L0LEGACYINTFUNCT0 : in std_ulogic; L0MRLSENSORCLOSEDN : in std_ulogic; L0MSIREQUEST0 : in std_logic_vector(3 downto 0); L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); L0PMEREQIN : in std_ulogic; L0PORTNUMBER : in std_logic_vector(7 downto 0); L0POWERFAULTDETECTED : in std_ulogic; L0PRESENCEDETECTSLOTEMPTYN : in std_ulogic; L0PWRNEWSTATEREQ : in std_ulogic; L0PWRNEXTLINKSTATE : in std_logic_vector(1 downto 0); L0REPLAYTIMERADJUSTMENT : in std_logic_vector(11 downto 0); L0ROOTTURNOFFREQ : in std_ulogic; L0RXTLTLPNONINITIALIZEDVC : in std_logic_vector(7 downto 0); L0SENDUNLOCKMESSAGE : in std_ulogic; L0SETCOMPLETERABORTERROR : in std_ulogic; L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; L0SETDETECTEDCORRERROR : in std_ulogic; L0SETDETECTEDFATALERROR : in std_ulogic; L0SETDETECTEDNONFATALERROR : in std_ulogic; L0SETLINKDETECTEDPARITYERROR : in std_ulogic; L0SETLINKMASTERDATAPARITY : in std_ulogic; L0SETLINKRECEIVEDMASTERABORT : in std_ulogic; L0SETLINKRECEIVEDTARGETABORT : in std_ulogic; L0SETLINKSIGNALLEDTARGETABORT : in std_ulogic; L0SETLINKSYSTEMERROR : in std_ulogic; L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; L0SETUSERDETECTEDPARITYERROR : in std_ulogic; L0SETUSERMASTERDATAPARITY : in std_ulogic; L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; L0SETUSERSYSTEMERROR : in std_ulogic; L0TLASFCCREDSTARVATION : in std_ulogic; L0TLLINKRETRAIN : in std_ulogic; L0TRANSACTIONSPENDING : in std_ulogic; L0TXBEACON : in std_ulogic; L0TXCFGPM : in std_ulogic; L0TXCFGPMTYPE : in std_logic_vector(2 downto 0); L0TXTLFCCMPLMCCRED : in std_logic_vector(159 downto 0); L0TXTLFCCMPLMCUPDATE : in std_logic_vector(15 downto 0); L0TXTLFCNPOSTBYPCRED : in std_logic_vector(191 downto 0); L0TXTLFCNPOSTBYPUPDATE : in std_logic_vector(15 downto 0); L0TXTLFCPOSTORDCRED : in std_logic_vector(159 downto 0); L0TXTLFCPOSTORDUPDATE : in std_logic_vector(15 downto 0); L0TXTLSBFCDATA : in std_logic_vector(18 downto 0); L0TXTLSBFCUPDATE : in std_ulogic; L0TXTLTLPDATA : in std_logic_vector(63 downto 0); L0TXTLTLPEDB : in std_ulogic; L0TXTLTLPENABLE : in std_logic_vector(1 downto 0); L0TXTLTLPEND : in std_logic_vector(1 downto 0); L0TXTLTLPLATENCY : in std_logic_vector(3 downto 0); L0TXTLTLPREQ : in std_ulogic; L0TXTLTLPREQEND : in std_ulogic; L0TXTLTLPWIDTH : in std_ulogic; L0UPSTREAMRXPORTINL0S : in std_ulogic; L0VC0PREVIEWEXPAND : in std_ulogic; L0WAKEN : in std_ulogic; LLKRXCHFIFO : in std_logic_vector(1 downto 0); LLKRXCHTC : in std_logic_vector(2 downto 0); LLKRXDSTCONTREQN : in std_ulogic; LLKRXDSTREQN : in std_ulogic; LLKTX4DWHEADERN : in std_ulogic; LLKTXCHFIFO : in std_logic_vector(1 downto 0); LLKTXCHTC : in std_logic_vector(2 downto 0); LLKTXCOMPLETEN : in std_ulogic; LLKTXCREATEECRCN : in std_ulogic; LLKTXDATA : in std_logic_vector(63 downto 0); LLKTXENABLEN : in std_logic_vector(1 downto 0); LLKTXEOFN : in std_ulogic; LLKTXEOPN : in std_ulogic; LLKTXSOFN : in std_ulogic; LLKTXSOPN : in std_ulogic; LLKTXSRCDSCN : in std_ulogic; LLKTXSRCRDYN : in std_ulogic; MAINPOWER : in std_ulogic; MGMTADDR : in std_logic_vector(10 downto 0); MGMTBWREN : in std_logic_vector(3 downto 0); MGMTRDEN : in std_ulogic; MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); MGMTWDATA : in std_logic_vector(31 downto 0); MGMTWREN : in std_ulogic; MIMDLLBRDATA : in std_logic_vector(63 downto 0); MIMRXBRDATA : in std_logic_vector(63 downto 0); MIMTXBRDATA : in std_logic_vector(63 downto 0); PIPEPHYSTATUSL0 : in std_ulogic; PIPEPHYSTATUSL1 : in std_ulogic; PIPEPHYSTATUSL2 : in std_ulogic; PIPEPHYSTATUSL3 : in std_ulogic; PIPEPHYSTATUSL4 : in std_ulogic; PIPEPHYSTATUSL5 : in std_ulogic; PIPEPHYSTATUSL6 : in std_ulogic; PIPEPHYSTATUSL7 : in std_ulogic; PIPERXCHANISALIGNEDL0 : in std_ulogic; PIPERXCHANISALIGNEDL1 : in std_ulogic; PIPERXCHANISALIGNEDL2 : in std_ulogic; PIPERXCHANISALIGNEDL3 : in std_ulogic; PIPERXCHANISALIGNEDL4 : in std_ulogic; PIPERXCHANISALIGNEDL5 : in std_ulogic; PIPERXCHANISALIGNEDL6 : in std_ulogic; PIPERXCHANISALIGNEDL7 : in std_ulogic; PIPERXDATAKL0 : in std_ulogic; PIPERXDATAKL1 : in std_ulogic; PIPERXDATAKL2 : in std_ulogic; PIPERXDATAKL3 : in std_ulogic; PIPERXDATAKL4 : in std_ulogic; PIPERXDATAKL5 : in std_ulogic; PIPERXDATAKL6 : in std_ulogic; PIPERXDATAKL7 : in std_ulogic; PIPERXDATAL0 : in std_logic_vector(7 downto 0); PIPERXDATAL1 : in std_logic_vector(7 downto 0); PIPERXDATAL2 : in std_logic_vector(7 downto 0); PIPERXDATAL3 : in std_logic_vector(7 downto 0); PIPERXDATAL4 : in std_logic_vector(7 downto 0); PIPERXDATAL5 : in std_logic_vector(7 downto 0); PIPERXDATAL6 : in std_logic_vector(7 downto 0); PIPERXDATAL7 : in std_logic_vector(7 downto 0); PIPERXELECIDLEL0 : in std_ulogic; PIPERXELECIDLEL1 : in std_ulogic; PIPERXELECIDLEL2 : in std_ulogic; PIPERXELECIDLEL3 : in std_ulogic; PIPERXELECIDLEL4 : in std_ulogic; PIPERXELECIDLEL5 : in std_ulogic; PIPERXELECIDLEL6 : in std_ulogic; PIPERXELECIDLEL7 : in std_ulogic; PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); PIPERXVALIDL0 : in std_ulogic; PIPERXVALIDL1 : in std_ulogic; PIPERXVALIDL2 : in std_ulogic; PIPERXVALIDL3 : in std_ulogic; PIPERXVALIDL4 : in std_ulogic; PIPERXVALIDL5 : in std_ulogic; PIPERXVALIDL6 : in std_ulogic; PIPERXVALIDL7 : in std_ulogic ); end PCIE_INTERNAL_1_1; architecture PCIE_INTERNAL_1_1_V of PCIE_INTERNAL_1_1 is component PCIE_INTERNAL_1_1_SWIFT port ( BUSMASTERENABLE : out std_ulogic; CRMDOHOTRESETN : out std_ulogic; CRMPWRSOFTRESETN : out std_ulogic; CRMRXHOTRESETN : out std_ulogic; DLLTXPMDLLPOUTSTANDING : out std_ulogic; INTERRUPTDISABLE : out std_ulogic; IOSPACEENABLE : out std_ulogic; L0ASAUTONOMOUSINITCOMPLETED : out std_ulogic; L0ATTENTIONINDICATORCONTROL : out std_logic_vector(1 downto 0); L0CFGLOOPBACKACK : out std_ulogic; L0COMPLETERID : out std_logic_vector(12 downto 0); L0CORRERRMSGRCVD : out std_ulogic; L0DLLASRXSTATE : out std_logic_vector(1 downto 0); L0DLLASTXSTATE : out std_ulogic; L0DLLERRORVECTOR : out std_logic_vector(6 downto 0); L0DLLRXACKOUTSTANDING : out std_ulogic; L0DLLTXNONFCOUTSTANDING : out std_ulogic; L0DLLTXOUTSTANDING : out std_ulogic; L0DLLVCSTATUS : out std_logic_vector(7 downto 0); L0DLUPDOWN : out std_logic_vector(7 downto 0); L0ERRMSGREQID : out std_logic_vector(15 downto 0); L0FATALERRMSGRCVD : out std_ulogic; L0FIRSTCFGWRITEOCCURRED : out std_ulogic; L0FWDCORRERROUT : out std_ulogic; L0FWDFATALERROUT : out std_ulogic; L0FWDNONFATALERROUT : out std_ulogic; L0LTSSMSTATE : out std_logic_vector(3 downto 0); L0MACENTEREDL0 : out std_ulogic; L0MACLINKTRAINING : out std_ulogic; L0MACLINKUP : out std_ulogic; L0MACNEGOTIATEDLINKWIDTH : out std_logic_vector(3 downto 0); L0MACNEWSTATEACK : out std_ulogic; L0MACRXL0SSTATE : out std_ulogic; L0MACUPSTREAMDOWNSTREAM : out std_ulogic; L0MCFOUND : out std_logic_vector(2 downto 0); L0MSIENABLE0 : out std_ulogic; L0MULTIMSGEN0 : out std_logic_vector(2 downto 0); L0NONFATALERRMSGRCVD : out std_ulogic; L0PMEACK : out std_ulogic; L0PMEEN : out std_ulogic; L0PMEREQOUT : out std_ulogic; L0POWERCONTROLLERCONTROL : out std_ulogic; L0POWERINDICATORCONTROL : out std_logic_vector(1 downto 0); L0PWRINHIBITTRANSFERS : out std_ulogic; L0PWRL1STATE : out std_ulogic; L0PWRL23READYDEVICE : out std_ulogic; L0PWRL23READYSTATE : out std_ulogic; L0PWRSTATE0 : out std_logic_vector(1 downto 0); L0PWRTURNOFFREQ : out std_ulogic; L0PWRTXL0SSTATE : out std_ulogic; L0RECEIVEDASSERTINTALEGACYINT : out std_ulogic; L0RECEIVEDASSERTINTBLEGACYINT : out std_ulogic; L0RECEIVEDASSERTINTCLEGACYINT : out std_ulogic; L0RECEIVEDASSERTINTDLEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTALEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTBLEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTCLEGACYINT : out std_ulogic; L0RECEIVEDDEASSERTINTDLEGACYINT : out std_ulogic; L0RXBEACON : out std_ulogic; L0RXDLLFCCMPLMCCRED : out std_logic_vector(23 downto 0); L0RXDLLFCCMPLMCUPDATE : out std_logic_vector(7 downto 0); L0RXDLLFCNPOSTBYPCRED : out std_logic_vector(19 downto 0); L0RXDLLFCNPOSTBYPUPDATE : out std_logic_vector(7 downto 0); L0RXDLLFCPOSTORDCRED : out std_logic_vector(23 downto 0); L0RXDLLFCPOSTORDUPDATE : out std_logic_vector(7 downto 0); L0RXDLLPM : out std_ulogic; L0RXDLLPMTYPE : out std_logic_vector(2 downto 0); L0RXDLLSBFCDATA : out std_logic_vector(18 downto 0); L0RXDLLSBFCUPDATE : out std_ulogic; L0RXDLLTLPECRCOK : out std_ulogic; L0RXDLLTLPEND : out std_logic_vector(1 downto 0); L0RXMACLINKERROR : out std_logic_vector(1 downto 0); L0STATSCFGOTHERRECEIVED : out std_ulogic; L0STATSCFGOTHERTRANSMITTED : out std_ulogic; L0STATSCFGRECEIVED : out std_ulogic; L0STATSCFGTRANSMITTED : out std_ulogic; L0STATSDLLPRECEIVED : out std_ulogic; L0STATSDLLPTRANSMITTED : out std_ulogic; L0STATSOSRECEIVED : out std_ulogic; L0STATSOSTRANSMITTED : out std_ulogic; L0STATSTLPRECEIVED : out std_ulogic; L0STATSTLPTRANSMITTED : out std_ulogic; L0TOGGLEELECTROMECHANICALINTERLOCK : out std_ulogic; L0TRANSFORMEDVC : out std_logic_vector(2 downto 0); L0TXDLLFCCMPLMCUPDATED : out std_logic_vector(7 downto 0); L0TXDLLFCNPOSTBYPUPDATED : out std_logic_vector(7 downto 0); L0TXDLLFCPOSTORDUPDATED : out std_logic_vector(7 downto 0); L0TXDLLPMUPDATED : out std_ulogic; L0TXDLLSBFCUPDATED : out std_ulogic; L0UCBYPFOUND : out std_logic_vector(3 downto 0); L0UCORDFOUND : out std_logic_vector(3 downto 0); L0UNLOCKRECEIVED : out std_ulogic; LLKRX4DWHEADERN : out std_ulogic; LLKRXCHCOMPLETIONAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXCHCOMPLETIONPARTIALN : out std_logic_vector(7 downto 0); LLKRXCHCONFIGAVAILABLEN : out std_ulogic; LLKRXCHCONFIGPARTIALN : out std_ulogic; LLKRXCHNONPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXCHNONPOSTEDPARTIALN : out std_logic_vector(7 downto 0); LLKRXCHPOSTEDAVAILABLEN : out std_logic_vector(7 downto 0); LLKRXCHPOSTEDPARTIALN : out std_logic_vector(7 downto 0); LLKRXDATA : out std_logic_vector(63 downto 0); LLKRXECRCBADN : out std_ulogic; LLKRXEOFN : out std_ulogic; LLKRXEOPN : out std_ulogic; LLKRXPREFERREDTYPE : out std_logic_vector(15 downto 0); LLKRXSOFN : out std_ulogic; LLKRXSOPN : out std_ulogic; LLKRXSRCDSCN : out std_ulogic; LLKRXSRCLASTREQN : out std_ulogic; LLKRXSRCRDYN : out std_ulogic; LLKRXVALIDN : out std_logic_vector(1 downto 0); LLKTCSTATUS : out std_logic_vector(7 downto 0); LLKTXCHANSPACE : out std_logic_vector(9 downto 0); LLKTXCHCOMPLETIONREADYN : out std_logic_vector(7 downto 0); LLKTXCHNONPOSTEDREADYN : out std_logic_vector(7 downto 0); LLKTXCHPOSTEDREADYN : out std_logic_vector(7 downto 0); LLKTXCONFIGREADYN : out std_ulogic; LLKTXDSTRDYN : out std_ulogic; MAXPAYLOADSIZE : out std_logic_vector(2 downto 0); MAXREADREQUESTSIZE : out std_logic_vector(2 downto 0); MEMSPACEENABLE : out std_ulogic; MGMTPSO : out std_logic_vector(16 downto 0); MGMTRDATA : out std_logic_vector(31 downto 0); MGMTSTATSCREDIT : out std_logic_vector(11 downto 0); MIMDLLBRADD : out std_logic_vector(11 downto 0); MIMDLLBREN : out std_ulogic; MIMDLLBWADD : out std_logic_vector(11 downto 0); MIMDLLBWDATA : out std_logic_vector(63 downto 0); MIMDLLBWEN : out std_ulogic; MIMRXBRADD : out std_logic_vector(12 downto 0); MIMRXBREN : out std_ulogic; MIMRXBWADD : out std_logic_vector(12 downto 0); MIMRXBWDATA : out std_logic_vector(63 downto 0); MIMRXBWEN : out std_ulogic; MIMTXBRADD : out std_logic_vector(12 downto 0); MIMTXBREN : out std_ulogic; MIMTXBWADD : out std_logic_vector(12 downto 0); MIMTXBWDATA : out std_logic_vector(63 downto 0); MIMTXBWEN : out std_ulogic; PARITYERRORRESPONSE : out std_ulogic; PIPEDESKEWLANESL0 : out std_ulogic; PIPEDESKEWLANESL1 : out std_ulogic; PIPEDESKEWLANESL2 : out std_ulogic; PIPEDESKEWLANESL3 : out std_ulogic; PIPEDESKEWLANESL4 : out std_ulogic; PIPEDESKEWLANESL5 : out std_ulogic; PIPEDESKEWLANESL6 : out std_ulogic; PIPEDESKEWLANESL7 : out std_ulogic; PIPEPOWERDOWNL0 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL1 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL2 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL3 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL4 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL5 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL6 : out std_logic_vector(1 downto 0); PIPEPOWERDOWNL7 : out std_logic_vector(1 downto 0); PIPERESETL0 : out std_ulogic; PIPERESETL1 : out std_ulogic; PIPERESETL2 : out std_ulogic; PIPERESETL3 : out std_ulogic; PIPERESETL4 : out std_ulogic; PIPERESETL5 : out std_ulogic; PIPERESETL6 : out std_ulogic; PIPERESETL7 : out std_ulogic; PIPERXPOLARITYL0 : out std_ulogic; PIPERXPOLARITYL1 : out std_ulogic; PIPERXPOLARITYL2 : out std_ulogic; PIPERXPOLARITYL3 : out std_ulogic; PIPERXPOLARITYL4 : out std_ulogic; PIPERXPOLARITYL5 : out std_ulogic; PIPERXPOLARITYL6 : out std_ulogic; PIPERXPOLARITYL7 : out std_ulogic; PIPETXCOMPLIANCEL0 : out std_ulogic; PIPETXCOMPLIANCEL1 : out std_ulogic; PIPETXCOMPLIANCEL2 : out std_ulogic; PIPETXCOMPLIANCEL3 : out std_ulogic; PIPETXCOMPLIANCEL4 : out std_ulogic; PIPETXCOMPLIANCEL5 : out std_ulogic; PIPETXCOMPLIANCEL6 : out std_ulogic; PIPETXCOMPLIANCEL7 : out std_ulogic; PIPETXDATAKL0 : out std_ulogic; PIPETXDATAKL1 : out std_ulogic; PIPETXDATAKL2 : out std_ulogic; PIPETXDATAKL3 : out std_ulogic; PIPETXDATAKL4 : out std_ulogic; PIPETXDATAKL5 : out std_ulogic; PIPETXDATAKL6 : out std_ulogic; PIPETXDATAKL7 : out std_ulogic; PIPETXDATAL0 : out std_logic_vector(7 downto 0); PIPETXDATAL1 : out std_logic_vector(7 downto 0); PIPETXDATAL2 : out std_logic_vector(7 downto 0); PIPETXDATAL3 : out std_logic_vector(7 downto 0); PIPETXDATAL4 : out std_logic_vector(7 downto 0); PIPETXDATAL5 : out std_logic_vector(7 downto 0); PIPETXDATAL6 : out std_logic_vector(7 downto 0); PIPETXDATAL7 : out std_logic_vector(7 downto 0); PIPETXDETECTRXLOOPBACKL0 : out std_ulogic; PIPETXDETECTRXLOOPBACKL1 : out std_ulogic; PIPETXDETECTRXLOOPBACKL2 : out std_ulogic; PIPETXDETECTRXLOOPBACKL3 : out std_ulogic; PIPETXDETECTRXLOOPBACKL4 : out std_ulogic; PIPETXDETECTRXLOOPBACKL5 : out std_ulogic; PIPETXDETECTRXLOOPBACKL6 : out std_ulogic; PIPETXDETECTRXLOOPBACKL7 : out std_ulogic; PIPETXELECIDLEL0 : out std_ulogic; PIPETXELECIDLEL1 : out std_ulogic; PIPETXELECIDLEL2 : out std_ulogic; PIPETXELECIDLEL3 : out std_ulogic; PIPETXELECIDLEL4 : out std_ulogic; PIPETXELECIDLEL5 : out std_ulogic; PIPETXELECIDLEL6 : out std_ulogic; PIPETXELECIDLEL7 : out std_ulogic; SERRENABLE : out std_ulogic; URREPORTINGENABLE : out std_ulogic; AUXPOWER : in std_ulogic; CFGNEGOTIATEDLINKWIDTH : in std_logic_vector(5 downto 0); COMPLIANCEAVOID : in std_ulogic; CRMCFGBRIDGEHOTRESET : in std_ulogic; CRMCORECLK : in std_ulogic; CRMCORECLKDLO : in std_ulogic; CRMCORECLKRXO : in std_ulogic; CRMCORECLKTXO : in std_ulogic; CRMLINKRSTN : in std_ulogic; CRMMACRSTN : in std_ulogic; CRMMGMTRSTN : in std_ulogic; CRMNVRSTN : in std_ulogic; CRMTXHOTRESETN : in std_ulogic; CRMURSTN : in std_ulogic; CRMUSERCFGRSTN : in std_ulogic; CRMUSERCLK : in std_ulogic; CRMUSERCLKRXO : in std_ulogic; CRMUSERCLKTXO : in std_ulogic; CROSSLINKSEED : in std_ulogic; GSR : in std_ulogic; L0ACKNAKTIMERADJUSTMENT : in std_logic_vector(11 downto 0); L0ALLDOWNPORTSINL1 : in std_ulogic; L0ALLDOWNRXPORTSINL0S : in std_ulogic; L0ASE : in std_ulogic; L0ASPORTCOUNT : in std_logic_vector(7 downto 0); L0ASTURNPOOLBITSCONSUMED : in std_logic_vector(2 downto 0); L0ATTENTIONBUTTONPRESSED : in std_ulogic; L0CFGASSPANTREEOWNEDSTATE : in std_ulogic; L0CFGASSTATECHANGECMD : in std_logic_vector(3 downto 0); L0CFGDISABLESCRAMBLE : in std_ulogic; L0CFGEXTENDEDSYNC : in std_ulogic; L0CFGL0SENTRYENABLE : in std_ulogic; L0CFGL0SENTRYSUP : in std_ulogic; L0CFGL0SEXITLAT : in std_logic_vector(2 downto 0); L0CFGLINKDISABLE : in std_ulogic; L0CFGLOOPBACKMASTER : in std_ulogic; L0CFGNEGOTIATEDMAXP : in std_logic_vector(2 downto 0); L0CFGVCENABLE : in std_logic_vector(7 downto 0); L0CFGVCID : in std_logic_vector(23 downto 0); L0DLLHOLDLINKUP : in std_ulogic; L0ELECTROMECHANICALINTERLOCKENGAGED : in std_ulogic; L0FWDASSERTINTALEGACYINT : in std_ulogic; L0FWDASSERTINTBLEGACYINT : in std_ulogic; L0FWDASSERTINTCLEGACYINT : in std_ulogic; L0FWDASSERTINTDLEGACYINT : in std_ulogic; L0FWDCORRERRIN : in std_ulogic; L0FWDDEASSERTINTALEGACYINT : in std_ulogic; L0FWDDEASSERTINTBLEGACYINT : in std_ulogic; L0FWDDEASSERTINTCLEGACYINT : in std_ulogic; L0FWDDEASSERTINTDLEGACYINT : in std_ulogic; L0FWDFATALERRIN : in std_ulogic; L0FWDNONFATALERRIN : in std_ulogic; L0LEGACYINTFUNCT0 : in std_ulogic; L0MRLSENSORCLOSEDN : in std_ulogic; L0MSIREQUEST0 : in std_logic_vector(3 downto 0); L0PACKETHEADERFROMUSER : in std_logic_vector(127 downto 0); L0PMEREQIN : in std_ulogic; L0PORTNUMBER : in std_logic_vector(7 downto 0); L0POWERFAULTDETECTED : in std_ulogic; L0PRESENCEDETECTSLOTEMPTYN : in std_ulogic; L0PWRNEWSTATEREQ : in std_ulogic; L0PWRNEXTLINKSTATE : in std_logic_vector(1 downto 0); L0REPLAYTIMERADJUSTMENT : in std_logic_vector(11 downto 0); L0ROOTTURNOFFREQ : in std_ulogic; L0RXTLTLPNONINITIALIZEDVC : in std_logic_vector(7 downto 0); L0SENDUNLOCKMESSAGE : in std_ulogic; L0SETCOMPLETERABORTERROR : in std_ulogic; L0SETCOMPLETIONTIMEOUTCORRERROR : in std_ulogic; L0SETCOMPLETIONTIMEOUTUNCORRERROR : in std_ulogic; L0SETDETECTEDCORRERROR : in std_ulogic; L0SETDETECTEDFATALERROR : in std_ulogic; L0SETDETECTEDNONFATALERROR : in std_ulogic; L0SETLINKDETECTEDPARITYERROR : in std_ulogic; L0SETLINKMASTERDATAPARITY : in std_ulogic; L0SETLINKRECEIVEDMASTERABORT : in std_ulogic; L0SETLINKRECEIVEDTARGETABORT : in std_ulogic; L0SETLINKSIGNALLEDTARGETABORT : in std_ulogic; L0SETLINKSYSTEMERROR : in std_ulogic; L0SETUNEXPECTEDCOMPLETIONCORRERROR : in std_ulogic; L0SETUNEXPECTEDCOMPLETIONUNCORRERROR : in std_ulogic; L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR : in std_ulogic; L0SETUNSUPPORTEDREQUESTOTHERERROR : in std_ulogic; L0SETUSERDETECTEDPARITYERROR : in std_ulogic; L0SETUSERMASTERDATAPARITY : in std_ulogic; L0SETUSERRECEIVEDMASTERABORT : in std_ulogic; L0SETUSERRECEIVEDTARGETABORT : in std_ulogic; L0SETUSERSIGNALLEDTARGETABORT : in std_ulogic; L0SETUSERSYSTEMERROR : in std_ulogic; L0TLASFCCREDSTARVATION : in std_ulogic; L0TLLINKRETRAIN : in std_ulogic; L0TRANSACTIONSPENDING : in std_ulogic; L0TXBEACON : in std_ulogic; L0TXCFGPM : in std_ulogic; L0TXCFGPMTYPE : in std_logic_vector(2 downto 0); L0TXTLFCCMPLMCCRED : in std_logic_vector(159 downto 0); L0TXTLFCCMPLMCUPDATE : in std_logic_vector(15 downto 0); L0TXTLFCNPOSTBYPCRED : in std_logic_vector(191 downto 0); L0TXTLFCNPOSTBYPUPDATE : in std_logic_vector(15 downto 0); L0TXTLFCPOSTORDCRED : in std_logic_vector(159 downto 0); L0TXTLFCPOSTORDUPDATE : in std_logic_vector(15 downto 0); L0TXTLSBFCDATA : in std_logic_vector(18 downto 0); L0TXTLSBFCUPDATE : in std_ulogic; L0TXTLTLPDATA : in std_logic_vector(63 downto 0); L0TXTLTLPEDB : in std_ulogic; L0TXTLTLPENABLE : in std_logic_vector(1 downto 0); L0TXTLTLPEND : in std_logic_vector(1 downto 0); L0TXTLTLPLATENCY : in std_logic_vector(3 downto 0); L0TXTLTLPREQ : in std_ulogic; L0TXTLTLPREQEND : in std_ulogic; L0TXTLTLPWIDTH : in std_ulogic; L0UPSTREAMRXPORTINL0S : in std_ulogic; L0VC0PREVIEWEXPAND : in std_ulogic; L0WAKEN : in std_ulogic; LLKRXCHFIFO : in std_logic_vector(1 downto 0); LLKRXCHTC : in std_logic_vector(2 downto 0); LLKRXDSTCONTREQN : in std_ulogic; LLKRXDSTREQN : in std_ulogic; LLKTX4DWHEADERN : in std_ulogic; LLKTXCHFIFO : in std_logic_vector(1 downto 0); LLKTXCHTC : in std_logic_vector(2 downto 0); LLKTXCOMPLETEN : in std_ulogic; LLKTXCREATEECRCN : in std_ulogic; LLKTXDATA : in std_logic_vector(63 downto 0); LLKTXENABLEN : in std_logic_vector(1 downto 0); LLKTXEOFN : in std_ulogic; LLKTXEOPN : in std_ulogic; LLKTXSOFN : in std_ulogic; LLKTXSOPN : in std_ulogic; LLKTXSRCDSCN : in std_ulogic; LLKTXSRCRDYN : in std_ulogic; MAINPOWER : in std_ulogic; MGMTADDR : in std_logic_vector(10 downto 0); MGMTBWREN : in std_logic_vector(3 downto 0); MGMTRDEN : in std_ulogic; MGMTSTATSCREDITSEL : in std_logic_vector(6 downto 0); MGMTWDATA : in std_logic_vector(31 downto 0); MGMTWREN : in std_ulogic; MIMDLLBRDATA : in std_logic_vector(63 downto 0); MIMRXBRDATA : in std_logic_vector(63 downto 0); MIMTXBRDATA : in std_logic_vector(63 downto 0); PIPEPHYSTATUSL0 : in std_ulogic; PIPEPHYSTATUSL1 : in std_ulogic; PIPEPHYSTATUSL2 : in std_ulogic; PIPEPHYSTATUSL3 : in std_ulogic; PIPEPHYSTATUSL4 : in std_ulogic; PIPEPHYSTATUSL5 : in std_ulogic; PIPEPHYSTATUSL6 : in std_ulogic; PIPEPHYSTATUSL7 : in std_ulogic; PIPERXCHANISALIGNEDL0 : in std_ulogic; PIPERXCHANISALIGNEDL1 : in std_ulogic; PIPERXCHANISALIGNEDL2 : in std_ulogic; PIPERXCHANISALIGNEDL3 : in std_ulogic; PIPERXCHANISALIGNEDL4 : in std_ulogic; PIPERXCHANISALIGNEDL5 : in std_ulogic; PIPERXCHANISALIGNEDL6 : in std_ulogic; PIPERXCHANISALIGNEDL7 : in std_ulogic; PIPERXDATAKL0 : in std_ulogic; PIPERXDATAKL1 : in std_ulogic; PIPERXDATAKL2 : in std_ulogic; PIPERXDATAKL3 : in std_ulogic; PIPERXDATAKL4 : in std_ulogic; PIPERXDATAKL5 : in std_ulogic; PIPERXDATAKL6 : in std_ulogic; PIPERXDATAKL7 : in std_ulogic; PIPERXDATAL0 : in std_logic_vector(7 downto 0); PIPERXDATAL1 : in std_logic_vector(7 downto 0); PIPERXDATAL2 : in std_logic_vector(7 downto 0); PIPERXDATAL3 : in std_logic_vector(7 downto 0); PIPERXDATAL4 : in std_logic_vector(7 downto 0); PIPERXDATAL5 : in std_logic_vector(7 downto 0); PIPERXDATAL6 : in std_logic_vector(7 downto 0); PIPERXDATAL7 : in std_logic_vector(7 downto 0); PIPERXELECIDLEL0 : in std_ulogic; PIPERXELECIDLEL1 : in std_ulogic; PIPERXELECIDLEL2 : in std_ulogic; PIPERXELECIDLEL3 : in std_ulogic; PIPERXELECIDLEL4 : in std_ulogic; PIPERXELECIDLEL5 : in std_ulogic; PIPERXELECIDLEL6 : in std_ulogic; PIPERXELECIDLEL7 : in std_ulogic; PIPERXSTATUSL0 : in std_logic_vector(2 downto 0); PIPERXSTATUSL1 : in std_logic_vector(2 downto 0); PIPERXSTATUSL2 : in std_logic_vector(2 downto 0); PIPERXSTATUSL3 : in std_logic_vector(2 downto 0); PIPERXSTATUSL4 : in std_logic_vector(2 downto 0); PIPERXSTATUSL5 : in std_logic_vector(2 downto 0); PIPERXSTATUSL6 : in std_logic_vector(2 downto 0); PIPERXSTATUSL7 : in std_logic_vector(2 downto 0); PIPERXVALIDL0 : in std_ulogic; PIPERXVALIDL1 : in std_ulogic; PIPERXVALIDL2 : in std_ulogic; PIPERXVALIDL3 : in std_ulogic; PIPERXVALIDL4 : in std_ulogic; PIPERXVALIDL5 : in std_ulogic; PIPERXVALIDL6 : in std_ulogic; PIPERXVALIDL7 : in std_ulogic; MCACTIVELANESIN : in std_logic_vector(7 downto 0); MCAERBASEPTR : in std_logic_vector(11 downto 0); MCAERCAPABILITYECRCCHECKCAPABLE : in std_ulogic; MCAERCAPABILITYECRCGENCAPABLE : in std_ulogic; MCAERCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); MCBAR0ADDRWIDTH : in std_ulogic; MCBAR0EXIST : in std_ulogic; MCBAR0IOMEMN : in std_ulogic; MCBAR0MASKWIDTH : in std_logic_vector(5 downto 0); MCBAR0PREFETCHABLE : in std_ulogic; MCBAR1ADDRWIDTH : in std_ulogic; MCBAR1EXIST : in std_ulogic; MCBAR1IOMEMN : in std_ulogic; MCBAR1MASKWIDTH : in std_logic_vector(5 downto 0); MCBAR1PREFETCHABLE : in std_ulogic; MCBAR2ADDRWIDTH : in std_ulogic; MCBAR2EXIST : in std_ulogic; MCBAR2IOMEMN : in std_ulogic; MCBAR2MASKWIDTH : in std_logic_vector(5 downto 0); MCBAR2PREFETCHABLE : in std_ulogic; MCBAR3ADDRWIDTH : in std_ulogic; MCBAR3EXIST : in std_ulogic; MCBAR3IOMEMN : in std_ulogic; MCBAR3MASKWIDTH : in std_logic_vector(5 downto 0); MCBAR3PREFETCHABLE : in std_ulogic; MCBAR4ADDRWIDTH : in std_ulogic; MCBAR4EXIST : in std_ulogic; MCBAR4IOMEMN : in std_ulogic; MCBAR4MASKWIDTH : in std_logic_vector(5 downto 0); MCBAR4PREFETCHABLE : in std_ulogic; MCBAR5ADDRWIDTH : in std_ulogic; MCBAR5EXIST : in std_ulogic; MCBAR5IOMEMN : in std_ulogic; MCBAR5MASKWIDTH : in std_logic_vector(5 downto 0); MCBAR5PREFETCHABLE : in std_ulogic; MCCAPABILITIESPOINTER : in std_logic_vector(7 downto 0); MCCARDBUSCISPOINTER : in std_logic_vector(31 downto 0); MCCLASSCODE : in std_logic_vector(23 downto 0); -- MCCLKDIVIDED : in std_ulogic; MCCONFIGROUTING : in std_logic_vector(2 downto 0); MCDEVICECAPABILITYENDPOINTL0SLATENCY : in std_logic_vector(2 downto 0); MCDEVICECAPABILITYENDPOINTL1LATENCY : in std_logic_vector(2 downto 0); MCDEVICEID : in std_logic_vector(15 downto 0); MCDEVICESERIALNUMBER : in std_logic_vector(63 downto 0); MCDSNBASEPTR : in std_logic_vector(11 downto 0); MCDSNCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); MCDUALCOREENABLE : in std_ulogic; MCDUALCORESLAVE : in std_ulogic; MCDUALROLECFGCNTRLROOTEPN : in std_ulogic; MCEXTCFGCAPPTR : in std_logic_vector(7 downto 0); MCEXTCFGXPCAPPTR : in std_logic_vector(11 downto 0); MCHEADERTYPE : in std_logic_vector(7 downto 0); MCINFINITECOMPLETIONS : in std_ulogic; MCINTERRUPTPIN : in std_logic_vector(7 downto 0); MCISSWITCH : in std_ulogic; MCL0SEXITLATENCY : in std_logic_vector(2 downto 0); MCL0SEXITLATENCYCOMCLK : in std_logic_vector(2 downto 0); MCL1EXITLATENCY : in std_logic_vector(2 downto 0); MCL1EXITLATENCYCOMCLK : in std_logic_vector(2 downto 0); MCLINKCAPABILITYASPMSUPPORT : in std_logic_vector(1 downto 0); MCLINKCAPABILITYMAXLINKWIDTH : in std_logic_vector(5 downto 0); MCLINKSTATUSSLOTCLOCKCONFIG : in std_ulogic; MCLLKBYPASS : in std_ulogic; MCLOWPRIORITYVCCOUNT : in std_logic_vector(2 downto 0); MCMSIBASEPTR : in std_logic_vector(11 downto 0); MCMSICAPABILITYMULTIMSGCAP : in std_logic_vector(2 downto 0); MCMSICAPABILITYNEXTPTR : in std_logic_vector(7 downto 0); MCPBBASEPTR : in std_logic_vector(11 downto 0); MCPBCAPABILITYDW0BASEPOWER : in std_logic_vector(7 downto 0); MCPBCAPABILITYDW0DATASCALE : in std_logic_vector(1 downto 0); MCPBCAPABILITYDW0PMSTATE : in std_logic_vector(1 downto 0); MCPBCAPABILITYDW0PMSUBSTATE : in std_logic_vector(2 downto 0); MCPBCAPABILITYDW0POWERRAIL : in std_logic_vector(2 downto 0); MCPBCAPABILITYDW0TYPE : in std_logic_vector(2 downto 0); MCPBCAPABILITYDW1BASEPOWER : in std_logic_vector(7 downto 0); MCPBCAPABILITYDW1DATASCALE : in std_logic_vector(1 downto 0); MCPBCAPABILITYDW1PMSTATE : in std_logic_vector(1 downto 0); MCPBCAPABILITYDW1PMSUBSTATE : in std_logic_vector(2 downto 0); MCPBCAPABILITYDW1POWERRAIL : in std_logic_vector(2 downto 0); MCPBCAPABILITYDW1TYPE : in std_logic_vector(2 downto 0); MCPBCAPABILITYDW2BASEPOWER : in std_logic_vector(7 downto 0); MCPBCAPABILITYDW2DATASCALE : in std_logic_vector(1 downto 0); MCPBCAPABILITYDW2PMSTATE : in std_logic_vector(1 downto 0); MCPBCAPABILITYDW2PMSUBSTATE : in std_logic_vector(2 downto 0); MCPBCAPABILITYDW2POWERRAIL : in std_logic_vector(2 downto 0); MCPBCAPABILITYDW2TYPE : in std_logic_vector(2 downto 0); MCPBCAPABILITYDW3BASEPOWER : in std_logic_vector(7 downto 0); MCPBCAPABILITYDW3DATASCALE : in std_logic_vector(1 downto 0); MCPBCAPABILITYDW3PMSTATE : in std_logic_vector(1 downto 0); MCPBCAPABILITYDW3PMSUBSTATE : in std_logic_vector(2 downto 0); MCPBCAPABILITYDW3POWERRAIL : in std_logic_vector(2 downto 0); MCPBCAPABILITYDW3TYPE : in std_logic_vector(2 downto 0); MCPBCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); MCPBCAPABILITYSYSTEMALLOCATED : in std_ulogic; MCPCIECAPABILITYINTMSGNUM : in std_logic_vector(4 downto 0); MCPCIECAPABILITYNEXTPTR : in std_logic_vector(7 downto 0); MCPCIECAPABILITYSLOTIMPL : in std_ulogic; MCPCIEREVISION : in std_ulogic; MCPMBASEPTR : in std_logic_vector(11 downto 0); MCPMCAPABILITYAUXCURRENT : in std_logic_vector(2 downto 0); MCPMCAPABILITYD1SUPPORT : in std_ulogic; MCPMCAPABILITYD2SUPPORT : in std_ulogic; MCPMCAPABILITYDSI : in std_ulogic; MCPMCAPABILITYNEXTPTR : in std_logic_vector(7 downto 0); MCPMCAPABILITYPMESUPPORT : in std_logic_vector(4 downto 0); MCPMDATA0 : in std_logic_vector(7 downto 0); MCPMDATA1 : in std_logic_vector(7 downto 0); MCPMDATA2 : in std_logic_vector(7 downto 0); MCPMDATA3 : in std_logic_vector(7 downto 0); MCPMDATA4 : in std_logic_vector(7 downto 0); MCPMDATA5 : in std_logic_vector(7 downto 0); MCPMDATA6 : in std_logic_vector(7 downto 0); MCPMDATA7 : in std_logic_vector(7 downto 0); MCPMDATA8 : in std_logic_vector(7 downto 0); MCPMDATASCALE0 : in std_logic_vector(1 downto 0); MCPMDATASCALE1 : in std_logic_vector(1 downto 0); MCPMDATASCALE2 : in std_logic_vector(1 downto 0); MCPMDATASCALE3 : in std_logic_vector(1 downto 0); MCPMDATASCALE4 : in std_logic_vector(1 downto 0); MCPMDATASCALE5 : in std_logic_vector(1 downto 0); MCPMDATASCALE6 : in std_logic_vector(1 downto 0); MCPMDATASCALE7 : in std_logic_vector(1 downto 0); MCPMDATASCALE8 : in std_logic_vector(1 downto 0); MCPMSTATUSCONTROLDATASCALE : in std_logic_vector(1 downto 0); MCPORTVCCAPABILITYEXTENDEDVCCOUNT : in std_logic_vector(2 downto 0); MCPORTVCCAPABILITYVCARBCAP : in std_logic_vector(7 downto 0); MCPORTVCCAPABILITYVCARBTABLEOFFSET : in std_logic_vector(7 downto 0); MCRAMSHARETXRX : in std_ulogic; MCRESETMODE : in std_ulogic; MCRETRYRAMREADLATENCY : in std_logic_vector(2 downto 0); MCRETRYRAMSIZE : in std_logic_vector(11 downto 0); MCRETRYRAMWIDTH : in std_ulogic; MCRETRYRAMWRITELATENCY : in std_logic_vector(2 downto 0); MCRETRYREADADDRPIPE : in std_ulogic; MCRETRYREADDATAPIPE : in std_ulogic; MCRETRYWRITEPIPE : in std_ulogic; MCREVISIONID : in std_logic_vector(7 downto 0); MCRXREADADDRPIPE : in std_ulogic; MCRXREADDATAPIPE : in std_ulogic; MCRXWRITEPIPE : in std_ulogic; MCSELECTASMODE : in std_ulogic; MCSELECTDLLIF : in std_ulogic; MCSLOTCAPABILITYATTBUTTONPRESENT : in std_ulogic; MCSLOTCAPABILITYATTINDICATORPRESENT : in std_ulogic; MCSLOTCAPABILITYHOTPLUGCAPABLE : in std_ulogic; MCSLOTCAPABILITYHOTPLUGSURPRISE : in std_ulogic; MCSLOTCAPABILITYMSLSENSORPRESENT : in std_ulogic; MCSLOTCAPABILITYPHYSICALSLOTNUM : in std_logic_vector(12 downto 0); MCSLOTCAPABILITYPOWERCONTROLLERPRESENT : in std_ulogic; MCSLOTCAPABILITYPOWERINDICATORPRESENT : in std_ulogic; MCSLOTCAPABILITYSLOTPOWERLIMITSCALE : in std_logic_vector(1 downto 0); MCSLOTCAPABILITYSLOTPOWERLIMITVALUE : in std_logic_vector(7 downto 0); MCSLOTIMPLEMENTED : in std_ulogic; MCSUBSYSTEMID : in std_logic_vector(15 downto 0); MCSUBSYSTEMVENDORID : in std_logic_vector(15 downto 0); MCTLRAMREADLATENCY : in std_logic_vector(2 downto 0); MCTLRAMWIDTH : in std_ulogic; MCTLRAMWRITELATENCY : in std_logic_vector(2 downto 0); MCTXREADADDRPIPE : in std_ulogic; MCTXREADDATAPIPE : in std_ulogic; MCTXTSNFTS : in std_logic_vector(7 downto 0); MCTXTSNFTSCOMCLK : in std_logic_vector(7 downto 0); MCTXWRITEPIPE : in std_ulogic; MCUPSTREAMFACING : in std_ulogic; MCVC0RXFIFOBASEC : in std_logic_vector(12 downto 0); MCVC0RXFIFOBASENP : in std_logic_vector(12 downto 0); MCVC0RXFIFOBASEP : in std_logic_vector(12 downto 0); MCVC0RXFIFOLIMITC : in std_logic_vector(12 downto 0); MCVC0RXFIFOLIMITNP : in std_logic_vector(12 downto 0); MCVC0RXFIFOLIMITP : in std_logic_vector(12 downto 0); MCVC0TOTALCREDITSCD : in std_logic_vector(10 downto 0); MCVC0TOTALCREDITSCH : in std_logic_vector(6 downto 0); MCVC0TOTALCREDITSNPH : in std_logic_vector(6 downto 0); MCVC0TOTALCREDITSPD : in std_logic_vector(10 downto 0); MCVC0TOTALCREDITSPH : in std_logic_vector(6 downto 0); MCVC0TXFIFOBASEC : in std_logic_vector(12 downto 0); MCVC0TXFIFOBASENP : in std_logic_vector(12 downto 0); MCVC0TXFIFOBASEP : in std_logic_vector(12 downto 0); MCVC0TXFIFOLIMITC : in std_logic_vector(12 downto 0); MCVC0TXFIFOLIMITNP : in std_logic_vector(12 downto 0); MCVC0TXFIFOLIMITP : in std_logic_vector(12 downto 0); MCVC1RXFIFOBASEC : in std_logic_vector(12 downto 0); MCVC1RXFIFOBASENP : in std_logic_vector(12 downto 0); MCVC1RXFIFOBASEP : in std_logic_vector(12 downto 0); MCVC1RXFIFOLIMITC : in std_logic_vector(12 downto 0); MCVC1RXFIFOLIMITNP : in std_logic_vector(12 downto 0); MCVC1RXFIFOLIMITP : in std_logic_vector(12 downto 0); MCVC1TOTALCREDITSCD : in std_logic_vector(10 downto 0); MCVC1TOTALCREDITSCH : in std_logic_vector(6 downto 0); MCVC1TOTALCREDITSNPH : in std_logic_vector(6 downto 0); MCVC1TOTALCREDITSPD : in std_logic_vector(10 downto 0); MCVC1TOTALCREDITSPH : in std_logic_vector(6 downto 0); MCVC1TXFIFOBASEC : in std_logic_vector(12 downto 0); MCVC1TXFIFOBASENP : in std_logic_vector(12 downto 0); MCVC1TXFIFOBASEP : in std_logic_vector(12 downto 0); MCVC1TXFIFOLIMITC : in std_logic_vector(12 downto 0); MCVC1TXFIFOLIMITNP : in std_logic_vector(12 downto 0); MCVC1TXFIFOLIMITP : in std_logic_vector(12 downto 0); MCVCBASEPTR : in std_logic_vector(11 downto 0); MCVCCAPABILITYNEXTPTR : in std_logic_vector(11 downto 0); MCVENDORID : in std_logic_vector(15 downto 0); MCXLINKSUPPORTED : in std_ulogic; MCXPBASEPTR : in std_logic_vector(7 downto 0); MCXPDEVICEPORTTYPE : in std_logic_vector(3 downto 0); MCXPMAXPAYLOAD : in std_logic_vector(2 downto 0); MCXPRCBCONTROL : in std_ulogic ); end component; constant IN_DELAY : time := 0 ps; constant OUT_DELAY : time := 0 ps; constant CLK_DELAY : time := 0 ps; constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); signal VC0TXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOBASEP)(12 downto 0); signal VC0TXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOBASENP)(12 downto 0); signal VC0TXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOBASEC)(12 downto 0); signal VC0TXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOLIMITP)(12 downto 0); signal VC0TXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOLIMITNP)(12 downto 0); signal VC0TXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0TXFIFOLIMITC)(12 downto 0); signal VC0TOTALCREDITSPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC0TOTALCREDITSPH)(6 downto 0); signal VC0TOTALCREDITSNPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC0TOTALCREDITSNPH)(6 downto 0); signal VC0TOTALCREDITSCH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC0TOTALCREDITSCH)(6 downto 0); signal VC0TOTALCREDITSPD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC0TOTALCREDITSPD)(10 downto 0); signal VC0TOTALCREDITSCD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC0TOTALCREDITSCD)(10 downto 0); signal VC0RXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOBASEP)(12 downto 0); signal VC0RXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOBASENP)(12 downto 0); signal VC0RXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOBASEC)(12 downto 0); signal VC0RXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOLIMITP)(12 downto 0); signal VC0RXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOLIMITNP)(12 downto 0); signal VC0RXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC0RXFIFOLIMITC)(12 downto 0); signal VC1TXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOBASEP)(12 downto 0); signal VC1TXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOBASENP)(12 downto 0); signal VC1TXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOBASEC)(12 downto 0); signal VC1TXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOLIMITP)(12 downto 0); signal VC1TXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOLIMITNP)(12 downto 0); signal VC1TXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1TXFIFOLIMITC)(12 downto 0); signal VC1TOTALCREDITSPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC1TOTALCREDITSPH)(6 downto 0); signal VC1TOTALCREDITSNPH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC1TOTALCREDITSNPH)(6 downto 0); signal VC1TOTALCREDITSCH_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(VC1TOTALCREDITSCH)(6 downto 0); signal VC1TOTALCREDITSPD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC1TOTALCREDITSPD)(10 downto 0); signal VC1TOTALCREDITSCD_BINARY : std_logic_vector(10 downto 0) := To_StdLogicVector(VC1TOTALCREDITSCD)(10 downto 0); signal VC1RXFIFOBASEP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOBASEP)(12 downto 0); signal VC1RXFIFOBASENP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOBASENP)(12 downto 0); signal VC1RXFIFOBASEC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOBASEC)(12 downto 0); signal VC1RXFIFOLIMITP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOLIMITP)(12 downto 0); signal VC1RXFIFOLIMITNP_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOLIMITNP)(12 downto 0); signal VC1RXFIFOLIMITC_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(VC1RXFIFOLIMITC)(12 downto 0); signal ACTIVELANESIN_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(ACTIVELANESIN); signal TXTSNFTS_BINARY : std_logic_vector(7 downto 0); signal TXTSNFTSCOMCLK_BINARY : std_logic_vector(7 downto 0); signal RETRYRAMREADLATENCY_BINARY : std_logic_vector(2 downto 0); signal RETRYRAMWRITELATENCY_BINARY : std_logic_vector(2 downto 0); signal RETRYRAMWIDTH_BINARY : std_ulogic; signal RETRYRAMSIZE_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(RETRYRAMSIZE); signal RETRYWRITEPIPE_BINARY : std_ulogic; signal RETRYREADADDRPIPE_BINARY : std_ulogic; signal RETRYREADDATAPIPE_BINARY : std_ulogic; signal XLINKSUPPORTED_BINARY : std_ulogic; signal INFINITECOMPLETIONS_BINARY : std_ulogic; signal TLRAMREADLATENCY_BINARY : std_logic_vector(2 downto 0); signal TLRAMWRITELATENCY_BINARY : std_logic_vector(2 downto 0); signal TLRAMWIDTH_BINARY : std_ulogic; signal RAMSHARETXRX_BINARY : std_ulogic; signal L0SEXITLATENCY_BINARY : std_logic_vector(2 downto 0); signal L0SEXITLATENCYCOMCLK_BINARY : std_logic_vector(2 downto 0); signal L1EXITLATENCY_BINARY : std_logic_vector(2 downto 0); signal L1EXITLATENCYCOMCLK_BINARY : std_logic_vector(2 downto 0); signal DUALCORESLAVE_BINARY : std_ulogic; signal DUALCOREENABLE_BINARY : std_ulogic; signal DUALROLECFGCNTRLROOTEPN_BINARY : std_ulogic; signal RXREADADDRPIPE_BINARY : std_ulogic; signal RXREADDATAPIPE_BINARY : std_ulogic; signal TXWRITEPIPE_BINARY : std_ulogic; signal TXREADADDRPIPE_BINARY : std_ulogic; signal TXREADDATAPIPE_BINARY : std_ulogic; signal RXWRITEPIPE_BINARY : std_ulogic; signal LLKBYPASS_BINARY : std_ulogic; signal PCIEREVISION_BINARY : std_ulogic; signal SELECTDLLIF_BINARY : std_ulogic; signal SELECTASMODE_BINARY : std_ulogic; signal ISSWITCH_BINARY : std_ulogic; signal UPSTREAMFACING_BINARY : std_ulogic; signal SLOTIMPLEMENTED_BINARY : std_ulogic; signal EXTCFGCAPPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(EXTCFGCAPPTR); signal EXTCFGXPCAPPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(EXTCFGXPCAPPTR); signal BAR0EXIST_BINARY : std_ulogic; signal BAR1EXIST_BINARY : std_ulogic; signal BAR2EXIST_BINARY : std_ulogic; signal BAR3EXIST_BINARY : std_ulogic; signal BAR4EXIST_BINARY : std_ulogic; signal BAR5EXIST_BINARY : std_ulogic; signal BAR0ADDRWIDTH_BINARY : std_ulogic; signal BAR1ADDRWIDTH_BINARY : std_ulogic; signal BAR2ADDRWIDTH_BINARY : std_ulogic; signal BAR3ADDRWIDTH_BINARY : std_ulogic; signal BAR4ADDRWIDTH_BINARY : std_ulogic; signal BAR5ADDRWIDTH_BINARY : std_ulogic := '0'; signal BAR0PREFETCHABLE_BINARY : std_ulogic; signal BAR1PREFETCHABLE_BINARY : std_ulogic; signal BAR2PREFETCHABLE_BINARY : std_ulogic; signal BAR3PREFETCHABLE_BINARY : std_ulogic; signal BAR4PREFETCHABLE_BINARY : std_ulogic; signal BAR5PREFETCHABLE_BINARY : std_ulogic; signal BAR0IOMEMN_BINARY : std_ulogic; signal BAR1IOMEMN_BINARY : std_ulogic; signal BAR2IOMEMN_BINARY : std_ulogic; signal BAR3IOMEMN_BINARY : std_ulogic; signal BAR4IOMEMN_BINARY : std_ulogic; signal BAR5IOMEMN_BINARY : std_ulogic; signal BAR0MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR0MASKWIDTH)(5 downto 0); signal BAR1MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR1MASKWIDTH)(5 downto 0); signal BAR2MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR2MASKWIDTH)(5 downto 0); signal BAR3MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR3MASKWIDTH)(5 downto 0); signal BAR4MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR4MASKWIDTH)(5 downto 0); signal BAR5MASKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(BAR5MASKWIDTH)(5 downto 0); signal CONFIGROUTING_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(CONFIGROUTING)(2 downto 0); signal XPDEVICEPORTTYPE_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(XPDEVICEPORTTYPE); signal HEADERTYPE_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(HEADERTYPE); signal XPMAXPAYLOAD_BINARY : std_logic_vector(2 downto 0); signal XPRCBCONTROL_BINARY : std_ulogic; signal LOWPRIORITYVCCOUNT_BINARY : std_logic_vector(2 downto 0); signal VENDORID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(VENDORID); signal DEVICEID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(DEVICEID); signal REVISIONID_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(REVISIONID); signal CLASSCODE_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(CLASSCODE); signal CARDBUSCISPOINTER_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(CARDBUSCISPOINTER); signal SUBSYSTEMVENDORID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(SUBSYSTEMVENDORID); signal SUBSYSTEMID_BINARY : std_logic_vector(15 downto 0) := To_StdLogicVector(SUBSYSTEMID); signal CAPABILITIESPOINTER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(CAPABILITIESPOINTER); signal INTERRUPTPIN_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(INTERRUPTPIN); signal PMCAPABILITYNEXTPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMCAPABILITYNEXTPTR); signal PMCAPABILITYDSI_BINARY : std_ulogic; signal PMCAPABILITYAUXCURRENT_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PMCAPABILITYAUXCURRENT)(2 downto 0); signal PMCAPABILITYD1SUPPORT_BINARY : std_ulogic; signal PMCAPABILITYD2SUPPORT_BINARY : std_ulogic; signal PMCAPABILITYPMESUPPORT_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(PMCAPABILITYPMESUPPORT)(4 downto 0); signal PMSTATUSCONTROLDATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PMSTATUSCONTROLDATASCALE)(1 downto 0); signal PMDATA0_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA0); signal PMDATA1_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA1); signal PMDATA2_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA2); signal PMDATA3_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA3); signal PMDATA4_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA4); signal PMDATA5_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA5); signal PMDATA6_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA6); signal PMDATA7_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA7); signal PMDATA8_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PMDATA8); signal PMDATASCALE0_BINARY : std_logic_vector(1 downto 0); signal PMDATASCALE1_BINARY : std_logic_vector(1 downto 0); signal PMDATASCALE2_BINARY : std_logic_vector(1 downto 0); signal PMDATASCALE3_BINARY : std_logic_vector(1 downto 0); signal PMDATASCALE4_BINARY : std_logic_vector(1 downto 0); signal PMDATASCALE5_BINARY : std_logic_vector(1 downto 0); signal PMDATASCALE6_BINARY : std_logic_vector(1 downto 0); signal PMDATASCALE7_BINARY : std_logic_vector(1 downto 0); signal PMDATASCALE8_BINARY : std_logic_vector(1 downto 0); signal MSICAPABILITYNEXTPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(MSICAPABILITYNEXTPTR); signal MSICAPABILITYMULTIMSGCAP_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(MSICAPABILITYMULTIMSGCAP)(2 downto 0); signal PCIECAPABILITYNEXTPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PCIECAPABILITYNEXTPTR); signal PCIECAPABILITYSLOTIMPL_BINARY : std_ulogic; signal PCIECAPABILITYINTMSGNUM_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(PCIECAPABILITYINTMSGNUM)(4 downto 0); signal DEVICECAPABILITYENDPOINTL0SLATENCY_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(DEVICECAPABILITYENDPOINTL0SLATENCY)(2 downto 0); signal DEVICECAPABILITYENDPOINTL1LATENCY_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(DEVICECAPABILITYENDPOINTL1LATENCY)(2 downto 0); signal LINKCAPABILITYMAXLINKWIDTH_BINARY : std_logic_vector(5 downto 0) := To_StdLogicVector(LINKCAPABILITYMAXLINKWIDTH)(5 downto 0); signal LINKCAPABILITYASPMSUPPORT_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(LINKCAPABILITYASPMSUPPORT)(1 downto 0); signal LINKSTATUSSLOTCLOCKCONFIG_BINARY : std_ulogic; signal SLOTCAPABILITYATTBUTTONPRESENT_BINARY : std_ulogic; signal SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY : std_ulogic; signal SLOTCAPABILITYMSLSENSORPRESENT_BINARY : std_ulogic; signal SLOTCAPABILITYATTINDICATORPRESENT_BINARY : std_ulogic; signal SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY : std_ulogic; signal SLOTCAPABILITYHOTPLUGSURPRISE_BINARY : std_ulogic; signal SLOTCAPABILITYHOTPLUGCAPABLE_BINARY : std_ulogic; signal SLOTCAPABILITYSLOTPOWERLIMITVALUE_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(SLOTCAPABILITYSLOTPOWERLIMITVALUE); signal SLOTCAPABILITYSLOTPOWERLIMITSCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(SLOTCAPABILITYSLOTPOWERLIMITSCALE)(1 downto 0); signal SLOTCAPABILITYPHYSICALSLOTNUM_BINARY : std_logic_vector(12 downto 0) := To_StdLogicVector(SLOTCAPABILITYPHYSICALSLOTNUM)(12 downto 0); signal AERCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(AERCAPABILITYNEXTPTR); signal AERCAPABILITYECRCGENCAPABLE_BINARY : std_ulogic; signal AERCAPABILITYECRCCHECKCAPABLE_BINARY : std_ulogic; signal VCCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(VCCAPABILITYNEXTPTR); signal PORTVCCAPABILITYEXTENDEDVCCOUNT_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PORTVCCAPABILITYEXTENDEDVCCOUNT)(2 downto 0); signal PORTVCCAPABILITYVCARBCAP_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PORTVCCAPABILITYVCARBCAP); signal PORTVCCAPABILITYVCARBTABLEOFFSET_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PORTVCCAPABILITYVCARBTABLEOFFSET); signal DSNCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(DSNCAPABILITYNEXTPTR); signal DEVICESERIALNUMBER_BINARY : std_logic_vector(63 downto 0) := To_StdLogicVector(DEVICESERIALNUMBER); signal PBCAPABILITYNEXTPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(PBCAPABILITYNEXTPTR); signal PBCAPABILITYDW0BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW0BASEPOWER); signal PBCAPABILITYDW0DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW0DATASCALE)(1 downto 0); signal PBCAPABILITYDW0PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW0PMSUBSTATE)(2 downto 0); signal PBCAPABILITYDW0PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW0PMSTATE)(1 downto 0); signal PBCAPABILITYDW0TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW0TYPE)(2 downto 0); signal PBCAPABILITYDW0POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW0POWERRAIL)(2 downto 0); signal PBCAPABILITYDW1BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW1BASEPOWER); signal PBCAPABILITYDW1DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW1DATASCALE)(1 downto 0); signal PBCAPABILITYDW1PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW1PMSUBSTATE)(2 downto 0); signal PBCAPABILITYDW1PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW1PMSTATE)(1 downto 0); signal PBCAPABILITYDW1TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW1TYPE)(2 downto 0); signal PBCAPABILITYDW1POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW1POWERRAIL)(2 downto 0); signal PBCAPABILITYDW2BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW2BASEPOWER); signal PBCAPABILITYDW2DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW2DATASCALE)(1 downto 0); signal PBCAPABILITYDW2PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW2PMSUBSTATE)(2 downto 0); signal PBCAPABILITYDW2PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW2PMSTATE)(1 downto 0); signal PBCAPABILITYDW2TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW2TYPE)(2 downto 0); signal PBCAPABILITYDW2POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW2POWERRAIL)(2 downto 0); signal PBCAPABILITYDW3BASEPOWER_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PBCAPABILITYDW3BASEPOWER); signal PBCAPABILITYDW3DATASCALE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW3DATASCALE)(1 downto 0); signal PBCAPABILITYDW3PMSUBSTATE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW3PMSUBSTATE)(2 downto 0); signal PBCAPABILITYDW3PMSTATE_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(PBCAPABILITYDW3PMSTATE)(1 downto 0); signal PBCAPABILITYDW3TYPE_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW3TYPE)(2 downto 0); signal PBCAPABILITYDW3POWERRAIL_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PBCAPABILITYDW3POWERRAIL)(2 downto 0); signal PBCAPABILITYSYSTEMALLOCATED_BINARY : std_ulogic; signal RESETMODE_BINARY : std_ulogic; signal AERBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(AERBASEPTR); signal DSNBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(DSNBASEPTR); signal MSIBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(MSIBASEPTR); signal PBBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(PBBASEPTR); signal PMBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(PMBASEPTR); signal VCBASEPTR_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(VCBASEPTR); signal XPBASEPTR_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(XPBASEPTR); signal CLKDIVIDED_BINARY : std_ulogic; signal PIPETXDATAL0_out : std_logic_vector(7 downto 0); signal PIPETXDATAKL0_out : std_ulogic; signal PIPETXELECIDLEL0_out : std_ulogic; signal PIPETXDETECTRXLOOPBACKL0_out : std_ulogic; signal PIPETXCOMPLIANCEL0_out : std_ulogic; signal PIPERXPOLARITYL0_out : std_ulogic; signal PIPEPOWERDOWNL0_out : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL0_out : std_ulogic; signal PIPERESETL0_out : std_ulogic; signal PIPETXDATAL1_out : std_logic_vector(7 downto 0); signal PIPETXDATAKL1_out : std_ulogic; signal PIPETXELECIDLEL1_out : std_ulogic; signal PIPETXDETECTRXLOOPBACKL1_out : std_ulogic; signal PIPETXCOMPLIANCEL1_out : std_ulogic; signal PIPERXPOLARITYL1_out : std_ulogic; signal PIPEPOWERDOWNL1_out : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL1_out : std_ulogic; signal PIPERESETL1_out : std_ulogic; signal PIPETXDATAL2_out : std_logic_vector(7 downto 0); signal PIPETXDATAKL2_out : std_ulogic; signal PIPETXELECIDLEL2_out : std_ulogic; signal PIPETXDETECTRXLOOPBACKL2_out : std_ulogic; signal PIPETXCOMPLIANCEL2_out : std_ulogic; signal PIPERXPOLARITYL2_out : std_ulogic; signal PIPEPOWERDOWNL2_out : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL2_out : std_ulogic; signal PIPERESETL2_out : std_ulogic; signal PIPETXDATAL3_out : std_logic_vector(7 downto 0); signal PIPETXDATAKL3_out : std_ulogic; signal PIPETXELECIDLEL3_out : std_ulogic; signal PIPETXDETECTRXLOOPBACKL3_out : std_ulogic; signal PIPETXCOMPLIANCEL3_out : std_ulogic; signal PIPERXPOLARITYL3_out : std_ulogic; signal PIPEPOWERDOWNL3_out : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL3_out : std_ulogic; signal PIPERESETL3_out : std_ulogic; signal PIPETXDATAL4_out : std_logic_vector(7 downto 0); signal PIPETXDATAKL4_out : std_ulogic; signal PIPETXELECIDLEL4_out : std_ulogic; signal PIPETXDETECTRXLOOPBACKL4_out : std_ulogic; signal PIPETXCOMPLIANCEL4_out : std_ulogic; signal PIPERXPOLARITYL4_out : std_ulogic; signal PIPEPOWERDOWNL4_out : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL4_out : std_ulogic; signal PIPERESETL4_out : std_ulogic; signal PIPETXDATAL5_out : std_logic_vector(7 downto 0); signal PIPETXDATAKL5_out : std_ulogic; signal PIPETXELECIDLEL5_out : std_ulogic; signal PIPETXDETECTRXLOOPBACKL5_out : std_ulogic; signal PIPETXCOMPLIANCEL5_out : std_ulogic; signal PIPERXPOLARITYL5_out : std_ulogic; signal PIPEPOWERDOWNL5_out : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL5_out : std_ulogic; signal PIPERESETL5_out : std_ulogic; signal PIPETXDATAL6_out : std_logic_vector(7 downto 0); signal PIPETXDATAKL6_out : std_ulogic; signal PIPETXELECIDLEL6_out : std_ulogic; signal PIPETXDETECTRXLOOPBACKL6_out : std_ulogic; signal PIPETXCOMPLIANCEL6_out : std_ulogic; signal PIPERXPOLARITYL6_out : std_ulogic; signal PIPEPOWERDOWNL6_out : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL6_out : std_ulogic; signal PIPERESETL6_out : std_ulogic; signal PIPETXDATAL7_out : std_logic_vector(7 downto 0); signal PIPETXDATAKL7_out : std_ulogic; signal PIPETXELECIDLEL7_out : std_ulogic; signal PIPETXDETECTRXLOOPBACKL7_out : std_ulogic; signal PIPETXCOMPLIANCEL7_out : std_ulogic; signal PIPERXPOLARITYL7_out : std_ulogic; signal PIPEPOWERDOWNL7_out : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL7_out : std_ulogic; signal PIPERESETL7_out : std_ulogic; signal MIMRXBWDATA_out : std_logic_vector(63 downto 0); signal MIMRXBWADD_out : std_logic_vector(12 downto 0); signal MIMRXBRADD_out : std_logic_vector(12 downto 0); signal MIMRXBWEN_out : std_ulogic; signal MIMRXBREN_out : std_ulogic; signal MIMTXBWDATA_out : std_logic_vector(63 downto 0); signal MIMTXBWADD_out : std_logic_vector(12 downto 0); signal MIMTXBRADD_out : std_logic_vector(12 downto 0); signal MIMTXBWEN_out : std_ulogic; signal MIMTXBREN_out : std_ulogic; signal MIMDLLBWDATA_out : std_logic_vector(63 downto 0); signal MIMDLLBWADD_out : std_logic_vector(11 downto 0); signal MIMDLLBRADD_out : std_logic_vector(11 downto 0); signal MIMDLLBWEN_out : std_ulogic; signal MIMDLLBREN_out : std_ulogic; signal CRMRXHOTRESETN_out : std_ulogic; signal CRMDOHOTRESETN_out : std_ulogic; signal CRMPWRSOFTRESETN_out : std_ulogic; signal LLKTCSTATUS_out : std_logic_vector(7 downto 0); signal LLKTXDSTRDYN_out : std_ulogic; signal LLKTXCHANSPACE_out : std_logic_vector(9 downto 0); signal LLKTXCHPOSTEDREADYN_out : std_logic_vector(7 downto 0); signal LLKTXCHNONPOSTEDREADYN_out : std_logic_vector(7 downto 0); signal LLKTXCHCOMPLETIONREADYN_out : std_logic_vector(7 downto 0); signal LLKTXCONFIGREADYN_out : std_ulogic; signal LLKRXDATA_out : std_logic_vector(63 downto 0); signal LLKRXSRCRDYN_out : std_ulogic; signal LLKRXSRCLASTREQN_out : std_ulogic; signal LLKRXSRCDSCN_out : std_ulogic; signal LLKRXSOFN_out : std_ulogic; signal LLKRXEOFN_out : std_ulogic; signal LLKRXSOPN_out : std_ulogic; signal LLKRXEOPN_out : std_ulogic; signal LLKRXVALIDN_out : std_logic_vector(1 downto 0); signal LLKRXPREFERREDTYPE_out : std_logic_vector(15 downto 0); signal LLKRXCHPOSTEDAVAILABLEN_out : std_logic_vector(7 downto 0); signal LLKRXCHNONPOSTEDAVAILABLEN_out : std_logic_vector(7 downto 0); signal LLKRXCHCOMPLETIONAVAILABLEN_out : std_logic_vector(7 downto 0); signal LLKRXCHCONFIGAVAILABLEN_out : std_ulogic; signal LLKRXCHPOSTEDPARTIALN_out : std_logic_vector(7 downto 0); signal LLKRXCHNONPOSTEDPARTIALN_out : std_logic_vector(7 downto 0); signal LLKRXCHCOMPLETIONPARTIALN_out : std_logic_vector(7 downto 0); signal LLKRXCHCONFIGPARTIALN_out : std_ulogic; signal LLKRX4DWHEADERN_out : std_ulogic; signal LLKRXECRCBADN_out : std_ulogic; signal MGMTRDATA_out : std_logic_vector(31 downto 0); signal MGMTPSO_out : std_logic_vector(16 downto 0); signal MGMTSTATSCREDIT_out : std_logic_vector(11 downto 0); signal L0RXDLLTLPECRCOK_out : std_ulogic; signal DLLTXPMDLLPOUTSTANDING_out : std_ulogic; signal L0FIRSTCFGWRITEOCCURRED_out : std_ulogic; signal L0CFGLOOPBACKACK_out : std_ulogic; signal L0MACUPSTREAMDOWNSTREAM_out : std_ulogic; signal L0RXMACLINKERROR_out : std_logic_vector(1 downto 0); signal L0MACLINKUP_out : std_ulogic; signal L0MACNEGOTIATEDLINKWIDTH_out : std_logic_vector(3 downto 0); signal L0MACLINKTRAINING_out : std_ulogic; signal L0LTSSMSTATE_out : std_logic_vector(3 downto 0); signal L0DLLVCSTATUS_out : std_logic_vector(7 downto 0); signal L0DLUPDOWN_out : std_logic_vector(7 downto 0); signal L0DLLERRORVECTOR_out : std_logic_vector(6 downto 0); signal L0DLLASRXSTATE_out : std_logic_vector(1 downto 0); signal L0DLLASTXSTATE_out : std_ulogic; signal L0ASAUTONOMOUSINITCOMPLETED_out : std_ulogic; signal L0COMPLETERID_out : std_logic_vector(12 downto 0); signal L0UNLOCKRECEIVED_out : std_ulogic; signal L0CORRERRMSGRCVD_out : std_ulogic; signal L0FATALERRMSGRCVD_out : std_ulogic; signal L0NONFATALERRMSGRCVD_out : std_ulogic; signal L0ERRMSGREQID_out : std_logic_vector(15 downto 0); signal L0FWDCORRERROUT_out : std_ulogic; signal L0FWDFATALERROUT_out : std_ulogic; signal L0FWDNONFATALERROUT_out : std_ulogic; signal L0RECEIVEDASSERTINTALEGACYINT_out : std_ulogic; signal L0RECEIVEDASSERTINTBLEGACYINT_out : std_ulogic; signal L0RECEIVEDASSERTINTCLEGACYINT_out : std_ulogic; signal L0RECEIVEDASSERTINTDLEGACYINT_out : std_ulogic; signal L0RECEIVEDDEASSERTINTALEGACYINT_out : std_ulogic; signal L0RECEIVEDDEASSERTINTBLEGACYINT_out : std_ulogic; signal L0RECEIVEDDEASSERTINTCLEGACYINT_out : std_ulogic; signal L0RECEIVEDDEASSERTINTDLEGACYINT_out : std_ulogic; signal L0MSIENABLE0_out : std_ulogic; signal L0MULTIMSGEN0_out : std_logic_vector(2 downto 0); signal L0STATSDLLPRECEIVED_out : std_ulogic; signal L0STATSDLLPTRANSMITTED_out : std_ulogic; signal L0STATSOSRECEIVED_out : std_ulogic; signal L0STATSOSTRANSMITTED_out : std_ulogic; signal L0STATSTLPRECEIVED_out : std_ulogic; signal L0STATSTLPTRANSMITTED_out : std_ulogic; signal L0STATSCFGRECEIVED_out : std_ulogic; signal L0STATSCFGTRANSMITTED_out : std_ulogic; signal L0STATSCFGOTHERRECEIVED_out : std_ulogic; signal L0STATSCFGOTHERTRANSMITTED_out : std_ulogic; signal MAXPAYLOADSIZE_out : std_logic_vector(2 downto 0); signal MAXREADREQUESTSIZE_out : std_logic_vector(2 downto 0); signal IOSPACEENABLE_out : std_ulogic; signal MEMSPACEENABLE_out : std_ulogic; signal L0ATTENTIONINDICATORCONTROL_out : std_logic_vector(1 downto 0); signal L0POWERINDICATORCONTROL_out : std_logic_vector(1 downto 0); signal L0POWERCONTROLLERCONTROL_out : std_ulogic; signal L0TOGGLEELECTROMECHANICALINTERLOCK_out : std_ulogic; signal L0RXBEACON_out : std_ulogic; signal L0PWRSTATE0_out : std_logic_vector(1 downto 0); signal L0PMEACK_out : std_ulogic; signal L0PMEREQOUT_out : std_ulogic; signal L0PMEEN_out : std_ulogic; signal L0PWRINHIBITTRANSFERS_out : std_ulogic; signal L0PWRL1STATE_out : std_ulogic; signal L0PWRL23READYDEVICE_out : std_ulogic; signal L0PWRL23READYSTATE_out : std_ulogic; signal L0PWRTXL0SSTATE_out : std_ulogic; signal L0PWRTURNOFFREQ_out : std_ulogic; signal L0RXDLLPM_out : std_ulogic; signal L0RXDLLPMTYPE_out : std_logic_vector(2 downto 0); signal L0TXDLLPMUPDATED_out : std_ulogic; signal L0MACNEWSTATEACK_out : std_ulogic; signal L0MACRXL0SSTATE_out : std_ulogic; signal L0MACENTEREDL0_out : std_ulogic; signal L0DLLRXACKOUTSTANDING_out : std_ulogic; signal L0DLLTXOUTSTANDING_out : std_ulogic; signal L0DLLTXNONFCOUTSTANDING_out : std_ulogic; signal L0RXDLLTLPEND_out : std_logic_vector(1 downto 0); signal L0TXDLLSBFCUPDATED_out : std_ulogic; signal L0RXDLLSBFCDATA_out : std_logic_vector(18 downto 0); signal L0RXDLLSBFCUPDATE_out : std_ulogic; signal L0TXDLLFCNPOSTBYPUPDATED_out : std_logic_vector(7 downto 0); signal L0TXDLLFCPOSTORDUPDATED_out : std_logic_vector(7 downto 0); signal L0TXDLLFCCMPLMCUPDATED_out : std_logic_vector(7 downto 0); signal L0RXDLLFCNPOSTBYPCRED_out : std_logic_vector(19 downto 0); signal L0RXDLLFCNPOSTBYPUPDATE_out : std_logic_vector(7 downto 0); signal L0RXDLLFCPOSTORDCRED_out : std_logic_vector(23 downto 0); signal L0RXDLLFCPOSTORDUPDATE_out : std_logic_vector(7 downto 0); signal L0RXDLLFCCMPLMCCRED_out : std_logic_vector(23 downto 0); signal L0RXDLLFCCMPLMCUPDATE_out : std_logic_vector(7 downto 0); signal L0UCBYPFOUND_out : std_logic_vector(3 downto 0); signal L0UCORDFOUND_out : std_logic_vector(3 downto 0); signal L0MCFOUND_out : std_logic_vector(2 downto 0); signal L0TRANSFORMEDVC_out : std_logic_vector(2 downto 0); signal BUSMASTERENABLE_out : std_ulogic; signal PARITYERRORRESPONSE_out : std_ulogic; signal SERRENABLE_out : std_ulogic; signal INTERRUPTDISABLE_out : std_ulogic; signal URREPORTINGENABLE_out : std_ulogic; signal PIPETXDATAL0_outdelay : std_logic_vector(7 downto 0); signal PIPETXDATAKL0_outdelay : std_ulogic; signal PIPETXELECIDLEL0_outdelay : std_ulogic; signal PIPETXDETECTRXLOOPBACKL0_outdelay : std_ulogic; signal PIPETXCOMPLIANCEL0_outdelay : std_ulogic; signal PIPERXPOLARITYL0_outdelay : std_ulogic; signal PIPEPOWERDOWNL0_outdelay : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL0_outdelay : std_ulogic; signal PIPERESETL0_outdelay : std_ulogic; signal PIPETXDATAL1_outdelay : std_logic_vector(7 downto 0); signal PIPETXDATAKL1_outdelay : std_ulogic; signal PIPETXELECIDLEL1_outdelay : std_ulogic; signal PIPETXDETECTRXLOOPBACKL1_outdelay : std_ulogic; signal PIPETXCOMPLIANCEL1_outdelay : std_ulogic; signal PIPERXPOLARITYL1_outdelay : std_ulogic; signal PIPEPOWERDOWNL1_outdelay : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL1_outdelay : std_ulogic; signal PIPERESETL1_outdelay : std_ulogic; signal PIPETXDATAL2_outdelay : std_logic_vector(7 downto 0); signal PIPETXDATAKL2_outdelay : std_ulogic; signal PIPETXELECIDLEL2_outdelay : std_ulogic; signal PIPETXDETECTRXLOOPBACKL2_outdelay : std_ulogic; signal PIPETXCOMPLIANCEL2_outdelay : std_ulogic; signal PIPERXPOLARITYL2_outdelay : std_ulogic; signal PIPEPOWERDOWNL2_outdelay : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL2_outdelay : std_ulogic; signal PIPERESETL2_outdelay : std_ulogic; signal PIPETXDATAL3_outdelay : std_logic_vector(7 downto 0); signal PIPETXDATAKL3_outdelay : std_ulogic; signal PIPETXELECIDLEL3_outdelay : std_ulogic; signal PIPETXDETECTRXLOOPBACKL3_outdelay : std_ulogic; signal PIPETXCOMPLIANCEL3_outdelay : std_ulogic; signal PIPERXPOLARITYL3_outdelay : std_ulogic; signal PIPEPOWERDOWNL3_outdelay : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL3_outdelay : std_ulogic; signal PIPERESETL3_outdelay : std_ulogic; signal PIPETXDATAL4_outdelay : std_logic_vector(7 downto 0); signal PIPETXDATAKL4_outdelay : std_ulogic; signal PIPETXELECIDLEL4_outdelay : std_ulogic; signal PIPETXDETECTRXLOOPBACKL4_outdelay : std_ulogic; signal PIPETXCOMPLIANCEL4_outdelay : std_ulogic; signal PIPERXPOLARITYL4_outdelay : std_ulogic; signal PIPEPOWERDOWNL4_outdelay : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL4_outdelay : std_ulogic; signal PIPERESETL4_outdelay : std_ulogic; signal PIPETXDATAL5_outdelay : std_logic_vector(7 downto 0); signal PIPETXDATAKL5_outdelay : std_ulogic; signal PIPETXELECIDLEL5_outdelay : std_ulogic; signal PIPETXDETECTRXLOOPBACKL5_outdelay : std_ulogic; signal PIPETXCOMPLIANCEL5_outdelay : std_ulogic; signal PIPERXPOLARITYL5_outdelay : std_ulogic; signal PIPEPOWERDOWNL5_outdelay : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL5_outdelay : std_ulogic; signal PIPERESETL5_outdelay : std_ulogic; signal PIPETXDATAL6_outdelay : std_logic_vector(7 downto 0); signal PIPETXDATAKL6_outdelay : std_ulogic; signal PIPETXELECIDLEL6_outdelay : std_ulogic; signal PIPETXDETECTRXLOOPBACKL6_outdelay : std_ulogic; signal PIPETXCOMPLIANCEL6_outdelay : std_ulogic; signal PIPERXPOLARITYL6_outdelay : std_ulogic; signal PIPEPOWERDOWNL6_outdelay : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL6_outdelay : std_ulogic; signal PIPERESETL6_outdelay : std_ulogic; signal PIPETXDATAL7_outdelay : std_logic_vector(7 downto 0); signal PIPETXDATAKL7_outdelay : std_ulogic; signal PIPETXELECIDLEL7_outdelay : std_ulogic; signal PIPETXDETECTRXLOOPBACKL7_outdelay : std_ulogic; signal PIPETXCOMPLIANCEL7_outdelay : std_ulogic; signal PIPERXPOLARITYL7_outdelay : std_ulogic; signal PIPEPOWERDOWNL7_outdelay : std_logic_vector(1 downto 0); signal PIPEDESKEWLANESL7_outdelay : std_ulogic; signal PIPERESETL7_outdelay : std_ulogic; signal MIMRXBWDATA_outdelay : std_logic_vector(63 downto 0); signal MIMRXBWADD_outdelay : std_logic_vector(12 downto 0); signal MIMRXBRADD_outdelay : std_logic_vector(12 downto 0); signal MIMRXBWEN_outdelay : std_ulogic; signal MIMRXBREN_outdelay : std_ulogic; signal MIMTXBWDATA_outdelay : std_logic_vector(63 downto 0); signal MIMTXBWADD_outdelay : std_logic_vector(12 downto 0); signal MIMTXBRADD_outdelay : std_logic_vector(12 downto 0); signal MIMTXBWEN_outdelay : std_ulogic; signal MIMTXBREN_outdelay : std_ulogic; signal MIMDLLBWDATA_outdelay : std_logic_vector(63 downto 0); signal MIMDLLBWADD_outdelay : std_logic_vector(11 downto 0); signal MIMDLLBRADD_outdelay : std_logic_vector(11 downto 0); signal MIMDLLBWEN_outdelay : std_ulogic; signal MIMDLLBREN_outdelay : std_ulogic; signal CRMRXHOTRESETN_outdelay : std_ulogic; signal CRMDOHOTRESETN_outdelay : std_ulogic; signal CRMPWRSOFTRESETN_outdelay : std_ulogic; signal LLKTCSTATUS_outdelay : std_logic_vector(7 downto 0); signal LLKTXDSTRDYN_outdelay : std_ulogic; signal LLKTXCHANSPACE_outdelay : std_logic_vector(9 downto 0); signal LLKTXCHPOSTEDREADYN_outdelay : std_logic_vector(7 downto 0); signal LLKTXCHNONPOSTEDREADYN_outdelay : std_logic_vector(7 downto 0); signal LLKTXCHCOMPLETIONREADYN_outdelay : std_logic_vector(7 downto 0); signal LLKTXCONFIGREADYN_outdelay : std_ulogic; signal LLKRXDATA_outdelay : std_logic_vector(63 downto 0); signal LLKRXSRCRDYN_outdelay : std_ulogic; signal LLKRXSRCLASTREQN_outdelay : std_ulogic; signal LLKRXSRCDSCN_outdelay : std_ulogic; signal LLKRXSOFN_outdelay : std_ulogic; signal LLKRXEOFN_outdelay : std_ulogic; signal LLKRXSOPN_outdelay : std_ulogic; signal LLKRXEOPN_outdelay : std_ulogic; signal LLKRXVALIDN_outdelay : std_logic_vector(1 downto 0); signal LLKRXPREFERREDTYPE_outdelay : std_logic_vector(15 downto 0); signal LLKRXCHPOSTEDAVAILABLEN_outdelay : std_logic_vector(7 downto 0); signal LLKRXCHNONPOSTEDAVAILABLEN_outdelay : std_logic_vector(7 downto 0); signal LLKRXCHCOMPLETIONAVAILABLEN_outdelay : std_logic_vector(7 downto 0); signal LLKRXCHCONFIGAVAILABLEN_outdelay : std_ulogic; signal LLKRXCHPOSTEDPARTIALN_outdelay : std_logic_vector(7 downto 0); signal LLKRXCHNONPOSTEDPARTIALN_outdelay : std_logic_vector(7 downto 0); signal LLKRXCHCOMPLETIONPARTIALN_outdelay : std_logic_vector(7 downto 0); signal LLKRXCHCONFIGPARTIALN_outdelay : std_ulogic; signal LLKRX4DWHEADERN_outdelay : std_ulogic; signal LLKRXECRCBADN_outdelay : std_ulogic; signal MGMTRDATA_outdelay : std_logic_vector(31 downto 0); signal MGMTPSO_outdelay : std_logic_vector(16 downto 0); signal MGMTSTATSCREDIT_outdelay : std_logic_vector(11 downto 0); signal L0RXDLLTLPECRCOK_outdelay : std_ulogic; signal DLLTXPMDLLPOUTSTANDING_outdelay : std_ulogic; signal L0FIRSTCFGWRITEOCCURRED_outdelay : std_ulogic; signal L0CFGLOOPBACKACK_outdelay : std_ulogic; signal L0MACUPSTREAMDOWNSTREAM_outdelay : std_ulogic; signal L0RXMACLINKERROR_outdelay : std_logic_vector(1 downto 0); signal L0MACLINKUP_outdelay : std_ulogic; signal L0MACNEGOTIATEDLINKWIDTH_outdelay : std_logic_vector(3 downto 0); signal L0MACLINKTRAINING_outdelay : std_ulogic; signal L0LTSSMSTATE_outdelay : std_logic_vector(3 downto 0); signal L0DLLVCSTATUS_outdelay : std_logic_vector(7 downto 0); signal L0DLUPDOWN_outdelay : std_logic_vector(7 downto 0); signal L0DLLERRORVECTOR_outdelay : std_logic_vector(6 downto 0); signal L0DLLASRXSTATE_outdelay : std_logic_vector(1 downto 0); signal L0DLLASTXSTATE_outdelay : std_ulogic; signal L0ASAUTONOMOUSINITCOMPLETED_outdelay : std_ulogic; signal L0COMPLETERID_outdelay : std_logic_vector(12 downto 0); signal L0UNLOCKRECEIVED_outdelay : std_ulogic; signal L0CORRERRMSGRCVD_outdelay : std_ulogic; signal L0FATALERRMSGRCVD_outdelay : std_ulogic; signal L0NONFATALERRMSGRCVD_outdelay : std_ulogic; signal L0ERRMSGREQID_outdelay : std_logic_vector(15 downto 0); signal L0FWDCORRERROUT_outdelay : std_ulogic; signal L0FWDFATALERROUT_outdelay : std_ulogic; signal L0FWDNONFATALERROUT_outdelay : std_ulogic; signal L0RECEIVEDASSERTINTALEGACYINT_outdelay : std_ulogic; signal L0RECEIVEDASSERTINTBLEGACYINT_outdelay : std_ulogic; signal L0RECEIVEDASSERTINTCLEGACYINT_outdelay : std_ulogic; signal L0RECEIVEDASSERTINTDLEGACYINT_outdelay : std_ulogic; signal L0RECEIVEDDEASSERTINTALEGACYINT_outdelay : std_ulogic; signal L0RECEIVEDDEASSERTINTBLEGACYINT_outdelay : std_ulogic; signal L0RECEIVEDDEASSERTINTCLEGACYINT_outdelay : std_ulogic; signal L0RECEIVEDDEASSERTINTDLEGACYINT_outdelay : std_ulogic; signal L0MSIENABLE0_outdelay : std_ulogic; signal L0MULTIMSGEN0_outdelay : std_logic_vector(2 downto 0); signal L0STATSDLLPRECEIVED_outdelay : std_ulogic; signal L0STATSDLLPTRANSMITTED_outdelay : std_ulogic; signal L0STATSOSRECEIVED_outdelay : std_ulogic; signal L0STATSOSTRANSMITTED_outdelay : std_ulogic; signal L0STATSTLPRECEIVED_outdelay : std_ulogic; signal L0STATSTLPTRANSMITTED_outdelay : std_ulogic; signal L0STATSCFGRECEIVED_outdelay : std_ulogic; signal L0STATSCFGTRANSMITTED_outdelay : std_ulogic; signal L0STATSCFGOTHERRECEIVED_outdelay : std_ulogic; signal L0STATSCFGOTHERTRANSMITTED_outdelay : std_ulogic; signal MAXPAYLOADSIZE_outdelay : std_logic_vector(2 downto 0); signal MAXREADREQUESTSIZE_outdelay : std_logic_vector(2 downto 0); signal IOSPACEENABLE_outdelay : std_ulogic; signal MEMSPACEENABLE_outdelay : std_ulogic; signal L0ATTENTIONINDICATORCONTROL_outdelay : std_logic_vector(1 downto 0); signal L0POWERINDICATORCONTROL_outdelay : std_logic_vector(1 downto 0); signal L0POWERCONTROLLERCONTROL_outdelay : std_ulogic; signal L0TOGGLEELECTROMECHANICALINTERLOCK_outdelay : std_ulogic; signal L0RXBEACON_outdelay : std_ulogic; signal L0PWRSTATE0_outdelay : std_logic_vector(1 downto 0); signal L0PMEACK_outdelay : std_ulogic; signal L0PMEREQOUT_outdelay : std_ulogic; signal L0PMEEN_outdelay : std_ulogic; signal L0PWRINHIBITTRANSFERS_outdelay : std_ulogic; signal L0PWRL1STATE_outdelay : std_ulogic; signal L0PWRL23READYDEVICE_outdelay : std_ulogic; signal L0PWRL23READYSTATE_outdelay : std_ulogic; signal L0PWRTXL0SSTATE_outdelay : std_ulogic; signal L0PWRTURNOFFREQ_outdelay : std_ulogic; signal L0RXDLLPM_outdelay : std_ulogic; signal L0RXDLLPMTYPE_outdelay : std_logic_vector(2 downto 0); signal L0TXDLLPMUPDATED_outdelay : std_ulogic; signal L0MACNEWSTATEACK_outdelay : std_ulogic; signal L0MACRXL0SSTATE_outdelay : std_ulogic; signal L0MACENTEREDL0_outdelay : std_ulogic; signal L0DLLRXACKOUTSTANDING_outdelay : std_ulogic; signal L0DLLTXOUTSTANDING_outdelay : std_ulogic; signal L0DLLTXNONFCOUTSTANDING_outdelay : std_ulogic; signal L0RXDLLTLPEND_outdelay : std_logic_vector(1 downto 0); signal L0TXDLLSBFCUPDATED_outdelay : std_ulogic; signal L0RXDLLSBFCDATA_outdelay : std_logic_vector(18 downto 0); signal L0RXDLLSBFCUPDATE_outdelay : std_ulogic; signal L0TXDLLFCNPOSTBYPUPDATED_outdelay : std_logic_vector(7 downto 0); signal L0TXDLLFCPOSTORDUPDATED_outdelay : std_logic_vector(7 downto 0); signal L0TXDLLFCCMPLMCUPDATED_outdelay : std_logic_vector(7 downto 0); signal L0RXDLLFCNPOSTBYPCRED_outdelay : std_logic_vector(19 downto 0); signal L0RXDLLFCNPOSTBYPUPDATE_outdelay : std_logic_vector(7 downto 0); signal L0RXDLLFCPOSTORDCRED_outdelay : std_logic_vector(23 downto 0); signal L0RXDLLFCPOSTORDUPDATE_outdelay : std_logic_vector(7 downto 0); signal L0RXDLLFCCMPLMCCRED_outdelay : std_logic_vector(23 downto 0); signal L0RXDLLFCCMPLMCUPDATE_outdelay : std_logic_vector(7 downto 0); signal L0UCBYPFOUND_outdelay : std_logic_vector(3 downto 0); signal L0UCORDFOUND_outdelay : std_logic_vector(3 downto 0); signal L0MCFOUND_outdelay : std_logic_vector(2 downto 0); signal L0TRANSFORMEDVC_outdelay : std_logic_vector(2 downto 0); signal BUSMASTERENABLE_outdelay : std_ulogic; signal PARITYERRORRESPONSE_outdelay : std_ulogic; signal SERRENABLE_outdelay : std_ulogic; signal INTERRUPTDISABLE_outdelay : std_ulogic; signal URREPORTINGENABLE_outdelay : std_ulogic; signal PIPERXELECIDLEL0_ipd : std_ulogic; signal PIPERXSTATUSL0_ipd : std_logic_vector(2 downto 0); signal PIPERXDATAL0_ipd : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL0_ipd : std_ulogic; signal PIPERXDATAKL0_ipd : std_ulogic; signal PIPERXVALIDL0_ipd : std_ulogic; signal PIPERXCHANISALIGNEDL0_ipd : std_ulogic; signal PIPERXELECIDLEL1_ipd : std_ulogic; signal PIPERXSTATUSL1_ipd : std_logic_vector(2 downto 0); signal PIPERXDATAL1_ipd : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL1_ipd : std_ulogic; signal PIPERXDATAKL1_ipd : std_ulogic; signal PIPERXVALIDL1_ipd : std_ulogic; signal PIPERXCHANISALIGNEDL1_ipd : std_ulogic; signal PIPERXELECIDLEL2_ipd : std_ulogic; signal PIPERXSTATUSL2_ipd : std_logic_vector(2 downto 0); signal PIPERXDATAL2_ipd : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL2_ipd : std_ulogic; signal PIPERXDATAKL2_ipd : std_ulogic; signal PIPERXVALIDL2_ipd : std_ulogic; signal PIPERXCHANISALIGNEDL2_ipd : std_ulogic; signal PIPERXELECIDLEL3_ipd : std_ulogic; signal PIPERXSTATUSL3_ipd : std_logic_vector(2 downto 0); signal PIPERXDATAL3_ipd : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL3_ipd : std_ulogic; signal PIPERXDATAKL3_ipd : std_ulogic; signal PIPERXVALIDL3_ipd : std_ulogic; signal PIPERXCHANISALIGNEDL3_ipd : std_ulogic; signal PIPERXELECIDLEL4_ipd : std_ulogic; signal PIPERXSTATUSL4_ipd : std_logic_vector(2 downto 0); signal PIPERXDATAL4_ipd : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL4_ipd : std_ulogic; signal PIPERXDATAKL4_ipd : std_ulogic; signal PIPERXVALIDL4_ipd : std_ulogic; signal PIPERXCHANISALIGNEDL4_ipd : std_ulogic; signal PIPERXELECIDLEL5_ipd : std_ulogic; signal PIPERXSTATUSL5_ipd : std_logic_vector(2 downto 0); signal PIPERXDATAL5_ipd : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL5_ipd : std_ulogic; signal PIPERXDATAKL5_ipd : std_ulogic; signal PIPERXVALIDL5_ipd : std_ulogic; signal PIPERXCHANISALIGNEDL5_ipd : std_ulogic; signal PIPERXELECIDLEL6_ipd : std_ulogic; signal PIPERXSTATUSL6_ipd : std_logic_vector(2 downto 0); signal PIPERXDATAL6_ipd : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL6_ipd : std_ulogic; signal PIPERXDATAKL6_ipd : std_ulogic; signal PIPERXVALIDL6_ipd : std_ulogic; signal PIPERXCHANISALIGNEDL6_ipd : std_ulogic; signal PIPERXELECIDLEL7_ipd : std_ulogic; signal PIPERXSTATUSL7_ipd : std_logic_vector(2 downto 0); signal PIPERXDATAL7_ipd : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL7_ipd : std_ulogic; signal PIPERXDATAKL7_ipd : std_ulogic; signal PIPERXVALIDL7_ipd : std_ulogic; signal PIPERXCHANISALIGNEDL7_ipd : std_ulogic; signal MIMRXBRDATA_ipd : std_logic_vector(63 downto 0); signal CRMCORECLKRXO_ipd : std_ulogic; signal CRMUSERCLKRXO_ipd : std_ulogic; signal MIMTXBRDATA_ipd : std_logic_vector(63 downto 0); signal CRMCORECLKTXO_ipd : std_ulogic; signal CRMUSERCLKTXO_ipd : std_ulogic; signal MIMDLLBRDATA_ipd : std_logic_vector(63 downto 0); signal CRMCORECLKDLO_ipd : std_ulogic; signal CRMCORECLK_ipd : std_ulogic; signal CRMUSERCLK_ipd : std_ulogic; signal CRMURSTN_ipd : std_ulogic; signal CRMNVRSTN_ipd : std_ulogic; signal CRMMGMTRSTN_ipd : std_ulogic; signal CRMUSERCFGRSTN_ipd : std_ulogic; signal CRMMACRSTN_ipd : std_ulogic; signal CRMLINKRSTN_ipd : std_ulogic; signal CRMTXHOTRESETN_ipd : std_ulogic; signal CRMCFGBRIDGEHOTRESET_ipd : std_ulogic; signal LLKTXDATA_ipd : std_logic_vector(63 downto 0); signal LLKTXSRCRDYN_ipd : std_ulogic; signal LLKTXSRCDSCN_ipd : std_ulogic; signal LLKTXCOMPLETEN_ipd : std_ulogic; signal LLKTXSOFN_ipd : std_ulogic; signal LLKTXEOFN_ipd : std_ulogic; signal LLKTXSOPN_ipd : std_ulogic; signal LLKTXEOPN_ipd : std_ulogic; signal LLKTXENABLEN_ipd : std_logic_vector(1 downto 0); signal LLKTXCHTC_ipd : std_logic_vector(2 downto 0); signal LLKTXCHFIFO_ipd : std_logic_vector(1 downto 0); signal LLKTXCREATEECRCN_ipd : std_ulogic; signal LLKTX4DWHEADERN_ipd : std_ulogic; signal LLKRXDSTREQN_ipd : std_ulogic; signal LLKRXCHTC_ipd : std_logic_vector(2 downto 0); signal LLKRXCHFIFO_ipd : std_logic_vector(1 downto 0); signal LLKRXDSTCONTREQN_ipd : std_ulogic; signal MGMTWDATA_ipd : std_logic_vector(31 downto 0); signal MGMTBWREN_ipd : std_logic_vector(3 downto 0); signal MGMTWREN_ipd : std_ulogic; signal MGMTADDR_ipd : std_logic_vector(10 downto 0); signal MGMTRDEN_ipd : std_ulogic; signal MGMTSTATSCREDITSEL_ipd : std_logic_vector(6 downto 0); signal MAINPOWER_ipd : std_ulogic; signal AUXPOWER_ipd : std_ulogic; signal L0TLLINKRETRAIN_ipd : std_ulogic; signal CFGNEGOTIATEDLINKWIDTH_ipd : std_logic_vector(5 downto 0); signal CROSSLINKSEED_ipd : std_ulogic; signal COMPLIANCEAVOID_ipd : std_ulogic; signal L0VC0PREVIEWEXPAND_ipd : std_ulogic; signal L0CFGVCID_ipd : std_logic_vector(23 downto 0); signal L0CFGLOOPBACKMASTER_ipd : std_ulogic; signal L0REPLAYTIMERADJUSTMENT_ipd : std_logic_vector(11 downto 0); signal L0ACKNAKTIMERADJUSTMENT_ipd : std_logic_vector(11 downto 0); signal L0DLLHOLDLINKUP_ipd : std_ulogic; signal L0CFGASSTATECHANGECMD_ipd : std_logic_vector(3 downto 0); signal L0CFGASSPANTREEOWNEDSTATE_ipd : std_ulogic; signal L0ASE_ipd : std_ulogic; signal L0ASTURNPOOLBITSCONSUMED_ipd : std_logic_vector(2 downto 0); signal L0ASPORTCOUNT_ipd : std_logic_vector(7 downto 0); signal L0CFGVCENABLE_ipd : std_logic_vector(7 downto 0); signal L0CFGNEGOTIATEDMAXP_ipd : std_logic_vector(2 downto 0); signal L0CFGDISABLESCRAMBLE_ipd : std_ulogic; signal L0CFGEXTENDEDSYNC_ipd : std_ulogic; signal L0CFGLINKDISABLE_ipd : std_ulogic; signal L0PORTNUMBER_ipd : std_logic_vector(7 downto 0); signal L0SENDUNLOCKMESSAGE_ipd : std_ulogic; signal L0ALLDOWNRXPORTSINL0S_ipd : std_ulogic; signal L0UPSTREAMRXPORTINL0S_ipd : std_ulogic; signal L0TRANSACTIONSPENDING_ipd : std_ulogic; signal L0ALLDOWNPORTSINL1_ipd : std_ulogic; signal L0FWDCORRERRIN_ipd : std_ulogic; signal L0FWDFATALERRIN_ipd : std_ulogic; signal L0FWDNONFATALERRIN_ipd : std_ulogic; signal L0SETCOMPLETERABORTERROR_ipd : std_ulogic; signal L0SETDETECTEDCORRERROR_ipd : std_ulogic; signal L0SETDETECTEDFATALERROR_ipd : std_ulogic; signal L0SETDETECTEDNONFATALERROR_ipd : std_ulogic; signal L0SETLINKDETECTEDPARITYERROR_ipd : std_ulogic; signal L0SETLINKMASTERDATAPARITY_ipd : std_ulogic; signal L0SETLINKRECEIVEDMASTERABORT_ipd : std_ulogic; signal L0SETLINKRECEIVEDTARGETABORT_ipd : std_ulogic; signal L0SETLINKSYSTEMERROR_ipd : std_ulogic; signal L0SETLINKSIGNALLEDTARGETABORT_ipd : std_ulogic; signal L0SETUSERDETECTEDPARITYERROR_ipd : std_ulogic; signal L0SETUSERMASTERDATAPARITY_ipd : std_ulogic; signal L0SETUSERRECEIVEDMASTERABORT_ipd : std_ulogic; signal L0SETUSERRECEIVEDTARGETABORT_ipd : std_ulogic; signal L0SETUSERSYSTEMERROR_ipd : std_ulogic; signal L0SETUSERSIGNALLEDTARGETABORT_ipd : std_ulogic; signal L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd : std_ulogic; signal L0SETCOMPLETIONTIMEOUTCORRERROR_ipd : std_ulogic; signal L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd : std_ulogic; signal L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd : std_ulogic; signal L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd : std_ulogic; signal L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd : std_ulogic; signal L0PACKETHEADERFROMUSER_ipd : std_logic_vector(127 downto 0); signal L0LEGACYINTFUNCT0_ipd : std_ulogic; signal L0FWDASSERTINTALEGACYINT_ipd : std_ulogic; signal L0FWDASSERTINTBLEGACYINT_ipd : std_ulogic; signal L0FWDASSERTINTCLEGACYINT_ipd : std_ulogic; signal L0FWDASSERTINTDLEGACYINT_ipd : std_ulogic; signal L0FWDDEASSERTINTALEGACYINT_ipd : std_ulogic; signal L0FWDDEASSERTINTBLEGACYINT_ipd : std_ulogic; signal L0FWDDEASSERTINTCLEGACYINT_ipd : std_ulogic; signal L0FWDDEASSERTINTDLEGACYINT_ipd : std_ulogic; signal L0MSIREQUEST0_ipd : std_logic_vector(3 downto 0); signal L0ELECTROMECHANICALINTERLOCKENGAGED_ipd : std_ulogic; signal L0MRLSENSORCLOSEDN_ipd : std_ulogic; signal L0POWERFAULTDETECTED_ipd : std_ulogic; signal L0PRESENCEDETECTSLOTEMPTYN_ipd : std_ulogic; signal L0ATTENTIONBUTTONPRESSED_ipd : std_ulogic; signal L0TXBEACON_ipd : std_ulogic; signal L0WAKEN_ipd : std_ulogic; signal L0PMEREQIN_ipd : std_ulogic; signal L0ROOTTURNOFFREQ_ipd : std_ulogic; signal L0TXCFGPM_ipd : std_ulogic; signal L0TXCFGPMTYPE_ipd : std_logic_vector(2 downto 0); signal L0PWRNEWSTATEREQ_ipd : std_ulogic; signal L0PWRNEXTLINKSTATE_ipd : std_logic_vector(1 downto 0); signal L0CFGL0SENTRYSUP_ipd : std_ulogic; signal L0CFGL0SENTRYENABLE_ipd : std_ulogic; signal L0CFGL0SEXITLAT_ipd : std_logic_vector(2 downto 0); signal L0TXTLTLPDATA_ipd : std_logic_vector(63 downto 0); signal L0TXTLTLPEND_ipd : std_logic_vector(1 downto 0); signal L0TXTLTLPENABLE_ipd : std_logic_vector(1 downto 0); signal L0TXTLTLPEDB_ipd : std_ulogic; signal L0TXTLTLPREQ_ipd : std_ulogic; signal L0TXTLTLPREQEND_ipd : std_ulogic; signal L0TXTLTLPWIDTH_ipd : std_ulogic; signal L0TXTLTLPLATENCY_ipd : std_logic_vector(3 downto 0); signal L0TLASFCCREDSTARVATION_ipd : std_ulogic; signal L0TXTLSBFCDATA_ipd : std_logic_vector(18 downto 0); signal L0TXTLSBFCUPDATE_ipd : std_ulogic; signal L0TXTLFCNPOSTBYPCRED_ipd : std_logic_vector(191 downto 0); signal L0TXTLFCNPOSTBYPUPDATE_ipd : std_logic_vector(15 downto 0); signal L0TXTLFCPOSTORDCRED_ipd : std_logic_vector(159 downto 0); signal L0TXTLFCPOSTORDUPDATE_ipd : std_logic_vector(15 downto 0); signal L0TXTLFCCMPLMCCRED_ipd : std_logic_vector(159 downto 0); signal L0TXTLFCCMPLMCUPDATE_ipd : std_logic_vector(15 downto 0); signal L0RXTLTLPNONINITIALIZEDVC_ipd : std_logic_vector(7 downto 0); signal PIPERXELECIDLEL0_indelay : std_ulogic; signal PIPERXSTATUSL0_indelay : std_logic_vector(2 downto 0); signal PIPERXDATAL0_indelay : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL0_indelay : std_ulogic; signal PIPERXDATAKL0_indelay : std_ulogic; signal PIPERXVALIDL0_indelay : std_ulogic; signal PIPERXCHANISALIGNEDL0_indelay : std_ulogic; signal PIPERXELECIDLEL1_indelay : std_ulogic; signal PIPERXSTATUSL1_indelay : std_logic_vector(2 downto 0); signal PIPERXDATAL1_indelay : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL1_indelay : std_ulogic; signal PIPERXDATAKL1_indelay : std_ulogic; signal PIPERXVALIDL1_indelay : std_ulogic; signal PIPERXCHANISALIGNEDL1_indelay : std_ulogic; signal PIPERXELECIDLEL2_indelay : std_ulogic; signal PIPERXSTATUSL2_indelay : std_logic_vector(2 downto 0); signal PIPERXDATAL2_indelay : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL2_indelay : std_ulogic; signal PIPERXDATAKL2_indelay : std_ulogic; signal PIPERXVALIDL2_indelay : std_ulogic; signal PIPERXCHANISALIGNEDL2_indelay : std_ulogic; signal PIPERXELECIDLEL3_indelay : std_ulogic; signal PIPERXSTATUSL3_indelay : std_logic_vector(2 downto 0); signal PIPERXDATAL3_indelay : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL3_indelay : std_ulogic; signal PIPERXDATAKL3_indelay : std_ulogic; signal PIPERXVALIDL3_indelay : std_ulogic; signal PIPERXCHANISALIGNEDL3_indelay : std_ulogic; signal PIPERXELECIDLEL4_indelay : std_ulogic; signal PIPERXSTATUSL4_indelay : std_logic_vector(2 downto 0); signal PIPERXDATAL4_indelay : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL4_indelay : std_ulogic; signal PIPERXDATAKL4_indelay : std_ulogic; signal PIPERXVALIDL4_indelay : std_ulogic; signal PIPERXCHANISALIGNEDL4_indelay : std_ulogic; signal PIPERXELECIDLEL5_indelay : std_ulogic; signal PIPERXSTATUSL5_indelay : std_logic_vector(2 downto 0); signal PIPERXDATAL5_indelay : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL5_indelay : std_ulogic; signal PIPERXDATAKL5_indelay : std_ulogic; signal PIPERXVALIDL5_indelay : std_ulogic; signal PIPERXCHANISALIGNEDL5_indelay : std_ulogic; signal PIPERXELECIDLEL6_indelay : std_ulogic; signal PIPERXSTATUSL6_indelay : std_logic_vector(2 downto 0); signal PIPERXDATAL6_indelay : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL6_indelay : std_ulogic; signal PIPERXDATAKL6_indelay : std_ulogic; signal PIPERXVALIDL6_indelay : std_ulogic; signal PIPERXCHANISALIGNEDL6_indelay : std_ulogic; signal PIPERXELECIDLEL7_indelay : std_ulogic; signal PIPERXSTATUSL7_indelay : std_logic_vector(2 downto 0); signal PIPERXDATAL7_indelay : std_logic_vector(7 downto 0); signal PIPEPHYSTATUSL7_indelay : std_ulogic; signal PIPERXDATAKL7_indelay : std_ulogic; signal PIPERXVALIDL7_indelay : std_ulogic; signal PIPERXCHANISALIGNEDL7_indelay : std_ulogic; signal MIMRXBRDATA_indelay : std_logic_vector(63 downto 0); signal CRMCORECLKRXO_indelay : std_ulogic; signal CRMUSERCLKRXO_indelay : std_ulogic; signal MIMTXBRDATA_indelay : std_logic_vector(63 downto 0); signal CRMCORECLKTXO_indelay : std_ulogic; signal CRMUSERCLKTXO_indelay : std_ulogic; signal MIMDLLBRDATA_indelay : std_logic_vector(63 downto 0); signal CRMCORECLKDLO_indelay : std_ulogic; signal CRMCORECLK_indelay : std_ulogic; signal CRMUSERCLK_indelay : std_ulogic; signal CRMURSTN_indelay : std_ulogic; signal CRMNVRSTN_indelay : std_ulogic; signal CRMMGMTRSTN_indelay : std_ulogic; signal CRMUSERCFGRSTN_indelay : std_ulogic; signal CRMMACRSTN_indelay : std_ulogic; signal CRMLINKRSTN_indelay : std_ulogic; signal CRMTXHOTRESETN_indelay : std_ulogic; signal CRMCFGBRIDGEHOTRESET_indelay : std_ulogic; signal LLKTXDATA_indelay : std_logic_vector(63 downto 0); signal LLKTXSRCRDYN_indelay : std_ulogic; signal LLKTXSRCDSCN_indelay : std_ulogic; signal LLKTXCOMPLETEN_indelay : std_ulogic; signal LLKTXSOFN_indelay : std_ulogic; signal LLKTXEOFN_indelay : std_ulogic; signal LLKTXSOPN_indelay : std_ulogic; signal LLKTXEOPN_indelay : std_ulogic; signal LLKTXENABLEN_indelay : std_logic_vector(1 downto 0); signal LLKTXCHTC_indelay : std_logic_vector(2 downto 0); signal LLKTXCHFIFO_indelay : std_logic_vector(1 downto 0); signal LLKTXCREATEECRCN_indelay : std_ulogic; signal LLKTX4DWHEADERN_indelay : std_ulogic; signal LLKRXDSTREQN_indelay : std_ulogic; signal LLKRXCHTC_indelay : std_logic_vector(2 downto 0); signal LLKRXCHFIFO_indelay : std_logic_vector(1 downto 0); signal LLKRXDSTCONTREQN_indelay : std_ulogic; signal MGMTWDATA_indelay : std_logic_vector(31 downto 0); signal MGMTBWREN_indelay : std_logic_vector(3 downto 0); signal MGMTWREN_indelay : std_ulogic; signal MGMTADDR_indelay : std_logic_vector(10 downto 0); signal MGMTRDEN_indelay : std_ulogic; signal MGMTSTATSCREDITSEL_indelay : std_logic_vector(6 downto 0); signal MAINPOWER_indelay : std_ulogic; signal AUXPOWER_indelay : std_ulogic; signal L0TLLINKRETRAIN_indelay : std_ulogic; signal CFGNEGOTIATEDLINKWIDTH_indelay : std_logic_vector(5 downto 0); signal CROSSLINKSEED_indelay : std_ulogic; signal COMPLIANCEAVOID_indelay : std_ulogic; signal L0VC0PREVIEWEXPAND_indelay : std_ulogic; signal L0CFGVCID_indelay : std_logic_vector(23 downto 0); signal L0CFGLOOPBACKMASTER_indelay : std_ulogic; signal L0REPLAYTIMERADJUSTMENT_indelay : std_logic_vector(11 downto 0); signal L0ACKNAKTIMERADJUSTMENT_indelay : std_logic_vector(11 downto 0); signal L0DLLHOLDLINKUP_indelay : std_ulogic; signal L0CFGASSTATECHANGECMD_indelay : std_logic_vector(3 downto 0); signal L0CFGASSPANTREEOWNEDSTATE_indelay : std_ulogic; signal L0ASE_indelay : std_ulogic; signal L0ASTURNPOOLBITSCONSUMED_indelay : std_logic_vector(2 downto 0); signal L0ASPORTCOUNT_indelay : std_logic_vector(7 downto 0); signal L0CFGVCENABLE_indelay : std_logic_vector(7 downto 0); signal L0CFGNEGOTIATEDMAXP_indelay : std_logic_vector(2 downto 0); signal L0CFGDISABLESCRAMBLE_indelay : std_ulogic; signal L0CFGEXTENDEDSYNC_indelay : std_ulogic; signal L0CFGLINKDISABLE_indelay : std_ulogic; signal L0PORTNUMBER_indelay : std_logic_vector(7 downto 0); signal L0SENDUNLOCKMESSAGE_indelay : std_ulogic; signal L0ALLDOWNRXPORTSINL0S_indelay : std_ulogic; signal L0UPSTREAMRXPORTINL0S_indelay : std_ulogic; signal L0TRANSACTIONSPENDING_indelay : std_ulogic; signal L0ALLDOWNPORTSINL1_indelay : std_ulogic; signal L0FWDCORRERRIN_indelay : std_ulogic; signal L0FWDFATALERRIN_indelay : std_ulogic; signal L0FWDNONFATALERRIN_indelay : std_ulogic; signal L0SETCOMPLETERABORTERROR_indelay : std_ulogic; signal L0SETDETECTEDCORRERROR_indelay : std_ulogic; signal L0SETDETECTEDFATALERROR_indelay : std_ulogic; signal L0SETDETECTEDNONFATALERROR_indelay : std_ulogic; signal L0SETLINKDETECTEDPARITYERROR_indelay : std_ulogic; signal L0SETLINKMASTERDATAPARITY_indelay : std_ulogic; signal L0SETLINKRECEIVEDMASTERABORT_indelay : std_ulogic; signal L0SETLINKRECEIVEDTARGETABORT_indelay : std_ulogic; signal L0SETLINKSYSTEMERROR_indelay : std_ulogic; signal L0SETLINKSIGNALLEDTARGETABORT_indelay : std_ulogic; signal L0SETUSERDETECTEDPARITYERROR_indelay : std_ulogic; signal L0SETUSERMASTERDATAPARITY_indelay : std_ulogic; signal L0SETUSERRECEIVEDMASTERABORT_indelay : std_ulogic; signal L0SETUSERRECEIVEDTARGETABORT_indelay : std_ulogic; signal L0SETUSERSYSTEMERROR_indelay : std_ulogic; signal L0SETUSERSIGNALLEDTARGETABORT_indelay : std_ulogic; signal L0SETCOMPLETIONTIMEOUTUNCORRERROR_indelay : std_ulogic; signal L0SETCOMPLETIONTIMEOUTCORRERROR_indelay : std_ulogic; signal L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_indelay : std_ulogic; signal L0SETUNEXPECTEDCOMPLETIONCORRERROR_indelay : std_ulogic; signal L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_indelay : std_ulogic; signal L0SETUNSUPPORTEDREQUESTOTHERERROR_indelay : std_ulogic; signal L0PACKETHEADERFROMUSER_indelay : std_logic_vector(127 downto 0); signal L0LEGACYINTFUNCT0_indelay : std_ulogic; signal L0FWDASSERTINTALEGACYINT_indelay : std_ulogic; signal L0FWDASSERTINTBLEGACYINT_indelay : std_ulogic; signal L0FWDASSERTINTCLEGACYINT_indelay : std_ulogic; signal L0FWDASSERTINTDLEGACYINT_indelay : std_ulogic; signal L0FWDDEASSERTINTALEGACYINT_indelay : std_ulogic; signal L0FWDDEASSERTINTBLEGACYINT_indelay : std_ulogic; signal L0FWDDEASSERTINTCLEGACYINT_indelay : std_ulogic; signal L0FWDDEASSERTINTDLEGACYINT_indelay : std_ulogic; signal L0MSIREQUEST0_indelay : std_logic_vector(3 downto 0); signal L0ELECTROMECHANICALINTERLOCKENGAGED_indelay : std_ulogic; signal L0MRLSENSORCLOSEDN_indelay : std_ulogic; signal L0POWERFAULTDETECTED_indelay : std_ulogic; signal L0PRESENCEDETECTSLOTEMPTYN_indelay : std_ulogic; signal L0ATTENTIONBUTTONPRESSED_indelay : std_ulogic; signal L0TXBEACON_indelay : std_ulogic; signal L0WAKEN_indelay : std_ulogic; signal L0PMEREQIN_indelay : std_ulogic; signal L0ROOTTURNOFFREQ_indelay : std_ulogic; signal L0TXCFGPM_indelay : std_ulogic; signal L0TXCFGPMTYPE_indelay : std_logic_vector(2 downto 0); signal L0PWRNEWSTATEREQ_indelay : std_ulogic; signal L0PWRNEXTLINKSTATE_indelay : std_logic_vector(1 downto 0); signal L0CFGL0SENTRYSUP_indelay : std_ulogic; signal L0CFGL0SENTRYENABLE_indelay : std_ulogic; signal L0CFGL0SEXITLAT_indelay : std_logic_vector(2 downto 0); signal L0TXTLTLPDATA_indelay : std_logic_vector(63 downto 0); signal L0TXTLTLPEND_indelay : std_logic_vector(1 downto 0); signal L0TXTLTLPENABLE_indelay : std_logic_vector(1 downto 0); signal L0TXTLTLPEDB_indelay : std_ulogic; signal L0TXTLTLPREQ_indelay : std_ulogic; signal L0TXTLTLPREQEND_indelay : std_ulogic; signal L0TXTLTLPWIDTH_indelay : std_ulogic; signal L0TXTLTLPLATENCY_indelay : std_logic_vector(3 downto 0); signal L0TLASFCCREDSTARVATION_indelay : std_ulogic; signal L0TXTLSBFCDATA_indelay : std_logic_vector(18 downto 0); signal L0TXTLSBFCUPDATE_indelay : std_ulogic; signal L0TXTLFCNPOSTBYPCRED_indelay : std_logic_vector(191 downto 0); signal L0TXTLFCNPOSTBYPUPDATE_indelay : std_logic_vector(15 downto 0); signal L0TXTLFCPOSTORDCRED_indelay : std_logic_vector(159 downto 0); signal L0TXTLFCPOSTORDUPDATE_indelay : std_logic_vector(15 downto 0); signal L0TXTLFCCMPLMCCRED_indelay : std_logic_vector(159 downto 0); signal L0TXTLFCCMPLMCUPDATE_indelay : std_logic_vector(15 downto 0); signal L0RXTLTLPNONINITIALIZEDVC_indelay : std_logic_vector(7 downto 0); begin BUSMASTERENABLE_out <= BUSMASTERENABLE_outdelay after OUT_DELAY; CRMDOHOTRESETN_out <= CRMDOHOTRESETN_outdelay after OUT_DELAY; CRMPWRSOFTRESETN_out <= CRMPWRSOFTRESETN_outdelay after OUT_DELAY; CRMRXHOTRESETN_out <= CRMRXHOTRESETN_outdelay after OUT_DELAY; DLLTXPMDLLPOUTSTANDING_out <= DLLTXPMDLLPOUTSTANDING_outdelay after OUT_DELAY; INTERRUPTDISABLE_out <= INTERRUPTDISABLE_outdelay after OUT_DELAY; IOSPACEENABLE_out <= IOSPACEENABLE_outdelay after OUT_DELAY; L0ASAUTONOMOUSINITCOMPLETED_out <= L0ASAUTONOMOUSINITCOMPLETED_outdelay after OUT_DELAY; L0ATTENTIONINDICATORCONTROL_out <= L0ATTENTIONINDICATORCONTROL_outdelay after OUT_DELAY; L0CFGLOOPBACKACK_out <= L0CFGLOOPBACKACK_outdelay after OUT_DELAY; L0COMPLETERID_out <= L0COMPLETERID_outdelay after OUT_DELAY; L0CORRERRMSGRCVD_out <= L0CORRERRMSGRCVD_outdelay after OUT_DELAY; L0DLLASRXSTATE_out <= L0DLLASRXSTATE_outdelay after OUT_DELAY; L0DLLASTXSTATE_out <= L0DLLASTXSTATE_outdelay after OUT_DELAY; L0DLLERRORVECTOR_out <= L0DLLERRORVECTOR_outdelay after OUT_DELAY; L0DLLRXACKOUTSTANDING_out <= L0DLLRXACKOUTSTANDING_outdelay after OUT_DELAY; L0DLLTXNONFCOUTSTANDING_out <= L0DLLTXNONFCOUTSTANDING_outdelay after OUT_DELAY; L0DLLTXOUTSTANDING_out <= L0DLLTXOUTSTANDING_outdelay after OUT_DELAY; L0DLLVCSTATUS_out <= L0DLLVCSTATUS_outdelay after OUT_DELAY; L0DLUPDOWN_out <= L0DLUPDOWN_outdelay after OUT_DELAY; L0ERRMSGREQID_out <= L0ERRMSGREQID_outdelay after OUT_DELAY; L0FATALERRMSGRCVD_out <= L0FATALERRMSGRCVD_outdelay after OUT_DELAY; L0FIRSTCFGWRITEOCCURRED_out <= L0FIRSTCFGWRITEOCCURRED_outdelay after OUT_DELAY; L0FWDCORRERROUT_out <= L0FWDCORRERROUT_outdelay after OUT_DELAY; L0FWDFATALERROUT_out <= L0FWDFATALERROUT_outdelay after OUT_DELAY; L0FWDNONFATALERROUT_out <= L0FWDNONFATALERROUT_outdelay after OUT_DELAY; L0LTSSMSTATE_out <= L0LTSSMSTATE_outdelay after OUT_DELAY; L0MACENTEREDL0_out <= L0MACENTEREDL0_outdelay after OUT_DELAY; L0MACLINKTRAINING_out <= L0MACLINKTRAINING_outdelay after OUT_DELAY; L0MACLINKUP_out <= L0MACLINKUP_outdelay after OUT_DELAY; L0MACNEGOTIATEDLINKWIDTH_out <= L0MACNEGOTIATEDLINKWIDTH_outdelay after OUT_DELAY; L0MACNEWSTATEACK_out <= L0MACNEWSTATEACK_outdelay after OUT_DELAY; L0MACRXL0SSTATE_out <= L0MACRXL0SSTATE_outdelay after OUT_DELAY; L0MACUPSTREAMDOWNSTREAM_out <= L0MACUPSTREAMDOWNSTREAM_outdelay after OUT_DELAY; L0MCFOUND_out <= L0MCFOUND_outdelay after OUT_DELAY; L0MSIENABLE0_out <= L0MSIENABLE0_outdelay after OUT_DELAY; L0MULTIMSGEN0_out <= L0MULTIMSGEN0_outdelay after OUT_DELAY; L0NONFATALERRMSGRCVD_out <= L0NONFATALERRMSGRCVD_outdelay after OUT_DELAY; L0PMEACK_out <= L0PMEACK_outdelay after OUT_DELAY; L0PMEEN_out <= L0PMEEN_outdelay after OUT_DELAY; L0PMEREQOUT_out <= L0PMEREQOUT_outdelay after OUT_DELAY; L0POWERCONTROLLERCONTROL_out <= L0POWERCONTROLLERCONTROL_outdelay after OUT_DELAY; L0POWERINDICATORCONTROL_out <= L0POWERINDICATORCONTROL_outdelay after OUT_DELAY; L0PWRINHIBITTRANSFERS_out <= L0PWRINHIBITTRANSFERS_outdelay after OUT_DELAY; L0PWRL1STATE_out <= L0PWRL1STATE_outdelay after OUT_DELAY; L0PWRL23READYDEVICE_out <= L0PWRL23READYDEVICE_outdelay after OUT_DELAY; L0PWRL23READYSTATE_out <= L0PWRL23READYSTATE_outdelay after OUT_DELAY; L0PWRSTATE0_out <= L0PWRSTATE0_outdelay after OUT_DELAY; L0PWRTURNOFFREQ_out <= L0PWRTURNOFFREQ_outdelay after OUT_DELAY; L0PWRTXL0SSTATE_out <= L0PWRTXL0SSTATE_outdelay after OUT_DELAY; L0RECEIVEDASSERTINTALEGACYINT_out <= L0RECEIVEDASSERTINTALEGACYINT_outdelay after OUT_DELAY; L0RECEIVEDASSERTINTBLEGACYINT_out <= L0RECEIVEDASSERTINTBLEGACYINT_outdelay after OUT_DELAY; L0RECEIVEDASSERTINTCLEGACYINT_out <= L0RECEIVEDASSERTINTCLEGACYINT_outdelay after OUT_DELAY; L0RECEIVEDASSERTINTDLEGACYINT_out <= L0RECEIVEDASSERTINTDLEGACYINT_outdelay after OUT_DELAY; L0RECEIVEDDEASSERTINTALEGACYINT_out <= L0RECEIVEDDEASSERTINTALEGACYINT_outdelay after OUT_DELAY; L0RECEIVEDDEASSERTINTBLEGACYINT_out <= L0RECEIVEDDEASSERTINTBLEGACYINT_outdelay after OUT_DELAY; L0RECEIVEDDEASSERTINTCLEGACYINT_out <= L0RECEIVEDDEASSERTINTCLEGACYINT_outdelay after OUT_DELAY; L0RECEIVEDDEASSERTINTDLEGACYINT_out <= L0RECEIVEDDEASSERTINTDLEGACYINT_outdelay after OUT_DELAY; L0RXBEACON_out <= L0RXBEACON_outdelay after OUT_DELAY; L0RXDLLFCCMPLMCCRED_out <= L0RXDLLFCCMPLMCCRED_outdelay after OUT_DELAY; L0RXDLLFCCMPLMCUPDATE_out <= L0RXDLLFCCMPLMCUPDATE_outdelay after OUT_DELAY; L0RXDLLFCNPOSTBYPCRED_out <= L0RXDLLFCNPOSTBYPCRED_outdelay after OUT_DELAY; L0RXDLLFCNPOSTBYPUPDATE_out <= L0RXDLLFCNPOSTBYPUPDATE_outdelay after OUT_DELAY; L0RXDLLFCPOSTORDCRED_out <= L0RXDLLFCPOSTORDCRED_outdelay after OUT_DELAY; L0RXDLLFCPOSTORDUPDATE_out <= L0RXDLLFCPOSTORDUPDATE_outdelay after OUT_DELAY; L0RXDLLPMTYPE_out <= L0RXDLLPMTYPE_outdelay after OUT_DELAY; L0RXDLLPM_out <= L0RXDLLPM_outdelay after OUT_DELAY; L0RXDLLSBFCDATA_out <= L0RXDLLSBFCDATA_outdelay after OUT_DELAY; L0RXDLLSBFCUPDATE_out <= L0RXDLLSBFCUPDATE_outdelay after OUT_DELAY; L0RXDLLTLPECRCOK_out <= L0RXDLLTLPECRCOK_outdelay after OUT_DELAY; L0RXDLLTLPEND_out <= L0RXDLLTLPEND_outdelay after OUT_DELAY; L0RXMACLINKERROR_out <= L0RXMACLINKERROR_outdelay after OUT_DELAY; L0STATSCFGOTHERRECEIVED_out <= L0STATSCFGOTHERRECEIVED_outdelay after OUT_DELAY; L0STATSCFGOTHERTRANSMITTED_out <= L0STATSCFGOTHERTRANSMITTED_outdelay after OUT_DELAY; L0STATSCFGRECEIVED_out <= L0STATSCFGRECEIVED_outdelay after OUT_DELAY; L0STATSCFGTRANSMITTED_out <= L0STATSCFGTRANSMITTED_outdelay after OUT_DELAY; L0STATSDLLPRECEIVED_out <= L0STATSDLLPRECEIVED_outdelay after OUT_DELAY; L0STATSDLLPTRANSMITTED_out <= L0STATSDLLPTRANSMITTED_outdelay after OUT_DELAY; L0STATSOSRECEIVED_out <= L0STATSOSRECEIVED_outdelay after OUT_DELAY; L0STATSOSTRANSMITTED_out <= L0STATSOSTRANSMITTED_outdelay after OUT_DELAY; L0STATSTLPRECEIVED_out <= L0STATSTLPRECEIVED_outdelay after OUT_DELAY; L0STATSTLPTRANSMITTED_out <= L0STATSTLPTRANSMITTED_outdelay after OUT_DELAY; L0TOGGLEELECTROMECHANICALINTERLOCK_out <= L0TOGGLEELECTROMECHANICALINTERLOCK_outdelay after OUT_DELAY; L0TRANSFORMEDVC_out <= L0TRANSFORMEDVC_outdelay after OUT_DELAY; L0TXDLLFCCMPLMCUPDATED_out <= L0TXDLLFCCMPLMCUPDATED_outdelay after OUT_DELAY; L0TXDLLFCNPOSTBYPUPDATED_out <= L0TXDLLFCNPOSTBYPUPDATED_outdelay after OUT_DELAY; L0TXDLLFCPOSTORDUPDATED_out <= L0TXDLLFCPOSTORDUPDATED_outdelay after OUT_DELAY; L0TXDLLPMUPDATED_out <= L0TXDLLPMUPDATED_outdelay after OUT_DELAY; L0TXDLLSBFCUPDATED_out <= L0TXDLLSBFCUPDATED_outdelay after OUT_DELAY; L0UCBYPFOUND_out <= L0UCBYPFOUND_outdelay after OUT_DELAY; L0UCORDFOUND_out <= L0UCORDFOUND_outdelay after OUT_DELAY; L0UNLOCKRECEIVED_out <= L0UNLOCKRECEIVED_outdelay after OUT_DELAY; LLKRX4DWHEADERN_out <= LLKRX4DWHEADERN_outdelay after OUT_DELAY; LLKRXCHCOMPLETIONAVAILABLEN_out <= LLKRXCHCOMPLETIONAVAILABLEN_outdelay after OUT_DELAY; LLKRXCHCOMPLETIONPARTIALN_out <= LLKRXCHCOMPLETIONPARTIALN_outdelay after OUT_DELAY; LLKRXCHCONFIGAVAILABLEN_out <= LLKRXCHCONFIGAVAILABLEN_outdelay after OUT_DELAY; LLKRXCHCONFIGPARTIALN_out <= LLKRXCHCONFIGPARTIALN_outdelay after OUT_DELAY; LLKRXCHNONPOSTEDAVAILABLEN_out <= LLKRXCHNONPOSTEDAVAILABLEN_outdelay after OUT_DELAY; LLKRXCHNONPOSTEDPARTIALN_out <= LLKRXCHNONPOSTEDPARTIALN_outdelay after OUT_DELAY; LLKRXCHPOSTEDAVAILABLEN_out <= LLKRXCHPOSTEDAVAILABLEN_outdelay after OUT_DELAY; LLKRXCHPOSTEDPARTIALN_out <= LLKRXCHPOSTEDPARTIALN_outdelay after OUT_DELAY; LLKRXDATA_out <= LLKRXDATA_outdelay after OUT_DELAY; LLKRXECRCBADN_out <= LLKRXECRCBADN_outdelay after OUT_DELAY; LLKRXEOFN_out <= LLKRXEOFN_outdelay after OUT_DELAY; LLKRXEOPN_out <= LLKRXEOPN_outdelay after OUT_DELAY; LLKRXPREFERREDTYPE_out <= LLKRXPREFERREDTYPE_outdelay after OUT_DELAY; LLKRXSOFN_out <= LLKRXSOFN_outdelay after OUT_DELAY; LLKRXSOPN_out <= LLKRXSOPN_outdelay after OUT_DELAY; LLKRXSRCDSCN_out <= LLKRXSRCDSCN_outdelay after OUT_DELAY; LLKRXSRCLASTREQN_out <= LLKRXSRCLASTREQN_outdelay after OUT_DELAY; LLKRXSRCRDYN_out <= LLKRXSRCRDYN_outdelay after OUT_DELAY; LLKRXVALIDN_out <= LLKRXVALIDN_outdelay after OUT_DELAY; LLKTCSTATUS_out <= LLKTCSTATUS_outdelay after OUT_DELAY; LLKTXCHANSPACE_out <= LLKTXCHANSPACE_outdelay after OUT_DELAY; LLKTXCHCOMPLETIONREADYN_out <= LLKTXCHCOMPLETIONREADYN_outdelay after OUT_DELAY; LLKTXCHNONPOSTEDREADYN_out <= LLKTXCHNONPOSTEDREADYN_outdelay after OUT_DELAY; LLKTXCHPOSTEDREADYN_out <= LLKTXCHPOSTEDREADYN_outdelay after OUT_DELAY; LLKTXCONFIGREADYN_out <= LLKTXCONFIGREADYN_outdelay after OUT_DELAY; LLKTXDSTRDYN_out <= LLKTXDSTRDYN_outdelay after OUT_DELAY; MAXPAYLOADSIZE_out <= MAXPAYLOADSIZE_outdelay after OUT_DELAY; MAXREADREQUESTSIZE_out <= MAXREADREQUESTSIZE_outdelay after OUT_DELAY; MEMSPACEENABLE_out <= MEMSPACEENABLE_outdelay after OUT_DELAY; MGMTPSO_out <= MGMTPSO_outdelay after OUT_DELAY; MGMTRDATA_out <= MGMTRDATA_outdelay after OUT_DELAY; MGMTSTATSCREDIT_out <= MGMTSTATSCREDIT_outdelay after OUT_DELAY; MIMDLLBRADD_out <= MIMDLLBRADD_outdelay after OUT_DELAY; MIMDLLBREN_out <= MIMDLLBREN_outdelay after OUT_DELAY; MIMDLLBWADD_out <= MIMDLLBWADD_outdelay after OUT_DELAY; MIMDLLBWDATA_out <= MIMDLLBWDATA_outdelay after OUT_DELAY; MIMDLLBWEN_out <= MIMDLLBWEN_outdelay after OUT_DELAY; MIMRXBRADD_out <= MIMRXBRADD_outdelay after OUT_DELAY; MIMRXBREN_out <= MIMRXBREN_outdelay after OUT_DELAY; MIMRXBWADD_out <= MIMRXBWADD_outdelay after OUT_DELAY; MIMRXBWDATA_out <= MIMRXBWDATA_outdelay after OUT_DELAY; MIMRXBWEN_out <= MIMRXBWEN_outdelay after OUT_DELAY; MIMTXBRADD_out <= MIMTXBRADD_outdelay after OUT_DELAY; MIMTXBREN_out <= MIMTXBREN_outdelay after OUT_DELAY; MIMTXBWADD_out <= MIMTXBWADD_outdelay after OUT_DELAY; MIMTXBWDATA_out <= MIMTXBWDATA_outdelay after OUT_DELAY; MIMTXBWEN_out <= MIMTXBWEN_outdelay after OUT_DELAY; PARITYERRORRESPONSE_out <= PARITYERRORRESPONSE_outdelay after OUT_DELAY; PIPEDESKEWLANESL0_out <= PIPEDESKEWLANESL0_outdelay after OUT_DELAY; PIPEDESKEWLANESL1_out <= PIPEDESKEWLANESL1_outdelay after OUT_DELAY; PIPEDESKEWLANESL2_out <= PIPEDESKEWLANESL2_outdelay after OUT_DELAY; PIPEDESKEWLANESL3_out <= PIPEDESKEWLANESL3_outdelay after OUT_DELAY; PIPEDESKEWLANESL4_out <= PIPEDESKEWLANESL4_outdelay after OUT_DELAY; PIPEDESKEWLANESL5_out <= PIPEDESKEWLANESL5_outdelay after OUT_DELAY; PIPEDESKEWLANESL6_out <= PIPEDESKEWLANESL6_outdelay after OUT_DELAY; PIPEDESKEWLANESL7_out <= PIPEDESKEWLANESL7_outdelay after OUT_DELAY; PIPEPOWERDOWNL0_out <= PIPEPOWERDOWNL0_outdelay after OUT_DELAY; PIPEPOWERDOWNL1_out <= PIPEPOWERDOWNL1_outdelay after OUT_DELAY; PIPEPOWERDOWNL2_out <= PIPEPOWERDOWNL2_outdelay after OUT_DELAY; PIPEPOWERDOWNL3_out <= PIPEPOWERDOWNL3_outdelay after OUT_DELAY; PIPEPOWERDOWNL4_out <= PIPEPOWERDOWNL4_outdelay after OUT_DELAY; PIPEPOWERDOWNL5_out <= PIPEPOWERDOWNL5_outdelay after OUT_DELAY; PIPEPOWERDOWNL6_out <= PIPEPOWERDOWNL6_outdelay after OUT_DELAY; PIPEPOWERDOWNL7_out <= PIPEPOWERDOWNL7_outdelay after OUT_DELAY; PIPERESETL0_out <= PIPERESETL0_outdelay after OUT_DELAY; PIPERESETL1_out <= PIPERESETL1_outdelay after OUT_DELAY; PIPERESETL2_out <= PIPERESETL2_outdelay after OUT_DELAY; PIPERESETL3_out <= PIPERESETL3_outdelay after OUT_DELAY; PIPERESETL4_out <= PIPERESETL4_outdelay after OUT_DELAY; PIPERESETL5_out <= PIPERESETL5_outdelay after OUT_DELAY; PIPERESETL6_out <= PIPERESETL6_outdelay after OUT_DELAY; PIPERESETL7_out <= PIPERESETL7_outdelay after OUT_DELAY; PIPERXPOLARITYL0_out <= PIPERXPOLARITYL0_outdelay after OUT_DELAY; PIPERXPOLARITYL1_out <= PIPERXPOLARITYL1_outdelay after OUT_DELAY; PIPERXPOLARITYL2_out <= PIPERXPOLARITYL2_outdelay after OUT_DELAY; PIPERXPOLARITYL3_out <= PIPERXPOLARITYL3_outdelay after OUT_DELAY; PIPERXPOLARITYL4_out <= PIPERXPOLARITYL4_outdelay after OUT_DELAY; PIPERXPOLARITYL5_out <= PIPERXPOLARITYL5_outdelay after OUT_DELAY; PIPERXPOLARITYL6_out <= PIPERXPOLARITYL6_outdelay after OUT_DELAY; PIPERXPOLARITYL7_out <= PIPERXPOLARITYL7_outdelay after OUT_DELAY; PIPETXCOMPLIANCEL0_out <= PIPETXCOMPLIANCEL0_outdelay after OUT_DELAY; PIPETXCOMPLIANCEL1_out <= PIPETXCOMPLIANCEL1_outdelay after OUT_DELAY; PIPETXCOMPLIANCEL2_out <= PIPETXCOMPLIANCEL2_outdelay after OUT_DELAY; PIPETXCOMPLIANCEL3_out <= PIPETXCOMPLIANCEL3_outdelay after OUT_DELAY; PIPETXCOMPLIANCEL4_out <= PIPETXCOMPLIANCEL4_outdelay after OUT_DELAY; PIPETXCOMPLIANCEL5_out <= PIPETXCOMPLIANCEL5_outdelay after OUT_DELAY; PIPETXCOMPLIANCEL6_out <= PIPETXCOMPLIANCEL6_outdelay after OUT_DELAY; PIPETXCOMPLIANCEL7_out <= PIPETXCOMPLIANCEL7_outdelay after OUT_DELAY; PIPETXDATAKL0_out <= PIPETXDATAKL0_outdelay after OUT_DELAY; PIPETXDATAKL1_out <= PIPETXDATAKL1_outdelay after OUT_DELAY; PIPETXDATAKL2_out <= PIPETXDATAKL2_outdelay after OUT_DELAY; PIPETXDATAKL3_out <= PIPETXDATAKL3_outdelay after OUT_DELAY; PIPETXDATAKL4_out <= PIPETXDATAKL4_outdelay after OUT_DELAY; PIPETXDATAKL5_out <= PIPETXDATAKL5_outdelay after OUT_DELAY; PIPETXDATAKL6_out <= PIPETXDATAKL6_outdelay after OUT_DELAY; PIPETXDATAKL7_out <= PIPETXDATAKL7_outdelay after OUT_DELAY; PIPETXDATAL0_out <= PIPETXDATAL0_outdelay after OUT_DELAY; PIPETXDATAL1_out <= PIPETXDATAL1_outdelay after OUT_DELAY; PIPETXDATAL2_out <= PIPETXDATAL2_outdelay after OUT_DELAY; PIPETXDATAL3_out <= PIPETXDATAL3_outdelay after OUT_DELAY; PIPETXDATAL4_out <= PIPETXDATAL4_outdelay after OUT_DELAY; PIPETXDATAL5_out <= PIPETXDATAL5_outdelay after OUT_DELAY; PIPETXDATAL6_out <= PIPETXDATAL6_outdelay after OUT_DELAY; PIPETXDATAL7_out <= PIPETXDATAL7_outdelay after OUT_DELAY; PIPETXDETECTRXLOOPBACKL0_out <= PIPETXDETECTRXLOOPBACKL0_outdelay after OUT_DELAY; PIPETXDETECTRXLOOPBACKL1_out <= PIPETXDETECTRXLOOPBACKL1_outdelay after OUT_DELAY; PIPETXDETECTRXLOOPBACKL2_out <= PIPETXDETECTRXLOOPBACKL2_outdelay after OUT_DELAY; PIPETXDETECTRXLOOPBACKL3_out <= PIPETXDETECTRXLOOPBACKL3_outdelay after OUT_DELAY; PIPETXDETECTRXLOOPBACKL4_out <= PIPETXDETECTRXLOOPBACKL4_outdelay after OUT_DELAY; PIPETXDETECTRXLOOPBACKL5_out <= PIPETXDETECTRXLOOPBACKL5_outdelay after OUT_DELAY; PIPETXDETECTRXLOOPBACKL6_out <= PIPETXDETECTRXLOOPBACKL6_outdelay after OUT_DELAY; PIPETXDETECTRXLOOPBACKL7_out <= PIPETXDETECTRXLOOPBACKL7_outdelay after OUT_DELAY; PIPETXELECIDLEL0_out <= PIPETXELECIDLEL0_outdelay after OUT_DELAY; PIPETXELECIDLEL1_out <= PIPETXELECIDLEL1_outdelay after OUT_DELAY; PIPETXELECIDLEL2_out <= PIPETXELECIDLEL2_outdelay after OUT_DELAY; PIPETXELECIDLEL3_out <= PIPETXELECIDLEL3_outdelay after OUT_DELAY; PIPETXELECIDLEL4_out <= PIPETXELECIDLEL4_outdelay after OUT_DELAY; PIPETXELECIDLEL5_out <= PIPETXELECIDLEL5_outdelay after OUT_DELAY; PIPETXELECIDLEL6_out <= PIPETXELECIDLEL6_outdelay after OUT_DELAY; PIPETXELECIDLEL7_out <= PIPETXELECIDLEL7_outdelay after OUT_DELAY; SERRENABLE_out <= SERRENABLE_outdelay after OUT_DELAY; URREPORTINGENABLE_out <= URREPORTINGENABLE_outdelay after OUT_DELAY; CRMCORECLKDLO_ipd <= CRMCORECLKDLO after CLK_DELAY; CRMCORECLKRXO_ipd <= CRMCORECLKRXO after CLK_DELAY; CRMCORECLKTXO_ipd <= CRMCORECLKTXO after CLK_DELAY; CRMCORECLK_ipd <= CRMCORECLK after CLK_DELAY; CRMUSERCLKRXO_ipd <= CRMUSERCLKRXO after CLK_DELAY; CRMUSERCLKTXO_ipd <= CRMUSERCLKTXO after CLK_DELAY; CRMUSERCLK_ipd <= CRMUSERCLK after CLK_DELAY; AUXPOWER_ipd <= AUXPOWER after CLK_DELAY; CFGNEGOTIATEDLINKWIDTH_ipd <= CFGNEGOTIATEDLINKWIDTH after CLK_DELAY; COMPLIANCEAVOID_ipd <= COMPLIANCEAVOID after CLK_DELAY; CRMCFGBRIDGEHOTRESET_ipd <= CRMCFGBRIDGEHOTRESET after CLK_DELAY; CRMLINKRSTN_ipd <= CRMLINKRSTN after CLK_DELAY; CRMMACRSTN_ipd <= CRMMACRSTN after CLK_DELAY; CRMMGMTRSTN_ipd <= CRMMGMTRSTN after CLK_DELAY; CRMNVRSTN_ipd <= CRMNVRSTN after CLK_DELAY; CRMTXHOTRESETN_ipd <= CRMTXHOTRESETN after CLK_DELAY; CRMURSTN_ipd <= CRMURSTN after CLK_DELAY; CRMUSERCFGRSTN_ipd <= CRMUSERCFGRSTN after CLK_DELAY; CROSSLINKSEED_ipd <= CROSSLINKSEED after CLK_DELAY; L0ACKNAKTIMERADJUSTMENT_ipd <= L0ACKNAKTIMERADJUSTMENT after CLK_DELAY; L0ALLDOWNPORTSINL1_ipd <= L0ALLDOWNPORTSINL1 after CLK_DELAY; L0ALLDOWNRXPORTSINL0S_ipd <= L0ALLDOWNRXPORTSINL0S after CLK_DELAY; L0ASE_ipd <= L0ASE after CLK_DELAY; L0ASPORTCOUNT_ipd <= L0ASPORTCOUNT after CLK_DELAY; L0ASTURNPOOLBITSCONSUMED_ipd <= L0ASTURNPOOLBITSCONSUMED after CLK_DELAY; L0ATTENTIONBUTTONPRESSED_ipd <= L0ATTENTIONBUTTONPRESSED after CLK_DELAY; L0CFGASSPANTREEOWNEDSTATE_ipd <= L0CFGASSPANTREEOWNEDSTATE after CLK_DELAY; L0CFGASSTATECHANGECMD_ipd <= L0CFGASSTATECHANGECMD after CLK_DELAY; L0CFGDISABLESCRAMBLE_ipd <= L0CFGDISABLESCRAMBLE after CLK_DELAY; L0CFGEXTENDEDSYNC_ipd <= L0CFGEXTENDEDSYNC after CLK_DELAY; L0CFGL0SENTRYENABLE_ipd <= L0CFGL0SENTRYENABLE after CLK_DELAY; L0CFGL0SENTRYSUP_ipd <= L0CFGL0SENTRYSUP after CLK_DELAY; L0CFGL0SEXITLAT_ipd <= L0CFGL0SEXITLAT after CLK_DELAY; L0CFGLINKDISABLE_ipd <= L0CFGLINKDISABLE after CLK_DELAY; L0CFGLOOPBACKMASTER_ipd <= L0CFGLOOPBACKMASTER after CLK_DELAY; L0CFGNEGOTIATEDMAXP_ipd <= L0CFGNEGOTIATEDMAXP after CLK_DELAY; L0CFGVCENABLE_ipd <= L0CFGVCENABLE after CLK_DELAY; L0CFGVCID_ipd <= L0CFGVCID after CLK_DELAY; L0DLLHOLDLINKUP_ipd <= L0DLLHOLDLINKUP after CLK_DELAY; L0ELECTROMECHANICALINTERLOCKENGAGED_ipd <= L0ELECTROMECHANICALINTERLOCKENGAGED after CLK_DELAY; L0FWDASSERTINTALEGACYINT_ipd <= L0FWDASSERTINTALEGACYINT after CLK_DELAY; L0FWDASSERTINTBLEGACYINT_ipd <= L0FWDASSERTINTBLEGACYINT after CLK_DELAY; L0FWDASSERTINTCLEGACYINT_ipd <= L0FWDASSERTINTCLEGACYINT after CLK_DELAY; L0FWDASSERTINTDLEGACYINT_ipd <= L0FWDASSERTINTDLEGACYINT after CLK_DELAY; L0FWDCORRERRIN_ipd <= L0FWDCORRERRIN after CLK_DELAY; L0FWDDEASSERTINTALEGACYINT_ipd <= L0FWDDEASSERTINTALEGACYINT after CLK_DELAY; L0FWDDEASSERTINTBLEGACYINT_ipd <= L0FWDDEASSERTINTBLEGACYINT after CLK_DELAY; L0FWDDEASSERTINTCLEGACYINT_ipd <= L0FWDDEASSERTINTCLEGACYINT after CLK_DELAY; L0FWDDEASSERTINTDLEGACYINT_ipd <= L0FWDDEASSERTINTDLEGACYINT after CLK_DELAY; L0FWDFATALERRIN_ipd <= L0FWDFATALERRIN after CLK_DELAY; L0FWDNONFATALERRIN_ipd <= L0FWDNONFATALERRIN after CLK_DELAY; L0LEGACYINTFUNCT0_ipd <= L0LEGACYINTFUNCT0 after CLK_DELAY; L0MRLSENSORCLOSEDN_ipd <= L0MRLSENSORCLOSEDN after CLK_DELAY; L0MSIREQUEST0_ipd <= L0MSIREQUEST0 after CLK_DELAY; L0PACKETHEADERFROMUSER_ipd <= L0PACKETHEADERFROMUSER after CLK_DELAY; L0PMEREQIN_ipd <= L0PMEREQIN after CLK_DELAY; L0PORTNUMBER_ipd <= L0PORTNUMBER after CLK_DELAY; L0POWERFAULTDETECTED_ipd <= L0POWERFAULTDETECTED after CLK_DELAY; L0PRESENCEDETECTSLOTEMPTYN_ipd <= L0PRESENCEDETECTSLOTEMPTYN after CLK_DELAY; L0PWRNEWSTATEREQ_ipd <= L0PWRNEWSTATEREQ after CLK_DELAY; L0PWRNEXTLINKSTATE_ipd <= L0PWRNEXTLINKSTATE after CLK_DELAY; L0REPLAYTIMERADJUSTMENT_ipd <= L0REPLAYTIMERADJUSTMENT after CLK_DELAY; L0ROOTTURNOFFREQ_ipd <= L0ROOTTURNOFFREQ after CLK_DELAY; L0RXTLTLPNONINITIALIZEDVC_ipd <= L0RXTLTLPNONINITIALIZEDVC after CLK_DELAY; L0SENDUNLOCKMESSAGE_ipd <= L0SENDUNLOCKMESSAGE after CLK_DELAY; L0SETCOMPLETERABORTERROR_ipd <= L0SETCOMPLETERABORTERROR after CLK_DELAY; L0SETCOMPLETIONTIMEOUTCORRERROR_ipd <= L0SETCOMPLETIONTIMEOUTCORRERROR after CLK_DELAY; L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd <= L0SETCOMPLETIONTIMEOUTUNCORRERROR after CLK_DELAY; L0SETDETECTEDCORRERROR_ipd <= L0SETDETECTEDCORRERROR after CLK_DELAY; L0SETDETECTEDFATALERROR_ipd <= L0SETDETECTEDFATALERROR after CLK_DELAY; L0SETDETECTEDNONFATALERROR_ipd <= L0SETDETECTEDNONFATALERROR after CLK_DELAY; L0SETLINKDETECTEDPARITYERROR_ipd <= L0SETLINKDETECTEDPARITYERROR after CLK_DELAY; L0SETLINKMASTERDATAPARITY_ipd <= L0SETLINKMASTERDATAPARITY after CLK_DELAY; L0SETLINKRECEIVEDMASTERABORT_ipd <= L0SETLINKRECEIVEDMASTERABORT after CLK_DELAY; L0SETLINKRECEIVEDTARGETABORT_ipd <= L0SETLINKRECEIVEDTARGETABORT after CLK_DELAY; L0SETLINKSIGNALLEDTARGETABORT_ipd <= L0SETLINKSIGNALLEDTARGETABORT after CLK_DELAY; L0SETLINKSYSTEMERROR_ipd <= L0SETLINKSYSTEMERROR after CLK_DELAY; L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd <= L0SETUNEXPECTEDCOMPLETIONCORRERROR after CLK_DELAY; L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd <= L0SETUNEXPECTEDCOMPLETIONUNCORRERROR after CLK_DELAY; L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd <= L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR after CLK_DELAY; L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd <= L0SETUNSUPPORTEDREQUESTOTHERERROR after CLK_DELAY; L0SETUSERDETECTEDPARITYERROR_ipd <= L0SETUSERDETECTEDPARITYERROR after CLK_DELAY; L0SETUSERMASTERDATAPARITY_ipd <= L0SETUSERMASTERDATAPARITY after CLK_DELAY; L0SETUSERRECEIVEDMASTERABORT_ipd <= L0SETUSERRECEIVEDMASTERABORT after CLK_DELAY; L0SETUSERRECEIVEDTARGETABORT_ipd <= L0SETUSERRECEIVEDTARGETABORT after CLK_DELAY; L0SETUSERSIGNALLEDTARGETABORT_ipd <= L0SETUSERSIGNALLEDTARGETABORT after CLK_DELAY; L0SETUSERSYSTEMERROR_ipd <= L0SETUSERSYSTEMERROR after CLK_DELAY; L0TLASFCCREDSTARVATION_ipd <= L0TLASFCCREDSTARVATION after CLK_DELAY; L0TLLINKRETRAIN_ipd <= L0TLLINKRETRAIN after CLK_DELAY; L0TRANSACTIONSPENDING_ipd <= L0TRANSACTIONSPENDING after CLK_DELAY; L0TXBEACON_ipd <= L0TXBEACON after CLK_DELAY; L0TXCFGPMTYPE_ipd <= L0TXCFGPMTYPE after CLK_DELAY; L0TXCFGPM_ipd <= L0TXCFGPM after CLK_DELAY; L0TXTLFCCMPLMCCRED_ipd <= L0TXTLFCCMPLMCCRED after CLK_DELAY; L0TXTLFCCMPLMCUPDATE_ipd <= L0TXTLFCCMPLMCUPDATE after CLK_DELAY; L0TXTLFCNPOSTBYPCRED_ipd <= L0TXTLFCNPOSTBYPCRED after CLK_DELAY; L0TXTLFCNPOSTBYPUPDATE_ipd <= L0TXTLFCNPOSTBYPUPDATE after CLK_DELAY; L0TXTLFCPOSTORDCRED_ipd <= L0TXTLFCPOSTORDCRED after CLK_DELAY; L0TXTLFCPOSTORDUPDATE_ipd <= L0TXTLFCPOSTORDUPDATE after CLK_DELAY; L0TXTLSBFCDATA_ipd <= L0TXTLSBFCDATA after CLK_DELAY; L0TXTLSBFCUPDATE_ipd <= L0TXTLSBFCUPDATE after CLK_DELAY; L0TXTLTLPDATA_ipd <= L0TXTLTLPDATA after CLK_DELAY; L0TXTLTLPEDB_ipd <= L0TXTLTLPEDB after CLK_DELAY; L0TXTLTLPENABLE_ipd <= L0TXTLTLPENABLE after CLK_DELAY; L0TXTLTLPEND_ipd <= L0TXTLTLPEND after CLK_DELAY; L0TXTLTLPLATENCY_ipd <= L0TXTLTLPLATENCY after CLK_DELAY; L0TXTLTLPREQEND_ipd <= L0TXTLTLPREQEND after CLK_DELAY; L0TXTLTLPREQ_ipd <= L0TXTLTLPREQ after CLK_DELAY; L0TXTLTLPWIDTH_ipd <= L0TXTLTLPWIDTH after CLK_DELAY; L0UPSTREAMRXPORTINL0S_ipd <= L0UPSTREAMRXPORTINL0S after CLK_DELAY; L0VC0PREVIEWEXPAND_ipd <= L0VC0PREVIEWEXPAND after CLK_DELAY; L0WAKEN_ipd <= L0WAKEN after CLK_DELAY; LLKRXCHFIFO_ipd <= LLKRXCHFIFO after CLK_DELAY; LLKRXCHTC_ipd <= LLKRXCHTC after CLK_DELAY; LLKRXDSTCONTREQN_ipd <= LLKRXDSTCONTREQN after CLK_DELAY; LLKRXDSTREQN_ipd <= LLKRXDSTREQN after CLK_DELAY; LLKTX4DWHEADERN_ipd <= LLKTX4DWHEADERN after CLK_DELAY; LLKTXCHFIFO_ipd <= LLKTXCHFIFO after CLK_DELAY; LLKTXCHTC_ipd <= LLKTXCHTC after CLK_DELAY; LLKTXCOMPLETEN_ipd <= LLKTXCOMPLETEN after CLK_DELAY; LLKTXCREATEECRCN_ipd <= LLKTXCREATEECRCN after CLK_DELAY; LLKTXDATA_ipd <= LLKTXDATA after CLK_DELAY; LLKTXENABLEN_ipd <= LLKTXENABLEN after CLK_DELAY; LLKTXEOFN_ipd <= LLKTXEOFN after CLK_DELAY; LLKTXEOPN_ipd <= LLKTXEOPN after CLK_DELAY; LLKTXSOFN_ipd <= LLKTXSOFN after CLK_DELAY; LLKTXSOPN_ipd <= LLKTXSOPN after CLK_DELAY; LLKTXSRCDSCN_ipd <= LLKTXSRCDSCN after CLK_DELAY; LLKTXSRCRDYN_ipd <= LLKTXSRCRDYN after CLK_DELAY; MAINPOWER_ipd <= MAINPOWER after CLK_DELAY; MGMTADDR_ipd <= MGMTADDR after CLK_DELAY; MGMTBWREN_ipd <= MGMTBWREN after CLK_DELAY; MGMTRDEN_ipd <= MGMTRDEN after CLK_DELAY; MGMTSTATSCREDITSEL_ipd <= MGMTSTATSCREDITSEL after CLK_DELAY; MGMTWDATA_ipd <= MGMTWDATA after CLK_DELAY; MGMTWREN_ipd <= MGMTWREN after CLK_DELAY; MIMDLLBRDATA_ipd <= MIMDLLBRDATA after CLK_DELAY; MIMRXBRDATA_ipd <= MIMRXBRDATA after CLK_DELAY; MIMTXBRDATA_ipd <= MIMTXBRDATA after CLK_DELAY; PIPEPHYSTATUSL0_ipd <= PIPEPHYSTATUSL0 after CLK_DELAY; PIPEPHYSTATUSL1_ipd <= PIPEPHYSTATUSL1 after CLK_DELAY; PIPEPHYSTATUSL2_ipd <= PIPEPHYSTATUSL2 after CLK_DELAY; PIPEPHYSTATUSL3_ipd <= PIPEPHYSTATUSL3 after CLK_DELAY; PIPEPHYSTATUSL4_ipd <= PIPEPHYSTATUSL4 after CLK_DELAY; PIPEPHYSTATUSL5_ipd <= PIPEPHYSTATUSL5 after CLK_DELAY; PIPEPHYSTATUSL6_ipd <= PIPEPHYSTATUSL6 after CLK_DELAY; PIPEPHYSTATUSL7_ipd <= PIPEPHYSTATUSL7 after CLK_DELAY; PIPERXCHANISALIGNEDL0_ipd <= PIPERXCHANISALIGNEDL0 after CLK_DELAY; PIPERXCHANISALIGNEDL1_ipd <= PIPERXCHANISALIGNEDL1 after CLK_DELAY; PIPERXCHANISALIGNEDL2_ipd <= PIPERXCHANISALIGNEDL2 after CLK_DELAY; PIPERXCHANISALIGNEDL3_ipd <= PIPERXCHANISALIGNEDL3 after CLK_DELAY; PIPERXCHANISALIGNEDL4_ipd <= PIPERXCHANISALIGNEDL4 after CLK_DELAY; PIPERXCHANISALIGNEDL5_ipd <= PIPERXCHANISALIGNEDL5 after CLK_DELAY; PIPERXCHANISALIGNEDL6_ipd <= PIPERXCHANISALIGNEDL6 after CLK_DELAY; PIPERXCHANISALIGNEDL7_ipd <= PIPERXCHANISALIGNEDL7 after CLK_DELAY; PIPERXDATAKL0_ipd <= PIPERXDATAKL0 after CLK_DELAY; PIPERXDATAKL1_ipd <= PIPERXDATAKL1 after CLK_DELAY; PIPERXDATAKL2_ipd <= PIPERXDATAKL2 after CLK_DELAY; PIPERXDATAKL3_ipd <= PIPERXDATAKL3 after CLK_DELAY; PIPERXDATAKL4_ipd <= PIPERXDATAKL4 after CLK_DELAY; PIPERXDATAKL5_ipd <= PIPERXDATAKL5 after CLK_DELAY; PIPERXDATAKL6_ipd <= PIPERXDATAKL6 after CLK_DELAY; PIPERXDATAKL7_ipd <= PIPERXDATAKL7 after CLK_DELAY; PIPERXDATAL0_ipd <= PIPERXDATAL0 after CLK_DELAY; PIPERXDATAL1_ipd <= PIPERXDATAL1 after CLK_DELAY; PIPERXDATAL2_ipd <= PIPERXDATAL2 after CLK_DELAY; PIPERXDATAL3_ipd <= PIPERXDATAL3 after CLK_DELAY; PIPERXDATAL4_ipd <= PIPERXDATAL4 after CLK_DELAY; PIPERXDATAL5_ipd <= PIPERXDATAL5 after CLK_DELAY; PIPERXDATAL6_ipd <= PIPERXDATAL6 after CLK_DELAY; PIPERXDATAL7_ipd <= PIPERXDATAL7 after CLK_DELAY; PIPERXELECIDLEL0_ipd <= PIPERXELECIDLEL0 after CLK_DELAY; PIPERXELECIDLEL1_ipd <= PIPERXELECIDLEL1 after CLK_DELAY; PIPERXELECIDLEL2_ipd <= PIPERXELECIDLEL2 after CLK_DELAY; PIPERXELECIDLEL3_ipd <= PIPERXELECIDLEL3 after CLK_DELAY; PIPERXELECIDLEL4_ipd <= PIPERXELECIDLEL4 after CLK_DELAY; PIPERXELECIDLEL5_ipd <= PIPERXELECIDLEL5 after CLK_DELAY; PIPERXELECIDLEL6_ipd <= PIPERXELECIDLEL6 after CLK_DELAY; PIPERXELECIDLEL7_ipd <= PIPERXELECIDLEL7 after CLK_DELAY; PIPERXSTATUSL0_ipd <= PIPERXSTATUSL0 after CLK_DELAY; PIPERXSTATUSL1_ipd <= PIPERXSTATUSL1 after CLK_DELAY; PIPERXSTATUSL2_ipd <= PIPERXSTATUSL2 after CLK_DELAY; PIPERXSTATUSL3_ipd <= PIPERXSTATUSL3 after CLK_DELAY; PIPERXSTATUSL4_ipd <= PIPERXSTATUSL4 after CLK_DELAY; PIPERXSTATUSL5_ipd <= PIPERXSTATUSL5 after CLK_DELAY; PIPERXSTATUSL6_ipd <= PIPERXSTATUSL6 after CLK_DELAY; PIPERXSTATUSL7_ipd <= PIPERXSTATUSL7 after CLK_DELAY; PIPERXVALIDL0_ipd <= PIPERXVALIDL0 after CLK_DELAY; PIPERXVALIDL1_ipd <= PIPERXVALIDL1 after CLK_DELAY; PIPERXVALIDL2_ipd <= PIPERXVALIDL2 after CLK_DELAY; PIPERXVALIDL3_ipd <= PIPERXVALIDL3 after CLK_DELAY; PIPERXVALIDL4_ipd <= PIPERXVALIDL4 after CLK_DELAY; PIPERXVALIDL5_ipd <= PIPERXVALIDL5 after CLK_DELAY; PIPERXVALIDL6_ipd <= PIPERXVALIDL6 after CLK_DELAY; PIPERXVALIDL7_ipd <= PIPERXVALIDL7 after CLK_DELAY; CRMCORECLKDLO_indelay <= CRMCORECLKDLO_ipd after CLK_DELAY; CRMCORECLKRXO_indelay <= CRMCORECLKRXO_ipd after CLK_DELAY; CRMCORECLKTXO_indelay <= CRMCORECLKTXO_ipd after CLK_DELAY; CRMCORECLK_indelay <= CRMCORECLK_ipd after CLK_DELAY; CRMUSERCLKRXO_indelay <= CRMUSERCLKRXO_ipd after CLK_DELAY; CRMUSERCLKTXO_indelay <= CRMUSERCLKTXO_ipd after CLK_DELAY; CRMUSERCLK_indelay <= CRMUSERCLK_ipd after CLK_DELAY; AUXPOWER_indelay <= AUXPOWER_ipd after IN_DELAY; CFGNEGOTIATEDLINKWIDTH_indelay <= CFGNEGOTIATEDLINKWIDTH_ipd after IN_DELAY; COMPLIANCEAVOID_indelay <= COMPLIANCEAVOID_ipd after IN_DELAY; CRMCFGBRIDGEHOTRESET_indelay <= CRMCFGBRIDGEHOTRESET_ipd after IN_DELAY; CRMLINKRSTN_indelay <= CRMLINKRSTN_ipd after IN_DELAY; CRMMACRSTN_indelay <= CRMMACRSTN_ipd after IN_DELAY; CRMMGMTRSTN_indelay <= CRMMGMTRSTN_ipd after IN_DELAY; CRMNVRSTN_indelay <= CRMNVRSTN_ipd after IN_DELAY; CRMTXHOTRESETN_indelay <= CRMTXHOTRESETN_ipd after IN_DELAY; CRMURSTN_indelay <= CRMURSTN_ipd after IN_DELAY; CRMUSERCFGRSTN_indelay <= CRMUSERCFGRSTN_ipd after IN_DELAY; CROSSLINKSEED_indelay <= CROSSLINKSEED_ipd after IN_DELAY; L0ACKNAKTIMERADJUSTMENT_indelay <= L0ACKNAKTIMERADJUSTMENT_ipd after IN_DELAY; L0ALLDOWNPORTSINL1_indelay <= L0ALLDOWNPORTSINL1_ipd after IN_DELAY; L0ALLDOWNRXPORTSINL0S_indelay <= L0ALLDOWNRXPORTSINL0S_ipd after IN_DELAY; L0ASE_indelay <= L0ASE_ipd after IN_DELAY; L0ASPORTCOUNT_indelay <= L0ASPORTCOUNT_ipd after IN_DELAY; L0ASTURNPOOLBITSCONSUMED_indelay <= L0ASTURNPOOLBITSCONSUMED_ipd after IN_DELAY; L0ATTENTIONBUTTONPRESSED_indelay <= L0ATTENTIONBUTTONPRESSED_ipd after IN_DELAY; L0CFGASSPANTREEOWNEDSTATE_indelay <= L0CFGASSPANTREEOWNEDSTATE_ipd after IN_DELAY; L0CFGASSTATECHANGECMD_indelay <= L0CFGASSTATECHANGECMD_ipd after IN_DELAY; L0CFGDISABLESCRAMBLE_indelay <= L0CFGDISABLESCRAMBLE_ipd after IN_DELAY; L0CFGEXTENDEDSYNC_indelay <= L0CFGEXTENDEDSYNC_ipd after IN_DELAY; L0CFGL0SENTRYENABLE_indelay <= L0CFGL0SENTRYENABLE_ipd after IN_DELAY; L0CFGL0SENTRYSUP_indelay <= L0CFGL0SENTRYSUP_ipd after IN_DELAY; L0CFGL0SEXITLAT_indelay <= L0CFGL0SEXITLAT_ipd after IN_DELAY; L0CFGLINKDISABLE_indelay <= L0CFGLINKDISABLE_ipd after IN_DELAY; L0CFGLOOPBACKMASTER_indelay <= L0CFGLOOPBACKMASTER_ipd after IN_DELAY; L0CFGNEGOTIATEDMAXP_indelay <= L0CFGNEGOTIATEDMAXP_ipd after IN_DELAY; L0CFGVCENABLE_indelay <= L0CFGVCENABLE_ipd after IN_DELAY; L0CFGVCID_indelay <= L0CFGVCID_ipd after IN_DELAY; L0DLLHOLDLINKUP_indelay <= L0DLLHOLDLINKUP_ipd after IN_DELAY; L0ELECTROMECHANICALINTERLOCKENGAGED_indelay <= L0ELECTROMECHANICALINTERLOCKENGAGED_ipd after IN_DELAY; L0FWDASSERTINTALEGACYINT_indelay <= L0FWDASSERTINTALEGACYINT_ipd after IN_DELAY; L0FWDASSERTINTBLEGACYINT_indelay <= L0FWDASSERTINTBLEGACYINT_ipd after IN_DELAY; L0FWDASSERTINTCLEGACYINT_indelay <= L0FWDASSERTINTCLEGACYINT_ipd after IN_DELAY; L0FWDASSERTINTDLEGACYINT_indelay <= L0FWDASSERTINTDLEGACYINT_ipd after IN_DELAY; L0FWDCORRERRIN_indelay <= L0FWDCORRERRIN_ipd after IN_DELAY; L0FWDDEASSERTINTALEGACYINT_indelay <= L0FWDDEASSERTINTALEGACYINT_ipd after IN_DELAY; L0FWDDEASSERTINTBLEGACYINT_indelay <= L0FWDDEASSERTINTBLEGACYINT_ipd after IN_DELAY; L0FWDDEASSERTINTCLEGACYINT_indelay <= L0FWDDEASSERTINTCLEGACYINT_ipd after IN_DELAY; L0FWDDEASSERTINTDLEGACYINT_indelay <= L0FWDDEASSERTINTDLEGACYINT_ipd after IN_DELAY; L0FWDFATALERRIN_indelay <= L0FWDFATALERRIN_ipd after IN_DELAY; L0FWDNONFATALERRIN_indelay <= L0FWDNONFATALERRIN_ipd after IN_DELAY; L0LEGACYINTFUNCT0_indelay <= L0LEGACYINTFUNCT0_ipd after IN_DELAY; L0MRLSENSORCLOSEDN_indelay <= L0MRLSENSORCLOSEDN_ipd after IN_DELAY; L0MSIREQUEST0_indelay <= L0MSIREQUEST0_ipd after IN_DELAY; L0PACKETHEADERFROMUSER_indelay <= L0PACKETHEADERFROMUSER_ipd after IN_DELAY; L0PMEREQIN_indelay <= L0PMEREQIN_ipd after IN_DELAY; L0PORTNUMBER_indelay <= L0PORTNUMBER_ipd after IN_DELAY; L0POWERFAULTDETECTED_indelay <= L0POWERFAULTDETECTED_ipd after IN_DELAY; L0PRESENCEDETECTSLOTEMPTYN_indelay <= L0PRESENCEDETECTSLOTEMPTYN_ipd after IN_DELAY; L0PWRNEWSTATEREQ_indelay <= L0PWRNEWSTATEREQ_ipd after IN_DELAY; L0PWRNEXTLINKSTATE_indelay <= L0PWRNEXTLINKSTATE_ipd after IN_DELAY; L0REPLAYTIMERADJUSTMENT_indelay <= L0REPLAYTIMERADJUSTMENT_ipd after IN_DELAY; L0ROOTTURNOFFREQ_indelay <= L0ROOTTURNOFFREQ_ipd after IN_DELAY; L0RXTLTLPNONINITIALIZEDVC_indelay <= L0RXTLTLPNONINITIALIZEDVC_ipd after IN_DELAY; L0SENDUNLOCKMESSAGE_indelay <= L0SENDUNLOCKMESSAGE_ipd after IN_DELAY; L0SETCOMPLETERABORTERROR_indelay <= L0SETCOMPLETERABORTERROR_ipd after IN_DELAY; L0SETCOMPLETIONTIMEOUTCORRERROR_indelay <= L0SETCOMPLETIONTIMEOUTCORRERROR_ipd after IN_DELAY; L0SETCOMPLETIONTIMEOUTUNCORRERROR_indelay <= L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd after IN_DELAY; L0SETDETECTEDCORRERROR_indelay <= L0SETDETECTEDCORRERROR_ipd after IN_DELAY; L0SETDETECTEDFATALERROR_indelay <= L0SETDETECTEDFATALERROR_ipd after IN_DELAY; L0SETDETECTEDNONFATALERROR_indelay <= L0SETDETECTEDNONFATALERROR_ipd after IN_DELAY; L0SETLINKDETECTEDPARITYERROR_indelay <= L0SETLINKDETECTEDPARITYERROR_ipd after IN_DELAY; L0SETLINKMASTERDATAPARITY_indelay <= L0SETLINKMASTERDATAPARITY_ipd after IN_DELAY; L0SETLINKRECEIVEDMASTERABORT_indelay <= L0SETLINKRECEIVEDMASTERABORT_ipd after IN_DELAY; L0SETLINKRECEIVEDTARGETABORT_indelay <= L0SETLINKRECEIVEDTARGETABORT_ipd after IN_DELAY; L0SETLINKSIGNALLEDTARGETABORT_indelay <= L0SETLINKSIGNALLEDTARGETABORT_ipd after IN_DELAY; L0SETLINKSYSTEMERROR_indelay <= L0SETLINKSYSTEMERROR_ipd after IN_DELAY; L0SETUNEXPECTEDCOMPLETIONCORRERROR_indelay <= L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd after IN_DELAY; L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_indelay <= L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd after IN_DELAY; L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_indelay <= L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd after IN_DELAY; L0SETUNSUPPORTEDREQUESTOTHERERROR_indelay <= L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd after IN_DELAY; L0SETUSERDETECTEDPARITYERROR_indelay <= L0SETUSERDETECTEDPARITYERROR_ipd after IN_DELAY; L0SETUSERMASTERDATAPARITY_indelay <= L0SETUSERMASTERDATAPARITY_ipd after IN_DELAY; L0SETUSERRECEIVEDMASTERABORT_indelay <= L0SETUSERRECEIVEDMASTERABORT_ipd after IN_DELAY; L0SETUSERRECEIVEDTARGETABORT_indelay <= L0SETUSERRECEIVEDTARGETABORT_ipd after IN_DELAY; L0SETUSERSIGNALLEDTARGETABORT_indelay <= L0SETUSERSIGNALLEDTARGETABORT_ipd after IN_DELAY; L0SETUSERSYSTEMERROR_indelay <= L0SETUSERSYSTEMERROR_ipd after IN_DELAY; L0TLASFCCREDSTARVATION_indelay <= L0TLASFCCREDSTARVATION_ipd after IN_DELAY; L0TLLINKRETRAIN_indelay <= L0TLLINKRETRAIN_ipd after IN_DELAY; L0TRANSACTIONSPENDING_indelay <= L0TRANSACTIONSPENDING_ipd after IN_DELAY; L0TXBEACON_indelay <= L0TXBEACON_ipd after IN_DELAY; L0TXCFGPMTYPE_indelay <= L0TXCFGPMTYPE_ipd after IN_DELAY; L0TXCFGPM_indelay <= L0TXCFGPM_ipd after IN_DELAY; L0TXTLFCCMPLMCCRED_indelay <= L0TXTLFCCMPLMCCRED_ipd after IN_DELAY; L0TXTLFCCMPLMCUPDATE_indelay <= L0TXTLFCCMPLMCUPDATE_ipd after IN_DELAY; L0TXTLFCNPOSTBYPCRED_indelay <= L0TXTLFCNPOSTBYPCRED_ipd after IN_DELAY; L0TXTLFCNPOSTBYPUPDATE_indelay <= L0TXTLFCNPOSTBYPUPDATE_ipd after IN_DELAY; L0TXTLFCPOSTORDCRED_indelay <= L0TXTLFCPOSTORDCRED_ipd after IN_DELAY; L0TXTLFCPOSTORDUPDATE_indelay <= L0TXTLFCPOSTORDUPDATE_ipd after IN_DELAY; L0TXTLSBFCDATA_indelay <= L0TXTLSBFCDATA_ipd after IN_DELAY; L0TXTLSBFCUPDATE_indelay <= L0TXTLSBFCUPDATE_ipd after IN_DELAY; L0TXTLTLPDATA_indelay <= L0TXTLTLPDATA_ipd after IN_DELAY; L0TXTLTLPEDB_indelay <= L0TXTLTLPEDB_ipd after IN_DELAY; L0TXTLTLPENABLE_indelay <= L0TXTLTLPENABLE_ipd after IN_DELAY; L0TXTLTLPEND_indelay <= L0TXTLTLPEND_ipd after IN_DELAY; L0TXTLTLPLATENCY_indelay <= L0TXTLTLPLATENCY_ipd after IN_DELAY; L0TXTLTLPREQEND_indelay <= L0TXTLTLPREQEND_ipd after IN_DELAY; L0TXTLTLPREQ_indelay <= L0TXTLTLPREQ_ipd after IN_DELAY; L0TXTLTLPWIDTH_indelay <= L0TXTLTLPWIDTH_ipd after IN_DELAY; L0UPSTREAMRXPORTINL0S_indelay <= L0UPSTREAMRXPORTINL0S_ipd after IN_DELAY; L0VC0PREVIEWEXPAND_indelay <= L0VC0PREVIEWEXPAND_ipd after IN_DELAY; L0WAKEN_indelay <= L0WAKEN_ipd after IN_DELAY; LLKRXCHFIFO_indelay <= LLKRXCHFIFO_ipd after IN_DELAY; LLKRXCHTC_indelay <= LLKRXCHTC_ipd after IN_DELAY; LLKRXDSTCONTREQN_indelay <= LLKRXDSTCONTREQN_ipd after IN_DELAY; LLKRXDSTREQN_indelay <= LLKRXDSTREQN_ipd after IN_DELAY; LLKTX4DWHEADERN_indelay <= LLKTX4DWHEADERN_ipd after IN_DELAY; LLKTXCHFIFO_indelay <= LLKTXCHFIFO_ipd after IN_DELAY; LLKTXCHTC_indelay <= LLKTXCHTC_ipd after IN_DELAY; LLKTXCOMPLETEN_indelay <= LLKTXCOMPLETEN_ipd after IN_DELAY; LLKTXCREATEECRCN_indelay <= LLKTXCREATEECRCN_ipd after IN_DELAY; LLKTXDATA_indelay <= LLKTXDATA_ipd after IN_DELAY; LLKTXENABLEN_indelay <= LLKTXENABLEN_ipd after IN_DELAY; LLKTXEOFN_indelay <= LLKTXEOFN_ipd after IN_DELAY; LLKTXEOPN_indelay <= LLKTXEOPN_ipd after IN_DELAY; LLKTXSOFN_indelay <= LLKTXSOFN_ipd after IN_DELAY; LLKTXSOPN_indelay <= LLKTXSOPN_ipd after IN_DELAY; LLKTXSRCDSCN_indelay <= LLKTXSRCDSCN_ipd after IN_DELAY; LLKTXSRCRDYN_indelay <= LLKTXSRCRDYN_ipd after IN_DELAY; MAINPOWER_indelay <= MAINPOWER_ipd after IN_DELAY; MGMTADDR_indelay <= MGMTADDR_ipd after IN_DELAY; MGMTBWREN_indelay <= MGMTBWREN_ipd after IN_DELAY; MGMTRDEN_indelay <= MGMTRDEN_ipd after IN_DELAY; MGMTSTATSCREDITSEL_indelay <= MGMTSTATSCREDITSEL_ipd after IN_DELAY; MGMTWDATA_indelay <= MGMTWDATA_ipd after IN_DELAY; MGMTWREN_indelay <= MGMTWREN_ipd after IN_DELAY; MIMDLLBRDATA_indelay <= MIMDLLBRDATA_ipd after IN_DELAY; MIMRXBRDATA_indelay <= MIMRXBRDATA_ipd after IN_DELAY; MIMTXBRDATA_indelay <= MIMTXBRDATA_ipd after IN_DELAY; PIPEPHYSTATUSL0_indelay <= PIPEPHYSTATUSL0_ipd after IN_DELAY; PIPEPHYSTATUSL1_indelay <= PIPEPHYSTATUSL1_ipd after IN_DELAY; PIPEPHYSTATUSL2_indelay <= PIPEPHYSTATUSL2_ipd after IN_DELAY; PIPEPHYSTATUSL3_indelay <= PIPEPHYSTATUSL3_ipd after IN_DELAY; PIPEPHYSTATUSL4_indelay <= PIPEPHYSTATUSL4_ipd after IN_DELAY; PIPEPHYSTATUSL5_indelay <= PIPEPHYSTATUSL5_ipd after IN_DELAY; PIPEPHYSTATUSL6_indelay <= PIPEPHYSTATUSL6_ipd after IN_DELAY; PIPEPHYSTATUSL7_indelay <= PIPEPHYSTATUSL7_ipd after IN_DELAY; PIPERXCHANISALIGNEDL0_indelay <= PIPERXCHANISALIGNEDL0_ipd after IN_DELAY; PIPERXCHANISALIGNEDL1_indelay <= PIPERXCHANISALIGNEDL1_ipd after IN_DELAY; PIPERXCHANISALIGNEDL2_indelay <= PIPERXCHANISALIGNEDL2_ipd after IN_DELAY; PIPERXCHANISALIGNEDL3_indelay <= PIPERXCHANISALIGNEDL3_ipd after IN_DELAY; PIPERXCHANISALIGNEDL4_indelay <= PIPERXCHANISALIGNEDL4_ipd after IN_DELAY; PIPERXCHANISALIGNEDL5_indelay <= PIPERXCHANISALIGNEDL5_ipd after IN_DELAY; PIPERXCHANISALIGNEDL6_indelay <= PIPERXCHANISALIGNEDL6_ipd after IN_DELAY; PIPERXCHANISALIGNEDL7_indelay <= PIPERXCHANISALIGNEDL7_ipd after IN_DELAY; PIPERXDATAKL0_indelay <= PIPERXDATAKL0_ipd after IN_DELAY; PIPERXDATAKL1_indelay <= PIPERXDATAKL1_ipd after IN_DELAY; PIPERXDATAKL2_indelay <= PIPERXDATAKL2_ipd after IN_DELAY; PIPERXDATAKL3_indelay <= PIPERXDATAKL3_ipd after IN_DELAY; PIPERXDATAKL4_indelay <= PIPERXDATAKL4_ipd after IN_DELAY; PIPERXDATAKL5_indelay <= PIPERXDATAKL5_ipd after IN_DELAY; PIPERXDATAKL6_indelay <= PIPERXDATAKL6_ipd after IN_DELAY; PIPERXDATAKL7_indelay <= PIPERXDATAKL7_ipd after IN_DELAY; PIPERXDATAL0_indelay <= PIPERXDATAL0_ipd after IN_DELAY; PIPERXDATAL1_indelay <= PIPERXDATAL1_ipd after IN_DELAY; PIPERXDATAL2_indelay <= PIPERXDATAL2_ipd after IN_DELAY; PIPERXDATAL3_indelay <= PIPERXDATAL3_ipd after IN_DELAY; PIPERXDATAL4_indelay <= PIPERXDATAL4_ipd after IN_DELAY; PIPERXDATAL5_indelay <= PIPERXDATAL5_ipd after IN_DELAY; PIPERXDATAL6_indelay <= PIPERXDATAL6_ipd after IN_DELAY; PIPERXDATAL7_indelay <= PIPERXDATAL7_ipd after IN_DELAY; PIPERXELECIDLEL0_indelay <= PIPERXELECIDLEL0_ipd after IN_DELAY; PIPERXELECIDLEL1_indelay <= PIPERXELECIDLEL1_ipd after IN_DELAY; PIPERXELECIDLEL2_indelay <= PIPERXELECIDLEL2_ipd after IN_DELAY; PIPERXELECIDLEL3_indelay <= PIPERXELECIDLEL3_ipd after IN_DELAY; PIPERXELECIDLEL4_indelay <= PIPERXELECIDLEL4_ipd after IN_DELAY; PIPERXELECIDLEL5_indelay <= PIPERXELECIDLEL5_ipd after IN_DELAY; PIPERXELECIDLEL6_indelay <= PIPERXELECIDLEL6_ipd after IN_DELAY; PIPERXELECIDLEL7_indelay <= PIPERXELECIDLEL7_ipd after IN_DELAY; PIPERXSTATUSL0_indelay <= PIPERXSTATUSL0_ipd after IN_DELAY; PIPERXSTATUSL1_indelay <= PIPERXSTATUSL1_ipd after IN_DELAY; PIPERXSTATUSL2_indelay <= PIPERXSTATUSL2_ipd after IN_DELAY; PIPERXSTATUSL3_indelay <= PIPERXSTATUSL3_ipd after IN_DELAY; PIPERXSTATUSL4_indelay <= PIPERXSTATUSL4_ipd after IN_DELAY; PIPERXSTATUSL5_indelay <= PIPERXSTATUSL5_ipd after IN_DELAY; PIPERXSTATUSL6_indelay <= PIPERXSTATUSL6_ipd after IN_DELAY; PIPERXSTATUSL7_indelay <= PIPERXSTATUSL7_ipd after IN_DELAY; PIPERXVALIDL0_indelay <= PIPERXVALIDL0_ipd after IN_DELAY; PIPERXVALIDL1_indelay <= PIPERXVALIDL1_ipd after IN_DELAY; PIPERXVALIDL2_indelay <= PIPERXVALIDL2_ipd after IN_DELAY; PIPERXVALIDL3_indelay <= PIPERXVALIDL3_ipd after IN_DELAY; PIPERXVALIDL4_indelay <= PIPERXVALIDL4_ipd after IN_DELAY; PIPERXVALIDL5_indelay <= PIPERXVALIDL5_ipd after IN_DELAY; PIPERXVALIDL6_indelay <= PIPERXVALIDL6_ipd after IN_DELAY; PIPERXVALIDL7_indelay <= PIPERXVALIDL7_ipd after IN_DELAY; pcie_internal_1_1_swift_bw_1 : PCIE_INTERNAL_1_1_SWIFT port map ( MCACTIVELANESIN => ACTIVELANESIN_BINARY, MCAERBASEPTR => AERBASEPTR_BINARY, MCAERCAPABILITYECRCCHECKCAPABLE => AERCAPABILITYECRCCHECKCAPABLE_BINARY, MCAERCAPABILITYECRCGENCAPABLE => AERCAPABILITYECRCGENCAPABLE_BINARY, MCAERCAPABILITYNEXTPTR => AERCAPABILITYNEXTPTR_BINARY, MCBAR0ADDRWIDTH => BAR0ADDRWIDTH_BINARY, MCBAR0EXIST => BAR0EXIST_BINARY, MCBAR0IOMEMN => BAR0IOMEMN_BINARY, MCBAR0MASKWIDTH => BAR0MASKWIDTH_BINARY, MCBAR0PREFETCHABLE => BAR0PREFETCHABLE_BINARY, MCBAR1ADDRWIDTH => BAR1ADDRWIDTH_BINARY, MCBAR1EXIST => BAR1EXIST_BINARY, MCBAR1IOMEMN => BAR1IOMEMN_BINARY, MCBAR1MASKWIDTH => BAR1MASKWIDTH_BINARY, MCBAR1PREFETCHABLE => BAR1PREFETCHABLE_BINARY, MCBAR2ADDRWIDTH => BAR2ADDRWIDTH_BINARY, MCBAR2EXIST => BAR2EXIST_BINARY, MCBAR2IOMEMN => BAR2IOMEMN_BINARY, MCBAR2MASKWIDTH => BAR2MASKWIDTH_BINARY, MCBAR2PREFETCHABLE => BAR2PREFETCHABLE_BINARY, MCBAR3ADDRWIDTH => BAR3ADDRWIDTH_BINARY, MCBAR3EXIST => BAR3EXIST_BINARY, MCBAR3IOMEMN => BAR3IOMEMN_BINARY, MCBAR3MASKWIDTH => BAR3MASKWIDTH_BINARY, MCBAR3PREFETCHABLE => BAR3PREFETCHABLE_BINARY, MCBAR4ADDRWIDTH => BAR4ADDRWIDTH_BINARY, MCBAR4EXIST => BAR4EXIST_BINARY, MCBAR4IOMEMN => BAR4IOMEMN_BINARY, MCBAR4MASKWIDTH => BAR4MASKWIDTH_BINARY, MCBAR4PREFETCHABLE => BAR4PREFETCHABLE_BINARY, MCBAR5ADDRWIDTH => BAR5ADDRWIDTH_BINARY, MCBAR5EXIST => BAR5EXIST_BINARY, MCBAR5IOMEMN => BAR5IOMEMN_BINARY, MCBAR5MASKWIDTH => BAR5MASKWIDTH_BINARY, MCBAR5PREFETCHABLE => BAR5PREFETCHABLE_BINARY, MCCAPABILITIESPOINTER => CAPABILITIESPOINTER_BINARY, MCCARDBUSCISPOINTER => CARDBUSCISPOINTER_BINARY, MCCLASSCODE => CLASSCODE_BINARY, -- MCCLKDIVIDED => CLKDIVIDED_BINARY, MCCONFIGROUTING => CONFIGROUTING_BINARY, MCDEVICECAPABILITYENDPOINTL0SLATENCY => DEVICECAPABILITYENDPOINTL0SLATENCY_BINARY, MCDEVICECAPABILITYENDPOINTL1LATENCY => DEVICECAPABILITYENDPOINTL1LATENCY_BINARY, MCDEVICEID => DEVICEID_BINARY, MCDEVICESERIALNUMBER => DEVICESERIALNUMBER_BINARY, MCDSNBASEPTR => DSNBASEPTR_BINARY, MCDSNCAPABILITYNEXTPTR => DSNCAPABILITYNEXTPTR_BINARY, MCDUALCOREENABLE => DUALCOREENABLE_BINARY, MCDUALCORESLAVE => DUALCORESLAVE_BINARY, MCDUALROLECFGCNTRLROOTEPN => DUALROLECFGCNTRLROOTEPN_BINARY, MCEXTCFGCAPPTR => EXTCFGCAPPTR_BINARY, MCEXTCFGXPCAPPTR => EXTCFGXPCAPPTR_BINARY, MCHEADERTYPE => HEADERTYPE_BINARY, MCINFINITECOMPLETIONS => INFINITECOMPLETIONS_BINARY, MCINTERRUPTPIN => INTERRUPTPIN_BINARY, MCISSWITCH => ISSWITCH_BINARY, MCL0SEXITLATENCY => L0SEXITLATENCY_BINARY, MCL0SEXITLATENCYCOMCLK => L0SEXITLATENCYCOMCLK_BINARY, MCL1EXITLATENCY => L1EXITLATENCY_BINARY, MCL1EXITLATENCYCOMCLK => L1EXITLATENCYCOMCLK_BINARY, MCLINKCAPABILITYASPMSUPPORT => LINKCAPABILITYASPMSUPPORT_BINARY, MCLINKCAPABILITYMAXLINKWIDTH => LINKCAPABILITYMAXLINKWIDTH_BINARY, MCLINKSTATUSSLOTCLOCKCONFIG => LINKSTATUSSLOTCLOCKCONFIG_BINARY, MCLLKBYPASS => LLKBYPASS_BINARY, MCLOWPRIORITYVCCOUNT => LOWPRIORITYVCCOUNT_BINARY, MCMSIBASEPTR => MSIBASEPTR_BINARY, MCMSICAPABILITYMULTIMSGCAP => MSICAPABILITYMULTIMSGCAP_BINARY, MCMSICAPABILITYNEXTPTR => MSICAPABILITYNEXTPTR_BINARY, MCPBBASEPTR => PBBASEPTR_BINARY, MCPBCAPABILITYDW0BASEPOWER => PBCAPABILITYDW0BASEPOWER_BINARY, MCPBCAPABILITYDW0DATASCALE => PBCAPABILITYDW0DATASCALE_BINARY, MCPBCAPABILITYDW0PMSTATE => PBCAPABILITYDW0PMSTATE_BINARY, MCPBCAPABILITYDW0PMSUBSTATE => PBCAPABILITYDW0PMSUBSTATE_BINARY, MCPBCAPABILITYDW0POWERRAIL => PBCAPABILITYDW0POWERRAIL_BINARY, MCPBCAPABILITYDW0TYPE => PBCAPABILITYDW0TYPE_BINARY, MCPBCAPABILITYDW1BASEPOWER => PBCAPABILITYDW1BASEPOWER_BINARY, MCPBCAPABILITYDW1DATASCALE => PBCAPABILITYDW1DATASCALE_BINARY, MCPBCAPABILITYDW1PMSTATE => PBCAPABILITYDW1PMSTATE_BINARY, MCPBCAPABILITYDW1PMSUBSTATE => PBCAPABILITYDW1PMSUBSTATE_BINARY, MCPBCAPABILITYDW1POWERRAIL => PBCAPABILITYDW1POWERRAIL_BINARY, MCPBCAPABILITYDW1TYPE => PBCAPABILITYDW1TYPE_BINARY, MCPBCAPABILITYDW2BASEPOWER => PBCAPABILITYDW2BASEPOWER_BINARY, MCPBCAPABILITYDW2DATASCALE => PBCAPABILITYDW2DATASCALE_BINARY, MCPBCAPABILITYDW2PMSTATE => PBCAPABILITYDW2PMSTATE_BINARY, MCPBCAPABILITYDW2PMSUBSTATE => PBCAPABILITYDW2PMSUBSTATE_BINARY, MCPBCAPABILITYDW2POWERRAIL => PBCAPABILITYDW2POWERRAIL_BINARY, MCPBCAPABILITYDW2TYPE => PBCAPABILITYDW2TYPE_BINARY, MCPBCAPABILITYDW3BASEPOWER => PBCAPABILITYDW3BASEPOWER_BINARY, MCPBCAPABILITYDW3DATASCALE => PBCAPABILITYDW3DATASCALE_BINARY, MCPBCAPABILITYDW3PMSTATE => PBCAPABILITYDW3PMSTATE_BINARY, MCPBCAPABILITYDW3PMSUBSTATE => PBCAPABILITYDW3PMSUBSTATE_BINARY, MCPBCAPABILITYDW3POWERRAIL => PBCAPABILITYDW3POWERRAIL_BINARY, MCPBCAPABILITYDW3TYPE => PBCAPABILITYDW3TYPE_BINARY, MCPBCAPABILITYNEXTPTR => PBCAPABILITYNEXTPTR_BINARY, MCPBCAPABILITYSYSTEMALLOCATED => PBCAPABILITYSYSTEMALLOCATED_BINARY, MCPCIECAPABILITYINTMSGNUM => PCIECAPABILITYINTMSGNUM_BINARY, MCPCIECAPABILITYNEXTPTR => PCIECAPABILITYNEXTPTR_BINARY, MCPCIECAPABILITYSLOTIMPL => PCIECAPABILITYSLOTIMPL_BINARY, MCPCIEREVISION => PCIEREVISION_BINARY, MCPMBASEPTR => PMBASEPTR_BINARY, MCPMCAPABILITYAUXCURRENT => PMCAPABILITYAUXCURRENT_BINARY, MCPMCAPABILITYD1SUPPORT => PMCAPABILITYD1SUPPORT_BINARY, MCPMCAPABILITYD2SUPPORT => PMCAPABILITYD2SUPPORT_BINARY, MCPMCAPABILITYDSI => PMCAPABILITYDSI_BINARY, MCPMCAPABILITYNEXTPTR => PMCAPABILITYNEXTPTR_BINARY, MCPMCAPABILITYPMESUPPORT => PMCAPABILITYPMESUPPORT_BINARY, MCPMDATA0 => PMDATA0_BINARY, MCPMDATA1 => PMDATA1_BINARY, MCPMDATA2 => PMDATA2_BINARY, MCPMDATA3 => PMDATA3_BINARY, MCPMDATA4 => PMDATA4_BINARY, MCPMDATA5 => PMDATA5_BINARY, MCPMDATA6 => PMDATA6_BINARY, MCPMDATA7 => PMDATA7_BINARY, MCPMDATA8 => PMDATA8_BINARY, MCPMDATASCALE0 => PMDATASCALE0_BINARY, MCPMDATASCALE1 => PMDATASCALE1_BINARY, MCPMDATASCALE2 => PMDATASCALE2_BINARY, MCPMDATASCALE3 => PMDATASCALE3_BINARY, MCPMDATASCALE4 => PMDATASCALE4_BINARY, MCPMDATASCALE5 => PMDATASCALE5_BINARY, MCPMDATASCALE6 => PMDATASCALE6_BINARY, MCPMDATASCALE7 => PMDATASCALE7_BINARY, MCPMDATASCALE8 => PMDATASCALE8_BINARY, MCPMSTATUSCONTROLDATASCALE => PMSTATUSCONTROLDATASCALE_BINARY, MCPORTVCCAPABILITYEXTENDEDVCCOUNT => PORTVCCAPABILITYEXTENDEDVCCOUNT_BINARY, MCPORTVCCAPABILITYVCARBCAP => PORTVCCAPABILITYVCARBCAP_BINARY, MCPORTVCCAPABILITYVCARBTABLEOFFSET => PORTVCCAPABILITYVCARBTABLEOFFSET_BINARY, MCRAMSHARETXRX => RAMSHARETXRX_BINARY, MCRESETMODE => RESETMODE_BINARY, MCRETRYRAMREADLATENCY => RETRYRAMREADLATENCY_BINARY, MCRETRYRAMSIZE => RETRYRAMSIZE_BINARY, MCRETRYRAMWIDTH => RETRYRAMWIDTH_BINARY, MCRETRYRAMWRITELATENCY => RETRYRAMWRITELATENCY_BINARY, MCRETRYREADADDRPIPE => RETRYREADADDRPIPE_BINARY, MCRETRYREADDATAPIPE => RETRYREADDATAPIPE_BINARY, MCRETRYWRITEPIPE => RETRYWRITEPIPE_BINARY, MCREVISIONID => REVISIONID_BINARY, MCRXREADADDRPIPE => RXREADADDRPIPE_BINARY, MCRXREADDATAPIPE => RXREADDATAPIPE_BINARY, MCRXWRITEPIPE => RXWRITEPIPE_BINARY, MCSELECTASMODE => SELECTASMODE_BINARY, MCSELECTDLLIF => SELECTDLLIF_BINARY, MCSLOTCAPABILITYATTBUTTONPRESENT => SLOTCAPABILITYATTBUTTONPRESENT_BINARY, MCSLOTCAPABILITYATTINDICATORPRESENT => SLOTCAPABILITYATTINDICATORPRESENT_BINARY, MCSLOTCAPABILITYHOTPLUGCAPABLE => SLOTCAPABILITYHOTPLUGCAPABLE_BINARY, MCSLOTCAPABILITYHOTPLUGSURPRISE => SLOTCAPABILITYHOTPLUGSURPRISE_BINARY, MCSLOTCAPABILITYMSLSENSORPRESENT => SLOTCAPABILITYMSLSENSORPRESENT_BINARY, MCSLOTCAPABILITYPHYSICALSLOTNUM => SLOTCAPABILITYPHYSICALSLOTNUM_BINARY, MCSLOTCAPABILITYPOWERCONTROLLERPRESENT => SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY, MCSLOTCAPABILITYPOWERINDICATORPRESENT => SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY, MCSLOTCAPABILITYSLOTPOWERLIMITSCALE => SLOTCAPABILITYSLOTPOWERLIMITSCALE_BINARY, MCSLOTCAPABILITYSLOTPOWERLIMITVALUE => SLOTCAPABILITYSLOTPOWERLIMITVALUE_BINARY, MCSLOTIMPLEMENTED => SLOTIMPLEMENTED_BINARY, MCSUBSYSTEMID => SUBSYSTEMID_BINARY, MCSUBSYSTEMVENDORID => SUBSYSTEMVENDORID_BINARY, MCTLRAMREADLATENCY => TLRAMREADLATENCY_BINARY, MCTLRAMWIDTH => TLRAMWIDTH_BINARY, MCTLRAMWRITELATENCY => TLRAMWRITELATENCY_BINARY, MCTXREADADDRPIPE => TXREADADDRPIPE_BINARY, MCTXREADDATAPIPE => TXREADDATAPIPE_BINARY, MCTXTSNFTS => TXTSNFTS_BINARY, MCTXTSNFTSCOMCLK => TXTSNFTSCOMCLK_BINARY, MCTXWRITEPIPE => TXWRITEPIPE_BINARY, MCUPSTREAMFACING => UPSTREAMFACING_BINARY, MCVC0RXFIFOBASEC => VC0RXFIFOBASEC_BINARY, MCVC0RXFIFOBASENP => VC0RXFIFOBASENP_BINARY, MCVC0RXFIFOBASEP => VC0RXFIFOBASEP_BINARY, MCVC0RXFIFOLIMITC => VC0RXFIFOLIMITC_BINARY, MCVC0RXFIFOLIMITNP => VC0RXFIFOLIMITNP_BINARY, MCVC0RXFIFOLIMITP => VC0RXFIFOLIMITP_BINARY, MCVC0TOTALCREDITSCD => VC0TOTALCREDITSCD_BINARY, MCVC0TOTALCREDITSCH => VC0TOTALCREDITSCH_BINARY, MCVC0TOTALCREDITSNPH => VC0TOTALCREDITSNPH_BINARY, MCVC0TOTALCREDITSPD => VC0TOTALCREDITSPD_BINARY, MCVC0TOTALCREDITSPH => VC0TOTALCREDITSPH_BINARY, MCVC0TXFIFOBASEC => VC0TXFIFOBASEC_BINARY, MCVC0TXFIFOBASENP => VC0TXFIFOBASENP_BINARY, MCVC0TXFIFOBASEP => VC0TXFIFOBASEP_BINARY, MCVC0TXFIFOLIMITC => VC0TXFIFOLIMITC_BINARY, MCVC0TXFIFOLIMITNP => VC0TXFIFOLIMITNP_BINARY, MCVC0TXFIFOLIMITP => VC0TXFIFOLIMITP_BINARY, MCVC1RXFIFOBASEC => VC1RXFIFOBASEC_BINARY, MCVC1RXFIFOBASENP => VC1RXFIFOBASENP_BINARY, MCVC1RXFIFOBASEP => VC1RXFIFOBASEP_BINARY, MCVC1RXFIFOLIMITC => VC1RXFIFOLIMITC_BINARY, MCVC1RXFIFOLIMITNP => VC1RXFIFOLIMITNP_BINARY, MCVC1RXFIFOLIMITP => VC1RXFIFOLIMITP_BINARY, MCVC1TOTALCREDITSCD => VC1TOTALCREDITSCD_BINARY, MCVC1TOTALCREDITSCH => VC1TOTALCREDITSCH_BINARY, MCVC1TOTALCREDITSNPH => VC1TOTALCREDITSNPH_BINARY, MCVC1TOTALCREDITSPD => VC1TOTALCREDITSPD_BINARY, MCVC1TOTALCREDITSPH => VC1TOTALCREDITSPH_BINARY, MCVC1TXFIFOBASEC => VC1TXFIFOBASEC_BINARY, MCVC1TXFIFOBASENP => VC1TXFIFOBASENP_BINARY, MCVC1TXFIFOBASEP => VC1TXFIFOBASEP_BINARY, MCVC1TXFIFOLIMITC => VC1TXFIFOLIMITC_BINARY, MCVC1TXFIFOLIMITNP => VC1TXFIFOLIMITNP_BINARY, MCVC1TXFIFOLIMITP => VC1TXFIFOLIMITP_BINARY, MCVCBASEPTR => VCBASEPTR_BINARY, MCVCCAPABILITYNEXTPTR => VCCAPABILITYNEXTPTR_BINARY, MCVENDORID => VENDORID_BINARY, MCXLINKSUPPORTED => XLINKSUPPORTED_BINARY, MCXPBASEPTR => XPBASEPTR_BINARY, MCXPDEVICEPORTTYPE => XPDEVICEPORTTYPE_BINARY, MCXPMAXPAYLOAD => XPMAXPAYLOAD_BINARY, MCXPRCBCONTROL => XPRCBCONTROL_BINARY, BUSMASTERENABLE => BUSMASTERENABLE_outdelay, CRMDOHOTRESETN => CRMDOHOTRESETN_outdelay, CRMPWRSOFTRESETN => CRMPWRSOFTRESETN_outdelay, CRMRXHOTRESETN => CRMRXHOTRESETN_outdelay, DLLTXPMDLLPOUTSTANDING => DLLTXPMDLLPOUTSTANDING_outdelay, INTERRUPTDISABLE => INTERRUPTDISABLE_outdelay, IOSPACEENABLE => IOSPACEENABLE_outdelay, L0ASAUTONOMOUSINITCOMPLETED => L0ASAUTONOMOUSINITCOMPLETED_outdelay, L0ATTENTIONINDICATORCONTROL => L0ATTENTIONINDICATORCONTROL_outdelay, L0CFGLOOPBACKACK => L0CFGLOOPBACKACK_outdelay, L0COMPLETERID => L0COMPLETERID_outdelay, L0CORRERRMSGRCVD => L0CORRERRMSGRCVD_outdelay, L0DLLASRXSTATE => L0DLLASRXSTATE_outdelay, L0DLLASTXSTATE => L0DLLASTXSTATE_outdelay, L0DLLERRORVECTOR => L0DLLERRORVECTOR_outdelay, L0DLLRXACKOUTSTANDING => L0DLLRXACKOUTSTANDING_outdelay, L0DLLTXNONFCOUTSTANDING => L0DLLTXNONFCOUTSTANDING_outdelay, L0DLLTXOUTSTANDING => L0DLLTXOUTSTANDING_outdelay, L0DLLVCSTATUS => L0DLLVCSTATUS_outdelay, L0DLUPDOWN => L0DLUPDOWN_outdelay, L0ERRMSGREQID => L0ERRMSGREQID_outdelay, L0FATALERRMSGRCVD => L0FATALERRMSGRCVD_outdelay, L0FIRSTCFGWRITEOCCURRED => L0FIRSTCFGWRITEOCCURRED_outdelay, L0FWDCORRERROUT => L0FWDCORRERROUT_outdelay, L0FWDFATALERROUT => L0FWDFATALERROUT_outdelay, L0FWDNONFATALERROUT => L0FWDNONFATALERROUT_outdelay, L0LTSSMSTATE => L0LTSSMSTATE_outdelay, L0MACENTEREDL0 => L0MACENTEREDL0_outdelay, L0MACLINKTRAINING => L0MACLINKTRAINING_outdelay, L0MACLINKUP => L0MACLINKUP_outdelay, L0MACNEGOTIATEDLINKWIDTH => L0MACNEGOTIATEDLINKWIDTH_outdelay, L0MACNEWSTATEACK => L0MACNEWSTATEACK_outdelay, L0MACRXL0SSTATE => L0MACRXL0SSTATE_outdelay, L0MACUPSTREAMDOWNSTREAM => L0MACUPSTREAMDOWNSTREAM_outdelay, L0MCFOUND => L0MCFOUND_outdelay, L0MSIENABLE0 => L0MSIENABLE0_outdelay, L0MULTIMSGEN0 => L0MULTIMSGEN0_outdelay, L0NONFATALERRMSGRCVD => L0NONFATALERRMSGRCVD_outdelay, L0PMEACK => L0PMEACK_outdelay, L0PMEEN => L0PMEEN_outdelay, L0PMEREQOUT => L0PMEREQOUT_outdelay, L0POWERCONTROLLERCONTROL => L0POWERCONTROLLERCONTROL_outdelay, L0POWERINDICATORCONTROL => L0POWERINDICATORCONTROL_outdelay, L0PWRINHIBITTRANSFERS => L0PWRINHIBITTRANSFERS_outdelay, L0PWRL1STATE => L0PWRL1STATE_outdelay, L0PWRL23READYDEVICE => L0PWRL23READYDEVICE_outdelay, L0PWRL23READYSTATE => L0PWRL23READYSTATE_outdelay, L0PWRSTATE0 => L0PWRSTATE0_outdelay, L0PWRTURNOFFREQ => L0PWRTURNOFFREQ_outdelay, L0PWRTXL0SSTATE => L0PWRTXL0SSTATE_outdelay, L0RECEIVEDASSERTINTALEGACYINT => L0RECEIVEDASSERTINTALEGACYINT_outdelay, L0RECEIVEDASSERTINTBLEGACYINT => L0RECEIVEDASSERTINTBLEGACYINT_outdelay, L0RECEIVEDASSERTINTCLEGACYINT => L0RECEIVEDASSERTINTCLEGACYINT_outdelay, L0RECEIVEDASSERTINTDLEGACYINT => L0RECEIVEDASSERTINTDLEGACYINT_outdelay, L0RECEIVEDDEASSERTINTALEGACYINT => L0RECEIVEDDEASSERTINTALEGACYINT_outdelay, L0RECEIVEDDEASSERTINTBLEGACYINT => L0RECEIVEDDEASSERTINTBLEGACYINT_outdelay, L0RECEIVEDDEASSERTINTCLEGACYINT => L0RECEIVEDDEASSERTINTCLEGACYINT_outdelay, L0RECEIVEDDEASSERTINTDLEGACYINT => L0RECEIVEDDEASSERTINTDLEGACYINT_outdelay, L0RXBEACON => L0RXBEACON_outdelay, L0RXDLLFCCMPLMCCRED => L0RXDLLFCCMPLMCCRED_outdelay, L0RXDLLFCCMPLMCUPDATE => L0RXDLLFCCMPLMCUPDATE_outdelay, L0RXDLLFCNPOSTBYPCRED => L0RXDLLFCNPOSTBYPCRED_outdelay, L0RXDLLFCNPOSTBYPUPDATE => L0RXDLLFCNPOSTBYPUPDATE_outdelay, L0RXDLLFCPOSTORDCRED => L0RXDLLFCPOSTORDCRED_outdelay, L0RXDLLFCPOSTORDUPDATE => L0RXDLLFCPOSTORDUPDATE_outdelay, L0RXDLLPM => L0RXDLLPM_outdelay, L0RXDLLPMTYPE => L0RXDLLPMTYPE_outdelay, L0RXDLLSBFCDATA => L0RXDLLSBFCDATA_outdelay, L0RXDLLSBFCUPDATE => L0RXDLLSBFCUPDATE_outdelay, L0RXDLLTLPECRCOK => L0RXDLLTLPECRCOK_outdelay, L0RXDLLTLPEND => L0RXDLLTLPEND_outdelay, L0RXMACLINKERROR => L0RXMACLINKERROR_outdelay, L0STATSCFGOTHERRECEIVED => L0STATSCFGOTHERRECEIVED_outdelay, L0STATSCFGOTHERTRANSMITTED => L0STATSCFGOTHERTRANSMITTED_outdelay, L0STATSCFGRECEIVED => L0STATSCFGRECEIVED_outdelay, L0STATSCFGTRANSMITTED => L0STATSCFGTRANSMITTED_outdelay, L0STATSDLLPRECEIVED => L0STATSDLLPRECEIVED_outdelay, L0STATSDLLPTRANSMITTED => L0STATSDLLPTRANSMITTED_outdelay, L0STATSOSRECEIVED => L0STATSOSRECEIVED_outdelay, L0STATSOSTRANSMITTED => L0STATSOSTRANSMITTED_outdelay, L0STATSTLPRECEIVED => L0STATSTLPRECEIVED_outdelay, L0STATSTLPTRANSMITTED => L0STATSTLPTRANSMITTED_outdelay, L0TOGGLEELECTROMECHANICALINTERLOCK => L0TOGGLEELECTROMECHANICALINTERLOCK_outdelay, L0TRANSFORMEDVC => L0TRANSFORMEDVC_outdelay, L0TXDLLFCCMPLMCUPDATED => L0TXDLLFCCMPLMCUPDATED_outdelay, L0TXDLLFCNPOSTBYPUPDATED => L0TXDLLFCNPOSTBYPUPDATED_outdelay, L0TXDLLFCPOSTORDUPDATED => L0TXDLLFCPOSTORDUPDATED_outdelay, L0TXDLLPMUPDATED => L0TXDLLPMUPDATED_outdelay, L0TXDLLSBFCUPDATED => L0TXDLLSBFCUPDATED_outdelay, L0UCBYPFOUND => L0UCBYPFOUND_outdelay, L0UCORDFOUND => L0UCORDFOUND_outdelay, L0UNLOCKRECEIVED => L0UNLOCKRECEIVED_outdelay, LLKRX4DWHEADERN => LLKRX4DWHEADERN_outdelay, LLKRXCHCOMPLETIONAVAILABLEN => LLKRXCHCOMPLETIONAVAILABLEN_outdelay, LLKRXCHCOMPLETIONPARTIALN => LLKRXCHCOMPLETIONPARTIALN_outdelay, LLKRXCHCONFIGAVAILABLEN => LLKRXCHCONFIGAVAILABLEN_outdelay, LLKRXCHCONFIGPARTIALN => LLKRXCHCONFIGPARTIALN_outdelay, LLKRXCHNONPOSTEDAVAILABLEN => LLKRXCHNONPOSTEDAVAILABLEN_outdelay, LLKRXCHNONPOSTEDPARTIALN => LLKRXCHNONPOSTEDPARTIALN_outdelay, LLKRXCHPOSTEDAVAILABLEN => LLKRXCHPOSTEDAVAILABLEN_outdelay, LLKRXCHPOSTEDPARTIALN => LLKRXCHPOSTEDPARTIALN_outdelay, LLKRXDATA => LLKRXDATA_outdelay, LLKRXECRCBADN => LLKRXECRCBADN_outdelay, LLKRXEOFN => LLKRXEOFN_outdelay, LLKRXEOPN => LLKRXEOPN_outdelay, LLKRXPREFERREDTYPE => LLKRXPREFERREDTYPE_outdelay, LLKRXSOFN => LLKRXSOFN_outdelay, LLKRXSOPN => LLKRXSOPN_outdelay, LLKRXSRCDSCN => LLKRXSRCDSCN_outdelay, LLKRXSRCLASTREQN => LLKRXSRCLASTREQN_outdelay, LLKRXSRCRDYN => LLKRXSRCRDYN_outdelay, LLKRXVALIDN => LLKRXVALIDN_outdelay, LLKTCSTATUS => LLKTCSTATUS_outdelay, LLKTXCHANSPACE => LLKTXCHANSPACE_outdelay, LLKTXCHCOMPLETIONREADYN => LLKTXCHCOMPLETIONREADYN_outdelay, LLKTXCHNONPOSTEDREADYN => LLKTXCHNONPOSTEDREADYN_outdelay, LLKTXCHPOSTEDREADYN => LLKTXCHPOSTEDREADYN_outdelay, LLKTXCONFIGREADYN => LLKTXCONFIGREADYN_outdelay, LLKTXDSTRDYN => LLKTXDSTRDYN_outdelay, MAXPAYLOADSIZE => MAXPAYLOADSIZE_outdelay, MAXREADREQUESTSIZE => MAXREADREQUESTSIZE_outdelay, MEMSPACEENABLE => MEMSPACEENABLE_outdelay, MGMTPSO => MGMTPSO_outdelay, MGMTRDATA => MGMTRDATA_outdelay, MGMTSTATSCREDIT => MGMTSTATSCREDIT_outdelay, MIMDLLBRADD => MIMDLLBRADD_outdelay, MIMDLLBREN => MIMDLLBREN_outdelay, MIMDLLBWADD => MIMDLLBWADD_outdelay, MIMDLLBWDATA => MIMDLLBWDATA_outdelay, MIMDLLBWEN => MIMDLLBWEN_outdelay, MIMRXBRADD => MIMRXBRADD_outdelay, MIMRXBREN => MIMRXBREN_outdelay, MIMRXBWADD => MIMRXBWADD_outdelay, MIMRXBWDATA => MIMRXBWDATA_outdelay, MIMRXBWEN => MIMRXBWEN_outdelay, MIMTXBRADD => MIMTXBRADD_outdelay, MIMTXBREN => MIMTXBREN_outdelay, MIMTXBWADD => MIMTXBWADD_outdelay, MIMTXBWDATA => MIMTXBWDATA_outdelay, MIMTXBWEN => MIMTXBWEN_outdelay, PARITYERRORRESPONSE => PARITYERRORRESPONSE_outdelay, PIPEDESKEWLANESL0 => PIPEDESKEWLANESL0_outdelay, PIPEDESKEWLANESL1 => PIPEDESKEWLANESL1_outdelay, PIPEDESKEWLANESL2 => PIPEDESKEWLANESL2_outdelay, PIPEDESKEWLANESL3 => PIPEDESKEWLANESL3_outdelay, PIPEDESKEWLANESL4 => PIPEDESKEWLANESL4_outdelay, PIPEDESKEWLANESL5 => PIPEDESKEWLANESL5_outdelay, PIPEDESKEWLANESL6 => PIPEDESKEWLANESL6_outdelay, PIPEDESKEWLANESL7 => PIPEDESKEWLANESL7_outdelay, PIPEPOWERDOWNL0 => PIPEPOWERDOWNL0_outdelay, PIPEPOWERDOWNL1 => PIPEPOWERDOWNL1_outdelay, PIPEPOWERDOWNL2 => PIPEPOWERDOWNL2_outdelay, PIPEPOWERDOWNL3 => PIPEPOWERDOWNL3_outdelay, PIPEPOWERDOWNL4 => PIPEPOWERDOWNL4_outdelay, PIPEPOWERDOWNL5 => PIPEPOWERDOWNL5_outdelay, PIPEPOWERDOWNL6 => PIPEPOWERDOWNL6_outdelay, PIPEPOWERDOWNL7 => PIPEPOWERDOWNL7_outdelay, PIPERESETL0 => PIPERESETL0_outdelay, PIPERESETL1 => PIPERESETL1_outdelay, PIPERESETL2 => PIPERESETL2_outdelay, PIPERESETL3 => PIPERESETL3_outdelay, PIPERESETL4 => PIPERESETL4_outdelay, PIPERESETL5 => PIPERESETL5_outdelay, PIPERESETL6 => PIPERESETL6_outdelay, PIPERESETL7 => PIPERESETL7_outdelay, PIPERXPOLARITYL0 => PIPERXPOLARITYL0_outdelay, PIPERXPOLARITYL1 => PIPERXPOLARITYL1_outdelay, PIPERXPOLARITYL2 => PIPERXPOLARITYL2_outdelay, PIPERXPOLARITYL3 => PIPERXPOLARITYL3_outdelay, PIPERXPOLARITYL4 => PIPERXPOLARITYL4_outdelay, PIPERXPOLARITYL5 => PIPERXPOLARITYL5_outdelay, PIPERXPOLARITYL6 => PIPERXPOLARITYL6_outdelay, PIPERXPOLARITYL7 => PIPERXPOLARITYL7_outdelay, PIPETXCOMPLIANCEL0 => PIPETXCOMPLIANCEL0_outdelay, PIPETXCOMPLIANCEL1 => PIPETXCOMPLIANCEL1_outdelay, PIPETXCOMPLIANCEL2 => PIPETXCOMPLIANCEL2_outdelay, PIPETXCOMPLIANCEL3 => PIPETXCOMPLIANCEL3_outdelay, PIPETXCOMPLIANCEL4 => PIPETXCOMPLIANCEL4_outdelay, PIPETXCOMPLIANCEL5 => PIPETXCOMPLIANCEL5_outdelay, PIPETXCOMPLIANCEL6 => PIPETXCOMPLIANCEL6_outdelay, PIPETXCOMPLIANCEL7 => PIPETXCOMPLIANCEL7_outdelay, PIPETXDATAKL0 => PIPETXDATAKL0_outdelay, PIPETXDATAKL1 => PIPETXDATAKL1_outdelay, PIPETXDATAKL2 => PIPETXDATAKL2_outdelay, PIPETXDATAKL3 => PIPETXDATAKL3_outdelay, PIPETXDATAKL4 => PIPETXDATAKL4_outdelay, PIPETXDATAKL5 => PIPETXDATAKL5_outdelay, PIPETXDATAKL6 => PIPETXDATAKL6_outdelay, PIPETXDATAKL7 => PIPETXDATAKL7_outdelay, PIPETXDATAL0 => PIPETXDATAL0_outdelay, PIPETXDATAL1 => PIPETXDATAL1_outdelay, PIPETXDATAL2 => PIPETXDATAL2_outdelay, PIPETXDATAL3 => PIPETXDATAL3_outdelay, PIPETXDATAL4 => PIPETXDATAL4_outdelay, PIPETXDATAL5 => PIPETXDATAL5_outdelay, PIPETXDATAL6 => PIPETXDATAL6_outdelay, PIPETXDATAL7 => PIPETXDATAL7_outdelay, PIPETXDETECTRXLOOPBACKL0 => PIPETXDETECTRXLOOPBACKL0_outdelay, PIPETXDETECTRXLOOPBACKL1 => PIPETXDETECTRXLOOPBACKL1_outdelay, PIPETXDETECTRXLOOPBACKL2 => PIPETXDETECTRXLOOPBACKL2_outdelay, PIPETXDETECTRXLOOPBACKL3 => PIPETXDETECTRXLOOPBACKL3_outdelay, PIPETXDETECTRXLOOPBACKL4 => PIPETXDETECTRXLOOPBACKL4_outdelay, PIPETXDETECTRXLOOPBACKL5 => PIPETXDETECTRXLOOPBACKL5_outdelay, PIPETXDETECTRXLOOPBACKL6 => PIPETXDETECTRXLOOPBACKL6_outdelay, PIPETXDETECTRXLOOPBACKL7 => PIPETXDETECTRXLOOPBACKL7_outdelay, PIPETXELECIDLEL0 => PIPETXELECIDLEL0_outdelay, PIPETXELECIDLEL1 => PIPETXELECIDLEL1_outdelay, PIPETXELECIDLEL2 => PIPETXELECIDLEL2_outdelay, PIPETXELECIDLEL3 => PIPETXELECIDLEL3_outdelay, PIPETXELECIDLEL4 => PIPETXELECIDLEL4_outdelay, PIPETXELECIDLEL5 => PIPETXELECIDLEL5_outdelay, PIPETXELECIDLEL6 => PIPETXELECIDLEL6_outdelay, PIPETXELECIDLEL7 => PIPETXELECIDLEL7_outdelay, SERRENABLE => SERRENABLE_outdelay, URREPORTINGENABLE => URREPORTINGENABLE_outdelay, AUXPOWER => AUXPOWER_indelay, CFGNEGOTIATEDLINKWIDTH => CFGNEGOTIATEDLINKWIDTH_indelay, COMPLIANCEAVOID => COMPLIANCEAVOID_indelay, CRMCFGBRIDGEHOTRESET => CRMCFGBRIDGEHOTRESET_indelay, CRMCORECLK => CRMCORECLK_indelay, CRMCORECLKDLO => CRMCORECLKDLO_indelay, CRMCORECLKRXO => CRMCORECLKRXO_indelay, CRMCORECLKTXO => CRMCORECLKTXO_indelay, CRMLINKRSTN => CRMLINKRSTN_indelay, CRMMACRSTN => CRMMACRSTN_indelay, CRMMGMTRSTN => CRMMGMTRSTN_indelay, CRMNVRSTN => CRMNVRSTN_indelay, CRMTXHOTRESETN => CRMTXHOTRESETN_indelay, CRMURSTN => CRMURSTN_indelay, CRMUSERCFGRSTN => CRMUSERCFGRSTN_indelay, CRMUSERCLK => CRMUSERCLK_indelay, CRMUSERCLKRXO => CRMUSERCLKRXO_indelay, CRMUSERCLKTXO => CRMUSERCLKTXO_indelay, CROSSLINKSEED => CROSSLINKSEED_indelay, GSR => GSR, L0ACKNAKTIMERADJUSTMENT => L0ACKNAKTIMERADJUSTMENT_indelay, L0ALLDOWNPORTSINL1 => L0ALLDOWNPORTSINL1_indelay, L0ALLDOWNRXPORTSINL0S => L0ALLDOWNRXPORTSINL0S_indelay, L0ASE => L0ASE_indelay, L0ASPORTCOUNT => L0ASPORTCOUNT_indelay, L0ASTURNPOOLBITSCONSUMED => L0ASTURNPOOLBITSCONSUMED_indelay, L0ATTENTIONBUTTONPRESSED => L0ATTENTIONBUTTONPRESSED_indelay, L0CFGASSPANTREEOWNEDSTATE => L0CFGASSPANTREEOWNEDSTATE_indelay, L0CFGASSTATECHANGECMD => L0CFGASSTATECHANGECMD_indelay, L0CFGDISABLESCRAMBLE => L0CFGDISABLESCRAMBLE_indelay, L0CFGEXTENDEDSYNC => L0CFGEXTENDEDSYNC_indelay, L0CFGL0SENTRYENABLE => L0CFGL0SENTRYENABLE_indelay, L0CFGL0SENTRYSUP => L0CFGL0SENTRYSUP_indelay, L0CFGL0SEXITLAT => L0CFGL0SEXITLAT_indelay, L0CFGLINKDISABLE => L0CFGLINKDISABLE_indelay, L0CFGLOOPBACKMASTER => L0CFGLOOPBACKMASTER_indelay, L0CFGNEGOTIATEDMAXP => L0CFGNEGOTIATEDMAXP_indelay, L0CFGVCENABLE => L0CFGVCENABLE_indelay, L0CFGVCID => L0CFGVCID_indelay, L0DLLHOLDLINKUP => L0DLLHOLDLINKUP_indelay, L0ELECTROMECHANICALINTERLOCKENGAGED => L0ELECTROMECHANICALINTERLOCKENGAGED_indelay, L0FWDASSERTINTALEGACYINT => L0FWDASSERTINTALEGACYINT_indelay, L0FWDASSERTINTBLEGACYINT => L0FWDASSERTINTBLEGACYINT_indelay, L0FWDASSERTINTCLEGACYINT => L0FWDASSERTINTCLEGACYINT_indelay, L0FWDASSERTINTDLEGACYINT => L0FWDASSERTINTDLEGACYINT_indelay, L0FWDCORRERRIN => L0FWDCORRERRIN_indelay, L0FWDDEASSERTINTALEGACYINT => L0FWDDEASSERTINTALEGACYINT_indelay, L0FWDDEASSERTINTBLEGACYINT => L0FWDDEASSERTINTBLEGACYINT_indelay, L0FWDDEASSERTINTCLEGACYINT => L0FWDDEASSERTINTCLEGACYINT_indelay, L0FWDDEASSERTINTDLEGACYINT => L0FWDDEASSERTINTDLEGACYINT_indelay, L0FWDFATALERRIN => L0FWDFATALERRIN_indelay, L0FWDNONFATALERRIN => L0FWDNONFATALERRIN_indelay, L0LEGACYINTFUNCT0 => L0LEGACYINTFUNCT0_indelay, L0MRLSENSORCLOSEDN => L0MRLSENSORCLOSEDN_indelay, L0MSIREQUEST0 => L0MSIREQUEST0_indelay, L0PACKETHEADERFROMUSER => L0PACKETHEADERFROMUSER_indelay, L0PMEREQIN => L0PMEREQIN_indelay, L0PORTNUMBER => L0PORTNUMBER_indelay, L0POWERFAULTDETECTED => L0POWERFAULTDETECTED_indelay, L0PRESENCEDETECTSLOTEMPTYN => L0PRESENCEDETECTSLOTEMPTYN_indelay, L0PWRNEWSTATEREQ => L0PWRNEWSTATEREQ_indelay, L0PWRNEXTLINKSTATE => L0PWRNEXTLINKSTATE_indelay, L0REPLAYTIMERADJUSTMENT => L0REPLAYTIMERADJUSTMENT_indelay, L0ROOTTURNOFFREQ => L0ROOTTURNOFFREQ_indelay, L0RXTLTLPNONINITIALIZEDVC => L0RXTLTLPNONINITIALIZEDVC_indelay, L0SENDUNLOCKMESSAGE => L0SENDUNLOCKMESSAGE_indelay, L0SETCOMPLETERABORTERROR => L0SETCOMPLETERABORTERROR_indelay, L0SETCOMPLETIONTIMEOUTCORRERROR => L0SETCOMPLETIONTIMEOUTCORRERROR_indelay, L0SETCOMPLETIONTIMEOUTUNCORRERROR => L0SETCOMPLETIONTIMEOUTUNCORRERROR_indelay, L0SETDETECTEDCORRERROR => L0SETDETECTEDCORRERROR_indelay, L0SETDETECTEDFATALERROR => L0SETDETECTEDFATALERROR_indelay, L0SETDETECTEDNONFATALERROR => L0SETDETECTEDNONFATALERROR_indelay, L0SETLINKDETECTEDPARITYERROR => L0SETLINKDETECTEDPARITYERROR_indelay, L0SETLINKMASTERDATAPARITY => L0SETLINKMASTERDATAPARITY_indelay, L0SETLINKRECEIVEDMASTERABORT => L0SETLINKRECEIVEDMASTERABORT_indelay, L0SETLINKRECEIVEDTARGETABORT => L0SETLINKRECEIVEDTARGETABORT_indelay, L0SETLINKSIGNALLEDTARGETABORT => L0SETLINKSIGNALLEDTARGETABORT_indelay, L0SETLINKSYSTEMERROR => L0SETLINKSYSTEMERROR_indelay, L0SETUNEXPECTEDCOMPLETIONCORRERROR => L0SETUNEXPECTEDCOMPLETIONCORRERROR_indelay, L0SETUNEXPECTEDCOMPLETIONUNCORRERROR => L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_indelay, L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR => L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_indelay, L0SETUNSUPPORTEDREQUESTOTHERERROR => L0SETUNSUPPORTEDREQUESTOTHERERROR_indelay, L0SETUSERDETECTEDPARITYERROR => L0SETUSERDETECTEDPARITYERROR_indelay, L0SETUSERMASTERDATAPARITY => L0SETUSERMASTERDATAPARITY_indelay, L0SETUSERRECEIVEDMASTERABORT => L0SETUSERRECEIVEDMASTERABORT_indelay, L0SETUSERRECEIVEDTARGETABORT => L0SETUSERRECEIVEDTARGETABORT_indelay, L0SETUSERSIGNALLEDTARGETABORT => L0SETUSERSIGNALLEDTARGETABORT_indelay, L0SETUSERSYSTEMERROR => L0SETUSERSYSTEMERROR_indelay, L0TLASFCCREDSTARVATION => L0TLASFCCREDSTARVATION_indelay, L0TLLINKRETRAIN => L0TLLINKRETRAIN_indelay, L0TRANSACTIONSPENDING => L0TRANSACTIONSPENDING_indelay, L0TXBEACON => L0TXBEACON_indelay, L0TXCFGPM => L0TXCFGPM_indelay, L0TXCFGPMTYPE => L0TXCFGPMTYPE_indelay, L0TXTLFCCMPLMCCRED => L0TXTLFCCMPLMCCRED_indelay, L0TXTLFCCMPLMCUPDATE => L0TXTLFCCMPLMCUPDATE_indelay, L0TXTLFCNPOSTBYPCRED => L0TXTLFCNPOSTBYPCRED_indelay, L0TXTLFCNPOSTBYPUPDATE => L0TXTLFCNPOSTBYPUPDATE_indelay, L0TXTLFCPOSTORDCRED => L0TXTLFCPOSTORDCRED_indelay, L0TXTLFCPOSTORDUPDATE => L0TXTLFCPOSTORDUPDATE_indelay, L0TXTLSBFCDATA => L0TXTLSBFCDATA_indelay, L0TXTLSBFCUPDATE => L0TXTLSBFCUPDATE_indelay, L0TXTLTLPDATA => L0TXTLTLPDATA_indelay, L0TXTLTLPEDB => L0TXTLTLPEDB_indelay, L0TXTLTLPENABLE => L0TXTLTLPENABLE_indelay, L0TXTLTLPEND => L0TXTLTLPEND_indelay, L0TXTLTLPLATENCY => L0TXTLTLPLATENCY_indelay, L0TXTLTLPREQ => L0TXTLTLPREQ_indelay, L0TXTLTLPREQEND => L0TXTLTLPREQEND_indelay, L0TXTLTLPWIDTH => L0TXTLTLPWIDTH_indelay, L0UPSTREAMRXPORTINL0S => L0UPSTREAMRXPORTINL0S_indelay, L0VC0PREVIEWEXPAND => L0VC0PREVIEWEXPAND_indelay, L0WAKEN => L0WAKEN_indelay, LLKRXCHFIFO => LLKRXCHFIFO_indelay, LLKRXCHTC => LLKRXCHTC_indelay, LLKRXDSTCONTREQN => LLKRXDSTCONTREQN_indelay, LLKRXDSTREQN => LLKRXDSTREQN_indelay, LLKTX4DWHEADERN => LLKTX4DWHEADERN_indelay, LLKTXCHFIFO => LLKTXCHFIFO_indelay, LLKTXCHTC => LLKTXCHTC_indelay, LLKTXCOMPLETEN => LLKTXCOMPLETEN_indelay, LLKTXCREATEECRCN => LLKTXCREATEECRCN_indelay, LLKTXDATA => LLKTXDATA_indelay, LLKTXENABLEN => LLKTXENABLEN_indelay, LLKTXEOFN => LLKTXEOFN_indelay, LLKTXEOPN => LLKTXEOPN_indelay, LLKTXSOFN => LLKTXSOFN_indelay, LLKTXSOPN => LLKTXSOPN_indelay, LLKTXSRCDSCN => LLKTXSRCDSCN_indelay, LLKTXSRCRDYN => LLKTXSRCRDYN_indelay, MAINPOWER => MAINPOWER_indelay, MGMTADDR => MGMTADDR_indelay, MGMTBWREN => MGMTBWREN_indelay, MGMTRDEN => MGMTRDEN_indelay, MGMTSTATSCREDITSEL => MGMTSTATSCREDITSEL_indelay, MGMTWDATA => MGMTWDATA_indelay, MGMTWREN => MGMTWREN_indelay, MIMDLLBRDATA => MIMDLLBRDATA_indelay, MIMRXBRDATA => MIMRXBRDATA_indelay, MIMTXBRDATA => MIMTXBRDATA_indelay, PIPEPHYSTATUSL0 => PIPEPHYSTATUSL0_indelay, PIPEPHYSTATUSL1 => PIPEPHYSTATUSL1_indelay, PIPEPHYSTATUSL2 => PIPEPHYSTATUSL2_indelay, PIPEPHYSTATUSL3 => PIPEPHYSTATUSL3_indelay, PIPEPHYSTATUSL4 => PIPEPHYSTATUSL4_indelay, PIPEPHYSTATUSL5 => PIPEPHYSTATUSL5_indelay, PIPEPHYSTATUSL6 => PIPEPHYSTATUSL6_indelay, PIPEPHYSTATUSL7 => PIPEPHYSTATUSL7_indelay, PIPERXCHANISALIGNEDL0 => PIPERXCHANISALIGNEDL0_indelay, PIPERXCHANISALIGNEDL1 => PIPERXCHANISALIGNEDL1_indelay, PIPERXCHANISALIGNEDL2 => PIPERXCHANISALIGNEDL2_indelay, PIPERXCHANISALIGNEDL3 => PIPERXCHANISALIGNEDL3_indelay, PIPERXCHANISALIGNEDL4 => PIPERXCHANISALIGNEDL4_indelay, PIPERXCHANISALIGNEDL5 => PIPERXCHANISALIGNEDL5_indelay, PIPERXCHANISALIGNEDL6 => PIPERXCHANISALIGNEDL6_indelay, PIPERXCHANISALIGNEDL7 => PIPERXCHANISALIGNEDL7_indelay, PIPERXDATAKL0 => PIPERXDATAKL0_indelay, PIPERXDATAKL1 => PIPERXDATAKL1_indelay, PIPERXDATAKL2 => PIPERXDATAKL2_indelay, PIPERXDATAKL3 => PIPERXDATAKL3_indelay, PIPERXDATAKL4 => PIPERXDATAKL4_indelay, PIPERXDATAKL5 => PIPERXDATAKL5_indelay, PIPERXDATAKL6 => PIPERXDATAKL6_indelay, PIPERXDATAKL7 => PIPERXDATAKL7_indelay, PIPERXDATAL0 => PIPERXDATAL0_indelay, PIPERXDATAL1 => PIPERXDATAL1_indelay, PIPERXDATAL2 => PIPERXDATAL2_indelay, PIPERXDATAL3 => PIPERXDATAL3_indelay, PIPERXDATAL4 => PIPERXDATAL4_indelay, PIPERXDATAL5 => PIPERXDATAL5_indelay, PIPERXDATAL6 => PIPERXDATAL6_indelay, PIPERXDATAL7 => PIPERXDATAL7_indelay, PIPERXELECIDLEL0 => PIPERXELECIDLEL0_indelay, PIPERXELECIDLEL1 => PIPERXELECIDLEL1_indelay, PIPERXELECIDLEL2 => PIPERXELECIDLEL2_indelay, PIPERXELECIDLEL3 => PIPERXELECIDLEL3_indelay, PIPERXELECIDLEL4 => PIPERXELECIDLEL4_indelay, PIPERXELECIDLEL5 => PIPERXELECIDLEL5_indelay, PIPERXELECIDLEL6 => PIPERXELECIDLEL6_indelay, PIPERXELECIDLEL7 => PIPERXELECIDLEL7_indelay, PIPERXSTATUSL0 => PIPERXSTATUSL0_indelay, PIPERXSTATUSL1 => PIPERXSTATUSL1_indelay, PIPERXSTATUSL2 => PIPERXSTATUSL2_indelay, PIPERXSTATUSL3 => PIPERXSTATUSL3_indelay, PIPERXSTATUSL4 => PIPERXSTATUSL4_indelay, PIPERXSTATUSL5 => PIPERXSTATUSL5_indelay, PIPERXSTATUSL6 => PIPERXSTATUSL6_indelay, PIPERXSTATUSL7 => PIPERXSTATUSL7_indelay, PIPERXVALIDL0 => PIPERXVALIDL0_indelay, PIPERXVALIDL1 => PIPERXVALIDL1_indelay, PIPERXVALIDL2 => PIPERXVALIDL2_indelay, PIPERXVALIDL3 => PIPERXVALIDL3_indelay, PIPERXVALIDL4 => PIPERXVALIDL4_indelay, PIPERXVALIDL5 => PIPERXVALIDL5_indelay, PIPERXVALIDL6 => PIPERXVALIDL6_indelay, PIPERXVALIDL7 => PIPERXVALIDL7_indelay ); INIPROC : process begin case TXTSNFTS is when 0 => TXTSNFTS_BINARY <= "00000000"; when 1 => TXTSNFTS_BINARY <= "00000001"; when 2 => TXTSNFTS_BINARY <= "00000010"; when 3 => TXTSNFTS_BINARY <= "00000011"; when 4 => TXTSNFTS_BINARY <= "00000100"; when 5 => TXTSNFTS_BINARY <= "00000101"; when 6 => TXTSNFTS_BINARY <= "00000110"; when 7 => TXTSNFTS_BINARY <= "00000111"; when 8 => TXTSNFTS_BINARY <= "00001000"; when 9 => TXTSNFTS_BINARY <= "00001001"; when 10 => TXTSNFTS_BINARY <= "00001010"; when 11 => TXTSNFTS_BINARY <= "00001011"; when 12 => TXTSNFTS_BINARY <= "00001100"; when 13 => TXTSNFTS_BINARY <= "00001101"; when 14 => TXTSNFTS_BINARY <= "00001110"; when 15 => TXTSNFTS_BINARY <= "00001111"; when 16 => TXTSNFTS_BINARY <= "00010000"; when 17 => TXTSNFTS_BINARY <= "00010001"; when 18 => TXTSNFTS_BINARY <= "00010010"; when 19 => TXTSNFTS_BINARY <= "00010011"; when 20 => TXTSNFTS_BINARY <= "00010100"; when 21 => TXTSNFTS_BINARY <= "00010101"; when 22 => TXTSNFTS_BINARY <= "00010110"; when 23 => TXTSNFTS_BINARY <= "00010111"; when 24 => TXTSNFTS_BINARY <= "00011000"; when 25 => TXTSNFTS_BINARY <= "00011001"; when 26 => TXTSNFTS_BINARY <= "00011010"; when 27 => TXTSNFTS_BINARY <= "00011011"; when 28 => TXTSNFTS_BINARY <= "00011100"; when 29 => TXTSNFTS_BINARY <= "00011101"; when 30 => TXTSNFTS_BINARY <= "00011110"; when 31 => TXTSNFTS_BINARY <= "00011111"; when 32 => TXTSNFTS_BINARY <= "00100000"; when 33 => TXTSNFTS_BINARY <= "00100001"; when 34 => TXTSNFTS_BINARY <= "00100010"; when 35 => TXTSNFTS_BINARY <= "00100011"; when 36 => TXTSNFTS_BINARY <= "00100100"; when 37 => TXTSNFTS_BINARY <= "00100101"; when 38 => TXTSNFTS_BINARY <= "00100110"; when 39 => TXTSNFTS_BINARY <= "00100111"; when 40 => TXTSNFTS_BINARY <= "00101000"; when 41 => TXTSNFTS_BINARY <= "00101001"; when 42 => TXTSNFTS_BINARY <= "00101010"; when 43 => TXTSNFTS_BINARY <= "00101011"; when 44 => TXTSNFTS_BINARY <= "00101100"; when 45 => TXTSNFTS_BINARY <= "00101101"; when 46 => TXTSNFTS_BINARY <= "00101110"; when 47 => TXTSNFTS_BINARY <= "00101111"; when 48 => TXTSNFTS_BINARY <= "00110000"; when 49 => TXTSNFTS_BINARY <= "00110001"; when 50 => TXTSNFTS_BINARY <= "00110010"; when 51 => TXTSNFTS_BINARY <= "00110011"; when 52 => TXTSNFTS_BINARY <= "00110100"; when 53 => TXTSNFTS_BINARY <= "00110101"; when 54 => TXTSNFTS_BINARY <= "00110110"; when 55 => TXTSNFTS_BINARY <= "00110111"; when 56 => TXTSNFTS_BINARY <= "00111000"; when 57 => TXTSNFTS_BINARY <= "00111001"; when 58 => TXTSNFTS_BINARY <= "00111010"; when 59 => TXTSNFTS_BINARY <= "00111011"; when 60 => TXTSNFTS_BINARY <= "00111100"; when 61 => TXTSNFTS_BINARY <= "00111101"; when 62 => TXTSNFTS_BINARY <= "00111110"; when 63 => TXTSNFTS_BINARY <= "00111111"; when 64 => TXTSNFTS_BINARY <= "01000000"; when 65 => TXTSNFTS_BINARY <= "01000001"; when 66 => TXTSNFTS_BINARY <= "01000010"; when 67 => TXTSNFTS_BINARY <= "01000011"; when 68 => TXTSNFTS_BINARY <= "01000100"; when 69 => TXTSNFTS_BINARY <= "01000101"; when 70 => TXTSNFTS_BINARY <= "01000110"; when 71 => TXTSNFTS_BINARY <= "01000111"; when 72 => TXTSNFTS_BINARY <= "01001000"; when 73 => TXTSNFTS_BINARY <= "01001001"; when 74 => TXTSNFTS_BINARY <= "01001010"; when 75 => TXTSNFTS_BINARY <= "01001011"; when 76 => TXTSNFTS_BINARY <= "01001100"; when 77 => TXTSNFTS_BINARY <= "01001101"; when 78 => TXTSNFTS_BINARY <= "01001110"; when 79 => TXTSNFTS_BINARY <= "01001111"; when 80 => TXTSNFTS_BINARY <= "01010000"; when 81 => TXTSNFTS_BINARY <= "01010001"; when 82 => TXTSNFTS_BINARY <= "01010010"; when 83 => TXTSNFTS_BINARY <= "01010011"; when 84 => TXTSNFTS_BINARY <= "01010100"; when 85 => TXTSNFTS_BINARY <= "01010101"; when 86 => TXTSNFTS_BINARY <= "01010110"; when 87 => TXTSNFTS_BINARY <= "01010111"; when 88 => TXTSNFTS_BINARY <= "01011000"; when 89 => TXTSNFTS_BINARY <= "01011001"; when 90 => TXTSNFTS_BINARY <= "01011010"; when 91 => TXTSNFTS_BINARY <= "01011011"; when 92 => TXTSNFTS_BINARY <= "01011100"; when 93 => TXTSNFTS_BINARY <= "01011101"; when 94 => TXTSNFTS_BINARY <= "01011110"; when 95 => TXTSNFTS_BINARY <= "01011111"; when 96 => TXTSNFTS_BINARY <= "01100000"; when 97 => TXTSNFTS_BINARY <= "01100001"; when 98 => TXTSNFTS_BINARY <= "01100010"; when 99 => TXTSNFTS_BINARY <= "01100011"; when 100 => TXTSNFTS_BINARY <= "01100100"; when 101 => TXTSNFTS_BINARY <= "01100101"; when 102 => TXTSNFTS_BINARY <= "01100110"; when 103 => TXTSNFTS_BINARY <= "01100111"; when 104 => TXTSNFTS_BINARY <= "01101000"; when 105 => TXTSNFTS_BINARY <= "01101001"; when 106 => TXTSNFTS_BINARY <= "01101010"; when 107 => TXTSNFTS_BINARY <= "01101011"; when 108 => TXTSNFTS_BINARY <= "01101100"; when 109 => TXTSNFTS_BINARY <= "01101101"; when 110 => TXTSNFTS_BINARY <= "01101110"; when 111 => TXTSNFTS_BINARY <= "01101111"; when 112 => TXTSNFTS_BINARY <= "01110000"; when 113 => TXTSNFTS_BINARY <= "01110001"; when 114 => TXTSNFTS_BINARY <= "01110010"; when 115 => TXTSNFTS_BINARY <= "01110011"; when 116 => TXTSNFTS_BINARY <= "01110100"; when 117 => TXTSNFTS_BINARY <= "01110101"; when 118 => TXTSNFTS_BINARY <= "01110110"; when 119 => TXTSNFTS_BINARY <= "01110111"; when 120 => TXTSNFTS_BINARY <= "01111000"; when 121 => TXTSNFTS_BINARY <= "01111001"; when 122 => TXTSNFTS_BINARY <= "01111010"; when 123 => TXTSNFTS_BINARY <= "01111011"; when 124 => TXTSNFTS_BINARY <= "01111100"; when 125 => TXTSNFTS_BINARY <= "01111101"; when 126 => TXTSNFTS_BINARY <= "01111110"; when 127 => TXTSNFTS_BINARY <= "01111111"; when 128 => TXTSNFTS_BINARY <= "10000000"; when 129 => TXTSNFTS_BINARY <= "10000001"; when 130 => TXTSNFTS_BINARY <= "10000010"; when 131 => TXTSNFTS_BINARY <= "10000011"; when 132 => TXTSNFTS_BINARY <= "10000100"; when 133 => TXTSNFTS_BINARY <= "10000101"; when 134 => TXTSNFTS_BINARY <= "10000110"; when 135 => TXTSNFTS_BINARY <= "10000111"; when 136 => TXTSNFTS_BINARY <= "10001000"; when 137 => TXTSNFTS_BINARY <= "10001001"; when 138 => TXTSNFTS_BINARY <= "10001010"; when 139 => TXTSNFTS_BINARY <= "10001011"; when 140 => TXTSNFTS_BINARY <= "10001100"; when 141 => TXTSNFTS_BINARY <= "10001101"; when 142 => TXTSNFTS_BINARY <= "10001110"; when 143 => TXTSNFTS_BINARY <= "10001111"; when 144 => TXTSNFTS_BINARY <= "10010000"; when 145 => TXTSNFTS_BINARY <= "10010001"; when 146 => TXTSNFTS_BINARY <= "10010010"; when 147 => TXTSNFTS_BINARY <= "10010011"; when 148 => TXTSNFTS_BINARY <= "10010100"; when 149 => TXTSNFTS_BINARY <= "10010101"; when 150 => TXTSNFTS_BINARY <= "10010110"; when 151 => TXTSNFTS_BINARY <= "10010111"; when 152 => TXTSNFTS_BINARY <= "10011000"; when 153 => TXTSNFTS_BINARY <= "10011001"; when 154 => TXTSNFTS_BINARY <= "10011010"; when 155 => TXTSNFTS_BINARY <= "10011011"; when 156 => TXTSNFTS_BINARY <= "10011100"; when 157 => TXTSNFTS_BINARY <= "10011101"; when 158 => TXTSNFTS_BINARY <= "10011110"; when 159 => TXTSNFTS_BINARY <= "10011111"; when 160 => TXTSNFTS_BINARY <= "10100000"; when 161 => TXTSNFTS_BINARY <= "10100001"; when 162 => TXTSNFTS_BINARY <= "10100010"; when 163 => TXTSNFTS_BINARY <= "10100011"; when 164 => TXTSNFTS_BINARY <= "10100100"; when 165 => TXTSNFTS_BINARY <= "10100101"; when 166 => TXTSNFTS_BINARY <= "10100110"; when 167 => TXTSNFTS_BINARY <= "10100111"; when 168 => TXTSNFTS_BINARY <= "10101000"; when 169 => TXTSNFTS_BINARY <= "10101001"; when 170 => TXTSNFTS_BINARY <= "10101010"; when 171 => TXTSNFTS_BINARY <= "10101011"; when 172 => TXTSNFTS_BINARY <= "10101100"; when 173 => TXTSNFTS_BINARY <= "10101101"; when 174 => TXTSNFTS_BINARY <= "10101110"; when 175 => TXTSNFTS_BINARY <= "10101111"; when 176 => TXTSNFTS_BINARY <= "10110000"; when 177 => TXTSNFTS_BINARY <= "10110001"; when 178 => TXTSNFTS_BINARY <= "10110010"; when 179 => TXTSNFTS_BINARY <= "10110011"; when 180 => TXTSNFTS_BINARY <= "10110100"; when 181 => TXTSNFTS_BINARY <= "10110101"; when 182 => TXTSNFTS_BINARY <= "10110110"; when 183 => TXTSNFTS_BINARY <= "10110111"; when 184 => TXTSNFTS_BINARY <= "10111000"; when 185 => TXTSNFTS_BINARY <= "10111001"; when 186 => TXTSNFTS_BINARY <= "10111010"; when 187 => TXTSNFTS_BINARY <= "10111011"; when 188 => TXTSNFTS_BINARY <= "10111100"; when 189 => TXTSNFTS_BINARY <= "10111101"; when 190 => TXTSNFTS_BINARY <= "10111110"; when 191 => TXTSNFTS_BINARY <= "10111111"; when 192 => TXTSNFTS_BINARY <= "11000000"; when 193 => TXTSNFTS_BINARY <= "11000001"; when 194 => TXTSNFTS_BINARY <= "11000010"; when 195 => TXTSNFTS_BINARY <= "11000011"; when 196 => TXTSNFTS_BINARY <= "11000100"; when 197 => TXTSNFTS_BINARY <= "11000101"; when 198 => TXTSNFTS_BINARY <= "11000110"; when 199 => TXTSNFTS_BINARY <= "11000111"; when 200 => TXTSNFTS_BINARY <= "11001000"; when 201 => TXTSNFTS_BINARY <= "11001001"; when 202 => TXTSNFTS_BINARY <= "11001010"; when 203 => TXTSNFTS_BINARY <= "11001011"; when 204 => TXTSNFTS_BINARY <= "11001100"; when 205 => TXTSNFTS_BINARY <= "11001101"; when 206 => TXTSNFTS_BINARY <= "11001110"; when 207 => TXTSNFTS_BINARY <= "11001111"; when 208 => TXTSNFTS_BINARY <= "11010000"; when 209 => TXTSNFTS_BINARY <= "11010001"; when 210 => TXTSNFTS_BINARY <= "11010010"; when 211 => TXTSNFTS_BINARY <= "11010011"; when 212 => TXTSNFTS_BINARY <= "11010100"; when 213 => TXTSNFTS_BINARY <= "11010101"; when 214 => TXTSNFTS_BINARY <= "11010110"; when 215 => TXTSNFTS_BINARY <= "11010111"; when 216 => TXTSNFTS_BINARY <= "11011000"; when 217 => TXTSNFTS_BINARY <= "11011001"; when 218 => TXTSNFTS_BINARY <= "11011010"; when 219 => TXTSNFTS_BINARY <= "11011011"; when 220 => TXTSNFTS_BINARY <= "11011100"; when 221 => TXTSNFTS_BINARY <= "11011101"; when 222 => TXTSNFTS_BINARY <= "11011110"; when 223 => TXTSNFTS_BINARY <= "11011111"; when 224 => TXTSNFTS_BINARY <= "11100000"; when 225 => TXTSNFTS_BINARY <= "11100001"; when 226 => TXTSNFTS_BINARY <= "11100010"; when 227 => TXTSNFTS_BINARY <= "11100011"; when 228 => TXTSNFTS_BINARY <= "11100100"; when 229 => TXTSNFTS_BINARY <= "11100101"; when 230 => TXTSNFTS_BINARY <= "11100110"; when 231 => TXTSNFTS_BINARY <= "11100111"; when 232 => TXTSNFTS_BINARY <= "11101000"; when 233 => TXTSNFTS_BINARY <= "11101001"; when 234 => TXTSNFTS_BINARY <= "11101010"; when 235 => TXTSNFTS_BINARY <= "11101011"; when 236 => TXTSNFTS_BINARY <= "11101100"; when 237 => TXTSNFTS_BINARY <= "11101101"; when 238 => TXTSNFTS_BINARY <= "11101110"; when 239 => TXTSNFTS_BINARY <= "11101111"; when 240 => TXTSNFTS_BINARY <= "11110000"; when 241 => TXTSNFTS_BINARY <= "11110001"; when 242 => TXTSNFTS_BINARY <= "11110010"; when 243 => TXTSNFTS_BINARY <= "11110011"; when 244 => TXTSNFTS_BINARY <= "11110100"; when 245 => TXTSNFTS_BINARY <= "11110101"; when 246 => TXTSNFTS_BINARY <= "11110110"; when 247 => TXTSNFTS_BINARY <= "11110111"; when 248 => TXTSNFTS_BINARY <= "11111000"; when 249 => TXTSNFTS_BINARY <= "11111001"; when 250 => TXTSNFTS_BINARY <= "11111010"; when 251 => TXTSNFTS_BINARY <= "11111011"; when 252 => TXTSNFTS_BINARY <= "11111100"; when 253 => TXTSNFTS_BINARY <= "11111101"; when 254 => TXTSNFTS_BINARY <= "11111110"; when 255 => TXTSNFTS_BINARY <= "11111111"; when others => assert FALSE report "Error : TXTSNFTS is not in range 0...255." severity error; end case; case TXTSNFTSCOMCLK is when 0 => TXTSNFTSCOMCLK_BINARY <= "00000000"; when 1 => TXTSNFTSCOMCLK_BINARY <= "00000001"; when 2 => TXTSNFTSCOMCLK_BINARY <= "00000010"; when 3 => TXTSNFTSCOMCLK_BINARY <= "00000011"; when 4 => TXTSNFTSCOMCLK_BINARY <= "00000100"; when 5 => TXTSNFTSCOMCLK_BINARY <= "00000101"; when 6 => TXTSNFTSCOMCLK_BINARY <= "00000110"; when 7 => TXTSNFTSCOMCLK_BINARY <= "00000111"; when 8 => TXTSNFTSCOMCLK_BINARY <= "00001000"; when 9 => TXTSNFTSCOMCLK_BINARY <= "00001001"; when 10 => TXTSNFTSCOMCLK_BINARY <= "00001010"; when 11 => TXTSNFTSCOMCLK_BINARY <= "00001011"; when 12 => TXTSNFTSCOMCLK_BINARY <= "00001100"; when 13 => TXTSNFTSCOMCLK_BINARY <= "00001101"; when 14 => TXTSNFTSCOMCLK_BINARY <= "00001110"; when 15 => TXTSNFTSCOMCLK_BINARY <= "00001111"; when 16 => TXTSNFTSCOMCLK_BINARY <= "00010000"; when 17 => TXTSNFTSCOMCLK_BINARY <= "00010001"; when 18 => TXTSNFTSCOMCLK_BINARY <= "00010010"; when 19 => TXTSNFTSCOMCLK_BINARY <= "00010011"; when 20 => TXTSNFTSCOMCLK_BINARY <= "00010100"; when 21 => TXTSNFTSCOMCLK_BINARY <= "00010101"; when 22 => TXTSNFTSCOMCLK_BINARY <= "00010110"; when 23 => TXTSNFTSCOMCLK_BINARY <= "00010111"; when 24 => TXTSNFTSCOMCLK_BINARY <= "00011000"; when 25 => TXTSNFTSCOMCLK_BINARY <= "00011001"; when 26 => TXTSNFTSCOMCLK_BINARY <= "00011010"; when 27 => TXTSNFTSCOMCLK_BINARY <= "00011011"; when 28 => TXTSNFTSCOMCLK_BINARY <= "00011100"; when 29 => TXTSNFTSCOMCLK_BINARY <= "00011101"; when 30 => TXTSNFTSCOMCLK_BINARY <= "00011110"; when 31 => TXTSNFTSCOMCLK_BINARY <= "00011111"; when 32 => TXTSNFTSCOMCLK_BINARY <= "00100000"; when 33 => TXTSNFTSCOMCLK_BINARY <= "00100001"; when 34 => TXTSNFTSCOMCLK_BINARY <= "00100010"; when 35 => TXTSNFTSCOMCLK_BINARY <= "00100011"; when 36 => TXTSNFTSCOMCLK_BINARY <= "00100100"; when 37 => TXTSNFTSCOMCLK_BINARY <= "00100101"; when 38 => TXTSNFTSCOMCLK_BINARY <= "00100110"; when 39 => TXTSNFTSCOMCLK_BINARY <= "00100111"; when 40 => TXTSNFTSCOMCLK_BINARY <= "00101000"; when 41 => TXTSNFTSCOMCLK_BINARY <= "00101001"; when 42 => TXTSNFTSCOMCLK_BINARY <= "00101010"; when 43 => TXTSNFTSCOMCLK_BINARY <= "00101011"; when 44 => TXTSNFTSCOMCLK_BINARY <= "00101100"; when 45 => TXTSNFTSCOMCLK_BINARY <= "00101101"; when 46 => TXTSNFTSCOMCLK_BINARY <= "00101110"; when 47 => TXTSNFTSCOMCLK_BINARY <= "00101111"; when 48 => TXTSNFTSCOMCLK_BINARY <= "00110000"; when 49 => TXTSNFTSCOMCLK_BINARY <= "00110001"; when 50 => TXTSNFTSCOMCLK_BINARY <= "00110010"; when 51 => TXTSNFTSCOMCLK_BINARY <= "00110011"; when 52 => TXTSNFTSCOMCLK_BINARY <= "00110100"; when 53 => TXTSNFTSCOMCLK_BINARY <= "00110101"; when 54 => TXTSNFTSCOMCLK_BINARY <= "00110110"; when 55 => TXTSNFTSCOMCLK_BINARY <= "00110111"; when 56 => TXTSNFTSCOMCLK_BINARY <= "00111000"; when 57 => TXTSNFTSCOMCLK_BINARY <= "00111001"; when 58 => TXTSNFTSCOMCLK_BINARY <= "00111010"; when 59 => TXTSNFTSCOMCLK_BINARY <= "00111011"; when 60 => TXTSNFTSCOMCLK_BINARY <= "00111100"; when 61 => TXTSNFTSCOMCLK_BINARY <= "00111101"; when 62 => TXTSNFTSCOMCLK_BINARY <= "00111110"; when 63 => TXTSNFTSCOMCLK_BINARY <= "00111111"; when 64 => TXTSNFTSCOMCLK_BINARY <= "01000000"; when 65 => TXTSNFTSCOMCLK_BINARY <= "01000001"; when 66 => TXTSNFTSCOMCLK_BINARY <= "01000010"; when 67 => TXTSNFTSCOMCLK_BINARY <= "01000011"; when 68 => TXTSNFTSCOMCLK_BINARY <= "01000100"; when 69 => TXTSNFTSCOMCLK_BINARY <= "01000101"; when 70 => TXTSNFTSCOMCLK_BINARY <= "01000110"; when 71 => TXTSNFTSCOMCLK_BINARY <= "01000111"; when 72 => TXTSNFTSCOMCLK_BINARY <= "01001000"; when 73 => TXTSNFTSCOMCLK_BINARY <= "01001001"; when 74 => TXTSNFTSCOMCLK_BINARY <= "01001010"; when 75 => TXTSNFTSCOMCLK_BINARY <= "01001011"; when 76 => TXTSNFTSCOMCLK_BINARY <= "01001100"; when 77 => TXTSNFTSCOMCLK_BINARY <= "01001101"; when 78 => TXTSNFTSCOMCLK_BINARY <= "01001110"; when 79 => TXTSNFTSCOMCLK_BINARY <= "01001111"; when 80 => TXTSNFTSCOMCLK_BINARY <= "01010000"; when 81 => TXTSNFTSCOMCLK_BINARY <= "01010001"; when 82 => TXTSNFTSCOMCLK_BINARY <= "01010010"; when 83 => TXTSNFTSCOMCLK_BINARY <= "01010011"; when 84 => TXTSNFTSCOMCLK_BINARY <= "01010100"; when 85 => TXTSNFTSCOMCLK_BINARY <= "01010101"; when 86 => TXTSNFTSCOMCLK_BINARY <= "01010110"; when 87 => TXTSNFTSCOMCLK_BINARY <= "01010111"; when 88 => TXTSNFTSCOMCLK_BINARY <= "01011000"; when 89 => TXTSNFTSCOMCLK_BINARY <= "01011001"; when 90 => TXTSNFTSCOMCLK_BINARY <= "01011010"; when 91 => TXTSNFTSCOMCLK_BINARY <= "01011011"; when 92 => TXTSNFTSCOMCLK_BINARY <= "01011100"; when 93 => TXTSNFTSCOMCLK_BINARY <= "01011101"; when 94 => TXTSNFTSCOMCLK_BINARY <= "01011110"; when 95 => TXTSNFTSCOMCLK_BINARY <= "01011111"; when 96 => TXTSNFTSCOMCLK_BINARY <= "01100000"; when 97 => TXTSNFTSCOMCLK_BINARY <= "01100001"; when 98 => TXTSNFTSCOMCLK_BINARY <= "01100010"; when 99 => TXTSNFTSCOMCLK_BINARY <= "01100011"; when 100 => TXTSNFTSCOMCLK_BINARY <= "01100100"; when 101 => TXTSNFTSCOMCLK_BINARY <= "01100101"; when 102 => TXTSNFTSCOMCLK_BINARY <= "01100110"; when 103 => TXTSNFTSCOMCLK_BINARY <= "01100111"; when 104 => TXTSNFTSCOMCLK_BINARY <= "01101000"; when 105 => TXTSNFTSCOMCLK_BINARY <= "01101001"; when 106 => TXTSNFTSCOMCLK_BINARY <= "01101010"; when 107 => TXTSNFTSCOMCLK_BINARY <= "01101011"; when 108 => TXTSNFTSCOMCLK_BINARY <= "01101100"; when 109 => TXTSNFTSCOMCLK_BINARY <= "01101101"; when 110 => TXTSNFTSCOMCLK_BINARY <= "01101110"; when 111 => TXTSNFTSCOMCLK_BINARY <= "01101111"; when 112 => TXTSNFTSCOMCLK_BINARY <= "01110000"; when 113 => TXTSNFTSCOMCLK_BINARY <= "01110001"; when 114 => TXTSNFTSCOMCLK_BINARY <= "01110010"; when 115 => TXTSNFTSCOMCLK_BINARY <= "01110011"; when 116 => TXTSNFTSCOMCLK_BINARY <= "01110100"; when 117 => TXTSNFTSCOMCLK_BINARY <= "01110101"; when 118 => TXTSNFTSCOMCLK_BINARY <= "01110110"; when 119 => TXTSNFTSCOMCLK_BINARY <= "01110111"; when 120 => TXTSNFTSCOMCLK_BINARY <= "01111000"; when 121 => TXTSNFTSCOMCLK_BINARY <= "01111001"; when 122 => TXTSNFTSCOMCLK_BINARY <= "01111010"; when 123 => TXTSNFTSCOMCLK_BINARY <= "01111011"; when 124 => TXTSNFTSCOMCLK_BINARY <= "01111100"; when 125 => TXTSNFTSCOMCLK_BINARY <= "01111101"; when 126 => TXTSNFTSCOMCLK_BINARY <= "01111110"; when 127 => TXTSNFTSCOMCLK_BINARY <= "01111111"; when 128 => TXTSNFTSCOMCLK_BINARY <= "10000000"; when 129 => TXTSNFTSCOMCLK_BINARY <= "10000001"; when 130 => TXTSNFTSCOMCLK_BINARY <= "10000010"; when 131 => TXTSNFTSCOMCLK_BINARY <= "10000011"; when 132 => TXTSNFTSCOMCLK_BINARY <= "10000100"; when 133 => TXTSNFTSCOMCLK_BINARY <= "10000101"; when 134 => TXTSNFTSCOMCLK_BINARY <= "10000110"; when 135 => TXTSNFTSCOMCLK_BINARY <= "10000111"; when 136 => TXTSNFTSCOMCLK_BINARY <= "10001000"; when 137 => TXTSNFTSCOMCLK_BINARY <= "10001001"; when 138 => TXTSNFTSCOMCLK_BINARY <= "10001010"; when 139 => TXTSNFTSCOMCLK_BINARY <= "10001011"; when 140 => TXTSNFTSCOMCLK_BINARY <= "10001100"; when 141 => TXTSNFTSCOMCLK_BINARY <= "10001101"; when 142 => TXTSNFTSCOMCLK_BINARY <= "10001110"; when 143 => TXTSNFTSCOMCLK_BINARY <= "10001111"; when 144 => TXTSNFTSCOMCLK_BINARY <= "10010000"; when 145 => TXTSNFTSCOMCLK_BINARY <= "10010001"; when 146 => TXTSNFTSCOMCLK_BINARY <= "10010010"; when 147 => TXTSNFTSCOMCLK_BINARY <= "10010011"; when 148 => TXTSNFTSCOMCLK_BINARY <= "10010100"; when 149 => TXTSNFTSCOMCLK_BINARY <= "10010101"; when 150 => TXTSNFTSCOMCLK_BINARY <= "10010110"; when 151 => TXTSNFTSCOMCLK_BINARY <= "10010111"; when 152 => TXTSNFTSCOMCLK_BINARY <= "10011000"; when 153 => TXTSNFTSCOMCLK_BINARY <= "10011001"; when 154 => TXTSNFTSCOMCLK_BINARY <= "10011010"; when 155 => TXTSNFTSCOMCLK_BINARY <= "10011011"; when 156 => TXTSNFTSCOMCLK_BINARY <= "10011100"; when 157 => TXTSNFTSCOMCLK_BINARY <= "10011101"; when 158 => TXTSNFTSCOMCLK_BINARY <= "10011110"; when 159 => TXTSNFTSCOMCLK_BINARY <= "10011111"; when 160 => TXTSNFTSCOMCLK_BINARY <= "10100000"; when 161 => TXTSNFTSCOMCLK_BINARY <= "10100001"; when 162 => TXTSNFTSCOMCLK_BINARY <= "10100010"; when 163 => TXTSNFTSCOMCLK_BINARY <= "10100011"; when 164 => TXTSNFTSCOMCLK_BINARY <= "10100100"; when 165 => TXTSNFTSCOMCLK_BINARY <= "10100101"; when 166 => TXTSNFTSCOMCLK_BINARY <= "10100110"; when 167 => TXTSNFTSCOMCLK_BINARY <= "10100111"; when 168 => TXTSNFTSCOMCLK_BINARY <= "10101000"; when 169 => TXTSNFTSCOMCLK_BINARY <= "10101001"; when 170 => TXTSNFTSCOMCLK_BINARY <= "10101010"; when 171 => TXTSNFTSCOMCLK_BINARY <= "10101011"; when 172 => TXTSNFTSCOMCLK_BINARY <= "10101100"; when 173 => TXTSNFTSCOMCLK_BINARY <= "10101101"; when 174 => TXTSNFTSCOMCLK_BINARY <= "10101110"; when 175 => TXTSNFTSCOMCLK_BINARY <= "10101111"; when 176 => TXTSNFTSCOMCLK_BINARY <= "10110000"; when 177 => TXTSNFTSCOMCLK_BINARY <= "10110001"; when 178 => TXTSNFTSCOMCLK_BINARY <= "10110010"; when 179 => TXTSNFTSCOMCLK_BINARY <= "10110011"; when 180 => TXTSNFTSCOMCLK_BINARY <= "10110100"; when 181 => TXTSNFTSCOMCLK_BINARY <= "10110101"; when 182 => TXTSNFTSCOMCLK_BINARY <= "10110110"; when 183 => TXTSNFTSCOMCLK_BINARY <= "10110111"; when 184 => TXTSNFTSCOMCLK_BINARY <= "10111000"; when 185 => TXTSNFTSCOMCLK_BINARY <= "10111001"; when 186 => TXTSNFTSCOMCLK_BINARY <= "10111010"; when 187 => TXTSNFTSCOMCLK_BINARY <= "10111011"; when 188 => TXTSNFTSCOMCLK_BINARY <= "10111100"; when 189 => TXTSNFTSCOMCLK_BINARY <= "10111101"; when 190 => TXTSNFTSCOMCLK_BINARY <= "10111110"; when 191 => TXTSNFTSCOMCLK_BINARY <= "10111111"; when 192 => TXTSNFTSCOMCLK_BINARY <= "11000000"; when 193 => TXTSNFTSCOMCLK_BINARY <= "11000001"; when 194 => TXTSNFTSCOMCLK_BINARY <= "11000010"; when 195 => TXTSNFTSCOMCLK_BINARY <= "11000011"; when 196 => TXTSNFTSCOMCLK_BINARY <= "11000100"; when 197 => TXTSNFTSCOMCLK_BINARY <= "11000101"; when 198 => TXTSNFTSCOMCLK_BINARY <= "11000110"; when 199 => TXTSNFTSCOMCLK_BINARY <= "11000111"; when 200 => TXTSNFTSCOMCLK_BINARY <= "11001000"; when 201 => TXTSNFTSCOMCLK_BINARY <= "11001001"; when 202 => TXTSNFTSCOMCLK_BINARY <= "11001010"; when 203 => TXTSNFTSCOMCLK_BINARY <= "11001011"; when 204 => TXTSNFTSCOMCLK_BINARY <= "11001100"; when 205 => TXTSNFTSCOMCLK_BINARY <= "11001101"; when 206 => TXTSNFTSCOMCLK_BINARY <= "11001110"; when 207 => TXTSNFTSCOMCLK_BINARY <= "11001111"; when 208 => TXTSNFTSCOMCLK_BINARY <= "11010000"; when 209 => TXTSNFTSCOMCLK_BINARY <= "11010001"; when 210 => TXTSNFTSCOMCLK_BINARY <= "11010010"; when 211 => TXTSNFTSCOMCLK_BINARY <= "11010011"; when 212 => TXTSNFTSCOMCLK_BINARY <= "11010100"; when 213 => TXTSNFTSCOMCLK_BINARY <= "11010101"; when 214 => TXTSNFTSCOMCLK_BINARY <= "11010110"; when 215 => TXTSNFTSCOMCLK_BINARY <= "11010111"; when 216 => TXTSNFTSCOMCLK_BINARY <= "11011000"; when 217 => TXTSNFTSCOMCLK_BINARY <= "11011001"; when 218 => TXTSNFTSCOMCLK_BINARY <= "11011010"; when 219 => TXTSNFTSCOMCLK_BINARY <= "11011011"; when 220 => TXTSNFTSCOMCLK_BINARY <= "11011100"; when 221 => TXTSNFTSCOMCLK_BINARY <= "11011101"; when 222 => TXTSNFTSCOMCLK_BINARY <= "11011110"; when 223 => TXTSNFTSCOMCLK_BINARY <= "11011111"; when 224 => TXTSNFTSCOMCLK_BINARY <= "11100000"; when 225 => TXTSNFTSCOMCLK_BINARY <= "11100001"; when 226 => TXTSNFTSCOMCLK_BINARY <= "11100010"; when 227 => TXTSNFTSCOMCLK_BINARY <= "11100011"; when 228 => TXTSNFTSCOMCLK_BINARY <= "11100100"; when 229 => TXTSNFTSCOMCLK_BINARY <= "11100101"; when 230 => TXTSNFTSCOMCLK_BINARY <= "11100110"; when 231 => TXTSNFTSCOMCLK_BINARY <= "11100111"; when 232 => TXTSNFTSCOMCLK_BINARY <= "11101000"; when 233 => TXTSNFTSCOMCLK_BINARY <= "11101001"; when 234 => TXTSNFTSCOMCLK_BINARY <= "11101010"; when 235 => TXTSNFTSCOMCLK_BINARY <= "11101011"; when 236 => TXTSNFTSCOMCLK_BINARY <= "11101100"; when 237 => TXTSNFTSCOMCLK_BINARY <= "11101101"; when 238 => TXTSNFTSCOMCLK_BINARY <= "11101110"; when 239 => TXTSNFTSCOMCLK_BINARY <= "11101111"; when 240 => TXTSNFTSCOMCLK_BINARY <= "11110000"; when 241 => TXTSNFTSCOMCLK_BINARY <= "11110001"; when 242 => TXTSNFTSCOMCLK_BINARY <= "11110010"; when 243 => TXTSNFTSCOMCLK_BINARY <= "11110011"; when 244 => TXTSNFTSCOMCLK_BINARY <= "11110100"; when 245 => TXTSNFTSCOMCLK_BINARY <= "11110101"; when 246 => TXTSNFTSCOMCLK_BINARY <= "11110110"; when 247 => TXTSNFTSCOMCLK_BINARY <= "11110111"; when 248 => TXTSNFTSCOMCLK_BINARY <= "11111000"; when 249 => TXTSNFTSCOMCLK_BINARY <= "11111001"; when 250 => TXTSNFTSCOMCLK_BINARY <= "11111010"; when 251 => TXTSNFTSCOMCLK_BINARY <= "11111011"; when 252 => TXTSNFTSCOMCLK_BINARY <= "11111100"; when 253 => TXTSNFTSCOMCLK_BINARY <= "11111101"; when 254 => TXTSNFTSCOMCLK_BINARY <= "11111110"; when 255 => TXTSNFTSCOMCLK_BINARY <= "11111111"; when others => assert FALSE report "Error : TXTSNFTSCOMCLK is not in range 0...255." severity error; end case; case RETRYRAMREADLATENCY is when 0 => RETRYRAMREADLATENCY_BINARY <= "000"; when 1 => RETRYRAMREADLATENCY_BINARY <= "001"; when 2 => RETRYRAMREADLATENCY_BINARY <= "010"; when 3 => RETRYRAMREADLATENCY_BINARY <= "011"; when 4 => RETRYRAMREADLATENCY_BINARY <= "100"; when 5 => RETRYRAMREADLATENCY_BINARY <= "101"; when 6 => RETRYRAMREADLATENCY_BINARY <= "110"; when 7 => RETRYRAMREADLATENCY_BINARY <= "111"; when others => assert FALSE report "Error : RETRYRAMREADLATENCY is not in range 0...7." severity error; end case; case RETRYRAMWRITELATENCY is when 0 => RETRYRAMWRITELATENCY_BINARY <= "000"; when 1 => RETRYRAMWRITELATENCY_BINARY <= "001"; when 2 => RETRYRAMWRITELATENCY_BINARY <= "010"; when 3 => RETRYRAMWRITELATENCY_BINARY <= "011"; when 4 => RETRYRAMWRITELATENCY_BINARY <= "100"; when 5 => RETRYRAMWRITELATENCY_BINARY <= "101"; when 6 => RETRYRAMWRITELATENCY_BINARY <= "110"; when 7 => RETRYRAMWRITELATENCY_BINARY <= "111"; when others => assert FALSE report "Error : RETRYRAMWRITELATENCY is not in range 0...7." severity error; end case; case RETRYRAMWIDTH is when 0 => RETRYRAMWIDTH_BINARY <= '0'; when 1 => RETRYRAMWIDTH_BINARY <= '1'; when others => assert FALSE report "Error : RETRYRAMWIDTH is not in range 0...1." severity error; end case; case RETRYWRITEPIPE is when FALSE => RETRYWRITEPIPE_BINARY <= '0'; when TRUE => RETRYWRITEPIPE_BINARY <= '1'; when others => assert FALSE report "Error : RETRYWRITEPIPE is neither TRUE nor FALSE." severity error; end case; case RETRYREADADDRPIPE is when FALSE => RETRYREADADDRPIPE_BINARY <= '0'; when TRUE => RETRYREADADDRPIPE_BINARY <= '1'; when others => assert FALSE report "Error : RETRYREADADDRPIPE is neither TRUE nor FALSE." severity error; end case; case RETRYREADDATAPIPE is when FALSE => RETRYREADDATAPIPE_BINARY <= '0'; when TRUE => RETRYREADDATAPIPE_BINARY <= '1'; when others => assert FALSE report "Error : RETRYREADDATAPIPE is neither TRUE nor FALSE." severity error; end case; case XLINKSUPPORTED is when FALSE => XLINKSUPPORTED_BINARY <= '0'; when TRUE => XLINKSUPPORTED_BINARY <= '1'; when others => assert FALSE report "Error : XLINKSUPPORTED is neither TRUE nor FALSE." severity error; end case; case INFINITECOMPLETIONS is when FALSE => INFINITECOMPLETIONS_BINARY <= '0'; when TRUE => INFINITECOMPLETIONS_BINARY <= '1'; when others => assert FALSE report "Error : INFINITECOMPLETIONS is neither TRUE nor FALSE." severity error; end case; case TLRAMREADLATENCY is when 0 => TLRAMREADLATENCY_BINARY <= "000"; when 1 => TLRAMREADLATENCY_BINARY <= "001"; when 2 => TLRAMREADLATENCY_BINARY <= "010"; when 3 => TLRAMREADLATENCY_BINARY <= "011"; when 4 => TLRAMREADLATENCY_BINARY <= "100"; when 5 => TLRAMREADLATENCY_BINARY <= "101"; when 6 => TLRAMREADLATENCY_BINARY <= "110"; when 7 => TLRAMREADLATENCY_BINARY <= "111"; when others => assert FALSE report "Error : TLRAMREADLATENCY is not in range 0...7." severity error; end case; case TLRAMWRITELATENCY is when 0 => TLRAMWRITELATENCY_BINARY <= "000"; when 1 => TLRAMWRITELATENCY_BINARY <= "001"; when 2 => TLRAMWRITELATENCY_BINARY <= "010"; when 3 => TLRAMWRITELATENCY_BINARY <= "011"; when 4 => TLRAMWRITELATENCY_BINARY <= "100"; when 5 => TLRAMWRITELATENCY_BINARY <= "101"; when 6 => TLRAMWRITELATENCY_BINARY <= "110"; when 7 => TLRAMWRITELATENCY_BINARY <= "111"; when others => assert FALSE report "Error : TLRAMWRITELATENCY is not in range 0...7." severity error; end case; case TLRAMWIDTH is when 0 => TLRAMWIDTH_BINARY <= '0'; when 1 => TLRAMWIDTH_BINARY <= '1'; when others => assert FALSE report "Error : TLRAMWIDTH is not in range 0...1." severity error; end case; case RAMSHARETXRX is when FALSE => RAMSHARETXRX_BINARY <= '0'; when TRUE => RAMSHARETXRX_BINARY <= '1'; when others => assert FALSE report "Error : RAMSHARETXRX is neither TRUE nor FALSE." severity error; end case; case L0SEXITLATENCY is when 0 => L0SEXITLATENCY_BINARY <= "000"; when 1 => L0SEXITLATENCY_BINARY <= "001"; when 2 => L0SEXITLATENCY_BINARY <= "010"; when 3 => L0SEXITLATENCY_BINARY <= "011"; when 4 => L0SEXITLATENCY_BINARY <= "100"; when 5 => L0SEXITLATENCY_BINARY <= "101"; when 6 => L0SEXITLATENCY_BINARY <= "110"; when 7 => L0SEXITLATENCY_BINARY <= "111"; when others => assert FALSE report "Error : L0SEXITLATENCY is not in range 0...7." severity error; end case; case L0SEXITLATENCYCOMCLK is when 0 => L0SEXITLATENCYCOMCLK_BINARY <= "000"; when 1 => L0SEXITLATENCYCOMCLK_BINARY <= "001"; when 2 => L0SEXITLATENCYCOMCLK_BINARY <= "010"; when 3 => L0SEXITLATENCYCOMCLK_BINARY <= "011"; when 4 => L0SEXITLATENCYCOMCLK_BINARY <= "100"; when 5 => L0SEXITLATENCYCOMCLK_BINARY <= "101"; when 6 => L0SEXITLATENCYCOMCLK_BINARY <= "110"; when 7 => L0SEXITLATENCYCOMCLK_BINARY <= "111"; when others => assert FALSE report "Error : L0SEXITLATENCYCOMCLK is not in range 0...7." severity error; end case; case L1EXITLATENCY is when 0 => L1EXITLATENCY_BINARY <= "000"; when 1 => L1EXITLATENCY_BINARY <= "001"; when 2 => L1EXITLATENCY_BINARY <= "010"; when 3 => L1EXITLATENCY_BINARY <= "011"; when 4 => L1EXITLATENCY_BINARY <= "100"; when 5 => L1EXITLATENCY_BINARY <= "101"; when 6 => L1EXITLATENCY_BINARY <= "110"; when 7 => L1EXITLATENCY_BINARY <= "111"; when others => assert FALSE report "Error : L1EXITLATENCY is not in range 0...7." severity error; end case; case L1EXITLATENCYCOMCLK is when 0 => L1EXITLATENCYCOMCLK_BINARY <= "000"; when 1 => L1EXITLATENCYCOMCLK_BINARY <= "001"; when 2 => L1EXITLATENCYCOMCLK_BINARY <= "010"; when 3 => L1EXITLATENCYCOMCLK_BINARY <= "011"; when 4 => L1EXITLATENCYCOMCLK_BINARY <= "100"; when 5 => L1EXITLATENCYCOMCLK_BINARY <= "101"; when 6 => L1EXITLATENCYCOMCLK_BINARY <= "110"; when 7 => L1EXITLATENCYCOMCLK_BINARY <= "111"; when others => assert FALSE report "Error : L1EXITLATENCYCOMCLK is not in range 0...7." severity error; end case; case DUALCORESLAVE is when FALSE => DUALCORESLAVE_BINARY <= '0'; when TRUE => DUALCORESLAVE_BINARY <= '1'; when others => assert FALSE report "Error : DUALCORESLAVE is neither TRUE nor FALSE." severity error; end case; case DUALCOREENABLE is when FALSE => DUALCOREENABLE_BINARY <= '0'; when TRUE => DUALCOREENABLE_BINARY <= '1'; when others => assert FALSE report "Error : DUALCOREENABLE is neither TRUE nor FALSE." severity error; end case; case DUALROLECFGCNTRLROOTEPN is when 0 => DUALROLECFGCNTRLROOTEPN_BINARY <= '0'; when 1 => DUALROLECFGCNTRLROOTEPN_BINARY <= '1'; when others => assert FALSE report "Error : DUALROLECFGCNTRLROOTEPN is not in range 0...1." severity error; end case; case RXREADADDRPIPE is when FALSE => RXREADADDRPIPE_BINARY <= '0'; when TRUE => RXREADADDRPIPE_BINARY <= '1'; when others => assert FALSE report "Error : RXREADADDRPIPE is neither TRUE nor FALSE." severity error; end case; case RXREADDATAPIPE is when FALSE => RXREADDATAPIPE_BINARY <= '0'; when TRUE => RXREADDATAPIPE_BINARY <= '1'; when others => assert FALSE report "Error : RXREADDATAPIPE is neither TRUE nor FALSE." severity error; end case; case TXWRITEPIPE is when FALSE => TXWRITEPIPE_BINARY <= '0'; when TRUE => TXWRITEPIPE_BINARY <= '1'; when others => assert FALSE report "Error : TXWRITEPIPE is neither TRUE nor FALSE." severity error; end case; case TXREADADDRPIPE is when FALSE => TXREADADDRPIPE_BINARY <= '0'; when TRUE => TXREADADDRPIPE_BINARY <= '1'; when others => assert FALSE report "Error : TXREADADDRPIPE is neither TRUE nor FALSE." severity error; end case; case TXREADDATAPIPE is when FALSE => TXREADDATAPIPE_BINARY <= '0'; when TRUE => TXREADDATAPIPE_BINARY <= '1'; when others => assert FALSE report "Error : TXREADDATAPIPE is neither TRUE nor FALSE." severity error; end case; case RXWRITEPIPE is when FALSE => RXWRITEPIPE_BINARY <= '0'; when TRUE => RXWRITEPIPE_BINARY <= '1'; when others => assert FALSE report "Error : RXWRITEPIPE is neither TRUE nor FALSE." severity error; end case; case LLKBYPASS is when FALSE => LLKBYPASS_BINARY <= '0'; when TRUE => LLKBYPASS_BINARY <= '1'; when others => assert FALSE report "Error : LLKBYPASS is neither TRUE nor FALSE." severity error; end case; case PCIEREVISION is when 0 => PCIEREVISION_BINARY <= '0'; when 1 => PCIEREVISION_BINARY <= '1'; when others => assert FALSE report "Error : PCIEREVISION is not in range 0...1." severity error; end case; case SELECTDLLIF is when FALSE => SELECTDLLIF_BINARY <= '0'; when TRUE => SELECTDLLIF_BINARY <= '1'; when others => assert FALSE report "Error : SELECTDLLIF is neither TRUE nor FALSE." severity error; end case; case SELECTASMODE is when FALSE => SELECTASMODE_BINARY <= '0'; when TRUE => SELECTASMODE_BINARY <= '1'; when others => assert FALSE report "Error : SELECTASMODE is neither TRUE nor FALSE." severity error; end case; case ISSWITCH is when FALSE => ISSWITCH_BINARY <= '0'; when TRUE => ISSWITCH_BINARY <= '1'; when others => assert FALSE report "Error : ISSWITCH is neither TRUE nor FALSE." severity error; end case; case UPSTREAMFACING is when FALSE => UPSTREAMFACING_BINARY <= '0'; when TRUE => UPSTREAMFACING_BINARY <= '1'; when others => assert FALSE report "Error : UPSTREAMFACING is neither TRUE nor FALSE." severity error; end case; case SLOTIMPLEMENTED is when FALSE => SLOTIMPLEMENTED_BINARY <= '0'; when TRUE => SLOTIMPLEMENTED_BINARY <= '1'; when others => assert FALSE report "Error : SLOTIMPLEMENTED is neither TRUE nor FALSE." severity error; end case; case BAR0EXIST is when FALSE => BAR0EXIST_BINARY <= '0'; when TRUE => BAR0EXIST_BINARY <= '1'; when others => assert FALSE report "Error : BAR0EXIST is neither TRUE nor FALSE." severity error; end case; case BAR1EXIST is when FALSE => BAR1EXIST_BINARY <= '0'; when TRUE => BAR1EXIST_BINARY <= '1'; when others => assert FALSE report "Error : BAR1EXIST is neither TRUE nor FALSE." severity error; end case; case BAR2EXIST is when FALSE => BAR2EXIST_BINARY <= '0'; when TRUE => BAR2EXIST_BINARY <= '1'; when others => assert FALSE report "Error : BAR2EXIST is neither TRUE nor FALSE." severity error; end case; case BAR3EXIST is when FALSE => BAR3EXIST_BINARY <= '0'; when TRUE => BAR3EXIST_BINARY <= '1'; when others => assert FALSE report "Error : BAR3EXIST is neither TRUE nor FALSE." severity error; end case; case BAR4EXIST is when FALSE => BAR4EXIST_BINARY <= '0'; when TRUE => BAR4EXIST_BINARY <= '1'; when others => assert FALSE report "Error : BAR4EXIST is neither TRUE nor FALSE." severity error; end case; case BAR5EXIST is when FALSE => BAR5EXIST_BINARY <= '0'; when TRUE => BAR5EXIST_BINARY <= '1'; when others => assert FALSE report "Error : BAR5EXIST is neither TRUE nor FALSE." severity error; end case; case BAR0ADDRWIDTH is when 0 => BAR0ADDRWIDTH_BINARY <= '0'; when 1 => BAR0ADDRWIDTH_BINARY <= '1'; when others => assert FALSE report "Error : BAR0ADDRWIDTH is not in range 0...1." severity error; end case; case BAR1ADDRWIDTH is when 0 => BAR1ADDRWIDTH_BINARY <= '0'; when 1 => BAR1ADDRWIDTH_BINARY <= '1'; when others => assert FALSE report "Error : BAR1ADDRWIDTH is not in range 0...1." severity error; end case; case BAR2ADDRWIDTH is when 0 => BAR2ADDRWIDTH_BINARY <= '0'; when 1 => BAR2ADDRWIDTH_BINARY <= '1'; when others => assert FALSE report "Error : BAR2ADDRWIDTH is not in range 0...1." severity error; end case; case BAR3ADDRWIDTH is when 0 => BAR3ADDRWIDTH_BINARY <= '0'; when 1 => BAR3ADDRWIDTH_BINARY <= '1'; when others => assert FALSE report "Error : BAR3ADDRWIDTH is not in range 0...1." severity error; end case; case BAR4ADDRWIDTH is when 0 => BAR4ADDRWIDTH_BINARY <= '0'; when 1 => BAR4ADDRWIDTH_BINARY <= '1'; when others => assert FALSE report "Error : BAR4ADDRWIDTH is not in range 0...1." severity error; end case; case BAR0PREFETCHABLE is when FALSE => BAR0PREFETCHABLE_BINARY <= '0'; when TRUE => BAR0PREFETCHABLE_BINARY <= '1'; when others => assert FALSE report "Error : BAR0PREFETCHABLE is neither TRUE nor FALSE." severity error; end case; case BAR1PREFETCHABLE is when FALSE => BAR1PREFETCHABLE_BINARY <= '0'; when TRUE => BAR1PREFETCHABLE_BINARY <= '1'; when others => assert FALSE report "Error : BAR1PREFETCHABLE is neither TRUE nor FALSE." severity error; end case; case BAR2PREFETCHABLE is when FALSE => BAR2PREFETCHABLE_BINARY <= '0'; when TRUE => BAR2PREFETCHABLE_BINARY <= '1'; when others => assert FALSE report "Error : BAR2PREFETCHABLE is neither TRUE nor FALSE." severity error; end case; case BAR3PREFETCHABLE is when FALSE => BAR3PREFETCHABLE_BINARY <= '0'; when TRUE => BAR3PREFETCHABLE_BINARY <= '1'; when others => assert FALSE report "Error : BAR3PREFETCHABLE is neither TRUE nor FALSE." severity error; end case; case BAR4PREFETCHABLE is when FALSE => BAR4PREFETCHABLE_BINARY <= '0'; when TRUE => BAR4PREFETCHABLE_BINARY <= '1'; when others => assert FALSE report "Error : BAR4PREFETCHABLE is neither TRUE nor FALSE." severity error; end case; case BAR5PREFETCHABLE is when FALSE => BAR5PREFETCHABLE_BINARY <= '0'; when TRUE => BAR5PREFETCHABLE_BINARY <= '1'; when others => assert FALSE report "Error : BAR5PREFETCHABLE is neither TRUE nor FALSE." severity error; end case; case BAR0IOMEMN is when 0 => BAR0IOMEMN_BINARY <= '0'; when 1 => BAR0IOMEMN_BINARY <= '1'; when others => assert FALSE report "Error : BAR0IOMEMN is not in range 0...1." severity error; end case; case BAR1IOMEMN is when 0 => BAR1IOMEMN_BINARY <= '0'; when 1 => BAR1IOMEMN_BINARY <= '1'; when others => assert FALSE report "Error : BAR1IOMEMN is not in range 0...1." severity error; end case; case BAR2IOMEMN is when 0 => BAR2IOMEMN_BINARY <= '0'; when 1 => BAR2IOMEMN_BINARY <= '1'; when others => assert FALSE report "Error : BAR2IOMEMN is not in range 0...1." severity error; end case; case BAR3IOMEMN is when 0 => BAR3IOMEMN_BINARY <= '0'; when 1 => BAR3IOMEMN_BINARY <= '1'; when others => assert FALSE report "Error : BAR3IOMEMN is not in range 0...1." severity error; end case; case BAR4IOMEMN is when 0 => BAR4IOMEMN_BINARY <= '0'; when 1 => BAR4IOMEMN_BINARY <= '1'; when others => assert FALSE report "Error : BAR4IOMEMN is not in range 0...1." severity error; end case; case BAR5IOMEMN is when 0 => BAR5IOMEMN_BINARY <= '0'; when 1 => BAR5IOMEMN_BINARY <= '1'; when others => assert FALSE report "Error : BAR5IOMEMN is not in range 0...1." severity error; end case; case XPMAXPAYLOAD is when 0 => XPMAXPAYLOAD_BINARY <= "000"; when 1 => XPMAXPAYLOAD_BINARY <= "001"; when 2 => XPMAXPAYLOAD_BINARY <= "010"; when 3 => XPMAXPAYLOAD_BINARY <= "011"; when 4 => XPMAXPAYLOAD_BINARY <= "100"; when 5 => XPMAXPAYLOAD_BINARY <= "101"; when 6 => XPMAXPAYLOAD_BINARY <= "110"; when 7 => XPMAXPAYLOAD_BINARY <= "111"; when others => assert FALSE report "Error : XPMAXPAYLOAD is not in range 0...7." severity error; end case; case XPRCBCONTROL is when 0 => XPRCBCONTROL_BINARY <= '0'; when 1 => XPRCBCONTROL_BINARY <= '1'; when others => assert FALSE report "Error : XPRCBCONTROL is not in range 0...1." severity error; end case; case LOWPRIORITYVCCOUNT is when 0 => LOWPRIORITYVCCOUNT_BINARY <= "000"; when 1 => LOWPRIORITYVCCOUNT_BINARY <= "001"; when 2 => LOWPRIORITYVCCOUNT_BINARY <= "010"; when 3 => LOWPRIORITYVCCOUNT_BINARY <= "011"; when 4 => LOWPRIORITYVCCOUNT_BINARY <= "100"; when 5 => LOWPRIORITYVCCOUNT_BINARY <= "101"; when 6 => LOWPRIORITYVCCOUNT_BINARY <= "110"; when 7 => LOWPRIORITYVCCOUNT_BINARY <= "111"; when others => assert FALSE report "Error : LOWPRIORITYVCCOUNT is not in range 0...7." severity error; end case; case PMCAPABILITYDSI is when FALSE => PMCAPABILITYDSI_BINARY <= '0'; when TRUE => PMCAPABILITYDSI_BINARY <= '1'; when others => assert FALSE report "Error : PMCAPABILITYDSI is neither TRUE nor FALSE." severity error; end case; case PMCAPABILITYD1SUPPORT is when FALSE => PMCAPABILITYD1SUPPORT_BINARY <= '0'; when TRUE => PMCAPABILITYD1SUPPORT_BINARY <= '1'; when others => assert FALSE report "Error : PMCAPABILITYD1SUPPORT is neither TRUE nor FALSE." severity error; end case; case PMCAPABILITYD2SUPPORT is when FALSE => PMCAPABILITYD2SUPPORT_BINARY <= '0'; when TRUE => PMCAPABILITYD2SUPPORT_BINARY <= '1'; when others => assert FALSE report "Error : PMCAPABILITYD2SUPPORT is neither TRUE nor FALSE." severity error; end case; case PMDATASCALE0 is when 0 => PMDATASCALE0_BINARY <= "00"; when 1 => PMDATASCALE0_BINARY <= "01"; when 2 => PMDATASCALE0_BINARY <= "10"; when 3 => PMDATASCALE0_BINARY <= "11"; when others => assert FALSE report "Error : PMDATASCALE0 is not in range 0...3." severity error; end case; case PMDATASCALE1 is when 0 => PMDATASCALE1_BINARY <= "00"; when 1 => PMDATASCALE1_BINARY <= "01"; when 2 => PMDATASCALE1_BINARY <= "10"; when 3 => PMDATASCALE1_BINARY <= "11"; when others => assert FALSE report "Error : PMDATASCALE1 is not in range 0...3." severity error; end case; case PMDATASCALE2 is when 0 => PMDATASCALE2_BINARY <= "00"; when 1 => PMDATASCALE2_BINARY <= "01"; when 2 => PMDATASCALE2_BINARY <= "10"; when 3 => PMDATASCALE2_BINARY <= "11"; when others => assert FALSE report "Error : PMDATASCALE2 is not in range 0...3." severity error; end case; case PMDATASCALE3 is when 0 => PMDATASCALE3_BINARY <= "00"; when 1 => PMDATASCALE3_BINARY <= "01"; when 2 => PMDATASCALE3_BINARY <= "10"; when 3 => PMDATASCALE3_BINARY <= "11"; when others => assert FALSE report "Error : PMDATASCALE3 is not in range 0...3." severity error; end case; case PMDATASCALE4 is when 0 => PMDATASCALE4_BINARY <= "00"; when 1 => PMDATASCALE4_BINARY <= "01"; when 2 => PMDATASCALE4_BINARY <= "10"; when 3 => PMDATASCALE4_BINARY <= "11"; when others => assert FALSE report "Error : PMDATASCALE4 is not in range 0...3." severity error; end case; case PMDATASCALE5 is when 0 => PMDATASCALE5_BINARY <= "00"; when 1 => PMDATASCALE5_BINARY <= "01"; when 2 => PMDATASCALE5_BINARY <= "10"; when 3 => PMDATASCALE5_BINARY <= "11"; when others => assert FALSE report "Error : PMDATASCALE5 is not in range 0...3." severity error; end case; case PMDATASCALE6 is when 0 => PMDATASCALE6_BINARY <= "00"; when 1 => PMDATASCALE6_BINARY <= "01"; when 2 => PMDATASCALE6_BINARY <= "10"; when 3 => PMDATASCALE6_BINARY <= "11"; when others => assert FALSE report "Error : PMDATASCALE6 is not in range 0...3." severity error; end case; case PMDATASCALE7 is when 0 => PMDATASCALE7_BINARY <= "00"; when 1 => PMDATASCALE7_BINARY <= "01"; when 2 => PMDATASCALE7_BINARY <= "10"; when 3 => PMDATASCALE7_BINARY <= "11"; when others => assert FALSE report "Error : PMDATASCALE7 is not in range 0...3." severity error; end case; case PMDATASCALE8 is when 0 => PMDATASCALE8_BINARY <= "00"; when 1 => PMDATASCALE8_BINARY <= "01"; when 2 => PMDATASCALE8_BINARY <= "10"; when 3 => PMDATASCALE8_BINARY <= "11"; when others => assert FALSE report "Error : PMDATASCALE8 is not in range 0...3." severity error; end case; case PCIECAPABILITYSLOTIMPL is when FALSE => PCIECAPABILITYSLOTIMPL_BINARY <= '0'; when TRUE => PCIECAPABILITYSLOTIMPL_BINARY <= '1'; when others => assert FALSE report "Error : PCIECAPABILITYSLOTIMPL is neither TRUE nor FALSE." severity error; end case; case LINKSTATUSSLOTCLOCKCONFIG is when FALSE => LINKSTATUSSLOTCLOCKCONFIG_BINARY <= '0'; when TRUE => LINKSTATUSSLOTCLOCKCONFIG_BINARY <= '1'; when others => assert FALSE report "Error : LINKSTATUSSLOTCLOCKCONFIG is neither TRUE nor FALSE." severity error; end case; case SLOTCAPABILITYATTBUTTONPRESENT is when FALSE => SLOTCAPABILITYATTBUTTONPRESENT_BINARY <= '0'; when TRUE => SLOTCAPABILITYATTBUTTONPRESENT_BINARY <= '1'; when others => assert FALSE report "Error : SLOTCAPABILITYATTBUTTONPRESENT is neither TRUE nor FALSE." severity error; end case; case SLOTCAPABILITYPOWERCONTROLLERPRESENT is when FALSE => SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY <= '0'; when TRUE => SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY <= '1'; when others => assert FALSE report "Error : SLOTCAPABILITYPOWERCONTROLLERPRESENT is neither TRUE nor FALSE." severity error; end case; case SLOTCAPABILITYMSLSENSORPRESENT is when FALSE => SLOTCAPABILITYMSLSENSORPRESENT_BINARY <= '0'; when TRUE => SLOTCAPABILITYMSLSENSORPRESENT_BINARY <= '1'; when others => assert FALSE report "Error : SLOTCAPABILITYMSLSENSORPRESENT is neither TRUE nor FALSE." severity error; end case; case SLOTCAPABILITYATTINDICATORPRESENT is when FALSE => SLOTCAPABILITYATTINDICATORPRESENT_BINARY <= '0'; when TRUE => SLOTCAPABILITYATTINDICATORPRESENT_BINARY <= '1'; when others => assert FALSE report "Error : SLOTCAPABILITYATTINDICATORPRESENT is neither TRUE nor FALSE." severity error; end case; case SLOTCAPABILITYPOWERINDICATORPRESENT is when FALSE => SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY <= '0'; when TRUE => SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY <= '1'; when others => assert FALSE report "Error : SLOTCAPABILITYPOWERINDICATORPRESENT is neither TRUE nor FALSE." severity error; end case; case SLOTCAPABILITYHOTPLUGSURPRISE is when FALSE => SLOTCAPABILITYHOTPLUGSURPRISE_BINARY <= '0'; when TRUE => SLOTCAPABILITYHOTPLUGSURPRISE_BINARY <= '1'; when others => assert FALSE report "Error : SLOTCAPABILITYHOTPLUGSURPRISE is neither TRUE nor FALSE." severity error; end case; case SLOTCAPABILITYHOTPLUGCAPABLE is when FALSE => SLOTCAPABILITYHOTPLUGCAPABLE_BINARY <= '0'; when TRUE => SLOTCAPABILITYHOTPLUGCAPABLE_BINARY <= '1'; when others => assert FALSE report "Error : SLOTCAPABILITYHOTPLUGCAPABLE is neither TRUE nor FALSE." severity error; end case; case AERCAPABILITYECRCGENCAPABLE is when FALSE => AERCAPABILITYECRCGENCAPABLE_BINARY <= '0'; when TRUE => AERCAPABILITYECRCGENCAPABLE_BINARY <= '1'; when others => assert FALSE report "Error : AERCAPABILITYECRCGENCAPABLE is neither TRUE nor FALSE." severity error; end case; case AERCAPABILITYECRCCHECKCAPABLE is when FALSE => AERCAPABILITYECRCCHECKCAPABLE_BINARY <= '0'; when TRUE => AERCAPABILITYECRCCHECKCAPABLE_BINARY <= '1'; when others => assert FALSE report "Error : AERCAPABILITYECRCCHECKCAPABLE is neither TRUE nor FALSE." severity error; end case; case PBCAPABILITYSYSTEMALLOCATED is when FALSE => PBCAPABILITYSYSTEMALLOCATED_BINARY <= '0'; when TRUE => PBCAPABILITYSYSTEMALLOCATED_BINARY <= '1'; when others => assert FALSE report "Error : PBCAPABILITYSYSTEMALLOCATED is neither TRUE nor FALSE." severity error; end case; case RESETMODE is when FALSE => RESETMODE_BINARY <= '0'; when TRUE => RESETMODE_BINARY <= '1'; when others => assert FALSE report "Error : RESETMODE is neither TRUE nor FALSE." severity error; end case; case CLKDIVIDED is when FALSE => CLKDIVIDED_BINARY <= '0'; when TRUE => CLKDIVIDED_BINARY <= '1'; when others => assert FALSE report "Error : CLKDIVIDED is neither TRUE nor FALSE." severity error; end case; wait; end process INIPROC; TIMING : process variable PIPETXDATAL00_GlitchData : VitalGlitchDataType; variable PIPETXDATAL01_GlitchData : VitalGlitchDataType; variable PIPETXDATAL02_GlitchData : VitalGlitchDataType; variable PIPETXDATAL03_GlitchData : VitalGlitchDataType; variable PIPETXDATAL04_GlitchData : VitalGlitchDataType; variable PIPETXDATAL05_GlitchData : VitalGlitchDataType; variable PIPETXDATAL06_GlitchData : VitalGlitchDataType; variable PIPETXDATAL07_GlitchData : VitalGlitchDataType; variable PIPETXDATAKL0_GlitchData : VitalGlitchDataType; variable PIPETXELECIDLEL0_GlitchData : VitalGlitchDataType; variable PIPETXDETECTRXLOOPBACKL0_GlitchData : VitalGlitchDataType; variable PIPETXCOMPLIANCEL0_GlitchData : VitalGlitchDataType; variable PIPERXPOLARITYL0_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL00_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL01_GlitchData : VitalGlitchDataType; variable PIPEDESKEWLANESL0_GlitchData : VitalGlitchDataType; variable PIPERESETL0_GlitchData : VitalGlitchDataType; variable PIPETXDATAL10_GlitchData : VitalGlitchDataType; variable PIPETXDATAL11_GlitchData : VitalGlitchDataType; variable PIPETXDATAL12_GlitchData : VitalGlitchDataType; variable PIPETXDATAL13_GlitchData : VitalGlitchDataType; variable PIPETXDATAL14_GlitchData : VitalGlitchDataType; variable PIPETXDATAL15_GlitchData : VitalGlitchDataType; variable PIPETXDATAL16_GlitchData : VitalGlitchDataType; variable PIPETXDATAL17_GlitchData : VitalGlitchDataType; variable PIPETXDATAKL1_GlitchData : VitalGlitchDataType; variable PIPETXELECIDLEL1_GlitchData : VitalGlitchDataType; variable PIPETXDETECTRXLOOPBACKL1_GlitchData : VitalGlitchDataType; variable PIPETXCOMPLIANCEL1_GlitchData : VitalGlitchDataType; variable PIPERXPOLARITYL1_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL10_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL11_GlitchData : VitalGlitchDataType; variable PIPEDESKEWLANESL1_GlitchData : VitalGlitchDataType; variable PIPERESETL1_GlitchData : VitalGlitchDataType; variable PIPETXDATAL20_GlitchData : VitalGlitchDataType; variable PIPETXDATAL21_GlitchData : VitalGlitchDataType; variable PIPETXDATAL22_GlitchData : VitalGlitchDataType; variable PIPETXDATAL23_GlitchData : VitalGlitchDataType; variable PIPETXDATAL24_GlitchData : VitalGlitchDataType; variable PIPETXDATAL25_GlitchData : VitalGlitchDataType; variable PIPETXDATAL26_GlitchData : VitalGlitchDataType; variable PIPETXDATAL27_GlitchData : VitalGlitchDataType; variable PIPETXDATAKL2_GlitchData : VitalGlitchDataType; variable PIPETXELECIDLEL2_GlitchData : VitalGlitchDataType; variable PIPETXDETECTRXLOOPBACKL2_GlitchData : VitalGlitchDataType; variable PIPETXCOMPLIANCEL2_GlitchData : VitalGlitchDataType; variable PIPERXPOLARITYL2_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL20_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL21_GlitchData : VitalGlitchDataType; variable PIPEDESKEWLANESL2_GlitchData : VitalGlitchDataType; variable PIPERESETL2_GlitchData : VitalGlitchDataType; variable PIPETXDATAL30_GlitchData : VitalGlitchDataType; variable PIPETXDATAL31_GlitchData : VitalGlitchDataType; variable PIPETXDATAL32_GlitchData : VitalGlitchDataType; variable PIPETXDATAL33_GlitchData : VitalGlitchDataType; variable PIPETXDATAL34_GlitchData : VitalGlitchDataType; variable PIPETXDATAL35_GlitchData : VitalGlitchDataType; variable PIPETXDATAL36_GlitchData : VitalGlitchDataType; variable PIPETXDATAL37_GlitchData : VitalGlitchDataType; variable PIPETXDATAKL3_GlitchData : VitalGlitchDataType; variable PIPETXELECIDLEL3_GlitchData : VitalGlitchDataType; variable PIPETXDETECTRXLOOPBACKL3_GlitchData : VitalGlitchDataType; variable PIPETXCOMPLIANCEL3_GlitchData : VitalGlitchDataType; variable PIPERXPOLARITYL3_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL30_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL31_GlitchData : VitalGlitchDataType; variable PIPEDESKEWLANESL3_GlitchData : VitalGlitchDataType; variable PIPERESETL3_GlitchData : VitalGlitchDataType; variable PIPETXDATAL40_GlitchData : VitalGlitchDataType; variable PIPETXDATAL41_GlitchData : VitalGlitchDataType; variable PIPETXDATAL42_GlitchData : VitalGlitchDataType; variable PIPETXDATAL43_GlitchData : VitalGlitchDataType; variable PIPETXDATAL44_GlitchData : VitalGlitchDataType; variable PIPETXDATAL45_GlitchData : VitalGlitchDataType; variable PIPETXDATAL46_GlitchData : VitalGlitchDataType; variable PIPETXDATAL47_GlitchData : VitalGlitchDataType; variable PIPETXDATAKL4_GlitchData : VitalGlitchDataType; variable PIPETXELECIDLEL4_GlitchData : VitalGlitchDataType; variable PIPETXDETECTRXLOOPBACKL4_GlitchData : VitalGlitchDataType; variable PIPETXCOMPLIANCEL4_GlitchData : VitalGlitchDataType; variable PIPERXPOLARITYL4_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL40_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL41_GlitchData : VitalGlitchDataType; variable PIPEDESKEWLANESL4_GlitchData : VitalGlitchDataType; variable PIPERESETL4_GlitchData : VitalGlitchDataType; variable PIPETXDATAL50_GlitchData : VitalGlitchDataType; variable PIPETXDATAL51_GlitchData : VitalGlitchDataType; variable PIPETXDATAL52_GlitchData : VitalGlitchDataType; variable PIPETXDATAL53_GlitchData : VitalGlitchDataType; variable PIPETXDATAL54_GlitchData : VitalGlitchDataType; variable PIPETXDATAL55_GlitchData : VitalGlitchDataType; variable PIPETXDATAL56_GlitchData : VitalGlitchDataType; variable PIPETXDATAL57_GlitchData : VitalGlitchDataType; variable PIPETXDATAKL5_GlitchData : VitalGlitchDataType; variable PIPETXELECIDLEL5_GlitchData : VitalGlitchDataType; variable PIPETXDETECTRXLOOPBACKL5_GlitchData : VitalGlitchDataType; variable PIPETXCOMPLIANCEL5_GlitchData : VitalGlitchDataType; variable PIPERXPOLARITYL5_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL50_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL51_GlitchData : VitalGlitchDataType; variable PIPEDESKEWLANESL5_GlitchData : VitalGlitchDataType; variable PIPERESETL5_GlitchData : VitalGlitchDataType; variable PIPETXDATAL60_GlitchData : VitalGlitchDataType; variable PIPETXDATAL61_GlitchData : VitalGlitchDataType; variable PIPETXDATAL62_GlitchData : VitalGlitchDataType; variable PIPETXDATAL63_GlitchData : VitalGlitchDataType; variable PIPETXDATAL64_GlitchData : VitalGlitchDataType; variable PIPETXDATAL65_GlitchData : VitalGlitchDataType; variable PIPETXDATAL66_GlitchData : VitalGlitchDataType; variable PIPETXDATAL67_GlitchData : VitalGlitchDataType; variable PIPETXDATAKL6_GlitchData : VitalGlitchDataType; variable PIPETXELECIDLEL6_GlitchData : VitalGlitchDataType; variable PIPETXDETECTRXLOOPBACKL6_GlitchData : VitalGlitchDataType; variable PIPETXCOMPLIANCEL6_GlitchData : VitalGlitchDataType; variable PIPERXPOLARITYL6_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL60_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL61_GlitchData : VitalGlitchDataType; variable PIPEDESKEWLANESL6_GlitchData : VitalGlitchDataType; variable PIPERESETL6_GlitchData : VitalGlitchDataType; variable PIPETXDATAL70_GlitchData : VitalGlitchDataType; variable PIPETXDATAL71_GlitchData : VitalGlitchDataType; variable PIPETXDATAL72_GlitchData : VitalGlitchDataType; variable PIPETXDATAL73_GlitchData : VitalGlitchDataType; variable PIPETXDATAL74_GlitchData : VitalGlitchDataType; variable PIPETXDATAL75_GlitchData : VitalGlitchDataType; variable PIPETXDATAL76_GlitchData : VitalGlitchDataType; variable PIPETXDATAL77_GlitchData : VitalGlitchDataType; variable PIPETXDATAKL7_GlitchData : VitalGlitchDataType; variable PIPETXELECIDLEL7_GlitchData : VitalGlitchDataType; variable PIPETXDETECTRXLOOPBACKL7_GlitchData : VitalGlitchDataType; variable PIPETXCOMPLIANCEL7_GlitchData : VitalGlitchDataType; variable PIPERXPOLARITYL7_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL70_GlitchData : VitalGlitchDataType; variable PIPEPOWERDOWNL71_GlitchData : VitalGlitchDataType; variable PIPEDESKEWLANESL7_GlitchData : VitalGlitchDataType; variable PIPERESETL7_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA0_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA1_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA2_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA3_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA4_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA5_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA6_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA7_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA8_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA9_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA10_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA11_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA12_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA13_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA14_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA15_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA16_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA17_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA18_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA19_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA20_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA21_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA22_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA23_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA24_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA25_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA26_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA27_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA28_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA29_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA30_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA31_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA32_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA33_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA34_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA35_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA36_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA37_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA38_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA39_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA40_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA41_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA42_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA43_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA44_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA45_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA46_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA47_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA48_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA49_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA50_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA51_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA52_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA53_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA54_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA55_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA56_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA57_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA58_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA59_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA60_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA61_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA62_GlitchData : VitalGlitchDataType; variable MIMRXBWDATA63_GlitchData : VitalGlitchDataType; variable MIMRXBWADD0_GlitchData : VitalGlitchDataType; variable MIMRXBWADD1_GlitchData : VitalGlitchDataType; variable MIMRXBWADD2_GlitchData : VitalGlitchDataType; variable MIMRXBWADD3_GlitchData : VitalGlitchDataType; variable MIMRXBWADD4_GlitchData : VitalGlitchDataType; variable MIMRXBWADD5_GlitchData : VitalGlitchDataType; variable MIMRXBWADD6_GlitchData : VitalGlitchDataType; variable MIMRXBWADD7_GlitchData : VitalGlitchDataType; variable MIMRXBWADD8_GlitchData : VitalGlitchDataType; variable MIMRXBWADD9_GlitchData : VitalGlitchDataType; variable MIMRXBWADD10_GlitchData : VitalGlitchDataType; variable MIMRXBWADD11_GlitchData : VitalGlitchDataType; variable MIMRXBWADD12_GlitchData : VitalGlitchDataType; variable MIMRXBRADD0_GlitchData : VitalGlitchDataType; variable MIMRXBRADD1_GlitchData : VitalGlitchDataType; variable MIMRXBRADD2_GlitchData : VitalGlitchDataType; variable MIMRXBRADD3_GlitchData : VitalGlitchDataType; variable MIMRXBRADD4_GlitchData : VitalGlitchDataType; variable MIMRXBRADD5_GlitchData : VitalGlitchDataType; variable MIMRXBRADD6_GlitchData : VitalGlitchDataType; variable MIMRXBRADD7_GlitchData : VitalGlitchDataType; variable MIMRXBRADD8_GlitchData : VitalGlitchDataType; variable MIMRXBRADD9_GlitchData : VitalGlitchDataType; variable MIMRXBRADD10_GlitchData : VitalGlitchDataType; variable MIMRXBRADD11_GlitchData : VitalGlitchDataType; variable MIMRXBRADD12_GlitchData : VitalGlitchDataType; variable MIMRXBWEN_GlitchData : VitalGlitchDataType; variable MIMRXBREN_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA0_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA1_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA2_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA3_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA4_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA5_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA6_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA7_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA8_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA9_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA10_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA11_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA12_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA13_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA14_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA15_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA16_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA17_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA18_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA19_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA20_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA21_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA22_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA23_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA24_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA25_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA26_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA27_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA28_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA29_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA30_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA31_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA32_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA33_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA34_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA35_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA36_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA37_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA38_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA39_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA40_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA41_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA42_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA43_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA44_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA45_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA46_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA47_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA48_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA49_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA50_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA51_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA52_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA53_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA54_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA55_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA56_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA57_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA58_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA59_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA60_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA61_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA62_GlitchData : VitalGlitchDataType; variable MIMTXBWDATA63_GlitchData : VitalGlitchDataType; variable MIMTXBWADD0_GlitchData : VitalGlitchDataType; variable MIMTXBWADD1_GlitchData : VitalGlitchDataType; variable MIMTXBWADD2_GlitchData : VitalGlitchDataType; variable MIMTXBWADD3_GlitchData : VitalGlitchDataType; variable MIMTXBWADD4_GlitchData : VitalGlitchDataType; variable MIMTXBWADD5_GlitchData : VitalGlitchDataType; variable MIMTXBWADD6_GlitchData : VitalGlitchDataType; variable MIMTXBWADD7_GlitchData : VitalGlitchDataType; variable MIMTXBWADD8_GlitchData : VitalGlitchDataType; variable MIMTXBWADD9_GlitchData : VitalGlitchDataType; variable MIMTXBWADD10_GlitchData : VitalGlitchDataType; variable MIMTXBWADD11_GlitchData : VitalGlitchDataType; variable MIMTXBWADD12_GlitchData : VitalGlitchDataType; variable MIMTXBRADD0_GlitchData : VitalGlitchDataType; variable MIMTXBRADD1_GlitchData : VitalGlitchDataType; variable MIMTXBRADD2_GlitchData : VitalGlitchDataType; variable MIMTXBRADD3_GlitchData : VitalGlitchDataType; variable MIMTXBRADD4_GlitchData : VitalGlitchDataType; variable MIMTXBRADD5_GlitchData : VitalGlitchDataType; variable MIMTXBRADD6_GlitchData : VitalGlitchDataType; variable MIMTXBRADD7_GlitchData : VitalGlitchDataType; variable MIMTXBRADD8_GlitchData : VitalGlitchDataType; variable MIMTXBRADD9_GlitchData : VitalGlitchDataType; variable MIMTXBRADD10_GlitchData : VitalGlitchDataType; variable MIMTXBRADD11_GlitchData : VitalGlitchDataType; variable MIMTXBRADD12_GlitchData : VitalGlitchDataType; variable MIMTXBWEN_GlitchData : VitalGlitchDataType; variable MIMTXBREN_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA0_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA1_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA2_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA3_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA4_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA5_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA6_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA7_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA8_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA9_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA10_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA11_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA12_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA13_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA14_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA15_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA16_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA17_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA18_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA19_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA20_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA21_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA22_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA23_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA24_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA25_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA26_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA27_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA28_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA29_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA30_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA31_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA32_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA33_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA34_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA35_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA36_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA37_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA38_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA39_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA40_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA41_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA42_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA43_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA44_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA45_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA46_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA47_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA48_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA49_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA50_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA51_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA52_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA53_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA54_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA55_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA56_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA57_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA58_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA59_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA60_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA61_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA62_GlitchData : VitalGlitchDataType; variable MIMDLLBWDATA63_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD0_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD1_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD2_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD3_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD4_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD5_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD6_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD7_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD8_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD9_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD10_GlitchData : VitalGlitchDataType; variable MIMDLLBWADD11_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD0_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD1_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD2_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD3_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD4_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD5_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD6_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD7_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD8_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD9_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD10_GlitchData : VitalGlitchDataType; variable MIMDLLBRADD11_GlitchData : VitalGlitchDataType; variable MIMDLLBWEN_GlitchData : VitalGlitchDataType; variable MIMDLLBREN_GlitchData : VitalGlitchDataType; variable CRMRXHOTRESETN_GlitchData : VitalGlitchDataType; variable CRMDOHOTRESETN_GlitchData : VitalGlitchDataType; variable CRMPWRSOFTRESETN_GlitchData : VitalGlitchDataType; variable LLKTCSTATUS0_GlitchData : VitalGlitchDataType; variable LLKTCSTATUS1_GlitchData : VitalGlitchDataType; variable LLKTCSTATUS2_GlitchData : VitalGlitchDataType; variable LLKTCSTATUS3_GlitchData : VitalGlitchDataType; variable LLKTCSTATUS4_GlitchData : VitalGlitchDataType; variable LLKTCSTATUS5_GlitchData : VitalGlitchDataType; variable LLKTCSTATUS6_GlitchData : VitalGlitchDataType; variable LLKTCSTATUS7_GlitchData : VitalGlitchDataType; variable LLKTXDSTRDYN_GlitchData : VitalGlitchDataType; variable LLKTXCHANSPACE0_GlitchData : VitalGlitchDataType; variable LLKTXCHANSPACE1_GlitchData : VitalGlitchDataType; variable LLKTXCHANSPACE2_GlitchData : VitalGlitchDataType; variable LLKTXCHANSPACE3_GlitchData : VitalGlitchDataType; variable LLKTXCHANSPACE4_GlitchData : VitalGlitchDataType; variable LLKTXCHANSPACE5_GlitchData : VitalGlitchDataType; variable LLKTXCHANSPACE6_GlitchData : VitalGlitchDataType; variable LLKTXCHANSPACE7_GlitchData : VitalGlitchDataType; variable LLKTXCHANSPACE8_GlitchData : VitalGlitchDataType; variable LLKTXCHANSPACE9_GlitchData : VitalGlitchDataType; variable LLKTXCHPOSTEDREADYN0_GlitchData : VitalGlitchDataType; variable LLKTXCHPOSTEDREADYN1_GlitchData : VitalGlitchDataType; variable LLKTXCHPOSTEDREADYN2_GlitchData : VitalGlitchDataType; variable LLKTXCHPOSTEDREADYN3_GlitchData : VitalGlitchDataType; variable LLKTXCHPOSTEDREADYN4_GlitchData : VitalGlitchDataType; variable LLKTXCHPOSTEDREADYN5_GlitchData : VitalGlitchDataType; variable LLKTXCHPOSTEDREADYN6_GlitchData : VitalGlitchDataType; variable LLKTXCHPOSTEDREADYN7_GlitchData : VitalGlitchDataType; variable LLKTXCHNONPOSTEDREADYN0_GlitchData : VitalGlitchDataType; variable LLKTXCHNONPOSTEDREADYN1_GlitchData : VitalGlitchDataType; variable LLKTXCHNONPOSTEDREADYN2_GlitchData : VitalGlitchDataType; variable LLKTXCHNONPOSTEDREADYN3_GlitchData : VitalGlitchDataType; variable LLKTXCHNONPOSTEDREADYN4_GlitchData : VitalGlitchDataType; variable LLKTXCHNONPOSTEDREADYN5_GlitchData : VitalGlitchDataType; variable LLKTXCHNONPOSTEDREADYN6_GlitchData : VitalGlitchDataType; variable LLKTXCHNONPOSTEDREADYN7_GlitchData : VitalGlitchDataType; variable LLKTXCHCOMPLETIONREADYN0_GlitchData : VitalGlitchDataType; variable LLKTXCHCOMPLETIONREADYN1_GlitchData : VitalGlitchDataType; variable LLKTXCHCOMPLETIONREADYN2_GlitchData : VitalGlitchDataType; variable LLKTXCHCOMPLETIONREADYN3_GlitchData : VitalGlitchDataType; variable LLKTXCHCOMPLETIONREADYN4_GlitchData : VitalGlitchDataType; variable LLKTXCHCOMPLETIONREADYN5_GlitchData : VitalGlitchDataType; variable LLKTXCHCOMPLETIONREADYN6_GlitchData : VitalGlitchDataType; variable LLKTXCHCOMPLETIONREADYN7_GlitchData : VitalGlitchDataType; variable LLKTXCONFIGREADYN_GlitchData : VitalGlitchDataType; variable LLKRXDATA0_GlitchData : VitalGlitchDataType; variable LLKRXDATA1_GlitchData : VitalGlitchDataType; variable LLKRXDATA2_GlitchData : VitalGlitchDataType; variable LLKRXDATA3_GlitchData : VitalGlitchDataType; variable LLKRXDATA4_GlitchData : VitalGlitchDataType; variable LLKRXDATA5_GlitchData : VitalGlitchDataType; variable LLKRXDATA6_GlitchData : VitalGlitchDataType; variable LLKRXDATA7_GlitchData : VitalGlitchDataType; variable LLKRXDATA8_GlitchData : VitalGlitchDataType; variable LLKRXDATA9_GlitchData : VitalGlitchDataType; variable LLKRXDATA10_GlitchData : VitalGlitchDataType; variable LLKRXDATA11_GlitchData : VitalGlitchDataType; variable LLKRXDATA12_GlitchData : VitalGlitchDataType; variable LLKRXDATA13_GlitchData : VitalGlitchDataType; variable LLKRXDATA14_GlitchData : VitalGlitchDataType; variable LLKRXDATA15_GlitchData : VitalGlitchDataType; variable LLKRXDATA16_GlitchData : VitalGlitchDataType; variable LLKRXDATA17_GlitchData : VitalGlitchDataType; variable LLKRXDATA18_GlitchData : VitalGlitchDataType; variable LLKRXDATA19_GlitchData : VitalGlitchDataType; variable LLKRXDATA20_GlitchData : VitalGlitchDataType; variable LLKRXDATA21_GlitchData : VitalGlitchDataType; variable LLKRXDATA22_GlitchData : VitalGlitchDataType; variable LLKRXDATA23_GlitchData : VitalGlitchDataType; variable LLKRXDATA24_GlitchData : VitalGlitchDataType; variable LLKRXDATA25_GlitchData : VitalGlitchDataType; variable LLKRXDATA26_GlitchData : VitalGlitchDataType; variable LLKRXDATA27_GlitchData : VitalGlitchDataType; variable LLKRXDATA28_GlitchData : VitalGlitchDataType; variable LLKRXDATA29_GlitchData : VitalGlitchDataType; variable LLKRXDATA30_GlitchData : VitalGlitchDataType; variable LLKRXDATA31_GlitchData : VitalGlitchDataType; variable LLKRXDATA32_GlitchData : VitalGlitchDataType; variable LLKRXDATA33_GlitchData : VitalGlitchDataType; variable LLKRXDATA34_GlitchData : VitalGlitchDataType; variable LLKRXDATA35_GlitchData : VitalGlitchDataType; variable LLKRXDATA36_GlitchData : VitalGlitchDataType; variable LLKRXDATA37_GlitchData : VitalGlitchDataType; variable LLKRXDATA38_GlitchData : VitalGlitchDataType; variable LLKRXDATA39_GlitchData : VitalGlitchDataType; variable LLKRXDATA40_GlitchData : VitalGlitchDataType; variable LLKRXDATA41_GlitchData : VitalGlitchDataType; variable LLKRXDATA42_GlitchData : VitalGlitchDataType; variable LLKRXDATA43_GlitchData : VitalGlitchDataType; variable LLKRXDATA44_GlitchData : VitalGlitchDataType; variable LLKRXDATA45_GlitchData : VitalGlitchDataType; variable LLKRXDATA46_GlitchData : VitalGlitchDataType; variable LLKRXDATA47_GlitchData : VitalGlitchDataType; variable LLKRXDATA48_GlitchData : VitalGlitchDataType; variable LLKRXDATA49_GlitchData : VitalGlitchDataType; variable LLKRXDATA50_GlitchData : VitalGlitchDataType; variable LLKRXDATA51_GlitchData : VitalGlitchDataType; variable LLKRXDATA52_GlitchData : VitalGlitchDataType; variable LLKRXDATA53_GlitchData : VitalGlitchDataType; variable LLKRXDATA54_GlitchData : VitalGlitchDataType; variable LLKRXDATA55_GlitchData : VitalGlitchDataType; variable LLKRXDATA56_GlitchData : VitalGlitchDataType; variable LLKRXDATA57_GlitchData : VitalGlitchDataType; variable LLKRXDATA58_GlitchData : VitalGlitchDataType; variable LLKRXDATA59_GlitchData : VitalGlitchDataType; variable LLKRXDATA60_GlitchData : VitalGlitchDataType; variable LLKRXDATA61_GlitchData : VitalGlitchDataType; variable LLKRXDATA62_GlitchData : VitalGlitchDataType; variable LLKRXDATA63_GlitchData : VitalGlitchDataType; variable LLKRXSRCRDYN_GlitchData : VitalGlitchDataType; variable LLKRXSRCLASTREQN_GlitchData : VitalGlitchDataType; variable LLKRXSRCDSCN_GlitchData : VitalGlitchDataType; variable LLKRXSOFN_GlitchData : VitalGlitchDataType; variable LLKRXEOFN_GlitchData : VitalGlitchDataType; variable LLKRXSOPN_GlitchData : VitalGlitchDataType; variable LLKRXEOPN_GlitchData : VitalGlitchDataType; variable LLKRXVALIDN0_GlitchData : VitalGlitchDataType; variable LLKRXVALIDN1_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE0_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE1_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE2_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE3_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE4_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE5_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE6_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE7_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE8_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE9_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE10_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE11_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE12_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE13_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE14_GlitchData : VitalGlitchDataType; variable LLKRXPREFERREDTYPE15_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDAVAILABLEN0_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDAVAILABLEN1_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDAVAILABLEN2_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDAVAILABLEN3_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDAVAILABLEN4_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDAVAILABLEN5_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDAVAILABLEN6_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDAVAILABLEN7_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDAVAILABLEN0_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDAVAILABLEN1_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDAVAILABLEN2_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDAVAILABLEN3_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDAVAILABLEN4_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDAVAILABLEN5_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDAVAILABLEN6_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDAVAILABLEN7_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONAVAILABLEN0_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONAVAILABLEN1_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONAVAILABLEN2_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONAVAILABLEN3_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONAVAILABLEN4_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONAVAILABLEN5_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONAVAILABLEN6_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONAVAILABLEN7_GlitchData : VitalGlitchDataType; variable LLKRXCHCONFIGAVAILABLEN_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDPARTIALN0_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDPARTIALN1_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDPARTIALN2_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDPARTIALN3_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDPARTIALN4_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDPARTIALN5_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDPARTIALN6_GlitchData : VitalGlitchDataType; variable LLKRXCHPOSTEDPARTIALN7_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDPARTIALN0_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDPARTIALN1_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDPARTIALN2_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDPARTIALN3_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDPARTIALN4_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDPARTIALN5_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDPARTIALN6_GlitchData : VitalGlitchDataType; variable LLKRXCHNONPOSTEDPARTIALN7_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONPARTIALN0_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONPARTIALN1_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONPARTIALN2_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONPARTIALN3_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONPARTIALN4_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONPARTIALN5_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONPARTIALN6_GlitchData : VitalGlitchDataType; variable LLKRXCHCOMPLETIONPARTIALN7_GlitchData : VitalGlitchDataType; variable LLKRXCHCONFIGPARTIALN_GlitchData : VitalGlitchDataType; variable LLKRX4DWHEADERN_GlitchData : VitalGlitchDataType; variable LLKRXECRCBADN_GlitchData : VitalGlitchDataType; variable MGMTRDATA0_GlitchData : VitalGlitchDataType; variable MGMTRDATA1_GlitchData : VitalGlitchDataType; variable MGMTRDATA2_GlitchData : VitalGlitchDataType; variable MGMTRDATA3_GlitchData : VitalGlitchDataType; variable MGMTRDATA4_GlitchData : VitalGlitchDataType; variable MGMTRDATA5_GlitchData : VitalGlitchDataType; variable MGMTRDATA6_GlitchData : VitalGlitchDataType; variable MGMTRDATA7_GlitchData : VitalGlitchDataType; variable MGMTRDATA8_GlitchData : VitalGlitchDataType; variable MGMTRDATA9_GlitchData : VitalGlitchDataType; variable MGMTRDATA10_GlitchData : VitalGlitchDataType; variable MGMTRDATA11_GlitchData : VitalGlitchDataType; variable MGMTRDATA12_GlitchData : VitalGlitchDataType; variable MGMTRDATA13_GlitchData : VitalGlitchDataType; variable MGMTRDATA14_GlitchData : VitalGlitchDataType; variable MGMTRDATA15_GlitchData : VitalGlitchDataType; variable MGMTRDATA16_GlitchData : VitalGlitchDataType; variable MGMTRDATA17_GlitchData : VitalGlitchDataType; variable MGMTRDATA18_GlitchData : VitalGlitchDataType; variable MGMTRDATA19_GlitchData : VitalGlitchDataType; variable MGMTRDATA20_GlitchData : VitalGlitchDataType; variable MGMTRDATA21_GlitchData : VitalGlitchDataType; variable MGMTRDATA22_GlitchData : VitalGlitchDataType; variable MGMTRDATA23_GlitchData : VitalGlitchDataType; variable MGMTRDATA24_GlitchData : VitalGlitchDataType; variable MGMTRDATA25_GlitchData : VitalGlitchDataType; variable MGMTRDATA26_GlitchData : VitalGlitchDataType; variable MGMTRDATA27_GlitchData : VitalGlitchDataType; variable MGMTRDATA28_GlitchData : VitalGlitchDataType; variable MGMTRDATA29_GlitchData : VitalGlitchDataType; variable MGMTRDATA30_GlitchData : VitalGlitchDataType; variable MGMTRDATA31_GlitchData : VitalGlitchDataType; variable MGMTPSO0_GlitchData : VitalGlitchDataType; variable MGMTPSO1_GlitchData : VitalGlitchDataType; variable MGMTPSO2_GlitchData : VitalGlitchDataType; variable MGMTPSO3_GlitchData : VitalGlitchDataType; variable MGMTPSO4_GlitchData : VitalGlitchDataType; variable MGMTPSO5_GlitchData : VitalGlitchDataType; variable MGMTPSO6_GlitchData : VitalGlitchDataType; variable MGMTPSO7_GlitchData : VitalGlitchDataType; variable MGMTPSO8_GlitchData : VitalGlitchDataType; variable MGMTPSO9_GlitchData : VitalGlitchDataType; variable MGMTPSO10_GlitchData : VitalGlitchDataType; variable MGMTPSO11_GlitchData : VitalGlitchDataType; variable MGMTPSO12_GlitchData : VitalGlitchDataType; variable MGMTPSO13_GlitchData : VitalGlitchDataType; variable MGMTPSO14_GlitchData : VitalGlitchDataType; variable MGMTPSO15_GlitchData : VitalGlitchDataType; variable MGMTPSO16_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT0_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT1_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT2_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT3_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT4_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT5_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT6_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT7_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT8_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT9_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT10_GlitchData : VitalGlitchDataType; variable MGMTSTATSCREDIT11_GlitchData : VitalGlitchDataType; variable L0RXDLLTLPECRCOK_GlitchData : VitalGlitchDataType; variable DLLTXPMDLLPOUTSTANDING_GlitchData : VitalGlitchDataType; variable L0FIRSTCFGWRITEOCCURRED_GlitchData : VitalGlitchDataType; variable L0CFGLOOPBACKACK_GlitchData : VitalGlitchDataType; variable L0MACUPSTREAMDOWNSTREAM_GlitchData : VitalGlitchDataType; variable L0RXMACLINKERROR0_GlitchData : VitalGlitchDataType; variable L0RXMACLINKERROR1_GlitchData : VitalGlitchDataType; variable L0MACLINKUP_GlitchData : VitalGlitchDataType; variable L0MACNEGOTIATEDLINKWIDTH0_GlitchData : VitalGlitchDataType; variable L0MACNEGOTIATEDLINKWIDTH1_GlitchData : VitalGlitchDataType; variable L0MACNEGOTIATEDLINKWIDTH2_GlitchData : VitalGlitchDataType; variable L0MACNEGOTIATEDLINKWIDTH3_GlitchData : VitalGlitchDataType; variable L0MACLINKTRAINING_GlitchData : VitalGlitchDataType; variable L0LTSSMSTATE0_GlitchData : VitalGlitchDataType; variable L0LTSSMSTATE1_GlitchData : VitalGlitchDataType; variable L0LTSSMSTATE2_GlitchData : VitalGlitchDataType; variable L0LTSSMSTATE3_GlitchData : VitalGlitchDataType; variable L0DLLVCSTATUS0_GlitchData : VitalGlitchDataType; variable L0DLLVCSTATUS1_GlitchData : VitalGlitchDataType; variable L0DLLVCSTATUS2_GlitchData : VitalGlitchDataType; variable L0DLLVCSTATUS3_GlitchData : VitalGlitchDataType; variable L0DLLVCSTATUS4_GlitchData : VitalGlitchDataType; variable L0DLLVCSTATUS5_GlitchData : VitalGlitchDataType; variable L0DLLVCSTATUS6_GlitchData : VitalGlitchDataType; variable L0DLLVCSTATUS7_GlitchData : VitalGlitchDataType; variable L0DLUPDOWN0_GlitchData : VitalGlitchDataType; variable L0DLUPDOWN1_GlitchData : VitalGlitchDataType; variable L0DLUPDOWN2_GlitchData : VitalGlitchDataType; variable L0DLUPDOWN3_GlitchData : VitalGlitchDataType; variable L0DLUPDOWN4_GlitchData : VitalGlitchDataType; variable L0DLUPDOWN5_GlitchData : VitalGlitchDataType; variable L0DLUPDOWN6_GlitchData : VitalGlitchDataType; variable L0DLUPDOWN7_GlitchData : VitalGlitchDataType; variable L0DLLERRORVECTOR0_GlitchData : VitalGlitchDataType; variable L0DLLERRORVECTOR1_GlitchData : VitalGlitchDataType; variable L0DLLERRORVECTOR2_GlitchData : VitalGlitchDataType; variable L0DLLERRORVECTOR3_GlitchData : VitalGlitchDataType; variable L0DLLERRORVECTOR4_GlitchData : VitalGlitchDataType; variable L0DLLERRORVECTOR5_GlitchData : VitalGlitchDataType; variable L0DLLERRORVECTOR6_GlitchData : VitalGlitchDataType; variable L0DLLASRXSTATE0_GlitchData : VitalGlitchDataType; variable L0DLLASRXSTATE1_GlitchData : VitalGlitchDataType; variable L0DLLASTXSTATE_GlitchData : VitalGlitchDataType; variable L0ASAUTONOMOUSINITCOMPLETED_GlitchData : VitalGlitchDataType; variable L0COMPLETERID0_GlitchData : VitalGlitchDataType; variable L0COMPLETERID1_GlitchData : VitalGlitchDataType; variable L0COMPLETERID2_GlitchData : VitalGlitchDataType; variable L0COMPLETERID3_GlitchData : VitalGlitchDataType; variable L0COMPLETERID4_GlitchData : VitalGlitchDataType; variable L0COMPLETERID5_GlitchData : VitalGlitchDataType; variable L0COMPLETERID6_GlitchData : VitalGlitchDataType; variable L0COMPLETERID7_GlitchData : VitalGlitchDataType; variable L0COMPLETERID8_GlitchData : VitalGlitchDataType; variable L0COMPLETERID9_GlitchData : VitalGlitchDataType; variable L0COMPLETERID10_GlitchData : VitalGlitchDataType; variable L0COMPLETERID11_GlitchData : VitalGlitchDataType; variable L0COMPLETERID12_GlitchData : VitalGlitchDataType; variable L0UNLOCKRECEIVED_GlitchData : VitalGlitchDataType; variable L0CORRERRMSGRCVD_GlitchData : VitalGlitchDataType; variable L0FATALERRMSGRCVD_GlitchData : VitalGlitchDataType; variable L0NONFATALERRMSGRCVD_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID0_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID1_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID2_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID3_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID4_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID5_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID6_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID7_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID8_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID9_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID10_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID11_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID12_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID13_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID14_GlitchData : VitalGlitchDataType; variable L0ERRMSGREQID15_GlitchData : VitalGlitchDataType; variable L0FWDCORRERROUT_GlitchData : VitalGlitchDataType; variable L0FWDFATALERROUT_GlitchData : VitalGlitchDataType; variable L0FWDNONFATALERROUT_GlitchData : VitalGlitchDataType; variable L0RECEIVEDASSERTINTALEGACYINT_GlitchData : VitalGlitchDataType; variable L0RECEIVEDASSERTINTBLEGACYINT_GlitchData : VitalGlitchDataType; variable L0RECEIVEDASSERTINTCLEGACYINT_GlitchData : VitalGlitchDataType; variable L0RECEIVEDASSERTINTDLEGACYINT_GlitchData : VitalGlitchDataType; variable L0RECEIVEDDEASSERTINTALEGACYINT_GlitchData : VitalGlitchDataType; variable L0RECEIVEDDEASSERTINTBLEGACYINT_GlitchData : VitalGlitchDataType; variable L0RECEIVEDDEASSERTINTCLEGACYINT_GlitchData : VitalGlitchDataType; variable L0RECEIVEDDEASSERTINTDLEGACYINT_GlitchData : VitalGlitchDataType; variable L0MSIENABLE0_GlitchData : VitalGlitchDataType; variable L0MULTIMSGEN00_GlitchData : VitalGlitchDataType; variable L0MULTIMSGEN01_GlitchData : VitalGlitchDataType; variable L0MULTIMSGEN02_GlitchData : VitalGlitchDataType; variable L0STATSDLLPRECEIVED_GlitchData : VitalGlitchDataType; variable L0STATSDLLPTRANSMITTED_GlitchData : VitalGlitchDataType; variable L0STATSOSRECEIVED_GlitchData : VitalGlitchDataType; variable L0STATSOSTRANSMITTED_GlitchData : VitalGlitchDataType; variable L0STATSTLPRECEIVED_GlitchData : VitalGlitchDataType; variable L0STATSTLPTRANSMITTED_GlitchData : VitalGlitchDataType; variable L0STATSCFGRECEIVED_GlitchData : VitalGlitchDataType; variable L0STATSCFGTRANSMITTED_GlitchData : VitalGlitchDataType; variable L0STATSCFGOTHERRECEIVED_GlitchData : VitalGlitchDataType; variable L0STATSCFGOTHERTRANSMITTED_GlitchData : VitalGlitchDataType; variable MAXPAYLOADSIZE0_GlitchData : VitalGlitchDataType; variable MAXPAYLOADSIZE1_GlitchData : VitalGlitchDataType; variable MAXPAYLOADSIZE2_GlitchData : VitalGlitchDataType; variable MAXREADREQUESTSIZE0_GlitchData : VitalGlitchDataType; variable MAXREADREQUESTSIZE1_GlitchData : VitalGlitchDataType; variable MAXREADREQUESTSIZE2_GlitchData : VitalGlitchDataType; variable IOSPACEENABLE_GlitchData : VitalGlitchDataType; variable MEMSPACEENABLE_GlitchData : VitalGlitchDataType; variable L0ATTENTIONINDICATORCONTROL0_GlitchData : VitalGlitchDataType; variable L0ATTENTIONINDICATORCONTROL1_GlitchData : VitalGlitchDataType; variable L0POWERINDICATORCONTROL0_GlitchData : VitalGlitchDataType; variable L0POWERINDICATORCONTROL1_GlitchData : VitalGlitchDataType; variable L0POWERCONTROLLERCONTROL_GlitchData : VitalGlitchDataType; variable L0TOGGLEELECTROMECHANICALINTERLOCK_GlitchData : VitalGlitchDataType; variable L0RXBEACON_GlitchData : VitalGlitchDataType; variable L0PWRSTATE00_GlitchData : VitalGlitchDataType; variable L0PWRSTATE01_GlitchData : VitalGlitchDataType; variable L0PMEACK_GlitchData : VitalGlitchDataType; variable L0PMEREQOUT_GlitchData : VitalGlitchDataType; variable L0PMEEN_GlitchData : VitalGlitchDataType; variable L0PWRINHIBITTRANSFERS_GlitchData : VitalGlitchDataType; variable L0PWRL1STATE_GlitchData : VitalGlitchDataType; variable L0PWRL23READYDEVICE_GlitchData : VitalGlitchDataType; variable L0PWRL23READYSTATE_GlitchData : VitalGlitchDataType; variable L0PWRTXL0SSTATE_GlitchData : VitalGlitchDataType; variable L0PWRTURNOFFREQ_GlitchData : VitalGlitchDataType; variable L0RXDLLPM_GlitchData : VitalGlitchDataType; variable L0RXDLLPMTYPE0_GlitchData : VitalGlitchDataType; variable L0RXDLLPMTYPE1_GlitchData : VitalGlitchDataType; variable L0RXDLLPMTYPE2_GlitchData : VitalGlitchDataType; variable L0TXDLLPMUPDATED_GlitchData : VitalGlitchDataType; variable L0MACNEWSTATEACK_GlitchData : VitalGlitchDataType; variable L0MACRXL0SSTATE_GlitchData : VitalGlitchDataType; variable L0MACENTEREDL0_GlitchData : VitalGlitchDataType; variable L0DLLRXACKOUTSTANDING_GlitchData : VitalGlitchDataType; variable L0DLLTXOUTSTANDING_GlitchData : VitalGlitchDataType; variable L0DLLTXNONFCOUTSTANDING_GlitchData : VitalGlitchDataType; variable L0RXDLLTLPEND0_GlitchData : VitalGlitchDataType; variable L0RXDLLTLPEND1_GlitchData : VitalGlitchDataType; variable L0TXDLLSBFCUPDATED_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA0_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA1_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA2_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA3_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA4_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA5_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA6_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA7_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA8_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA9_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA10_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA11_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA12_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA13_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA14_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA15_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA16_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA17_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCDATA18_GlitchData : VitalGlitchDataType; variable L0RXDLLSBFCUPDATE_GlitchData : VitalGlitchDataType; variable L0TXDLLFCNPOSTBYPUPDATED0_GlitchData : VitalGlitchDataType; variable L0TXDLLFCNPOSTBYPUPDATED1_GlitchData : VitalGlitchDataType; variable L0TXDLLFCNPOSTBYPUPDATED2_GlitchData : VitalGlitchDataType; variable L0TXDLLFCNPOSTBYPUPDATED3_GlitchData : VitalGlitchDataType; variable L0TXDLLFCNPOSTBYPUPDATED4_GlitchData : VitalGlitchDataType; variable L0TXDLLFCNPOSTBYPUPDATED5_GlitchData : VitalGlitchDataType; variable L0TXDLLFCNPOSTBYPUPDATED6_GlitchData : VitalGlitchDataType; variable L0TXDLLFCNPOSTBYPUPDATED7_GlitchData : VitalGlitchDataType; variable L0TXDLLFCPOSTORDUPDATED0_GlitchData : VitalGlitchDataType; variable L0TXDLLFCPOSTORDUPDATED1_GlitchData : VitalGlitchDataType; variable L0TXDLLFCPOSTORDUPDATED2_GlitchData : VitalGlitchDataType; variable L0TXDLLFCPOSTORDUPDATED3_GlitchData : VitalGlitchDataType; variable L0TXDLLFCPOSTORDUPDATED4_GlitchData : VitalGlitchDataType; variable L0TXDLLFCPOSTORDUPDATED5_GlitchData : VitalGlitchDataType; variable L0TXDLLFCPOSTORDUPDATED6_GlitchData : VitalGlitchDataType; variable L0TXDLLFCPOSTORDUPDATED7_GlitchData : VitalGlitchDataType; variable L0TXDLLFCCMPLMCUPDATED0_GlitchData : VitalGlitchDataType; variable L0TXDLLFCCMPLMCUPDATED1_GlitchData : VitalGlitchDataType; variable L0TXDLLFCCMPLMCUPDATED2_GlitchData : VitalGlitchDataType; variable L0TXDLLFCCMPLMCUPDATED3_GlitchData : VitalGlitchDataType; variable L0TXDLLFCCMPLMCUPDATED4_GlitchData : VitalGlitchDataType; variable L0TXDLLFCCMPLMCUPDATED5_GlitchData : VitalGlitchDataType; variable L0TXDLLFCCMPLMCUPDATED6_GlitchData : VitalGlitchDataType; variable L0TXDLLFCCMPLMCUPDATED7_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED0_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED1_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED2_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED3_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED4_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED5_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED6_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED7_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED8_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED9_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED10_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED11_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED12_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED13_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED14_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED15_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED16_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED17_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED18_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPCRED19_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPUPDATE0_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPUPDATE1_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPUPDATE2_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPUPDATE3_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPUPDATE4_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPUPDATE5_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPUPDATE6_GlitchData : VitalGlitchDataType; variable L0RXDLLFCNPOSTBYPUPDATE7_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED0_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED1_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED2_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED3_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED4_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED5_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED6_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED7_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED8_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED9_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED10_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED11_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED12_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED13_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED14_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED15_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED16_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED17_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED18_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED19_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED20_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED21_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED22_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDCRED23_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDUPDATE0_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDUPDATE1_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDUPDATE2_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDUPDATE3_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDUPDATE4_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDUPDATE5_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDUPDATE6_GlitchData : VitalGlitchDataType; variable L0RXDLLFCPOSTORDUPDATE7_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED0_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED1_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED2_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED3_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED4_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED5_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED6_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED7_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED8_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED9_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED10_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED11_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED12_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED13_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED14_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED15_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED16_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED17_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED18_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED19_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED20_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED21_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED22_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCCRED23_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCUPDATE0_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCUPDATE1_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCUPDATE2_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCUPDATE3_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCUPDATE4_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCUPDATE5_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCUPDATE6_GlitchData : VitalGlitchDataType; variable L0RXDLLFCCMPLMCUPDATE7_GlitchData : VitalGlitchDataType; variable L0UCBYPFOUND0_GlitchData : VitalGlitchDataType; variable L0UCBYPFOUND1_GlitchData : VitalGlitchDataType; variable L0UCBYPFOUND2_GlitchData : VitalGlitchDataType; variable L0UCBYPFOUND3_GlitchData : VitalGlitchDataType; variable L0UCORDFOUND0_GlitchData : VitalGlitchDataType; variable L0UCORDFOUND1_GlitchData : VitalGlitchDataType; variable L0UCORDFOUND2_GlitchData : VitalGlitchDataType; variable L0UCORDFOUND3_GlitchData : VitalGlitchDataType; variable L0MCFOUND0_GlitchData : VitalGlitchDataType; variable L0MCFOUND1_GlitchData : VitalGlitchDataType; variable L0MCFOUND2_GlitchData : VitalGlitchDataType; variable L0TRANSFORMEDVC0_GlitchData : VitalGlitchDataType; variable L0TRANSFORMEDVC1_GlitchData : VitalGlitchDataType; variable L0TRANSFORMEDVC2_GlitchData : VitalGlitchDataType; variable BUSMASTERENABLE_GlitchData : VitalGlitchDataType; variable PARITYERRORRESPONSE_GlitchData : VitalGlitchDataType; variable SERRENABLE_GlitchData : VitalGlitchDataType; variable INTERRUPTDISABLE_GlitchData : VitalGlitchDataType; variable URREPORTINGENABLE_GlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => PIPETXDATAL0(0), GlitchData => PIPETXDATAL00_GlitchData, OutSignalName => "PIPETXDATAL0(0)", OutTemp => PIPETXDATAL0_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL0(1), GlitchData => PIPETXDATAL01_GlitchData, OutSignalName => "PIPETXDATAL0(1)", OutTemp => PIPETXDATAL0_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL0(2), GlitchData => PIPETXDATAL02_GlitchData, OutSignalName => "PIPETXDATAL0(2)", OutTemp => PIPETXDATAL0_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL0(3), GlitchData => PIPETXDATAL03_GlitchData, OutSignalName => "PIPETXDATAL0(3)", OutTemp => PIPETXDATAL0_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL0(4), GlitchData => PIPETXDATAL04_GlitchData, OutSignalName => "PIPETXDATAL0(4)", OutTemp => PIPETXDATAL0_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL0(5), GlitchData => PIPETXDATAL05_GlitchData, OutSignalName => "PIPETXDATAL0(5)", OutTemp => PIPETXDATAL0_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL0(6), GlitchData => PIPETXDATAL06_GlitchData, OutSignalName => "PIPETXDATAL0(6)", OutTemp => PIPETXDATAL0_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL0(7), GlitchData => PIPETXDATAL07_GlitchData, OutSignalName => "PIPETXDATAL0(7)", OutTemp => PIPETXDATAL0_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAKL0, GlitchData => PIPETXDATAKL0_GlitchData, OutSignalName => "PIPETXDATAKL0", OutTemp => PIPETXDATAKL0_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXELECIDLEL0, GlitchData => PIPETXELECIDLEL0_GlitchData, OutSignalName => "PIPETXELECIDLEL0", OutTemp => PIPETXELECIDLEL0_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDETECTRXLOOPBACKL0, GlitchData => PIPETXDETECTRXLOOPBACKL0_GlitchData, OutSignalName => "PIPETXDETECTRXLOOPBACKL0", OutTemp => PIPETXDETECTRXLOOPBACKL0_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXCOMPLIANCEL0, GlitchData => PIPETXCOMPLIANCEL0_GlitchData, OutSignalName => "PIPETXCOMPLIANCEL0", OutTemp => PIPETXCOMPLIANCEL0_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERXPOLARITYL0, GlitchData => PIPERXPOLARITYL0_GlitchData, OutSignalName => "PIPERXPOLARITYL0", OutTemp => PIPERXPOLARITYL0_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL0(0), GlitchData => PIPEPOWERDOWNL00_GlitchData, OutSignalName => "PIPEPOWERDOWNL0(0)", OutTemp => PIPEPOWERDOWNL0_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL0(0), GlitchData => PIPEPOWERDOWNL00_GlitchData, OutSignalName => "PIPEPOWERDOWNL0(0)", OutTemp => PIPEPOWERDOWNL0_OUT(0), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL0(1), GlitchData => PIPEPOWERDOWNL01_GlitchData, OutSignalName => "PIPEPOWERDOWNL0(1)", OutTemp => PIPEPOWERDOWNL0_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL0(1), GlitchData => PIPEPOWERDOWNL01_GlitchData, OutSignalName => "PIPEPOWERDOWNL0(1)", OutTemp => PIPEPOWERDOWNL0_OUT(1), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEDESKEWLANESL0, GlitchData => PIPEDESKEWLANESL0_GlitchData, OutSignalName => "PIPEDESKEWLANESL0", OutTemp => PIPEDESKEWLANESL0_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERESETL0, GlitchData => PIPERESETL0_GlitchData, OutSignalName => "PIPERESETL0", OutTemp => PIPERESETL0_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL1(0), GlitchData => PIPETXDATAL10_GlitchData, OutSignalName => "PIPETXDATAL1(0)", OutTemp => PIPETXDATAL1_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL1(1), GlitchData => PIPETXDATAL11_GlitchData, OutSignalName => "PIPETXDATAL1(1)", OutTemp => PIPETXDATAL1_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL1(2), GlitchData => PIPETXDATAL12_GlitchData, OutSignalName => "PIPETXDATAL1(2)", OutTemp => PIPETXDATAL1_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL1(3), GlitchData => PIPETXDATAL13_GlitchData, OutSignalName => "PIPETXDATAL1(3)", OutTemp => PIPETXDATAL1_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL1(4), GlitchData => PIPETXDATAL14_GlitchData, OutSignalName => "PIPETXDATAL1(4)", OutTemp => PIPETXDATAL1_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL1(5), GlitchData => PIPETXDATAL15_GlitchData, OutSignalName => "PIPETXDATAL1(5)", OutTemp => PIPETXDATAL1_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL1(6), GlitchData => PIPETXDATAL16_GlitchData, OutSignalName => "PIPETXDATAL1(6)", OutTemp => PIPETXDATAL1_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL1(7), GlitchData => PIPETXDATAL17_GlitchData, OutSignalName => "PIPETXDATAL1(7)", OutTemp => PIPETXDATAL1_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAKL1, GlitchData => PIPETXDATAKL1_GlitchData, OutSignalName => "PIPETXDATAKL1", OutTemp => PIPETXDATAKL1_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXELECIDLEL1, GlitchData => PIPETXELECIDLEL1_GlitchData, OutSignalName => "PIPETXELECIDLEL1", OutTemp => PIPETXELECIDLEL1_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDETECTRXLOOPBACKL1, GlitchData => PIPETXDETECTRXLOOPBACKL1_GlitchData, OutSignalName => "PIPETXDETECTRXLOOPBACKL1", OutTemp => PIPETXDETECTRXLOOPBACKL1_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXCOMPLIANCEL1, GlitchData => PIPETXCOMPLIANCEL1_GlitchData, OutSignalName => "PIPETXCOMPLIANCEL1", OutTemp => PIPETXCOMPLIANCEL1_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERXPOLARITYL1, GlitchData => PIPERXPOLARITYL1_GlitchData, OutSignalName => "PIPERXPOLARITYL1", OutTemp => PIPERXPOLARITYL1_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL1(0), GlitchData => PIPEPOWERDOWNL10_GlitchData, OutSignalName => "PIPEPOWERDOWNL1(0)", OutTemp => PIPEPOWERDOWNL1_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL1(0), GlitchData => PIPEPOWERDOWNL10_GlitchData, OutSignalName => "PIPEPOWERDOWNL1(0)", OutTemp => PIPEPOWERDOWNL1_OUT(0), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL1(1), GlitchData => PIPEPOWERDOWNL11_GlitchData, OutSignalName => "PIPEPOWERDOWNL1(1)", OutTemp => PIPEPOWERDOWNL1_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL1(1), GlitchData => PIPEPOWERDOWNL11_GlitchData, OutSignalName => "PIPEPOWERDOWNL1(1)", OutTemp => PIPEPOWERDOWNL1_OUT(1), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEDESKEWLANESL1, GlitchData => PIPEDESKEWLANESL1_GlitchData, OutSignalName => "PIPEDESKEWLANESL1", OutTemp => PIPEDESKEWLANESL1_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERESETL1, GlitchData => PIPERESETL1_GlitchData, OutSignalName => "PIPERESETL1", OutTemp => PIPERESETL1_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL2(0), GlitchData => PIPETXDATAL20_GlitchData, OutSignalName => "PIPETXDATAL2(0)", OutTemp => PIPETXDATAL2_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL2(1), GlitchData => PIPETXDATAL21_GlitchData, OutSignalName => "PIPETXDATAL2(1)", OutTemp => PIPETXDATAL2_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL2(2), GlitchData => PIPETXDATAL22_GlitchData, OutSignalName => "PIPETXDATAL2(2)", OutTemp => PIPETXDATAL2_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL2(3), GlitchData => PIPETXDATAL23_GlitchData, OutSignalName => "PIPETXDATAL2(3)", OutTemp => PIPETXDATAL2_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL2(4), GlitchData => PIPETXDATAL24_GlitchData, OutSignalName => "PIPETXDATAL2(4)", OutTemp => PIPETXDATAL2_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL2(5), GlitchData => PIPETXDATAL25_GlitchData, OutSignalName => "PIPETXDATAL2(5)", OutTemp => PIPETXDATAL2_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL2(6), GlitchData => PIPETXDATAL26_GlitchData, OutSignalName => "PIPETXDATAL2(6)", OutTemp => PIPETXDATAL2_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL2(7), GlitchData => PIPETXDATAL27_GlitchData, OutSignalName => "PIPETXDATAL2(7)", OutTemp => PIPETXDATAL2_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAKL2, GlitchData => PIPETXDATAKL2_GlitchData, OutSignalName => "PIPETXDATAKL2", OutTemp => PIPETXDATAKL2_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXELECIDLEL2, GlitchData => PIPETXELECIDLEL2_GlitchData, OutSignalName => "PIPETXELECIDLEL2", OutTemp => PIPETXELECIDLEL2_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDETECTRXLOOPBACKL2, GlitchData => PIPETXDETECTRXLOOPBACKL2_GlitchData, OutSignalName => "PIPETXDETECTRXLOOPBACKL2", OutTemp => PIPETXDETECTRXLOOPBACKL2_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXCOMPLIANCEL2, GlitchData => PIPETXCOMPLIANCEL2_GlitchData, OutSignalName => "PIPETXCOMPLIANCEL2", OutTemp => PIPETXCOMPLIANCEL2_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERXPOLARITYL2, GlitchData => PIPERXPOLARITYL2_GlitchData, OutSignalName => "PIPERXPOLARITYL2", OutTemp => PIPERXPOLARITYL2_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL2(0), GlitchData => PIPEPOWERDOWNL20_GlitchData, OutSignalName => "PIPEPOWERDOWNL2(0)", OutTemp => PIPEPOWERDOWNL2_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL2(0), GlitchData => PIPEPOWERDOWNL20_GlitchData, OutSignalName => "PIPEPOWERDOWNL2(0)", OutTemp => PIPEPOWERDOWNL2_OUT(0), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL2(1), GlitchData => PIPEPOWERDOWNL21_GlitchData, OutSignalName => "PIPEPOWERDOWNL2(1)", OutTemp => PIPEPOWERDOWNL2_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL2(1), GlitchData => PIPEPOWERDOWNL21_GlitchData, OutSignalName => "PIPEPOWERDOWNL2(1)", OutTemp => PIPEPOWERDOWNL2_OUT(1), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEDESKEWLANESL2, GlitchData => PIPEDESKEWLANESL2_GlitchData, OutSignalName => "PIPEDESKEWLANESL2", OutTemp => PIPEDESKEWLANESL2_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERESETL2, GlitchData => PIPERESETL2_GlitchData, OutSignalName => "PIPERESETL2", OutTemp => PIPERESETL2_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL3(0), GlitchData => PIPETXDATAL30_GlitchData, OutSignalName => "PIPETXDATAL3(0)", OutTemp => PIPETXDATAL3_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL3(1), GlitchData => PIPETXDATAL31_GlitchData, OutSignalName => "PIPETXDATAL3(1)", OutTemp => PIPETXDATAL3_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL3(2), GlitchData => PIPETXDATAL32_GlitchData, OutSignalName => "PIPETXDATAL3(2)", OutTemp => PIPETXDATAL3_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL3(3), GlitchData => PIPETXDATAL33_GlitchData, OutSignalName => "PIPETXDATAL3(3)", OutTemp => PIPETXDATAL3_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL3(4), GlitchData => PIPETXDATAL34_GlitchData, OutSignalName => "PIPETXDATAL3(4)", OutTemp => PIPETXDATAL3_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL3(5), GlitchData => PIPETXDATAL35_GlitchData, OutSignalName => "PIPETXDATAL3(5)", OutTemp => PIPETXDATAL3_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL3(6), GlitchData => PIPETXDATAL36_GlitchData, OutSignalName => "PIPETXDATAL3(6)", OutTemp => PIPETXDATAL3_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL3(7), GlitchData => PIPETXDATAL37_GlitchData, OutSignalName => "PIPETXDATAL3(7)", OutTemp => PIPETXDATAL3_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAKL3, GlitchData => PIPETXDATAKL3_GlitchData, OutSignalName => "PIPETXDATAKL3", OutTemp => PIPETXDATAKL3_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXELECIDLEL3, GlitchData => PIPETXELECIDLEL3_GlitchData, OutSignalName => "PIPETXELECIDLEL3", OutTemp => PIPETXELECIDLEL3_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDETECTRXLOOPBACKL3, GlitchData => PIPETXDETECTRXLOOPBACKL3_GlitchData, OutSignalName => "PIPETXDETECTRXLOOPBACKL3", OutTemp => PIPETXDETECTRXLOOPBACKL3_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXCOMPLIANCEL3, GlitchData => PIPETXCOMPLIANCEL3_GlitchData, OutSignalName => "PIPETXCOMPLIANCEL3", OutTemp => PIPETXCOMPLIANCEL3_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERXPOLARITYL3, GlitchData => PIPERXPOLARITYL3_GlitchData, OutSignalName => "PIPERXPOLARITYL3", OutTemp => PIPERXPOLARITYL3_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL3(0), GlitchData => PIPEPOWERDOWNL30_GlitchData, OutSignalName => "PIPEPOWERDOWNL3(0)", OutTemp => PIPEPOWERDOWNL3_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL3(0), GlitchData => PIPEPOWERDOWNL30_GlitchData, OutSignalName => "PIPEPOWERDOWNL3(0)", OutTemp => PIPEPOWERDOWNL3_OUT(0), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL3(1), GlitchData => PIPEPOWERDOWNL31_GlitchData, OutSignalName => "PIPEPOWERDOWNL3(1)", OutTemp => PIPEPOWERDOWNL3_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL3(1), GlitchData => PIPEPOWERDOWNL31_GlitchData, OutSignalName => "PIPEPOWERDOWNL3(1)", OutTemp => PIPEPOWERDOWNL3_OUT(1), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEDESKEWLANESL3, GlitchData => PIPEDESKEWLANESL3_GlitchData, OutSignalName => "PIPEDESKEWLANESL3", OutTemp => PIPEDESKEWLANESL3_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERESETL3, GlitchData => PIPERESETL3_GlitchData, OutSignalName => "PIPERESETL3", OutTemp => PIPERESETL3_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL4(0), GlitchData => PIPETXDATAL40_GlitchData, OutSignalName => "PIPETXDATAL4(0)", OutTemp => PIPETXDATAL4_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL4(1), GlitchData => PIPETXDATAL41_GlitchData, OutSignalName => "PIPETXDATAL4(1)", OutTemp => PIPETXDATAL4_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL4(2), GlitchData => PIPETXDATAL42_GlitchData, OutSignalName => "PIPETXDATAL4(2)", OutTemp => PIPETXDATAL4_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL4(3), GlitchData => PIPETXDATAL43_GlitchData, OutSignalName => "PIPETXDATAL4(3)", OutTemp => PIPETXDATAL4_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL4(4), GlitchData => PIPETXDATAL44_GlitchData, OutSignalName => "PIPETXDATAL4(4)", OutTemp => PIPETXDATAL4_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL4(5), GlitchData => PIPETXDATAL45_GlitchData, OutSignalName => "PIPETXDATAL4(5)", OutTemp => PIPETXDATAL4_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL4(6), GlitchData => PIPETXDATAL46_GlitchData, OutSignalName => "PIPETXDATAL4(6)", OutTemp => PIPETXDATAL4_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL4(7), GlitchData => PIPETXDATAL47_GlitchData, OutSignalName => "PIPETXDATAL4(7)", OutTemp => PIPETXDATAL4_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAKL4, GlitchData => PIPETXDATAKL4_GlitchData, OutSignalName => "PIPETXDATAKL4", OutTemp => PIPETXDATAKL4_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXELECIDLEL4, GlitchData => PIPETXELECIDLEL4_GlitchData, OutSignalName => "PIPETXELECIDLEL4", OutTemp => PIPETXELECIDLEL4_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDETECTRXLOOPBACKL4, GlitchData => PIPETXDETECTRXLOOPBACKL4_GlitchData, OutSignalName => "PIPETXDETECTRXLOOPBACKL4", OutTemp => PIPETXDETECTRXLOOPBACKL4_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXCOMPLIANCEL4, GlitchData => PIPETXCOMPLIANCEL4_GlitchData, OutSignalName => "PIPETXCOMPLIANCEL4", OutTemp => PIPETXCOMPLIANCEL4_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERXPOLARITYL4, GlitchData => PIPERXPOLARITYL4_GlitchData, OutSignalName => "PIPERXPOLARITYL4", OutTemp => PIPERXPOLARITYL4_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL4(0), GlitchData => PIPEPOWERDOWNL40_GlitchData, OutSignalName => "PIPEPOWERDOWNL4(0)", OutTemp => PIPEPOWERDOWNL4_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL4(0), GlitchData => PIPEPOWERDOWNL40_GlitchData, OutSignalName => "PIPEPOWERDOWNL4(0)", OutTemp => PIPEPOWERDOWNL4_OUT(0), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL4(1), GlitchData => PIPEPOWERDOWNL41_GlitchData, OutSignalName => "PIPEPOWERDOWNL4(1)", OutTemp => PIPEPOWERDOWNL4_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL4(1), GlitchData => PIPEPOWERDOWNL41_GlitchData, OutSignalName => "PIPEPOWERDOWNL4(1)", OutTemp => PIPEPOWERDOWNL4_OUT(1), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEDESKEWLANESL4, GlitchData => PIPEDESKEWLANESL4_GlitchData, OutSignalName => "PIPEDESKEWLANESL4", OutTemp => PIPEDESKEWLANESL4_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERESETL4, GlitchData => PIPERESETL4_GlitchData, OutSignalName => "PIPERESETL4", OutTemp => PIPERESETL4_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL5(0), GlitchData => PIPETXDATAL50_GlitchData, OutSignalName => "PIPETXDATAL5(0)", OutTemp => PIPETXDATAL5_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL5(1), GlitchData => PIPETXDATAL51_GlitchData, OutSignalName => "PIPETXDATAL5(1)", OutTemp => PIPETXDATAL5_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL5(2), GlitchData => PIPETXDATAL52_GlitchData, OutSignalName => "PIPETXDATAL5(2)", OutTemp => PIPETXDATAL5_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL5(3), GlitchData => PIPETXDATAL53_GlitchData, OutSignalName => "PIPETXDATAL5(3)", OutTemp => PIPETXDATAL5_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL5(4), GlitchData => PIPETXDATAL54_GlitchData, OutSignalName => "PIPETXDATAL5(4)", OutTemp => PIPETXDATAL5_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL5(5), GlitchData => PIPETXDATAL55_GlitchData, OutSignalName => "PIPETXDATAL5(5)", OutTemp => PIPETXDATAL5_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL5(6), GlitchData => PIPETXDATAL56_GlitchData, OutSignalName => "PIPETXDATAL5(6)", OutTemp => PIPETXDATAL5_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL5(7), GlitchData => PIPETXDATAL57_GlitchData, OutSignalName => "PIPETXDATAL5(7)", OutTemp => PIPETXDATAL5_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAKL5, GlitchData => PIPETXDATAKL5_GlitchData, OutSignalName => "PIPETXDATAKL5", OutTemp => PIPETXDATAKL5_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXELECIDLEL5, GlitchData => PIPETXELECIDLEL5_GlitchData, OutSignalName => "PIPETXELECIDLEL5", OutTemp => PIPETXELECIDLEL5_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDETECTRXLOOPBACKL5, GlitchData => PIPETXDETECTRXLOOPBACKL5_GlitchData, OutSignalName => "PIPETXDETECTRXLOOPBACKL5", OutTemp => PIPETXDETECTRXLOOPBACKL5_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXCOMPLIANCEL5, GlitchData => PIPETXCOMPLIANCEL5_GlitchData, OutSignalName => "PIPETXCOMPLIANCEL5", OutTemp => PIPETXCOMPLIANCEL5_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERXPOLARITYL5, GlitchData => PIPERXPOLARITYL5_GlitchData, OutSignalName => "PIPERXPOLARITYL5", OutTemp => PIPERXPOLARITYL5_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL5(0), GlitchData => PIPEPOWERDOWNL50_GlitchData, OutSignalName => "PIPEPOWERDOWNL5(0)", OutTemp => PIPEPOWERDOWNL5_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL5(0), GlitchData => PIPEPOWERDOWNL50_GlitchData, OutSignalName => "PIPEPOWERDOWNL5(0)", OutTemp => PIPEPOWERDOWNL5_OUT(0), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL5(1), GlitchData => PIPEPOWERDOWNL51_GlitchData, OutSignalName => "PIPEPOWERDOWNL5(1)", OutTemp => PIPEPOWERDOWNL5_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL5(1), GlitchData => PIPEPOWERDOWNL51_GlitchData, OutSignalName => "PIPEPOWERDOWNL5(1)", OutTemp => PIPEPOWERDOWNL5_OUT(1), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEDESKEWLANESL5, GlitchData => PIPEDESKEWLANESL5_GlitchData, OutSignalName => "PIPEDESKEWLANESL5", OutTemp => PIPEDESKEWLANESL5_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERESETL5, GlitchData => PIPERESETL5_GlitchData, OutSignalName => "PIPERESETL5", OutTemp => PIPERESETL5_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL6(0), GlitchData => PIPETXDATAL60_GlitchData, OutSignalName => "PIPETXDATAL6(0)", OutTemp => PIPETXDATAL6_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL6(1), GlitchData => PIPETXDATAL61_GlitchData, OutSignalName => "PIPETXDATAL6(1)", OutTemp => PIPETXDATAL6_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL6(2), GlitchData => PIPETXDATAL62_GlitchData, OutSignalName => "PIPETXDATAL6(2)", OutTemp => PIPETXDATAL6_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL6(3), GlitchData => PIPETXDATAL63_GlitchData, OutSignalName => "PIPETXDATAL6(3)", OutTemp => PIPETXDATAL6_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL6(4), GlitchData => PIPETXDATAL64_GlitchData, OutSignalName => "PIPETXDATAL6(4)", OutTemp => PIPETXDATAL6_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL6(5), GlitchData => PIPETXDATAL65_GlitchData, OutSignalName => "PIPETXDATAL6(5)", OutTemp => PIPETXDATAL6_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL6(6), GlitchData => PIPETXDATAL66_GlitchData, OutSignalName => "PIPETXDATAL6(6)", OutTemp => PIPETXDATAL6_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL6(7), GlitchData => PIPETXDATAL67_GlitchData, OutSignalName => "PIPETXDATAL6(7)", OutTemp => PIPETXDATAL6_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAKL6, GlitchData => PIPETXDATAKL6_GlitchData, OutSignalName => "PIPETXDATAKL6", OutTemp => PIPETXDATAKL6_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXELECIDLEL6, GlitchData => PIPETXELECIDLEL6_GlitchData, OutSignalName => "PIPETXELECIDLEL6", OutTemp => PIPETXELECIDLEL6_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDETECTRXLOOPBACKL6, GlitchData => PIPETXDETECTRXLOOPBACKL6_GlitchData, OutSignalName => "PIPETXDETECTRXLOOPBACKL6", OutTemp => PIPETXDETECTRXLOOPBACKL6_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXCOMPLIANCEL6, GlitchData => PIPETXCOMPLIANCEL6_GlitchData, OutSignalName => "PIPETXCOMPLIANCEL6", OutTemp => PIPETXCOMPLIANCEL6_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERXPOLARITYL6, GlitchData => PIPERXPOLARITYL6_GlitchData, OutSignalName => "PIPERXPOLARITYL6", OutTemp => PIPERXPOLARITYL6_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL6(0), GlitchData => PIPEPOWERDOWNL60_GlitchData, OutSignalName => "PIPEPOWERDOWNL6(0)", OutTemp => PIPEPOWERDOWNL6_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL6(0), GlitchData => PIPEPOWERDOWNL60_GlitchData, OutSignalName => "PIPEPOWERDOWNL6(0)", OutTemp => PIPEPOWERDOWNL6_OUT(0), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL6(1), GlitchData => PIPEPOWERDOWNL61_GlitchData, OutSignalName => "PIPEPOWERDOWNL6(1)", OutTemp => PIPEPOWERDOWNL6_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL6(1), GlitchData => PIPEPOWERDOWNL61_GlitchData, OutSignalName => "PIPEPOWERDOWNL6(1)", OutTemp => PIPEPOWERDOWNL6_OUT(1), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEDESKEWLANESL6, GlitchData => PIPEDESKEWLANESL6_GlitchData, OutSignalName => "PIPEDESKEWLANESL6", OutTemp => PIPEDESKEWLANESL6_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERESETL6, GlitchData => PIPERESETL6_GlitchData, OutSignalName => "PIPERESETL6", OutTemp => PIPERESETL6_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL7(0), GlitchData => PIPETXDATAL70_GlitchData, OutSignalName => "PIPETXDATAL7(0)", OutTemp => PIPETXDATAL7_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL7(1), GlitchData => PIPETXDATAL71_GlitchData, OutSignalName => "PIPETXDATAL7(1)", OutTemp => PIPETXDATAL7_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL7(2), GlitchData => PIPETXDATAL72_GlitchData, OutSignalName => "PIPETXDATAL7(2)", OutTemp => PIPETXDATAL7_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL7(3), GlitchData => PIPETXDATAL73_GlitchData, OutSignalName => "PIPETXDATAL7(3)", OutTemp => PIPETXDATAL7_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL7(4), GlitchData => PIPETXDATAL74_GlitchData, OutSignalName => "PIPETXDATAL7(4)", OutTemp => PIPETXDATAL7_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL7(5), GlitchData => PIPETXDATAL75_GlitchData, OutSignalName => "PIPETXDATAL7(5)", OutTemp => PIPETXDATAL7_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL7(6), GlitchData => PIPETXDATAL76_GlitchData, OutSignalName => "PIPETXDATAL7(6)", OutTemp => PIPETXDATAL7_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAL7(7), GlitchData => PIPETXDATAL77_GlitchData, OutSignalName => "PIPETXDATAL7(7)", OutTemp => PIPETXDATAL7_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDATAKL7, GlitchData => PIPETXDATAKL7_GlitchData, OutSignalName => "PIPETXDATAKL7", OutTemp => PIPETXDATAKL7_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXELECIDLEL7, GlitchData => PIPETXELECIDLEL7_GlitchData, OutSignalName => "PIPETXELECIDLEL7", OutTemp => PIPETXELECIDLEL7_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXDETECTRXLOOPBACKL7, GlitchData => PIPETXDETECTRXLOOPBACKL7_GlitchData, OutSignalName => "PIPETXDETECTRXLOOPBACKL7", OutTemp => PIPETXDETECTRXLOOPBACKL7_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPETXCOMPLIANCEL7, GlitchData => PIPETXCOMPLIANCEL7_GlitchData, OutSignalName => "PIPETXCOMPLIANCEL7", OutTemp => PIPETXCOMPLIANCEL7_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERXPOLARITYL7, GlitchData => PIPERXPOLARITYL7_GlitchData, OutSignalName => "PIPERXPOLARITYL7", OutTemp => PIPERXPOLARITYL7_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL7(0), GlitchData => PIPEPOWERDOWNL70_GlitchData, OutSignalName => "PIPEPOWERDOWNL7(0)", OutTemp => PIPEPOWERDOWNL7_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL7(0), GlitchData => PIPEPOWERDOWNL70_GlitchData, OutSignalName => "PIPEPOWERDOWNL7(0)", OutTemp => PIPEPOWERDOWNL7_OUT(0), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL7(1), GlitchData => PIPEPOWERDOWNL71_GlitchData, OutSignalName => "PIPEPOWERDOWNL7(1)", OutTemp => PIPEPOWERDOWNL7_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEPOWERDOWNL7(1), GlitchData => PIPEPOWERDOWNL71_GlitchData, OutSignalName => "PIPEPOWERDOWNL7(1)", OutTemp => PIPEPOWERDOWNL7_OUT(1), Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPEDESKEWLANESL7, GlitchData => PIPEDESKEWLANESL7_GlitchData, OutSignalName => "PIPEDESKEWLANESL7", OutTemp => PIPEDESKEWLANESL7_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PIPERESETL7, GlitchData => PIPERESETL7_GlitchData, OutSignalName => "PIPERESETL7", OutTemp => PIPERESETL7_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(0), GlitchData => MIMRXBWDATA0_GlitchData, OutSignalName => "MIMRXBWDATA(0)", OutTemp => MIMRXBWDATA_OUT(0), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(1), GlitchData => MIMRXBWDATA1_GlitchData, OutSignalName => "MIMRXBWDATA(1)", OutTemp => MIMRXBWDATA_OUT(1), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(2), GlitchData => MIMRXBWDATA2_GlitchData, OutSignalName => "MIMRXBWDATA(2)", OutTemp => MIMRXBWDATA_OUT(2), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(3), GlitchData => MIMRXBWDATA3_GlitchData, OutSignalName => "MIMRXBWDATA(3)", OutTemp => MIMRXBWDATA_OUT(3), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(4), GlitchData => MIMRXBWDATA4_GlitchData, OutSignalName => "MIMRXBWDATA(4)", OutTemp => MIMRXBWDATA_OUT(4), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(5), GlitchData => MIMRXBWDATA5_GlitchData, OutSignalName => "MIMRXBWDATA(5)", OutTemp => MIMRXBWDATA_OUT(5), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(6), GlitchData => MIMRXBWDATA6_GlitchData, OutSignalName => "MIMRXBWDATA(6)", OutTemp => MIMRXBWDATA_OUT(6), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(7), GlitchData => MIMRXBWDATA7_GlitchData, OutSignalName => "MIMRXBWDATA(7)", OutTemp => MIMRXBWDATA_OUT(7), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(8), GlitchData => MIMRXBWDATA8_GlitchData, OutSignalName => "MIMRXBWDATA(8)", OutTemp => MIMRXBWDATA_OUT(8), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(9), GlitchData => MIMRXBWDATA9_GlitchData, OutSignalName => "MIMRXBWDATA(9)", OutTemp => MIMRXBWDATA_OUT(9), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(10), GlitchData => MIMRXBWDATA10_GlitchData, OutSignalName => "MIMRXBWDATA(10)", OutTemp => MIMRXBWDATA_OUT(10), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(11), GlitchData => MIMRXBWDATA11_GlitchData, OutSignalName => "MIMRXBWDATA(11)", OutTemp => MIMRXBWDATA_OUT(11), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(12), GlitchData => MIMRXBWDATA12_GlitchData, OutSignalName => "MIMRXBWDATA(12)", OutTemp => MIMRXBWDATA_OUT(12), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(13), GlitchData => MIMRXBWDATA13_GlitchData, OutSignalName => "MIMRXBWDATA(13)", OutTemp => MIMRXBWDATA_OUT(13), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(14), GlitchData => MIMRXBWDATA14_GlitchData, OutSignalName => "MIMRXBWDATA(14)", OutTemp => MIMRXBWDATA_OUT(14), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(15), GlitchData => MIMRXBWDATA15_GlitchData, OutSignalName => "MIMRXBWDATA(15)", OutTemp => MIMRXBWDATA_OUT(15), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(16), GlitchData => MIMRXBWDATA16_GlitchData, OutSignalName => "MIMRXBWDATA(16)", OutTemp => MIMRXBWDATA_OUT(16), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(17), GlitchData => MIMRXBWDATA17_GlitchData, OutSignalName => "MIMRXBWDATA(17)", OutTemp => MIMRXBWDATA_OUT(17), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(18), GlitchData => MIMRXBWDATA18_GlitchData, OutSignalName => "MIMRXBWDATA(18)", OutTemp => MIMRXBWDATA_OUT(18), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(19), GlitchData => MIMRXBWDATA19_GlitchData, OutSignalName => "MIMRXBWDATA(19)", OutTemp => MIMRXBWDATA_OUT(19), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(20), GlitchData => MIMRXBWDATA20_GlitchData, OutSignalName => "MIMRXBWDATA(20)", OutTemp => MIMRXBWDATA_OUT(20), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(21), GlitchData => MIMRXBWDATA21_GlitchData, OutSignalName => "MIMRXBWDATA(21)", OutTemp => MIMRXBWDATA_OUT(21), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(22), GlitchData => MIMRXBWDATA22_GlitchData, OutSignalName => "MIMRXBWDATA(22)", OutTemp => MIMRXBWDATA_OUT(22), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(23), GlitchData => MIMRXBWDATA23_GlitchData, OutSignalName => "MIMRXBWDATA(23)", OutTemp => MIMRXBWDATA_OUT(23), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(24), GlitchData => MIMRXBWDATA24_GlitchData, OutSignalName => "MIMRXBWDATA(24)", OutTemp => MIMRXBWDATA_OUT(24), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(25), GlitchData => MIMRXBWDATA25_GlitchData, OutSignalName => "MIMRXBWDATA(25)", OutTemp => MIMRXBWDATA_OUT(25), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(26), GlitchData => MIMRXBWDATA26_GlitchData, OutSignalName => "MIMRXBWDATA(26)", OutTemp => MIMRXBWDATA_OUT(26), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(27), GlitchData => MIMRXBWDATA27_GlitchData, OutSignalName => "MIMRXBWDATA(27)", OutTemp => MIMRXBWDATA_OUT(27), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(28), GlitchData => MIMRXBWDATA28_GlitchData, OutSignalName => "MIMRXBWDATA(28)", OutTemp => MIMRXBWDATA_OUT(28), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(29), GlitchData => MIMRXBWDATA29_GlitchData, OutSignalName => "MIMRXBWDATA(29)", OutTemp => MIMRXBWDATA_OUT(29), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(30), GlitchData => MIMRXBWDATA30_GlitchData, OutSignalName => "MIMRXBWDATA(30)", OutTemp => MIMRXBWDATA_OUT(30), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(31), GlitchData => MIMRXBWDATA31_GlitchData, OutSignalName => "MIMRXBWDATA(31)", OutTemp => MIMRXBWDATA_OUT(31), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(32), GlitchData => MIMRXBWDATA32_GlitchData, OutSignalName => "MIMRXBWDATA(32)", OutTemp => MIMRXBWDATA_OUT(32), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(33), GlitchData => MIMRXBWDATA33_GlitchData, OutSignalName => "MIMRXBWDATA(33)", OutTemp => MIMRXBWDATA_OUT(33), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(34), GlitchData => MIMRXBWDATA34_GlitchData, OutSignalName => "MIMRXBWDATA(34)", OutTemp => MIMRXBWDATA_OUT(34), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(35), GlitchData => MIMRXBWDATA35_GlitchData, OutSignalName => "MIMRXBWDATA(35)", OutTemp => MIMRXBWDATA_OUT(35), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(36), GlitchData => MIMRXBWDATA36_GlitchData, OutSignalName => "MIMRXBWDATA(36)", OutTemp => MIMRXBWDATA_OUT(36), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(37), GlitchData => MIMRXBWDATA37_GlitchData, OutSignalName => "MIMRXBWDATA(37)", OutTemp => MIMRXBWDATA_OUT(37), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(38), GlitchData => MIMRXBWDATA38_GlitchData, OutSignalName => "MIMRXBWDATA(38)", OutTemp => MIMRXBWDATA_OUT(38), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(39), GlitchData => MIMRXBWDATA39_GlitchData, OutSignalName => "MIMRXBWDATA(39)", OutTemp => MIMRXBWDATA_OUT(39), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(40), GlitchData => MIMRXBWDATA40_GlitchData, OutSignalName => "MIMRXBWDATA(40)", OutTemp => MIMRXBWDATA_OUT(40), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(41), GlitchData => MIMRXBWDATA41_GlitchData, OutSignalName => "MIMRXBWDATA(41)", OutTemp => MIMRXBWDATA_OUT(41), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(42), GlitchData => MIMRXBWDATA42_GlitchData, OutSignalName => "MIMRXBWDATA(42)", OutTemp => MIMRXBWDATA_OUT(42), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(43), GlitchData => MIMRXBWDATA43_GlitchData, OutSignalName => "MIMRXBWDATA(43)", OutTemp => MIMRXBWDATA_OUT(43), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(44), GlitchData => MIMRXBWDATA44_GlitchData, OutSignalName => "MIMRXBWDATA(44)", OutTemp => MIMRXBWDATA_OUT(44), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(45), GlitchData => MIMRXBWDATA45_GlitchData, OutSignalName => "MIMRXBWDATA(45)", OutTemp => MIMRXBWDATA_OUT(45), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(46), GlitchData => MIMRXBWDATA46_GlitchData, OutSignalName => "MIMRXBWDATA(46)", OutTemp => MIMRXBWDATA_OUT(46), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(47), GlitchData => MIMRXBWDATA47_GlitchData, OutSignalName => "MIMRXBWDATA(47)", OutTemp => MIMRXBWDATA_OUT(47), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(48), GlitchData => MIMRXBWDATA48_GlitchData, OutSignalName => "MIMRXBWDATA(48)", OutTemp => MIMRXBWDATA_OUT(48), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(49), GlitchData => MIMRXBWDATA49_GlitchData, OutSignalName => "MIMRXBWDATA(49)", OutTemp => MIMRXBWDATA_OUT(49), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(50), GlitchData => MIMRXBWDATA50_GlitchData, OutSignalName => "MIMRXBWDATA(50)", OutTemp => MIMRXBWDATA_OUT(50), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(51), GlitchData => MIMRXBWDATA51_GlitchData, OutSignalName => "MIMRXBWDATA(51)", OutTemp => MIMRXBWDATA_OUT(51), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(52), GlitchData => MIMRXBWDATA52_GlitchData, OutSignalName => "MIMRXBWDATA(52)", OutTemp => MIMRXBWDATA_OUT(52), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(53), GlitchData => MIMRXBWDATA53_GlitchData, OutSignalName => "MIMRXBWDATA(53)", OutTemp => MIMRXBWDATA_OUT(53), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(54), GlitchData => MIMRXBWDATA54_GlitchData, OutSignalName => "MIMRXBWDATA(54)", OutTemp => MIMRXBWDATA_OUT(54), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(55), GlitchData => MIMRXBWDATA55_GlitchData, OutSignalName => "MIMRXBWDATA(55)", OutTemp => MIMRXBWDATA_OUT(55), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(56), GlitchData => MIMRXBWDATA56_GlitchData, OutSignalName => "MIMRXBWDATA(56)", OutTemp => MIMRXBWDATA_OUT(56), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(57), GlitchData => MIMRXBWDATA57_GlitchData, OutSignalName => "MIMRXBWDATA(57)", OutTemp => MIMRXBWDATA_OUT(57), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(58), GlitchData => MIMRXBWDATA58_GlitchData, OutSignalName => "MIMRXBWDATA(58)", OutTemp => MIMRXBWDATA_OUT(58), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(59), GlitchData => MIMRXBWDATA59_GlitchData, OutSignalName => "MIMRXBWDATA(59)", OutTemp => MIMRXBWDATA_OUT(59), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(60), GlitchData => MIMRXBWDATA60_GlitchData, OutSignalName => "MIMRXBWDATA(60)", OutTemp => MIMRXBWDATA_OUT(60), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(61), GlitchData => MIMRXBWDATA61_GlitchData, OutSignalName => "MIMRXBWDATA(61)", OutTemp => MIMRXBWDATA_OUT(61), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(62), GlitchData => MIMRXBWDATA62_GlitchData, OutSignalName => "MIMRXBWDATA(62)", OutTemp => MIMRXBWDATA_OUT(62), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWDATA(63), GlitchData => MIMRXBWDATA63_GlitchData, OutSignalName => "MIMRXBWDATA(63)", OutTemp => MIMRXBWDATA_OUT(63), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(0), GlitchData => MIMRXBWADD0_GlitchData, OutSignalName => "MIMRXBWADD(0)", OutTemp => MIMRXBWADD_OUT(0), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(1), GlitchData => MIMRXBWADD1_GlitchData, OutSignalName => "MIMRXBWADD(1)", OutTemp => MIMRXBWADD_OUT(1), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(2), GlitchData => MIMRXBWADD2_GlitchData, OutSignalName => "MIMRXBWADD(2)", OutTemp => MIMRXBWADD_OUT(2), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(3), GlitchData => MIMRXBWADD3_GlitchData, OutSignalName => "MIMRXBWADD(3)", OutTemp => MIMRXBWADD_OUT(3), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(4), GlitchData => MIMRXBWADD4_GlitchData, OutSignalName => "MIMRXBWADD(4)", OutTemp => MIMRXBWADD_OUT(4), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(5), GlitchData => MIMRXBWADD5_GlitchData, OutSignalName => "MIMRXBWADD(5)", OutTemp => MIMRXBWADD_OUT(5), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(6), GlitchData => MIMRXBWADD6_GlitchData, OutSignalName => "MIMRXBWADD(6)", OutTemp => MIMRXBWADD_OUT(6), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(7), GlitchData => MIMRXBWADD7_GlitchData, OutSignalName => "MIMRXBWADD(7)", OutTemp => MIMRXBWADD_OUT(7), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(8), GlitchData => MIMRXBWADD8_GlitchData, OutSignalName => "MIMRXBWADD(8)", OutTemp => MIMRXBWADD_OUT(8), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(9), GlitchData => MIMRXBWADD9_GlitchData, OutSignalName => "MIMRXBWADD(9)", OutTemp => MIMRXBWADD_OUT(9), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(10), GlitchData => MIMRXBWADD10_GlitchData, OutSignalName => "MIMRXBWADD(10)", OutTemp => MIMRXBWADD_OUT(10), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(11), GlitchData => MIMRXBWADD11_GlitchData, OutSignalName => "MIMRXBWADD(11)", OutTemp => MIMRXBWADD_OUT(11), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWADD(12), GlitchData => MIMRXBWADD12_GlitchData, OutSignalName => "MIMRXBWADD(12)", OutTemp => MIMRXBWADD_OUT(12), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(0), GlitchData => MIMRXBRADD0_GlitchData, OutSignalName => "MIMRXBRADD(0)", OutTemp => MIMRXBRADD_OUT(0), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(0), GlitchData => MIMRXBRADD0_GlitchData, OutSignalName => "MIMRXBRADD(0)", OutTemp => MIMRXBRADD_OUT(0), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(1), GlitchData => MIMRXBRADD1_GlitchData, OutSignalName => "MIMRXBRADD(1)", OutTemp => MIMRXBRADD_OUT(1), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(1), GlitchData => MIMRXBRADD1_GlitchData, OutSignalName => "MIMRXBRADD(1)", OutTemp => MIMRXBRADD_OUT(1), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(2), GlitchData => MIMRXBRADD2_GlitchData, OutSignalName => "MIMRXBRADD(2)", OutTemp => MIMRXBRADD_OUT(2), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(2), GlitchData => MIMRXBRADD2_GlitchData, OutSignalName => "MIMRXBRADD(2)", OutTemp => MIMRXBRADD_OUT(2), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(3), GlitchData => MIMRXBRADD3_GlitchData, OutSignalName => "MIMRXBRADD(3)", OutTemp => MIMRXBRADD_OUT(3), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(3), GlitchData => MIMRXBRADD3_GlitchData, OutSignalName => "MIMRXBRADD(3)", OutTemp => MIMRXBRADD_OUT(3), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(4), GlitchData => MIMRXBRADD4_GlitchData, OutSignalName => "MIMRXBRADD(4)", OutTemp => MIMRXBRADD_OUT(4), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(4), GlitchData => MIMRXBRADD4_GlitchData, OutSignalName => "MIMRXBRADD(4)", OutTemp => MIMRXBRADD_OUT(4), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(5), GlitchData => MIMRXBRADD5_GlitchData, OutSignalName => "MIMRXBRADD(5)", OutTemp => MIMRXBRADD_OUT(5), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(5), GlitchData => MIMRXBRADD5_GlitchData, OutSignalName => "MIMRXBRADD(5)", OutTemp => MIMRXBRADD_OUT(5), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(6), GlitchData => MIMRXBRADD6_GlitchData, OutSignalName => "MIMRXBRADD(6)", OutTemp => MIMRXBRADD_OUT(6), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(6), GlitchData => MIMRXBRADD6_GlitchData, OutSignalName => "MIMRXBRADD(6)", OutTemp => MIMRXBRADD_OUT(6), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(7), GlitchData => MIMRXBRADD7_GlitchData, OutSignalName => "MIMRXBRADD(7)", OutTemp => MIMRXBRADD_OUT(7), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(7), GlitchData => MIMRXBRADD7_GlitchData, OutSignalName => "MIMRXBRADD(7)", OutTemp => MIMRXBRADD_OUT(7), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(8), GlitchData => MIMRXBRADD8_GlitchData, OutSignalName => "MIMRXBRADD(8)", OutTemp => MIMRXBRADD_OUT(8), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(8), GlitchData => MIMRXBRADD8_GlitchData, OutSignalName => "MIMRXBRADD(8)", OutTemp => MIMRXBRADD_OUT(8), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(9), GlitchData => MIMRXBRADD9_GlitchData, OutSignalName => "MIMRXBRADD(9)", OutTemp => MIMRXBRADD_OUT(9), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(9), GlitchData => MIMRXBRADD9_GlitchData, OutSignalName => "MIMRXBRADD(9)", OutTemp => MIMRXBRADD_OUT(9), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(10), GlitchData => MIMRXBRADD10_GlitchData, OutSignalName => "MIMRXBRADD(10)", OutTemp => MIMRXBRADD_OUT(10), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(10), GlitchData => MIMRXBRADD10_GlitchData, OutSignalName => "MIMRXBRADD(10)", OutTemp => MIMRXBRADD_OUT(10), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(11), GlitchData => MIMRXBRADD11_GlitchData, OutSignalName => "MIMRXBRADD(11)", OutTemp => MIMRXBRADD_OUT(11), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(11), GlitchData => MIMRXBRADD11_GlitchData, OutSignalName => "MIMRXBRADD(11)", OutTemp => MIMRXBRADD_OUT(11), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(12), GlitchData => MIMRXBRADD12_GlitchData, OutSignalName => "MIMRXBRADD(12)", OutTemp => MIMRXBRADD_OUT(12), Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBRADD(12), GlitchData => MIMRXBRADD12_GlitchData, OutSignalName => "MIMRXBRADD(12)", OutTemp => MIMRXBRADD_OUT(12), Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBWEN, GlitchData => MIMRXBWEN_GlitchData, OutSignalName => "MIMRXBWEN", OutTemp => MIMRXBWEN_OUT, Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBREN, GlitchData => MIMRXBREN_GlitchData, OutSignalName => "MIMRXBREN", OutTemp => MIMRXBREN_OUT, Paths => (0 => (CRMUSERCLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMRXBREN, GlitchData => MIMRXBREN_GlitchData, OutSignalName => "MIMRXBREN", OutTemp => MIMRXBREN_OUT, Paths => (0 => (CRMCORECLKRXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(0), GlitchData => MIMTXBWDATA0_GlitchData, OutSignalName => "MIMTXBWDATA(0)", OutTemp => MIMTXBWDATA_OUT(0), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(0), GlitchData => MIMTXBWDATA0_GlitchData, OutSignalName => "MIMTXBWDATA(0)", OutTemp => MIMTXBWDATA_OUT(0), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(1), GlitchData => MIMTXBWDATA1_GlitchData, OutSignalName => "MIMTXBWDATA(1)", OutTemp => MIMTXBWDATA_OUT(1), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(1), GlitchData => MIMTXBWDATA1_GlitchData, OutSignalName => "MIMTXBWDATA(1)", OutTemp => MIMTXBWDATA_OUT(1), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(2), GlitchData => MIMTXBWDATA2_GlitchData, OutSignalName => "MIMTXBWDATA(2)", OutTemp => MIMTXBWDATA_OUT(2), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(2), GlitchData => MIMTXBWDATA2_GlitchData, OutSignalName => "MIMTXBWDATA(2)", OutTemp => MIMTXBWDATA_OUT(2), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(3), GlitchData => MIMTXBWDATA3_GlitchData, OutSignalName => "MIMTXBWDATA(3)", OutTemp => MIMTXBWDATA_OUT(3), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(3), GlitchData => MIMTXBWDATA3_GlitchData, OutSignalName => "MIMTXBWDATA(3)", OutTemp => MIMTXBWDATA_OUT(3), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(4), GlitchData => MIMTXBWDATA4_GlitchData, OutSignalName => "MIMTXBWDATA(4)", OutTemp => MIMTXBWDATA_OUT(4), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(4), GlitchData => MIMTXBWDATA4_GlitchData, OutSignalName => "MIMTXBWDATA(4)", OutTemp => MIMTXBWDATA_OUT(4), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(5), GlitchData => MIMTXBWDATA5_GlitchData, OutSignalName => "MIMTXBWDATA(5)", OutTemp => MIMTXBWDATA_OUT(5), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(5), GlitchData => MIMTXBWDATA5_GlitchData, OutSignalName => "MIMTXBWDATA(5)", OutTemp => MIMTXBWDATA_OUT(5), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(6), GlitchData => MIMTXBWDATA6_GlitchData, OutSignalName => "MIMTXBWDATA(6)", OutTemp => MIMTXBWDATA_OUT(6), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(6), GlitchData => MIMTXBWDATA6_GlitchData, OutSignalName => "MIMTXBWDATA(6)", OutTemp => MIMTXBWDATA_OUT(6), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(7), GlitchData => MIMTXBWDATA7_GlitchData, OutSignalName => "MIMTXBWDATA(7)", OutTemp => MIMTXBWDATA_OUT(7), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(7), GlitchData => MIMTXBWDATA7_GlitchData, OutSignalName => "MIMTXBWDATA(7)", OutTemp => MIMTXBWDATA_OUT(7), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(8), GlitchData => MIMTXBWDATA8_GlitchData, OutSignalName => "MIMTXBWDATA(8)", OutTemp => MIMTXBWDATA_OUT(8), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(8), GlitchData => MIMTXBWDATA8_GlitchData, OutSignalName => "MIMTXBWDATA(8)", OutTemp => MIMTXBWDATA_OUT(8), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(9), GlitchData => MIMTXBWDATA9_GlitchData, OutSignalName => "MIMTXBWDATA(9)", OutTemp => MIMTXBWDATA_OUT(9), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(9), GlitchData => MIMTXBWDATA9_GlitchData, OutSignalName => "MIMTXBWDATA(9)", OutTemp => MIMTXBWDATA_OUT(9), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(10), GlitchData => MIMTXBWDATA10_GlitchData, OutSignalName => "MIMTXBWDATA(10)", OutTemp => MIMTXBWDATA_OUT(10), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(10), GlitchData => MIMTXBWDATA10_GlitchData, OutSignalName => "MIMTXBWDATA(10)", OutTemp => MIMTXBWDATA_OUT(10), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(11), GlitchData => MIMTXBWDATA11_GlitchData, OutSignalName => "MIMTXBWDATA(11)", OutTemp => MIMTXBWDATA_OUT(11), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(11), GlitchData => MIMTXBWDATA11_GlitchData, OutSignalName => "MIMTXBWDATA(11)", OutTemp => MIMTXBWDATA_OUT(11), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(12), GlitchData => MIMTXBWDATA12_GlitchData, OutSignalName => "MIMTXBWDATA(12)", OutTemp => MIMTXBWDATA_OUT(12), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(12), GlitchData => MIMTXBWDATA12_GlitchData, OutSignalName => "MIMTXBWDATA(12)", OutTemp => MIMTXBWDATA_OUT(12), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(13), GlitchData => MIMTXBWDATA13_GlitchData, OutSignalName => "MIMTXBWDATA(13)", OutTemp => MIMTXBWDATA_OUT(13), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(13), GlitchData => MIMTXBWDATA13_GlitchData, OutSignalName => "MIMTXBWDATA(13)", OutTemp => MIMTXBWDATA_OUT(13), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(14), GlitchData => MIMTXBWDATA14_GlitchData, OutSignalName => "MIMTXBWDATA(14)", OutTemp => MIMTXBWDATA_OUT(14), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(14), GlitchData => MIMTXBWDATA14_GlitchData, OutSignalName => "MIMTXBWDATA(14)", OutTemp => MIMTXBWDATA_OUT(14), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(15), GlitchData => MIMTXBWDATA15_GlitchData, OutSignalName => "MIMTXBWDATA(15)", OutTemp => MIMTXBWDATA_OUT(15), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(15), GlitchData => MIMTXBWDATA15_GlitchData, OutSignalName => "MIMTXBWDATA(15)", OutTemp => MIMTXBWDATA_OUT(15), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(16), GlitchData => MIMTXBWDATA16_GlitchData, OutSignalName => "MIMTXBWDATA(16)", OutTemp => MIMTXBWDATA_OUT(16), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(16), GlitchData => MIMTXBWDATA16_GlitchData, OutSignalName => "MIMTXBWDATA(16)", OutTemp => MIMTXBWDATA_OUT(16), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(17), GlitchData => MIMTXBWDATA17_GlitchData, OutSignalName => "MIMTXBWDATA(17)", OutTemp => MIMTXBWDATA_OUT(17), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(17), GlitchData => MIMTXBWDATA17_GlitchData, OutSignalName => "MIMTXBWDATA(17)", OutTemp => MIMTXBWDATA_OUT(17), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(18), GlitchData => MIMTXBWDATA18_GlitchData, OutSignalName => "MIMTXBWDATA(18)", OutTemp => MIMTXBWDATA_OUT(18), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(18), GlitchData => MIMTXBWDATA18_GlitchData, OutSignalName => "MIMTXBWDATA(18)", OutTemp => MIMTXBWDATA_OUT(18), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(19), GlitchData => MIMTXBWDATA19_GlitchData, OutSignalName => "MIMTXBWDATA(19)", OutTemp => MIMTXBWDATA_OUT(19), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(19), GlitchData => MIMTXBWDATA19_GlitchData, OutSignalName => "MIMTXBWDATA(19)", OutTemp => MIMTXBWDATA_OUT(19), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(20), GlitchData => MIMTXBWDATA20_GlitchData, OutSignalName => "MIMTXBWDATA(20)", OutTemp => MIMTXBWDATA_OUT(20), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(20), GlitchData => MIMTXBWDATA20_GlitchData, OutSignalName => "MIMTXBWDATA(20)", OutTemp => MIMTXBWDATA_OUT(20), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(21), GlitchData => MIMTXBWDATA21_GlitchData, OutSignalName => "MIMTXBWDATA(21)", OutTemp => MIMTXBWDATA_OUT(21), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(21), GlitchData => MIMTXBWDATA21_GlitchData, OutSignalName => "MIMTXBWDATA(21)", OutTemp => MIMTXBWDATA_OUT(21), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(22), GlitchData => MIMTXBWDATA22_GlitchData, OutSignalName => "MIMTXBWDATA(22)", OutTemp => MIMTXBWDATA_OUT(22), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(22), GlitchData => MIMTXBWDATA22_GlitchData, OutSignalName => "MIMTXBWDATA(22)", OutTemp => MIMTXBWDATA_OUT(22), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(23), GlitchData => MIMTXBWDATA23_GlitchData, OutSignalName => "MIMTXBWDATA(23)", OutTemp => MIMTXBWDATA_OUT(23), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(23), GlitchData => MIMTXBWDATA23_GlitchData, OutSignalName => "MIMTXBWDATA(23)", OutTemp => MIMTXBWDATA_OUT(23), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(24), GlitchData => MIMTXBWDATA24_GlitchData, OutSignalName => "MIMTXBWDATA(24)", OutTemp => MIMTXBWDATA_OUT(24), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(24), GlitchData => MIMTXBWDATA24_GlitchData, OutSignalName => "MIMTXBWDATA(24)", OutTemp => MIMTXBWDATA_OUT(24), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(25), GlitchData => MIMTXBWDATA25_GlitchData, OutSignalName => "MIMTXBWDATA(25)", OutTemp => MIMTXBWDATA_OUT(25), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(25), GlitchData => MIMTXBWDATA25_GlitchData, OutSignalName => "MIMTXBWDATA(25)", OutTemp => MIMTXBWDATA_OUT(25), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(26), GlitchData => MIMTXBWDATA26_GlitchData, OutSignalName => "MIMTXBWDATA(26)", OutTemp => MIMTXBWDATA_OUT(26), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(26), GlitchData => MIMTXBWDATA26_GlitchData, OutSignalName => "MIMTXBWDATA(26)", OutTemp => MIMTXBWDATA_OUT(26), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(27), GlitchData => MIMTXBWDATA27_GlitchData, OutSignalName => "MIMTXBWDATA(27)", OutTemp => MIMTXBWDATA_OUT(27), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(27), GlitchData => MIMTXBWDATA27_GlitchData, OutSignalName => "MIMTXBWDATA(27)", OutTemp => MIMTXBWDATA_OUT(27), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(28), GlitchData => MIMTXBWDATA28_GlitchData, OutSignalName => "MIMTXBWDATA(28)", OutTemp => MIMTXBWDATA_OUT(28), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(28), GlitchData => MIMTXBWDATA28_GlitchData, OutSignalName => "MIMTXBWDATA(28)", OutTemp => MIMTXBWDATA_OUT(28), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(29), GlitchData => MIMTXBWDATA29_GlitchData, OutSignalName => "MIMTXBWDATA(29)", OutTemp => MIMTXBWDATA_OUT(29), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(29), GlitchData => MIMTXBWDATA29_GlitchData, OutSignalName => "MIMTXBWDATA(29)", OutTemp => MIMTXBWDATA_OUT(29), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(30), GlitchData => MIMTXBWDATA30_GlitchData, OutSignalName => "MIMTXBWDATA(30)", OutTemp => MIMTXBWDATA_OUT(30), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(30), GlitchData => MIMTXBWDATA30_GlitchData, OutSignalName => "MIMTXBWDATA(30)", OutTemp => MIMTXBWDATA_OUT(30), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(31), GlitchData => MIMTXBWDATA31_GlitchData, OutSignalName => "MIMTXBWDATA(31)", OutTemp => MIMTXBWDATA_OUT(31), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(31), GlitchData => MIMTXBWDATA31_GlitchData, OutSignalName => "MIMTXBWDATA(31)", OutTemp => MIMTXBWDATA_OUT(31), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(32), GlitchData => MIMTXBWDATA32_GlitchData, OutSignalName => "MIMTXBWDATA(32)", OutTemp => MIMTXBWDATA_OUT(32), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(32), GlitchData => MIMTXBWDATA32_GlitchData, OutSignalName => "MIMTXBWDATA(32)", OutTemp => MIMTXBWDATA_OUT(32), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(33), GlitchData => MIMTXBWDATA33_GlitchData, OutSignalName => "MIMTXBWDATA(33)", OutTemp => MIMTXBWDATA_OUT(33), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(33), GlitchData => MIMTXBWDATA33_GlitchData, OutSignalName => "MIMTXBWDATA(33)", OutTemp => MIMTXBWDATA_OUT(33), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(34), GlitchData => MIMTXBWDATA34_GlitchData, OutSignalName => "MIMTXBWDATA(34)", OutTemp => MIMTXBWDATA_OUT(34), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(34), GlitchData => MIMTXBWDATA34_GlitchData, OutSignalName => "MIMTXBWDATA(34)", OutTemp => MIMTXBWDATA_OUT(34), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(35), GlitchData => MIMTXBWDATA35_GlitchData, OutSignalName => "MIMTXBWDATA(35)", OutTemp => MIMTXBWDATA_OUT(35), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(35), GlitchData => MIMTXBWDATA35_GlitchData, OutSignalName => "MIMTXBWDATA(35)", OutTemp => MIMTXBWDATA_OUT(35), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(36), GlitchData => MIMTXBWDATA36_GlitchData, OutSignalName => "MIMTXBWDATA(36)", OutTemp => MIMTXBWDATA_OUT(36), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(36), GlitchData => MIMTXBWDATA36_GlitchData, OutSignalName => "MIMTXBWDATA(36)", OutTemp => MIMTXBWDATA_OUT(36), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(37), GlitchData => MIMTXBWDATA37_GlitchData, OutSignalName => "MIMTXBWDATA(37)", OutTemp => MIMTXBWDATA_OUT(37), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(37), GlitchData => MIMTXBWDATA37_GlitchData, OutSignalName => "MIMTXBWDATA(37)", OutTemp => MIMTXBWDATA_OUT(37), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(38), GlitchData => MIMTXBWDATA38_GlitchData, OutSignalName => "MIMTXBWDATA(38)", OutTemp => MIMTXBWDATA_OUT(38), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(38), GlitchData => MIMTXBWDATA38_GlitchData, OutSignalName => "MIMTXBWDATA(38)", OutTemp => MIMTXBWDATA_OUT(38), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(39), GlitchData => MIMTXBWDATA39_GlitchData, OutSignalName => "MIMTXBWDATA(39)", OutTemp => MIMTXBWDATA_OUT(39), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(39), GlitchData => MIMTXBWDATA39_GlitchData, OutSignalName => "MIMTXBWDATA(39)", OutTemp => MIMTXBWDATA_OUT(39), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(40), GlitchData => MIMTXBWDATA40_GlitchData, OutSignalName => "MIMTXBWDATA(40)", OutTemp => MIMTXBWDATA_OUT(40), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(40), GlitchData => MIMTXBWDATA40_GlitchData, OutSignalName => "MIMTXBWDATA(40)", OutTemp => MIMTXBWDATA_OUT(40), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(41), GlitchData => MIMTXBWDATA41_GlitchData, OutSignalName => "MIMTXBWDATA(41)", OutTemp => MIMTXBWDATA_OUT(41), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(41), GlitchData => MIMTXBWDATA41_GlitchData, OutSignalName => "MIMTXBWDATA(41)", OutTemp => MIMTXBWDATA_OUT(41), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(42), GlitchData => MIMTXBWDATA42_GlitchData, OutSignalName => "MIMTXBWDATA(42)", OutTemp => MIMTXBWDATA_OUT(42), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(42), GlitchData => MIMTXBWDATA42_GlitchData, OutSignalName => "MIMTXBWDATA(42)", OutTemp => MIMTXBWDATA_OUT(42), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(43), GlitchData => MIMTXBWDATA43_GlitchData, OutSignalName => "MIMTXBWDATA(43)", OutTemp => MIMTXBWDATA_OUT(43), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(43), GlitchData => MIMTXBWDATA43_GlitchData, OutSignalName => "MIMTXBWDATA(43)", OutTemp => MIMTXBWDATA_OUT(43), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(44), GlitchData => MIMTXBWDATA44_GlitchData, OutSignalName => "MIMTXBWDATA(44)", OutTemp => MIMTXBWDATA_OUT(44), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(44), GlitchData => MIMTXBWDATA44_GlitchData, OutSignalName => "MIMTXBWDATA(44)", OutTemp => MIMTXBWDATA_OUT(44), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(45), GlitchData => MIMTXBWDATA45_GlitchData, OutSignalName => "MIMTXBWDATA(45)", OutTemp => MIMTXBWDATA_OUT(45), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(45), GlitchData => MIMTXBWDATA45_GlitchData, OutSignalName => "MIMTXBWDATA(45)", OutTemp => MIMTXBWDATA_OUT(45), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(46), GlitchData => MIMTXBWDATA46_GlitchData, OutSignalName => "MIMTXBWDATA(46)", OutTemp => MIMTXBWDATA_OUT(46), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(46), GlitchData => MIMTXBWDATA46_GlitchData, OutSignalName => "MIMTXBWDATA(46)", OutTemp => MIMTXBWDATA_OUT(46), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(47), GlitchData => MIMTXBWDATA47_GlitchData, OutSignalName => "MIMTXBWDATA(47)", OutTemp => MIMTXBWDATA_OUT(47), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(47), GlitchData => MIMTXBWDATA47_GlitchData, OutSignalName => "MIMTXBWDATA(47)", OutTemp => MIMTXBWDATA_OUT(47), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(48), GlitchData => MIMTXBWDATA48_GlitchData, OutSignalName => "MIMTXBWDATA(48)", OutTemp => MIMTXBWDATA_OUT(48), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(48), GlitchData => MIMTXBWDATA48_GlitchData, OutSignalName => "MIMTXBWDATA(48)", OutTemp => MIMTXBWDATA_OUT(48), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(49), GlitchData => MIMTXBWDATA49_GlitchData, OutSignalName => "MIMTXBWDATA(49)", OutTemp => MIMTXBWDATA_OUT(49), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(49), GlitchData => MIMTXBWDATA49_GlitchData, OutSignalName => "MIMTXBWDATA(49)", OutTemp => MIMTXBWDATA_OUT(49), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(50), GlitchData => MIMTXBWDATA50_GlitchData, OutSignalName => "MIMTXBWDATA(50)", OutTemp => MIMTXBWDATA_OUT(50), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(50), GlitchData => MIMTXBWDATA50_GlitchData, OutSignalName => "MIMTXBWDATA(50)", OutTemp => MIMTXBWDATA_OUT(50), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(51), GlitchData => MIMTXBWDATA51_GlitchData, OutSignalName => "MIMTXBWDATA(51)", OutTemp => MIMTXBWDATA_OUT(51), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(51), GlitchData => MIMTXBWDATA51_GlitchData, OutSignalName => "MIMTXBWDATA(51)", OutTemp => MIMTXBWDATA_OUT(51), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(52), GlitchData => MIMTXBWDATA52_GlitchData, OutSignalName => "MIMTXBWDATA(52)", OutTemp => MIMTXBWDATA_OUT(52), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(52), GlitchData => MIMTXBWDATA52_GlitchData, OutSignalName => "MIMTXBWDATA(52)", OutTemp => MIMTXBWDATA_OUT(52), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(53), GlitchData => MIMTXBWDATA53_GlitchData, OutSignalName => "MIMTXBWDATA(53)", OutTemp => MIMTXBWDATA_OUT(53), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(53), GlitchData => MIMTXBWDATA53_GlitchData, OutSignalName => "MIMTXBWDATA(53)", OutTemp => MIMTXBWDATA_OUT(53), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(54), GlitchData => MIMTXBWDATA54_GlitchData, OutSignalName => "MIMTXBWDATA(54)", OutTemp => MIMTXBWDATA_OUT(54), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(54), GlitchData => MIMTXBWDATA54_GlitchData, OutSignalName => "MIMTXBWDATA(54)", OutTemp => MIMTXBWDATA_OUT(54), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(55), GlitchData => MIMTXBWDATA55_GlitchData, OutSignalName => "MIMTXBWDATA(55)", OutTemp => MIMTXBWDATA_OUT(55), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(55), GlitchData => MIMTXBWDATA55_GlitchData, OutSignalName => "MIMTXBWDATA(55)", OutTemp => MIMTXBWDATA_OUT(55), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(56), GlitchData => MIMTXBWDATA56_GlitchData, OutSignalName => "MIMTXBWDATA(56)", OutTemp => MIMTXBWDATA_OUT(56), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(56), GlitchData => MIMTXBWDATA56_GlitchData, OutSignalName => "MIMTXBWDATA(56)", OutTemp => MIMTXBWDATA_OUT(56), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(57), GlitchData => MIMTXBWDATA57_GlitchData, OutSignalName => "MIMTXBWDATA(57)", OutTemp => MIMTXBWDATA_OUT(57), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(57), GlitchData => MIMTXBWDATA57_GlitchData, OutSignalName => "MIMTXBWDATA(57)", OutTemp => MIMTXBWDATA_OUT(57), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(58), GlitchData => MIMTXBWDATA58_GlitchData, OutSignalName => "MIMTXBWDATA(58)", OutTemp => MIMTXBWDATA_OUT(58), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(58), GlitchData => MIMTXBWDATA58_GlitchData, OutSignalName => "MIMTXBWDATA(58)", OutTemp => MIMTXBWDATA_OUT(58), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(59), GlitchData => MIMTXBWDATA59_GlitchData, OutSignalName => "MIMTXBWDATA(59)", OutTemp => MIMTXBWDATA_OUT(59), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(59), GlitchData => MIMTXBWDATA59_GlitchData, OutSignalName => "MIMTXBWDATA(59)", OutTemp => MIMTXBWDATA_OUT(59), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(60), GlitchData => MIMTXBWDATA60_GlitchData, OutSignalName => "MIMTXBWDATA(60)", OutTemp => MIMTXBWDATA_OUT(60), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(60), GlitchData => MIMTXBWDATA60_GlitchData, OutSignalName => "MIMTXBWDATA(60)", OutTemp => MIMTXBWDATA_OUT(60), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(61), GlitchData => MIMTXBWDATA61_GlitchData, OutSignalName => "MIMTXBWDATA(61)", OutTemp => MIMTXBWDATA_OUT(61), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(61), GlitchData => MIMTXBWDATA61_GlitchData, OutSignalName => "MIMTXBWDATA(61)", OutTemp => MIMTXBWDATA_OUT(61), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(62), GlitchData => MIMTXBWDATA62_GlitchData, OutSignalName => "MIMTXBWDATA(62)", OutTemp => MIMTXBWDATA_OUT(62), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(62), GlitchData => MIMTXBWDATA62_GlitchData, OutSignalName => "MIMTXBWDATA(62)", OutTemp => MIMTXBWDATA_OUT(62), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(63), GlitchData => MIMTXBWDATA63_GlitchData, OutSignalName => "MIMTXBWDATA(63)", OutTemp => MIMTXBWDATA_OUT(63), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWDATA(63), GlitchData => MIMTXBWDATA63_GlitchData, OutSignalName => "MIMTXBWDATA(63)", OutTemp => MIMTXBWDATA_OUT(63), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(0), GlitchData => MIMTXBWADD0_GlitchData, OutSignalName => "MIMTXBWADD(0)", OutTemp => MIMTXBWADD_OUT(0), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(0), GlitchData => MIMTXBWADD0_GlitchData, OutSignalName => "MIMTXBWADD(0)", OutTemp => MIMTXBWADD_OUT(0), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(1), GlitchData => MIMTXBWADD1_GlitchData, OutSignalName => "MIMTXBWADD(1)", OutTemp => MIMTXBWADD_OUT(1), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(1), GlitchData => MIMTXBWADD1_GlitchData, OutSignalName => "MIMTXBWADD(1)", OutTemp => MIMTXBWADD_OUT(1), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(2), GlitchData => MIMTXBWADD2_GlitchData, OutSignalName => "MIMTXBWADD(2)", OutTemp => MIMTXBWADD_OUT(2), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(2), GlitchData => MIMTXBWADD2_GlitchData, OutSignalName => "MIMTXBWADD(2)", OutTemp => MIMTXBWADD_OUT(2), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(3), GlitchData => MIMTXBWADD3_GlitchData, OutSignalName => "MIMTXBWADD(3)", OutTemp => MIMTXBWADD_OUT(3), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(3), GlitchData => MIMTXBWADD3_GlitchData, OutSignalName => "MIMTXBWADD(3)", OutTemp => MIMTXBWADD_OUT(3), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(4), GlitchData => MIMTXBWADD4_GlitchData, OutSignalName => "MIMTXBWADD(4)", OutTemp => MIMTXBWADD_OUT(4), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(4), GlitchData => MIMTXBWADD4_GlitchData, OutSignalName => "MIMTXBWADD(4)", OutTemp => MIMTXBWADD_OUT(4), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(5), GlitchData => MIMTXBWADD5_GlitchData, OutSignalName => "MIMTXBWADD(5)", OutTemp => MIMTXBWADD_OUT(5), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(5), GlitchData => MIMTXBWADD5_GlitchData, OutSignalName => "MIMTXBWADD(5)", OutTemp => MIMTXBWADD_OUT(5), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(6), GlitchData => MIMTXBWADD6_GlitchData, OutSignalName => "MIMTXBWADD(6)", OutTemp => MIMTXBWADD_OUT(6), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(6), GlitchData => MIMTXBWADD6_GlitchData, OutSignalName => "MIMTXBWADD(6)", OutTemp => MIMTXBWADD_OUT(6), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(7), GlitchData => MIMTXBWADD7_GlitchData, OutSignalName => "MIMTXBWADD(7)", OutTemp => MIMTXBWADD_OUT(7), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(7), GlitchData => MIMTXBWADD7_GlitchData, OutSignalName => "MIMTXBWADD(7)", OutTemp => MIMTXBWADD_OUT(7), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(8), GlitchData => MIMTXBWADD8_GlitchData, OutSignalName => "MIMTXBWADD(8)", OutTemp => MIMTXBWADD_OUT(8), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(8), GlitchData => MIMTXBWADD8_GlitchData, OutSignalName => "MIMTXBWADD(8)", OutTemp => MIMTXBWADD_OUT(8), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(9), GlitchData => MIMTXBWADD9_GlitchData, OutSignalName => "MIMTXBWADD(9)", OutTemp => MIMTXBWADD_OUT(9), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(9), GlitchData => MIMTXBWADD9_GlitchData, OutSignalName => "MIMTXBWADD(9)", OutTemp => MIMTXBWADD_OUT(9), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(10), GlitchData => MIMTXBWADD10_GlitchData, OutSignalName => "MIMTXBWADD(10)", OutTemp => MIMTXBWADD_OUT(10), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(10), GlitchData => MIMTXBWADD10_GlitchData, OutSignalName => "MIMTXBWADD(10)", OutTemp => MIMTXBWADD_OUT(10), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(11), GlitchData => MIMTXBWADD11_GlitchData, OutSignalName => "MIMTXBWADD(11)", OutTemp => MIMTXBWADD_OUT(11), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(11), GlitchData => MIMTXBWADD11_GlitchData, OutSignalName => "MIMTXBWADD(11)", OutTemp => MIMTXBWADD_OUT(11), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(12), GlitchData => MIMTXBWADD12_GlitchData, OutSignalName => "MIMTXBWADD(12)", OutTemp => MIMTXBWADD_OUT(12), Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWADD(12), GlitchData => MIMTXBWADD12_GlitchData, OutSignalName => "MIMTXBWADD(12)", OutTemp => MIMTXBWADD_OUT(12), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(0), GlitchData => MIMTXBRADD0_GlitchData, OutSignalName => "MIMTXBRADD(0)", OutTemp => MIMTXBRADD_OUT(0), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(1), GlitchData => MIMTXBRADD1_GlitchData, OutSignalName => "MIMTXBRADD(1)", OutTemp => MIMTXBRADD_OUT(1), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(2), GlitchData => MIMTXBRADD2_GlitchData, OutSignalName => "MIMTXBRADD(2)", OutTemp => MIMTXBRADD_OUT(2), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(3), GlitchData => MIMTXBRADD3_GlitchData, OutSignalName => "MIMTXBRADD(3)", OutTemp => MIMTXBRADD_OUT(3), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(4), GlitchData => MIMTXBRADD4_GlitchData, OutSignalName => "MIMTXBRADD(4)", OutTemp => MIMTXBRADD_OUT(4), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(5), GlitchData => MIMTXBRADD5_GlitchData, OutSignalName => "MIMTXBRADD(5)", OutTemp => MIMTXBRADD_OUT(5), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(6), GlitchData => MIMTXBRADD6_GlitchData, OutSignalName => "MIMTXBRADD(6)", OutTemp => MIMTXBRADD_OUT(6), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(7), GlitchData => MIMTXBRADD7_GlitchData, OutSignalName => "MIMTXBRADD(7)", OutTemp => MIMTXBRADD_OUT(7), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(8), GlitchData => MIMTXBRADD8_GlitchData, OutSignalName => "MIMTXBRADD(8)", OutTemp => MIMTXBRADD_OUT(8), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(9), GlitchData => MIMTXBRADD9_GlitchData, OutSignalName => "MIMTXBRADD(9)", OutTemp => MIMTXBRADD_OUT(9), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(10), GlitchData => MIMTXBRADD10_GlitchData, OutSignalName => "MIMTXBRADD(10)", OutTemp => MIMTXBRADD_OUT(10), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(11), GlitchData => MIMTXBRADD11_GlitchData, OutSignalName => "MIMTXBRADD(11)", OutTemp => MIMTXBRADD_OUT(11), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBRADD(12), GlitchData => MIMTXBRADD12_GlitchData, OutSignalName => "MIMTXBRADD(12)", OutTemp => MIMTXBRADD_OUT(12), Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWEN, GlitchData => MIMTXBWEN_GlitchData, OutSignalName => "MIMTXBWEN", OutTemp => MIMTXBWEN_OUT, Paths => (0 => (CRMUSERCLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBWEN, GlitchData => MIMTXBWEN_GlitchData, OutSignalName => "MIMTXBWEN", OutTemp => MIMTXBWEN_OUT, Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMTXBREN, GlitchData => MIMTXBREN_GlitchData, OutSignalName => "MIMTXBREN", OutTemp => MIMTXBREN_OUT, Paths => (0 => (CRMCORECLKTXO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(0), GlitchData => MIMDLLBWDATA0_GlitchData, OutSignalName => "MIMDLLBWDATA(0)", OutTemp => MIMDLLBWDATA_OUT(0), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(1), GlitchData => MIMDLLBWDATA1_GlitchData, OutSignalName => "MIMDLLBWDATA(1)", OutTemp => MIMDLLBWDATA_OUT(1), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(2), GlitchData => MIMDLLBWDATA2_GlitchData, OutSignalName => "MIMDLLBWDATA(2)", OutTemp => MIMDLLBWDATA_OUT(2), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(3), GlitchData => MIMDLLBWDATA3_GlitchData, OutSignalName => "MIMDLLBWDATA(3)", OutTemp => MIMDLLBWDATA_OUT(3), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(4), GlitchData => MIMDLLBWDATA4_GlitchData, OutSignalName => "MIMDLLBWDATA(4)", OutTemp => MIMDLLBWDATA_OUT(4), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(5), GlitchData => MIMDLLBWDATA5_GlitchData, OutSignalName => "MIMDLLBWDATA(5)", OutTemp => MIMDLLBWDATA_OUT(5), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(6), GlitchData => MIMDLLBWDATA6_GlitchData, OutSignalName => "MIMDLLBWDATA(6)", OutTemp => MIMDLLBWDATA_OUT(6), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(7), GlitchData => MIMDLLBWDATA7_GlitchData, OutSignalName => "MIMDLLBWDATA(7)", OutTemp => MIMDLLBWDATA_OUT(7), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(8), GlitchData => MIMDLLBWDATA8_GlitchData, OutSignalName => "MIMDLLBWDATA(8)", OutTemp => MIMDLLBWDATA_OUT(8), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(9), GlitchData => MIMDLLBWDATA9_GlitchData, OutSignalName => "MIMDLLBWDATA(9)", OutTemp => MIMDLLBWDATA_OUT(9), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(10), GlitchData => MIMDLLBWDATA10_GlitchData, OutSignalName => "MIMDLLBWDATA(10)", OutTemp => MIMDLLBWDATA_OUT(10), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(11), GlitchData => MIMDLLBWDATA11_GlitchData, OutSignalName => "MIMDLLBWDATA(11)", OutTemp => MIMDLLBWDATA_OUT(11), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(12), GlitchData => MIMDLLBWDATA12_GlitchData, OutSignalName => "MIMDLLBWDATA(12)", OutTemp => MIMDLLBWDATA_OUT(12), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(13), GlitchData => MIMDLLBWDATA13_GlitchData, OutSignalName => "MIMDLLBWDATA(13)", OutTemp => MIMDLLBWDATA_OUT(13), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(14), GlitchData => MIMDLLBWDATA14_GlitchData, OutSignalName => "MIMDLLBWDATA(14)", OutTemp => MIMDLLBWDATA_OUT(14), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(15), GlitchData => MIMDLLBWDATA15_GlitchData, OutSignalName => "MIMDLLBWDATA(15)", OutTemp => MIMDLLBWDATA_OUT(15), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(16), GlitchData => MIMDLLBWDATA16_GlitchData, OutSignalName => "MIMDLLBWDATA(16)", OutTemp => MIMDLLBWDATA_OUT(16), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(17), GlitchData => MIMDLLBWDATA17_GlitchData, OutSignalName => "MIMDLLBWDATA(17)", OutTemp => MIMDLLBWDATA_OUT(17), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(18), GlitchData => MIMDLLBWDATA18_GlitchData, OutSignalName => "MIMDLLBWDATA(18)", OutTemp => MIMDLLBWDATA_OUT(18), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(19), GlitchData => MIMDLLBWDATA19_GlitchData, OutSignalName => "MIMDLLBWDATA(19)", OutTemp => MIMDLLBWDATA_OUT(19), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(20), GlitchData => MIMDLLBWDATA20_GlitchData, OutSignalName => "MIMDLLBWDATA(20)", OutTemp => MIMDLLBWDATA_OUT(20), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(21), GlitchData => MIMDLLBWDATA21_GlitchData, OutSignalName => "MIMDLLBWDATA(21)", OutTemp => MIMDLLBWDATA_OUT(21), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(22), GlitchData => MIMDLLBWDATA22_GlitchData, OutSignalName => "MIMDLLBWDATA(22)", OutTemp => MIMDLLBWDATA_OUT(22), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(23), GlitchData => MIMDLLBWDATA23_GlitchData, OutSignalName => "MIMDLLBWDATA(23)", OutTemp => MIMDLLBWDATA_OUT(23), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(24), GlitchData => MIMDLLBWDATA24_GlitchData, OutSignalName => "MIMDLLBWDATA(24)", OutTemp => MIMDLLBWDATA_OUT(24), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(25), GlitchData => MIMDLLBWDATA25_GlitchData, OutSignalName => "MIMDLLBWDATA(25)", OutTemp => MIMDLLBWDATA_OUT(25), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(26), GlitchData => MIMDLLBWDATA26_GlitchData, OutSignalName => "MIMDLLBWDATA(26)", OutTemp => MIMDLLBWDATA_OUT(26), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(27), GlitchData => MIMDLLBWDATA27_GlitchData, OutSignalName => "MIMDLLBWDATA(27)", OutTemp => MIMDLLBWDATA_OUT(27), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(28), GlitchData => MIMDLLBWDATA28_GlitchData, OutSignalName => "MIMDLLBWDATA(28)", OutTemp => MIMDLLBWDATA_OUT(28), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(29), GlitchData => MIMDLLBWDATA29_GlitchData, OutSignalName => "MIMDLLBWDATA(29)", OutTemp => MIMDLLBWDATA_OUT(29), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(30), GlitchData => MIMDLLBWDATA30_GlitchData, OutSignalName => "MIMDLLBWDATA(30)", OutTemp => MIMDLLBWDATA_OUT(30), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(31), GlitchData => MIMDLLBWDATA31_GlitchData, OutSignalName => "MIMDLLBWDATA(31)", OutTemp => MIMDLLBWDATA_OUT(31), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(32), GlitchData => MIMDLLBWDATA32_GlitchData, OutSignalName => "MIMDLLBWDATA(32)", OutTemp => MIMDLLBWDATA_OUT(32), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(33), GlitchData => MIMDLLBWDATA33_GlitchData, OutSignalName => "MIMDLLBWDATA(33)", OutTemp => MIMDLLBWDATA_OUT(33), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(34), GlitchData => MIMDLLBWDATA34_GlitchData, OutSignalName => "MIMDLLBWDATA(34)", OutTemp => MIMDLLBWDATA_OUT(34), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(35), GlitchData => MIMDLLBWDATA35_GlitchData, OutSignalName => "MIMDLLBWDATA(35)", OutTemp => MIMDLLBWDATA_OUT(35), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(36), GlitchData => MIMDLLBWDATA36_GlitchData, OutSignalName => "MIMDLLBWDATA(36)", OutTemp => MIMDLLBWDATA_OUT(36), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(37), GlitchData => MIMDLLBWDATA37_GlitchData, OutSignalName => "MIMDLLBWDATA(37)", OutTemp => MIMDLLBWDATA_OUT(37), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(38), GlitchData => MIMDLLBWDATA38_GlitchData, OutSignalName => "MIMDLLBWDATA(38)", OutTemp => MIMDLLBWDATA_OUT(38), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(39), GlitchData => MIMDLLBWDATA39_GlitchData, OutSignalName => "MIMDLLBWDATA(39)", OutTemp => MIMDLLBWDATA_OUT(39), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(40), GlitchData => MIMDLLBWDATA40_GlitchData, OutSignalName => "MIMDLLBWDATA(40)", OutTemp => MIMDLLBWDATA_OUT(40), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(41), GlitchData => MIMDLLBWDATA41_GlitchData, OutSignalName => "MIMDLLBWDATA(41)", OutTemp => MIMDLLBWDATA_OUT(41), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(42), GlitchData => MIMDLLBWDATA42_GlitchData, OutSignalName => "MIMDLLBWDATA(42)", OutTemp => MIMDLLBWDATA_OUT(42), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(43), GlitchData => MIMDLLBWDATA43_GlitchData, OutSignalName => "MIMDLLBWDATA(43)", OutTemp => MIMDLLBWDATA_OUT(43), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(44), GlitchData => MIMDLLBWDATA44_GlitchData, OutSignalName => "MIMDLLBWDATA(44)", OutTemp => MIMDLLBWDATA_OUT(44), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(45), GlitchData => MIMDLLBWDATA45_GlitchData, OutSignalName => "MIMDLLBWDATA(45)", OutTemp => MIMDLLBWDATA_OUT(45), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(46), GlitchData => MIMDLLBWDATA46_GlitchData, OutSignalName => "MIMDLLBWDATA(46)", OutTemp => MIMDLLBWDATA_OUT(46), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(47), GlitchData => MIMDLLBWDATA47_GlitchData, OutSignalName => "MIMDLLBWDATA(47)", OutTemp => MIMDLLBWDATA_OUT(47), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(48), GlitchData => MIMDLLBWDATA48_GlitchData, OutSignalName => "MIMDLLBWDATA(48)", OutTemp => MIMDLLBWDATA_OUT(48), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(49), GlitchData => MIMDLLBWDATA49_GlitchData, OutSignalName => "MIMDLLBWDATA(49)", OutTemp => MIMDLLBWDATA_OUT(49), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(50), GlitchData => MIMDLLBWDATA50_GlitchData, OutSignalName => "MIMDLLBWDATA(50)", OutTemp => MIMDLLBWDATA_OUT(50), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(51), GlitchData => MIMDLLBWDATA51_GlitchData, OutSignalName => "MIMDLLBWDATA(51)", OutTemp => MIMDLLBWDATA_OUT(51), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(52), GlitchData => MIMDLLBWDATA52_GlitchData, OutSignalName => "MIMDLLBWDATA(52)", OutTemp => MIMDLLBWDATA_OUT(52), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(53), GlitchData => MIMDLLBWDATA53_GlitchData, OutSignalName => "MIMDLLBWDATA(53)", OutTemp => MIMDLLBWDATA_OUT(53), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(54), GlitchData => MIMDLLBWDATA54_GlitchData, OutSignalName => "MIMDLLBWDATA(54)", OutTemp => MIMDLLBWDATA_OUT(54), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(55), GlitchData => MIMDLLBWDATA55_GlitchData, OutSignalName => "MIMDLLBWDATA(55)", OutTemp => MIMDLLBWDATA_OUT(55), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(56), GlitchData => MIMDLLBWDATA56_GlitchData, OutSignalName => "MIMDLLBWDATA(56)", OutTemp => MIMDLLBWDATA_OUT(56), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(57), GlitchData => MIMDLLBWDATA57_GlitchData, OutSignalName => "MIMDLLBWDATA(57)", OutTemp => MIMDLLBWDATA_OUT(57), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(58), GlitchData => MIMDLLBWDATA58_GlitchData, OutSignalName => "MIMDLLBWDATA(58)", OutTemp => MIMDLLBWDATA_OUT(58), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(59), GlitchData => MIMDLLBWDATA59_GlitchData, OutSignalName => "MIMDLLBWDATA(59)", OutTemp => MIMDLLBWDATA_OUT(59), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(60), GlitchData => MIMDLLBWDATA60_GlitchData, OutSignalName => "MIMDLLBWDATA(60)", OutTemp => MIMDLLBWDATA_OUT(60), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(61), GlitchData => MIMDLLBWDATA61_GlitchData, OutSignalName => "MIMDLLBWDATA(61)", OutTemp => MIMDLLBWDATA_OUT(61), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(62), GlitchData => MIMDLLBWDATA62_GlitchData, OutSignalName => "MIMDLLBWDATA(62)", OutTemp => MIMDLLBWDATA_OUT(62), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWDATA(63), GlitchData => MIMDLLBWDATA63_GlitchData, OutSignalName => "MIMDLLBWDATA(63)", OutTemp => MIMDLLBWDATA_OUT(63), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(0), GlitchData => MIMDLLBWADD0_GlitchData, OutSignalName => "MIMDLLBWADD(0)", OutTemp => MIMDLLBWADD_OUT(0), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(1), GlitchData => MIMDLLBWADD1_GlitchData, OutSignalName => "MIMDLLBWADD(1)", OutTemp => MIMDLLBWADD_OUT(1), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(2), GlitchData => MIMDLLBWADD2_GlitchData, OutSignalName => "MIMDLLBWADD(2)", OutTemp => MIMDLLBWADD_OUT(2), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(3), GlitchData => MIMDLLBWADD3_GlitchData, OutSignalName => "MIMDLLBWADD(3)", OutTemp => MIMDLLBWADD_OUT(3), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(4), GlitchData => MIMDLLBWADD4_GlitchData, OutSignalName => "MIMDLLBWADD(4)", OutTemp => MIMDLLBWADD_OUT(4), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(5), GlitchData => MIMDLLBWADD5_GlitchData, OutSignalName => "MIMDLLBWADD(5)", OutTemp => MIMDLLBWADD_OUT(5), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(6), GlitchData => MIMDLLBWADD6_GlitchData, OutSignalName => "MIMDLLBWADD(6)", OutTemp => MIMDLLBWADD_OUT(6), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(7), GlitchData => MIMDLLBWADD7_GlitchData, OutSignalName => "MIMDLLBWADD(7)", OutTemp => MIMDLLBWADD_OUT(7), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(8), GlitchData => MIMDLLBWADD8_GlitchData, OutSignalName => "MIMDLLBWADD(8)", OutTemp => MIMDLLBWADD_OUT(8), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(9), GlitchData => MIMDLLBWADD9_GlitchData, OutSignalName => "MIMDLLBWADD(9)", OutTemp => MIMDLLBWADD_OUT(9), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(10), GlitchData => MIMDLLBWADD10_GlitchData, OutSignalName => "MIMDLLBWADD(10)", OutTemp => MIMDLLBWADD_OUT(10), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWADD(11), GlitchData => MIMDLLBWADD11_GlitchData, OutSignalName => "MIMDLLBWADD(11)", OutTemp => MIMDLLBWADD_OUT(11), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(0), GlitchData => MIMDLLBRADD0_GlitchData, OutSignalName => "MIMDLLBRADD(0)", OutTemp => MIMDLLBRADD_OUT(0), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(1), GlitchData => MIMDLLBRADD1_GlitchData, OutSignalName => "MIMDLLBRADD(1)", OutTemp => MIMDLLBRADD_OUT(1), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(2), GlitchData => MIMDLLBRADD2_GlitchData, OutSignalName => "MIMDLLBRADD(2)", OutTemp => MIMDLLBRADD_OUT(2), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(3), GlitchData => MIMDLLBRADD3_GlitchData, OutSignalName => "MIMDLLBRADD(3)", OutTemp => MIMDLLBRADD_OUT(3), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(4), GlitchData => MIMDLLBRADD4_GlitchData, OutSignalName => "MIMDLLBRADD(4)", OutTemp => MIMDLLBRADD_OUT(4), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(5), GlitchData => MIMDLLBRADD5_GlitchData, OutSignalName => "MIMDLLBRADD(5)", OutTemp => MIMDLLBRADD_OUT(5), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(6), GlitchData => MIMDLLBRADD6_GlitchData, OutSignalName => "MIMDLLBRADD(6)", OutTemp => MIMDLLBRADD_OUT(6), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(7), GlitchData => MIMDLLBRADD7_GlitchData, OutSignalName => "MIMDLLBRADD(7)", OutTemp => MIMDLLBRADD_OUT(7), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(8), GlitchData => MIMDLLBRADD8_GlitchData, OutSignalName => "MIMDLLBRADD(8)", OutTemp => MIMDLLBRADD_OUT(8), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(9), GlitchData => MIMDLLBRADD9_GlitchData, OutSignalName => "MIMDLLBRADD(9)", OutTemp => MIMDLLBRADD_OUT(9), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(10), GlitchData => MIMDLLBRADD10_GlitchData, OutSignalName => "MIMDLLBRADD(10)", OutTemp => MIMDLLBRADD_OUT(10), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBRADD(11), GlitchData => MIMDLLBRADD11_GlitchData, OutSignalName => "MIMDLLBRADD(11)", OutTemp => MIMDLLBRADD_OUT(11), Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBWEN, GlitchData => MIMDLLBWEN_GlitchData, OutSignalName => "MIMDLLBWEN", OutTemp => MIMDLLBWEN_OUT, Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMDLLBREN, GlitchData => MIMDLLBREN_GlitchData, OutSignalName => "MIMDLLBREN", OutTemp => MIMDLLBREN_OUT, Paths => (0 => (CRMCORECLKDLO_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CRMRXHOTRESETN, GlitchData => CRMRXHOTRESETN_GlitchData, OutSignalName => "CRMRXHOTRESETN", OutTemp => CRMRXHOTRESETN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CRMDOHOTRESETN, GlitchData => CRMDOHOTRESETN_GlitchData, OutSignalName => "CRMDOHOTRESETN", OutTemp => CRMDOHOTRESETN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => CRMPWRSOFTRESETN, GlitchData => CRMPWRSOFTRESETN_GlitchData, OutSignalName => "CRMPWRSOFTRESETN", OutTemp => CRMPWRSOFTRESETN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(0), GlitchData => LLKTCSTATUS0_GlitchData, OutSignalName => "LLKTCSTATUS(0)", OutTemp => LLKTCSTATUS_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(0), GlitchData => LLKTCSTATUS0_GlitchData, OutSignalName => "LLKTCSTATUS(0)", OutTemp => LLKTCSTATUS_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(1), GlitchData => LLKTCSTATUS1_GlitchData, OutSignalName => "LLKTCSTATUS(1)", OutTemp => LLKTCSTATUS_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(1), GlitchData => LLKTCSTATUS1_GlitchData, OutSignalName => "LLKTCSTATUS(1)", OutTemp => LLKTCSTATUS_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(2), GlitchData => LLKTCSTATUS2_GlitchData, OutSignalName => "LLKTCSTATUS(2)", OutTemp => LLKTCSTATUS_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(2), GlitchData => LLKTCSTATUS2_GlitchData, OutSignalName => "LLKTCSTATUS(2)", OutTemp => LLKTCSTATUS_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(3), GlitchData => LLKTCSTATUS3_GlitchData, OutSignalName => "LLKTCSTATUS(3)", OutTemp => LLKTCSTATUS_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(3), GlitchData => LLKTCSTATUS3_GlitchData, OutSignalName => "LLKTCSTATUS(3)", OutTemp => LLKTCSTATUS_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(4), GlitchData => LLKTCSTATUS4_GlitchData, OutSignalName => "LLKTCSTATUS(4)", OutTemp => LLKTCSTATUS_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(4), GlitchData => LLKTCSTATUS4_GlitchData, OutSignalName => "LLKTCSTATUS(4)", OutTemp => LLKTCSTATUS_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(5), GlitchData => LLKTCSTATUS5_GlitchData, OutSignalName => "LLKTCSTATUS(5)", OutTemp => LLKTCSTATUS_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(5), GlitchData => LLKTCSTATUS5_GlitchData, OutSignalName => "LLKTCSTATUS(5)", OutTemp => LLKTCSTATUS_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(6), GlitchData => LLKTCSTATUS6_GlitchData, OutSignalName => "LLKTCSTATUS(6)", OutTemp => LLKTCSTATUS_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(6), GlitchData => LLKTCSTATUS6_GlitchData, OutSignalName => "LLKTCSTATUS(6)", OutTemp => LLKTCSTATUS_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(7), GlitchData => LLKTCSTATUS7_GlitchData, OutSignalName => "LLKTCSTATUS(7)", OutTemp => LLKTCSTATUS_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTCSTATUS(7), GlitchData => LLKTCSTATUS7_GlitchData, OutSignalName => "LLKTCSTATUS(7)", OutTemp => LLKTCSTATUS_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXDSTRDYN, GlitchData => LLKTXDSTRDYN_GlitchData, OutSignalName => "LLKTXDSTRDYN", OutTemp => LLKTXDSTRDYN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXDSTRDYN, GlitchData => LLKTXDSTRDYN_GlitchData, OutSignalName => "LLKTXDSTRDYN", OutTemp => LLKTXDSTRDYN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(0), GlitchData => LLKTXCHANSPACE0_GlitchData, OutSignalName => "LLKTXCHANSPACE(0)", OutTemp => LLKTXCHANSPACE_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(0), GlitchData => LLKTXCHANSPACE0_GlitchData, OutSignalName => "LLKTXCHANSPACE(0)", OutTemp => LLKTXCHANSPACE_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(1), GlitchData => LLKTXCHANSPACE1_GlitchData, OutSignalName => "LLKTXCHANSPACE(1)", OutTemp => LLKTXCHANSPACE_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(1), GlitchData => LLKTXCHANSPACE1_GlitchData, OutSignalName => "LLKTXCHANSPACE(1)", OutTemp => LLKTXCHANSPACE_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(2), GlitchData => LLKTXCHANSPACE2_GlitchData, OutSignalName => "LLKTXCHANSPACE(2)", OutTemp => LLKTXCHANSPACE_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(2), GlitchData => LLKTXCHANSPACE2_GlitchData, OutSignalName => "LLKTXCHANSPACE(2)", OutTemp => LLKTXCHANSPACE_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(3), GlitchData => LLKTXCHANSPACE3_GlitchData, OutSignalName => "LLKTXCHANSPACE(3)", OutTemp => LLKTXCHANSPACE_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(3), GlitchData => LLKTXCHANSPACE3_GlitchData, OutSignalName => "LLKTXCHANSPACE(3)", OutTemp => LLKTXCHANSPACE_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(4), GlitchData => LLKTXCHANSPACE4_GlitchData, OutSignalName => "LLKTXCHANSPACE(4)", OutTemp => LLKTXCHANSPACE_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(4), GlitchData => LLKTXCHANSPACE4_GlitchData, OutSignalName => "LLKTXCHANSPACE(4)", OutTemp => LLKTXCHANSPACE_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(5), GlitchData => LLKTXCHANSPACE5_GlitchData, OutSignalName => "LLKTXCHANSPACE(5)", OutTemp => LLKTXCHANSPACE_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(5), GlitchData => LLKTXCHANSPACE5_GlitchData, OutSignalName => "LLKTXCHANSPACE(5)", OutTemp => LLKTXCHANSPACE_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(6), GlitchData => LLKTXCHANSPACE6_GlitchData, OutSignalName => "LLKTXCHANSPACE(6)", OutTemp => LLKTXCHANSPACE_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(6), GlitchData => LLKTXCHANSPACE6_GlitchData, OutSignalName => "LLKTXCHANSPACE(6)", OutTemp => LLKTXCHANSPACE_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(7), GlitchData => LLKTXCHANSPACE7_GlitchData, OutSignalName => "LLKTXCHANSPACE(7)", OutTemp => LLKTXCHANSPACE_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(7), GlitchData => LLKTXCHANSPACE7_GlitchData, OutSignalName => "LLKTXCHANSPACE(7)", OutTemp => LLKTXCHANSPACE_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(8), GlitchData => LLKTXCHANSPACE8_GlitchData, OutSignalName => "LLKTXCHANSPACE(8)", OutTemp => LLKTXCHANSPACE_OUT(8), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(8), GlitchData => LLKTXCHANSPACE8_GlitchData, OutSignalName => "LLKTXCHANSPACE(8)", OutTemp => LLKTXCHANSPACE_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(9), GlitchData => LLKTXCHANSPACE9_GlitchData, OutSignalName => "LLKTXCHANSPACE(9)", OutTemp => LLKTXCHANSPACE_OUT(9), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHANSPACE(9), GlitchData => LLKTXCHANSPACE9_GlitchData, OutSignalName => "LLKTXCHANSPACE(9)", OutTemp => LLKTXCHANSPACE_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(0), GlitchData => LLKTXCHPOSTEDREADYN0_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(0)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(0), GlitchData => LLKTXCHPOSTEDREADYN0_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(0)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(1), GlitchData => LLKTXCHPOSTEDREADYN1_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(1)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(1), GlitchData => LLKTXCHPOSTEDREADYN1_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(1)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(2), GlitchData => LLKTXCHPOSTEDREADYN2_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(2)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(2), GlitchData => LLKTXCHPOSTEDREADYN2_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(2)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(3), GlitchData => LLKTXCHPOSTEDREADYN3_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(3)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(3), GlitchData => LLKTXCHPOSTEDREADYN3_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(3)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(4), GlitchData => LLKTXCHPOSTEDREADYN4_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(4)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(4), GlitchData => LLKTXCHPOSTEDREADYN4_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(4)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(5), GlitchData => LLKTXCHPOSTEDREADYN5_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(5)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(5), GlitchData => LLKTXCHPOSTEDREADYN5_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(5)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(6), GlitchData => LLKTXCHPOSTEDREADYN6_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(6)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(6), GlitchData => LLKTXCHPOSTEDREADYN6_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(6)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(7), GlitchData => LLKTXCHPOSTEDREADYN7_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(7)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHPOSTEDREADYN(7), GlitchData => LLKTXCHPOSTEDREADYN7_GlitchData, OutSignalName => "LLKTXCHPOSTEDREADYN(7)", OutTemp => LLKTXCHPOSTEDREADYN_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(0), GlitchData => LLKTXCHNONPOSTEDREADYN0_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(0)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(0), GlitchData => LLKTXCHNONPOSTEDREADYN0_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(0)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(1), GlitchData => LLKTXCHNONPOSTEDREADYN1_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(1)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(1), GlitchData => LLKTXCHNONPOSTEDREADYN1_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(1)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(2), GlitchData => LLKTXCHNONPOSTEDREADYN2_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(2)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(2), GlitchData => LLKTXCHNONPOSTEDREADYN2_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(2)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(3), GlitchData => LLKTXCHNONPOSTEDREADYN3_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(3)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(3), GlitchData => LLKTXCHNONPOSTEDREADYN3_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(3)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(4), GlitchData => LLKTXCHNONPOSTEDREADYN4_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(4)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(4), GlitchData => LLKTXCHNONPOSTEDREADYN4_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(4)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(5), GlitchData => LLKTXCHNONPOSTEDREADYN5_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(5)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(5), GlitchData => LLKTXCHNONPOSTEDREADYN5_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(5)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(6), GlitchData => LLKTXCHNONPOSTEDREADYN6_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(6)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(6), GlitchData => LLKTXCHNONPOSTEDREADYN6_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(6)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(7), GlitchData => LLKTXCHNONPOSTEDREADYN7_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(7)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHNONPOSTEDREADYN(7), GlitchData => LLKTXCHNONPOSTEDREADYN7_GlitchData, OutSignalName => "LLKTXCHNONPOSTEDREADYN(7)", OutTemp => LLKTXCHNONPOSTEDREADYN_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(0), GlitchData => LLKTXCHCOMPLETIONREADYN0_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(0)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(0), GlitchData => LLKTXCHCOMPLETIONREADYN0_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(0)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(1), GlitchData => LLKTXCHCOMPLETIONREADYN1_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(1)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(1), GlitchData => LLKTXCHCOMPLETIONREADYN1_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(1)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(2), GlitchData => LLKTXCHCOMPLETIONREADYN2_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(2)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(2), GlitchData => LLKTXCHCOMPLETIONREADYN2_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(2)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(3), GlitchData => LLKTXCHCOMPLETIONREADYN3_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(3)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(3), GlitchData => LLKTXCHCOMPLETIONREADYN3_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(3)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(4), GlitchData => LLKTXCHCOMPLETIONREADYN4_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(4)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(4), GlitchData => LLKTXCHCOMPLETIONREADYN4_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(4)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(5), GlitchData => LLKTXCHCOMPLETIONREADYN5_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(5)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(5), GlitchData => LLKTXCHCOMPLETIONREADYN5_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(5)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(6), GlitchData => LLKTXCHCOMPLETIONREADYN6_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(6)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(6), GlitchData => LLKTXCHCOMPLETIONREADYN6_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(6)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(7), GlitchData => LLKTXCHCOMPLETIONREADYN7_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(7)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCHCOMPLETIONREADYN(7), GlitchData => LLKTXCHCOMPLETIONREADYN7_GlitchData, OutSignalName => "LLKTXCHCOMPLETIONREADYN(7)", OutTemp => LLKTXCHCOMPLETIONREADYN_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCONFIGREADYN, GlitchData => LLKTXCONFIGREADYN_GlitchData, OutSignalName => "LLKTXCONFIGREADYN", OutTemp => LLKTXCONFIGREADYN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKTXCONFIGREADYN, GlitchData => LLKTXCONFIGREADYN_GlitchData, OutSignalName => "LLKTXCONFIGREADYN", OutTemp => LLKTXCONFIGREADYN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(0), GlitchData => LLKRXDATA0_GlitchData, OutSignalName => "LLKRXDATA(0)", OutTemp => LLKRXDATA_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(0), GlitchData => LLKRXDATA0_GlitchData, OutSignalName => "LLKRXDATA(0)", OutTemp => LLKRXDATA_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(1), GlitchData => LLKRXDATA1_GlitchData, OutSignalName => "LLKRXDATA(1)", OutTemp => LLKRXDATA_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(1), GlitchData => LLKRXDATA1_GlitchData, OutSignalName => "LLKRXDATA(1)", OutTemp => LLKRXDATA_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(2), GlitchData => LLKRXDATA2_GlitchData, OutSignalName => "LLKRXDATA(2)", OutTemp => LLKRXDATA_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(2), GlitchData => LLKRXDATA2_GlitchData, OutSignalName => "LLKRXDATA(2)", OutTemp => LLKRXDATA_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(3), GlitchData => LLKRXDATA3_GlitchData, OutSignalName => "LLKRXDATA(3)", OutTemp => LLKRXDATA_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(3), GlitchData => LLKRXDATA3_GlitchData, OutSignalName => "LLKRXDATA(3)", OutTemp => LLKRXDATA_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(4), GlitchData => LLKRXDATA4_GlitchData, OutSignalName => "LLKRXDATA(4)", OutTemp => LLKRXDATA_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(4), GlitchData => LLKRXDATA4_GlitchData, OutSignalName => "LLKRXDATA(4)", OutTemp => LLKRXDATA_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(5), GlitchData => LLKRXDATA5_GlitchData, OutSignalName => "LLKRXDATA(5)", OutTemp => LLKRXDATA_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(5), GlitchData => LLKRXDATA5_GlitchData, OutSignalName => "LLKRXDATA(5)", OutTemp => LLKRXDATA_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(6), GlitchData => LLKRXDATA6_GlitchData, OutSignalName => "LLKRXDATA(6)", OutTemp => LLKRXDATA_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(6), GlitchData => LLKRXDATA6_GlitchData, OutSignalName => "LLKRXDATA(6)", OutTemp => LLKRXDATA_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(7), GlitchData => LLKRXDATA7_GlitchData, OutSignalName => "LLKRXDATA(7)", OutTemp => LLKRXDATA_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(7), GlitchData => LLKRXDATA7_GlitchData, OutSignalName => "LLKRXDATA(7)", OutTemp => LLKRXDATA_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(8), GlitchData => LLKRXDATA8_GlitchData, OutSignalName => "LLKRXDATA(8)", OutTemp => LLKRXDATA_OUT(8), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(8), GlitchData => LLKRXDATA8_GlitchData, OutSignalName => "LLKRXDATA(8)", OutTemp => LLKRXDATA_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(9), GlitchData => LLKRXDATA9_GlitchData, OutSignalName => "LLKRXDATA(9)", OutTemp => LLKRXDATA_OUT(9), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(9), GlitchData => LLKRXDATA9_GlitchData, OutSignalName => "LLKRXDATA(9)", OutTemp => LLKRXDATA_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(10), GlitchData => LLKRXDATA10_GlitchData, OutSignalName => "LLKRXDATA(10)", OutTemp => LLKRXDATA_OUT(10), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(10), GlitchData => LLKRXDATA10_GlitchData, OutSignalName => "LLKRXDATA(10)", OutTemp => LLKRXDATA_OUT(10), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(11), GlitchData => LLKRXDATA11_GlitchData, OutSignalName => "LLKRXDATA(11)", OutTemp => LLKRXDATA_OUT(11), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(11), GlitchData => LLKRXDATA11_GlitchData, OutSignalName => "LLKRXDATA(11)", OutTemp => LLKRXDATA_OUT(11), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(12), GlitchData => LLKRXDATA12_GlitchData, OutSignalName => "LLKRXDATA(12)", OutTemp => LLKRXDATA_OUT(12), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(12), GlitchData => LLKRXDATA12_GlitchData, OutSignalName => "LLKRXDATA(12)", OutTemp => LLKRXDATA_OUT(12), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(13), GlitchData => LLKRXDATA13_GlitchData, OutSignalName => "LLKRXDATA(13)", OutTemp => LLKRXDATA_OUT(13), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(13), GlitchData => LLKRXDATA13_GlitchData, OutSignalName => "LLKRXDATA(13)", OutTemp => LLKRXDATA_OUT(13), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(14), GlitchData => LLKRXDATA14_GlitchData, OutSignalName => "LLKRXDATA(14)", OutTemp => LLKRXDATA_OUT(14), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(14), GlitchData => LLKRXDATA14_GlitchData, OutSignalName => "LLKRXDATA(14)", OutTemp => LLKRXDATA_OUT(14), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(15), GlitchData => LLKRXDATA15_GlitchData, OutSignalName => "LLKRXDATA(15)", OutTemp => LLKRXDATA_OUT(15), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(15), GlitchData => LLKRXDATA15_GlitchData, OutSignalName => "LLKRXDATA(15)", OutTemp => LLKRXDATA_OUT(15), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(16), GlitchData => LLKRXDATA16_GlitchData, OutSignalName => "LLKRXDATA(16)", OutTemp => LLKRXDATA_OUT(16), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(16), GlitchData => LLKRXDATA16_GlitchData, OutSignalName => "LLKRXDATA(16)", OutTemp => LLKRXDATA_OUT(16), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(17), GlitchData => LLKRXDATA17_GlitchData, OutSignalName => "LLKRXDATA(17)", OutTemp => LLKRXDATA_OUT(17), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(17), GlitchData => LLKRXDATA17_GlitchData, OutSignalName => "LLKRXDATA(17)", OutTemp => LLKRXDATA_OUT(17), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(18), GlitchData => LLKRXDATA18_GlitchData, OutSignalName => "LLKRXDATA(18)", OutTemp => LLKRXDATA_OUT(18), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(18), GlitchData => LLKRXDATA18_GlitchData, OutSignalName => "LLKRXDATA(18)", OutTemp => LLKRXDATA_OUT(18), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(19), GlitchData => LLKRXDATA19_GlitchData, OutSignalName => "LLKRXDATA(19)", OutTemp => LLKRXDATA_OUT(19), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(19), GlitchData => LLKRXDATA19_GlitchData, OutSignalName => "LLKRXDATA(19)", OutTemp => LLKRXDATA_OUT(19), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(20), GlitchData => LLKRXDATA20_GlitchData, OutSignalName => "LLKRXDATA(20)", OutTemp => LLKRXDATA_OUT(20), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(20), GlitchData => LLKRXDATA20_GlitchData, OutSignalName => "LLKRXDATA(20)", OutTemp => LLKRXDATA_OUT(20), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(21), GlitchData => LLKRXDATA21_GlitchData, OutSignalName => "LLKRXDATA(21)", OutTemp => LLKRXDATA_OUT(21), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(21), GlitchData => LLKRXDATA21_GlitchData, OutSignalName => "LLKRXDATA(21)", OutTemp => LLKRXDATA_OUT(21), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(22), GlitchData => LLKRXDATA22_GlitchData, OutSignalName => "LLKRXDATA(22)", OutTemp => LLKRXDATA_OUT(22), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(22), GlitchData => LLKRXDATA22_GlitchData, OutSignalName => "LLKRXDATA(22)", OutTemp => LLKRXDATA_OUT(22), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(23), GlitchData => LLKRXDATA23_GlitchData, OutSignalName => "LLKRXDATA(23)", OutTemp => LLKRXDATA_OUT(23), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(23), GlitchData => LLKRXDATA23_GlitchData, OutSignalName => "LLKRXDATA(23)", OutTemp => LLKRXDATA_OUT(23), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(24), GlitchData => LLKRXDATA24_GlitchData, OutSignalName => "LLKRXDATA(24)", OutTemp => LLKRXDATA_OUT(24), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(24), GlitchData => LLKRXDATA24_GlitchData, OutSignalName => "LLKRXDATA(24)", OutTemp => LLKRXDATA_OUT(24), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(25), GlitchData => LLKRXDATA25_GlitchData, OutSignalName => "LLKRXDATA(25)", OutTemp => LLKRXDATA_OUT(25), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(25), GlitchData => LLKRXDATA25_GlitchData, OutSignalName => "LLKRXDATA(25)", OutTemp => LLKRXDATA_OUT(25), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(26), GlitchData => LLKRXDATA26_GlitchData, OutSignalName => "LLKRXDATA(26)", OutTemp => LLKRXDATA_OUT(26), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(26), GlitchData => LLKRXDATA26_GlitchData, OutSignalName => "LLKRXDATA(26)", OutTemp => LLKRXDATA_OUT(26), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(27), GlitchData => LLKRXDATA27_GlitchData, OutSignalName => "LLKRXDATA(27)", OutTemp => LLKRXDATA_OUT(27), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(27), GlitchData => LLKRXDATA27_GlitchData, OutSignalName => "LLKRXDATA(27)", OutTemp => LLKRXDATA_OUT(27), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(28), GlitchData => LLKRXDATA28_GlitchData, OutSignalName => "LLKRXDATA(28)", OutTemp => LLKRXDATA_OUT(28), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(28), GlitchData => LLKRXDATA28_GlitchData, OutSignalName => "LLKRXDATA(28)", OutTemp => LLKRXDATA_OUT(28), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(29), GlitchData => LLKRXDATA29_GlitchData, OutSignalName => "LLKRXDATA(29)", OutTemp => LLKRXDATA_OUT(29), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(29), GlitchData => LLKRXDATA29_GlitchData, OutSignalName => "LLKRXDATA(29)", OutTemp => LLKRXDATA_OUT(29), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(30), GlitchData => LLKRXDATA30_GlitchData, OutSignalName => "LLKRXDATA(30)", OutTemp => LLKRXDATA_OUT(30), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(30), GlitchData => LLKRXDATA30_GlitchData, OutSignalName => "LLKRXDATA(30)", OutTemp => LLKRXDATA_OUT(30), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(31), GlitchData => LLKRXDATA31_GlitchData, OutSignalName => "LLKRXDATA(31)", OutTemp => LLKRXDATA_OUT(31), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(31), GlitchData => LLKRXDATA31_GlitchData, OutSignalName => "LLKRXDATA(31)", OutTemp => LLKRXDATA_OUT(31), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(32), GlitchData => LLKRXDATA32_GlitchData, OutSignalName => "LLKRXDATA(32)", OutTemp => LLKRXDATA_OUT(32), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(32), GlitchData => LLKRXDATA32_GlitchData, OutSignalName => "LLKRXDATA(32)", OutTemp => LLKRXDATA_OUT(32), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(33), GlitchData => LLKRXDATA33_GlitchData, OutSignalName => "LLKRXDATA(33)", OutTemp => LLKRXDATA_OUT(33), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(33), GlitchData => LLKRXDATA33_GlitchData, OutSignalName => "LLKRXDATA(33)", OutTemp => LLKRXDATA_OUT(33), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(34), GlitchData => LLKRXDATA34_GlitchData, OutSignalName => "LLKRXDATA(34)", OutTemp => LLKRXDATA_OUT(34), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(34), GlitchData => LLKRXDATA34_GlitchData, OutSignalName => "LLKRXDATA(34)", OutTemp => LLKRXDATA_OUT(34), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(35), GlitchData => LLKRXDATA35_GlitchData, OutSignalName => "LLKRXDATA(35)", OutTemp => LLKRXDATA_OUT(35), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(35), GlitchData => LLKRXDATA35_GlitchData, OutSignalName => "LLKRXDATA(35)", OutTemp => LLKRXDATA_OUT(35), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(36), GlitchData => LLKRXDATA36_GlitchData, OutSignalName => "LLKRXDATA(36)", OutTemp => LLKRXDATA_OUT(36), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(36), GlitchData => LLKRXDATA36_GlitchData, OutSignalName => "LLKRXDATA(36)", OutTemp => LLKRXDATA_OUT(36), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(37), GlitchData => LLKRXDATA37_GlitchData, OutSignalName => "LLKRXDATA(37)", OutTemp => LLKRXDATA_OUT(37), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(37), GlitchData => LLKRXDATA37_GlitchData, OutSignalName => "LLKRXDATA(37)", OutTemp => LLKRXDATA_OUT(37), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(38), GlitchData => LLKRXDATA38_GlitchData, OutSignalName => "LLKRXDATA(38)", OutTemp => LLKRXDATA_OUT(38), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(38), GlitchData => LLKRXDATA38_GlitchData, OutSignalName => "LLKRXDATA(38)", OutTemp => LLKRXDATA_OUT(38), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(39), GlitchData => LLKRXDATA39_GlitchData, OutSignalName => "LLKRXDATA(39)", OutTemp => LLKRXDATA_OUT(39), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(39), GlitchData => LLKRXDATA39_GlitchData, OutSignalName => "LLKRXDATA(39)", OutTemp => LLKRXDATA_OUT(39), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(40), GlitchData => LLKRXDATA40_GlitchData, OutSignalName => "LLKRXDATA(40)", OutTemp => LLKRXDATA_OUT(40), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(40), GlitchData => LLKRXDATA40_GlitchData, OutSignalName => "LLKRXDATA(40)", OutTemp => LLKRXDATA_OUT(40), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(41), GlitchData => LLKRXDATA41_GlitchData, OutSignalName => "LLKRXDATA(41)", OutTemp => LLKRXDATA_OUT(41), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(41), GlitchData => LLKRXDATA41_GlitchData, OutSignalName => "LLKRXDATA(41)", OutTemp => LLKRXDATA_OUT(41), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(42), GlitchData => LLKRXDATA42_GlitchData, OutSignalName => "LLKRXDATA(42)", OutTemp => LLKRXDATA_OUT(42), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(42), GlitchData => LLKRXDATA42_GlitchData, OutSignalName => "LLKRXDATA(42)", OutTemp => LLKRXDATA_OUT(42), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(43), GlitchData => LLKRXDATA43_GlitchData, OutSignalName => "LLKRXDATA(43)", OutTemp => LLKRXDATA_OUT(43), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(43), GlitchData => LLKRXDATA43_GlitchData, OutSignalName => "LLKRXDATA(43)", OutTemp => LLKRXDATA_OUT(43), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(44), GlitchData => LLKRXDATA44_GlitchData, OutSignalName => "LLKRXDATA(44)", OutTemp => LLKRXDATA_OUT(44), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(44), GlitchData => LLKRXDATA44_GlitchData, OutSignalName => "LLKRXDATA(44)", OutTemp => LLKRXDATA_OUT(44), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(45), GlitchData => LLKRXDATA45_GlitchData, OutSignalName => "LLKRXDATA(45)", OutTemp => LLKRXDATA_OUT(45), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(45), GlitchData => LLKRXDATA45_GlitchData, OutSignalName => "LLKRXDATA(45)", OutTemp => LLKRXDATA_OUT(45), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(46), GlitchData => LLKRXDATA46_GlitchData, OutSignalName => "LLKRXDATA(46)", OutTemp => LLKRXDATA_OUT(46), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(46), GlitchData => LLKRXDATA46_GlitchData, OutSignalName => "LLKRXDATA(46)", OutTemp => LLKRXDATA_OUT(46), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(47), GlitchData => LLKRXDATA47_GlitchData, OutSignalName => "LLKRXDATA(47)", OutTemp => LLKRXDATA_OUT(47), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(47), GlitchData => LLKRXDATA47_GlitchData, OutSignalName => "LLKRXDATA(47)", OutTemp => LLKRXDATA_OUT(47), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(48), GlitchData => LLKRXDATA48_GlitchData, OutSignalName => "LLKRXDATA(48)", OutTemp => LLKRXDATA_OUT(48), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(48), GlitchData => LLKRXDATA48_GlitchData, OutSignalName => "LLKRXDATA(48)", OutTemp => LLKRXDATA_OUT(48), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(49), GlitchData => LLKRXDATA49_GlitchData, OutSignalName => "LLKRXDATA(49)", OutTemp => LLKRXDATA_OUT(49), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(49), GlitchData => LLKRXDATA49_GlitchData, OutSignalName => "LLKRXDATA(49)", OutTemp => LLKRXDATA_OUT(49), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(50), GlitchData => LLKRXDATA50_GlitchData, OutSignalName => "LLKRXDATA(50)", OutTemp => LLKRXDATA_OUT(50), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(50), GlitchData => LLKRXDATA50_GlitchData, OutSignalName => "LLKRXDATA(50)", OutTemp => LLKRXDATA_OUT(50), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(51), GlitchData => LLKRXDATA51_GlitchData, OutSignalName => "LLKRXDATA(51)", OutTemp => LLKRXDATA_OUT(51), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(51), GlitchData => LLKRXDATA51_GlitchData, OutSignalName => "LLKRXDATA(51)", OutTemp => LLKRXDATA_OUT(51), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(52), GlitchData => LLKRXDATA52_GlitchData, OutSignalName => "LLKRXDATA(52)", OutTemp => LLKRXDATA_OUT(52), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(52), GlitchData => LLKRXDATA52_GlitchData, OutSignalName => "LLKRXDATA(52)", OutTemp => LLKRXDATA_OUT(52), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(53), GlitchData => LLKRXDATA53_GlitchData, OutSignalName => "LLKRXDATA(53)", OutTemp => LLKRXDATA_OUT(53), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(53), GlitchData => LLKRXDATA53_GlitchData, OutSignalName => "LLKRXDATA(53)", OutTemp => LLKRXDATA_OUT(53), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(54), GlitchData => LLKRXDATA54_GlitchData, OutSignalName => "LLKRXDATA(54)", OutTemp => LLKRXDATA_OUT(54), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(54), GlitchData => LLKRXDATA54_GlitchData, OutSignalName => "LLKRXDATA(54)", OutTemp => LLKRXDATA_OUT(54), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(55), GlitchData => LLKRXDATA55_GlitchData, OutSignalName => "LLKRXDATA(55)", OutTemp => LLKRXDATA_OUT(55), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(55), GlitchData => LLKRXDATA55_GlitchData, OutSignalName => "LLKRXDATA(55)", OutTemp => LLKRXDATA_OUT(55), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(56), GlitchData => LLKRXDATA56_GlitchData, OutSignalName => "LLKRXDATA(56)", OutTemp => LLKRXDATA_OUT(56), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(56), GlitchData => LLKRXDATA56_GlitchData, OutSignalName => "LLKRXDATA(56)", OutTemp => LLKRXDATA_OUT(56), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(57), GlitchData => LLKRXDATA57_GlitchData, OutSignalName => "LLKRXDATA(57)", OutTemp => LLKRXDATA_OUT(57), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(57), GlitchData => LLKRXDATA57_GlitchData, OutSignalName => "LLKRXDATA(57)", OutTemp => LLKRXDATA_OUT(57), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(58), GlitchData => LLKRXDATA58_GlitchData, OutSignalName => "LLKRXDATA(58)", OutTemp => LLKRXDATA_OUT(58), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(58), GlitchData => LLKRXDATA58_GlitchData, OutSignalName => "LLKRXDATA(58)", OutTemp => LLKRXDATA_OUT(58), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(59), GlitchData => LLKRXDATA59_GlitchData, OutSignalName => "LLKRXDATA(59)", OutTemp => LLKRXDATA_OUT(59), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(59), GlitchData => LLKRXDATA59_GlitchData, OutSignalName => "LLKRXDATA(59)", OutTemp => LLKRXDATA_OUT(59), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(60), GlitchData => LLKRXDATA60_GlitchData, OutSignalName => "LLKRXDATA(60)", OutTemp => LLKRXDATA_OUT(60), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(60), GlitchData => LLKRXDATA60_GlitchData, OutSignalName => "LLKRXDATA(60)", OutTemp => LLKRXDATA_OUT(60), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(61), GlitchData => LLKRXDATA61_GlitchData, OutSignalName => "LLKRXDATA(61)", OutTemp => LLKRXDATA_OUT(61), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(61), GlitchData => LLKRXDATA61_GlitchData, OutSignalName => "LLKRXDATA(61)", OutTemp => LLKRXDATA_OUT(61), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(62), GlitchData => LLKRXDATA62_GlitchData, OutSignalName => "LLKRXDATA(62)", OutTemp => LLKRXDATA_OUT(62), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(62), GlitchData => LLKRXDATA62_GlitchData, OutSignalName => "LLKRXDATA(62)", OutTemp => LLKRXDATA_OUT(62), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(63), GlitchData => LLKRXDATA63_GlitchData, OutSignalName => "LLKRXDATA(63)", OutTemp => LLKRXDATA_OUT(63), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXDATA(63), GlitchData => LLKRXDATA63_GlitchData, OutSignalName => "LLKRXDATA(63)", OutTemp => LLKRXDATA_OUT(63), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXSRCRDYN, GlitchData => LLKRXSRCRDYN_GlitchData, OutSignalName => "LLKRXSRCRDYN", OutTemp => LLKRXSRCRDYN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXSRCRDYN, GlitchData => LLKRXSRCRDYN_GlitchData, OutSignalName => "LLKRXSRCRDYN", OutTemp => LLKRXSRCRDYN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXSRCLASTREQN, GlitchData => LLKRXSRCLASTREQN_GlitchData, OutSignalName => "LLKRXSRCLASTREQN", OutTemp => LLKRXSRCLASTREQN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXSRCLASTREQN, GlitchData => LLKRXSRCLASTREQN_GlitchData, OutSignalName => "LLKRXSRCLASTREQN", OutTemp => LLKRXSRCLASTREQN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXSRCDSCN, GlitchData => LLKRXSRCDSCN_GlitchData, OutSignalName => "LLKRXSRCDSCN", OutTemp => LLKRXSRCDSCN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXSRCDSCN, GlitchData => LLKRXSRCDSCN_GlitchData, OutSignalName => "LLKRXSRCDSCN", OutTemp => LLKRXSRCDSCN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXSOFN, GlitchData => LLKRXSOFN_GlitchData, OutSignalName => "LLKRXSOFN", OutTemp => LLKRXSOFN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXSOFN, GlitchData => LLKRXSOFN_GlitchData, OutSignalName => "LLKRXSOFN", OutTemp => LLKRXSOFN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXEOFN, GlitchData => LLKRXEOFN_GlitchData, OutSignalName => "LLKRXEOFN", OutTemp => LLKRXEOFN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXEOFN, GlitchData => LLKRXEOFN_GlitchData, OutSignalName => "LLKRXEOFN", OutTemp => LLKRXEOFN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXSOPN, GlitchData => LLKRXSOPN_GlitchData, OutSignalName => "LLKRXSOPN", OutTemp => LLKRXSOPN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXSOPN, GlitchData => LLKRXSOPN_GlitchData, OutSignalName => "LLKRXSOPN", OutTemp => LLKRXSOPN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXEOPN, GlitchData => LLKRXEOPN_GlitchData, OutSignalName => "LLKRXEOPN", OutTemp => LLKRXEOPN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXEOPN, GlitchData => LLKRXEOPN_GlitchData, OutSignalName => "LLKRXEOPN", OutTemp => LLKRXEOPN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXVALIDN(0), GlitchData => LLKRXVALIDN0_GlitchData, OutSignalName => "LLKRXVALIDN(0)", OutTemp => LLKRXVALIDN_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXVALIDN(0), GlitchData => LLKRXVALIDN0_GlitchData, OutSignalName => "LLKRXVALIDN(0)", OutTemp => LLKRXVALIDN_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXVALIDN(1), GlitchData => LLKRXVALIDN1_GlitchData, OutSignalName => "LLKRXVALIDN(1)", OutTemp => LLKRXVALIDN_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXVALIDN(1), GlitchData => LLKRXVALIDN1_GlitchData, OutSignalName => "LLKRXVALIDN(1)", OutTemp => LLKRXVALIDN_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(0), GlitchData => LLKRXPREFERREDTYPE0_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(0)", OutTemp => LLKRXPREFERREDTYPE_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(0), GlitchData => LLKRXPREFERREDTYPE0_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(0)", OutTemp => LLKRXPREFERREDTYPE_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(1), GlitchData => LLKRXPREFERREDTYPE1_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(1)", OutTemp => LLKRXPREFERREDTYPE_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(1), GlitchData => LLKRXPREFERREDTYPE1_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(1)", OutTemp => LLKRXPREFERREDTYPE_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(2), GlitchData => LLKRXPREFERREDTYPE2_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(2)", OutTemp => LLKRXPREFERREDTYPE_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(2), GlitchData => LLKRXPREFERREDTYPE2_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(2)", OutTemp => LLKRXPREFERREDTYPE_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(3), GlitchData => LLKRXPREFERREDTYPE3_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(3)", OutTemp => LLKRXPREFERREDTYPE_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(3), GlitchData => LLKRXPREFERREDTYPE3_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(3)", OutTemp => LLKRXPREFERREDTYPE_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(4), GlitchData => LLKRXPREFERREDTYPE4_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(4)", OutTemp => LLKRXPREFERREDTYPE_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(4), GlitchData => LLKRXPREFERREDTYPE4_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(4)", OutTemp => LLKRXPREFERREDTYPE_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(5), GlitchData => LLKRXPREFERREDTYPE5_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(5)", OutTemp => LLKRXPREFERREDTYPE_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(5), GlitchData => LLKRXPREFERREDTYPE5_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(5)", OutTemp => LLKRXPREFERREDTYPE_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(6), GlitchData => LLKRXPREFERREDTYPE6_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(6)", OutTemp => LLKRXPREFERREDTYPE_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(6), GlitchData => LLKRXPREFERREDTYPE6_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(6)", OutTemp => LLKRXPREFERREDTYPE_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(7), GlitchData => LLKRXPREFERREDTYPE7_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(7)", OutTemp => LLKRXPREFERREDTYPE_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(7), GlitchData => LLKRXPREFERREDTYPE7_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(7)", OutTemp => LLKRXPREFERREDTYPE_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(8), GlitchData => LLKRXPREFERREDTYPE8_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(8)", OutTemp => LLKRXPREFERREDTYPE_OUT(8), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(8), GlitchData => LLKRXPREFERREDTYPE8_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(8)", OutTemp => LLKRXPREFERREDTYPE_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(9), GlitchData => LLKRXPREFERREDTYPE9_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(9)", OutTemp => LLKRXPREFERREDTYPE_OUT(9), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(9), GlitchData => LLKRXPREFERREDTYPE9_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(9)", OutTemp => LLKRXPREFERREDTYPE_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(10), GlitchData => LLKRXPREFERREDTYPE10_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(10)", OutTemp => LLKRXPREFERREDTYPE_OUT(10), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(10), GlitchData => LLKRXPREFERREDTYPE10_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(10)", OutTemp => LLKRXPREFERREDTYPE_OUT(10), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(11), GlitchData => LLKRXPREFERREDTYPE11_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(11)", OutTemp => LLKRXPREFERREDTYPE_OUT(11), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(11), GlitchData => LLKRXPREFERREDTYPE11_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(11)", OutTemp => LLKRXPREFERREDTYPE_OUT(11), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(12), GlitchData => LLKRXPREFERREDTYPE12_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(12)", OutTemp => LLKRXPREFERREDTYPE_OUT(12), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(12), GlitchData => LLKRXPREFERREDTYPE12_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(12)", OutTemp => LLKRXPREFERREDTYPE_OUT(12), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(13), GlitchData => LLKRXPREFERREDTYPE13_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(13)", OutTemp => LLKRXPREFERREDTYPE_OUT(13), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(13), GlitchData => LLKRXPREFERREDTYPE13_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(13)", OutTemp => LLKRXPREFERREDTYPE_OUT(13), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(14), GlitchData => LLKRXPREFERREDTYPE14_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(14)", OutTemp => LLKRXPREFERREDTYPE_OUT(14), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(14), GlitchData => LLKRXPREFERREDTYPE14_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(14)", OutTemp => LLKRXPREFERREDTYPE_OUT(14), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(15), GlitchData => LLKRXPREFERREDTYPE15_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(15)", OutTemp => LLKRXPREFERREDTYPE_OUT(15), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXPREFERREDTYPE(15), GlitchData => LLKRXPREFERREDTYPE15_GlitchData, OutSignalName => "LLKRXPREFERREDTYPE(15)", OutTemp => LLKRXPREFERREDTYPE_OUT(15), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(0), GlitchData => LLKRXCHPOSTEDAVAILABLEN0_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(0)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(0), GlitchData => LLKRXCHPOSTEDAVAILABLEN0_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(0)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(1), GlitchData => LLKRXCHPOSTEDAVAILABLEN1_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(1)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(1), GlitchData => LLKRXCHPOSTEDAVAILABLEN1_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(1)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(2), GlitchData => LLKRXCHPOSTEDAVAILABLEN2_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(2)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(2), GlitchData => LLKRXCHPOSTEDAVAILABLEN2_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(2)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(3), GlitchData => LLKRXCHPOSTEDAVAILABLEN3_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(3)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(3), GlitchData => LLKRXCHPOSTEDAVAILABLEN3_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(3)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(4), GlitchData => LLKRXCHPOSTEDAVAILABLEN4_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(4)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(4), GlitchData => LLKRXCHPOSTEDAVAILABLEN4_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(4)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(5), GlitchData => LLKRXCHPOSTEDAVAILABLEN5_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(5)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(5), GlitchData => LLKRXCHPOSTEDAVAILABLEN5_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(5)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(6), GlitchData => LLKRXCHPOSTEDAVAILABLEN6_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(6)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(6), GlitchData => LLKRXCHPOSTEDAVAILABLEN6_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(6)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(7), GlitchData => LLKRXCHPOSTEDAVAILABLEN7_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(7)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDAVAILABLEN(7), GlitchData => LLKRXCHPOSTEDAVAILABLEN7_GlitchData, OutSignalName => "LLKRXCHPOSTEDAVAILABLEN(7)", OutTemp => LLKRXCHPOSTEDAVAILABLEN_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(0), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN0_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(0)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(0), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN0_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(0)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(1), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN1_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(1)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(1), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN1_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(1)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(2), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN2_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(2)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(2), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN2_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(2)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(3), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN3_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(3)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(3), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN3_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(3)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(4), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN4_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(4)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(4), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN4_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(4)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(5), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN5_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(5)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(5), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN5_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(5)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(6), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN6_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(6)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(6), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN6_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(6)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(7), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN7_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(7)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDAVAILABLEN(7), GlitchData => LLKRXCHNONPOSTEDAVAILABLEN7_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDAVAILABLEN(7)", OutTemp => LLKRXCHNONPOSTEDAVAILABLEN_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(0), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN0_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(0)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(0), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN0_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(0)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(1), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN1_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(1)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(1), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN1_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(1)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(2), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN2_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(2)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(2), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN2_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(2)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(3), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN3_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(3)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(3), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN3_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(3)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(4), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN4_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(4)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(4), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN4_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(4)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(5), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN5_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(5)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(5), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN5_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(5)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(6), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN6_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(6)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(6), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN6_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(6)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(7), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN7_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(7)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONAVAILABLEN(7), GlitchData => LLKRXCHCOMPLETIONAVAILABLEN7_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONAVAILABLEN(7)", OutTemp => LLKRXCHCOMPLETIONAVAILABLEN_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCONFIGAVAILABLEN, GlitchData => LLKRXCHCONFIGAVAILABLEN_GlitchData, OutSignalName => "LLKRXCHCONFIGAVAILABLEN", OutTemp => LLKRXCHCONFIGAVAILABLEN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCONFIGAVAILABLEN, GlitchData => LLKRXCHCONFIGAVAILABLEN_GlitchData, OutSignalName => "LLKRXCHCONFIGAVAILABLEN", OutTemp => LLKRXCHCONFIGAVAILABLEN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(0), GlitchData => LLKRXCHPOSTEDPARTIALN0_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(0)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(0), GlitchData => LLKRXCHPOSTEDPARTIALN0_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(0)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(1), GlitchData => LLKRXCHPOSTEDPARTIALN1_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(1)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(1), GlitchData => LLKRXCHPOSTEDPARTIALN1_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(1)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(2), GlitchData => LLKRXCHPOSTEDPARTIALN2_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(2)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(2), GlitchData => LLKRXCHPOSTEDPARTIALN2_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(2)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(3), GlitchData => LLKRXCHPOSTEDPARTIALN3_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(3)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(3), GlitchData => LLKRXCHPOSTEDPARTIALN3_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(3)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(4), GlitchData => LLKRXCHPOSTEDPARTIALN4_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(4)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(4), GlitchData => LLKRXCHPOSTEDPARTIALN4_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(4)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(5), GlitchData => LLKRXCHPOSTEDPARTIALN5_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(5)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(5), GlitchData => LLKRXCHPOSTEDPARTIALN5_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(5)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(6), GlitchData => LLKRXCHPOSTEDPARTIALN6_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(6)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(6), GlitchData => LLKRXCHPOSTEDPARTIALN6_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(6)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(7), GlitchData => LLKRXCHPOSTEDPARTIALN7_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(7)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHPOSTEDPARTIALN(7), GlitchData => LLKRXCHPOSTEDPARTIALN7_GlitchData, OutSignalName => "LLKRXCHPOSTEDPARTIALN(7)", OutTemp => LLKRXCHPOSTEDPARTIALN_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(0), GlitchData => LLKRXCHNONPOSTEDPARTIALN0_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(0)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(0), GlitchData => LLKRXCHNONPOSTEDPARTIALN0_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(0)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(1), GlitchData => LLKRXCHNONPOSTEDPARTIALN1_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(1)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(1), GlitchData => LLKRXCHNONPOSTEDPARTIALN1_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(1)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(2), GlitchData => LLKRXCHNONPOSTEDPARTIALN2_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(2)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(2), GlitchData => LLKRXCHNONPOSTEDPARTIALN2_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(2)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(3), GlitchData => LLKRXCHNONPOSTEDPARTIALN3_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(3)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(3), GlitchData => LLKRXCHNONPOSTEDPARTIALN3_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(3)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(4), GlitchData => LLKRXCHNONPOSTEDPARTIALN4_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(4)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(4), GlitchData => LLKRXCHNONPOSTEDPARTIALN4_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(4)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(5), GlitchData => LLKRXCHNONPOSTEDPARTIALN5_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(5)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(5), GlitchData => LLKRXCHNONPOSTEDPARTIALN5_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(5)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(6), GlitchData => LLKRXCHNONPOSTEDPARTIALN6_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(6)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(6), GlitchData => LLKRXCHNONPOSTEDPARTIALN6_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(6)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(7), GlitchData => LLKRXCHNONPOSTEDPARTIALN7_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(7)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHNONPOSTEDPARTIALN(7), GlitchData => LLKRXCHNONPOSTEDPARTIALN7_GlitchData, OutSignalName => "LLKRXCHNONPOSTEDPARTIALN(7)", OutTemp => LLKRXCHNONPOSTEDPARTIALN_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(0), GlitchData => LLKRXCHCOMPLETIONPARTIALN0_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(0)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(0), GlitchData => LLKRXCHCOMPLETIONPARTIALN0_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(0)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(1), GlitchData => LLKRXCHCOMPLETIONPARTIALN1_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(1)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(1), GlitchData => LLKRXCHCOMPLETIONPARTIALN1_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(1)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(2), GlitchData => LLKRXCHCOMPLETIONPARTIALN2_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(2)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(2), GlitchData => LLKRXCHCOMPLETIONPARTIALN2_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(2)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(3), GlitchData => LLKRXCHCOMPLETIONPARTIALN3_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(3)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(3), GlitchData => LLKRXCHCOMPLETIONPARTIALN3_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(3)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(4), GlitchData => LLKRXCHCOMPLETIONPARTIALN4_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(4)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(4), GlitchData => LLKRXCHCOMPLETIONPARTIALN4_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(4)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(5), GlitchData => LLKRXCHCOMPLETIONPARTIALN5_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(5)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(5), GlitchData => LLKRXCHCOMPLETIONPARTIALN5_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(5)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(6), GlitchData => LLKRXCHCOMPLETIONPARTIALN6_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(6)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(6), GlitchData => LLKRXCHCOMPLETIONPARTIALN6_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(6)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(7), GlitchData => LLKRXCHCOMPLETIONPARTIALN7_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(7)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCOMPLETIONPARTIALN(7), GlitchData => LLKRXCHCOMPLETIONPARTIALN7_GlitchData, OutSignalName => "LLKRXCHCOMPLETIONPARTIALN(7)", OutTemp => LLKRXCHCOMPLETIONPARTIALN_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCONFIGPARTIALN, GlitchData => LLKRXCHCONFIGPARTIALN_GlitchData, OutSignalName => "LLKRXCHCONFIGPARTIALN", OutTemp => LLKRXCHCONFIGPARTIALN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXCHCONFIGPARTIALN, GlitchData => LLKRXCHCONFIGPARTIALN_GlitchData, OutSignalName => "LLKRXCHCONFIGPARTIALN", OutTemp => LLKRXCHCONFIGPARTIALN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRX4DWHEADERN, GlitchData => LLKRX4DWHEADERN_GlitchData, OutSignalName => "LLKRX4DWHEADERN", OutTemp => LLKRX4DWHEADERN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRX4DWHEADERN, GlitchData => LLKRX4DWHEADERN_GlitchData, OutSignalName => "LLKRX4DWHEADERN", OutTemp => LLKRX4DWHEADERN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXECRCBADN, GlitchData => LLKRXECRCBADN_GlitchData, OutSignalName => "LLKRXECRCBADN", OutTemp => LLKRXECRCBADN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => LLKRXECRCBADN, GlitchData => LLKRXECRCBADN_GlitchData, OutSignalName => "LLKRXECRCBADN", OutTemp => LLKRXECRCBADN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(0), GlitchData => MGMTRDATA0_GlitchData, OutSignalName => "MGMTRDATA(0)", OutTemp => MGMTRDATA_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(0), GlitchData => MGMTRDATA0_GlitchData, OutSignalName => "MGMTRDATA(0)", OutTemp => MGMTRDATA_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(1), GlitchData => MGMTRDATA1_GlitchData, OutSignalName => "MGMTRDATA(1)", OutTemp => MGMTRDATA_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(1), GlitchData => MGMTRDATA1_GlitchData, OutSignalName => "MGMTRDATA(1)", OutTemp => MGMTRDATA_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(2), GlitchData => MGMTRDATA2_GlitchData, OutSignalName => "MGMTRDATA(2)", OutTemp => MGMTRDATA_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(2), GlitchData => MGMTRDATA2_GlitchData, OutSignalName => "MGMTRDATA(2)", OutTemp => MGMTRDATA_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(3), GlitchData => MGMTRDATA3_GlitchData, OutSignalName => "MGMTRDATA(3)", OutTemp => MGMTRDATA_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(3), GlitchData => MGMTRDATA3_GlitchData, OutSignalName => "MGMTRDATA(3)", OutTemp => MGMTRDATA_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(4), GlitchData => MGMTRDATA4_GlitchData, OutSignalName => "MGMTRDATA(4)", OutTemp => MGMTRDATA_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(4), GlitchData => MGMTRDATA4_GlitchData, OutSignalName => "MGMTRDATA(4)", OutTemp => MGMTRDATA_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(5), GlitchData => MGMTRDATA5_GlitchData, OutSignalName => "MGMTRDATA(5)", OutTemp => MGMTRDATA_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(5), GlitchData => MGMTRDATA5_GlitchData, OutSignalName => "MGMTRDATA(5)", OutTemp => MGMTRDATA_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(6), GlitchData => MGMTRDATA6_GlitchData, OutSignalName => "MGMTRDATA(6)", OutTemp => MGMTRDATA_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(6), GlitchData => MGMTRDATA6_GlitchData, OutSignalName => "MGMTRDATA(6)", OutTemp => MGMTRDATA_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(7), GlitchData => MGMTRDATA7_GlitchData, OutSignalName => "MGMTRDATA(7)", OutTemp => MGMTRDATA_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(7), GlitchData => MGMTRDATA7_GlitchData, OutSignalName => "MGMTRDATA(7)", OutTemp => MGMTRDATA_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(8), GlitchData => MGMTRDATA8_GlitchData, OutSignalName => "MGMTRDATA(8)", OutTemp => MGMTRDATA_OUT(8), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(8), GlitchData => MGMTRDATA8_GlitchData, OutSignalName => "MGMTRDATA(8)", OutTemp => MGMTRDATA_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(9), GlitchData => MGMTRDATA9_GlitchData, OutSignalName => "MGMTRDATA(9)", OutTemp => MGMTRDATA_OUT(9), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(9), GlitchData => MGMTRDATA9_GlitchData, OutSignalName => "MGMTRDATA(9)", OutTemp => MGMTRDATA_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(10), GlitchData => MGMTRDATA10_GlitchData, OutSignalName => "MGMTRDATA(10)", OutTemp => MGMTRDATA_OUT(10), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(10), GlitchData => MGMTRDATA10_GlitchData, OutSignalName => "MGMTRDATA(10)", OutTemp => MGMTRDATA_OUT(10), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(11), GlitchData => MGMTRDATA11_GlitchData, OutSignalName => "MGMTRDATA(11)", OutTemp => MGMTRDATA_OUT(11), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(11), GlitchData => MGMTRDATA11_GlitchData, OutSignalName => "MGMTRDATA(11)", OutTemp => MGMTRDATA_OUT(11), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(12), GlitchData => MGMTRDATA12_GlitchData, OutSignalName => "MGMTRDATA(12)", OutTemp => MGMTRDATA_OUT(12), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(12), GlitchData => MGMTRDATA12_GlitchData, OutSignalName => "MGMTRDATA(12)", OutTemp => MGMTRDATA_OUT(12), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(13), GlitchData => MGMTRDATA13_GlitchData, OutSignalName => "MGMTRDATA(13)", OutTemp => MGMTRDATA_OUT(13), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(13), GlitchData => MGMTRDATA13_GlitchData, OutSignalName => "MGMTRDATA(13)", OutTemp => MGMTRDATA_OUT(13), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(14), GlitchData => MGMTRDATA14_GlitchData, OutSignalName => "MGMTRDATA(14)", OutTemp => MGMTRDATA_OUT(14), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(14), GlitchData => MGMTRDATA14_GlitchData, OutSignalName => "MGMTRDATA(14)", OutTemp => MGMTRDATA_OUT(14), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(15), GlitchData => MGMTRDATA15_GlitchData, OutSignalName => "MGMTRDATA(15)", OutTemp => MGMTRDATA_OUT(15), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(15), GlitchData => MGMTRDATA15_GlitchData, OutSignalName => "MGMTRDATA(15)", OutTemp => MGMTRDATA_OUT(15), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(16), GlitchData => MGMTRDATA16_GlitchData, OutSignalName => "MGMTRDATA(16)", OutTemp => MGMTRDATA_OUT(16), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(16), GlitchData => MGMTRDATA16_GlitchData, OutSignalName => "MGMTRDATA(16)", OutTemp => MGMTRDATA_OUT(16), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(17), GlitchData => MGMTRDATA17_GlitchData, OutSignalName => "MGMTRDATA(17)", OutTemp => MGMTRDATA_OUT(17), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(17), GlitchData => MGMTRDATA17_GlitchData, OutSignalName => "MGMTRDATA(17)", OutTemp => MGMTRDATA_OUT(17), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(18), GlitchData => MGMTRDATA18_GlitchData, OutSignalName => "MGMTRDATA(18)", OutTemp => MGMTRDATA_OUT(18), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(18), GlitchData => MGMTRDATA18_GlitchData, OutSignalName => "MGMTRDATA(18)", OutTemp => MGMTRDATA_OUT(18), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(19), GlitchData => MGMTRDATA19_GlitchData, OutSignalName => "MGMTRDATA(19)", OutTemp => MGMTRDATA_OUT(19), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(19), GlitchData => MGMTRDATA19_GlitchData, OutSignalName => "MGMTRDATA(19)", OutTemp => MGMTRDATA_OUT(19), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(20), GlitchData => MGMTRDATA20_GlitchData, OutSignalName => "MGMTRDATA(20)", OutTemp => MGMTRDATA_OUT(20), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(20), GlitchData => MGMTRDATA20_GlitchData, OutSignalName => "MGMTRDATA(20)", OutTemp => MGMTRDATA_OUT(20), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(21), GlitchData => MGMTRDATA21_GlitchData, OutSignalName => "MGMTRDATA(21)", OutTemp => MGMTRDATA_OUT(21), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(21), GlitchData => MGMTRDATA21_GlitchData, OutSignalName => "MGMTRDATA(21)", OutTemp => MGMTRDATA_OUT(21), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(22), GlitchData => MGMTRDATA22_GlitchData, OutSignalName => "MGMTRDATA(22)", OutTemp => MGMTRDATA_OUT(22), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(22), GlitchData => MGMTRDATA22_GlitchData, OutSignalName => "MGMTRDATA(22)", OutTemp => MGMTRDATA_OUT(22), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(23), GlitchData => MGMTRDATA23_GlitchData, OutSignalName => "MGMTRDATA(23)", OutTemp => MGMTRDATA_OUT(23), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(23), GlitchData => MGMTRDATA23_GlitchData, OutSignalName => "MGMTRDATA(23)", OutTemp => MGMTRDATA_OUT(23), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(24), GlitchData => MGMTRDATA24_GlitchData, OutSignalName => "MGMTRDATA(24)", OutTemp => MGMTRDATA_OUT(24), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(24), GlitchData => MGMTRDATA24_GlitchData, OutSignalName => "MGMTRDATA(24)", OutTemp => MGMTRDATA_OUT(24), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(25), GlitchData => MGMTRDATA25_GlitchData, OutSignalName => "MGMTRDATA(25)", OutTemp => MGMTRDATA_OUT(25), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(25), GlitchData => MGMTRDATA25_GlitchData, OutSignalName => "MGMTRDATA(25)", OutTemp => MGMTRDATA_OUT(25), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(26), GlitchData => MGMTRDATA26_GlitchData, OutSignalName => "MGMTRDATA(26)", OutTemp => MGMTRDATA_OUT(26), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(26), GlitchData => MGMTRDATA26_GlitchData, OutSignalName => "MGMTRDATA(26)", OutTemp => MGMTRDATA_OUT(26), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(27), GlitchData => MGMTRDATA27_GlitchData, OutSignalName => "MGMTRDATA(27)", OutTemp => MGMTRDATA_OUT(27), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(27), GlitchData => MGMTRDATA27_GlitchData, OutSignalName => "MGMTRDATA(27)", OutTemp => MGMTRDATA_OUT(27), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(28), GlitchData => MGMTRDATA28_GlitchData, OutSignalName => "MGMTRDATA(28)", OutTemp => MGMTRDATA_OUT(28), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(28), GlitchData => MGMTRDATA28_GlitchData, OutSignalName => "MGMTRDATA(28)", OutTemp => MGMTRDATA_OUT(28), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(29), GlitchData => MGMTRDATA29_GlitchData, OutSignalName => "MGMTRDATA(29)", OutTemp => MGMTRDATA_OUT(29), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(29), GlitchData => MGMTRDATA29_GlitchData, OutSignalName => "MGMTRDATA(29)", OutTemp => MGMTRDATA_OUT(29), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(30), GlitchData => MGMTRDATA30_GlitchData, OutSignalName => "MGMTRDATA(30)", OutTemp => MGMTRDATA_OUT(30), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(30), GlitchData => MGMTRDATA30_GlitchData, OutSignalName => "MGMTRDATA(30)", OutTemp => MGMTRDATA_OUT(30), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(31), GlitchData => MGMTRDATA31_GlitchData, OutSignalName => "MGMTRDATA(31)", OutTemp => MGMTRDATA_OUT(31), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTRDATA(31), GlitchData => MGMTRDATA31_GlitchData, OutSignalName => "MGMTRDATA(31)", OutTemp => MGMTRDATA_OUT(31), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(0), GlitchData => MGMTPSO0_GlitchData, OutSignalName => "MGMTPSO(0)", OutTemp => MGMTPSO_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(0), GlitchData => MGMTPSO0_GlitchData, OutSignalName => "MGMTPSO(0)", OutTemp => MGMTPSO_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(1), GlitchData => MGMTPSO1_GlitchData, OutSignalName => "MGMTPSO(1)", OutTemp => MGMTPSO_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(1), GlitchData => MGMTPSO1_GlitchData, OutSignalName => "MGMTPSO(1)", OutTemp => MGMTPSO_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(2), GlitchData => MGMTPSO2_GlitchData, OutSignalName => "MGMTPSO(2)", OutTemp => MGMTPSO_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(2), GlitchData => MGMTPSO2_GlitchData, OutSignalName => "MGMTPSO(2)", OutTemp => MGMTPSO_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(3), GlitchData => MGMTPSO3_GlitchData, OutSignalName => "MGMTPSO(3)", OutTemp => MGMTPSO_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(3), GlitchData => MGMTPSO3_GlitchData, OutSignalName => "MGMTPSO(3)", OutTemp => MGMTPSO_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(4), GlitchData => MGMTPSO4_GlitchData, OutSignalName => "MGMTPSO(4)", OutTemp => MGMTPSO_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(4), GlitchData => MGMTPSO4_GlitchData, OutSignalName => "MGMTPSO(4)", OutTemp => MGMTPSO_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(5), GlitchData => MGMTPSO5_GlitchData, OutSignalName => "MGMTPSO(5)", OutTemp => MGMTPSO_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(5), GlitchData => MGMTPSO5_GlitchData, OutSignalName => "MGMTPSO(5)", OutTemp => MGMTPSO_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(6), GlitchData => MGMTPSO6_GlitchData, OutSignalName => "MGMTPSO(6)", OutTemp => MGMTPSO_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(6), GlitchData => MGMTPSO6_GlitchData, OutSignalName => "MGMTPSO(6)", OutTemp => MGMTPSO_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(7), GlitchData => MGMTPSO7_GlitchData, OutSignalName => "MGMTPSO(7)", OutTemp => MGMTPSO_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(7), GlitchData => MGMTPSO7_GlitchData, OutSignalName => "MGMTPSO(7)", OutTemp => MGMTPSO_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(8), GlitchData => MGMTPSO8_GlitchData, OutSignalName => "MGMTPSO(8)", OutTemp => MGMTPSO_OUT(8), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(8), GlitchData => MGMTPSO8_GlitchData, OutSignalName => "MGMTPSO(8)", OutTemp => MGMTPSO_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(9), GlitchData => MGMTPSO9_GlitchData, OutSignalName => "MGMTPSO(9)", OutTemp => MGMTPSO_OUT(9), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(9), GlitchData => MGMTPSO9_GlitchData, OutSignalName => "MGMTPSO(9)", OutTemp => MGMTPSO_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(10), GlitchData => MGMTPSO10_GlitchData, OutSignalName => "MGMTPSO(10)", OutTemp => MGMTPSO_OUT(10), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(10), GlitchData => MGMTPSO10_GlitchData, OutSignalName => "MGMTPSO(10)", OutTemp => MGMTPSO_OUT(10), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(11), GlitchData => MGMTPSO11_GlitchData, OutSignalName => "MGMTPSO(11)", OutTemp => MGMTPSO_OUT(11), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(11), GlitchData => MGMTPSO11_GlitchData, OutSignalName => "MGMTPSO(11)", OutTemp => MGMTPSO_OUT(11), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(12), GlitchData => MGMTPSO12_GlitchData, OutSignalName => "MGMTPSO(12)", OutTemp => MGMTPSO_OUT(12), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(12), GlitchData => MGMTPSO12_GlitchData, OutSignalName => "MGMTPSO(12)", OutTemp => MGMTPSO_OUT(12), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(13), GlitchData => MGMTPSO13_GlitchData, OutSignalName => "MGMTPSO(13)", OutTemp => MGMTPSO_OUT(13), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(13), GlitchData => MGMTPSO13_GlitchData, OutSignalName => "MGMTPSO(13)", OutTemp => MGMTPSO_OUT(13), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(14), GlitchData => MGMTPSO14_GlitchData, OutSignalName => "MGMTPSO(14)", OutTemp => MGMTPSO_OUT(14), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(14), GlitchData => MGMTPSO14_GlitchData, OutSignalName => "MGMTPSO(14)", OutTemp => MGMTPSO_OUT(14), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(15), GlitchData => MGMTPSO15_GlitchData, OutSignalName => "MGMTPSO(15)", OutTemp => MGMTPSO_OUT(15), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(15), GlitchData => MGMTPSO15_GlitchData, OutSignalName => "MGMTPSO(15)", OutTemp => MGMTPSO_OUT(15), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(16), GlitchData => MGMTPSO16_GlitchData, OutSignalName => "MGMTPSO(16)", OutTemp => MGMTPSO_OUT(16), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTPSO(16), GlitchData => MGMTPSO16_GlitchData, OutSignalName => "MGMTPSO(16)", OutTemp => MGMTPSO_OUT(16), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(0), GlitchData => MGMTSTATSCREDIT0_GlitchData, OutSignalName => "MGMTSTATSCREDIT(0)", OutTemp => MGMTSTATSCREDIT_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(0), GlitchData => MGMTSTATSCREDIT0_GlitchData, OutSignalName => "MGMTSTATSCREDIT(0)", OutTemp => MGMTSTATSCREDIT_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(1), GlitchData => MGMTSTATSCREDIT1_GlitchData, OutSignalName => "MGMTSTATSCREDIT(1)", OutTemp => MGMTSTATSCREDIT_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(1), GlitchData => MGMTSTATSCREDIT1_GlitchData, OutSignalName => "MGMTSTATSCREDIT(1)", OutTemp => MGMTSTATSCREDIT_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(2), GlitchData => MGMTSTATSCREDIT2_GlitchData, OutSignalName => "MGMTSTATSCREDIT(2)", OutTemp => MGMTSTATSCREDIT_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(2), GlitchData => MGMTSTATSCREDIT2_GlitchData, OutSignalName => "MGMTSTATSCREDIT(2)", OutTemp => MGMTSTATSCREDIT_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(3), GlitchData => MGMTSTATSCREDIT3_GlitchData, OutSignalName => "MGMTSTATSCREDIT(3)", OutTemp => MGMTSTATSCREDIT_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(3), GlitchData => MGMTSTATSCREDIT3_GlitchData, OutSignalName => "MGMTSTATSCREDIT(3)", OutTemp => MGMTSTATSCREDIT_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(4), GlitchData => MGMTSTATSCREDIT4_GlitchData, OutSignalName => "MGMTSTATSCREDIT(4)", OutTemp => MGMTSTATSCREDIT_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(4), GlitchData => MGMTSTATSCREDIT4_GlitchData, OutSignalName => "MGMTSTATSCREDIT(4)", OutTemp => MGMTSTATSCREDIT_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(5), GlitchData => MGMTSTATSCREDIT5_GlitchData, OutSignalName => "MGMTSTATSCREDIT(5)", OutTemp => MGMTSTATSCREDIT_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(5), GlitchData => MGMTSTATSCREDIT5_GlitchData, OutSignalName => "MGMTSTATSCREDIT(5)", OutTemp => MGMTSTATSCREDIT_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(6), GlitchData => MGMTSTATSCREDIT6_GlitchData, OutSignalName => "MGMTSTATSCREDIT(6)", OutTemp => MGMTSTATSCREDIT_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(6), GlitchData => MGMTSTATSCREDIT6_GlitchData, OutSignalName => "MGMTSTATSCREDIT(6)", OutTemp => MGMTSTATSCREDIT_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(7), GlitchData => MGMTSTATSCREDIT7_GlitchData, OutSignalName => "MGMTSTATSCREDIT(7)", OutTemp => MGMTSTATSCREDIT_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(7), GlitchData => MGMTSTATSCREDIT7_GlitchData, OutSignalName => "MGMTSTATSCREDIT(7)", OutTemp => MGMTSTATSCREDIT_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(8), GlitchData => MGMTSTATSCREDIT8_GlitchData, OutSignalName => "MGMTSTATSCREDIT(8)", OutTemp => MGMTSTATSCREDIT_OUT(8), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(8), GlitchData => MGMTSTATSCREDIT8_GlitchData, OutSignalName => "MGMTSTATSCREDIT(8)", OutTemp => MGMTSTATSCREDIT_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(9), GlitchData => MGMTSTATSCREDIT9_GlitchData, OutSignalName => "MGMTSTATSCREDIT(9)", OutTemp => MGMTSTATSCREDIT_OUT(9), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(9), GlitchData => MGMTSTATSCREDIT9_GlitchData, OutSignalName => "MGMTSTATSCREDIT(9)", OutTemp => MGMTSTATSCREDIT_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(10), GlitchData => MGMTSTATSCREDIT10_GlitchData, OutSignalName => "MGMTSTATSCREDIT(10)", OutTemp => MGMTSTATSCREDIT_OUT(10), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(10), GlitchData => MGMTSTATSCREDIT10_GlitchData, OutSignalName => "MGMTSTATSCREDIT(10)", OutTemp => MGMTSTATSCREDIT_OUT(10), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(11), GlitchData => MGMTSTATSCREDIT11_GlitchData, OutSignalName => "MGMTSTATSCREDIT(11)", OutTemp => MGMTSTATSCREDIT_OUT(11), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MGMTSTATSCREDIT(11), GlitchData => MGMTSTATSCREDIT11_GlitchData, OutSignalName => "MGMTSTATSCREDIT(11)", OutTemp => MGMTSTATSCREDIT_OUT(11), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLTLPECRCOK, GlitchData => L0RXDLLTLPECRCOK_GlitchData, OutSignalName => "L0RXDLLTLPECRCOK", OutTemp => L0RXDLLTLPECRCOK_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DLLTXPMDLLPOUTSTANDING, GlitchData => DLLTXPMDLLPOUTSTANDING_GlitchData, OutSignalName => "DLLTXPMDLLPOUTSTANDING", OutTemp => DLLTXPMDLLPOUTSTANDING_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0FIRSTCFGWRITEOCCURRED, GlitchData => L0FIRSTCFGWRITEOCCURRED_GlitchData, OutSignalName => "L0FIRSTCFGWRITEOCCURRED", OutTemp => L0FIRSTCFGWRITEOCCURRED_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0FIRSTCFGWRITEOCCURRED, GlitchData => L0FIRSTCFGWRITEOCCURRED_GlitchData, OutSignalName => "L0FIRSTCFGWRITEOCCURRED", OutTemp => L0FIRSTCFGWRITEOCCURRED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0CFGLOOPBACKACK, GlitchData => L0CFGLOOPBACKACK_GlitchData, OutSignalName => "L0CFGLOOPBACKACK", OutTemp => L0CFGLOOPBACKACK_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MACUPSTREAMDOWNSTREAM, GlitchData => L0MACUPSTREAMDOWNSTREAM_GlitchData, OutSignalName => "L0MACUPSTREAMDOWNSTREAM", OutTemp => L0MACUPSTREAMDOWNSTREAM_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXMACLINKERROR(0), GlitchData => L0RXMACLINKERROR0_GlitchData, OutSignalName => "L0RXMACLINKERROR(0)", OutTemp => L0RXMACLINKERROR_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXMACLINKERROR(1), GlitchData => L0RXMACLINKERROR1_GlitchData, OutSignalName => "L0RXMACLINKERROR(1)", OutTemp => L0RXMACLINKERROR_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MACLINKUP, GlitchData => L0MACLINKUP_GlitchData, OutSignalName => "L0MACLINKUP", OutTemp => L0MACLINKUP_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MACNEGOTIATEDLINKWIDTH(0), GlitchData => L0MACNEGOTIATEDLINKWIDTH0_GlitchData, OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(0)", OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MACNEGOTIATEDLINKWIDTH(1), GlitchData => L0MACNEGOTIATEDLINKWIDTH1_GlitchData, OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(1)", OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MACNEGOTIATEDLINKWIDTH(2), GlitchData => L0MACNEGOTIATEDLINKWIDTH2_GlitchData, OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(2)", OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MACNEGOTIATEDLINKWIDTH(3), GlitchData => L0MACNEGOTIATEDLINKWIDTH3_GlitchData, OutSignalName => "L0MACNEGOTIATEDLINKWIDTH(3)", OutTemp => L0MACNEGOTIATEDLINKWIDTH_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MACLINKTRAINING, GlitchData => L0MACLINKTRAINING_GlitchData, OutSignalName => "L0MACLINKTRAINING", OutTemp => L0MACLINKTRAINING_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0LTSSMSTATE(0), GlitchData => L0LTSSMSTATE0_GlitchData, OutSignalName => "L0LTSSMSTATE(0)", OutTemp => L0LTSSMSTATE_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0LTSSMSTATE(1), GlitchData => L0LTSSMSTATE1_GlitchData, OutSignalName => "L0LTSSMSTATE(1)", OutTemp => L0LTSSMSTATE_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0LTSSMSTATE(2), GlitchData => L0LTSSMSTATE2_GlitchData, OutSignalName => "L0LTSSMSTATE(2)", OutTemp => L0LTSSMSTATE_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0LTSSMSTATE(3), GlitchData => L0LTSSMSTATE3_GlitchData, OutSignalName => "L0LTSSMSTATE(3)", OutTemp => L0LTSSMSTATE_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLVCSTATUS(0), GlitchData => L0DLLVCSTATUS0_GlitchData, OutSignalName => "L0DLLVCSTATUS(0)", OutTemp => L0DLLVCSTATUS_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLVCSTATUS(1), GlitchData => L0DLLVCSTATUS1_GlitchData, OutSignalName => "L0DLLVCSTATUS(1)", OutTemp => L0DLLVCSTATUS_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLVCSTATUS(2), GlitchData => L0DLLVCSTATUS2_GlitchData, OutSignalName => "L0DLLVCSTATUS(2)", OutTemp => L0DLLVCSTATUS_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLVCSTATUS(3), GlitchData => L0DLLVCSTATUS3_GlitchData, OutSignalName => "L0DLLVCSTATUS(3)", OutTemp => L0DLLVCSTATUS_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLVCSTATUS(4), GlitchData => L0DLLVCSTATUS4_GlitchData, OutSignalName => "L0DLLVCSTATUS(4)", OutTemp => L0DLLVCSTATUS_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLVCSTATUS(5), GlitchData => L0DLLVCSTATUS5_GlitchData, OutSignalName => "L0DLLVCSTATUS(5)", OutTemp => L0DLLVCSTATUS_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLVCSTATUS(6), GlitchData => L0DLLVCSTATUS6_GlitchData, OutSignalName => "L0DLLVCSTATUS(6)", OutTemp => L0DLLVCSTATUS_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLVCSTATUS(7), GlitchData => L0DLLVCSTATUS7_GlitchData, OutSignalName => "L0DLLVCSTATUS(7)", OutTemp => L0DLLVCSTATUS_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLUPDOWN(0), GlitchData => L0DLUPDOWN0_GlitchData, OutSignalName => "L0DLUPDOWN(0)", OutTemp => L0DLUPDOWN_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLUPDOWN(1), GlitchData => L0DLUPDOWN1_GlitchData, OutSignalName => "L0DLUPDOWN(1)", OutTemp => L0DLUPDOWN_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLUPDOWN(2), GlitchData => L0DLUPDOWN2_GlitchData, OutSignalName => "L0DLUPDOWN(2)", OutTemp => L0DLUPDOWN_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLUPDOWN(3), GlitchData => L0DLUPDOWN3_GlitchData, OutSignalName => "L0DLUPDOWN(3)", OutTemp => L0DLUPDOWN_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLUPDOWN(4), GlitchData => L0DLUPDOWN4_GlitchData, OutSignalName => "L0DLUPDOWN(4)", OutTemp => L0DLUPDOWN_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLUPDOWN(5), GlitchData => L0DLUPDOWN5_GlitchData, OutSignalName => "L0DLUPDOWN(5)", OutTemp => L0DLUPDOWN_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLUPDOWN(6), GlitchData => L0DLUPDOWN6_GlitchData, OutSignalName => "L0DLUPDOWN(6)", OutTemp => L0DLUPDOWN_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLUPDOWN(7), GlitchData => L0DLUPDOWN7_GlitchData, OutSignalName => "L0DLUPDOWN(7)", OutTemp => L0DLUPDOWN_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLERRORVECTOR(0), GlitchData => L0DLLERRORVECTOR0_GlitchData, OutSignalName => "L0DLLERRORVECTOR(0)", OutTemp => L0DLLERRORVECTOR_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLERRORVECTOR(1), GlitchData => L0DLLERRORVECTOR1_GlitchData, OutSignalName => "L0DLLERRORVECTOR(1)", OutTemp => L0DLLERRORVECTOR_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLERRORVECTOR(2), GlitchData => L0DLLERRORVECTOR2_GlitchData, OutSignalName => "L0DLLERRORVECTOR(2)", OutTemp => L0DLLERRORVECTOR_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLERRORVECTOR(3), GlitchData => L0DLLERRORVECTOR3_GlitchData, OutSignalName => "L0DLLERRORVECTOR(3)", OutTemp => L0DLLERRORVECTOR_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLERRORVECTOR(4), GlitchData => L0DLLERRORVECTOR4_GlitchData, OutSignalName => "L0DLLERRORVECTOR(4)", OutTemp => L0DLLERRORVECTOR_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLERRORVECTOR(5), GlitchData => L0DLLERRORVECTOR5_GlitchData, OutSignalName => "L0DLLERRORVECTOR(5)", OutTemp => L0DLLERRORVECTOR_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLERRORVECTOR(6), GlitchData => L0DLLERRORVECTOR6_GlitchData, OutSignalName => "L0DLLERRORVECTOR(6)", OutTemp => L0DLLERRORVECTOR_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLASRXSTATE(0), GlitchData => L0DLLASRXSTATE0_GlitchData, OutSignalName => "L0DLLASRXSTATE(0)", OutTemp => L0DLLASRXSTATE_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLASRXSTATE(1), GlitchData => L0DLLASRXSTATE1_GlitchData, OutSignalName => "L0DLLASRXSTATE(1)", OutTemp => L0DLLASRXSTATE_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLASTXSTATE, GlitchData => L0DLLASTXSTATE_GlitchData, OutSignalName => "L0DLLASTXSTATE", OutTemp => L0DLLASTXSTATE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ASAUTONOMOUSINITCOMPLETED, GlitchData => L0ASAUTONOMOUSINITCOMPLETED_GlitchData, OutSignalName => "L0ASAUTONOMOUSINITCOMPLETED", OutTemp => L0ASAUTONOMOUSINITCOMPLETED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(0), GlitchData => L0COMPLETERID0_GlitchData, OutSignalName => "L0COMPLETERID(0)", OutTemp => L0COMPLETERID_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(0), GlitchData => L0COMPLETERID0_GlitchData, OutSignalName => "L0COMPLETERID(0)", OutTemp => L0COMPLETERID_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(1), GlitchData => L0COMPLETERID1_GlitchData, OutSignalName => "L0COMPLETERID(1)", OutTemp => L0COMPLETERID_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(1), GlitchData => L0COMPLETERID1_GlitchData, OutSignalName => "L0COMPLETERID(1)", OutTemp => L0COMPLETERID_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(2), GlitchData => L0COMPLETERID2_GlitchData, OutSignalName => "L0COMPLETERID(2)", OutTemp => L0COMPLETERID_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(2), GlitchData => L0COMPLETERID2_GlitchData, OutSignalName => "L0COMPLETERID(2)", OutTemp => L0COMPLETERID_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(3), GlitchData => L0COMPLETERID3_GlitchData, OutSignalName => "L0COMPLETERID(3)", OutTemp => L0COMPLETERID_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(3), GlitchData => L0COMPLETERID3_GlitchData, OutSignalName => "L0COMPLETERID(3)", OutTemp => L0COMPLETERID_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(4), GlitchData => L0COMPLETERID4_GlitchData, OutSignalName => "L0COMPLETERID(4)", OutTemp => L0COMPLETERID_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(4), GlitchData => L0COMPLETERID4_GlitchData, OutSignalName => "L0COMPLETERID(4)", OutTemp => L0COMPLETERID_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(5), GlitchData => L0COMPLETERID5_GlitchData, OutSignalName => "L0COMPLETERID(5)", OutTemp => L0COMPLETERID_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(5), GlitchData => L0COMPLETERID5_GlitchData, OutSignalName => "L0COMPLETERID(5)", OutTemp => L0COMPLETERID_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(6), GlitchData => L0COMPLETERID6_GlitchData, OutSignalName => "L0COMPLETERID(6)", OutTemp => L0COMPLETERID_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(6), GlitchData => L0COMPLETERID6_GlitchData, OutSignalName => "L0COMPLETERID(6)", OutTemp => L0COMPLETERID_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(7), GlitchData => L0COMPLETERID7_GlitchData, OutSignalName => "L0COMPLETERID(7)", OutTemp => L0COMPLETERID_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(7), GlitchData => L0COMPLETERID7_GlitchData, OutSignalName => "L0COMPLETERID(7)", OutTemp => L0COMPLETERID_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(8), GlitchData => L0COMPLETERID8_GlitchData, OutSignalName => "L0COMPLETERID(8)", OutTemp => L0COMPLETERID_OUT(8), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(8), GlitchData => L0COMPLETERID8_GlitchData, OutSignalName => "L0COMPLETERID(8)", OutTemp => L0COMPLETERID_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(9), GlitchData => L0COMPLETERID9_GlitchData, OutSignalName => "L0COMPLETERID(9)", OutTemp => L0COMPLETERID_OUT(9), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(9), GlitchData => L0COMPLETERID9_GlitchData, OutSignalName => "L0COMPLETERID(9)", OutTemp => L0COMPLETERID_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(10), GlitchData => L0COMPLETERID10_GlitchData, OutSignalName => "L0COMPLETERID(10)", OutTemp => L0COMPLETERID_OUT(10), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(10), GlitchData => L0COMPLETERID10_GlitchData, OutSignalName => "L0COMPLETERID(10)", OutTemp => L0COMPLETERID_OUT(10), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(11), GlitchData => L0COMPLETERID11_GlitchData, OutSignalName => "L0COMPLETERID(11)", OutTemp => L0COMPLETERID_OUT(11), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(11), GlitchData => L0COMPLETERID11_GlitchData, OutSignalName => "L0COMPLETERID(11)", OutTemp => L0COMPLETERID_OUT(11), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(12), GlitchData => L0COMPLETERID12_GlitchData, OutSignalName => "L0COMPLETERID(12)", OutTemp => L0COMPLETERID_OUT(12), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0COMPLETERID(12), GlitchData => L0COMPLETERID12_GlitchData, OutSignalName => "L0COMPLETERID(12)", OutTemp => L0COMPLETERID_OUT(12), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0UNLOCKRECEIVED, GlitchData => L0UNLOCKRECEIVED_GlitchData, OutSignalName => "L0UNLOCKRECEIVED", OutTemp => L0UNLOCKRECEIVED_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0UNLOCKRECEIVED, GlitchData => L0UNLOCKRECEIVED_GlitchData, OutSignalName => "L0UNLOCKRECEIVED", OutTemp => L0UNLOCKRECEIVED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0CORRERRMSGRCVD, GlitchData => L0CORRERRMSGRCVD_GlitchData, OutSignalName => "L0CORRERRMSGRCVD", OutTemp => L0CORRERRMSGRCVD_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0CORRERRMSGRCVD, GlitchData => L0CORRERRMSGRCVD_GlitchData, OutSignalName => "L0CORRERRMSGRCVD", OutTemp => L0CORRERRMSGRCVD_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0FATALERRMSGRCVD, GlitchData => L0FATALERRMSGRCVD_GlitchData, OutSignalName => "L0FATALERRMSGRCVD", OutTemp => L0FATALERRMSGRCVD_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0FATALERRMSGRCVD, GlitchData => L0FATALERRMSGRCVD_GlitchData, OutSignalName => "L0FATALERRMSGRCVD", OutTemp => L0FATALERRMSGRCVD_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0NONFATALERRMSGRCVD, GlitchData => L0NONFATALERRMSGRCVD_GlitchData, OutSignalName => "L0NONFATALERRMSGRCVD", OutTemp => L0NONFATALERRMSGRCVD_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0NONFATALERRMSGRCVD, GlitchData => L0NONFATALERRMSGRCVD_GlitchData, OutSignalName => "L0NONFATALERRMSGRCVD", OutTemp => L0NONFATALERRMSGRCVD_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(0), GlitchData => L0ERRMSGREQID0_GlitchData, OutSignalName => "L0ERRMSGREQID(0)", OutTemp => L0ERRMSGREQID_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(0), GlitchData => L0ERRMSGREQID0_GlitchData, OutSignalName => "L0ERRMSGREQID(0)", OutTemp => L0ERRMSGREQID_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(1), GlitchData => L0ERRMSGREQID1_GlitchData, OutSignalName => "L0ERRMSGREQID(1)", OutTemp => L0ERRMSGREQID_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(1), GlitchData => L0ERRMSGREQID1_GlitchData, OutSignalName => "L0ERRMSGREQID(1)", OutTemp => L0ERRMSGREQID_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(2), GlitchData => L0ERRMSGREQID2_GlitchData, OutSignalName => "L0ERRMSGREQID(2)", OutTemp => L0ERRMSGREQID_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(2), GlitchData => L0ERRMSGREQID2_GlitchData, OutSignalName => "L0ERRMSGREQID(2)", OutTemp => L0ERRMSGREQID_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(3), GlitchData => L0ERRMSGREQID3_GlitchData, OutSignalName => "L0ERRMSGREQID(3)", OutTemp => L0ERRMSGREQID_OUT(3), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(3), GlitchData => L0ERRMSGREQID3_GlitchData, OutSignalName => "L0ERRMSGREQID(3)", OutTemp => L0ERRMSGREQID_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(4), GlitchData => L0ERRMSGREQID4_GlitchData, OutSignalName => "L0ERRMSGREQID(4)", OutTemp => L0ERRMSGREQID_OUT(4), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(4), GlitchData => L0ERRMSGREQID4_GlitchData, OutSignalName => "L0ERRMSGREQID(4)", OutTemp => L0ERRMSGREQID_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(5), GlitchData => L0ERRMSGREQID5_GlitchData, OutSignalName => "L0ERRMSGREQID(5)", OutTemp => L0ERRMSGREQID_OUT(5), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(5), GlitchData => L0ERRMSGREQID5_GlitchData, OutSignalName => "L0ERRMSGREQID(5)", OutTemp => L0ERRMSGREQID_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(6), GlitchData => L0ERRMSGREQID6_GlitchData, OutSignalName => "L0ERRMSGREQID(6)", OutTemp => L0ERRMSGREQID_OUT(6), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(6), GlitchData => L0ERRMSGREQID6_GlitchData, OutSignalName => "L0ERRMSGREQID(6)", OutTemp => L0ERRMSGREQID_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(7), GlitchData => L0ERRMSGREQID7_GlitchData, OutSignalName => "L0ERRMSGREQID(7)", OutTemp => L0ERRMSGREQID_OUT(7), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(7), GlitchData => L0ERRMSGREQID7_GlitchData, OutSignalName => "L0ERRMSGREQID(7)", OutTemp => L0ERRMSGREQID_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(8), GlitchData => L0ERRMSGREQID8_GlitchData, OutSignalName => "L0ERRMSGREQID(8)", OutTemp => L0ERRMSGREQID_OUT(8), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(8), GlitchData => L0ERRMSGREQID8_GlitchData, OutSignalName => "L0ERRMSGREQID(8)", OutTemp => L0ERRMSGREQID_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(9), GlitchData => L0ERRMSGREQID9_GlitchData, OutSignalName => "L0ERRMSGREQID(9)", OutTemp => L0ERRMSGREQID_OUT(9), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(9), GlitchData => L0ERRMSGREQID9_GlitchData, OutSignalName => "L0ERRMSGREQID(9)", OutTemp => L0ERRMSGREQID_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(10), GlitchData => L0ERRMSGREQID10_GlitchData, OutSignalName => "L0ERRMSGREQID(10)", OutTemp => L0ERRMSGREQID_OUT(10), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(10), GlitchData => L0ERRMSGREQID10_GlitchData, OutSignalName => "L0ERRMSGREQID(10)", OutTemp => L0ERRMSGREQID_OUT(10), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(11), GlitchData => L0ERRMSGREQID11_GlitchData, OutSignalName => "L0ERRMSGREQID(11)", OutTemp => L0ERRMSGREQID_OUT(11), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(11), GlitchData => L0ERRMSGREQID11_GlitchData, OutSignalName => "L0ERRMSGREQID(11)", OutTemp => L0ERRMSGREQID_OUT(11), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(12), GlitchData => L0ERRMSGREQID12_GlitchData, OutSignalName => "L0ERRMSGREQID(12)", OutTemp => L0ERRMSGREQID_OUT(12), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(12), GlitchData => L0ERRMSGREQID12_GlitchData, OutSignalName => "L0ERRMSGREQID(12)", OutTemp => L0ERRMSGREQID_OUT(12), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(13), GlitchData => L0ERRMSGREQID13_GlitchData, OutSignalName => "L0ERRMSGREQID(13)", OutTemp => L0ERRMSGREQID_OUT(13), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(13), GlitchData => L0ERRMSGREQID13_GlitchData, OutSignalName => "L0ERRMSGREQID(13)", OutTemp => L0ERRMSGREQID_OUT(13), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(14), GlitchData => L0ERRMSGREQID14_GlitchData, OutSignalName => "L0ERRMSGREQID(14)", OutTemp => L0ERRMSGREQID_OUT(14), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(14), GlitchData => L0ERRMSGREQID14_GlitchData, OutSignalName => "L0ERRMSGREQID(14)", OutTemp => L0ERRMSGREQID_OUT(14), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(15), GlitchData => L0ERRMSGREQID15_GlitchData, OutSignalName => "L0ERRMSGREQID(15)", OutTemp => L0ERRMSGREQID_OUT(15), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ERRMSGREQID(15), GlitchData => L0ERRMSGREQID15_GlitchData, OutSignalName => "L0ERRMSGREQID(15)", OutTemp => L0ERRMSGREQID_OUT(15), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0FWDCORRERROUT, GlitchData => L0FWDCORRERROUT_GlitchData, OutSignalName => "L0FWDCORRERROUT", OutTemp => L0FWDCORRERROUT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0FWDCORRERROUT, GlitchData => L0FWDCORRERROUT_GlitchData, OutSignalName => "L0FWDCORRERROUT", OutTemp => L0FWDCORRERROUT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0FWDFATALERROUT, GlitchData => L0FWDFATALERROUT_GlitchData, OutSignalName => "L0FWDFATALERROUT", OutTemp => L0FWDFATALERROUT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0FWDFATALERROUT, GlitchData => L0FWDFATALERROUT_GlitchData, OutSignalName => "L0FWDFATALERROUT", OutTemp => L0FWDFATALERROUT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0FWDNONFATALERROUT, GlitchData => L0FWDNONFATALERROUT_GlitchData, OutSignalName => "L0FWDNONFATALERROUT", OutTemp => L0FWDNONFATALERROUT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0FWDNONFATALERROUT, GlitchData => L0FWDNONFATALERROUT_GlitchData, OutSignalName => "L0FWDNONFATALERROUT", OutTemp => L0FWDNONFATALERROUT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDASSERTINTALEGACYINT, GlitchData => L0RECEIVEDASSERTINTALEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDASSERTINTALEGACYINT", OutTemp => L0RECEIVEDASSERTINTALEGACYINT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDASSERTINTALEGACYINT, GlitchData => L0RECEIVEDASSERTINTALEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDASSERTINTALEGACYINT", OutTemp => L0RECEIVEDASSERTINTALEGACYINT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDASSERTINTBLEGACYINT, GlitchData => L0RECEIVEDASSERTINTBLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDASSERTINTBLEGACYINT", OutTemp => L0RECEIVEDASSERTINTBLEGACYINT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDASSERTINTBLEGACYINT, GlitchData => L0RECEIVEDASSERTINTBLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDASSERTINTBLEGACYINT", OutTemp => L0RECEIVEDASSERTINTBLEGACYINT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDASSERTINTCLEGACYINT, GlitchData => L0RECEIVEDASSERTINTCLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDASSERTINTCLEGACYINT", OutTemp => L0RECEIVEDASSERTINTCLEGACYINT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDASSERTINTCLEGACYINT, GlitchData => L0RECEIVEDASSERTINTCLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDASSERTINTCLEGACYINT", OutTemp => L0RECEIVEDASSERTINTCLEGACYINT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDASSERTINTDLEGACYINT, GlitchData => L0RECEIVEDASSERTINTDLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDASSERTINTDLEGACYINT", OutTemp => L0RECEIVEDASSERTINTDLEGACYINT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDASSERTINTDLEGACYINT, GlitchData => L0RECEIVEDASSERTINTDLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDASSERTINTDLEGACYINT", OutTemp => L0RECEIVEDASSERTINTDLEGACYINT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDDEASSERTINTALEGACYINT, GlitchData => L0RECEIVEDDEASSERTINTALEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDDEASSERTINTALEGACYINT", OutTemp => L0RECEIVEDDEASSERTINTALEGACYINT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDDEASSERTINTALEGACYINT, GlitchData => L0RECEIVEDDEASSERTINTALEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDDEASSERTINTALEGACYINT", OutTemp => L0RECEIVEDDEASSERTINTALEGACYINT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDDEASSERTINTBLEGACYINT, GlitchData => L0RECEIVEDDEASSERTINTBLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDDEASSERTINTBLEGACYINT", OutTemp => L0RECEIVEDDEASSERTINTBLEGACYINT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDDEASSERTINTBLEGACYINT, GlitchData => L0RECEIVEDDEASSERTINTBLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDDEASSERTINTBLEGACYINT", OutTemp => L0RECEIVEDDEASSERTINTBLEGACYINT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDDEASSERTINTCLEGACYINT, GlitchData => L0RECEIVEDDEASSERTINTCLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDDEASSERTINTCLEGACYINT", OutTemp => L0RECEIVEDDEASSERTINTCLEGACYINT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDDEASSERTINTCLEGACYINT, GlitchData => L0RECEIVEDDEASSERTINTCLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDDEASSERTINTCLEGACYINT", OutTemp => L0RECEIVEDDEASSERTINTCLEGACYINT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDDEASSERTINTDLEGACYINT, GlitchData => L0RECEIVEDDEASSERTINTDLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDDEASSERTINTDLEGACYINT", OutTemp => L0RECEIVEDDEASSERTINTDLEGACYINT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RECEIVEDDEASSERTINTDLEGACYINT, GlitchData => L0RECEIVEDDEASSERTINTDLEGACYINT_GlitchData, OutSignalName => "L0RECEIVEDDEASSERTINTDLEGACYINT", OutTemp => L0RECEIVEDDEASSERTINTDLEGACYINT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MSIENABLE0, GlitchData => L0MSIENABLE0_GlitchData, OutSignalName => "L0MSIENABLE0", OutTemp => L0MSIENABLE0_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MSIENABLE0, GlitchData => L0MSIENABLE0_GlitchData, OutSignalName => "L0MSIENABLE0", OutTemp => L0MSIENABLE0_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MULTIMSGEN0(0), GlitchData => L0MULTIMSGEN00_GlitchData, OutSignalName => "L0MULTIMSGEN0(0)", OutTemp => L0MULTIMSGEN0_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MULTIMSGEN0(0), GlitchData => L0MULTIMSGEN00_GlitchData, OutSignalName => "L0MULTIMSGEN0(0)", OutTemp => L0MULTIMSGEN0_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MULTIMSGEN0(1), GlitchData => L0MULTIMSGEN01_GlitchData, OutSignalName => "L0MULTIMSGEN0(1)", OutTemp => L0MULTIMSGEN0_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MULTIMSGEN0(1), GlitchData => L0MULTIMSGEN01_GlitchData, OutSignalName => "L0MULTIMSGEN0(1)", OutTemp => L0MULTIMSGEN0_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MULTIMSGEN0(2), GlitchData => L0MULTIMSGEN02_GlitchData, OutSignalName => "L0MULTIMSGEN0(2)", OutTemp => L0MULTIMSGEN0_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MULTIMSGEN0(2), GlitchData => L0MULTIMSGEN02_GlitchData, OutSignalName => "L0MULTIMSGEN0(2)", OutTemp => L0MULTIMSGEN0_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSDLLPRECEIVED, GlitchData => L0STATSDLLPRECEIVED_GlitchData, OutSignalName => "L0STATSDLLPRECEIVED", OutTemp => L0STATSDLLPRECEIVED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSDLLPTRANSMITTED, GlitchData => L0STATSDLLPTRANSMITTED_GlitchData, OutSignalName => "L0STATSDLLPTRANSMITTED", OutTemp => L0STATSDLLPTRANSMITTED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSOSRECEIVED, GlitchData => L0STATSOSRECEIVED_GlitchData, OutSignalName => "L0STATSOSRECEIVED", OutTemp => L0STATSOSRECEIVED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSOSTRANSMITTED, GlitchData => L0STATSOSTRANSMITTED_GlitchData, OutSignalName => "L0STATSOSTRANSMITTED", OutTemp => L0STATSOSTRANSMITTED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSTLPRECEIVED, GlitchData => L0STATSTLPRECEIVED_GlitchData, OutSignalName => "L0STATSTLPRECEIVED", OutTemp => L0STATSTLPRECEIVED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSTLPTRANSMITTED, GlitchData => L0STATSTLPTRANSMITTED_GlitchData, OutSignalName => "L0STATSTLPTRANSMITTED", OutTemp => L0STATSTLPTRANSMITTED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSCFGRECEIVED, GlitchData => L0STATSCFGRECEIVED_GlitchData, OutSignalName => "L0STATSCFGRECEIVED", OutTemp => L0STATSCFGRECEIVED_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSCFGRECEIVED, GlitchData => L0STATSCFGRECEIVED_GlitchData, OutSignalName => "L0STATSCFGRECEIVED", OutTemp => L0STATSCFGRECEIVED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSCFGTRANSMITTED, GlitchData => L0STATSCFGTRANSMITTED_GlitchData, OutSignalName => "L0STATSCFGTRANSMITTED", OutTemp => L0STATSCFGTRANSMITTED_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSCFGTRANSMITTED, GlitchData => L0STATSCFGTRANSMITTED_GlitchData, OutSignalName => "L0STATSCFGTRANSMITTED", OutTemp => L0STATSCFGTRANSMITTED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSCFGOTHERRECEIVED, GlitchData => L0STATSCFGOTHERRECEIVED_GlitchData, OutSignalName => "L0STATSCFGOTHERRECEIVED", OutTemp => L0STATSCFGOTHERRECEIVED_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSCFGOTHERRECEIVED, GlitchData => L0STATSCFGOTHERRECEIVED_GlitchData, OutSignalName => "L0STATSCFGOTHERRECEIVED", OutTemp => L0STATSCFGOTHERRECEIVED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSCFGOTHERTRANSMITTED, GlitchData => L0STATSCFGOTHERTRANSMITTED_GlitchData, OutSignalName => "L0STATSCFGOTHERTRANSMITTED", OutTemp => L0STATSCFGOTHERTRANSMITTED_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0STATSCFGOTHERTRANSMITTED, GlitchData => L0STATSCFGOTHERTRANSMITTED_GlitchData, OutSignalName => "L0STATSCFGOTHERTRANSMITTED", OutTemp => L0STATSCFGOTHERTRANSMITTED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXPAYLOADSIZE(0), GlitchData => MAXPAYLOADSIZE0_GlitchData, OutSignalName => "MAXPAYLOADSIZE(0)", OutTemp => MAXPAYLOADSIZE_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXPAYLOADSIZE(0), GlitchData => MAXPAYLOADSIZE0_GlitchData, OutSignalName => "MAXPAYLOADSIZE(0)", OutTemp => MAXPAYLOADSIZE_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXPAYLOADSIZE(1), GlitchData => MAXPAYLOADSIZE1_GlitchData, OutSignalName => "MAXPAYLOADSIZE(1)", OutTemp => MAXPAYLOADSIZE_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXPAYLOADSIZE(1), GlitchData => MAXPAYLOADSIZE1_GlitchData, OutSignalName => "MAXPAYLOADSIZE(1)", OutTemp => MAXPAYLOADSIZE_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXPAYLOADSIZE(2), GlitchData => MAXPAYLOADSIZE2_GlitchData, OutSignalName => "MAXPAYLOADSIZE(2)", OutTemp => MAXPAYLOADSIZE_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXPAYLOADSIZE(2), GlitchData => MAXPAYLOADSIZE2_GlitchData, OutSignalName => "MAXPAYLOADSIZE(2)", OutTemp => MAXPAYLOADSIZE_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXREADREQUESTSIZE(0), GlitchData => MAXREADREQUESTSIZE0_GlitchData, OutSignalName => "MAXREADREQUESTSIZE(0)", OutTemp => MAXREADREQUESTSIZE_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXREADREQUESTSIZE(0), GlitchData => MAXREADREQUESTSIZE0_GlitchData, OutSignalName => "MAXREADREQUESTSIZE(0)", OutTemp => MAXREADREQUESTSIZE_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXREADREQUESTSIZE(1), GlitchData => MAXREADREQUESTSIZE1_GlitchData, OutSignalName => "MAXREADREQUESTSIZE(1)", OutTemp => MAXREADREQUESTSIZE_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXREADREQUESTSIZE(1), GlitchData => MAXREADREQUESTSIZE1_GlitchData, OutSignalName => "MAXREADREQUESTSIZE(1)", OutTemp => MAXREADREQUESTSIZE_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXREADREQUESTSIZE(2), GlitchData => MAXREADREQUESTSIZE2_GlitchData, OutSignalName => "MAXREADREQUESTSIZE(2)", OutTemp => MAXREADREQUESTSIZE_OUT(2), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MAXREADREQUESTSIZE(2), GlitchData => MAXREADREQUESTSIZE2_GlitchData, OutSignalName => "MAXREADREQUESTSIZE(2)", OutTemp => MAXREADREQUESTSIZE_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => IOSPACEENABLE, GlitchData => IOSPACEENABLE_GlitchData, OutSignalName => "IOSPACEENABLE", OutTemp => IOSPACEENABLE_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => IOSPACEENABLE, GlitchData => IOSPACEENABLE_GlitchData, OutSignalName => "IOSPACEENABLE", OutTemp => IOSPACEENABLE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MEMSPACEENABLE, GlitchData => MEMSPACEENABLE_GlitchData, OutSignalName => "MEMSPACEENABLE", OutTemp => MEMSPACEENABLE_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MEMSPACEENABLE, GlitchData => MEMSPACEENABLE_GlitchData, OutSignalName => "MEMSPACEENABLE", OutTemp => MEMSPACEENABLE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ATTENTIONINDICATORCONTROL(0), GlitchData => L0ATTENTIONINDICATORCONTROL0_GlitchData, OutSignalName => "L0ATTENTIONINDICATORCONTROL(0)", OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ATTENTIONINDICATORCONTROL(0), GlitchData => L0ATTENTIONINDICATORCONTROL0_GlitchData, OutSignalName => "L0ATTENTIONINDICATORCONTROL(0)", OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ATTENTIONINDICATORCONTROL(1), GlitchData => L0ATTENTIONINDICATORCONTROL1_GlitchData, OutSignalName => "L0ATTENTIONINDICATORCONTROL(1)", OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0ATTENTIONINDICATORCONTROL(1), GlitchData => L0ATTENTIONINDICATORCONTROL1_GlitchData, OutSignalName => "L0ATTENTIONINDICATORCONTROL(1)", OutTemp => L0ATTENTIONINDICATORCONTROL_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0POWERINDICATORCONTROL(0), GlitchData => L0POWERINDICATORCONTROL0_GlitchData, OutSignalName => "L0POWERINDICATORCONTROL(0)", OutTemp => L0POWERINDICATORCONTROL_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0POWERINDICATORCONTROL(0), GlitchData => L0POWERINDICATORCONTROL0_GlitchData, OutSignalName => "L0POWERINDICATORCONTROL(0)", OutTemp => L0POWERINDICATORCONTROL_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0POWERINDICATORCONTROL(1), GlitchData => L0POWERINDICATORCONTROL1_GlitchData, OutSignalName => "L0POWERINDICATORCONTROL(1)", OutTemp => L0POWERINDICATORCONTROL_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0POWERINDICATORCONTROL(1), GlitchData => L0POWERINDICATORCONTROL1_GlitchData, OutSignalName => "L0POWERINDICATORCONTROL(1)", OutTemp => L0POWERINDICATORCONTROL_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0POWERCONTROLLERCONTROL, GlitchData => L0POWERCONTROLLERCONTROL_GlitchData, OutSignalName => "L0POWERCONTROLLERCONTROL", OutTemp => L0POWERCONTROLLERCONTROL_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0POWERCONTROLLERCONTROL, GlitchData => L0POWERCONTROLLERCONTROL_GlitchData, OutSignalName => "L0POWERCONTROLLERCONTROL", OutTemp => L0POWERCONTROLLERCONTROL_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TOGGLEELECTROMECHANICALINTERLOCK, GlitchData => L0TOGGLEELECTROMECHANICALINTERLOCK_GlitchData, OutSignalName => "L0TOGGLEELECTROMECHANICALINTERLOCK", OutTemp => L0TOGGLEELECTROMECHANICALINTERLOCK_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TOGGLEELECTROMECHANICALINTERLOCK, GlitchData => L0TOGGLEELECTROMECHANICALINTERLOCK_GlitchData, OutSignalName => "L0TOGGLEELECTROMECHANICALINTERLOCK", OutTemp => L0TOGGLEELECTROMECHANICALINTERLOCK_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXBEACON, GlitchData => L0RXBEACON_GlitchData, OutSignalName => "L0RXBEACON", OutTemp => L0RXBEACON_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXBEACON, GlitchData => L0RXBEACON_GlitchData, OutSignalName => "L0RXBEACON", OutTemp => L0RXBEACON_OUT, Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXBEACON, GlitchData => L0RXBEACON_GlitchData, OutSignalName => "L0RXBEACON", OutTemp => L0RXBEACON_OUT, Paths => (0 => (L0WAKEN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRSTATE0(0), GlitchData => L0PWRSTATE00_GlitchData, OutSignalName => "L0PWRSTATE0(0)", OutTemp => L0PWRSTATE0_OUT(0), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRSTATE0(0), GlitchData => L0PWRSTATE00_GlitchData, OutSignalName => "L0PWRSTATE0(0)", OutTemp => L0PWRSTATE0_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRSTATE0(1), GlitchData => L0PWRSTATE01_GlitchData, OutSignalName => "L0PWRSTATE0(1)", OutTemp => L0PWRSTATE0_OUT(1), Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRSTATE0(1), GlitchData => L0PWRSTATE01_GlitchData, OutSignalName => "L0PWRSTATE0(1)", OutTemp => L0PWRSTATE0_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PMEACK, GlitchData => L0PMEACK_GlitchData, OutSignalName => "L0PMEACK", OutTemp => L0PMEACK_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PMEACK, GlitchData => L0PMEACK_GlitchData, OutSignalName => "L0PMEACK", OutTemp => L0PMEACK_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PMEREQOUT, GlitchData => L0PMEREQOUT_GlitchData, OutSignalName => "L0PMEREQOUT", OutTemp => L0PMEREQOUT_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PMEREQOUT, GlitchData => L0PMEREQOUT_GlitchData, OutSignalName => "L0PMEREQOUT", OutTemp => L0PMEREQOUT_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PMEREQOUT, GlitchData => L0PMEREQOUT_GlitchData, OutSignalName => "L0PMEREQOUT", OutTemp => L0PMEREQOUT_OUT, Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PMEEN, GlitchData => L0PMEEN_GlitchData, OutSignalName => "L0PMEEN", OutTemp => L0PMEEN_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PMEEN, GlitchData => L0PMEEN_GlitchData, OutSignalName => "L0PMEEN", OutTemp => L0PMEEN_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PMEEN, GlitchData => L0PMEEN_GlitchData, OutSignalName => "L0PMEEN", OutTemp => L0PMEEN_OUT, Paths => (0 => (MAINPOWER_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRINHIBITTRANSFERS, GlitchData => L0PWRINHIBITTRANSFERS_GlitchData, OutSignalName => "L0PWRINHIBITTRANSFERS", OutTemp => L0PWRINHIBITTRANSFERS_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRL1STATE, GlitchData => L0PWRL1STATE_GlitchData, OutSignalName => "L0PWRL1STATE", OutTemp => L0PWRL1STATE_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRL1STATE, GlitchData => L0PWRL1STATE_GlitchData, OutSignalName => "L0PWRL1STATE", OutTemp => L0PWRL1STATE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRL23READYDEVICE, GlitchData => L0PWRL23READYDEVICE_GlitchData, OutSignalName => "L0PWRL23READYDEVICE", OutTemp => L0PWRL23READYDEVICE_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRL23READYDEVICE, GlitchData => L0PWRL23READYDEVICE_GlitchData, OutSignalName => "L0PWRL23READYDEVICE", OutTemp => L0PWRL23READYDEVICE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRL23READYSTATE, GlitchData => L0PWRL23READYSTATE_GlitchData, OutSignalName => "L0PWRL23READYSTATE", OutTemp => L0PWRL23READYSTATE_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRL23READYSTATE, GlitchData => L0PWRL23READYSTATE_GlitchData, OutSignalName => "L0PWRL23READYSTATE", OutTemp => L0PWRL23READYSTATE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRTXL0SSTATE, GlitchData => L0PWRTXL0SSTATE_GlitchData, OutSignalName => "L0PWRTXL0SSTATE", OutTemp => L0PWRTXL0SSTATE_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRTXL0SSTATE, GlitchData => L0PWRTXL0SSTATE_GlitchData, OutSignalName => "L0PWRTXL0SSTATE", OutTemp => L0PWRTXL0SSTATE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRTURNOFFREQ, GlitchData => L0PWRTURNOFFREQ_GlitchData, OutSignalName => "L0PWRTURNOFFREQ", OutTemp => L0PWRTURNOFFREQ_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0PWRTURNOFFREQ, GlitchData => L0PWRTURNOFFREQ_GlitchData, OutSignalName => "L0PWRTURNOFFREQ", OutTemp => L0PWRTURNOFFREQ_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLPM, GlitchData => L0RXDLLPM_GlitchData, OutSignalName => "L0RXDLLPM", OutTemp => L0RXDLLPM_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLPMTYPE(0), GlitchData => L0RXDLLPMTYPE0_GlitchData, OutSignalName => "L0RXDLLPMTYPE(0)", OutTemp => L0RXDLLPMTYPE_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLPMTYPE(1), GlitchData => L0RXDLLPMTYPE1_GlitchData, OutSignalName => "L0RXDLLPMTYPE(1)", OutTemp => L0RXDLLPMTYPE_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLPMTYPE(2), GlitchData => L0RXDLLPMTYPE2_GlitchData, OutSignalName => "L0RXDLLPMTYPE(2)", OutTemp => L0RXDLLPMTYPE_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLPMUPDATED, GlitchData => L0TXDLLPMUPDATED_GlitchData, OutSignalName => "L0TXDLLPMUPDATED", OutTemp => L0TXDLLPMUPDATED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MACNEWSTATEACK, GlitchData => L0MACNEWSTATEACK_GlitchData, OutSignalName => "L0MACNEWSTATEACK", OutTemp => L0MACNEWSTATEACK_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MACRXL0SSTATE, GlitchData => L0MACRXL0SSTATE_GlitchData, OutSignalName => "L0MACRXL0SSTATE", OutTemp => L0MACRXL0SSTATE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MACENTEREDL0, GlitchData => L0MACENTEREDL0_GlitchData, OutSignalName => "L0MACENTEREDL0", OutTemp => L0MACENTEREDL0_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLRXACKOUTSTANDING, GlitchData => L0DLLRXACKOUTSTANDING_GlitchData, OutSignalName => "L0DLLRXACKOUTSTANDING", OutTemp => L0DLLRXACKOUTSTANDING_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLTXOUTSTANDING, GlitchData => L0DLLTXOUTSTANDING_GlitchData, OutSignalName => "L0DLLTXOUTSTANDING", OutTemp => L0DLLTXOUTSTANDING_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0DLLTXNONFCOUTSTANDING, GlitchData => L0DLLTXNONFCOUTSTANDING_GlitchData, OutSignalName => "L0DLLTXNONFCOUTSTANDING", OutTemp => L0DLLTXNONFCOUTSTANDING_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLTLPEND(0), GlitchData => L0RXDLLTLPEND0_GlitchData, OutSignalName => "L0RXDLLTLPEND(0)", OutTemp => L0RXDLLTLPEND_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLTLPEND(1), GlitchData => L0RXDLLTLPEND1_GlitchData, OutSignalName => "L0RXDLLTLPEND(1)", OutTemp => L0RXDLLTLPEND_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLSBFCUPDATED, GlitchData => L0TXDLLSBFCUPDATED_GlitchData, OutSignalName => "L0TXDLLSBFCUPDATED", OutTemp => L0TXDLLSBFCUPDATED_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(0), GlitchData => L0RXDLLSBFCDATA0_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(0)", OutTemp => L0RXDLLSBFCDATA_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(1), GlitchData => L0RXDLLSBFCDATA1_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(1)", OutTemp => L0RXDLLSBFCDATA_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(2), GlitchData => L0RXDLLSBFCDATA2_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(2)", OutTemp => L0RXDLLSBFCDATA_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(3), GlitchData => L0RXDLLSBFCDATA3_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(3)", OutTemp => L0RXDLLSBFCDATA_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(4), GlitchData => L0RXDLLSBFCDATA4_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(4)", OutTemp => L0RXDLLSBFCDATA_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(5), GlitchData => L0RXDLLSBFCDATA5_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(5)", OutTemp => L0RXDLLSBFCDATA_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(6), GlitchData => L0RXDLLSBFCDATA6_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(6)", OutTemp => L0RXDLLSBFCDATA_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(7), GlitchData => L0RXDLLSBFCDATA7_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(7)", OutTemp => L0RXDLLSBFCDATA_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(8), GlitchData => L0RXDLLSBFCDATA8_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(8)", OutTemp => L0RXDLLSBFCDATA_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(9), GlitchData => L0RXDLLSBFCDATA9_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(9)", OutTemp => L0RXDLLSBFCDATA_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(10), GlitchData => L0RXDLLSBFCDATA10_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(10)", OutTemp => L0RXDLLSBFCDATA_OUT(10), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(11), GlitchData => L0RXDLLSBFCDATA11_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(11)", OutTemp => L0RXDLLSBFCDATA_OUT(11), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(12), GlitchData => L0RXDLLSBFCDATA12_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(12)", OutTemp => L0RXDLLSBFCDATA_OUT(12), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(13), GlitchData => L0RXDLLSBFCDATA13_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(13)", OutTemp => L0RXDLLSBFCDATA_OUT(13), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(14), GlitchData => L0RXDLLSBFCDATA14_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(14)", OutTemp => L0RXDLLSBFCDATA_OUT(14), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(15), GlitchData => L0RXDLLSBFCDATA15_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(15)", OutTemp => L0RXDLLSBFCDATA_OUT(15), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(16), GlitchData => L0RXDLLSBFCDATA16_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(16)", OutTemp => L0RXDLLSBFCDATA_OUT(16), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(17), GlitchData => L0RXDLLSBFCDATA17_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(17)", OutTemp => L0RXDLLSBFCDATA_OUT(17), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCDATA(18), GlitchData => L0RXDLLSBFCDATA18_GlitchData, OutSignalName => "L0RXDLLSBFCDATA(18)", OutTemp => L0RXDLLSBFCDATA_OUT(18), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLSBFCUPDATE, GlitchData => L0RXDLLSBFCUPDATE_GlitchData, OutSignalName => "L0RXDLLSBFCUPDATE", OutTemp => L0RXDLLSBFCUPDATE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCNPOSTBYPUPDATED(0), GlitchData => L0TXDLLFCNPOSTBYPUPDATED0_GlitchData, OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(0)", OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCNPOSTBYPUPDATED(1), GlitchData => L0TXDLLFCNPOSTBYPUPDATED1_GlitchData, OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(1)", OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCNPOSTBYPUPDATED(2), GlitchData => L0TXDLLFCNPOSTBYPUPDATED2_GlitchData, OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(2)", OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCNPOSTBYPUPDATED(3), GlitchData => L0TXDLLFCNPOSTBYPUPDATED3_GlitchData, OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(3)", OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCNPOSTBYPUPDATED(4), GlitchData => L0TXDLLFCNPOSTBYPUPDATED4_GlitchData, OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(4)", OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCNPOSTBYPUPDATED(5), GlitchData => L0TXDLLFCNPOSTBYPUPDATED5_GlitchData, OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(5)", OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCNPOSTBYPUPDATED(6), GlitchData => L0TXDLLFCNPOSTBYPUPDATED6_GlitchData, OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(6)", OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCNPOSTBYPUPDATED(7), GlitchData => L0TXDLLFCNPOSTBYPUPDATED7_GlitchData, OutSignalName => "L0TXDLLFCNPOSTBYPUPDATED(7)", OutTemp => L0TXDLLFCNPOSTBYPUPDATED_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCPOSTORDUPDATED(0), GlitchData => L0TXDLLFCPOSTORDUPDATED0_GlitchData, OutSignalName => "L0TXDLLFCPOSTORDUPDATED(0)", OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCPOSTORDUPDATED(1), GlitchData => L0TXDLLFCPOSTORDUPDATED1_GlitchData, OutSignalName => "L0TXDLLFCPOSTORDUPDATED(1)", OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCPOSTORDUPDATED(2), GlitchData => L0TXDLLFCPOSTORDUPDATED2_GlitchData, OutSignalName => "L0TXDLLFCPOSTORDUPDATED(2)", OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCPOSTORDUPDATED(3), GlitchData => L0TXDLLFCPOSTORDUPDATED3_GlitchData, OutSignalName => "L0TXDLLFCPOSTORDUPDATED(3)", OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCPOSTORDUPDATED(4), GlitchData => L0TXDLLFCPOSTORDUPDATED4_GlitchData, OutSignalName => "L0TXDLLFCPOSTORDUPDATED(4)", OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCPOSTORDUPDATED(5), GlitchData => L0TXDLLFCPOSTORDUPDATED5_GlitchData, OutSignalName => "L0TXDLLFCPOSTORDUPDATED(5)", OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCPOSTORDUPDATED(6), GlitchData => L0TXDLLFCPOSTORDUPDATED6_GlitchData, OutSignalName => "L0TXDLLFCPOSTORDUPDATED(6)", OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCPOSTORDUPDATED(7), GlitchData => L0TXDLLFCPOSTORDUPDATED7_GlitchData, OutSignalName => "L0TXDLLFCPOSTORDUPDATED(7)", OutTemp => L0TXDLLFCPOSTORDUPDATED_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCCMPLMCUPDATED(0), GlitchData => L0TXDLLFCCMPLMCUPDATED0_GlitchData, OutSignalName => "L0TXDLLFCCMPLMCUPDATED(0)", OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCCMPLMCUPDATED(1), GlitchData => L0TXDLLFCCMPLMCUPDATED1_GlitchData, OutSignalName => "L0TXDLLFCCMPLMCUPDATED(1)", OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCCMPLMCUPDATED(2), GlitchData => L0TXDLLFCCMPLMCUPDATED2_GlitchData, OutSignalName => "L0TXDLLFCCMPLMCUPDATED(2)", OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCCMPLMCUPDATED(3), GlitchData => L0TXDLLFCCMPLMCUPDATED3_GlitchData, OutSignalName => "L0TXDLLFCCMPLMCUPDATED(3)", OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCCMPLMCUPDATED(4), GlitchData => L0TXDLLFCCMPLMCUPDATED4_GlitchData, OutSignalName => "L0TXDLLFCCMPLMCUPDATED(4)", OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCCMPLMCUPDATED(5), GlitchData => L0TXDLLFCCMPLMCUPDATED5_GlitchData, OutSignalName => "L0TXDLLFCCMPLMCUPDATED(5)", OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCCMPLMCUPDATED(6), GlitchData => L0TXDLLFCCMPLMCUPDATED6_GlitchData, OutSignalName => "L0TXDLLFCCMPLMCUPDATED(6)", OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TXDLLFCCMPLMCUPDATED(7), GlitchData => L0TXDLLFCCMPLMCUPDATED7_GlitchData, OutSignalName => "L0TXDLLFCCMPLMCUPDATED(7)", OutTemp => L0TXDLLFCCMPLMCUPDATED_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(0), GlitchData => L0RXDLLFCNPOSTBYPCRED0_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(0)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(1), GlitchData => L0RXDLLFCNPOSTBYPCRED1_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(1)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(2), GlitchData => L0RXDLLFCNPOSTBYPCRED2_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(2)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(3), GlitchData => L0RXDLLFCNPOSTBYPCRED3_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(3)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(4), GlitchData => L0RXDLLFCNPOSTBYPCRED4_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(4)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(5), GlitchData => L0RXDLLFCNPOSTBYPCRED5_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(5)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(6), GlitchData => L0RXDLLFCNPOSTBYPCRED6_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(6)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(7), GlitchData => L0RXDLLFCNPOSTBYPCRED7_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(7)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(8), GlitchData => L0RXDLLFCNPOSTBYPCRED8_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(8)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(9), GlitchData => L0RXDLLFCNPOSTBYPCRED9_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(9)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(10), GlitchData => L0RXDLLFCNPOSTBYPCRED10_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(10)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(10), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(11), GlitchData => L0RXDLLFCNPOSTBYPCRED11_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(11)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(11), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(12), GlitchData => L0RXDLLFCNPOSTBYPCRED12_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(12)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(12), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(13), GlitchData => L0RXDLLFCNPOSTBYPCRED13_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(13)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(13), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(14), GlitchData => L0RXDLLFCNPOSTBYPCRED14_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(14)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(14), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(15), GlitchData => L0RXDLLFCNPOSTBYPCRED15_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(15)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(15), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(16), GlitchData => L0RXDLLFCNPOSTBYPCRED16_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(16)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(16), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(17), GlitchData => L0RXDLLFCNPOSTBYPCRED17_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(17)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(17), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(18), GlitchData => L0RXDLLFCNPOSTBYPCRED18_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(18)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(18), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPCRED(19), GlitchData => L0RXDLLFCNPOSTBYPCRED19_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPCRED(19)", OutTemp => L0RXDLLFCNPOSTBYPCRED_OUT(19), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPUPDATE(0), GlitchData => L0RXDLLFCNPOSTBYPUPDATE0_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(0)", OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPUPDATE(1), GlitchData => L0RXDLLFCNPOSTBYPUPDATE1_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(1)", OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPUPDATE(2), GlitchData => L0RXDLLFCNPOSTBYPUPDATE2_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(2)", OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPUPDATE(3), GlitchData => L0RXDLLFCNPOSTBYPUPDATE3_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(3)", OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPUPDATE(4), GlitchData => L0RXDLLFCNPOSTBYPUPDATE4_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(4)", OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPUPDATE(5), GlitchData => L0RXDLLFCNPOSTBYPUPDATE5_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(5)", OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPUPDATE(6), GlitchData => L0RXDLLFCNPOSTBYPUPDATE6_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(6)", OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCNPOSTBYPUPDATE(7), GlitchData => L0RXDLLFCNPOSTBYPUPDATE7_GlitchData, OutSignalName => "L0RXDLLFCNPOSTBYPUPDATE(7)", OutTemp => L0RXDLLFCNPOSTBYPUPDATE_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(0), GlitchData => L0RXDLLFCPOSTORDCRED0_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(0)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(1), GlitchData => L0RXDLLFCPOSTORDCRED1_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(1)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(2), GlitchData => L0RXDLLFCPOSTORDCRED2_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(2)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(3), GlitchData => L0RXDLLFCPOSTORDCRED3_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(3)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(4), GlitchData => L0RXDLLFCPOSTORDCRED4_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(4)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(5), GlitchData => L0RXDLLFCPOSTORDCRED5_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(5)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(6), GlitchData => L0RXDLLFCPOSTORDCRED6_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(6)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(7), GlitchData => L0RXDLLFCPOSTORDCRED7_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(7)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(8), GlitchData => L0RXDLLFCPOSTORDCRED8_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(8)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(9), GlitchData => L0RXDLLFCPOSTORDCRED9_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(9)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(10), GlitchData => L0RXDLLFCPOSTORDCRED10_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(10)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(10), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(11), GlitchData => L0RXDLLFCPOSTORDCRED11_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(11)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(11), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(12), GlitchData => L0RXDLLFCPOSTORDCRED12_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(12)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(12), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(13), GlitchData => L0RXDLLFCPOSTORDCRED13_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(13)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(13), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(14), GlitchData => L0RXDLLFCPOSTORDCRED14_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(14)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(14), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(15), GlitchData => L0RXDLLFCPOSTORDCRED15_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(15)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(15), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(16), GlitchData => L0RXDLLFCPOSTORDCRED16_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(16)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(16), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(17), GlitchData => L0RXDLLFCPOSTORDCRED17_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(17)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(17), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(18), GlitchData => L0RXDLLFCPOSTORDCRED18_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(18)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(18), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(19), GlitchData => L0RXDLLFCPOSTORDCRED19_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(19)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(19), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(20), GlitchData => L0RXDLLFCPOSTORDCRED20_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(20)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(20), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(21), GlitchData => L0RXDLLFCPOSTORDCRED21_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(21)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(21), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(22), GlitchData => L0RXDLLFCPOSTORDCRED22_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(22)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(22), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDCRED(23), GlitchData => L0RXDLLFCPOSTORDCRED23_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDCRED(23)", OutTemp => L0RXDLLFCPOSTORDCRED_OUT(23), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDUPDATE(0), GlitchData => L0RXDLLFCPOSTORDUPDATE0_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDUPDATE(0)", OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDUPDATE(1), GlitchData => L0RXDLLFCPOSTORDUPDATE1_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDUPDATE(1)", OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDUPDATE(2), GlitchData => L0RXDLLFCPOSTORDUPDATE2_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDUPDATE(2)", OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDUPDATE(3), GlitchData => L0RXDLLFCPOSTORDUPDATE3_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDUPDATE(3)", OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDUPDATE(4), GlitchData => L0RXDLLFCPOSTORDUPDATE4_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDUPDATE(4)", OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDUPDATE(5), GlitchData => L0RXDLLFCPOSTORDUPDATE5_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDUPDATE(5)", OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDUPDATE(6), GlitchData => L0RXDLLFCPOSTORDUPDATE6_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDUPDATE(6)", OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCPOSTORDUPDATE(7), GlitchData => L0RXDLLFCPOSTORDUPDATE7_GlitchData, OutSignalName => "L0RXDLLFCPOSTORDUPDATE(7)", OutTemp => L0RXDLLFCPOSTORDUPDATE_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(0), GlitchData => L0RXDLLFCCMPLMCCRED0_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(0)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(1), GlitchData => L0RXDLLFCCMPLMCCRED1_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(1)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(2), GlitchData => L0RXDLLFCCMPLMCCRED2_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(2)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(3), GlitchData => L0RXDLLFCCMPLMCCRED3_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(3)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(4), GlitchData => L0RXDLLFCCMPLMCCRED4_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(4)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(5), GlitchData => L0RXDLLFCCMPLMCCRED5_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(5)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(6), GlitchData => L0RXDLLFCCMPLMCCRED6_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(6)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(7), GlitchData => L0RXDLLFCCMPLMCCRED7_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(7)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(8), GlitchData => L0RXDLLFCCMPLMCCRED8_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(8)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(8), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(9), GlitchData => L0RXDLLFCCMPLMCCRED9_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(9)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(9), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(10), GlitchData => L0RXDLLFCCMPLMCCRED10_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(10)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(10), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(11), GlitchData => L0RXDLLFCCMPLMCCRED11_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(11)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(11), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(12), GlitchData => L0RXDLLFCCMPLMCCRED12_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(12)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(12), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(13), GlitchData => L0RXDLLFCCMPLMCCRED13_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(13)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(13), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(14), GlitchData => L0RXDLLFCCMPLMCCRED14_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(14)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(14), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(15), GlitchData => L0RXDLLFCCMPLMCCRED15_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(15)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(15), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(16), GlitchData => L0RXDLLFCCMPLMCCRED16_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(16)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(16), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(17), GlitchData => L0RXDLLFCCMPLMCCRED17_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(17)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(17), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(18), GlitchData => L0RXDLLFCCMPLMCCRED18_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(18)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(18), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(19), GlitchData => L0RXDLLFCCMPLMCCRED19_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(19)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(19), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(20), GlitchData => L0RXDLLFCCMPLMCCRED20_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(20)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(20), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(21), GlitchData => L0RXDLLFCCMPLMCCRED21_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(21)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(21), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(22), GlitchData => L0RXDLLFCCMPLMCCRED22_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(22)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(22), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCCRED(23), GlitchData => L0RXDLLFCCMPLMCCRED23_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCCRED(23)", OutTemp => L0RXDLLFCCMPLMCCRED_OUT(23), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCUPDATE(0), GlitchData => L0RXDLLFCCMPLMCUPDATE0_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCUPDATE(0)", OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCUPDATE(1), GlitchData => L0RXDLLFCCMPLMCUPDATE1_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCUPDATE(1)", OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCUPDATE(2), GlitchData => L0RXDLLFCCMPLMCUPDATE2_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCUPDATE(2)", OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCUPDATE(3), GlitchData => L0RXDLLFCCMPLMCUPDATE3_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCUPDATE(3)", OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCUPDATE(4), GlitchData => L0RXDLLFCCMPLMCUPDATE4_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCUPDATE(4)", OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(4), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCUPDATE(5), GlitchData => L0RXDLLFCCMPLMCUPDATE5_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCUPDATE(5)", OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(5), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCUPDATE(6), GlitchData => L0RXDLLFCCMPLMCUPDATE6_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCUPDATE(6)", OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(6), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0RXDLLFCCMPLMCUPDATE(7), GlitchData => L0RXDLLFCCMPLMCUPDATE7_GlitchData, OutSignalName => "L0RXDLLFCCMPLMCUPDATE(7)", OutTemp => L0RXDLLFCCMPLMCUPDATE_OUT(7), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0UCBYPFOUND(0), GlitchData => L0UCBYPFOUND0_GlitchData, OutSignalName => "L0UCBYPFOUND(0)", OutTemp => L0UCBYPFOUND_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0UCBYPFOUND(1), GlitchData => L0UCBYPFOUND1_GlitchData, OutSignalName => "L0UCBYPFOUND(1)", OutTemp => L0UCBYPFOUND_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0UCBYPFOUND(2), GlitchData => L0UCBYPFOUND2_GlitchData, OutSignalName => "L0UCBYPFOUND(2)", OutTemp => L0UCBYPFOUND_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0UCBYPFOUND(3), GlitchData => L0UCBYPFOUND3_GlitchData, OutSignalName => "L0UCBYPFOUND(3)", OutTemp => L0UCBYPFOUND_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0UCORDFOUND(0), GlitchData => L0UCORDFOUND0_GlitchData, OutSignalName => "L0UCORDFOUND(0)", OutTemp => L0UCORDFOUND_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0UCORDFOUND(1), GlitchData => L0UCORDFOUND1_GlitchData, OutSignalName => "L0UCORDFOUND(1)", OutTemp => L0UCORDFOUND_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0UCORDFOUND(2), GlitchData => L0UCORDFOUND2_GlitchData, OutSignalName => "L0UCORDFOUND(2)", OutTemp => L0UCORDFOUND_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0UCORDFOUND(3), GlitchData => L0UCORDFOUND3_GlitchData, OutSignalName => "L0UCORDFOUND(3)", OutTemp => L0UCORDFOUND_OUT(3), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MCFOUND(0), GlitchData => L0MCFOUND0_GlitchData, OutSignalName => "L0MCFOUND(0)", OutTemp => L0MCFOUND_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MCFOUND(1), GlitchData => L0MCFOUND1_GlitchData, OutSignalName => "L0MCFOUND(1)", OutTemp => L0MCFOUND_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0MCFOUND(2), GlitchData => L0MCFOUND2_GlitchData, OutSignalName => "L0MCFOUND(2)", OutTemp => L0MCFOUND_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TRANSFORMEDVC(0), GlitchData => L0TRANSFORMEDVC0_GlitchData, OutSignalName => "L0TRANSFORMEDVC(0)", OutTemp => L0TRANSFORMEDVC_OUT(0), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TRANSFORMEDVC(1), GlitchData => L0TRANSFORMEDVC1_GlitchData, OutSignalName => "L0TRANSFORMEDVC(1)", OutTemp => L0TRANSFORMEDVC_OUT(1), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => L0TRANSFORMEDVC(2), GlitchData => L0TRANSFORMEDVC2_GlitchData, OutSignalName => "L0TRANSFORMEDVC(2)", OutTemp => L0TRANSFORMEDVC_OUT(2), Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => BUSMASTERENABLE, GlitchData => BUSMASTERENABLE_GlitchData, OutSignalName => "BUSMASTERENABLE", OutTemp => BUSMASTERENABLE_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => BUSMASTERENABLE, GlitchData => BUSMASTERENABLE_GlitchData, OutSignalName => "BUSMASTERENABLE", OutTemp => BUSMASTERENABLE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PARITYERRORRESPONSE, GlitchData => PARITYERRORRESPONSE_GlitchData, OutSignalName => "PARITYERRORRESPONSE", OutTemp => PARITYERRORRESPONSE_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PARITYERRORRESPONSE, GlitchData => PARITYERRORRESPONSE_GlitchData, OutSignalName => "PARITYERRORRESPONSE", OutTemp => PARITYERRORRESPONSE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => SERRENABLE, GlitchData => SERRENABLE_GlitchData, OutSignalName => "SERRENABLE", OutTemp => SERRENABLE_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => SERRENABLE, GlitchData => SERRENABLE_GlitchData, OutSignalName => "SERRENABLE", OutTemp => SERRENABLE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => INTERRUPTDISABLE, GlitchData => INTERRUPTDISABLE_GlitchData, OutSignalName => "INTERRUPTDISABLE", OutTemp => INTERRUPTDISABLE_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => INTERRUPTDISABLE, GlitchData => INTERRUPTDISABLE_GlitchData, OutSignalName => "INTERRUPTDISABLE", OutTemp => INTERRUPTDISABLE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => URREPORTINGENABLE, GlitchData => URREPORTINGENABLE_GlitchData, OutSignalName => "URREPORTINGENABLE", OutTemp => URREPORTINGENABLE_OUT, Paths => (0 => (CRMUSERCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => URREPORTINGENABLE, GlitchData => URREPORTINGENABLE_GlitchData, OutSignalName => "URREPORTINGENABLE", OutTemp => URREPORTINGENABLE_OUT, Paths => (0 => (CRMCORECLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); wait on BUSMASTERENABLE_out, CRMDOHOTRESETN_out, CRMPWRSOFTRESETN_out, CRMRXHOTRESETN_out, DLLTXPMDLLPOUTSTANDING_out, INTERRUPTDISABLE_out, IOSPACEENABLE_out, L0ASAUTONOMOUSINITCOMPLETED_out, L0ATTENTIONINDICATORCONTROL_out, L0CFGLOOPBACKACK_out, L0COMPLETERID_out, L0CORRERRMSGRCVD_out, L0DLLASRXSTATE_out, L0DLLASTXSTATE_out, L0DLLERRORVECTOR_out, L0DLLRXACKOUTSTANDING_out, L0DLLTXNONFCOUTSTANDING_out, L0DLLTXOUTSTANDING_out, L0DLLVCSTATUS_out, L0DLUPDOWN_out, L0ERRMSGREQID_out, L0FATALERRMSGRCVD_out, L0FIRSTCFGWRITEOCCURRED_out, L0FWDCORRERROUT_out, L0FWDFATALERROUT_out, L0FWDNONFATALERROUT_out, L0LTSSMSTATE_out, L0MACENTEREDL0_out, L0MACLINKTRAINING_out, L0MACLINKUP_out, L0MACNEGOTIATEDLINKWIDTH_out, L0MACNEWSTATEACK_out, L0MACRXL0SSTATE_out, L0MACUPSTREAMDOWNSTREAM_out, L0MCFOUND_out, L0MSIENABLE0_out, L0MULTIMSGEN0_out, L0NONFATALERRMSGRCVD_out, L0PMEACK_out, L0PMEEN_out, L0PMEREQOUT_out, L0POWERCONTROLLERCONTROL_out, L0POWERINDICATORCONTROL_out, L0PWRINHIBITTRANSFERS_out, L0PWRL1STATE_out, L0PWRL23READYDEVICE_out, L0PWRL23READYSTATE_out, L0PWRSTATE0_out, L0PWRTURNOFFREQ_out, L0PWRTXL0SSTATE_out, L0RECEIVEDASSERTINTALEGACYINT_out, L0RECEIVEDASSERTINTBLEGACYINT_out, L0RECEIVEDASSERTINTCLEGACYINT_out, L0RECEIVEDASSERTINTDLEGACYINT_out, L0RECEIVEDDEASSERTINTALEGACYINT_out, L0RECEIVEDDEASSERTINTBLEGACYINT_out, L0RECEIVEDDEASSERTINTCLEGACYINT_out, L0RECEIVEDDEASSERTINTDLEGACYINT_out, L0RXBEACON_out, L0RXDLLFCCMPLMCCRED_out, L0RXDLLFCCMPLMCUPDATE_out, L0RXDLLFCNPOSTBYPCRED_out, L0RXDLLFCNPOSTBYPUPDATE_out, L0RXDLLFCPOSTORDCRED_out, L0RXDLLFCPOSTORDUPDATE_out, L0RXDLLPMTYPE_out, L0RXDLLPM_out, L0RXDLLSBFCDATA_out, L0RXDLLSBFCUPDATE_out, L0RXDLLTLPECRCOK_out, L0RXDLLTLPEND_out, L0RXMACLINKERROR_out, L0STATSCFGOTHERRECEIVED_out, L0STATSCFGOTHERTRANSMITTED_out, L0STATSCFGRECEIVED_out, L0STATSCFGTRANSMITTED_out, L0STATSDLLPRECEIVED_out, L0STATSDLLPTRANSMITTED_out, L0STATSOSRECEIVED_out, L0STATSOSTRANSMITTED_out, L0STATSTLPRECEIVED_out, L0STATSTLPTRANSMITTED_out, L0TOGGLEELECTROMECHANICALINTERLOCK_out, L0TRANSFORMEDVC_out, L0TXDLLFCCMPLMCUPDATED_out, L0TXDLLFCNPOSTBYPUPDATED_out, L0TXDLLFCPOSTORDUPDATED_out, L0TXDLLPMUPDATED_out, L0TXDLLSBFCUPDATED_out, L0UCBYPFOUND_out, L0UCORDFOUND_out, L0UNLOCKRECEIVED_out, LLKRX4DWHEADERN_out, LLKRXCHCOMPLETIONAVAILABLEN_out, LLKRXCHCOMPLETIONPARTIALN_out, LLKRXCHCONFIGAVAILABLEN_out, LLKRXCHCONFIGPARTIALN_out, LLKRXCHNONPOSTEDAVAILABLEN_out, LLKRXCHNONPOSTEDPARTIALN_out, LLKRXCHPOSTEDAVAILABLEN_out, LLKRXCHPOSTEDPARTIALN_out, LLKRXDATA_out, LLKRXECRCBADN_out, LLKRXEOFN_out, LLKRXEOPN_out, LLKRXPREFERREDTYPE_out, LLKRXSOFN_out, LLKRXSOPN_out, LLKRXSRCDSCN_out, LLKRXSRCLASTREQN_out, LLKRXSRCRDYN_out, LLKRXVALIDN_out, LLKTCSTATUS_out, LLKTXCHANSPACE_out, LLKTXCHCOMPLETIONREADYN_out, LLKTXCHNONPOSTEDREADYN_out, LLKTXCHPOSTEDREADYN_out, LLKTXCONFIGREADYN_out, LLKTXDSTRDYN_out, MAXPAYLOADSIZE_out, MAXREADREQUESTSIZE_out, MEMSPACEENABLE_out, MGMTPSO_out, MGMTRDATA_out, MGMTSTATSCREDIT_out, MIMDLLBRADD_out, MIMDLLBREN_out, MIMDLLBWADD_out, MIMDLLBWDATA_out, MIMDLLBWEN_out, MIMRXBRADD_out, MIMRXBREN_out, MIMRXBWADD_out, MIMRXBWDATA_out, MIMRXBWEN_out, MIMTXBRADD_out, MIMTXBREN_out, MIMTXBWADD_out, MIMTXBWDATA_out, MIMTXBWEN_out, PARITYERRORRESPONSE_out, PIPEDESKEWLANESL0_out, PIPEDESKEWLANESL1_out, PIPEDESKEWLANESL2_out, PIPEDESKEWLANESL3_out, PIPEDESKEWLANESL4_out, PIPEDESKEWLANESL5_out, PIPEDESKEWLANESL6_out, PIPEDESKEWLANESL7_out, PIPEPOWERDOWNL0_out, PIPEPOWERDOWNL1_out, PIPEPOWERDOWNL2_out, PIPEPOWERDOWNL3_out, PIPEPOWERDOWNL4_out, PIPEPOWERDOWNL5_out, PIPEPOWERDOWNL6_out, PIPEPOWERDOWNL7_out, PIPERESETL0_out, PIPERESETL1_out, PIPERESETL2_out, PIPERESETL3_out, PIPERESETL4_out, PIPERESETL5_out, PIPERESETL6_out, PIPERESETL7_out, PIPERXPOLARITYL0_out, PIPERXPOLARITYL1_out, PIPERXPOLARITYL2_out, PIPERXPOLARITYL3_out, PIPERXPOLARITYL4_out, PIPERXPOLARITYL5_out, PIPERXPOLARITYL6_out, PIPERXPOLARITYL7_out, PIPETXCOMPLIANCEL0_out, PIPETXCOMPLIANCEL1_out, PIPETXCOMPLIANCEL2_out, PIPETXCOMPLIANCEL3_out, PIPETXCOMPLIANCEL4_out, PIPETXCOMPLIANCEL5_out, PIPETXCOMPLIANCEL6_out, PIPETXCOMPLIANCEL7_out, PIPETXDATAKL0_out, PIPETXDATAKL1_out, PIPETXDATAKL2_out, PIPETXDATAKL3_out, PIPETXDATAKL4_out, PIPETXDATAKL5_out, PIPETXDATAKL6_out, PIPETXDATAKL7_out, PIPETXDATAL0_out, PIPETXDATAL1_out, PIPETXDATAL2_out, PIPETXDATAL3_out, PIPETXDATAL4_out, PIPETXDATAL5_out, PIPETXDATAL6_out, PIPETXDATAL7_out, PIPETXDETECTRXLOOPBACKL0_out, PIPETXDETECTRXLOOPBACKL1_out, PIPETXDETECTRXLOOPBACKL2_out, PIPETXDETECTRXLOOPBACKL3_out, PIPETXDETECTRXLOOPBACKL4_out, PIPETXDETECTRXLOOPBACKL5_out, PIPETXDETECTRXLOOPBACKL6_out, PIPETXDETECTRXLOOPBACKL7_out, PIPETXELECIDLEL0_out, PIPETXELECIDLEL1_out, PIPETXELECIDLEL2_out, PIPETXELECIDLEL3_out, PIPETXELECIDLEL4_out, PIPETXELECIDLEL5_out, PIPETXELECIDLEL6_out, PIPETXELECIDLEL7_out, SERRENABLE_out, URREPORTINGENABLE_out, AUXPOWER_ipd, CFGNEGOTIATEDLINKWIDTH_ipd, COMPLIANCEAVOID_ipd, CRMCFGBRIDGEHOTRESET_ipd, CRMCORECLKDLO_ipd, CRMCORECLKRXO_ipd, CRMCORECLKTXO_ipd, CRMCORECLK_ipd, CRMLINKRSTN_ipd, CRMMACRSTN_ipd, CRMMGMTRSTN_ipd, CRMNVRSTN_ipd, CRMTXHOTRESETN_ipd, CRMURSTN_ipd, CRMUSERCFGRSTN_ipd, CRMUSERCLKRXO_ipd, CRMUSERCLKTXO_ipd, CRMUSERCLK_ipd, CROSSLINKSEED_ipd, L0ACKNAKTIMERADJUSTMENT_ipd, L0ALLDOWNPORTSINL1_ipd, L0ALLDOWNRXPORTSINL0S_ipd, L0ASE_ipd, L0ASPORTCOUNT_ipd, L0ASTURNPOOLBITSCONSUMED_ipd, L0ATTENTIONBUTTONPRESSED_ipd, L0CFGASSPANTREEOWNEDSTATE_ipd, L0CFGASSTATECHANGECMD_ipd, L0CFGDISABLESCRAMBLE_ipd, L0CFGEXTENDEDSYNC_ipd, L0CFGL0SENTRYENABLE_ipd, L0CFGL0SENTRYSUP_ipd, L0CFGL0SEXITLAT_ipd, L0CFGLINKDISABLE_ipd, L0CFGLOOPBACKMASTER_ipd, L0CFGNEGOTIATEDMAXP_ipd, L0CFGVCENABLE_ipd, L0CFGVCID_ipd, L0DLLHOLDLINKUP_ipd, L0ELECTROMECHANICALINTERLOCKENGAGED_ipd, L0FWDASSERTINTALEGACYINT_ipd, L0FWDASSERTINTBLEGACYINT_ipd, L0FWDASSERTINTCLEGACYINT_ipd, L0FWDASSERTINTDLEGACYINT_ipd, L0FWDCORRERRIN_ipd, L0FWDDEASSERTINTALEGACYINT_ipd, L0FWDDEASSERTINTBLEGACYINT_ipd, L0FWDDEASSERTINTCLEGACYINT_ipd, L0FWDDEASSERTINTDLEGACYINT_ipd, L0FWDFATALERRIN_ipd, L0FWDNONFATALERRIN_ipd, L0LEGACYINTFUNCT0_ipd, L0MRLSENSORCLOSEDN_ipd, L0MSIREQUEST0_ipd, L0PACKETHEADERFROMUSER_ipd, L0PMEREQIN_ipd, L0PORTNUMBER_ipd, L0POWERFAULTDETECTED_ipd, L0PRESENCEDETECTSLOTEMPTYN_ipd, L0PWRNEWSTATEREQ_ipd, L0PWRNEXTLINKSTATE_ipd, L0REPLAYTIMERADJUSTMENT_ipd, L0ROOTTURNOFFREQ_ipd, L0RXTLTLPNONINITIALIZEDVC_ipd, L0SENDUNLOCKMESSAGE_ipd, L0SETCOMPLETERABORTERROR_ipd, L0SETCOMPLETIONTIMEOUTCORRERROR_ipd, L0SETCOMPLETIONTIMEOUTUNCORRERROR_ipd, L0SETDETECTEDCORRERROR_ipd, L0SETDETECTEDFATALERROR_ipd, L0SETDETECTEDNONFATALERROR_ipd, L0SETLINKDETECTEDPARITYERROR_ipd, L0SETLINKMASTERDATAPARITY_ipd, L0SETLINKRECEIVEDMASTERABORT_ipd, L0SETLINKRECEIVEDTARGETABORT_ipd, L0SETLINKSIGNALLEDTARGETABORT_ipd, L0SETLINKSYSTEMERROR_ipd, L0SETUNEXPECTEDCOMPLETIONCORRERROR_ipd, L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_ipd, L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_ipd, L0SETUNSUPPORTEDREQUESTOTHERERROR_ipd, L0SETUSERDETECTEDPARITYERROR_ipd, L0SETUSERMASTERDATAPARITY_ipd, L0SETUSERRECEIVEDMASTERABORT_ipd, L0SETUSERRECEIVEDTARGETABORT_ipd, L0SETUSERSIGNALLEDTARGETABORT_ipd, L0SETUSERSYSTEMERROR_ipd, L0TLASFCCREDSTARVATION_ipd, L0TLLINKRETRAIN_ipd, L0TRANSACTIONSPENDING_ipd, L0TXBEACON_ipd, L0TXCFGPMTYPE_ipd, L0TXCFGPM_ipd, L0TXTLFCCMPLMCCRED_ipd, L0TXTLFCCMPLMCUPDATE_ipd, L0TXTLFCNPOSTBYPCRED_ipd, L0TXTLFCNPOSTBYPUPDATE_ipd, L0TXTLFCPOSTORDCRED_ipd, L0TXTLFCPOSTORDUPDATE_ipd, L0TXTLSBFCDATA_ipd, L0TXTLSBFCUPDATE_ipd, L0TXTLTLPDATA_ipd, L0TXTLTLPEDB_ipd, L0TXTLTLPENABLE_ipd, L0TXTLTLPEND_ipd, L0TXTLTLPLATENCY_ipd, L0TXTLTLPREQEND_ipd, L0TXTLTLPREQ_ipd, L0TXTLTLPWIDTH_ipd, L0UPSTREAMRXPORTINL0S_ipd, L0VC0PREVIEWEXPAND_ipd, L0WAKEN_ipd, LLKRXCHFIFO_ipd, LLKRXCHTC_ipd, LLKRXDSTCONTREQN_ipd, LLKRXDSTREQN_ipd, LLKTX4DWHEADERN_ipd, LLKTXCHFIFO_ipd, LLKTXCHTC_ipd, LLKTXCOMPLETEN_ipd, LLKTXCREATEECRCN_ipd, LLKTXDATA_ipd, LLKTXENABLEN_ipd, LLKTXEOFN_ipd, LLKTXEOPN_ipd, LLKTXSOFN_ipd, LLKTXSOPN_ipd, LLKTXSRCDSCN_ipd, LLKTXSRCRDYN_ipd, MAINPOWER_ipd, MGMTADDR_ipd, MGMTBWREN_ipd, MGMTRDEN_ipd, MGMTSTATSCREDITSEL_ipd, MGMTWDATA_ipd, MGMTWREN_ipd, MIMDLLBRDATA_ipd, MIMRXBRDATA_ipd, MIMTXBRDATA_ipd, PIPEPHYSTATUSL0_ipd, PIPEPHYSTATUSL1_ipd, PIPEPHYSTATUSL2_ipd, PIPEPHYSTATUSL3_ipd, PIPEPHYSTATUSL4_ipd, PIPEPHYSTATUSL5_ipd, PIPEPHYSTATUSL6_ipd, PIPEPHYSTATUSL7_ipd, PIPERXCHANISALIGNEDL0_ipd, PIPERXCHANISALIGNEDL1_ipd, PIPERXCHANISALIGNEDL2_ipd, PIPERXCHANISALIGNEDL3_ipd, PIPERXCHANISALIGNEDL4_ipd, PIPERXCHANISALIGNEDL5_ipd, PIPERXCHANISALIGNEDL6_ipd, PIPERXCHANISALIGNEDL7_ipd, PIPERXDATAKL0_ipd, PIPERXDATAKL1_ipd, PIPERXDATAKL2_ipd, PIPERXDATAKL3_ipd, PIPERXDATAKL4_ipd, PIPERXDATAKL5_ipd, PIPERXDATAKL6_ipd, PIPERXDATAKL7_ipd, PIPERXDATAL0_ipd, PIPERXDATAL1_ipd, PIPERXDATAL2_ipd, PIPERXDATAL3_ipd, PIPERXDATAL4_ipd, PIPERXDATAL5_ipd, PIPERXDATAL6_ipd, PIPERXDATAL7_ipd, PIPERXELECIDLEL0_ipd, PIPERXELECIDLEL1_ipd, PIPERXELECIDLEL2_ipd, PIPERXELECIDLEL3_ipd, PIPERXELECIDLEL4_ipd, PIPERXELECIDLEL5_ipd, PIPERXELECIDLEL6_ipd, PIPERXELECIDLEL7_ipd, PIPERXSTATUSL0_ipd, PIPERXSTATUSL1_ipd, PIPERXSTATUSL2_ipd, PIPERXSTATUSL3_ipd, PIPERXSTATUSL4_ipd, PIPERXSTATUSL5_ipd, PIPERXSTATUSL6_ipd, PIPERXSTATUSL7_ipd, PIPERXVALIDL0_ipd, PIPERXVALIDL1_ipd, PIPERXVALIDL2_ipd, PIPERXVALIDL3_ipd, PIPERXVALIDL4_ipd, PIPERXVALIDL5_ipd, PIPERXVALIDL6_ipd, PIPERXVALIDL7_ipd; end process TIMING; end PCIE_INTERNAL_1_1_V; ------------------------------------------------------------------------------- -- Copyright (c) 1995/2006 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / Tri-Mode Ethernet MAC -- /___/ /\ Filename : temac.vhd -- \ \ / \ Timestamp : Thu Dec 8 2005 -- \___\/\___\ -- -- Revision: -- 12/08/05 - Initial version. -- 01/09/06 - Added architecture -- 02/06/06 - pinTime updates -- 02/23/06 - Updated Header -- 03/10/06 - CR#226740. Changed generic type of some of the generics from -- string to boolean -- 03/27/06 - Updated TEMAC smartmodel to version number 00.002 for following changes -- CR#224695 - -- 1. TEMAC smartmodel 16 bit client interface problem. -- 2. Compiled smartmodel with `delay_mode_zero directive -- CR#226083 - -- 1. Loopback attributes don't work in Verilog TEMAC smartmodel. -- CR#224695 - -- 1 . Added 50 ps input delay to all inputs(except clocks) going into temac swift model -- 04/11/06 - CR#228762 - Added some missing path delays to timing block. -- 04/27/06 - CR#230105 - Fixed connectivity for CLK -- 05/23/06 - CR#231962 - Add buffers for connectivity -- 09/15/06 - CR#423162 - Timing updates -- 10/26/06 - - replaced ZERO_DELAY with CLK_DELAY to be consistent with writers (PPC440 update) -- 06/08/07 - CR#440717 - Add constant EMAC0MIITXCLK_DELAY & EMAC1MIITXCLK_DELAY -- 08/28/07 - CR#447575 - Path Delay updates due to pinDev/pinTime updates -- End Revision ----- CELL TEMAC ----- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; library secureip; use secureip.all; entity TEMAC is generic ( EMAC0_1000BASEX_ENABLE : boolean := FALSE; EMAC0_ADDRFILTER_ENABLE : boolean := FALSE; EMAC0_BYTEPHY : boolean := FALSE; EMAC0_CONFIGVEC_79 : boolean := FALSE; EMAC0_DCRBASEADDR : bit_vector := X"00"; EMAC0_GTLOOPBACK : boolean := FALSE; EMAC0_HOST_ENABLE : boolean := FALSE; EMAC0_LINKTIMERVAL : bit_vector := X"000"; EMAC0_LTCHECK_DISABLE : boolean := FALSE; EMAC0_MDIO_ENABLE : boolean := FALSE; EMAC0_PAUSEADDR : bit_vector := X"000000000000"; EMAC0_PHYINITAUTONEG_ENABLE : boolean := FALSE; EMAC0_PHYISOLATE : boolean := FALSE; EMAC0_PHYLOOPBACKMSB : boolean := FALSE; EMAC0_PHYPOWERDOWN : boolean := FALSE; EMAC0_PHYRESET : boolean := FALSE; EMAC0_RGMII_ENABLE : boolean := FALSE; EMAC0_RX16BITCLIENT_ENABLE : boolean := FALSE; EMAC0_RXFLOWCTRL_ENABLE : boolean := FALSE; EMAC0_RXHALFDUPLEX : boolean := FALSE; EMAC0_RXINBANDFCS_ENABLE : boolean := FALSE; EMAC0_RXJUMBOFRAME_ENABLE : boolean := FALSE; EMAC0_RXRESET : boolean := FALSE; EMAC0_RXVLAN_ENABLE : boolean := FALSE; EMAC0_RX_ENABLE : boolean := FALSE; EMAC0_SGMII_ENABLE : boolean := FALSE; EMAC0_SPEED_LSB : boolean := FALSE; EMAC0_SPEED_MSB : boolean := FALSE; EMAC0_TX16BITCLIENT_ENABLE : boolean := FALSE; EMAC0_TXFLOWCTRL_ENABLE : boolean := FALSE; EMAC0_TXHALFDUPLEX : boolean := FALSE; EMAC0_TXIFGADJUST_ENABLE : boolean := FALSE; EMAC0_TXINBANDFCS_ENABLE : boolean := FALSE; EMAC0_TXJUMBOFRAME_ENABLE : boolean := FALSE; EMAC0_TXRESET : boolean := FALSE; EMAC0_TXVLAN_ENABLE : boolean := FALSE; EMAC0_TX_ENABLE : boolean := FALSE; EMAC0_UNICASTADDR : bit_vector := X"000000000000"; EMAC0_UNIDIRECTION_ENABLE : boolean := FALSE; EMAC0_USECLKEN : boolean := FALSE; EMAC1_1000BASEX_ENABLE : boolean := FALSE; EMAC1_ADDRFILTER_ENABLE : boolean := FALSE; EMAC1_BYTEPHY : boolean := FALSE; EMAC1_CONFIGVEC_79 : boolean := FALSE; EMAC1_DCRBASEADDR : bit_vector := X"00"; EMAC1_GTLOOPBACK : boolean := FALSE; EMAC1_HOST_ENABLE : boolean := FALSE; EMAC1_LINKTIMERVAL : bit_vector := X"000"; EMAC1_LTCHECK_DISABLE : boolean := FALSE; EMAC1_MDIO_ENABLE : boolean := FALSE; EMAC1_PAUSEADDR : bit_vector := X"000000000000"; EMAC1_PHYINITAUTONEG_ENABLE : boolean := FALSE; EMAC1_PHYISOLATE : boolean := FALSE; EMAC1_PHYLOOPBACKMSB : boolean := FALSE; EMAC1_PHYPOWERDOWN : boolean := FALSE; EMAC1_PHYRESET : boolean := FALSE; EMAC1_RGMII_ENABLE : boolean := FALSE; EMAC1_RX16BITCLIENT_ENABLE : boolean := FALSE; EMAC1_RXFLOWCTRL_ENABLE : boolean := FALSE; EMAC1_RXHALFDUPLEX : boolean := FALSE; EMAC1_RXINBANDFCS_ENABLE : boolean := FALSE; EMAC1_RXJUMBOFRAME_ENABLE : boolean := FALSE; EMAC1_RXRESET : boolean := FALSE; EMAC1_RXVLAN_ENABLE : boolean := FALSE; EMAC1_RX_ENABLE : boolean := FALSE; EMAC1_SGMII_ENABLE : boolean := FALSE; EMAC1_SPEED_LSB : boolean := FALSE; EMAC1_SPEED_MSB : boolean := FALSE; EMAC1_TX16BITCLIENT_ENABLE : boolean := FALSE; EMAC1_TXFLOWCTRL_ENABLE : boolean := FALSE; EMAC1_TXHALFDUPLEX : boolean := FALSE; EMAC1_TXIFGADJUST_ENABLE : boolean := FALSE; EMAC1_TXINBANDFCS_ENABLE : boolean := FALSE; EMAC1_TXJUMBOFRAME_ENABLE : boolean := FALSE; EMAC1_TXRESET : boolean := FALSE; EMAC1_TXVLAN_ENABLE : boolean := FALSE; EMAC1_TX_ENABLE : boolean := FALSE; EMAC1_UNICASTADDR : bit_vector := X"000000000000"; EMAC1_UNIDIRECTION_ENABLE : boolean := FALSE; EMAC1_USECLKEN : boolean := FALSE ); port ( DCRHOSTDONEIR : out std_ulogic; EMAC0CLIENTANINTERRUPT : out std_ulogic; EMAC0CLIENTRXBADFRAME : out std_ulogic; EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); EMAC0CLIENTRXDVLD : out std_ulogic; EMAC0CLIENTRXDVLDMSW : out std_ulogic; EMAC0CLIENTRXFRAMEDROP : out std_ulogic; EMAC0CLIENTRXGOODFRAME : out std_ulogic; EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; EMAC0CLIENTRXSTATSVLD : out std_ulogic; EMAC0CLIENTTXACK : out std_ulogic; EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; EMAC0CLIENTTXCOLLISION : out std_ulogic; EMAC0CLIENTTXRETRANSMIT : out std_ulogic; EMAC0CLIENTTXSTATS : out std_ulogic; EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; EMAC0CLIENTTXSTATSVLD : out std_ulogic; EMAC0PHYENCOMMAALIGN : out std_ulogic; EMAC0PHYLOOPBACKMSB : out std_ulogic; EMAC0PHYMCLKOUT : out std_ulogic; EMAC0PHYMDOUT : out std_ulogic; EMAC0PHYMDTRI : out std_ulogic; EMAC0PHYMGTRXRESET : out std_ulogic; EMAC0PHYMGTTXRESET : out std_ulogic; EMAC0PHYPOWERDOWN : out std_ulogic; EMAC0PHYSYNCACQSTATUS : out std_ulogic; EMAC0PHYTXCHARDISPMODE : out std_ulogic; EMAC0PHYTXCHARDISPVAL : out std_ulogic; EMAC0PHYTXCHARISK : out std_ulogic; EMAC0PHYTXCLK : out std_ulogic; EMAC0PHYTXD : out std_logic_vector(7 downto 0); EMAC0PHYTXEN : out std_ulogic; EMAC0PHYTXER : out std_ulogic; EMAC0PHYTXGMIIMIICLKOUT : out std_ulogic; EMAC0SPEEDIS10100 : out std_ulogic; EMAC1CLIENTANINTERRUPT : out std_ulogic; EMAC1CLIENTRXBADFRAME : out std_ulogic; EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); EMAC1CLIENTRXDVLD : out std_ulogic; EMAC1CLIENTRXDVLDMSW : out std_ulogic; EMAC1CLIENTRXFRAMEDROP : out std_ulogic; EMAC1CLIENTRXGOODFRAME : out std_ulogic; EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; EMAC1CLIENTRXSTATSVLD : out std_ulogic; EMAC1CLIENTTXACK : out std_ulogic; EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; EMAC1CLIENTTXCOLLISION : out std_ulogic; EMAC1CLIENTTXRETRANSMIT : out std_ulogic; EMAC1CLIENTTXSTATS : out std_ulogic; EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; EMAC1CLIENTTXSTATSVLD : out std_ulogic; EMAC1PHYENCOMMAALIGN : out std_ulogic; EMAC1PHYLOOPBACKMSB : out std_ulogic; EMAC1PHYMCLKOUT : out std_ulogic; EMAC1PHYMDOUT : out std_ulogic; EMAC1PHYMDTRI : out std_ulogic; EMAC1PHYMGTRXRESET : out std_ulogic; EMAC1PHYMGTTXRESET : out std_ulogic; EMAC1PHYPOWERDOWN : out std_ulogic; EMAC1PHYSYNCACQSTATUS : out std_ulogic; EMAC1PHYTXCHARDISPMODE : out std_ulogic; EMAC1PHYTXCHARDISPVAL : out std_ulogic; EMAC1PHYTXCHARISK : out std_ulogic; EMAC1PHYTXCLK : out std_ulogic; EMAC1PHYTXD : out std_logic_vector(7 downto 0); EMAC1PHYTXEN : out std_ulogic; EMAC1PHYTXER : out std_ulogic; EMAC1PHYTXGMIIMIICLKOUT : out std_ulogic; EMAC1SPEEDIS10100 : out std_ulogic; EMACDCRACK : out std_ulogic; EMACDCRDBUS : out std_logic_vector(0 to 31); HOSTMIIMRDY : out std_ulogic; HOSTRDDATA : out std_logic_vector(31 downto 0); CLIENTEMAC0DCMLOCKED : in std_ulogic; CLIENTEMAC0PAUSEREQ : in std_ulogic; CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); CLIENTEMAC0TXDVLD : in std_ulogic; CLIENTEMAC0TXDVLDMSW : in std_ulogic; CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); CLIENTEMAC0TXUNDERRUN : in std_ulogic; CLIENTEMAC1DCMLOCKED : in std_ulogic; CLIENTEMAC1PAUSEREQ : in std_ulogic; CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); CLIENTEMAC1TXDVLD : in std_ulogic; CLIENTEMAC1TXDVLDMSW : in std_ulogic; CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); CLIENTEMAC1TXUNDERRUN : in std_ulogic; DCREMACABUS : in std_logic_vector(0 to 9); DCREMACCLK : in std_ulogic; DCREMACDBUS : in std_logic_vector(0 to 31); DCREMACENABLE : in std_ulogic; DCREMACREAD : in std_ulogic; DCREMACWRITE : in std_ulogic; HOSTADDR : in std_logic_vector(9 downto 0); HOSTCLK : in std_ulogic; HOSTEMAC1SEL : in std_ulogic; HOSTMIIMSEL : in std_ulogic; HOSTOPCODE : in std_logic_vector(1 downto 0); HOSTREQ : in std_ulogic; HOSTWRDATA : in std_logic_vector(31 downto 0); PHYEMAC0COL : in std_ulogic; PHYEMAC0CRS : in std_ulogic; PHYEMAC0GTXCLK : in std_ulogic; PHYEMAC0MCLKIN : in std_ulogic; PHYEMAC0MDIN : in std_ulogic; PHYEMAC0MIITXCLK : in std_ulogic; PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); PHYEMAC0RXBUFERR : in std_ulogic; PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); PHYEMAC0RXCHARISCOMMA : in std_ulogic; PHYEMAC0RXCHARISK : in std_ulogic; PHYEMAC0RXCHECKINGCRC : in std_ulogic; PHYEMAC0RXCLK : in std_ulogic; PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); PHYEMAC0RXCOMMADET : in std_ulogic; PHYEMAC0RXD : in std_logic_vector(7 downto 0); PHYEMAC0RXDISPERR : in std_ulogic; PHYEMAC0RXDV : in std_ulogic; PHYEMAC0RXER : in std_ulogic; PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); PHYEMAC0RXNOTINTABLE : in std_ulogic; PHYEMAC0RXRUNDISP : in std_ulogic; PHYEMAC0SIGNALDET : in std_ulogic; PHYEMAC0TXBUFERR : in std_ulogic; PHYEMAC0TXGMIIMIICLKIN : in std_ulogic; PHYEMAC1COL : in std_ulogic; PHYEMAC1CRS : in std_ulogic; PHYEMAC1GTXCLK : in std_ulogic; PHYEMAC1MCLKIN : in std_ulogic; PHYEMAC1MDIN : in std_ulogic; PHYEMAC1MIITXCLK : in std_ulogic; PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); PHYEMAC1RXBUFERR : in std_ulogic; PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); PHYEMAC1RXCHARISCOMMA : in std_ulogic; PHYEMAC1RXCHARISK : in std_ulogic; PHYEMAC1RXCHECKINGCRC : in std_ulogic; PHYEMAC1RXCLK : in std_ulogic; PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); PHYEMAC1RXCOMMADET : in std_ulogic; PHYEMAC1RXD : in std_logic_vector(7 downto 0); PHYEMAC1RXDISPERR : in std_ulogic; PHYEMAC1RXDV : in std_ulogic; PHYEMAC1RXER : in std_ulogic; PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); PHYEMAC1RXNOTINTABLE : in std_ulogic; PHYEMAC1RXRUNDISP : in std_ulogic; PHYEMAC1SIGNALDET : in std_ulogic; PHYEMAC1TXBUFERR : in std_ulogic; PHYEMAC1TXGMIIMIICLKIN : in std_ulogic; RESET : in std_ulogic ); end TEMAC; architecture TEMAC_V of TEMAC is component TEMAC_SWIFT port ( DCRHOSTDONEIR : out std_ulogic; EMAC0CLIENTANINTERRUPT : out std_ulogic; EMAC0CLIENTRXBADFRAME : out std_ulogic; EMAC0CLIENTRXCLIENTCLKOUT : out std_ulogic; EMAC0CLIENTRXD : out std_logic_vector(15 downto 0); EMAC0CLIENTRXDVLD : out std_ulogic; EMAC0CLIENTRXDVLDMSW : out std_ulogic; EMAC0CLIENTRXFRAMEDROP : out std_ulogic; EMAC0CLIENTRXGOODFRAME : out std_ulogic; EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); EMAC0CLIENTRXSTATSBYTEVLD : out std_ulogic; EMAC0CLIENTRXSTATSVLD : out std_ulogic; EMAC0CLIENTTXACK : out std_ulogic; EMAC0CLIENTTXCLIENTCLKOUT : out std_ulogic; EMAC0CLIENTTXCOLLISION : out std_ulogic; EMAC0CLIENTTXRETRANSMIT : out std_ulogic; EMAC0CLIENTTXSTATS : out std_ulogic; EMAC0CLIENTTXSTATSBYTEVLD : out std_ulogic; EMAC0CLIENTTXSTATSVLD : out std_ulogic; EMAC0PHYENCOMMAALIGN : out std_ulogic; EMAC0PHYLOOPBACKMSB : out std_ulogic; EMAC0PHYMCLKOUT : out std_ulogic; EMAC0PHYMDOUT : out std_ulogic; EMAC0PHYMDTRI : out std_ulogic; EMAC0PHYMGTRXRESET : out std_ulogic; EMAC0PHYMGTTXRESET : out std_ulogic; EMAC0PHYPOWERDOWN : out std_ulogic; EMAC0PHYSYNCACQSTATUS : out std_ulogic; EMAC0PHYTXCHARDISPMODE : out std_ulogic; EMAC0PHYTXCHARDISPVAL : out std_ulogic; EMAC0PHYTXCHARISK : out std_ulogic; EMAC0PHYTXCLK : out std_ulogic; EMAC0PHYTXD : out std_logic_vector(7 downto 0); EMAC0PHYTXEN : out std_ulogic; EMAC0PHYTXER : out std_ulogic; EMAC0PHYTXGMIIMIICLKOUT : out std_ulogic; EMAC0SPEEDIS10100 : out std_ulogic; EMAC1CLIENTANINTERRUPT : out std_ulogic; EMAC1CLIENTRXBADFRAME : out std_ulogic; EMAC1CLIENTRXCLIENTCLKOUT : out std_ulogic; EMAC1CLIENTRXD : out std_logic_vector(15 downto 0); EMAC1CLIENTRXDVLD : out std_ulogic; EMAC1CLIENTRXDVLDMSW : out std_ulogic; EMAC1CLIENTRXFRAMEDROP : out std_ulogic; EMAC1CLIENTRXGOODFRAME : out std_ulogic; EMAC1CLIENTRXSTATS : out std_logic_vector(6 downto 0); EMAC1CLIENTRXSTATSBYTEVLD : out std_ulogic; EMAC1CLIENTRXSTATSVLD : out std_ulogic; EMAC1CLIENTTXACK : out std_ulogic; EMAC1CLIENTTXCLIENTCLKOUT : out std_ulogic; EMAC1CLIENTTXCOLLISION : out std_ulogic; EMAC1CLIENTTXRETRANSMIT : out std_ulogic; EMAC1CLIENTTXSTATS : out std_ulogic; EMAC1CLIENTTXSTATSBYTEVLD : out std_ulogic; EMAC1CLIENTTXSTATSVLD : out std_ulogic; EMAC1PHYENCOMMAALIGN : out std_ulogic; EMAC1PHYLOOPBACKMSB : out std_ulogic; EMAC1PHYMCLKOUT : out std_ulogic; EMAC1PHYMDOUT : out std_ulogic; EMAC1PHYMDTRI : out std_ulogic; EMAC1PHYMGTRXRESET : out std_ulogic; EMAC1PHYMGTTXRESET : out std_ulogic; EMAC1PHYPOWERDOWN : out std_ulogic; EMAC1PHYSYNCACQSTATUS : out std_ulogic; EMAC1PHYTXCHARDISPMODE : out std_ulogic; EMAC1PHYTXCHARDISPVAL : out std_ulogic; EMAC1PHYTXCHARISK : out std_ulogic; EMAC1PHYTXCLK : out std_ulogic; EMAC1PHYTXD : out std_logic_vector(7 downto 0); EMAC1PHYTXEN : out std_ulogic; EMAC1PHYTXER : out std_ulogic; EMAC1PHYTXGMIIMIICLKOUT : out std_ulogic; EMAC1SPEEDIS10100 : out std_ulogic; EMACDCRACK : out std_ulogic; EMACDCRDBUS : out std_logic_vector(0 to 31); HOSTMIIMRDY : out std_ulogic; HOSTRDDATA : out std_logic_vector(31 downto 0); CLIENTEMAC0DCMLOCKED : in std_ulogic; CLIENTEMAC0PAUSEREQ : in std_ulogic; CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); CLIENTEMAC0RXCLIENTCLKIN : in std_ulogic; CLIENTEMAC0TXCLIENTCLKIN : in std_ulogic; CLIENTEMAC0TXD : in std_logic_vector(15 downto 0); CLIENTEMAC0TXDVLD : in std_ulogic; CLIENTEMAC0TXDVLDMSW : in std_ulogic; CLIENTEMAC0TXFIRSTBYTE : in std_ulogic; CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); CLIENTEMAC0TXUNDERRUN : in std_ulogic; CLIENTEMAC1DCMLOCKED : in std_ulogic; CLIENTEMAC1PAUSEREQ : in std_ulogic; CLIENTEMAC1PAUSEVAL : in std_logic_vector(15 downto 0); CLIENTEMAC1RXCLIENTCLKIN : in std_ulogic; CLIENTEMAC1TXCLIENTCLKIN : in std_ulogic; CLIENTEMAC1TXD : in std_logic_vector(15 downto 0); CLIENTEMAC1TXDVLD : in std_ulogic; CLIENTEMAC1TXDVLDMSW : in std_ulogic; CLIENTEMAC1TXFIRSTBYTE : in std_ulogic; CLIENTEMAC1TXIFGDELAY : in std_logic_vector(7 downto 0); CLIENTEMAC1TXUNDERRUN : in std_ulogic; DCREMACABUS : in std_logic_vector(0 to 9); DCREMACCLK : in std_ulogic; DCREMACDBUS : in std_logic_vector(0 to 31); DCREMACENABLE : in std_ulogic; DCREMACREAD : in std_ulogic; DCREMACWRITE : in std_ulogic; HOSTADDR : in std_logic_vector(9 downto 0); HOSTCLK : in std_ulogic; HOSTEMAC1SEL : in std_ulogic; HOSTMIIMSEL : in std_ulogic; HOSTOPCODE : in std_logic_vector(1 downto 0); HOSTREQ : in std_ulogic; HOSTWRDATA : in std_logic_vector(31 downto 0); PHYEMAC0COL : in std_ulogic; PHYEMAC0CRS : in std_ulogic; PHYEMAC0GTXCLK : in std_ulogic; PHYEMAC0MCLKIN : in std_ulogic; PHYEMAC0MDIN : in std_ulogic; PHYEMAC0MIITXCLK : in std_ulogic; PHYEMAC0PHYAD : in std_logic_vector(4 downto 0); PHYEMAC0RXBUFERR : in std_ulogic; PHYEMAC0RXBUFSTATUS : in std_logic_vector(1 downto 0); PHYEMAC0RXCHARISCOMMA : in std_ulogic; PHYEMAC0RXCHARISK : in std_ulogic; PHYEMAC0RXCHECKINGCRC : in std_ulogic; PHYEMAC0RXCLK : in std_ulogic; PHYEMAC0RXCLKCORCNT : in std_logic_vector(2 downto 0); PHYEMAC0RXCOMMADET : in std_ulogic; PHYEMAC0RXD : in std_logic_vector(7 downto 0); PHYEMAC0RXDISPERR : in std_ulogic; PHYEMAC0RXDV : in std_ulogic; PHYEMAC0RXER : in std_ulogic; PHYEMAC0RXLOSSOFSYNC : in std_logic_vector(1 downto 0); PHYEMAC0RXNOTINTABLE : in std_ulogic; PHYEMAC0RXRUNDISP : in std_ulogic; PHYEMAC0SIGNALDET : in std_ulogic; PHYEMAC0TXBUFERR : in std_ulogic; PHYEMAC0TXGMIIMIICLKIN : in std_ulogic; PHYEMAC1COL : in std_ulogic; PHYEMAC1CRS : in std_ulogic; PHYEMAC1GTXCLK : in std_ulogic; PHYEMAC1MCLKIN : in std_ulogic; PHYEMAC1MDIN : in std_ulogic; PHYEMAC1MIITXCLK : in std_ulogic; PHYEMAC1PHYAD : in std_logic_vector(4 downto 0); PHYEMAC1RXBUFERR : in std_ulogic; PHYEMAC1RXBUFSTATUS : in std_logic_vector(1 downto 0); PHYEMAC1RXCHARISCOMMA : in std_ulogic; PHYEMAC1RXCHARISK : in std_ulogic; PHYEMAC1RXCHECKINGCRC : in std_ulogic; PHYEMAC1RXCLK : in std_ulogic; PHYEMAC1RXCLKCORCNT : in std_logic_vector(2 downto 0); PHYEMAC1RXCOMMADET : in std_ulogic; PHYEMAC1RXD : in std_logic_vector(7 downto 0); PHYEMAC1RXDISPERR : in std_ulogic; PHYEMAC1RXDV : in std_ulogic; PHYEMAC1RXER : in std_ulogic; PHYEMAC1RXLOSSOFSYNC : in std_logic_vector(1 downto 0); PHYEMAC1RXNOTINTABLE : in std_ulogic; PHYEMAC1RXRUNDISP : in std_ulogic; PHYEMAC1SIGNALDET : in std_ulogic; PHYEMAC1TXBUFERR : in std_ulogic; PHYEMAC1TXGMIIMIICLKIN : in std_ulogic; RESET : in std_ulogic; EMAC0_1000BASEX_ENABLE : in std_ulogic; EMAC0_ADDRFILTER_ENABLE : in std_ulogic; EMAC0_BYTEPHY : in std_ulogic; EMAC0_CONFIGVEC_79 : in std_ulogic; EMAC0_DCRBASEADDR : in std_logic_vector(0 to 7); EMAC0_GTLOOPBACK : in std_ulogic; EMAC0_HOST_ENABLE : in std_ulogic; EMAC0_LINKTIMERVAL : in std_logic_vector(8 downto 0); EMAC0_LTCHECK_DISABLE : in std_ulogic; EMAC0_MDIO_ENABLE : in std_ulogic; EMAC0_PAUSEADDR : in std_logic_vector(47 downto 0); EMAC0_PHYINITAUTONEG_ENABLE : in std_ulogic; EMAC0_PHYISOLATE : in std_ulogic; EMAC0_PHYLOOPBACKMSB : in std_ulogic; EMAC0_PHYPOWERDOWN : in std_ulogic; EMAC0_PHYRESET : in std_ulogic; EMAC0_RGMII_ENABLE : in std_ulogic; EMAC0_RX16BITCLIENT_ENABLE : in std_ulogic; EMAC0_RXFLOWCTRL_ENABLE : in std_ulogic; EMAC0_RXHALFDUPLEX : in std_ulogic; EMAC0_RXINBANDFCS_ENABLE : in std_ulogic; EMAC0_RXJUMBOFRAME_ENABLE : in std_ulogic; EMAC0_RXRESET : in std_ulogic; EMAC0_RXVLAN_ENABLE : in std_ulogic; EMAC0_RX_ENABLE : in std_ulogic; EMAC0_SGMII_ENABLE : in std_ulogic; EMAC0_SPEED_LSB : in std_ulogic; EMAC0_SPEED_MSB : in std_ulogic; EMAC0_TX16BITCLIENT_ENABLE : in std_ulogic; EMAC0_TXFLOWCTRL_ENABLE : in std_ulogic; EMAC0_TXHALFDUPLEX : in std_ulogic; EMAC0_TXIFGADJUST_ENABLE : in std_ulogic; EMAC0_TXINBANDFCS_ENABLE : in std_ulogic; EMAC0_TXJUMBOFRAME_ENABLE : in std_ulogic; EMAC0_TXRESET : in std_ulogic; EMAC0_TXVLAN_ENABLE : in std_ulogic; EMAC0_TX_ENABLE : in std_ulogic; EMAC0_UNICASTADDR : in std_logic_vector(47 downto 0); EMAC0_UNIDIRECTION_ENABLE : in std_ulogic; EMAC0_USECLKEN : in std_ulogic; EMAC1_1000BASEX_ENABLE : in std_ulogic; EMAC1_ADDRFILTER_ENABLE : in std_ulogic; EMAC1_BYTEPHY : in std_ulogic; EMAC1_CONFIGVEC_79 : in std_ulogic; EMAC1_DCRBASEADDR : in std_logic_vector(0 to 7); EMAC1_GTLOOPBACK : in std_ulogic; EMAC1_HOST_ENABLE : in std_ulogic; EMAC1_LINKTIMERVAL : in std_logic_vector(8 downto 0); EMAC1_LTCHECK_DISABLE : in std_ulogic; EMAC1_MDIO_ENABLE : in std_ulogic; EMAC1_PAUSEADDR : in std_logic_vector(47 downto 0); EMAC1_PHYINITAUTONEG_ENABLE : in std_ulogic; EMAC1_PHYISOLATE : in std_ulogic; EMAC1_PHYLOOPBACKMSB : in std_ulogic; EMAC1_PHYPOWERDOWN : in std_ulogic; EMAC1_PHYRESET : in std_ulogic; EMAC1_RGMII_ENABLE : in std_ulogic; EMAC1_RX16BITCLIENT_ENABLE : in std_ulogic; EMAC1_RXFLOWCTRL_ENABLE : in std_ulogic; EMAC1_RXHALFDUPLEX : in std_ulogic; EMAC1_RXINBANDFCS_ENABLE : in std_ulogic; EMAC1_RXJUMBOFRAME_ENABLE : in std_ulogic; EMAC1_RXRESET : in std_ulogic; EMAC1_RXVLAN_ENABLE : in std_ulogic; EMAC1_RX_ENABLE : in std_ulogic; EMAC1_SGMII_ENABLE : in std_ulogic; EMAC1_SPEED_LSB : in std_ulogic; EMAC1_SPEED_MSB : in std_ulogic; EMAC1_TX16BITCLIENT_ENABLE : in std_ulogic; EMAC1_TXFLOWCTRL_ENABLE : in std_ulogic; EMAC1_TXHALFDUPLEX : in std_ulogic; EMAC1_TXIFGADJUST_ENABLE : in std_ulogic; EMAC1_TXINBANDFCS_ENABLE : in std_ulogic; EMAC1_TXJUMBOFRAME_ENABLE : in std_ulogic; EMAC1_TXRESET : in std_ulogic; EMAC1_TXVLAN_ENABLE : in std_ulogic; EMAC1_TX_ENABLE : in std_ulogic; EMAC1_UNICASTADDR : in std_logic_vector(47 downto 0); EMAC1_UNIDIRECTION_ENABLE : in std_ulogic; EMAC1_USECLKEN : in std_ulogic ); end component; function GetValue_EMAC0 ( EMAC0_TX16BITCLIENT_ENABLE : in boolean ) return time is variable delay_time : time; begin case EMAC0_TX16BITCLIENT_ENABLE is when TRUE => delay_time := 25 ps; when FALSE => delay_time := 0 ps; end case; return delay_time; end; function GetValue_EMAC1 ( EMAC1_TX16BITCLIENT_ENABLE : in boolean ) return time is variable delay_time : time; begin case EMAC1_TX16BITCLIENT_ENABLE is when TRUE => delay_time := 25 ps; when FALSE => delay_time := 0 ps; end case; return delay_time; end; constant IN_DELAY : time := 50 ps; constant OUT_DELAY : time := 0 ps; constant CLK_DELAY : time := 0 ps; constant EMAC0MIITXCLK_DELAY : time := GetValue_EMAC0(EMAC0_TX16BITCLIENT_ENABLE); constant EMAC1MIITXCLK_DELAY : time := GetValue_EMAC1(EMAC1_TX16BITCLIENT_ENABLE); constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); signal EMAC0_PAUSEADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC0_PAUSEADDR); signal EMAC0_RXHALFDUPLEX_BINARY : std_ulogic; signal EMAC0_RXVLAN_ENABLE_BINARY : std_ulogic; signal EMAC0_RX_ENABLE_BINARY : std_ulogic; signal EMAC0_RXINBANDFCS_ENABLE_BINARY : std_ulogic; signal EMAC0_RXJUMBOFRAME_ENABLE_BINARY : std_ulogic; signal EMAC0_RXRESET_BINARY : std_ulogic; signal EMAC0_TXIFGADJUST_ENABLE_BINARY : std_ulogic; signal EMAC0_TXHALFDUPLEX_BINARY : std_ulogic; signal EMAC0_TXVLAN_ENABLE_BINARY : std_ulogic; signal EMAC0_TX_ENABLE_BINARY : std_ulogic; signal EMAC0_TXINBANDFCS_ENABLE_BINARY : std_ulogic; signal EMAC0_TXJUMBOFRAME_ENABLE_BINARY : std_ulogic; signal EMAC0_TXRESET_BINARY : std_ulogic; signal EMAC0_TXFLOWCTRL_ENABLE_BINARY : std_ulogic; signal EMAC0_RXFLOWCTRL_ENABLE_BINARY : std_ulogic; signal EMAC0_LTCHECK_DISABLE_BINARY : std_ulogic; signal EMAC0_ADDRFILTER_ENABLE_BINARY : std_ulogic; signal EMAC0_RX16BITCLIENT_ENABLE_BINARY : std_ulogic; signal EMAC0_TX16BITCLIENT_ENABLE_BINARY : std_ulogic; signal EMAC0_HOST_ENABLE_BINARY : std_ulogic; signal EMAC0_1000BASEX_ENABLE_BINARY : std_ulogic; signal EMAC0_SGMII_ENABLE_BINARY : std_ulogic; signal EMAC0_RGMII_ENABLE_BINARY : std_ulogic; signal EMAC0_SPEED_LSB_BINARY : std_ulogic; signal EMAC0_SPEED_MSB_BINARY : std_ulogic; signal EMAC0_MDIO_ENABLE_BINARY : std_ulogic; signal EMAC0_PHYLOOPBACKMSB_BINARY : std_ulogic; signal EMAC0_PHYPOWERDOWN_BINARY : std_ulogic; signal EMAC0_PHYISOLATE_BINARY : std_ulogic; signal EMAC0_PHYINITAUTONEG_ENABLE_BINARY : std_ulogic; signal EMAC0_PHYRESET_BINARY : std_ulogic; signal EMAC0_CONFIGVEC_79_BINARY : std_ulogic; signal EMAC0_UNIDIRECTION_ENABLE_BINARY : std_ulogic; signal EMAC0_GTLOOPBACK_BINARY : std_ulogic; signal EMAC0_UNICASTADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC0_UNICASTADDR); signal EMAC0_LINKTIMERVAL_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(EMAC0_LINKTIMERVAL)(8 downto 0); signal EMAC0_BYTEPHY_BINARY : std_ulogic; signal EMAC0_USECLKEN_BINARY : std_ulogic; signal EMAC0_DCRBASEADDR_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(EMAC0_DCRBASEADDR); signal EMAC1_PAUSEADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC1_PAUSEADDR); signal EMAC1_RXHALFDUPLEX_BINARY : std_ulogic; signal EMAC1_RXVLAN_ENABLE_BINARY : std_ulogic; signal EMAC1_RX_ENABLE_BINARY : std_ulogic; signal EMAC1_RXINBANDFCS_ENABLE_BINARY : std_ulogic; signal EMAC1_RXJUMBOFRAME_ENABLE_BINARY : std_ulogic; signal EMAC1_RXRESET_BINARY : std_ulogic; signal EMAC1_TXIFGADJUST_ENABLE_BINARY : std_ulogic; signal EMAC1_TXHALFDUPLEX_BINARY : std_ulogic; signal EMAC1_TXVLAN_ENABLE_BINARY : std_ulogic; signal EMAC1_TX_ENABLE_BINARY : std_ulogic; signal EMAC1_TXINBANDFCS_ENABLE_BINARY : std_ulogic; signal EMAC1_TXJUMBOFRAME_ENABLE_BINARY : std_ulogic; signal EMAC1_TXRESET_BINARY : std_ulogic; signal EMAC1_TXFLOWCTRL_ENABLE_BINARY : std_ulogic; signal EMAC1_RXFLOWCTRL_ENABLE_BINARY : std_ulogic; signal EMAC1_LTCHECK_DISABLE_BINARY : std_ulogic; signal EMAC1_ADDRFILTER_ENABLE_BINARY : std_ulogic; signal EMAC1_RX16BITCLIENT_ENABLE_BINARY : std_ulogic; signal EMAC1_TX16BITCLIENT_ENABLE_BINARY : std_ulogic; signal EMAC1_HOST_ENABLE_BINARY : std_ulogic; signal EMAC1_1000BASEX_ENABLE_BINARY : std_ulogic; signal EMAC1_SGMII_ENABLE_BINARY : std_ulogic; signal EMAC1_RGMII_ENABLE_BINARY : std_ulogic; signal EMAC1_SPEED_LSB_BINARY : std_ulogic; signal EMAC1_SPEED_MSB_BINARY : std_ulogic; signal EMAC1_MDIO_ENABLE_BINARY : std_ulogic; signal EMAC1_PHYLOOPBACKMSB_BINARY : std_ulogic; signal EMAC1_PHYPOWERDOWN_BINARY : std_ulogic; signal EMAC1_PHYISOLATE_BINARY : std_ulogic; signal EMAC1_PHYINITAUTONEG_ENABLE_BINARY : std_ulogic; signal EMAC1_PHYRESET_BINARY : std_ulogic; signal EMAC1_CONFIGVEC_79_BINARY : std_ulogic; signal EMAC1_UNIDIRECTION_ENABLE_BINARY : std_ulogic; signal EMAC1_GTLOOPBACK_BINARY : std_ulogic; signal EMAC1_UNICASTADDR_BINARY : std_logic_vector(47 downto 0) := To_StdLogicVector(EMAC1_UNICASTADDR); signal EMAC1_LINKTIMERVAL_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(EMAC1_LINKTIMERVAL)(8 downto 0); signal EMAC1_BYTEPHY_BINARY : std_ulogic; signal EMAC1_USECLKEN_BINARY : std_ulogic; signal EMAC1_DCRBASEADDR_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(EMAC1_DCRBASEADDR); signal DCRHOSTDONEIR_out : std_ulogic; signal EMAC0CLIENTANINTERRUPT_out : std_ulogic; signal EMAC0CLIENTRXBADFRAME_out : std_ulogic; signal EMAC0CLIENTRXCLIENTCLKOUT_out : std_ulogic; signal EMAC0CLIENTRXD_out : std_logic_vector(15 downto 0); signal EMAC0CLIENTRXDVLD_out : std_ulogic; signal EMAC0CLIENTRXDVLDMSW_out : std_ulogic; signal EMAC0CLIENTRXFRAMEDROP_out : std_ulogic; signal EMAC0CLIENTRXGOODFRAME_out : std_ulogic; signal EMAC0CLIENTRXSTATS_out : std_logic_vector(6 downto 0); signal EMAC0CLIENTRXSTATSBYTEVLD_out : std_ulogic; signal EMAC0CLIENTRXSTATSVLD_out : std_ulogic; signal EMAC0CLIENTTXACK_out : std_ulogic; signal EMAC0CLIENTTXCLIENTCLKOUT_out : std_ulogic; signal EMAC0CLIENTTXCOLLISION_out : std_ulogic; signal EMAC0PHYTXGMIIMIICLKOUT_out : std_ulogic; signal EMAC0CLIENTTXRETRANSMIT_out : std_ulogic; signal EMAC0CLIENTTXSTATS_out : std_ulogic; signal EMAC0CLIENTTXSTATSBYTEVLD_out : std_ulogic; signal EMAC0CLIENTTXSTATSVLD_out : std_ulogic; signal EMAC0PHYENCOMMAALIGN_out : std_ulogic; signal EMAC0PHYLOOPBACKMSB_out : std_ulogic; signal EMAC0PHYMCLKOUT_out : std_ulogic; signal EMAC0PHYMDOUT_out : std_ulogic; signal EMAC0PHYMDTRI_out : std_ulogic; signal EMAC0PHYMGTRXRESET_out : std_ulogic; signal EMAC0PHYMGTTXRESET_out : std_ulogic; signal EMAC0PHYPOWERDOWN_out : std_ulogic; signal EMAC0PHYSYNCACQSTATUS_out : std_ulogic; signal EMAC0PHYTXCHARDISPMODE_out : std_ulogic; signal EMAC0PHYTXCHARDISPVAL_out : std_ulogic; signal EMAC0PHYTXCHARISK_out : std_ulogic; signal EMAC0PHYTXCLK_out : std_ulogic; signal EMAC0PHYTXD_out : std_logic_vector(7 downto 0); signal EMAC0PHYTXEN_out : std_ulogic; signal EMAC0PHYTXER_out : std_ulogic; signal EMAC0SPEEDIS10100_out : std_ulogic; signal EMAC1CLIENTANINTERRUPT_out : std_ulogic; signal EMAC1CLIENTRXBADFRAME_out : std_ulogic; signal EMAC1CLIENTRXCLIENTCLKOUT_out : std_ulogic; signal EMAC1CLIENTRXD_out : std_logic_vector(15 downto 0); signal EMAC1CLIENTRXDVLD_out : std_ulogic; signal EMAC1CLIENTRXDVLDMSW_out : std_ulogic; signal EMAC1CLIENTRXFRAMEDROP_out : std_ulogic; signal EMAC1CLIENTRXGOODFRAME_out : std_ulogic; signal EMAC1CLIENTRXSTATS_out : std_logic_vector(6 downto 0); signal EMAC1CLIENTRXSTATSBYTEVLD_out : std_ulogic; signal EMAC1CLIENTRXSTATSVLD_out : std_ulogic; signal EMAC1CLIENTTXACK_out : std_ulogic; signal EMAC1CLIENTTXCLIENTCLKOUT_out : std_ulogic; signal EMAC1CLIENTTXCOLLISION_out : std_ulogic; signal EMAC1PHYTXGMIIMIICLKOUT_out : std_ulogic; signal EMAC1CLIENTTXRETRANSMIT_out : std_ulogic; signal EMAC1CLIENTTXSTATS_out : std_ulogic; signal EMAC1CLIENTTXSTATSBYTEVLD_out : std_ulogic; signal EMAC1CLIENTTXSTATSVLD_out : std_ulogic; signal EMAC1PHYENCOMMAALIGN_out : std_ulogic; signal EMAC1PHYLOOPBACKMSB_out : std_ulogic; signal EMAC1PHYMCLKOUT_out : std_ulogic; signal EMAC1PHYMDOUT_out : std_ulogic; signal EMAC1PHYMDTRI_out : std_ulogic; signal EMAC1PHYMGTRXRESET_out : std_ulogic; signal EMAC1PHYMGTTXRESET_out : std_ulogic; signal EMAC1PHYPOWERDOWN_out : std_ulogic; signal EMAC1PHYSYNCACQSTATUS_out : std_ulogic; signal EMAC1PHYTXCHARDISPMODE_out : std_ulogic; signal EMAC1PHYTXCHARDISPVAL_out : std_ulogic; signal EMAC1PHYTXCHARISK_out : std_ulogic; signal EMAC1PHYTXCLK_out : std_ulogic; signal EMAC1PHYTXD_out : std_logic_vector(7 downto 0); signal EMAC1PHYTXEN_out : std_ulogic; signal EMAC1PHYTXER_out : std_ulogic; signal EMAC1SPEEDIS10100_out : std_ulogic; signal EMACDCRACK_out : std_ulogic; signal EMACDCRDBUS_out : std_logic_vector(0 to 31); signal HOSTMIIMRDY_out : std_ulogic; signal HOSTRDDATA_out : std_logic_vector(31 downto 0); signal EMAC0CLIENTRXCLIENTCLKOUT_outdelay : std_ulogic; signal EMAC0CLIENTTXCLIENTCLKOUT_outdelay : std_ulogic; signal EMAC0PHYTXGMIIMIICLKOUT_outdelay : std_ulogic; signal EMAC0PHYMCLKOUT_outdelay : std_ulogic; signal EMAC0PHYTXCLK_outdelay : std_ulogic; signal EMAC1CLIENTRXCLIENTCLKOUT_outdelay : std_ulogic; signal EMAC1CLIENTTXCLIENTCLKOUT_outdelay : std_ulogic; signal EMAC1PHYTXGMIIMIICLKOUT_outdelay : std_ulogic; signal EMAC1PHYMCLKOUT_outdelay : std_ulogic; signal EMAC1PHYTXCLK_outdelay : std_ulogic; signal DCRHOSTDONEIR_outdelay : std_ulogic; signal EMAC0CLIENTANINTERRUPT_outdelay : std_ulogic; signal EMAC0CLIENTRXBADFRAME_outdelay : std_ulogic; signal EMAC0CLIENTRXD_outdelay : std_logic_vector(15 downto 0); signal EMAC0CLIENTRXDVLD_outdelay : std_ulogic; signal EMAC0CLIENTRXDVLDMSW_outdelay : std_ulogic; signal EMAC0CLIENTRXFRAMEDROP_outdelay : std_ulogic; signal EMAC0CLIENTRXGOODFRAME_outdelay : std_ulogic; signal EMAC0CLIENTRXSTATS_outdelay : std_logic_vector(6 downto 0); signal EMAC0CLIENTRXSTATSBYTEVLD_outdelay : std_ulogic; signal EMAC0CLIENTRXSTATSVLD_outdelay : std_ulogic; signal EMAC0CLIENTTXACK_outdelay : std_ulogic; signal EMAC0CLIENTTXCOLLISION_outdelay : std_ulogic; signal EMAC0CLIENTTXRETRANSMIT_outdelay : std_ulogic; signal EMAC0CLIENTTXSTATS_outdelay : std_ulogic; signal EMAC0CLIENTTXSTATSBYTEVLD_outdelay : std_ulogic; signal EMAC0CLIENTTXSTATSVLD_outdelay : std_ulogic; signal EMAC0PHYENCOMMAALIGN_outdelay : std_ulogic; signal EMAC0PHYLOOPBACKMSB_outdelay : std_ulogic; signal EMAC0PHYMDOUT_outdelay : std_ulogic; signal EMAC0PHYMDTRI_outdelay : std_ulogic; signal EMAC0PHYMGTRXRESET_outdelay : std_ulogic; signal EMAC0PHYMGTTXRESET_outdelay : std_ulogic; signal EMAC0PHYPOWERDOWN_outdelay : std_ulogic; signal EMAC0PHYSYNCACQSTATUS_outdelay : std_ulogic; signal EMAC0PHYTXCHARDISPMODE_outdelay : std_ulogic; signal EMAC0PHYTXCHARDISPVAL_outdelay : std_ulogic; signal EMAC0PHYTXCHARISK_outdelay : std_ulogic; signal EMAC0PHYTXD_outdelay : std_logic_vector(7 downto 0); signal EMAC0PHYTXEN_outdelay : std_ulogic; signal EMAC0PHYTXER_outdelay : std_ulogic; signal EMAC0SPEEDIS10100_outdelay : std_ulogic; signal EMAC1CLIENTANINTERRUPT_outdelay : std_ulogic; signal EMAC1CLIENTRXBADFRAME_outdelay : std_ulogic; signal EMAC1CLIENTRXD_outdelay : std_logic_vector(15 downto 0); signal EMAC1CLIENTRXDVLD_outdelay : std_ulogic; signal EMAC1CLIENTRXDVLDMSW_outdelay : std_ulogic; signal EMAC1CLIENTRXFRAMEDROP_outdelay : std_ulogic; signal EMAC1CLIENTRXGOODFRAME_outdelay : std_ulogic; signal EMAC1CLIENTRXSTATS_outdelay : std_logic_vector(6 downto 0); signal EMAC1CLIENTRXSTATSBYTEVLD_outdelay : std_ulogic; signal EMAC1CLIENTRXSTATSVLD_outdelay : std_ulogic; signal EMAC1CLIENTTXACK_outdelay : std_ulogic; signal EMAC1CLIENTTXCOLLISION_outdelay : std_ulogic; signal EMAC1CLIENTTXRETRANSMIT_outdelay : std_ulogic; signal EMAC1CLIENTTXSTATS_outdelay : std_ulogic; signal EMAC1CLIENTTXSTATSBYTEVLD_outdelay : std_ulogic; signal EMAC1CLIENTTXSTATSVLD_outdelay : std_ulogic; signal EMAC1PHYENCOMMAALIGN_outdelay : std_ulogic; signal EMAC1PHYLOOPBACKMSB_outdelay : std_ulogic; signal EMAC1PHYMDOUT_outdelay : std_ulogic; signal EMAC1PHYMDTRI_outdelay : std_ulogic; signal EMAC1PHYMGTRXRESET_outdelay : std_ulogic; signal EMAC1PHYMGTTXRESET_outdelay : std_ulogic; signal EMAC1PHYPOWERDOWN_outdelay : std_ulogic; signal EMAC1PHYSYNCACQSTATUS_outdelay : std_ulogic; signal EMAC1PHYTXCHARDISPMODE_outdelay : std_ulogic; signal EMAC1PHYTXCHARDISPVAL_outdelay : std_ulogic; signal EMAC1PHYTXCHARISK_outdelay : std_ulogic; signal EMAC1PHYTXD_outdelay : std_logic_vector(7 downto 0); signal EMAC1PHYTXEN_outdelay : std_ulogic; signal EMAC1PHYTXER_outdelay : std_ulogic; signal EMAC1SPEEDIS10100_outdelay : std_ulogic; signal EMACDCRACK_outdelay : std_ulogic; signal EMACDCRDBUS_outdelay : std_logic_vector(0 to 31); signal HOSTMIIMRDY_outdelay : std_ulogic; signal HOSTRDDATA_outdelay : std_logic_vector(31 downto 0); signal CLIENTEMAC0DCMLOCKED_ipd : std_ulogic; signal CLIENTEMAC0PAUSEREQ_ipd : std_ulogic; signal CLIENTEMAC0PAUSEVAL_ipd : std_logic_vector(15 downto 0); signal CLIENTEMAC0RXCLIENTCLKIN_ipd : std_ulogic; signal CLIENTEMAC0TXCLIENTCLKIN_ipd : std_ulogic; signal CLIENTEMAC0TXD_ipd : std_logic_vector(15 downto 0); signal CLIENTEMAC0TXDVLD_ipd : std_ulogic; signal CLIENTEMAC0TXDVLDMSW_ipd : std_ulogic; signal CLIENTEMAC0TXFIRSTBYTE_ipd : std_ulogic; signal PHYEMAC0TXGMIIMIICLKIN_ipd : std_ulogic; signal CLIENTEMAC0TXIFGDELAY_ipd : std_logic_vector(7 downto 0); signal CLIENTEMAC0TXUNDERRUN_ipd : std_ulogic; signal CLIENTEMAC1DCMLOCKED_ipd : std_ulogic; signal CLIENTEMAC1PAUSEREQ_ipd : std_ulogic; signal CLIENTEMAC1PAUSEVAL_ipd : std_logic_vector(15 downto 0); signal CLIENTEMAC1RXCLIENTCLKIN_ipd : std_ulogic; signal CLIENTEMAC1TXCLIENTCLKIN_ipd : std_ulogic; signal CLIENTEMAC1TXD_ipd : std_logic_vector(15 downto 0); signal CLIENTEMAC1TXDVLD_ipd : std_ulogic; signal CLIENTEMAC1TXDVLDMSW_ipd : std_ulogic; signal CLIENTEMAC1TXFIRSTBYTE_ipd : std_ulogic; signal PHYEMAC1TXGMIIMIICLKIN_ipd : std_ulogic; signal CLIENTEMAC1TXIFGDELAY_ipd : std_logic_vector(7 downto 0); signal CLIENTEMAC1TXUNDERRUN_ipd : std_ulogic; signal DCREMACABUS_ipd : std_logic_vector(0 to 9); signal DCREMACCLK_ipd : std_ulogic; signal DCREMACDBUS_ipd : std_logic_vector(0 to 31); signal DCREMACENABLE_ipd : std_ulogic; signal DCREMACREAD_ipd : std_ulogic; signal DCREMACWRITE_ipd : std_ulogic; signal HOSTADDR_ipd : std_logic_vector(9 downto 0); signal HOSTCLK_ipd : std_ulogic; signal HOSTEMAC1SEL_ipd : std_ulogic; signal HOSTMIIMSEL_ipd : std_ulogic; signal HOSTOPCODE_ipd : std_logic_vector(1 downto 0); signal HOSTREQ_ipd : std_ulogic; signal HOSTWRDATA_ipd : std_logic_vector(31 downto 0); signal PHYEMAC0COL_ipd : std_ulogic; signal PHYEMAC0CRS_ipd : std_ulogic; signal PHYEMAC0GTXCLK_ipd : std_ulogic; signal PHYEMAC0MCLKIN_ipd : std_ulogic; signal PHYEMAC0MDIN_ipd : std_ulogic; signal PHYEMAC0MIITXCLK_ipd : std_ulogic; signal PHYEMAC0PHYAD_ipd : std_logic_vector(4 downto 0); signal PHYEMAC0RXBUFERR_ipd : std_ulogic; signal PHYEMAC0RXBUFSTATUS_ipd : std_logic_vector(1 downto 0); signal PHYEMAC0RXCHARISCOMMA_ipd : std_ulogic; signal PHYEMAC0RXCHARISK_ipd : std_ulogic; signal PHYEMAC0RXCHECKINGCRC_ipd : std_ulogic; signal PHYEMAC0RXCLK_ipd : std_ulogic; signal PHYEMAC0RXCLKCORCNT_ipd : std_logic_vector(2 downto 0); signal PHYEMAC0RXCOMMADET_ipd : std_ulogic; signal PHYEMAC0RXD_ipd : std_logic_vector(7 downto 0); signal PHYEMAC0RXDISPERR_ipd : std_ulogic; signal PHYEMAC0RXDV_ipd : std_ulogic; signal PHYEMAC0RXER_ipd : std_ulogic; signal PHYEMAC0RXLOSSOFSYNC_ipd : std_logic_vector(1 downto 0); signal PHYEMAC0RXNOTINTABLE_ipd : std_ulogic; signal PHYEMAC0RXRUNDISP_ipd : std_ulogic; signal PHYEMAC0SIGNALDET_ipd : std_ulogic; signal PHYEMAC0TXBUFERR_ipd : std_ulogic; signal PHYEMAC1COL_ipd : std_ulogic; signal PHYEMAC1CRS_ipd : std_ulogic; signal PHYEMAC1GTXCLK_ipd : std_ulogic; signal PHYEMAC1MCLKIN_ipd : std_ulogic; signal PHYEMAC1MDIN_ipd : std_ulogic; signal PHYEMAC1MIITXCLK_ipd : std_ulogic; signal PHYEMAC1PHYAD_ipd : std_logic_vector(4 downto 0); signal PHYEMAC1RXBUFERR_ipd : std_ulogic; signal PHYEMAC1RXBUFSTATUS_ipd : std_logic_vector(1 downto 0); signal PHYEMAC1RXCHARISCOMMA_ipd : std_ulogic; signal PHYEMAC1RXCHARISK_ipd : std_ulogic; signal PHYEMAC1RXCHECKINGCRC_ipd : std_ulogic; signal PHYEMAC1RXCLK_ipd : std_ulogic; signal PHYEMAC1RXCLKCORCNT_ipd : std_logic_vector(2 downto 0); signal PHYEMAC1RXCOMMADET_ipd : std_ulogic; signal PHYEMAC1RXD_ipd : std_logic_vector(7 downto 0); signal PHYEMAC1RXDISPERR_ipd : std_ulogic; signal PHYEMAC1RXDV_ipd : std_ulogic; signal PHYEMAC1RXER_ipd : std_ulogic; signal PHYEMAC1RXLOSSOFSYNC_ipd : std_logic_vector(1 downto 0); signal PHYEMAC1RXNOTINTABLE_ipd : std_ulogic; signal PHYEMAC1RXRUNDISP_ipd : std_ulogic; signal PHYEMAC1SIGNALDET_ipd : std_ulogic; signal PHYEMAC1TXBUFERR_ipd : std_ulogic; signal RESET_ipd : std_ulogic; signal CLIENTEMAC0DCMLOCKED_indelay : std_ulogic; signal CLIENTEMAC0PAUSEREQ_indelay : std_ulogic; signal CLIENTEMAC0PAUSEVAL_indelay : std_logic_vector(15 downto 0); signal CLIENTEMAC0RXCLIENTCLKIN_indelay : std_ulogic; signal CLIENTEMAC0TXCLIENTCLKIN_indelay : std_ulogic; signal CLIENTEMAC0TXD_indelay : std_logic_vector(15 downto 0); signal CLIENTEMAC0TXDVLD_indelay : std_ulogic; signal CLIENTEMAC0TXDVLDMSW_indelay : std_ulogic; signal CLIENTEMAC0TXFIRSTBYTE_indelay : std_ulogic; signal PHYEMAC0TXGMIIMIICLKIN_indelay : std_ulogic; signal CLIENTEMAC0TXIFGDELAY_indelay : std_logic_vector(7 downto 0); signal CLIENTEMAC0TXUNDERRUN_indelay : std_ulogic; signal CLIENTEMAC1DCMLOCKED_indelay : std_ulogic; signal CLIENTEMAC1PAUSEREQ_indelay : std_ulogic; signal CLIENTEMAC1PAUSEVAL_indelay : std_logic_vector(15 downto 0); signal CLIENTEMAC1RXCLIENTCLKIN_indelay : std_ulogic; signal CLIENTEMAC1TXCLIENTCLKIN_indelay : std_ulogic; signal CLIENTEMAC1TXD_indelay : std_logic_vector(15 downto 0); signal CLIENTEMAC1TXDVLD_indelay : std_ulogic; signal CLIENTEMAC1TXDVLDMSW_indelay : std_ulogic; signal CLIENTEMAC1TXFIRSTBYTE_indelay : std_ulogic; signal PHYEMAC1TXGMIIMIICLKIN_indelay : std_ulogic; signal CLIENTEMAC1TXIFGDELAY_indelay : std_logic_vector(7 downto 0); signal CLIENTEMAC1TXUNDERRUN_indelay : std_ulogic; signal DCREMACABUS_indelay : std_logic_vector(0 to 9); signal DCREMACCLK_indelay : std_ulogic; signal DCREMACDBUS_indelay : std_logic_vector(0 to 31); signal DCREMACENABLE_indelay : std_ulogic; signal DCREMACREAD_indelay : std_ulogic; signal DCREMACWRITE_indelay : std_ulogic; signal HOSTADDR_indelay : std_logic_vector(9 downto 0); signal HOSTCLK_indelay : std_ulogic; signal HOSTEMAC1SEL_indelay : std_ulogic; signal HOSTMIIMSEL_indelay : std_ulogic; signal HOSTOPCODE_indelay : std_logic_vector(1 downto 0); signal HOSTREQ_indelay : std_ulogic; signal HOSTWRDATA_indelay : std_logic_vector(31 downto 0); signal PHYEMAC0COL_indelay : std_ulogic; signal PHYEMAC0CRS_indelay : std_ulogic; signal PHYEMAC0GTXCLK_indelay : std_ulogic; signal PHYEMAC0MCLKIN_indelay : std_ulogic; signal PHYEMAC0MDIN_indelay : std_ulogic; signal PHYEMAC0MIITXCLK_indelay : std_ulogic; signal PHYEMAC0PHYAD_indelay : std_logic_vector(4 downto 0); signal PHYEMAC0RXBUFERR_indelay : std_ulogic; signal PHYEMAC0RXBUFSTATUS_indelay : std_logic_vector(1 downto 0); signal PHYEMAC0RXCHARISCOMMA_indelay : std_ulogic; signal PHYEMAC0RXCHARISK_indelay : std_ulogic; signal PHYEMAC0RXCHECKINGCRC_indelay : std_ulogic; signal PHYEMAC0RXCLK_indelay : std_ulogic; signal PHYEMAC0RXCLKCORCNT_indelay : std_logic_vector(2 downto 0); signal PHYEMAC0RXCOMMADET_indelay : std_ulogic; signal PHYEMAC0RXD_indelay : std_logic_vector(7 downto 0); signal PHYEMAC0RXDISPERR_indelay : std_ulogic; signal PHYEMAC0RXDV_indelay : std_ulogic; signal PHYEMAC0RXER_indelay : std_ulogic; signal PHYEMAC0RXLOSSOFSYNC_indelay : std_logic_vector(1 downto 0); signal PHYEMAC0RXNOTINTABLE_indelay : std_ulogic; signal PHYEMAC0RXRUNDISP_indelay : std_ulogic; signal PHYEMAC0SIGNALDET_indelay : std_ulogic; signal PHYEMAC0TXBUFERR_indelay : std_ulogic; signal PHYEMAC1COL_indelay : std_ulogic; signal PHYEMAC1CRS_indelay : std_ulogic; signal PHYEMAC1GTXCLK_indelay : std_ulogic; signal PHYEMAC1MCLKIN_indelay : std_ulogic; signal PHYEMAC1MDIN_indelay : std_ulogic; signal PHYEMAC1MIITXCLK_indelay : std_ulogic; signal PHYEMAC1PHYAD_indelay : std_logic_vector(4 downto 0); signal PHYEMAC1RXBUFERR_indelay : std_ulogic; signal PHYEMAC1RXBUFSTATUS_indelay : std_logic_vector(1 downto 0); signal PHYEMAC1RXCHARISCOMMA_indelay : std_ulogic; signal PHYEMAC1RXCHARISK_indelay : std_ulogic; signal PHYEMAC1RXCHECKINGCRC_indelay : std_ulogic; signal PHYEMAC1RXCLK_indelay : std_ulogic; signal PHYEMAC1RXCLKCORCNT_indelay : std_logic_vector(2 downto 0); signal PHYEMAC1RXCOMMADET_indelay : std_ulogic; signal PHYEMAC1RXD_indelay : std_logic_vector(7 downto 0); signal PHYEMAC1RXDISPERR_indelay : std_ulogic; signal PHYEMAC1RXDV_indelay : std_ulogic; signal PHYEMAC1RXER_indelay : std_ulogic; signal PHYEMAC1RXLOSSOFSYNC_indelay : std_logic_vector(1 downto 0); signal PHYEMAC1RXNOTINTABLE_indelay : std_ulogic; signal PHYEMAC1RXRUNDISP_indelay : std_ulogic; signal PHYEMAC1SIGNALDET_indelay : std_ulogic; signal PHYEMAC1TXBUFERR_indelay : std_ulogic; signal RESET_indelay : std_ulogic; begin EMAC0CLIENTRXCLIENTCLKOUT_out <= EMAC0CLIENTRXCLIENTCLKOUT_outdelay after CLK_DELAY; EMAC0CLIENTTXCLIENTCLKOUT_out <= EMAC0CLIENTTXCLIENTCLKOUT_outdelay after CLK_DELAY; EMAC0PHYMCLKOUT_out <= EMAC0PHYMCLKOUT_outdelay after CLK_DELAY; EMAC0PHYTXCLK_out <= EMAC0PHYTXCLK_outdelay after CLK_DELAY; EMAC0PHYTXGMIIMIICLKOUT_out <= EMAC0PHYTXGMIIMIICLKOUT_outdelay after CLK_DELAY; EMAC1CLIENTRXCLIENTCLKOUT_out <= EMAC1CLIENTRXCLIENTCLKOUT_outdelay after CLK_DELAY; EMAC1CLIENTTXCLIENTCLKOUT_out <= EMAC1CLIENTTXCLIENTCLKOUT_outdelay after CLK_DELAY; EMAC1PHYMCLKOUT_out <= EMAC1PHYMCLKOUT_outdelay after CLK_DELAY; EMAC1PHYTXCLK_out <= EMAC1PHYTXCLK_outdelay after CLK_DELAY; EMAC1PHYTXGMIIMIICLKOUT_out <= EMAC1PHYTXGMIIMIICLKOUT_outdelay after CLK_DELAY; DCRHOSTDONEIR_out <= DCRHOSTDONEIR_outdelay after OUT_DELAY; EMAC0CLIENTANINTERRUPT_out <= EMAC0CLIENTANINTERRUPT_outdelay after OUT_DELAY; EMAC0CLIENTRXBADFRAME_out <= EMAC0CLIENTRXBADFRAME_outdelay after OUT_DELAY; EMAC0CLIENTRXDVLDMSW_out <= EMAC0CLIENTRXDVLDMSW_outdelay after OUT_DELAY; EMAC0CLIENTRXDVLD_out <= EMAC0CLIENTRXDVLD_outdelay after OUT_DELAY; EMAC0CLIENTRXD_out <= EMAC0CLIENTRXD_outdelay after OUT_DELAY; EMAC0CLIENTRXFRAMEDROP_out <= EMAC0CLIENTRXFRAMEDROP_outdelay after OUT_DELAY; EMAC0CLIENTRXGOODFRAME_out <= EMAC0CLIENTRXGOODFRAME_outdelay after OUT_DELAY; EMAC0CLIENTRXSTATSBYTEVLD_out <= EMAC0CLIENTRXSTATSBYTEVLD_outdelay after OUT_DELAY; EMAC0CLIENTRXSTATSVLD_out <= EMAC0CLIENTRXSTATSVLD_outdelay after OUT_DELAY; EMAC0CLIENTRXSTATS_out <= EMAC0CLIENTRXSTATS_outdelay after OUT_DELAY; EMAC0CLIENTTXACK_out <= EMAC0CLIENTTXACK_outdelay after OUT_DELAY; EMAC0CLIENTTXCOLLISION_out <= EMAC0CLIENTTXCOLLISION_outdelay after OUT_DELAY; EMAC0CLIENTTXRETRANSMIT_out <= EMAC0CLIENTTXRETRANSMIT_outdelay after OUT_DELAY; EMAC0CLIENTTXSTATSBYTEVLD_out <= EMAC0CLIENTTXSTATSBYTEVLD_outdelay after OUT_DELAY; EMAC0CLIENTTXSTATSVLD_out <= EMAC0CLIENTTXSTATSVLD_outdelay after OUT_DELAY; EMAC0CLIENTTXSTATS_out <= EMAC0CLIENTTXSTATS_outdelay after OUT_DELAY; EMAC0PHYENCOMMAALIGN_out <= EMAC0PHYENCOMMAALIGN_outdelay after OUT_DELAY; EMAC0PHYLOOPBACKMSB_out <= EMAC0PHYLOOPBACKMSB_outdelay after OUT_DELAY; EMAC0PHYMDOUT_out <= EMAC0PHYMDOUT_outdelay after OUT_DELAY; EMAC0PHYMDTRI_out <= EMAC0PHYMDTRI_outdelay after OUT_DELAY; EMAC0PHYMGTRXRESET_out <= EMAC0PHYMGTRXRESET_outdelay after OUT_DELAY; EMAC0PHYMGTTXRESET_out <= EMAC0PHYMGTTXRESET_outdelay after OUT_DELAY; EMAC0PHYPOWERDOWN_out <= EMAC0PHYPOWERDOWN_outdelay after OUT_DELAY; EMAC0PHYSYNCACQSTATUS_out <= EMAC0PHYSYNCACQSTATUS_outdelay after OUT_DELAY; EMAC0PHYTXCHARDISPMODE_out <= EMAC0PHYTXCHARDISPMODE_outdelay after OUT_DELAY; EMAC0PHYTXCHARDISPVAL_out <= EMAC0PHYTXCHARDISPVAL_outdelay after OUT_DELAY; EMAC0PHYTXCHARISK_out <= EMAC0PHYTXCHARISK_outdelay after OUT_DELAY; EMAC0PHYTXD_out <= EMAC0PHYTXD_outdelay after OUT_DELAY; EMAC0PHYTXEN_out <= EMAC0PHYTXEN_outdelay after OUT_DELAY; EMAC0PHYTXER_out <= EMAC0PHYTXER_outdelay after OUT_DELAY; EMAC0SPEEDIS10100_out <= EMAC0SPEEDIS10100_outdelay after OUT_DELAY; EMAC1CLIENTANINTERRUPT_out <= EMAC1CLIENTANINTERRUPT_outdelay after OUT_DELAY; EMAC1CLIENTRXBADFRAME_out <= EMAC1CLIENTRXBADFRAME_outdelay after OUT_DELAY; EMAC1CLIENTRXDVLDMSW_out <= EMAC1CLIENTRXDVLDMSW_outdelay after OUT_DELAY; EMAC1CLIENTRXDVLD_out <= EMAC1CLIENTRXDVLD_outdelay after OUT_DELAY; EMAC1CLIENTRXD_out <= EMAC1CLIENTRXD_outdelay after OUT_DELAY; EMAC1CLIENTRXFRAMEDROP_out <= EMAC1CLIENTRXFRAMEDROP_outdelay after OUT_DELAY; EMAC1CLIENTRXGOODFRAME_out <= EMAC1CLIENTRXGOODFRAME_outdelay after OUT_DELAY; EMAC1CLIENTRXSTATSBYTEVLD_out <= EMAC1CLIENTRXSTATSBYTEVLD_outdelay after OUT_DELAY; EMAC1CLIENTRXSTATSVLD_out <= EMAC1CLIENTRXSTATSVLD_outdelay after OUT_DELAY; EMAC1CLIENTRXSTATS_out <= EMAC1CLIENTRXSTATS_outdelay after OUT_DELAY; EMAC1CLIENTTXACK_out <= EMAC1CLIENTTXACK_outdelay after OUT_DELAY; EMAC1CLIENTTXCOLLISION_out <= EMAC1CLIENTTXCOLLISION_outdelay after OUT_DELAY; EMAC1CLIENTTXRETRANSMIT_out <= EMAC1CLIENTTXRETRANSMIT_outdelay after OUT_DELAY; EMAC1CLIENTTXSTATSBYTEVLD_out <= EMAC1CLIENTTXSTATSBYTEVLD_outdelay after OUT_DELAY; EMAC1CLIENTTXSTATSVLD_out <= EMAC1CLIENTTXSTATSVLD_outdelay after OUT_DELAY; EMAC1CLIENTTXSTATS_out <= EMAC1CLIENTTXSTATS_outdelay after OUT_DELAY; EMAC1PHYENCOMMAALIGN_out <= EMAC1PHYENCOMMAALIGN_outdelay after OUT_DELAY; EMAC1PHYLOOPBACKMSB_out <= EMAC1PHYLOOPBACKMSB_outdelay after OUT_DELAY; EMAC1PHYMDOUT_out <= EMAC1PHYMDOUT_outdelay after OUT_DELAY; EMAC1PHYMDTRI_out <= EMAC1PHYMDTRI_outdelay after OUT_DELAY; EMAC1PHYMGTRXRESET_out <= EMAC1PHYMGTRXRESET_outdelay after OUT_DELAY; EMAC1PHYMGTTXRESET_out <= EMAC1PHYMGTTXRESET_outdelay after OUT_DELAY; EMAC1PHYPOWERDOWN_out <= EMAC1PHYPOWERDOWN_outdelay after OUT_DELAY; EMAC1PHYSYNCACQSTATUS_out <= EMAC1PHYSYNCACQSTATUS_outdelay after OUT_DELAY; EMAC1PHYTXCHARDISPMODE_out <= EMAC1PHYTXCHARDISPMODE_outdelay after OUT_DELAY; EMAC1PHYTXCHARDISPVAL_out <= EMAC1PHYTXCHARDISPVAL_outdelay after OUT_DELAY; EMAC1PHYTXCHARISK_out <= EMAC1PHYTXCHARISK_outdelay after OUT_DELAY; EMAC1PHYTXD_out <= EMAC1PHYTXD_outdelay after OUT_DELAY; EMAC1PHYTXEN_out <= EMAC1PHYTXEN_outdelay after OUT_DELAY; EMAC1PHYTXER_out <= EMAC1PHYTXER_outdelay after OUT_DELAY; EMAC1SPEEDIS10100_out <= EMAC1SPEEDIS10100_outdelay after OUT_DELAY; EMACDCRACK_out <= EMACDCRACK_outdelay after OUT_DELAY; EMACDCRDBUS_out <= EMACDCRDBUS_outdelay after OUT_DELAY; HOSTMIIMRDY_out <= HOSTMIIMRDY_outdelay after OUT_DELAY; HOSTRDDATA_out <= HOSTRDDATA_outdelay after OUT_DELAY; CLIENTEMAC0RXCLIENTCLKIN_ipd <= CLIENTEMAC0RXCLIENTCLKIN after CLK_DELAY; CLIENTEMAC0TXCLIENTCLKIN_ipd <= CLIENTEMAC0TXCLIENTCLKIN after CLK_DELAY; CLIENTEMAC1RXCLIENTCLKIN_ipd <= CLIENTEMAC1RXCLIENTCLKIN after CLK_DELAY; CLIENTEMAC1TXCLIENTCLKIN_ipd <= CLIENTEMAC1TXCLIENTCLKIN after CLK_DELAY; DCREMACCLK_ipd <= DCREMACCLK after CLK_DELAY; HOSTCLK_ipd <= HOSTCLK after CLK_DELAY; PHYEMAC0GTXCLK_ipd <= PHYEMAC0GTXCLK after CLK_DELAY; PHYEMAC0MCLKIN_ipd <= PHYEMAC0MCLKIN after CLK_DELAY; PHYEMAC0MIITXCLK_ipd <= PHYEMAC0MIITXCLK after EMAC0MIITXCLK_DELAY; PHYEMAC0RXCLK_ipd <= PHYEMAC0RXCLK after CLK_DELAY; PHYEMAC0TXGMIIMIICLKIN_ipd <= PHYEMAC0TXGMIIMIICLKIN after CLK_DELAY; PHYEMAC1GTXCLK_ipd <= PHYEMAC1GTXCLK after CLK_DELAY; PHYEMAC1MCLKIN_ipd <= PHYEMAC1MCLKIN after CLK_DELAY; PHYEMAC1MIITXCLK_ipd <= PHYEMAC1MIITXCLK after EMAC1MIITXCLK_DELAY; PHYEMAC1RXCLK_ipd <= PHYEMAC1RXCLK after CLK_DELAY; PHYEMAC1TXGMIIMIICLKIN_ipd <= PHYEMAC1TXGMIIMIICLKIN after CLK_DELAY; CLIENTEMAC0DCMLOCKED_ipd <= CLIENTEMAC0DCMLOCKED after CLK_DELAY; CLIENTEMAC0PAUSEREQ_ipd <= CLIENTEMAC0PAUSEREQ after CLK_DELAY; CLIENTEMAC0PAUSEVAL_ipd <= CLIENTEMAC0PAUSEVAL after CLK_DELAY; CLIENTEMAC0TXDVLDMSW_ipd <= CLIENTEMAC0TXDVLDMSW after CLK_DELAY; CLIENTEMAC0TXDVLD_ipd <= CLIENTEMAC0TXDVLD after CLK_DELAY; CLIENTEMAC0TXD_ipd <= CLIENTEMAC0TXD after CLK_DELAY; CLIENTEMAC0TXFIRSTBYTE_ipd <= CLIENTEMAC0TXFIRSTBYTE after CLK_DELAY; CLIENTEMAC0TXIFGDELAY_ipd <= CLIENTEMAC0TXIFGDELAY after CLK_DELAY; CLIENTEMAC0TXUNDERRUN_ipd <= CLIENTEMAC0TXUNDERRUN after CLK_DELAY; CLIENTEMAC1DCMLOCKED_ipd <= CLIENTEMAC1DCMLOCKED after CLK_DELAY; CLIENTEMAC1PAUSEREQ_ipd <= CLIENTEMAC1PAUSEREQ after CLK_DELAY; CLIENTEMAC1PAUSEVAL_ipd <= CLIENTEMAC1PAUSEVAL after CLK_DELAY; CLIENTEMAC1TXDVLDMSW_ipd <= CLIENTEMAC1TXDVLDMSW after CLK_DELAY; CLIENTEMAC1TXDVLD_ipd <= CLIENTEMAC1TXDVLD after CLK_DELAY; CLIENTEMAC1TXD_ipd <= CLIENTEMAC1TXD after CLK_DELAY; CLIENTEMAC1TXFIRSTBYTE_ipd <= CLIENTEMAC1TXFIRSTBYTE after CLK_DELAY; CLIENTEMAC1TXIFGDELAY_ipd <= CLIENTEMAC1TXIFGDELAY after CLK_DELAY; CLIENTEMAC1TXUNDERRUN_ipd <= CLIENTEMAC1TXUNDERRUN after CLK_DELAY; DCREMACABUS_ipd <= DCREMACABUS after CLK_DELAY; DCREMACDBUS_ipd <= DCREMACDBUS after CLK_DELAY; DCREMACENABLE_ipd <= DCREMACENABLE after CLK_DELAY; DCREMACREAD_ipd <= DCREMACREAD after CLK_DELAY; DCREMACWRITE_ipd <= DCREMACWRITE after CLK_DELAY; HOSTADDR_ipd <= HOSTADDR after CLK_DELAY; HOSTEMAC1SEL_ipd <= HOSTEMAC1SEL after CLK_DELAY; HOSTMIIMSEL_ipd <= HOSTMIIMSEL after CLK_DELAY; HOSTOPCODE_ipd <= HOSTOPCODE after CLK_DELAY; HOSTREQ_ipd <= HOSTREQ after CLK_DELAY; HOSTWRDATA_ipd <= HOSTWRDATA after CLK_DELAY; PHYEMAC0COL_ipd <= PHYEMAC0COL after CLK_DELAY; PHYEMAC0CRS_ipd <= PHYEMAC0CRS after CLK_DELAY; PHYEMAC0MDIN_ipd <= PHYEMAC0MDIN after CLK_DELAY; PHYEMAC0PHYAD_ipd <= PHYEMAC0PHYAD after CLK_DELAY; PHYEMAC0RXBUFERR_ipd <= PHYEMAC0RXBUFERR after CLK_DELAY; PHYEMAC0RXBUFSTATUS_ipd <= PHYEMAC0RXBUFSTATUS after CLK_DELAY; PHYEMAC0RXCHARISCOMMA_ipd <= PHYEMAC0RXCHARISCOMMA after CLK_DELAY; PHYEMAC0RXCHARISK_ipd <= PHYEMAC0RXCHARISK after CLK_DELAY; PHYEMAC0RXCHECKINGCRC_ipd <= PHYEMAC0RXCHECKINGCRC after CLK_DELAY; PHYEMAC0RXCLKCORCNT_ipd <= PHYEMAC0RXCLKCORCNT after CLK_DELAY; PHYEMAC0RXCOMMADET_ipd <= PHYEMAC0RXCOMMADET after CLK_DELAY; PHYEMAC0RXDISPERR_ipd <= PHYEMAC0RXDISPERR after CLK_DELAY; PHYEMAC0RXDV_ipd <= PHYEMAC0RXDV after CLK_DELAY; PHYEMAC0RXD_ipd <= PHYEMAC0RXD after CLK_DELAY; PHYEMAC0RXER_ipd <= PHYEMAC0RXER after CLK_DELAY; PHYEMAC0RXLOSSOFSYNC_ipd <= PHYEMAC0RXLOSSOFSYNC after CLK_DELAY; PHYEMAC0RXNOTINTABLE_ipd <= PHYEMAC0RXNOTINTABLE after CLK_DELAY; PHYEMAC0RXRUNDISP_ipd <= PHYEMAC0RXRUNDISP after CLK_DELAY; PHYEMAC0SIGNALDET_ipd <= PHYEMAC0SIGNALDET after CLK_DELAY; PHYEMAC0TXBUFERR_ipd <= PHYEMAC0TXBUFERR after CLK_DELAY; PHYEMAC1COL_ipd <= PHYEMAC1COL after CLK_DELAY; PHYEMAC1CRS_ipd <= PHYEMAC1CRS after CLK_DELAY; PHYEMAC1MDIN_ipd <= PHYEMAC1MDIN after CLK_DELAY; PHYEMAC1PHYAD_ipd <= PHYEMAC1PHYAD after CLK_DELAY; PHYEMAC1RXBUFERR_ipd <= PHYEMAC1RXBUFERR after CLK_DELAY; PHYEMAC1RXBUFSTATUS_ipd <= PHYEMAC1RXBUFSTATUS after CLK_DELAY; PHYEMAC1RXCHARISCOMMA_ipd <= PHYEMAC1RXCHARISCOMMA after CLK_DELAY; PHYEMAC1RXCHARISK_ipd <= PHYEMAC1RXCHARISK after CLK_DELAY; PHYEMAC1RXCHECKINGCRC_ipd <= PHYEMAC1RXCHECKINGCRC after CLK_DELAY; PHYEMAC1RXCLKCORCNT_ipd <= PHYEMAC1RXCLKCORCNT after CLK_DELAY; PHYEMAC1RXCOMMADET_ipd <= PHYEMAC1RXCOMMADET after CLK_DELAY; PHYEMAC1RXDISPERR_ipd <= PHYEMAC1RXDISPERR after CLK_DELAY; PHYEMAC1RXDV_ipd <= PHYEMAC1RXDV after CLK_DELAY; PHYEMAC1RXD_ipd <= PHYEMAC1RXD after CLK_DELAY; PHYEMAC1RXER_ipd <= PHYEMAC1RXER after CLK_DELAY; PHYEMAC1RXLOSSOFSYNC_ipd <= PHYEMAC1RXLOSSOFSYNC after CLK_DELAY; PHYEMAC1RXNOTINTABLE_ipd <= PHYEMAC1RXNOTINTABLE after CLK_DELAY; PHYEMAC1RXRUNDISP_ipd <= PHYEMAC1RXRUNDISP after CLK_DELAY; PHYEMAC1SIGNALDET_ipd <= PHYEMAC1SIGNALDET after CLK_DELAY; PHYEMAC1TXBUFERR_ipd <= PHYEMAC1TXBUFERR after CLK_DELAY; RESET_ipd <= RESET after CLK_DELAY; CLIENTEMAC0RXCLIENTCLKIN_indelay <= CLIENTEMAC0RXCLIENTCLKIN_ipd after CLK_DELAY; CLIENTEMAC0TXCLIENTCLKIN_indelay <= CLIENTEMAC0TXCLIENTCLKIN_ipd after CLK_DELAY; CLIENTEMAC1RXCLIENTCLKIN_indelay <= CLIENTEMAC1RXCLIENTCLKIN_ipd after CLK_DELAY; CLIENTEMAC1TXCLIENTCLKIN_indelay <= CLIENTEMAC1TXCLIENTCLKIN_ipd after CLK_DELAY; DCREMACCLK_indelay <= DCREMACCLK_ipd after CLK_DELAY; HOSTCLK_indelay <= HOSTCLK_ipd after CLK_DELAY; PHYEMAC0GTXCLK_indelay <= PHYEMAC0GTXCLK_ipd after CLK_DELAY; PHYEMAC0MCLKIN_indelay <= PHYEMAC0MCLKIN_ipd after CLK_DELAY; PHYEMAC0MIITXCLK_indelay <= PHYEMAC0MIITXCLK_ipd after EMAC0MIITXCLK_DELAY; PHYEMAC0RXCLK_indelay <= PHYEMAC0RXCLK_ipd after CLK_DELAY; PHYEMAC0TXGMIIMIICLKIN_indelay <= PHYEMAC0TXGMIIMIICLKIN_ipd after CLK_DELAY; PHYEMAC1GTXCLK_indelay <= PHYEMAC1GTXCLK_ipd after CLK_DELAY; PHYEMAC1MCLKIN_indelay <= PHYEMAC1MCLKIN_ipd after CLK_DELAY; PHYEMAC1MIITXCLK_indelay <= PHYEMAC1MIITXCLK_ipd after EMAC1MIITXCLK_DELAY; PHYEMAC1RXCLK_indelay <= PHYEMAC1RXCLK_ipd after CLK_DELAY; PHYEMAC1TXGMIIMIICLKIN_indelay <= PHYEMAC1TXGMIIMIICLKIN_ipd after CLK_DELAY; CLIENTEMAC0DCMLOCKED_indelay <= CLIENTEMAC0DCMLOCKED_ipd after IN_DELAY; CLIENTEMAC0PAUSEREQ_indelay <= CLIENTEMAC0PAUSEREQ_ipd after IN_DELAY; CLIENTEMAC0PAUSEVAL_indelay <= CLIENTEMAC0PAUSEVAL_ipd after IN_DELAY; CLIENTEMAC0TXDVLDMSW_indelay <= CLIENTEMAC0TXDVLDMSW_ipd after IN_DELAY; CLIENTEMAC0TXDVLD_indelay <= CLIENTEMAC0TXDVLD_ipd after IN_DELAY; CLIENTEMAC0TXD_indelay <= CLIENTEMAC0TXD_ipd after IN_DELAY; CLIENTEMAC0TXFIRSTBYTE_indelay <= CLIENTEMAC0TXFIRSTBYTE_ipd after IN_DELAY; CLIENTEMAC0TXIFGDELAY_indelay <= CLIENTEMAC0TXIFGDELAY_ipd after IN_DELAY; CLIENTEMAC0TXUNDERRUN_indelay <= CLIENTEMAC0TXUNDERRUN_ipd after IN_DELAY; CLIENTEMAC1DCMLOCKED_indelay <= CLIENTEMAC1DCMLOCKED_ipd after IN_DELAY; CLIENTEMAC1PAUSEREQ_indelay <= CLIENTEMAC1PAUSEREQ_ipd after IN_DELAY; CLIENTEMAC1PAUSEVAL_indelay <= CLIENTEMAC1PAUSEVAL_ipd after IN_DELAY; CLIENTEMAC1TXDVLDMSW_indelay <= CLIENTEMAC1TXDVLDMSW_ipd after IN_DELAY; CLIENTEMAC1TXDVLD_indelay <= CLIENTEMAC1TXDVLD_ipd after IN_DELAY; CLIENTEMAC1TXD_indelay <= CLIENTEMAC1TXD_ipd after IN_DELAY; CLIENTEMAC1TXFIRSTBYTE_indelay <= CLIENTEMAC1TXFIRSTBYTE_ipd after IN_DELAY; CLIENTEMAC1TXIFGDELAY_indelay <= CLIENTEMAC1TXIFGDELAY_ipd after IN_DELAY; CLIENTEMAC1TXUNDERRUN_indelay <= CLIENTEMAC1TXUNDERRUN_ipd after IN_DELAY; DCREMACABUS_indelay <= DCREMACABUS_ipd after IN_DELAY; DCREMACDBUS_indelay <= DCREMACDBUS_ipd after IN_DELAY; DCREMACENABLE_indelay <= DCREMACENABLE_ipd after IN_DELAY; DCREMACREAD_indelay <= DCREMACREAD_ipd after IN_DELAY; DCREMACWRITE_indelay <= DCREMACWRITE_ipd after IN_DELAY; HOSTADDR_indelay <= HOSTADDR_ipd after IN_DELAY; HOSTEMAC1SEL_indelay <= HOSTEMAC1SEL_ipd after IN_DELAY; HOSTMIIMSEL_indelay <= HOSTMIIMSEL_ipd after IN_DELAY; HOSTOPCODE_indelay <= HOSTOPCODE_ipd after IN_DELAY; HOSTREQ_indelay <= HOSTREQ_ipd after IN_DELAY; HOSTWRDATA_indelay <= HOSTWRDATA_ipd after IN_DELAY; PHYEMAC0COL_indelay <= PHYEMAC0COL_ipd after IN_DELAY; PHYEMAC0CRS_indelay <= PHYEMAC0CRS_ipd after IN_DELAY; PHYEMAC0MDIN_indelay <= PHYEMAC0MDIN_ipd after IN_DELAY; PHYEMAC0PHYAD_indelay <= PHYEMAC0PHYAD_ipd after IN_DELAY; PHYEMAC0RXBUFERR_indelay <= PHYEMAC0RXBUFERR_ipd after IN_DELAY; PHYEMAC0RXBUFSTATUS_indelay <= PHYEMAC0RXBUFSTATUS_ipd after IN_DELAY; PHYEMAC0RXCHARISCOMMA_indelay <= PHYEMAC0RXCHARISCOMMA_ipd after IN_DELAY; PHYEMAC0RXCHARISK_indelay <= PHYEMAC0RXCHARISK_ipd after IN_DELAY; PHYEMAC0RXCHECKINGCRC_indelay <= PHYEMAC0RXCHECKINGCRC_ipd after IN_DELAY; PHYEMAC0RXCLKCORCNT_indelay <= PHYEMAC0RXCLKCORCNT_ipd after IN_DELAY; PHYEMAC0RXCOMMADET_indelay <= PHYEMAC0RXCOMMADET_ipd after IN_DELAY; PHYEMAC0RXDISPERR_indelay <= PHYEMAC0RXDISPERR_ipd after IN_DELAY; PHYEMAC0RXDV_indelay <= PHYEMAC0RXDV_ipd after IN_DELAY; PHYEMAC0RXD_indelay <= PHYEMAC0RXD_ipd after IN_DELAY; PHYEMAC0RXER_indelay <= PHYEMAC0RXER_ipd after IN_DELAY; PHYEMAC0RXLOSSOFSYNC_indelay <= PHYEMAC0RXLOSSOFSYNC_ipd after IN_DELAY; PHYEMAC0RXNOTINTABLE_indelay <= PHYEMAC0RXNOTINTABLE_ipd after IN_DELAY; PHYEMAC0RXRUNDISP_indelay <= PHYEMAC0RXRUNDISP_ipd after IN_DELAY; PHYEMAC0SIGNALDET_indelay <= PHYEMAC0SIGNALDET_ipd after IN_DELAY; PHYEMAC0TXBUFERR_indelay <= PHYEMAC0TXBUFERR_ipd after IN_DELAY; PHYEMAC1COL_indelay <= PHYEMAC1COL_ipd after IN_DELAY; PHYEMAC1CRS_indelay <= PHYEMAC1CRS_ipd after IN_DELAY; PHYEMAC1MDIN_indelay <= PHYEMAC1MDIN_ipd after IN_DELAY; PHYEMAC1PHYAD_indelay <= PHYEMAC1PHYAD_ipd after IN_DELAY; PHYEMAC1RXBUFERR_indelay <= PHYEMAC1RXBUFERR_ipd after IN_DELAY; PHYEMAC1RXBUFSTATUS_indelay <= PHYEMAC1RXBUFSTATUS_ipd after IN_DELAY; PHYEMAC1RXCHARISCOMMA_indelay <= PHYEMAC1RXCHARISCOMMA_ipd after IN_DELAY; PHYEMAC1RXCHARISK_indelay <= PHYEMAC1RXCHARISK_ipd after IN_DELAY; PHYEMAC1RXCHECKINGCRC_indelay <= PHYEMAC1RXCHECKINGCRC_ipd after IN_DELAY; PHYEMAC1RXCLKCORCNT_indelay <= PHYEMAC1RXCLKCORCNT_ipd after IN_DELAY; PHYEMAC1RXCOMMADET_indelay <= PHYEMAC1RXCOMMADET_ipd after IN_DELAY; PHYEMAC1RXDISPERR_indelay <= PHYEMAC1RXDISPERR_ipd after IN_DELAY; PHYEMAC1RXDV_indelay <= PHYEMAC1RXDV_ipd after IN_DELAY; PHYEMAC1RXD_indelay <= PHYEMAC1RXD_ipd after IN_DELAY; PHYEMAC1RXER_indelay <= PHYEMAC1RXER_ipd after IN_DELAY; PHYEMAC1RXLOSSOFSYNC_indelay <= PHYEMAC1RXLOSSOFSYNC_ipd after IN_DELAY; PHYEMAC1RXNOTINTABLE_indelay <= PHYEMAC1RXNOTINTABLE_ipd after IN_DELAY; PHYEMAC1RXRUNDISP_indelay <= PHYEMAC1RXRUNDISP_ipd after IN_DELAY; PHYEMAC1SIGNALDET_indelay <= PHYEMAC1SIGNALDET_ipd after IN_DELAY; PHYEMAC1TXBUFERR_indelay <= PHYEMAC1TXBUFERR_ipd after IN_DELAY; RESET_indelay <= RESET_ipd after IN_DELAY; temac_swift_bw_1 : TEMAC_SWIFT port map ( EMAC0_1000BASEX_ENABLE => EMAC0_1000BASEX_ENABLE_BINARY, EMAC0_ADDRFILTER_ENABLE => EMAC0_ADDRFILTER_ENABLE_BINARY, EMAC0_BYTEPHY => EMAC0_BYTEPHY_BINARY, EMAC0_CONFIGVEC_79 => EMAC0_CONFIGVEC_79_BINARY, EMAC0_DCRBASEADDR => EMAC0_DCRBASEADDR_BINARY, EMAC0_GTLOOPBACK => EMAC0_GTLOOPBACK_BINARY, EMAC0_HOST_ENABLE => EMAC0_HOST_ENABLE_BINARY, EMAC0_LINKTIMERVAL => EMAC0_LINKTIMERVAL_BINARY, EMAC0_LTCHECK_DISABLE => EMAC0_LTCHECK_DISABLE_BINARY, EMAC0_MDIO_ENABLE => EMAC0_MDIO_ENABLE_BINARY, EMAC0_PAUSEADDR => EMAC0_PAUSEADDR_BINARY, EMAC0_PHYINITAUTONEG_ENABLE => EMAC0_PHYINITAUTONEG_ENABLE_BINARY, EMAC0_PHYISOLATE => EMAC0_PHYISOLATE_BINARY, EMAC0_PHYLOOPBACKMSB => EMAC0_PHYLOOPBACKMSB_BINARY, EMAC0_PHYPOWERDOWN => EMAC0_PHYPOWERDOWN_BINARY, EMAC0_PHYRESET => EMAC0_PHYRESET_BINARY, EMAC0_RGMII_ENABLE => EMAC0_RGMII_ENABLE_BINARY, EMAC0_RX16BITCLIENT_ENABLE => EMAC0_RX16BITCLIENT_ENABLE_BINARY, EMAC0_RXFLOWCTRL_ENABLE => EMAC0_RXFLOWCTRL_ENABLE_BINARY, EMAC0_RXHALFDUPLEX => EMAC0_RXHALFDUPLEX_BINARY, EMAC0_RXINBANDFCS_ENABLE => EMAC0_RXINBANDFCS_ENABLE_BINARY, EMAC0_RXJUMBOFRAME_ENABLE => EMAC0_RXJUMBOFRAME_ENABLE_BINARY, EMAC0_RXRESET => EMAC0_RXRESET_BINARY, EMAC0_RXVLAN_ENABLE => EMAC0_RXVLAN_ENABLE_BINARY, EMAC0_RX_ENABLE => EMAC0_RX_ENABLE_BINARY, EMAC0_SGMII_ENABLE => EMAC0_SGMII_ENABLE_BINARY, EMAC0_SPEED_LSB => EMAC0_SPEED_LSB_BINARY, EMAC0_SPEED_MSB => EMAC0_SPEED_MSB_BINARY, EMAC0_TX16BITCLIENT_ENABLE => EMAC0_TX16BITCLIENT_ENABLE_BINARY, EMAC0_TXFLOWCTRL_ENABLE => EMAC0_TXFLOWCTRL_ENABLE_BINARY, EMAC0_TXHALFDUPLEX => EMAC0_TXHALFDUPLEX_BINARY, EMAC0_TXIFGADJUST_ENABLE => EMAC0_TXIFGADJUST_ENABLE_BINARY, EMAC0_TXINBANDFCS_ENABLE => EMAC0_TXINBANDFCS_ENABLE_BINARY, EMAC0_TXJUMBOFRAME_ENABLE => EMAC0_TXJUMBOFRAME_ENABLE_BINARY, EMAC0_TXRESET => EMAC0_TXRESET_BINARY, EMAC0_TXVLAN_ENABLE => EMAC0_TXVLAN_ENABLE_BINARY, EMAC0_TX_ENABLE => EMAC0_TX_ENABLE_BINARY, EMAC0_UNICASTADDR => EMAC0_UNICASTADDR_BINARY, EMAC0_UNIDIRECTION_ENABLE => EMAC0_UNIDIRECTION_ENABLE_BINARY, EMAC0_USECLKEN => EMAC0_USECLKEN_BINARY, EMAC1_1000BASEX_ENABLE => EMAC1_1000BASEX_ENABLE_BINARY, EMAC1_ADDRFILTER_ENABLE => EMAC1_ADDRFILTER_ENABLE_BINARY, EMAC1_BYTEPHY => EMAC1_BYTEPHY_BINARY, EMAC1_CONFIGVEC_79 => EMAC1_CONFIGVEC_79_BINARY, EMAC1_DCRBASEADDR => EMAC1_DCRBASEADDR_BINARY, EMAC1_GTLOOPBACK => EMAC1_GTLOOPBACK_BINARY, EMAC1_HOST_ENABLE => EMAC1_HOST_ENABLE_BINARY, EMAC1_LINKTIMERVAL => EMAC1_LINKTIMERVAL_BINARY, EMAC1_LTCHECK_DISABLE => EMAC1_LTCHECK_DISABLE_BINARY, EMAC1_MDIO_ENABLE => EMAC1_MDIO_ENABLE_BINARY, EMAC1_PAUSEADDR => EMAC1_PAUSEADDR_BINARY, EMAC1_PHYINITAUTONEG_ENABLE => EMAC1_PHYINITAUTONEG_ENABLE_BINARY, EMAC1_PHYISOLATE => EMAC1_PHYISOLATE_BINARY, EMAC1_PHYLOOPBACKMSB => EMAC1_PHYLOOPBACKMSB_BINARY, EMAC1_PHYPOWERDOWN => EMAC1_PHYPOWERDOWN_BINARY, EMAC1_PHYRESET => EMAC1_PHYRESET_BINARY, EMAC1_RGMII_ENABLE => EMAC1_RGMII_ENABLE_BINARY, EMAC1_RX16BITCLIENT_ENABLE => EMAC1_RX16BITCLIENT_ENABLE_BINARY, EMAC1_RXFLOWCTRL_ENABLE => EMAC1_RXFLOWCTRL_ENABLE_BINARY, EMAC1_RXHALFDUPLEX => EMAC1_RXHALFDUPLEX_BINARY, EMAC1_RXINBANDFCS_ENABLE => EMAC1_RXINBANDFCS_ENABLE_BINARY, EMAC1_RXJUMBOFRAME_ENABLE => EMAC1_RXJUMBOFRAME_ENABLE_BINARY, EMAC1_RXRESET => EMAC1_RXRESET_BINARY, EMAC1_RXVLAN_ENABLE => EMAC1_RXVLAN_ENABLE_BINARY, EMAC1_RX_ENABLE => EMAC1_RX_ENABLE_BINARY, EMAC1_SGMII_ENABLE => EMAC1_SGMII_ENABLE_BINARY, EMAC1_SPEED_LSB => EMAC1_SPEED_LSB_BINARY, EMAC1_SPEED_MSB => EMAC1_SPEED_MSB_BINARY, EMAC1_TX16BITCLIENT_ENABLE => EMAC1_TX16BITCLIENT_ENABLE_BINARY, EMAC1_TXFLOWCTRL_ENABLE => EMAC1_TXFLOWCTRL_ENABLE_BINARY, EMAC1_TXHALFDUPLEX => EMAC1_TXHALFDUPLEX_BINARY, EMAC1_TXIFGADJUST_ENABLE => EMAC1_TXIFGADJUST_ENABLE_BINARY, EMAC1_TXINBANDFCS_ENABLE => EMAC1_TXINBANDFCS_ENABLE_BINARY, EMAC1_TXJUMBOFRAME_ENABLE => EMAC1_TXJUMBOFRAME_ENABLE_BINARY, EMAC1_TXRESET => EMAC1_TXRESET_BINARY, EMAC1_TXVLAN_ENABLE => EMAC1_TXVLAN_ENABLE_BINARY, EMAC1_TX_ENABLE => EMAC1_TX_ENABLE_BINARY, EMAC1_UNICASTADDR => EMAC1_UNICASTADDR_BINARY, EMAC1_UNIDIRECTION_ENABLE => EMAC1_UNIDIRECTION_ENABLE_BINARY, EMAC1_USECLKEN => EMAC1_USECLKEN_BINARY, DCRHOSTDONEIR => DCRHOSTDONEIR_outdelay, EMAC0CLIENTANINTERRUPT => EMAC0CLIENTANINTERRUPT_outdelay, EMAC0CLIENTRXBADFRAME => EMAC0CLIENTRXBADFRAME_outdelay, EMAC0CLIENTRXCLIENTCLKOUT => EMAC0CLIENTRXCLIENTCLKOUT_outdelay, EMAC0CLIENTRXD => EMAC0CLIENTRXD_outdelay, EMAC0CLIENTRXDVLD => EMAC0CLIENTRXDVLD_outdelay, EMAC0CLIENTRXDVLDMSW => EMAC0CLIENTRXDVLDMSW_outdelay, EMAC0CLIENTRXFRAMEDROP => EMAC0CLIENTRXFRAMEDROP_outdelay, EMAC0CLIENTRXGOODFRAME => EMAC0CLIENTRXGOODFRAME_outdelay, EMAC0CLIENTRXSTATS => EMAC0CLIENTRXSTATS_outdelay, EMAC0CLIENTRXSTATSBYTEVLD => EMAC0CLIENTRXSTATSBYTEVLD_outdelay, EMAC0CLIENTRXSTATSVLD => EMAC0CLIENTRXSTATSVLD_outdelay, EMAC0CLIENTTXACK => EMAC0CLIENTTXACK_outdelay, EMAC0CLIENTTXCLIENTCLKOUT => EMAC0CLIENTTXCLIENTCLKOUT_outdelay, EMAC0CLIENTTXCOLLISION => EMAC0CLIENTTXCOLLISION_outdelay, EMAC0CLIENTTXRETRANSMIT => EMAC0CLIENTTXRETRANSMIT_outdelay, EMAC0CLIENTTXSTATS => EMAC0CLIENTTXSTATS_outdelay, EMAC0CLIENTTXSTATSBYTEVLD => EMAC0CLIENTTXSTATSBYTEVLD_outdelay, EMAC0CLIENTTXSTATSVLD => EMAC0CLIENTTXSTATSVLD_outdelay, EMAC0PHYENCOMMAALIGN => EMAC0PHYENCOMMAALIGN_outdelay, EMAC0PHYLOOPBACKMSB => EMAC0PHYLOOPBACKMSB_outdelay, EMAC0PHYMCLKOUT => EMAC0PHYMCLKOUT_outdelay, EMAC0PHYMDOUT => EMAC0PHYMDOUT_outdelay, EMAC0PHYMDTRI => EMAC0PHYMDTRI_outdelay, EMAC0PHYMGTRXRESET => EMAC0PHYMGTRXRESET_outdelay, EMAC0PHYMGTTXRESET => EMAC0PHYMGTTXRESET_outdelay, EMAC0PHYPOWERDOWN => EMAC0PHYPOWERDOWN_outdelay, EMAC0PHYSYNCACQSTATUS => EMAC0PHYSYNCACQSTATUS_outdelay, EMAC0PHYTXCHARDISPMODE => EMAC0PHYTXCHARDISPMODE_outdelay, EMAC0PHYTXCHARDISPVAL => EMAC0PHYTXCHARDISPVAL_outdelay, EMAC0PHYTXCHARISK => EMAC0PHYTXCHARISK_outdelay, EMAC0PHYTXCLK => EMAC0PHYTXCLK_outdelay, EMAC0PHYTXD => EMAC0PHYTXD_outdelay, EMAC0PHYTXEN => EMAC0PHYTXEN_outdelay, EMAC0PHYTXER => EMAC0PHYTXER_outdelay, EMAC0PHYTXGMIIMIICLKOUT => EMAC0PHYTXGMIIMIICLKOUT_outdelay, EMAC0SPEEDIS10100 => EMAC0SPEEDIS10100_outdelay, EMAC1CLIENTANINTERRUPT => EMAC1CLIENTANINTERRUPT_outdelay, EMAC1CLIENTRXBADFRAME => EMAC1CLIENTRXBADFRAME_outdelay, EMAC1CLIENTRXCLIENTCLKOUT => EMAC1CLIENTRXCLIENTCLKOUT_outdelay, EMAC1CLIENTRXD => EMAC1CLIENTRXD_outdelay, EMAC1CLIENTRXDVLD => EMAC1CLIENTRXDVLD_outdelay, EMAC1CLIENTRXDVLDMSW => EMAC1CLIENTRXDVLDMSW_outdelay, EMAC1CLIENTRXFRAMEDROP => EMAC1CLIENTRXFRAMEDROP_outdelay, EMAC1CLIENTRXGOODFRAME => EMAC1CLIENTRXGOODFRAME_outdelay, EMAC1CLIENTRXSTATS => EMAC1CLIENTRXSTATS_outdelay, EMAC1CLIENTRXSTATSBYTEVLD => EMAC1CLIENTRXSTATSBYTEVLD_outdelay, EMAC1CLIENTRXSTATSVLD => EMAC1CLIENTRXSTATSVLD_outdelay, EMAC1CLIENTTXACK => EMAC1CLIENTTXACK_outdelay, EMAC1CLIENTTXCLIENTCLKOUT => EMAC1CLIENTTXCLIENTCLKOUT_outdelay, EMAC1CLIENTTXCOLLISION => EMAC1CLIENTTXCOLLISION_outdelay, EMAC1CLIENTTXRETRANSMIT => EMAC1CLIENTTXRETRANSMIT_outdelay, EMAC1CLIENTTXSTATS => EMAC1CLIENTTXSTATS_outdelay, EMAC1CLIENTTXSTATSBYTEVLD => EMAC1CLIENTTXSTATSBYTEVLD_outdelay, EMAC1CLIENTTXSTATSVLD => EMAC1CLIENTTXSTATSVLD_outdelay, EMAC1PHYENCOMMAALIGN => EMAC1PHYENCOMMAALIGN_outdelay, EMAC1PHYLOOPBACKMSB => EMAC1PHYLOOPBACKMSB_outdelay, EMAC1PHYMCLKOUT => EMAC1PHYMCLKOUT_outdelay, EMAC1PHYMDOUT => EMAC1PHYMDOUT_outdelay, EMAC1PHYMDTRI => EMAC1PHYMDTRI_outdelay, EMAC1PHYMGTRXRESET => EMAC1PHYMGTRXRESET_outdelay, EMAC1PHYMGTTXRESET => EMAC1PHYMGTTXRESET_outdelay, EMAC1PHYPOWERDOWN => EMAC1PHYPOWERDOWN_outdelay, EMAC1PHYSYNCACQSTATUS => EMAC1PHYSYNCACQSTATUS_outdelay, EMAC1PHYTXCHARDISPMODE => EMAC1PHYTXCHARDISPMODE_outdelay, EMAC1PHYTXCHARDISPVAL => EMAC1PHYTXCHARDISPVAL_outdelay, EMAC1PHYTXCHARISK => EMAC1PHYTXCHARISK_outdelay, EMAC1PHYTXCLK => EMAC1PHYTXCLK_outdelay, EMAC1PHYTXD => EMAC1PHYTXD_outdelay, EMAC1PHYTXEN => EMAC1PHYTXEN_outdelay, EMAC1PHYTXER => EMAC1PHYTXER_outdelay, EMAC1PHYTXGMIIMIICLKOUT => EMAC1PHYTXGMIIMIICLKOUT_outdelay, EMAC1SPEEDIS10100 => EMAC1SPEEDIS10100_outdelay, EMACDCRACK => EMACDCRACK_outdelay, EMACDCRDBUS => EMACDCRDBUS_outdelay, HOSTMIIMRDY => HOSTMIIMRDY_outdelay, HOSTRDDATA => HOSTRDDATA_outdelay, CLIENTEMAC0DCMLOCKED => CLIENTEMAC0DCMLOCKED_indelay, CLIENTEMAC0PAUSEREQ => CLIENTEMAC0PAUSEREQ_indelay, CLIENTEMAC0PAUSEVAL => CLIENTEMAC0PAUSEVAL_indelay, CLIENTEMAC0RXCLIENTCLKIN => CLIENTEMAC0RXCLIENTCLKIN_indelay, CLIENTEMAC0TXCLIENTCLKIN => CLIENTEMAC0TXCLIENTCLKIN_indelay, CLIENTEMAC0TXD => CLIENTEMAC0TXD_indelay, CLIENTEMAC0TXDVLD => CLIENTEMAC0TXDVLD_indelay, CLIENTEMAC0TXDVLDMSW => CLIENTEMAC0TXDVLDMSW_indelay, CLIENTEMAC0TXFIRSTBYTE => CLIENTEMAC0TXFIRSTBYTE_indelay, CLIENTEMAC0TXIFGDELAY => CLIENTEMAC0TXIFGDELAY_indelay, CLIENTEMAC0TXUNDERRUN => CLIENTEMAC0TXUNDERRUN_indelay, CLIENTEMAC1DCMLOCKED => CLIENTEMAC1DCMLOCKED_indelay, CLIENTEMAC1PAUSEREQ => CLIENTEMAC1PAUSEREQ_indelay, CLIENTEMAC1PAUSEVAL => CLIENTEMAC1PAUSEVAL_indelay, CLIENTEMAC1RXCLIENTCLKIN => CLIENTEMAC1RXCLIENTCLKIN_indelay, CLIENTEMAC1TXCLIENTCLKIN => CLIENTEMAC1TXCLIENTCLKIN_indelay, CLIENTEMAC1TXD => CLIENTEMAC1TXD_indelay, CLIENTEMAC1TXDVLD => CLIENTEMAC1TXDVLD_indelay, CLIENTEMAC1TXDVLDMSW => CLIENTEMAC1TXDVLDMSW_indelay, CLIENTEMAC1TXFIRSTBYTE => CLIENTEMAC1TXFIRSTBYTE_indelay, CLIENTEMAC1TXIFGDELAY => CLIENTEMAC1TXIFGDELAY_indelay, CLIENTEMAC1TXUNDERRUN => CLIENTEMAC1TXUNDERRUN_indelay, DCREMACABUS => DCREMACABUS_indelay, DCREMACCLK => DCREMACCLK_indelay, DCREMACDBUS => DCREMACDBUS_indelay, DCREMACENABLE => DCREMACENABLE_indelay, DCREMACREAD => DCREMACREAD_indelay, DCREMACWRITE => DCREMACWRITE_indelay, HOSTADDR => HOSTADDR_indelay, HOSTCLK => HOSTCLK_indelay, HOSTEMAC1SEL => HOSTEMAC1SEL_indelay, HOSTMIIMSEL => HOSTMIIMSEL_indelay, HOSTOPCODE => HOSTOPCODE_indelay, HOSTREQ => HOSTREQ_indelay, HOSTWRDATA => HOSTWRDATA_indelay, PHYEMAC0COL => PHYEMAC0COL_indelay, PHYEMAC0CRS => PHYEMAC0CRS_indelay, PHYEMAC0GTXCLK => PHYEMAC0GTXCLK_indelay, PHYEMAC0MCLKIN => PHYEMAC0MCLKIN_indelay, PHYEMAC0MDIN => PHYEMAC0MDIN_indelay, PHYEMAC0MIITXCLK => PHYEMAC0MIITXCLK_indelay, PHYEMAC0PHYAD => PHYEMAC0PHYAD_indelay, PHYEMAC0RXBUFERR => PHYEMAC0RXBUFERR_indelay, PHYEMAC0RXBUFSTATUS => PHYEMAC0RXBUFSTATUS_indelay, PHYEMAC0RXCHARISCOMMA => PHYEMAC0RXCHARISCOMMA_indelay, PHYEMAC0RXCHARISK => PHYEMAC0RXCHARISK_indelay, PHYEMAC0RXCHECKINGCRC => PHYEMAC0RXCHECKINGCRC_indelay, PHYEMAC0RXCLK => PHYEMAC0RXCLK_indelay, PHYEMAC0RXCLKCORCNT => PHYEMAC0RXCLKCORCNT_indelay, PHYEMAC0RXCOMMADET => PHYEMAC0RXCOMMADET_indelay, PHYEMAC0RXD => PHYEMAC0RXD_indelay, PHYEMAC0RXDISPERR => PHYEMAC0RXDISPERR_indelay, PHYEMAC0RXDV => PHYEMAC0RXDV_indelay, PHYEMAC0RXER => PHYEMAC0RXER_indelay, PHYEMAC0RXLOSSOFSYNC => PHYEMAC0RXLOSSOFSYNC_indelay, PHYEMAC0RXNOTINTABLE => PHYEMAC0RXNOTINTABLE_indelay, PHYEMAC0RXRUNDISP => PHYEMAC0RXRUNDISP_indelay, PHYEMAC0SIGNALDET => PHYEMAC0SIGNALDET_indelay, PHYEMAC0TXBUFERR => PHYEMAC0TXBUFERR_indelay, PHYEMAC0TXGMIIMIICLKIN => PHYEMAC0TXGMIIMIICLKIN_indelay, PHYEMAC1COL => PHYEMAC1COL_indelay, PHYEMAC1CRS => PHYEMAC1CRS_indelay, PHYEMAC1GTXCLK => PHYEMAC1GTXCLK_indelay, PHYEMAC1MCLKIN => PHYEMAC1MCLKIN_indelay, PHYEMAC1MDIN => PHYEMAC1MDIN_indelay, PHYEMAC1MIITXCLK => PHYEMAC1MIITXCLK_indelay, PHYEMAC1PHYAD => PHYEMAC1PHYAD_indelay, PHYEMAC1RXBUFERR => PHYEMAC1RXBUFERR_indelay, PHYEMAC1RXBUFSTATUS => PHYEMAC1RXBUFSTATUS_indelay, PHYEMAC1RXCHARISCOMMA => PHYEMAC1RXCHARISCOMMA_indelay, PHYEMAC1RXCHARISK => PHYEMAC1RXCHARISK_indelay, PHYEMAC1RXCHECKINGCRC => PHYEMAC1RXCHECKINGCRC_indelay, PHYEMAC1RXCLK => PHYEMAC1RXCLK_indelay, PHYEMAC1RXCLKCORCNT => PHYEMAC1RXCLKCORCNT_indelay, PHYEMAC1RXCOMMADET => PHYEMAC1RXCOMMADET_indelay, PHYEMAC1RXD => PHYEMAC1RXD_indelay, PHYEMAC1RXDISPERR => PHYEMAC1RXDISPERR_indelay, PHYEMAC1RXDV => PHYEMAC1RXDV_indelay, PHYEMAC1RXER => PHYEMAC1RXER_indelay, PHYEMAC1RXLOSSOFSYNC => PHYEMAC1RXLOSSOFSYNC_indelay, PHYEMAC1RXNOTINTABLE => PHYEMAC1RXNOTINTABLE_indelay, PHYEMAC1RXRUNDISP => PHYEMAC1RXRUNDISP_indelay, PHYEMAC1SIGNALDET => PHYEMAC1SIGNALDET_indelay, PHYEMAC1TXBUFERR => PHYEMAC1TXBUFERR_indelay, PHYEMAC1TXGMIIMIICLKIN => PHYEMAC1TXGMIIMIICLKIN_indelay, RESET => RESET_indelay ); INIPROC : process begin case EMAC0_RXHALFDUPLEX is when FALSE => EMAC0_RXHALFDUPLEX_BINARY <= '0'; when TRUE => EMAC0_RXHALFDUPLEX_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_RXHALFDUPLEX is neither TRUE nor FALSE." severity error; end case; case EMAC0_RXVLAN_ENABLE is when FALSE => EMAC0_RXVLAN_ENABLE_BINARY <= '0'; when TRUE => EMAC0_RXVLAN_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_RXVLAN_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_RX_ENABLE is when FALSE => EMAC0_RX_ENABLE_BINARY <= '0'; when TRUE => EMAC0_RX_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_RX_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_RXINBANDFCS_ENABLE is when FALSE => EMAC0_RXINBANDFCS_ENABLE_BINARY <= '0'; when TRUE => EMAC0_RXINBANDFCS_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_RXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_RXJUMBOFRAME_ENABLE is when FALSE => EMAC0_RXJUMBOFRAME_ENABLE_BINARY <= '0'; when TRUE => EMAC0_RXJUMBOFRAME_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_RXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_RXRESET is when FALSE => EMAC0_RXRESET_BINARY <= '0'; when TRUE => EMAC0_RXRESET_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_RXRESET is neither TRUE nor FALSE." severity error; end case; case EMAC0_TXIFGADJUST_ENABLE is when FALSE => EMAC0_TXIFGADJUST_ENABLE_BINARY <= '0'; when TRUE => EMAC0_TXIFGADJUST_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_TXIFGADJUST_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_TXHALFDUPLEX is when FALSE => EMAC0_TXHALFDUPLEX_BINARY <= '0'; when TRUE => EMAC0_TXHALFDUPLEX_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_TXHALFDUPLEX is neither TRUE nor FALSE." severity error; end case; case EMAC0_TXVLAN_ENABLE is when FALSE => EMAC0_TXVLAN_ENABLE_BINARY <= '0'; when TRUE => EMAC0_TXVLAN_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_TXVLAN_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_TX_ENABLE is when FALSE => EMAC0_TX_ENABLE_BINARY <= '0'; when TRUE => EMAC0_TX_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_TX_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_TXINBANDFCS_ENABLE is when FALSE => EMAC0_TXINBANDFCS_ENABLE_BINARY <= '0'; when TRUE => EMAC0_TXINBANDFCS_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_TXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_TXJUMBOFRAME_ENABLE is when FALSE => EMAC0_TXJUMBOFRAME_ENABLE_BINARY <= '0'; when TRUE => EMAC0_TXJUMBOFRAME_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_TXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_TXRESET is when FALSE => EMAC0_TXRESET_BINARY <= '0'; when TRUE => EMAC0_TXRESET_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_TXRESET is neither TRUE nor FALSE." severity error; end case; case EMAC0_TXFLOWCTRL_ENABLE is when FALSE => EMAC0_TXFLOWCTRL_ENABLE_BINARY <= '0'; when TRUE => EMAC0_TXFLOWCTRL_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_TXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_RXFLOWCTRL_ENABLE is when FALSE => EMAC0_RXFLOWCTRL_ENABLE_BINARY <= '0'; when TRUE => EMAC0_RXFLOWCTRL_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_RXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_LTCHECK_DISABLE is when FALSE => EMAC0_LTCHECK_DISABLE_BINARY <= '0'; when TRUE => EMAC0_LTCHECK_DISABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_LTCHECK_DISABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_ADDRFILTER_ENABLE is when FALSE => EMAC0_ADDRFILTER_ENABLE_BINARY <= '0'; when TRUE => EMAC0_ADDRFILTER_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_ADDRFILTER_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_RX16BITCLIENT_ENABLE is when FALSE => EMAC0_RX16BITCLIENT_ENABLE_BINARY <= '0'; when TRUE => EMAC0_RX16BITCLIENT_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_RX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_TX16BITCLIENT_ENABLE is when FALSE => EMAC0_TX16BITCLIENT_ENABLE_BINARY <= '0'; when TRUE => EMAC0_TX16BITCLIENT_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_TX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_HOST_ENABLE is when FALSE => EMAC0_HOST_ENABLE_BINARY <= '0'; when TRUE => EMAC0_HOST_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_HOST_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_1000BASEX_ENABLE is when FALSE => EMAC0_1000BASEX_ENABLE_BINARY <= '0'; when TRUE => EMAC0_1000BASEX_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_1000BASEX_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_SGMII_ENABLE is when FALSE => EMAC0_SGMII_ENABLE_BINARY <= '0'; when TRUE => EMAC0_SGMII_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_SGMII_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_RGMII_ENABLE is when FALSE => EMAC0_RGMII_ENABLE_BINARY <= '0'; when TRUE => EMAC0_RGMII_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_RGMII_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_SPEED_LSB is when FALSE => EMAC0_SPEED_LSB_BINARY <= '0'; when TRUE => EMAC0_SPEED_LSB_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_SPEED_LSB is neither TRUE nor FALSE." severity error; end case; case EMAC0_SPEED_MSB is when FALSE => EMAC0_SPEED_MSB_BINARY <= '0'; when TRUE => EMAC0_SPEED_MSB_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_SPEED_MSB is neither TRUE nor FALSE." severity error; end case; case EMAC0_MDIO_ENABLE is when FALSE => EMAC0_MDIO_ENABLE_BINARY <= '0'; when TRUE => EMAC0_MDIO_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_MDIO_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_PHYLOOPBACKMSB is when FALSE => EMAC0_PHYLOOPBACKMSB_BINARY <= '0'; when TRUE => EMAC0_PHYLOOPBACKMSB_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_PHYLOOPBACKMSB is neither TRUE nor FALSE." severity error; end case; case EMAC0_PHYPOWERDOWN is when FALSE => EMAC0_PHYPOWERDOWN_BINARY <= '0'; when TRUE => EMAC0_PHYPOWERDOWN_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_PHYPOWERDOWN is neither TRUE nor FALSE." severity error; end case; case EMAC0_PHYISOLATE is when FALSE => EMAC0_PHYISOLATE_BINARY <= '0'; when TRUE => EMAC0_PHYISOLATE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_PHYISOLATE is neither TRUE nor FALSE." severity error; end case; case EMAC0_PHYINITAUTONEG_ENABLE is when FALSE => EMAC0_PHYINITAUTONEG_ENABLE_BINARY <= '0'; when TRUE => EMAC0_PHYINITAUTONEG_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_PHYINITAUTONEG_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_PHYRESET is when FALSE => EMAC0_PHYRESET_BINARY <= '0'; when TRUE => EMAC0_PHYRESET_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_PHYRESET is neither TRUE nor FALSE." severity error; end case; case EMAC0_CONFIGVEC_79 is when FALSE => EMAC0_CONFIGVEC_79_BINARY <= '0'; when TRUE => EMAC0_CONFIGVEC_79_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_CONFIGVEC_79 is neither TRUE nor FALSE." severity error; end case; case EMAC0_UNIDIRECTION_ENABLE is when FALSE => EMAC0_UNIDIRECTION_ENABLE_BINARY <= '0'; when TRUE => EMAC0_UNIDIRECTION_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_UNIDIRECTION_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC0_GTLOOPBACK is when FALSE => EMAC0_GTLOOPBACK_BINARY <= '0'; when TRUE => EMAC0_GTLOOPBACK_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_GTLOOPBACK is neither TRUE nor FALSE." severity error; end case; case EMAC0_BYTEPHY is when FALSE => EMAC0_BYTEPHY_BINARY <= '0'; when TRUE => EMAC0_BYTEPHY_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_BYTEPHY is neither TRUE nor FALSE." severity error; end case; case EMAC0_USECLKEN is when FALSE => EMAC0_USECLKEN_BINARY <= '0'; when TRUE => EMAC0_USECLKEN_BINARY <= '1'; when others => assert FALSE report "Error : EMAC0_USECLKEN is neither TRUE nor FALSE." severity error; end case; case EMAC1_RXHALFDUPLEX is when FALSE => EMAC1_RXHALFDUPLEX_BINARY <= '0'; when TRUE => EMAC1_RXHALFDUPLEX_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_RXHALFDUPLEX is neither TRUE nor FALSE." severity error; end case; case EMAC1_RXVLAN_ENABLE is when FALSE => EMAC1_RXVLAN_ENABLE_BINARY <= '0'; when TRUE => EMAC1_RXVLAN_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_RXVLAN_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_RX_ENABLE is when FALSE => EMAC1_RX_ENABLE_BINARY <= '0'; when TRUE => EMAC1_RX_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_RX_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_RXINBANDFCS_ENABLE is when FALSE => EMAC1_RXINBANDFCS_ENABLE_BINARY <= '0'; when TRUE => EMAC1_RXINBANDFCS_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_RXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_RXJUMBOFRAME_ENABLE is when FALSE => EMAC1_RXJUMBOFRAME_ENABLE_BINARY <= '0'; when TRUE => EMAC1_RXJUMBOFRAME_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_RXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_RXRESET is when FALSE => EMAC1_RXRESET_BINARY <= '0'; when TRUE => EMAC1_RXRESET_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_RXRESET is neither TRUE nor FALSE." severity error; end case; case EMAC1_TXIFGADJUST_ENABLE is when FALSE => EMAC1_TXIFGADJUST_ENABLE_BINARY <= '0'; when TRUE => EMAC1_TXIFGADJUST_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_TXIFGADJUST_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_TXHALFDUPLEX is when FALSE => EMAC1_TXHALFDUPLEX_BINARY <= '0'; when TRUE => EMAC1_TXHALFDUPLEX_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_TXHALFDUPLEX is neither TRUE nor FALSE." severity error; end case; case EMAC1_TXVLAN_ENABLE is when FALSE => EMAC1_TXVLAN_ENABLE_BINARY <= '0'; when TRUE => EMAC1_TXVLAN_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_TXVLAN_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_TX_ENABLE is when FALSE => EMAC1_TX_ENABLE_BINARY <= '0'; when TRUE => EMAC1_TX_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_TX_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_TXINBANDFCS_ENABLE is when FALSE => EMAC1_TXINBANDFCS_ENABLE_BINARY <= '0'; when TRUE => EMAC1_TXINBANDFCS_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_TXINBANDFCS_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_TXJUMBOFRAME_ENABLE is when FALSE => EMAC1_TXJUMBOFRAME_ENABLE_BINARY <= '0'; when TRUE => EMAC1_TXJUMBOFRAME_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_TXJUMBOFRAME_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_TXRESET is when FALSE => EMAC1_TXRESET_BINARY <= '0'; when TRUE => EMAC1_TXRESET_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_TXRESET is neither TRUE nor FALSE." severity error; end case; case EMAC1_TXFLOWCTRL_ENABLE is when FALSE => EMAC1_TXFLOWCTRL_ENABLE_BINARY <= '0'; when TRUE => EMAC1_TXFLOWCTRL_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_TXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_RXFLOWCTRL_ENABLE is when FALSE => EMAC1_RXFLOWCTRL_ENABLE_BINARY <= '0'; when TRUE => EMAC1_RXFLOWCTRL_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_RXFLOWCTRL_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_LTCHECK_DISABLE is when FALSE => EMAC1_LTCHECK_DISABLE_BINARY <= '0'; when TRUE => EMAC1_LTCHECK_DISABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_LTCHECK_DISABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_ADDRFILTER_ENABLE is when FALSE => EMAC1_ADDRFILTER_ENABLE_BINARY <= '0'; when TRUE => EMAC1_ADDRFILTER_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_ADDRFILTER_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_RX16BITCLIENT_ENABLE is when FALSE => EMAC1_RX16BITCLIENT_ENABLE_BINARY <= '0'; when TRUE => EMAC1_RX16BITCLIENT_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_RX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_TX16BITCLIENT_ENABLE is when FALSE => EMAC1_TX16BITCLIENT_ENABLE_BINARY <= '0'; when TRUE => EMAC1_TX16BITCLIENT_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_TX16BITCLIENT_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_HOST_ENABLE is when FALSE => EMAC1_HOST_ENABLE_BINARY <= '0'; when TRUE => EMAC1_HOST_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_HOST_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_1000BASEX_ENABLE is when FALSE => EMAC1_1000BASEX_ENABLE_BINARY <= '0'; when TRUE => EMAC1_1000BASEX_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_1000BASEX_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_SGMII_ENABLE is when FALSE => EMAC1_SGMII_ENABLE_BINARY <= '0'; when TRUE => EMAC1_SGMII_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_SGMII_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_RGMII_ENABLE is when FALSE => EMAC1_RGMII_ENABLE_BINARY <= '0'; when TRUE => EMAC1_RGMII_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_RGMII_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_SPEED_LSB is when FALSE => EMAC1_SPEED_LSB_BINARY <= '0'; when TRUE => EMAC1_SPEED_LSB_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_SPEED_LSB is neither TRUE nor FALSE." severity error; end case; case EMAC1_SPEED_MSB is when FALSE => EMAC1_SPEED_MSB_BINARY <= '0'; when TRUE => EMAC1_SPEED_MSB_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_SPEED_MSB is neither TRUE nor FALSE." severity error; end case; case EMAC1_MDIO_ENABLE is when FALSE => EMAC1_MDIO_ENABLE_BINARY <= '0'; when TRUE => EMAC1_MDIO_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_MDIO_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_PHYLOOPBACKMSB is when FALSE => EMAC1_PHYLOOPBACKMSB_BINARY <= '0'; when TRUE => EMAC1_PHYLOOPBACKMSB_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_PHYLOOPBACKMSB is neither TRUE nor FALSE." severity error; end case; case EMAC1_PHYPOWERDOWN is when FALSE => EMAC1_PHYPOWERDOWN_BINARY <= '0'; when TRUE => EMAC1_PHYPOWERDOWN_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_PHYPOWERDOWN is neither TRUE nor FALSE." severity error; end case; case EMAC1_PHYISOLATE is when FALSE => EMAC1_PHYISOLATE_BINARY <= '0'; when TRUE => EMAC1_PHYISOLATE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_PHYISOLATE is neither TRUE nor FALSE." severity error; end case; case EMAC1_PHYINITAUTONEG_ENABLE is when FALSE => EMAC1_PHYINITAUTONEG_ENABLE_BINARY <= '0'; when TRUE => EMAC1_PHYINITAUTONEG_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_PHYINITAUTONEG_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_PHYRESET is when FALSE => EMAC1_PHYRESET_BINARY <= '0'; when TRUE => EMAC1_PHYRESET_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_PHYRESET is neither TRUE nor FALSE." severity error; end case; case EMAC1_CONFIGVEC_79 is when FALSE => EMAC1_CONFIGVEC_79_BINARY <= '0'; when TRUE => EMAC1_CONFIGVEC_79_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_CONFIGVEC_79 is neither TRUE nor FALSE." severity error; end case; case EMAC1_UNIDIRECTION_ENABLE is when FALSE => EMAC1_UNIDIRECTION_ENABLE_BINARY <= '0'; when TRUE => EMAC1_UNIDIRECTION_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_UNIDIRECTION_ENABLE is neither TRUE nor FALSE." severity error; end case; case EMAC1_GTLOOPBACK is when FALSE => EMAC1_GTLOOPBACK_BINARY <= '0'; when TRUE => EMAC1_GTLOOPBACK_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_GTLOOPBACK is neither TRUE nor FALSE." severity error; end case; case EMAC1_BYTEPHY is when FALSE => EMAC1_BYTEPHY_BINARY <= '0'; when TRUE => EMAC1_BYTEPHY_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_BYTEPHY is neither TRUE nor FALSE." severity error; end case; case EMAC1_USECLKEN is when FALSE => EMAC1_USECLKEN_BINARY <= '0'; when TRUE => EMAC1_USECLKEN_BINARY <= '1'; when others => assert FALSE report "Error : EMAC1_USECLKEN is neither TRUE nor FALSE." severity error; end case; wait; end process INIPROC; TIMING : process variable DCRHOSTDONEIR_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTANINTERRUPT_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXBADFRAME_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD0_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD1_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD2_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD3_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD4_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD5_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD6_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD7_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD8_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD9_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD10_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD11_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD12_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD13_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD14_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXD15_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXDVLD_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXDVLDMSW_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXFRAMEDROP_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXGOODFRAME_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS0_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS1_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS2_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS3_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS4_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS5_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATS6_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTRXSTATSVLD_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXACK_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXCOLLISION_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXGMIIMIICLKOUT_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXRETRANSMIT_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXSTATS_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; variable EMAC0CLIENTTXSTATSVLD_GlitchData : VitalGlitchDataType; variable EMAC0PHYENCOMMAALIGN_GlitchData : VitalGlitchDataType; variable EMAC0PHYLOOPBACKMSB_GlitchData : VitalGlitchDataType; variable EMAC0PHYMCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC0PHYMDOUT_GlitchData : VitalGlitchDataType; variable EMAC0PHYMDTRI_GlitchData : VitalGlitchDataType; variable EMAC0PHYMGTRXRESET_GlitchData : VitalGlitchDataType; variable EMAC0PHYMGTTXRESET_GlitchData : VitalGlitchDataType; variable EMAC0PHYPOWERDOWN_GlitchData : VitalGlitchDataType; variable EMAC0PHYSYNCACQSTATUS_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXCHARDISPMODE_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXCHARDISPVAL_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXCHARISK_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXCLK_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD0_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD1_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD2_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD3_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD4_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD5_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD6_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXD7_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXEN_GlitchData : VitalGlitchDataType; variable EMAC0PHYTXER_GlitchData : VitalGlitchDataType; variable EMAC0SPEEDIS10100_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTANINTERRUPT_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXBADFRAME_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD0_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD1_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD2_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD3_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD4_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD5_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD6_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD7_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD8_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD9_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD10_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD11_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD12_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD13_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD14_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXD15_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXDVLD_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXDVLDMSW_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXFRAMEDROP_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXGOODFRAME_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS0_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS1_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS2_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS3_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS4_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS5_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATS6_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTRXSTATSVLD_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXACK_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXCLIENTCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXCOLLISION_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXGMIIMIICLKOUT_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXRETRANSMIT_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXSTATS_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXSTATSBYTEVLD_GlitchData : VitalGlitchDataType; variable EMAC1CLIENTTXSTATSVLD_GlitchData : VitalGlitchDataType; variable EMAC1PHYENCOMMAALIGN_GlitchData : VitalGlitchDataType; variable EMAC1PHYLOOPBACKMSB_GlitchData : VitalGlitchDataType; variable EMAC1PHYMCLKOUT_GlitchData : VitalGlitchDataType; variable EMAC1PHYMDOUT_GlitchData : VitalGlitchDataType; variable EMAC1PHYMDTRI_GlitchData : VitalGlitchDataType; variable EMAC1PHYMGTRXRESET_GlitchData : VitalGlitchDataType; variable EMAC1PHYMGTTXRESET_GlitchData : VitalGlitchDataType; variable EMAC1PHYPOWERDOWN_GlitchData : VitalGlitchDataType; variable EMAC1PHYSYNCACQSTATUS_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXCHARDISPMODE_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXCHARDISPVAL_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXCHARISK_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXCLK_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD0_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD1_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD2_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD3_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD4_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD5_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD6_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXD7_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXEN_GlitchData : VitalGlitchDataType; variable EMAC1PHYTXER_GlitchData : VitalGlitchDataType; variable EMAC1SPEEDIS10100_GlitchData : VitalGlitchDataType; variable EMACDCRACK_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS0_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS1_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS2_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS3_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS4_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS5_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS6_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS7_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS8_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS9_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS10_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS11_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS12_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS13_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS14_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS15_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS16_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS17_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS18_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS19_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS20_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS21_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS22_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS23_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS24_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS25_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS26_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS27_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS28_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS29_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS30_GlitchData : VitalGlitchDataType; variable EMACDCRDBUS31_GlitchData : VitalGlitchDataType; variable HOSTMIIMRDY_GlitchData : VitalGlitchDataType; variable HOSTRDDATA0_GlitchData : VitalGlitchDataType; variable HOSTRDDATA1_GlitchData : VitalGlitchDataType; variable HOSTRDDATA2_GlitchData : VitalGlitchDataType; variable HOSTRDDATA3_GlitchData : VitalGlitchDataType; variable HOSTRDDATA4_GlitchData : VitalGlitchDataType; variable HOSTRDDATA5_GlitchData : VitalGlitchDataType; variable HOSTRDDATA6_GlitchData : VitalGlitchDataType; variable HOSTRDDATA7_GlitchData : VitalGlitchDataType; variable HOSTRDDATA8_GlitchData : VitalGlitchDataType; variable HOSTRDDATA9_GlitchData : VitalGlitchDataType; variable HOSTRDDATA10_GlitchData : VitalGlitchDataType; variable HOSTRDDATA11_GlitchData : VitalGlitchDataType; variable HOSTRDDATA12_GlitchData : VitalGlitchDataType; variable HOSTRDDATA13_GlitchData : VitalGlitchDataType; variable HOSTRDDATA14_GlitchData : VitalGlitchDataType; variable HOSTRDDATA15_GlitchData : VitalGlitchDataType; variable HOSTRDDATA16_GlitchData : VitalGlitchDataType; variable HOSTRDDATA17_GlitchData : VitalGlitchDataType; variable HOSTRDDATA18_GlitchData : VitalGlitchDataType; variable HOSTRDDATA19_GlitchData : VitalGlitchDataType; variable HOSTRDDATA20_GlitchData : VitalGlitchDataType; variable HOSTRDDATA21_GlitchData : VitalGlitchDataType; variable HOSTRDDATA22_GlitchData : VitalGlitchDataType; variable HOSTRDDATA23_GlitchData : VitalGlitchDataType; variable HOSTRDDATA24_GlitchData : VitalGlitchDataType; variable HOSTRDDATA25_GlitchData : VitalGlitchDataType; variable HOSTRDDATA26_GlitchData : VitalGlitchDataType; variable HOSTRDDATA27_GlitchData : VitalGlitchDataType; variable HOSTRDDATA28_GlitchData : VitalGlitchDataType; variable HOSTRDDATA29_GlitchData : VitalGlitchDataType; variable HOSTRDDATA30_GlitchData : VitalGlitchDataType; variable HOSTRDDATA31_GlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => DCRHOSTDONEIR, GlitchData => DCRHOSTDONEIR_GlitchData, OutSignalName => "DCRHOSTDONEIR", OutTemp => DCRHOSTDONEIR_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTANINTERRUPT, GlitchData => EMAC0CLIENTANINTERRUPT_GlitchData, OutSignalName => "EMAC0CLIENTANINTERRUPT", OutTemp => EMAC0CLIENTANINTERRUPT_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXBADFRAME, GlitchData => EMAC0CLIENTRXBADFRAME_GlitchData, OutSignalName => "EMAC0CLIENTRXBADFRAME", OutTemp => EMAC0CLIENTRXBADFRAME_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXBADFRAME, GlitchData => EMAC0CLIENTRXBADFRAME_GlitchData, OutSignalName => "EMAC0CLIENTRXBADFRAME", OutTemp => EMAC0CLIENTRXBADFRAME_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXBADFRAME, GlitchData => EMAC0CLIENTRXBADFRAME_GlitchData, OutSignalName => "EMAC0CLIENTRXBADFRAME", OutTemp => EMAC0CLIENTRXBADFRAME_OUT, Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXCLIENTCLKOUT, GlitchData => EMAC0CLIENTRXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC0CLIENTRXCLIENTCLKOUT", OutTemp => EMAC0CLIENTRXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(0), GlitchData => EMAC0CLIENTRXD0_GlitchData, OutSignalName => "EMAC0CLIENTRXD(0)", OutTemp => EMAC0CLIENTRXD_OUT(0), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(0), GlitchData => EMAC0CLIENTRXD0_GlitchData, OutSignalName => "EMAC0CLIENTRXD(0)", OutTemp => EMAC0CLIENTRXD_OUT(0), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(0), GlitchData => EMAC0CLIENTRXD0_GlitchData, OutSignalName => "EMAC0CLIENTRXD(0)", OutTemp => EMAC0CLIENTRXD_OUT(0), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(1), GlitchData => EMAC0CLIENTRXD1_GlitchData, OutSignalName => "EMAC0CLIENTRXD(1)", OutTemp => EMAC0CLIENTRXD_OUT(1), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(1), GlitchData => EMAC0CLIENTRXD1_GlitchData, OutSignalName => "EMAC0CLIENTRXD(1)", OutTemp => EMAC0CLIENTRXD_OUT(1), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(1), GlitchData => EMAC0CLIENTRXD1_GlitchData, OutSignalName => "EMAC0CLIENTRXD(1)", OutTemp => EMAC0CLIENTRXD_OUT(1), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(2), GlitchData => EMAC0CLIENTRXD2_GlitchData, OutSignalName => "EMAC0CLIENTRXD(2)", OutTemp => EMAC0CLIENTRXD_OUT(2), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(2), GlitchData => EMAC0CLIENTRXD2_GlitchData, OutSignalName => "EMAC0CLIENTRXD(2)", OutTemp => EMAC0CLIENTRXD_OUT(2), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(2), GlitchData => EMAC0CLIENTRXD2_GlitchData, OutSignalName => "EMAC0CLIENTRXD(2)", OutTemp => EMAC0CLIENTRXD_OUT(2), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(3), GlitchData => EMAC0CLIENTRXD3_GlitchData, OutSignalName => "EMAC0CLIENTRXD(3)", OutTemp => EMAC0CLIENTRXD_OUT(3), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(3), GlitchData => EMAC0CLIENTRXD3_GlitchData, OutSignalName => "EMAC0CLIENTRXD(3)", OutTemp => EMAC0CLIENTRXD_OUT(3), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(3), GlitchData => EMAC0CLIENTRXD3_GlitchData, OutSignalName => "EMAC0CLIENTRXD(3)", OutTemp => EMAC0CLIENTRXD_OUT(3), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(4), GlitchData => EMAC0CLIENTRXD4_GlitchData, OutSignalName => "EMAC0CLIENTRXD(4)", OutTemp => EMAC0CLIENTRXD_OUT(4), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(4), GlitchData => EMAC0CLIENTRXD4_GlitchData, OutSignalName => "EMAC0CLIENTRXD(4)", OutTemp => EMAC0CLIENTRXD_OUT(4), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(4), GlitchData => EMAC0CLIENTRXD4_GlitchData, OutSignalName => "EMAC0CLIENTRXD(4)", OutTemp => EMAC0CLIENTRXD_OUT(4), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(5), GlitchData => EMAC0CLIENTRXD5_GlitchData, OutSignalName => "EMAC0CLIENTRXD(5)", OutTemp => EMAC0CLIENTRXD_OUT(5), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(5), GlitchData => EMAC0CLIENTRXD5_GlitchData, OutSignalName => "EMAC0CLIENTRXD(5)", OutTemp => EMAC0CLIENTRXD_OUT(5), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(5), GlitchData => EMAC0CLIENTRXD5_GlitchData, OutSignalName => "EMAC0CLIENTRXD(5)", OutTemp => EMAC0CLIENTRXD_OUT(5), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(6), GlitchData => EMAC0CLIENTRXD6_GlitchData, OutSignalName => "EMAC0CLIENTRXD(6)", OutTemp => EMAC0CLIENTRXD_OUT(6), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(6), GlitchData => EMAC0CLIENTRXD6_GlitchData, OutSignalName => "EMAC0CLIENTRXD(6)", OutTemp => EMAC0CLIENTRXD_OUT(6), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(6), GlitchData => EMAC0CLIENTRXD6_GlitchData, OutSignalName => "EMAC0CLIENTRXD(6)", OutTemp => EMAC0CLIENTRXD_OUT(6), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(7), GlitchData => EMAC0CLIENTRXD7_GlitchData, OutSignalName => "EMAC0CLIENTRXD(7)", OutTemp => EMAC0CLIENTRXD_OUT(7), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(7), GlitchData => EMAC0CLIENTRXD7_GlitchData, OutSignalName => "EMAC0CLIENTRXD(7)", OutTemp => EMAC0CLIENTRXD_OUT(7), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(7), GlitchData => EMAC0CLIENTRXD7_GlitchData, OutSignalName => "EMAC0CLIENTRXD(7)", OutTemp => EMAC0CLIENTRXD_OUT(7), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(8), GlitchData => EMAC0CLIENTRXD8_GlitchData, OutSignalName => "EMAC0CLIENTRXD(8)", OutTemp => EMAC0CLIENTRXD_OUT(8), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(8), GlitchData => EMAC0CLIENTRXD8_GlitchData, OutSignalName => "EMAC0CLIENTRXD(8)", OutTemp => EMAC0CLIENTRXD_OUT(8), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(8), GlitchData => EMAC0CLIENTRXD8_GlitchData, OutSignalName => "EMAC0CLIENTRXD(8)", OutTemp => EMAC0CLIENTRXD_OUT(8), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(9), GlitchData => EMAC0CLIENTRXD9_GlitchData, OutSignalName => "EMAC0CLIENTRXD(9)", OutTemp => EMAC0CLIENTRXD_OUT(9), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(9), GlitchData => EMAC0CLIENTRXD9_GlitchData, OutSignalName => "EMAC0CLIENTRXD(9)", OutTemp => EMAC0CLIENTRXD_OUT(9), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(9), GlitchData => EMAC0CLIENTRXD9_GlitchData, OutSignalName => "EMAC0CLIENTRXD(9)", OutTemp => EMAC0CLIENTRXD_OUT(9), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(10), GlitchData => EMAC0CLIENTRXD10_GlitchData, OutSignalName => "EMAC0CLIENTRXD(10)", OutTemp => EMAC0CLIENTRXD_OUT(10), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(10), GlitchData => EMAC0CLIENTRXD10_GlitchData, OutSignalName => "EMAC0CLIENTRXD(10)", OutTemp => EMAC0CLIENTRXD_OUT(10), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(10), GlitchData => EMAC0CLIENTRXD10_GlitchData, OutSignalName => "EMAC0CLIENTRXD(10)", OutTemp => EMAC0CLIENTRXD_OUT(10), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(11), GlitchData => EMAC0CLIENTRXD11_GlitchData, OutSignalName => "EMAC0CLIENTRXD(11)", OutTemp => EMAC0CLIENTRXD_OUT(11), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(11), GlitchData => EMAC0CLIENTRXD11_GlitchData, OutSignalName => "EMAC0CLIENTRXD(11)", OutTemp => EMAC0CLIENTRXD_OUT(11), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(11), GlitchData => EMAC0CLIENTRXD11_GlitchData, OutSignalName => "EMAC0CLIENTRXD(11)", OutTemp => EMAC0CLIENTRXD_OUT(11), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(12), GlitchData => EMAC0CLIENTRXD12_GlitchData, OutSignalName => "EMAC0CLIENTRXD(12)", OutTemp => EMAC0CLIENTRXD_OUT(12), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(12), GlitchData => EMAC0CLIENTRXD12_GlitchData, OutSignalName => "EMAC0CLIENTRXD(12)", OutTemp => EMAC0CLIENTRXD_OUT(12), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(12), GlitchData => EMAC0CLIENTRXD12_GlitchData, OutSignalName => "EMAC0CLIENTRXD(12)", OutTemp => EMAC0CLIENTRXD_OUT(12), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(13), GlitchData => EMAC0CLIENTRXD13_GlitchData, OutSignalName => "EMAC0CLIENTRXD(13)", OutTemp => EMAC0CLIENTRXD_OUT(13), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(13), GlitchData => EMAC0CLIENTRXD13_GlitchData, OutSignalName => "EMAC0CLIENTRXD(13)", OutTemp => EMAC0CLIENTRXD_OUT(13), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(13), GlitchData => EMAC0CLIENTRXD13_GlitchData, OutSignalName => "EMAC0CLIENTRXD(13)", OutTemp => EMAC0CLIENTRXD_OUT(13), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(14), GlitchData => EMAC0CLIENTRXD14_GlitchData, OutSignalName => "EMAC0CLIENTRXD(14)", OutTemp => EMAC0CLIENTRXD_OUT(14), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(14), GlitchData => EMAC0CLIENTRXD14_GlitchData, OutSignalName => "EMAC0CLIENTRXD(14)", OutTemp => EMAC0CLIENTRXD_OUT(14), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(14), GlitchData => EMAC0CLIENTRXD14_GlitchData, OutSignalName => "EMAC0CLIENTRXD(14)", OutTemp => EMAC0CLIENTRXD_OUT(14), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(15), GlitchData => EMAC0CLIENTRXD15_GlitchData, OutSignalName => "EMAC0CLIENTRXD(15)", OutTemp => EMAC0CLIENTRXD_OUT(15), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(15), GlitchData => EMAC0CLIENTRXD15_GlitchData, OutSignalName => "EMAC0CLIENTRXD(15)", OutTemp => EMAC0CLIENTRXD_OUT(15), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXD(15), GlitchData => EMAC0CLIENTRXD15_GlitchData, OutSignalName => "EMAC0CLIENTRXD(15)", OutTemp => EMAC0CLIENTRXD_OUT(15), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXDVLD, GlitchData => EMAC0CLIENTRXDVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXDVLD", OutTemp => EMAC0CLIENTRXDVLD_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXDVLD, GlitchData => EMAC0CLIENTRXDVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXDVLD", OutTemp => EMAC0CLIENTRXDVLD_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXDVLD, GlitchData => EMAC0CLIENTRXDVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXDVLD", OutTemp => EMAC0CLIENTRXDVLD_OUT, Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXDVLDMSW, GlitchData => EMAC0CLIENTRXDVLDMSW_GlitchData, OutSignalName => "EMAC0CLIENTRXDVLDMSW", OutTemp => EMAC0CLIENTRXDVLDMSW_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXDVLDMSW, GlitchData => EMAC0CLIENTRXDVLDMSW_GlitchData, OutSignalName => "EMAC0CLIENTRXDVLDMSW", OutTemp => EMAC0CLIENTRXDVLDMSW_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXDVLDMSW, GlitchData => EMAC0CLIENTRXDVLDMSW_GlitchData, OutSignalName => "EMAC0CLIENTRXDVLDMSW", OutTemp => EMAC0CLIENTRXDVLDMSW_OUT, Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXFRAMEDROP, GlitchData => EMAC0CLIENTRXFRAMEDROP_GlitchData, OutSignalName => "EMAC0CLIENTRXFRAMEDROP", OutTemp => EMAC0CLIENTRXFRAMEDROP_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXFRAMEDROP, GlitchData => EMAC0CLIENTRXFRAMEDROP_GlitchData, OutSignalName => "EMAC0CLIENTRXFRAMEDROP", OutTemp => EMAC0CLIENTRXFRAMEDROP_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXFRAMEDROP, GlitchData => EMAC0CLIENTRXFRAMEDROP_GlitchData, OutSignalName => "EMAC0CLIENTRXFRAMEDROP", OutTemp => EMAC0CLIENTRXFRAMEDROP_OUT, Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXGOODFRAME, GlitchData => EMAC0CLIENTRXGOODFRAME_GlitchData, OutSignalName => "EMAC0CLIENTRXGOODFRAME", OutTemp => EMAC0CLIENTRXGOODFRAME_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXGOODFRAME, GlitchData => EMAC0CLIENTRXGOODFRAME_GlitchData, OutSignalName => "EMAC0CLIENTRXGOODFRAME", OutTemp => EMAC0CLIENTRXGOODFRAME_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXGOODFRAME, GlitchData => EMAC0CLIENTRXGOODFRAME_GlitchData, OutSignalName => "EMAC0CLIENTRXGOODFRAME", OutTemp => EMAC0CLIENTRXGOODFRAME_OUT, Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(0), GlitchData => EMAC0CLIENTRXSTATS0_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(0)", OutTemp => EMAC0CLIENTRXSTATS_OUT(0), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(0), GlitchData => EMAC0CLIENTRXSTATS0_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(0)", OutTemp => EMAC0CLIENTRXSTATS_OUT(0), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(0), GlitchData => EMAC0CLIENTRXSTATS0_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(0)", OutTemp => EMAC0CLIENTRXSTATS_OUT(0), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(1), GlitchData => EMAC0CLIENTRXSTATS1_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(1)", OutTemp => EMAC0CLIENTRXSTATS_OUT(1), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(1), GlitchData => EMAC0CLIENTRXSTATS1_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(1)", OutTemp => EMAC0CLIENTRXSTATS_OUT(1), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(1), GlitchData => EMAC0CLIENTRXSTATS1_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(1)", OutTemp => EMAC0CLIENTRXSTATS_OUT(1), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(2), GlitchData => EMAC0CLIENTRXSTATS2_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(2)", OutTemp => EMAC0CLIENTRXSTATS_OUT(2), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(2), GlitchData => EMAC0CLIENTRXSTATS2_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(2)", OutTemp => EMAC0CLIENTRXSTATS_OUT(2), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(2), GlitchData => EMAC0CLIENTRXSTATS2_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(2)", OutTemp => EMAC0CLIENTRXSTATS_OUT(2), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(3), GlitchData => EMAC0CLIENTRXSTATS3_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(3)", OutTemp => EMAC0CLIENTRXSTATS_OUT(3), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(3), GlitchData => EMAC0CLIENTRXSTATS3_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(3)", OutTemp => EMAC0CLIENTRXSTATS_OUT(3), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(3), GlitchData => EMAC0CLIENTRXSTATS3_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(3)", OutTemp => EMAC0CLIENTRXSTATS_OUT(3), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(4), GlitchData => EMAC0CLIENTRXSTATS4_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(4)", OutTemp => EMAC0CLIENTRXSTATS_OUT(4), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(4), GlitchData => EMAC0CLIENTRXSTATS4_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(4)", OutTemp => EMAC0CLIENTRXSTATS_OUT(4), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(4), GlitchData => EMAC0CLIENTRXSTATS4_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(4)", OutTemp => EMAC0CLIENTRXSTATS_OUT(4), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(5), GlitchData => EMAC0CLIENTRXSTATS5_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(5)", OutTemp => EMAC0CLIENTRXSTATS_OUT(5), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(5), GlitchData => EMAC0CLIENTRXSTATS5_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(5)", OutTemp => EMAC0CLIENTRXSTATS_OUT(5), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(5), GlitchData => EMAC0CLIENTRXSTATS5_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(5)", OutTemp => EMAC0CLIENTRXSTATS_OUT(5), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(6), GlitchData => EMAC0CLIENTRXSTATS6_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(6)", OutTemp => EMAC0CLIENTRXSTATS_OUT(6), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(6), GlitchData => EMAC0CLIENTRXSTATS6_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(6)", OutTemp => EMAC0CLIENTRXSTATS_OUT(6), Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATS(6), GlitchData => EMAC0CLIENTRXSTATS6_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATS(6)", OutTemp => EMAC0CLIENTRXSTATS_OUT(6), Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATSBYTEVLD, GlitchData => EMAC0CLIENTRXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATSBYTEVLD", OutTemp => EMAC0CLIENTRXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATSBYTEVLD, GlitchData => EMAC0CLIENTRXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATSBYTEVLD", OutTemp => EMAC0CLIENTRXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATSBYTEVLD, GlitchData => EMAC0CLIENTRXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATSBYTEVLD", OutTemp => EMAC0CLIENTRXSTATSBYTEVLD_OUT, Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATSVLD, GlitchData => EMAC0CLIENTRXSTATSVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATSVLD", OutTemp => EMAC0CLIENTRXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATSVLD, GlitchData => EMAC0CLIENTRXSTATSVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATSVLD", OutTemp => EMAC0CLIENTRXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC0RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTRXSTATSVLD, GlitchData => EMAC0CLIENTRXSTATSVLD_GlitchData, OutSignalName => "EMAC0CLIENTRXSTATSVLD", OutTemp => EMAC0CLIENTRXSTATSVLD_OUT, Paths => (0 => (PHYEMAC0RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXACK, GlitchData => EMAC0CLIENTTXACK_GlitchData, OutSignalName => "EMAC0CLIENTTXACK", OutTemp => EMAC0CLIENTTXACK_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXACK, GlitchData => EMAC0CLIENTTXACK_GlitchData, OutSignalName => "EMAC0CLIENTTXACK", OutTemp => EMAC0CLIENTTXACK_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXACK, GlitchData => EMAC0CLIENTTXACK_GlitchData, OutSignalName => "EMAC0CLIENTTXACK", OutTemp => EMAC0CLIENTTXACK_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXCLIENTCLKOUT, GlitchData => EMAC0CLIENTTXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC0CLIENTTXCLIENTCLKOUT", OutTemp => EMAC0CLIENTTXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXCLIENTCLKOUT, GlitchData => EMAC0CLIENTTXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC0CLIENTTXCLIENTCLKOUT", OutTemp => EMAC0CLIENTTXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC0MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXCLIENTCLKOUT, GlitchData => EMAC0CLIENTTXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC0CLIENTTXCLIENTCLKOUT", OutTemp => EMAC0CLIENTTXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXCOLLISION, GlitchData => EMAC0CLIENTTXCOLLISION_GlitchData, OutSignalName => "EMAC0CLIENTTXCOLLISION", OutTemp => EMAC0CLIENTTXCOLLISION_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXCOLLISION, GlitchData => EMAC0CLIENTTXCOLLISION_GlitchData, OutSignalName => "EMAC0CLIENTTXCOLLISION", OutTemp => EMAC0CLIENTTXCOLLISION_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXCOLLISION, GlitchData => EMAC0CLIENTTXCOLLISION_GlitchData, OutSignalName => "EMAC0CLIENTTXCOLLISION", OutTemp => EMAC0CLIENTTXCOLLISION_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXGMIIMIICLKOUT, GlitchData => EMAC0PHYTXGMIIMIICLKOUT_GlitchData, OutSignalName => "EMAC0PHYTXGMIIMIICLKOUT", OutTemp => EMAC0PHYTXGMIIMIICLKOUT_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXGMIIMIICLKOUT, GlitchData => EMAC0PHYTXGMIIMIICLKOUT_GlitchData, OutSignalName => "EMAC0PHYTXGMIIMIICLKOUT", OutTemp => EMAC0PHYTXGMIIMIICLKOUT_OUT, Paths => (0 => (PHYEMAC0MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXRETRANSMIT, GlitchData => EMAC0CLIENTTXRETRANSMIT_GlitchData, OutSignalName => "EMAC0CLIENTTXRETRANSMIT", OutTemp => EMAC0CLIENTTXRETRANSMIT_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXRETRANSMIT, GlitchData => EMAC0CLIENTTXRETRANSMIT_GlitchData, OutSignalName => "EMAC0CLIENTTXRETRANSMIT", OutTemp => EMAC0CLIENTTXRETRANSMIT_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXRETRANSMIT, GlitchData => EMAC0CLIENTTXRETRANSMIT_GlitchData, OutSignalName => "EMAC0CLIENTTXRETRANSMIT", OutTemp => EMAC0CLIENTTXRETRANSMIT_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATS, GlitchData => EMAC0CLIENTTXSTATS_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATS", OutTemp => EMAC0CLIENTTXSTATS_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATS, GlitchData => EMAC0CLIENTTXSTATS_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATS", OutTemp => EMAC0CLIENTTXSTATS_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATS, GlitchData => EMAC0CLIENTTXSTATS_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATS", OutTemp => EMAC0CLIENTTXSTATS_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATSBYTEVLD, GlitchData => EMAC0CLIENTTXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATSBYTEVLD", OutTemp => EMAC0CLIENTTXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATSBYTEVLD, GlitchData => EMAC0CLIENTTXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATSBYTEVLD", OutTemp => EMAC0CLIENTTXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATSBYTEVLD, GlitchData => EMAC0CLIENTTXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATSBYTEVLD", OutTemp => EMAC0CLIENTTXSTATSBYTEVLD_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATSVLD, GlitchData => EMAC0CLIENTTXSTATSVLD_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATSVLD", OutTemp => EMAC0CLIENTTXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATSVLD, GlitchData => EMAC0CLIENTTXSTATSVLD_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATSVLD", OutTemp => EMAC0CLIENTTXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC0TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0CLIENTTXSTATSVLD, GlitchData => EMAC0CLIENTTXSTATSVLD_GlitchData, OutSignalName => "EMAC0CLIENTTXSTATSVLD", OutTemp => EMAC0CLIENTTXSTATSVLD_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYENCOMMAALIGN, GlitchData => EMAC0PHYENCOMMAALIGN_GlitchData, OutSignalName => "EMAC0PHYENCOMMAALIGN", OutTemp => EMAC0PHYENCOMMAALIGN_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYLOOPBACKMSB, GlitchData => EMAC0PHYLOOPBACKMSB_GlitchData, OutSignalName => "EMAC0PHYLOOPBACKMSB", OutTemp => EMAC0PHYLOOPBACKMSB_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMCLKOUT, GlitchData => EMAC0PHYMCLKOUT_GlitchData, OutSignalName => "EMAC0PHYMCLKOUT", OutTemp => EMAC0PHYMCLKOUT_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMCLKOUT, GlitchData => EMAC0PHYMCLKOUT_GlitchData, OutSignalName => "EMAC0PHYMCLKOUT", OutTemp => EMAC0PHYMCLKOUT_OUT, Paths => (0 => (PHYEMAC0MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMDOUT, GlitchData => EMAC0PHYMDOUT_GlitchData, OutSignalName => "EMAC0PHYMDOUT", OutTemp => EMAC0PHYMDOUT_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMDOUT, GlitchData => EMAC0PHYMDOUT_GlitchData, OutSignalName => "EMAC0PHYMDOUT", OutTemp => EMAC0PHYMDOUT_OUT, Paths => (0 => (PHYEMAC0MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMDTRI, GlitchData => EMAC0PHYMDTRI_GlitchData, OutSignalName => "EMAC0PHYMDTRI", OutTemp => EMAC0PHYMDTRI_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMDTRI, GlitchData => EMAC0PHYMDTRI_GlitchData, OutSignalName => "EMAC0PHYMDTRI", OutTemp => EMAC0PHYMDTRI_OUT, Paths => (0 => (PHYEMAC0MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMGTRXRESET, GlitchData => EMAC0PHYMGTRXRESET_GlitchData, OutSignalName => "EMAC0PHYMGTRXRESET", OutTemp => EMAC0PHYMGTRXRESET_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYMGTTXRESET, GlitchData => EMAC0PHYMGTTXRESET_GlitchData, OutSignalName => "EMAC0PHYMGTTXRESET", OutTemp => EMAC0PHYMGTTXRESET_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYPOWERDOWN, GlitchData => EMAC0PHYPOWERDOWN_GlitchData, OutSignalName => "EMAC0PHYPOWERDOWN", OutTemp => EMAC0PHYPOWERDOWN_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYSYNCACQSTATUS, GlitchData => EMAC0PHYSYNCACQSTATUS_GlitchData, OutSignalName => "EMAC0PHYSYNCACQSTATUS", OutTemp => EMAC0PHYSYNCACQSTATUS_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYSYNCACQSTATUS, GlitchData => EMAC0PHYSYNCACQSTATUS_GlitchData, OutSignalName => "EMAC0PHYSYNCACQSTATUS", OutTemp => EMAC0PHYSYNCACQSTATUS_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYSYNCACQSTATUS, GlitchData => EMAC0PHYSYNCACQSTATUS_GlitchData, OutSignalName => "EMAC0PHYSYNCACQSTATUS", OutTemp => EMAC0PHYSYNCACQSTATUS_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARDISPMODE, GlitchData => EMAC0PHYTXCHARDISPMODE_GlitchData, OutSignalName => "EMAC0PHYTXCHARDISPMODE", OutTemp => EMAC0PHYTXCHARDISPMODE_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARDISPMODE, GlitchData => EMAC0PHYTXCHARDISPMODE_GlitchData, OutSignalName => "EMAC0PHYTXCHARDISPMODE", OutTemp => EMAC0PHYTXCHARDISPMODE_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARDISPMODE, GlitchData => EMAC0PHYTXCHARDISPMODE_GlitchData, OutSignalName => "EMAC0PHYTXCHARDISPMODE", OutTemp => EMAC0PHYTXCHARDISPMODE_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARDISPVAL, GlitchData => EMAC0PHYTXCHARDISPVAL_GlitchData, OutSignalName => "EMAC0PHYTXCHARDISPVAL", OutTemp => EMAC0PHYTXCHARDISPVAL_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARDISPVAL, GlitchData => EMAC0PHYTXCHARDISPVAL_GlitchData, OutSignalName => "EMAC0PHYTXCHARDISPVAL", OutTemp => EMAC0PHYTXCHARDISPVAL_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARDISPVAL, GlitchData => EMAC0PHYTXCHARDISPVAL_GlitchData, OutSignalName => "EMAC0PHYTXCHARDISPVAL", OutTemp => EMAC0PHYTXCHARDISPVAL_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARISK, GlitchData => EMAC0PHYTXCHARISK_GlitchData, OutSignalName => "EMAC0PHYTXCHARISK", OutTemp => EMAC0PHYTXCHARISK_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARISK, GlitchData => EMAC0PHYTXCHARISK_GlitchData, OutSignalName => "EMAC0PHYTXCHARISK", OutTemp => EMAC0PHYTXCHARISK_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCHARISK, GlitchData => EMAC0PHYTXCHARISK_GlitchData, OutSignalName => "EMAC0PHYTXCHARISK", OutTemp => EMAC0PHYTXCHARISK_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCLK, GlitchData => EMAC0PHYTXCLK_GlitchData, OutSignalName => "EMAC0PHYTXCLK", OutTemp => EMAC0PHYTXCLK_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCLK, GlitchData => EMAC0PHYTXCLK_GlitchData, OutSignalName => "EMAC0PHYTXCLK", OutTemp => EMAC0PHYTXCLK_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXCLK, GlitchData => EMAC0PHYTXCLK_GlitchData, OutSignalName => "EMAC0PHYTXCLK", OutTemp => EMAC0PHYTXCLK_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(0), GlitchData => EMAC0PHYTXD0_GlitchData, OutSignalName => "EMAC0PHYTXD(0)", OutTemp => EMAC0PHYTXD_OUT(0), Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(0), GlitchData => EMAC0PHYTXD0_GlitchData, OutSignalName => "EMAC0PHYTXD(0)", OutTemp => EMAC0PHYTXD_OUT(0), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(0), GlitchData => EMAC0PHYTXD0_GlitchData, OutSignalName => "EMAC0PHYTXD(0)", OutTemp => EMAC0PHYTXD_OUT(0), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(1), GlitchData => EMAC0PHYTXD1_GlitchData, OutSignalName => "EMAC0PHYTXD(1)", OutTemp => EMAC0PHYTXD_OUT(1), Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(1), GlitchData => EMAC0PHYTXD1_GlitchData, OutSignalName => "EMAC0PHYTXD(1)", OutTemp => EMAC0PHYTXD_OUT(1), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(1), GlitchData => EMAC0PHYTXD1_GlitchData, OutSignalName => "EMAC0PHYTXD(1)", OutTemp => EMAC0PHYTXD_OUT(1), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(2), GlitchData => EMAC0PHYTXD2_GlitchData, OutSignalName => "EMAC0PHYTXD(2)", OutTemp => EMAC0PHYTXD_OUT(2), Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(2), GlitchData => EMAC0PHYTXD2_GlitchData, OutSignalName => "EMAC0PHYTXD(2)", OutTemp => EMAC0PHYTXD_OUT(2), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(2), GlitchData => EMAC0PHYTXD2_GlitchData, OutSignalName => "EMAC0PHYTXD(2)", OutTemp => EMAC0PHYTXD_OUT(2), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(3), GlitchData => EMAC0PHYTXD3_GlitchData, OutSignalName => "EMAC0PHYTXD(3)", OutTemp => EMAC0PHYTXD_OUT(3), Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(3), GlitchData => EMAC0PHYTXD3_GlitchData, OutSignalName => "EMAC0PHYTXD(3)", OutTemp => EMAC0PHYTXD_OUT(3), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(3), GlitchData => EMAC0PHYTXD3_GlitchData, OutSignalName => "EMAC0PHYTXD(3)", OutTemp => EMAC0PHYTXD_OUT(3), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(4), GlitchData => EMAC0PHYTXD4_GlitchData, OutSignalName => "EMAC0PHYTXD(4)", OutTemp => EMAC0PHYTXD_OUT(4), Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(4), GlitchData => EMAC0PHYTXD4_GlitchData, OutSignalName => "EMAC0PHYTXD(4)", OutTemp => EMAC0PHYTXD_OUT(4), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(4), GlitchData => EMAC0PHYTXD4_GlitchData, OutSignalName => "EMAC0PHYTXD(4)", OutTemp => EMAC0PHYTXD_OUT(4), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(4), GlitchData => EMAC0PHYTXD4_GlitchData, OutSignalName => "EMAC0PHYTXD(4)", OutTemp => EMAC0PHYTXD_OUT(4), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(5), GlitchData => EMAC0PHYTXD5_GlitchData, OutSignalName => "EMAC0PHYTXD(5)", OutTemp => EMAC0PHYTXD_OUT(5), Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(5), GlitchData => EMAC0PHYTXD5_GlitchData, OutSignalName => "EMAC0PHYTXD(5)", OutTemp => EMAC0PHYTXD_OUT(5), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(5), GlitchData => EMAC0PHYTXD5_GlitchData, OutSignalName => "EMAC0PHYTXD(5)", OutTemp => EMAC0PHYTXD_OUT(5), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(5), GlitchData => EMAC0PHYTXD5_GlitchData, OutSignalName => "EMAC0PHYTXD(5)", OutTemp => EMAC0PHYTXD_OUT(5), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(6), GlitchData => EMAC0PHYTXD6_GlitchData, OutSignalName => "EMAC0PHYTXD(6)", OutTemp => EMAC0PHYTXD_OUT(6), Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(6), GlitchData => EMAC0PHYTXD6_GlitchData, OutSignalName => "EMAC0PHYTXD(6)", OutTemp => EMAC0PHYTXD_OUT(6), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(6), GlitchData => EMAC0PHYTXD6_GlitchData, OutSignalName => "EMAC0PHYTXD(6)", OutTemp => EMAC0PHYTXD_OUT(6), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(6), GlitchData => EMAC0PHYTXD6_GlitchData, OutSignalName => "EMAC0PHYTXD(6)", OutTemp => EMAC0PHYTXD_OUT(6), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(7), GlitchData => EMAC0PHYTXD7_GlitchData, OutSignalName => "EMAC0PHYTXD(7)", OutTemp => EMAC0PHYTXD_OUT(7), Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(7), GlitchData => EMAC0PHYTXD7_GlitchData, OutSignalName => "EMAC0PHYTXD(7)", OutTemp => EMAC0PHYTXD_OUT(7), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(7), GlitchData => EMAC0PHYTXD7_GlitchData, OutSignalName => "EMAC0PHYTXD(7)", OutTemp => EMAC0PHYTXD_OUT(7), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXD(7), GlitchData => EMAC0PHYTXD7_GlitchData, OutSignalName => "EMAC0PHYTXD(7)", OutTemp => EMAC0PHYTXD_OUT(7), Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXEN, GlitchData => EMAC0PHYTXEN_GlitchData, OutSignalName => "EMAC0PHYTXEN", OutTemp => EMAC0PHYTXEN_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXEN, GlitchData => EMAC0PHYTXEN_GlitchData, OutSignalName => "EMAC0PHYTXEN", OutTemp => EMAC0PHYTXEN_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXEN, GlitchData => EMAC0PHYTXEN_GlitchData, OutSignalName => "EMAC0PHYTXEN", OutTemp => EMAC0PHYTXEN_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXER, GlitchData => EMAC0PHYTXER_GlitchData, OutSignalName => "EMAC0PHYTXER", OutTemp => EMAC0PHYTXER_OUT, Paths => (0 => (PHYEMAC0GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXER, GlitchData => EMAC0PHYTXER_GlitchData, OutSignalName => "EMAC0PHYTXER", OutTemp => EMAC0PHYTXER_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXER, GlitchData => EMAC0PHYTXER_GlitchData, OutSignalName => "EMAC0PHYTXER", OutTemp => EMAC0PHYTXER_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0PHYTXER, GlitchData => EMAC0PHYTXER_GlitchData, OutSignalName => "EMAC0PHYTXER", OutTemp => EMAC0PHYTXER_OUT, Paths => (0 => (PHYEMAC0TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC0SPEEDIS10100, GlitchData => EMAC0SPEEDIS10100_GlitchData, OutSignalName => "EMAC0SPEEDIS10100", OutTemp => EMAC0SPEEDIS10100_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTANINTERRUPT, GlitchData => EMAC1CLIENTANINTERRUPT_GlitchData, OutSignalName => "EMAC1CLIENTANINTERRUPT", OutTemp => EMAC1CLIENTANINTERRUPT_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXBADFRAME, GlitchData => EMAC1CLIENTRXBADFRAME_GlitchData, OutSignalName => "EMAC1CLIENTRXBADFRAME", OutTemp => EMAC1CLIENTRXBADFRAME_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXBADFRAME, GlitchData => EMAC1CLIENTRXBADFRAME_GlitchData, OutSignalName => "EMAC1CLIENTRXBADFRAME", OutTemp => EMAC1CLIENTRXBADFRAME_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXBADFRAME, GlitchData => EMAC1CLIENTRXBADFRAME_GlitchData, OutSignalName => "EMAC1CLIENTRXBADFRAME", OutTemp => EMAC1CLIENTRXBADFRAME_OUT, Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXCLIENTCLKOUT, GlitchData => EMAC1CLIENTRXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC1CLIENTRXCLIENTCLKOUT", OutTemp => EMAC1CLIENTRXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(0), GlitchData => EMAC1CLIENTRXD0_GlitchData, OutSignalName => "EMAC1CLIENTRXD(0)", OutTemp => EMAC1CLIENTRXD_OUT(0), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(0), GlitchData => EMAC1CLIENTRXD0_GlitchData, OutSignalName => "EMAC1CLIENTRXD(0)", OutTemp => EMAC1CLIENTRXD_OUT(0), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(0), GlitchData => EMAC1CLIENTRXD0_GlitchData, OutSignalName => "EMAC1CLIENTRXD(0)", OutTemp => EMAC1CLIENTRXD_OUT(0), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(1), GlitchData => EMAC1CLIENTRXD1_GlitchData, OutSignalName => "EMAC1CLIENTRXD(1)", OutTemp => EMAC1CLIENTRXD_OUT(1), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(1), GlitchData => EMAC1CLIENTRXD1_GlitchData, OutSignalName => "EMAC1CLIENTRXD(1)", OutTemp => EMAC1CLIENTRXD_OUT(1), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(1), GlitchData => EMAC1CLIENTRXD1_GlitchData, OutSignalName => "EMAC1CLIENTRXD(1)", OutTemp => EMAC1CLIENTRXD_OUT(1), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(2), GlitchData => EMAC1CLIENTRXD2_GlitchData, OutSignalName => "EMAC1CLIENTRXD(2)", OutTemp => EMAC1CLIENTRXD_OUT(2), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(2), GlitchData => EMAC1CLIENTRXD2_GlitchData, OutSignalName => "EMAC1CLIENTRXD(2)", OutTemp => EMAC1CLIENTRXD_OUT(2), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(2), GlitchData => EMAC1CLIENTRXD2_GlitchData, OutSignalName => "EMAC1CLIENTRXD(2)", OutTemp => EMAC1CLIENTRXD_OUT(2), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(3), GlitchData => EMAC1CLIENTRXD3_GlitchData, OutSignalName => "EMAC1CLIENTRXD(3)", OutTemp => EMAC1CLIENTRXD_OUT(3), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(3), GlitchData => EMAC1CLIENTRXD3_GlitchData, OutSignalName => "EMAC1CLIENTRXD(3)", OutTemp => EMAC1CLIENTRXD_OUT(3), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(3), GlitchData => EMAC1CLIENTRXD3_GlitchData, OutSignalName => "EMAC1CLIENTRXD(3)", OutTemp => EMAC1CLIENTRXD_OUT(3), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(4), GlitchData => EMAC1CLIENTRXD4_GlitchData, OutSignalName => "EMAC1CLIENTRXD(4)", OutTemp => EMAC1CLIENTRXD_OUT(4), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(4), GlitchData => EMAC1CLIENTRXD4_GlitchData, OutSignalName => "EMAC1CLIENTRXD(4)", OutTemp => EMAC1CLIENTRXD_OUT(4), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(4), GlitchData => EMAC1CLIENTRXD4_GlitchData, OutSignalName => "EMAC1CLIENTRXD(4)", OutTemp => EMAC1CLIENTRXD_OUT(4), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(5), GlitchData => EMAC1CLIENTRXD5_GlitchData, OutSignalName => "EMAC1CLIENTRXD(5)", OutTemp => EMAC1CLIENTRXD_OUT(5), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(5), GlitchData => EMAC1CLIENTRXD5_GlitchData, OutSignalName => "EMAC1CLIENTRXD(5)", OutTemp => EMAC1CLIENTRXD_OUT(5), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(5), GlitchData => EMAC1CLIENTRXD5_GlitchData, OutSignalName => "EMAC1CLIENTRXD(5)", OutTemp => EMAC1CLIENTRXD_OUT(5), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(6), GlitchData => EMAC1CLIENTRXD6_GlitchData, OutSignalName => "EMAC1CLIENTRXD(6)", OutTemp => EMAC1CLIENTRXD_OUT(6), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(6), GlitchData => EMAC1CLIENTRXD6_GlitchData, OutSignalName => "EMAC1CLIENTRXD(6)", OutTemp => EMAC1CLIENTRXD_OUT(6), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(6), GlitchData => EMAC1CLIENTRXD6_GlitchData, OutSignalName => "EMAC1CLIENTRXD(6)", OutTemp => EMAC1CLIENTRXD_OUT(6), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(7), GlitchData => EMAC1CLIENTRXD7_GlitchData, OutSignalName => "EMAC1CLIENTRXD(7)", OutTemp => EMAC1CLIENTRXD_OUT(7), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(7), GlitchData => EMAC1CLIENTRXD7_GlitchData, OutSignalName => "EMAC1CLIENTRXD(7)", OutTemp => EMAC1CLIENTRXD_OUT(7), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(7), GlitchData => EMAC1CLIENTRXD7_GlitchData, OutSignalName => "EMAC1CLIENTRXD(7)", OutTemp => EMAC1CLIENTRXD_OUT(7), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(8), GlitchData => EMAC1CLIENTRXD8_GlitchData, OutSignalName => "EMAC1CLIENTRXD(8)", OutTemp => EMAC1CLIENTRXD_OUT(8), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(8), GlitchData => EMAC1CLIENTRXD8_GlitchData, OutSignalName => "EMAC1CLIENTRXD(8)", OutTemp => EMAC1CLIENTRXD_OUT(8), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(8), GlitchData => EMAC1CLIENTRXD8_GlitchData, OutSignalName => "EMAC1CLIENTRXD(8)", OutTemp => EMAC1CLIENTRXD_OUT(8), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(9), GlitchData => EMAC1CLIENTRXD9_GlitchData, OutSignalName => "EMAC1CLIENTRXD(9)", OutTemp => EMAC1CLIENTRXD_OUT(9), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(9), GlitchData => EMAC1CLIENTRXD9_GlitchData, OutSignalName => "EMAC1CLIENTRXD(9)", OutTemp => EMAC1CLIENTRXD_OUT(9), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(9), GlitchData => EMAC1CLIENTRXD9_GlitchData, OutSignalName => "EMAC1CLIENTRXD(9)", OutTemp => EMAC1CLIENTRXD_OUT(9), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(10), GlitchData => EMAC1CLIENTRXD10_GlitchData, OutSignalName => "EMAC1CLIENTRXD(10)", OutTemp => EMAC1CLIENTRXD_OUT(10), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(10), GlitchData => EMAC1CLIENTRXD10_GlitchData, OutSignalName => "EMAC1CLIENTRXD(10)", OutTemp => EMAC1CLIENTRXD_OUT(10), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(10), GlitchData => EMAC1CLIENTRXD10_GlitchData, OutSignalName => "EMAC1CLIENTRXD(10)", OutTemp => EMAC1CLIENTRXD_OUT(10), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(11), GlitchData => EMAC1CLIENTRXD11_GlitchData, OutSignalName => "EMAC1CLIENTRXD(11)", OutTemp => EMAC1CLIENTRXD_OUT(11), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(11), GlitchData => EMAC1CLIENTRXD11_GlitchData, OutSignalName => "EMAC1CLIENTRXD(11)", OutTemp => EMAC1CLIENTRXD_OUT(11), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(11), GlitchData => EMAC1CLIENTRXD11_GlitchData, OutSignalName => "EMAC1CLIENTRXD(11)", OutTemp => EMAC1CLIENTRXD_OUT(11), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(12), GlitchData => EMAC1CLIENTRXD12_GlitchData, OutSignalName => "EMAC1CLIENTRXD(12)", OutTemp => EMAC1CLIENTRXD_OUT(12), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(12), GlitchData => EMAC1CLIENTRXD12_GlitchData, OutSignalName => "EMAC1CLIENTRXD(12)", OutTemp => EMAC1CLIENTRXD_OUT(12), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(12), GlitchData => EMAC1CLIENTRXD12_GlitchData, OutSignalName => "EMAC1CLIENTRXD(12)", OutTemp => EMAC1CLIENTRXD_OUT(12), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(13), GlitchData => EMAC1CLIENTRXD13_GlitchData, OutSignalName => "EMAC1CLIENTRXD(13)", OutTemp => EMAC1CLIENTRXD_OUT(13), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(13), GlitchData => EMAC1CLIENTRXD13_GlitchData, OutSignalName => "EMAC1CLIENTRXD(13)", OutTemp => EMAC1CLIENTRXD_OUT(13), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(13), GlitchData => EMAC1CLIENTRXD13_GlitchData, OutSignalName => "EMAC1CLIENTRXD(13)", OutTemp => EMAC1CLIENTRXD_OUT(13), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(14), GlitchData => EMAC1CLIENTRXD14_GlitchData, OutSignalName => "EMAC1CLIENTRXD(14)", OutTemp => EMAC1CLIENTRXD_OUT(14), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(14), GlitchData => EMAC1CLIENTRXD14_GlitchData, OutSignalName => "EMAC1CLIENTRXD(14)", OutTemp => EMAC1CLIENTRXD_OUT(14), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(14), GlitchData => EMAC1CLIENTRXD14_GlitchData, OutSignalName => "EMAC1CLIENTRXD(14)", OutTemp => EMAC1CLIENTRXD_OUT(14), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(15), GlitchData => EMAC1CLIENTRXD15_GlitchData, OutSignalName => "EMAC1CLIENTRXD(15)", OutTemp => EMAC1CLIENTRXD_OUT(15), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(15), GlitchData => EMAC1CLIENTRXD15_GlitchData, OutSignalName => "EMAC1CLIENTRXD(15)", OutTemp => EMAC1CLIENTRXD_OUT(15), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXD(15), GlitchData => EMAC1CLIENTRXD15_GlitchData, OutSignalName => "EMAC1CLIENTRXD(15)", OutTemp => EMAC1CLIENTRXD_OUT(15), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXDVLD, GlitchData => EMAC1CLIENTRXDVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXDVLD", OutTemp => EMAC1CLIENTRXDVLD_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXDVLD, GlitchData => EMAC1CLIENTRXDVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXDVLD", OutTemp => EMAC1CLIENTRXDVLD_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXDVLD, GlitchData => EMAC1CLIENTRXDVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXDVLD", OutTemp => EMAC1CLIENTRXDVLD_OUT, Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXDVLDMSW, GlitchData => EMAC1CLIENTRXDVLDMSW_GlitchData, OutSignalName => "EMAC1CLIENTRXDVLDMSW", OutTemp => EMAC1CLIENTRXDVLDMSW_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXDVLDMSW, GlitchData => EMAC1CLIENTRXDVLDMSW_GlitchData, OutSignalName => "EMAC1CLIENTRXDVLDMSW", OutTemp => EMAC1CLIENTRXDVLDMSW_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXDVLDMSW, GlitchData => EMAC1CLIENTRXDVLDMSW_GlitchData, OutSignalName => "EMAC1CLIENTRXDVLDMSW", OutTemp => EMAC1CLIENTRXDVLDMSW_OUT, Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXFRAMEDROP, GlitchData => EMAC1CLIENTRXFRAMEDROP_GlitchData, OutSignalName => "EMAC1CLIENTRXFRAMEDROP", OutTemp => EMAC1CLIENTRXFRAMEDROP_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXFRAMEDROP, GlitchData => EMAC1CLIENTRXFRAMEDROP_GlitchData, OutSignalName => "EMAC1CLIENTRXFRAMEDROP", OutTemp => EMAC1CLIENTRXFRAMEDROP_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXFRAMEDROP, GlitchData => EMAC1CLIENTRXFRAMEDROP_GlitchData, OutSignalName => "EMAC1CLIENTRXFRAMEDROP", OutTemp => EMAC1CLIENTRXFRAMEDROP_OUT, Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXGOODFRAME, GlitchData => EMAC1CLIENTRXGOODFRAME_GlitchData, OutSignalName => "EMAC1CLIENTRXGOODFRAME", OutTemp => EMAC1CLIENTRXGOODFRAME_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXGOODFRAME, GlitchData => EMAC1CLIENTRXGOODFRAME_GlitchData, OutSignalName => "EMAC1CLIENTRXGOODFRAME", OutTemp => EMAC1CLIENTRXGOODFRAME_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXGOODFRAME, GlitchData => EMAC1CLIENTRXGOODFRAME_GlitchData, OutSignalName => "EMAC1CLIENTRXGOODFRAME", OutTemp => EMAC1CLIENTRXGOODFRAME_OUT, Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(0), GlitchData => EMAC1CLIENTRXSTATS0_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(0)", OutTemp => EMAC1CLIENTRXSTATS_OUT(0), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(0), GlitchData => EMAC1CLIENTRXSTATS0_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(0)", OutTemp => EMAC1CLIENTRXSTATS_OUT(0), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(0), GlitchData => EMAC1CLIENTRXSTATS0_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(0)", OutTemp => EMAC1CLIENTRXSTATS_OUT(0), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(1), GlitchData => EMAC1CLIENTRXSTATS1_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(1)", OutTemp => EMAC1CLIENTRXSTATS_OUT(1), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(1), GlitchData => EMAC1CLIENTRXSTATS1_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(1)", OutTemp => EMAC1CLIENTRXSTATS_OUT(1), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(1), GlitchData => EMAC1CLIENTRXSTATS1_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(1)", OutTemp => EMAC1CLIENTRXSTATS_OUT(1), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(2), GlitchData => EMAC1CLIENTRXSTATS2_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(2)", OutTemp => EMAC1CLIENTRXSTATS_OUT(2), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(2), GlitchData => EMAC1CLIENTRXSTATS2_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(2)", OutTemp => EMAC1CLIENTRXSTATS_OUT(2), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(2), GlitchData => EMAC1CLIENTRXSTATS2_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(2)", OutTemp => EMAC1CLIENTRXSTATS_OUT(2), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(3), GlitchData => EMAC1CLIENTRXSTATS3_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(3)", OutTemp => EMAC1CLIENTRXSTATS_OUT(3), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(3), GlitchData => EMAC1CLIENTRXSTATS3_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(3)", OutTemp => EMAC1CLIENTRXSTATS_OUT(3), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(3), GlitchData => EMAC1CLIENTRXSTATS3_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(3)", OutTemp => EMAC1CLIENTRXSTATS_OUT(3), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(4), GlitchData => EMAC1CLIENTRXSTATS4_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(4)", OutTemp => EMAC1CLIENTRXSTATS_OUT(4), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(4), GlitchData => EMAC1CLIENTRXSTATS4_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(4)", OutTemp => EMAC1CLIENTRXSTATS_OUT(4), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(4), GlitchData => EMAC1CLIENTRXSTATS4_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(4)", OutTemp => EMAC1CLIENTRXSTATS_OUT(4), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(5), GlitchData => EMAC1CLIENTRXSTATS5_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(5)", OutTemp => EMAC1CLIENTRXSTATS_OUT(5), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(5), GlitchData => EMAC1CLIENTRXSTATS5_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(5)", OutTemp => EMAC1CLIENTRXSTATS_OUT(5), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(5), GlitchData => EMAC1CLIENTRXSTATS5_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(5)", OutTemp => EMAC1CLIENTRXSTATS_OUT(5), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(6), GlitchData => EMAC1CLIENTRXSTATS6_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(6)", OutTemp => EMAC1CLIENTRXSTATS_OUT(6), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(6), GlitchData => EMAC1CLIENTRXSTATS6_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(6)", OutTemp => EMAC1CLIENTRXSTATS_OUT(6), Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATS(6), GlitchData => EMAC1CLIENTRXSTATS6_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATS(6)", OutTemp => EMAC1CLIENTRXSTATS_OUT(6), Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATSBYTEVLD, GlitchData => EMAC1CLIENTRXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATSBYTEVLD", OutTemp => EMAC1CLIENTRXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATSBYTEVLD, GlitchData => EMAC1CLIENTRXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATSBYTEVLD", OutTemp => EMAC1CLIENTRXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATSBYTEVLD, GlitchData => EMAC1CLIENTRXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATSBYTEVLD", OutTemp => EMAC1CLIENTRXSTATSBYTEVLD_OUT, Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATSVLD, GlitchData => EMAC1CLIENTRXSTATSVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATSVLD", OutTemp => EMAC1CLIENTRXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATSVLD, GlitchData => EMAC1CLIENTRXSTATSVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATSVLD", OutTemp => EMAC1CLIENTRXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC1RXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTRXSTATSVLD, GlitchData => EMAC1CLIENTRXSTATSVLD_GlitchData, OutSignalName => "EMAC1CLIENTRXSTATSVLD", OutTemp => EMAC1CLIENTRXSTATSVLD_OUT, Paths => (0 => (PHYEMAC1RXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXACK, GlitchData => EMAC1CLIENTTXACK_GlitchData, OutSignalName => "EMAC1CLIENTTXACK", OutTemp => EMAC1CLIENTTXACK_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXACK, GlitchData => EMAC1CLIENTTXACK_GlitchData, OutSignalName => "EMAC1CLIENTTXACK", OutTemp => EMAC1CLIENTTXACK_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXACK, GlitchData => EMAC1CLIENTTXACK_GlitchData, OutSignalName => "EMAC1CLIENTTXACK", OutTemp => EMAC1CLIENTTXACK_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXCLIENTCLKOUT, GlitchData => EMAC1CLIENTTXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC1CLIENTTXCLIENTCLKOUT", OutTemp => EMAC1CLIENTTXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXCLIENTCLKOUT, GlitchData => EMAC1CLIENTTXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC1CLIENTTXCLIENTCLKOUT", OutTemp => EMAC1CLIENTTXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC1MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXCLIENTCLKOUT, GlitchData => EMAC1CLIENTTXCLIENTCLKOUT_GlitchData, OutSignalName => "EMAC1CLIENTTXCLIENTCLKOUT", OutTemp => EMAC1CLIENTTXCLIENTCLKOUT_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXCOLLISION, GlitchData => EMAC1CLIENTTXCOLLISION_GlitchData, OutSignalName => "EMAC1CLIENTTXCOLLISION", OutTemp => EMAC1CLIENTTXCOLLISION_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXCOLLISION, GlitchData => EMAC1CLIENTTXCOLLISION_GlitchData, OutSignalName => "EMAC1CLIENTTXCOLLISION", OutTemp => EMAC1CLIENTTXCOLLISION_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXCOLLISION, GlitchData => EMAC1CLIENTTXCOLLISION_GlitchData, OutSignalName => "EMAC1CLIENTTXCOLLISION", OutTemp => EMAC1CLIENTTXCOLLISION_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXGMIIMIICLKOUT, GlitchData => EMAC1PHYTXGMIIMIICLKOUT_GlitchData, OutSignalName => "EMAC1PHYTXGMIIMIICLKOUT", OutTemp => EMAC1PHYTXGMIIMIICLKOUT_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXGMIIMIICLKOUT, GlitchData => EMAC1PHYTXGMIIMIICLKOUT_GlitchData, OutSignalName => "EMAC1PHYTXGMIIMIICLKOUT", OutTemp => EMAC1PHYTXGMIIMIICLKOUT_OUT, Paths => (0 => (PHYEMAC1MIITXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXRETRANSMIT, GlitchData => EMAC1CLIENTTXRETRANSMIT_GlitchData, OutSignalName => "EMAC1CLIENTTXRETRANSMIT", OutTemp => EMAC1CLIENTTXRETRANSMIT_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXRETRANSMIT, GlitchData => EMAC1CLIENTTXRETRANSMIT_GlitchData, OutSignalName => "EMAC1CLIENTTXRETRANSMIT", OutTemp => EMAC1CLIENTTXRETRANSMIT_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXRETRANSMIT, GlitchData => EMAC1CLIENTTXRETRANSMIT_GlitchData, OutSignalName => "EMAC1CLIENTTXRETRANSMIT", OutTemp => EMAC1CLIENTTXRETRANSMIT_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATS, GlitchData => EMAC1CLIENTTXSTATS_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATS", OutTemp => EMAC1CLIENTTXSTATS_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATS, GlitchData => EMAC1CLIENTTXSTATS_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATS", OutTemp => EMAC1CLIENTTXSTATS_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATS, GlitchData => EMAC1CLIENTTXSTATS_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATS", OutTemp => EMAC1CLIENTTXSTATS_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATSBYTEVLD, GlitchData => EMAC1CLIENTTXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATSBYTEVLD", OutTemp => EMAC1CLIENTTXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATSBYTEVLD, GlitchData => EMAC1CLIENTTXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATSBYTEVLD", OutTemp => EMAC1CLIENTTXSTATSBYTEVLD_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATSBYTEVLD, GlitchData => EMAC1CLIENTTXSTATSBYTEVLD_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATSBYTEVLD", OutTemp => EMAC1CLIENTTXSTATSBYTEVLD_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATSVLD, GlitchData => EMAC1CLIENTTXSTATSVLD_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATSVLD", OutTemp => EMAC1CLIENTTXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATSVLD, GlitchData => EMAC1CLIENTTXSTATSVLD_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATSVLD", OutTemp => EMAC1CLIENTTXSTATSVLD_OUT, Paths => (0 => (CLIENTEMAC1TXCLIENTCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1CLIENTTXSTATSVLD, GlitchData => EMAC1CLIENTTXSTATSVLD_GlitchData, OutSignalName => "EMAC1CLIENTTXSTATSVLD", OutTemp => EMAC1CLIENTTXSTATSVLD_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYENCOMMAALIGN, GlitchData => EMAC1PHYENCOMMAALIGN_GlitchData, OutSignalName => "EMAC1PHYENCOMMAALIGN", OutTemp => EMAC1PHYENCOMMAALIGN_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYLOOPBACKMSB, GlitchData => EMAC1PHYLOOPBACKMSB_GlitchData, OutSignalName => "EMAC1PHYLOOPBACKMSB", OutTemp => EMAC1PHYLOOPBACKMSB_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMCLKOUT, GlitchData => EMAC1PHYMCLKOUT_GlitchData, OutSignalName => "EMAC1PHYMCLKOUT", OutTemp => EMAC1PHYMCLKOUT_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMCLKOUT, GlitchData => EMAC1PHYMCLKOUT_GlitchData, OutSignalName => "EMAC1PHYMCLKOUT", OutTemp => EMAC1PHYMCLKOUT_OUT, Paths => (0 => (PHYEMAC1MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMDOUT, GlitchData => EMAC1PHYMDOUT_GlitchData, OutSignalName => "EMAC1PHYMDOUT", OutTemp => EMAC1PHYMDOUT_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMDOUT, GlitchData => EMAC1PHYMDOUT_GlitchData, OutSignalName => "EMAC1PHYMDOUT", OutTemp => EMAC1PHYMDOUT_OUT, Paths => (0 => (PHYEMAC1MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMDTRI, GlitchData => EMAC1PHYMDTRI_GlitchData, OutSignalName => "EMAC1PHYMDTRI", OutTemp => EMAC1PHYMDTRI_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMDTRI, GlitchData => EMAC1PHYMDTRI_GlitchData, OutSignalName => "EMAC1PHYMDTRI", OutTemp => EMAC1PHYMDTRI_OUT, Paths => (0 => (PHYEMAC1MCLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMGTRXRESET, GlitchData => EMAC1PHYMGTRXRESET_GlitchData, OutSignalName => "EMAC1PHYMGTRXRESET", OutTemp => EMAC1PHYMGTRXRESET_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYMGTTXRESET, GlitchData => EMAC1PHYMGTTXRESET_GlitchData, OutSignalName => "EMAC1PHYMGTTXRESET", OutTemp => EMAC1PHYMGTTXRESET_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYPOWERDOWN, GlitchData => EMAC1PHYPOWERDOWN_GlitchData, OutSignalName => "EMAC1PHYPOWERDOWN", OutTemp => EMAC1PHYPOWERDOWN_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYSYNCACQSTATUS, GlitchData => EMAC1PHYSYNCACQSTATUS_GlitchData, OutSignalName => "EMAC1PHYSYNCACQSTATUS", OutTemp => EMAC1PHYSYNCACQSTATUS_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYSYNCACQSTATUS, GlitchData => EMAC1PHYSYNCACQSTATUS_GlitchData, OutSignalName => "EMAC1PHYSYNCACQSTATUS", OutTemp => EMAC1PHYSYNCACQSTATUS_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYSYNCACQSTATUS, GlitchData => EMAC1PHYSYNCACQSTATUS_GlitchData, OutSignalName => "EMAC1PHYSYNCACQSTATUS", OutTemp => EMAC1PHYSYNCACQSTATUS_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARDISPMODE, GlitchData => EMAC1PHYTXCHARDISPMODE_GlitchData, OutSignalName => "EMAC1PHYTXCHARDISPMODE", OutTemp => EMAC1PHYTXCHARDISPMODE_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARDISPMODE, GlitchData => EMAC1PHYTXCHARDISPMODE_GlitchData, OutSignalName => "EMAC1PHYTXCHARDISPMODE", OutTemp => EMAC1PHYTXCHARDISPMODE_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARDISPMODE, GlitchData => EMAC1PHYTXCHARDISPMODE_GlitchData, OutSignalName => "EMAC1PHYTXCHARDISPMODE", OutTemp => EMAC1PHYTXCHARDISPMODE_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARDISPVAL, GlitchData => EMAC1PHYTXCHARDISPVAL_GlitchData, OutSignalName => "EMAC1PHYTXCHARDISPVAL", OutTemp => EMAC1PHYTXCHARDISPVAL_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARDISPVAL, GlitchData => EMAC1PHYTXCHARDISPVAL_GlitchData, OutSignalName => "EMAC1PHYTXCHARDISPVAL", OutTemp => EMAC1PHYTXCHARDISPVAL_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARDISPVAL, GlitchData => EMAC1PHYTXCHARDISPVAL_GlitchData, OutSignalName => "EMAC1PHYTXCHARDISPVAL", OutTemp => EMAC1PHYTXCHARDISPVAL_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARISK, GlitchData => EMAC1PHYTXCHARISK_GlitchData, OutSignalName => "EMAC1PHYTXCHARISK", OutTemp => EMAC1PHYTXCHARISK_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARISK, GlitchData => EMAC1PHYTXCHARISK_GlitchData, OutSignalName => "EMAC1PHYTXCHARISK", OutTemp => EMAC1PHYTXCHARISK_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCHARISK, GlitchData => EMAC1PHYTXCHARISK_GlitchData, OutSignalName => "EMAC1PHYTXCHARISK", OutTemp => EMAC1PHYTXCHARISK_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCLK, GlitchData => EMAC1PHYTXCLK_GlitchData, OutSignalName => "EMAC1PHYTXCLK", OutTemp => EMAC1PHYTXCLK_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCLK, GlitchData => EMAC1PHYTXCLK_GlitchData, OutSignalName => "EMAC1PHYTXCLK", OutTemp => EMAC1PHYTXCLK_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXCLK, GlitchData => EMAC1PHYTXCLK_GlitchData, OutSignalName => "EMAC1PHYTXCLK", OutTemp => EMAC1PHYTXCLK_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(0), GlitchData => EMAC1PHYTXD0_GlitchData, OutSignalName => "EMAC1PHYTXD(0)", OutTemp => EMAC1PHYTXD_OUT(0), Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(0), GlitchData => EMAC1PHYTXD0_GlitchData, OutSignalName => "EMAC1PHYTXD(0)", OutTemp => EMAC1PHYTXD_OUT(0), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(0), GlitchData => EMAC1PHYTXD0_GlitchData, OutSignalName => "EMAC1PHYTXD(0)", OutTemp => EMAC1PHYTXD_OUT(0), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(1), GlitchData => EMAC1PHYTXD1_GlitchData, OutSignalName => "EMAC1PHYTXD(1)", OutTemp => EMAC1PHYTXD_OUT(1), Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(1), GlitchData => EMAC1PHYTXD1_GlitchData, OutSignalName => "EMAC1PHYTXD(1)", OutTemp => EMAC1PHYTXD_OUT(1), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(1), GlitchData => EMAC1PHYTXD1_GlitchData, OutSignalName => "EMAC1PHYTXD(1)", OutTemp => EMAC1PHYTXD_OUT(1), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(2), GlitchData => EMAC1PHYTXD2_GlitchData, OutSignalName => "EMAC1PHYTXD(2)", OutTemp => EMAC1PHYTXD_OUT(2), Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(2), GlitchData => EMAC1PHYTXD2_GlitchData, OutSignalName => "EMAC1PHYTXD(2)", OutTemp => EMAC1PHYTXD_OUT(2), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(2), GlitchData => EMAC1PHYTXD2_GlitchData, OutSignalName => "EMAC1PHYTXD(2)", OutTemp => EMAC1PHYTXD_OUT(2), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(3), GlitchData => EMAC1PHYTXD3_GlitchData, OutSignalName => "EMAC1PHYTXD(3)", OutTemp => EMAC1PHYTXD_OUT(3), Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(3), GlitchData => EMAC1PHYTXD3_GlitchData, OutSignalName => "EMAC1PHYTXD(3)", OutTemp => EMAC1PHYTXD_OUT(3), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(3), GlitchData => EMAC1PHYTXD3_GlitchData, OutSignalName => "EMAC1PHYTXD(3)", OutTemp => EMAC1PHYTXD_OUT(3), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(4), GlitchData => EMAC1PHYTXD4_GlitchData, OutSignalName => "EMAC1PHYTXD(4)", OutTemp => EMAC1PHYTXD_OUT(4), Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(4), GlitchData => EMAC1PHYTXD4_GlitchData, OutSignalName => "EMAC1PHYTXD(4)", OutTemp => EMAC1PHYTXD_OUT(4), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(4), GlitchData => EMAC1PHYTXD4_GlitchData, OutSignalName => "EMAC1PHYTXD(4)", OutTemp => EMAC1PHYTXD_OUT(4), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(4), GlitchData => EMAC1PHYTXD4_GlitchData, OutSignalName => "EMAC1PHYTXD(4)", OutTemp => EMAC1PHYTXD_OUT(4), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(5), GlitchData => EMAC1PHYTXD5_GlitchData, OutSignalName => "EMAC1PHYTXD(5)", OutTemp => EMAC1PHYTXD_OUT(5), Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(5), GlitchData => EMAC1PHYTXD5_GlitchData, OutSignalName => "EMAC1PHYTXD(5)", OutTemp => EMAC1PHYTXD_OUT(5), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(5), GlitchData => EMAC1PHYTXD5_GlitchData, OutSignalName => "EMAC1PHYTXD(5)", OutTemp => EMAC1PHYTXD_OUT(5), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(5), GlitchData => EMAC1PHYTXD5_GlitchData, OutSignalName => "EMAC1PHYTXD(5)", OutTemp => EMAC1PHYTXD_OUT(5), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(6), GlitchData => EMAC1PHYTXD6_GlitchData, OutSignalName => "EMAC1PHYTXD(6)", OutTemp => EMAC1PHYTXD_OUT(6), Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(6), GlitchData => EMAC1PHYTXD6_GlitchData, OutSignalName => "EMAC1PHYTXD(6)", OutTemp => EMAC1PHYTXD_OUT(6), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(6), GlitchData => EMAC1PHYTXD6_GlitchData, OutSignalName => "EMAC1PHYTXD(6)", OutTemp => EMAC1PHYTXD_OUT(6), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(6), GlitchData => EMAC1PHYTXD6_GlitchData, OutSignalName => "EMAC1PHYTXD(6)", OutTemp => EMAC1PHYTXD_OUT(6), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(7), GlitchData => EMAC1PHYTXD7_GlitchData, OutSignalName => "EMAC1PHYTXD(7)", OutTemp => EMAC1PHYTXD_OUT(7), Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(7), GlitchData => EMAC1PHYTXD7_GlitchData, OutSignalName => "EMAC1PHYTXD(7)", OutTemp => EMAC1PHYTXD_OUT(7), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(7), GlitchData => EMAC1PHYTXD7_GlitchData, OutSignalName => "EMAC1PHYTXD(7)", OutTemp => EMAC1PHYTXD_OUT(7), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXD(7), GlitchData => EMAC1PHYTXD7_GlitchData, OutSignalName => "EMAC1PHYTXD(7)", OutTemp => EMAC1PHYTXD_OUT(7), Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXEN, GlitchData => EMAC1PHYTXEN_GlitchData, OutSignalName => "EMAC1PHYTXEN", OutTemp => EMAC1PHYTXEN_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXEN, GlitchData => EMAC1PHYTXEN_GlitchData, OutSignalName => "EMAC1PHYTXEN", OutTemp => EMAC1PHYTXEN_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXEN, GlitchData => EMAC1PHYTXEN_GlitchData, OutSignalName => "EMAC1PHYTXEN", OutTemp => EMAC1PHYTXEN_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXER, GlitchData => EMAC1PHYTXER_GlitchData, OutSignalName => "EMAC1PHYTXER", OutTemp => EMAC1PHYTXER_OUT, Paths => (0 => (PHYEMAC1GTXCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXER, GlitchData => EMAC1PHYTXER_GlitchData, OutSignalName => "EMAC1PHYTXER", OutTemp => EMAC1PHYTXER_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXER, GlitchData => EMAC1PHYTXER_GlitchData, OutSignalName => "EMAC1PHYTXER", OutTemp => EMAC1PHYTXER_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1PHYTXER, GlitchData => EMAC1PHYTXER_GlitchData, OutSignalName => "EMAC1PHYTXER", OutTemp => EMAC1PHYTXER_OUT, Paths => (0 => (PHYEMAC1TXGMIIMIICLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMAC1SPEEDIS10100, GlitchData => EMAC1SPEEDIS10100_GlitchData, OutSignalName => "EMAC1SPEEDIS10100", OutTemp => EMAC1SPEEDIS10100_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRACK, GlitchData => EMACDCRACK_GlitchData, OutSignalName => "EMACDCRACK", OutTemp => EMACDCRACK_OUT, Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(0), GlitchData => EMACDCRDBUS0_GlitchData, OutSignalName => "EMACDCRDBUS(0)", OutTemp => EMACDCRDBUS_OUT(0), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(1), GlitchData => EMACDCRDBUS1_GlitchData, OutSignalName => "EMACDCRDBUS(1)", OutTemp => EMACDCRDBUS_OUT(1), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(2), GlitchData => EMACDCRDBUS2_GlitchData, OutSignalName => "EMACDCRDBUS(2)", OutTemp => EMACDCRDBUS_OUT(2), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(3), GlitchData => EMACDCRDBUS3_GlitchData, OutSignalName => "EMACDCRDBUS(3)", OutTemp => EMACDCRDBUS_OUT(3), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(4), GlitchData => EMACDCRDBUS4_GlitchData, OutSignalName => "EMACDCRDBUS(4)", OutTemp => EMACDCRDBUS_OUT(4), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(5), GlitchData => EMACDCRDBUS5_GlitchData, OutSignalName => "EMACDCRDBUS(5)", OutTemp => EMACDCRDBUS_OUT(5), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(6), GlitchData => EMACDCRDBUS6_GlitchData, OutSignalName => "EMACDCRDBUS(6)", OutTemp => EMACDCRDBUS_OUT(6), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(7), GlitchData => EMACDCRDBUS7_GlitchData, OutSignalName => "EMACDCRDBUS(7)", OutTemp => EMACDCRDBUS_OUT(7), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(8), GlitchData => EMACDCRDBUS8_GlitchData, OutSignalName => "EMACDCRDBUS(8)", OutTemp => EMACDCRDBUS_OUT(8), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(9), GlitchData => EMACDCRDBUS9_GlitchData, OutSignalName => "EMACDCRDBUS(9)", OutTemp => EMACDCRDBUS_OUT(9), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(10), GlitchData => EMACDCRDBUS10_GlitchData, OutSignalName => "EMACDCRDBUS(10)", OutTemp => EMACDCRDBUS_OUT(10), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(11), GlitchData => EMACDCRDBUS11_GlitchData, OutSignalName => "EMACDCRDBUS(11)", OutTemp => EMACDCRDBUS_OUT(11), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(12), GlitchData => EMACDCRDBUS12_GlitchData, OutSignalName => "EMACDCRDBUS(12)", OutTemp => EMACDCRDBUS_OUT(12), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(13), GlitchData => EMACDCRDBUS13_GlitchData, OutSignalName => "EMACDCRDBUS(13)", OutTemp => EMACDCRDBUS_OUT(13), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(14), GlitchData => EMACDCRDBUS14_GlitchData, OutSignalName => "EMACDCRDBUS(14)", OutTemp => EMACDCRDBUS_OUT(14), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(15), GlitchData => EMACDCRDBUS15_GlitchData, OutSignalName => "EMACDCRDBUS(15)", OutTemp => EMACDCRDBUS_OUT(15), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(16), GlitchData => EMACDCRDBUS16_GlitchData, OutSignalName => "EMACDCRDBUS(16)", OutTemp => EMACDCRDBUS_OUT(16), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(17), GlitchData => EMACDCRDBUS17_GlitchData, OutSignalName => "EMACDCRDBUS(17)", OutTemp => EMACDCRDBUS_OUT(17), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(18), GlitchData => EMACDCRDBUS18_GlitchData, OutSignalName => "EMACDCRDBUS(18)", OutTemp => EMACDCRDBUS_OUT(18), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(19), GlitchData => EMACDCRDBUS19_GlitchData, OutSignalName => "EMACDCRDBUS(19)", OutTemp => EMACDCRDBUS_OUT(19), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(20), GlitchData => EMACDCRDBUS20_GlitchData, OutSignalName => "EMACDCRDBUS(20)", OutTemp => EMACDCRDBUS_OUT(20), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(21), GlitchData => EMACDCRDBUS21_GlitchData, OutSignalName => "EMACDCRDBUS(21)", OutTemp => EMACDCRDBUS_OUT(21), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(22), GlitchData => EMACDCRDBUS22_GlitchData, OutSignalName => "EMACDCRDBUS(22)", OutTemp => EMACDCRDBUS_OUT(22), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(23), GlitchData => EMACDCRDBUS23_GlitchData, OutSignalName => "EMACDCRDBUS(23)", OutTemp => EMACDCRDBUS_OUT(23), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(24), GlitchData => EMACDCRDBUS24_GlitchData, OutSignalName => "EMACDCRDBUS(24)", OutTemp => EMACDCRDBUS_OUT(24), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(25), GlitchData => EMACDCRDBUS25_GlitchData, OutSignalName => "EMACDCRDBUS(25)", OutTemp => EMACDCRDBUS_OUT(25), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(26), GlitchData => EMACDCRDBUS26_GlitchData, OutSignalName => "EMACDCRDBUS(26)", OutTemp => EMACDCRDBUS_OUT(26), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(27), GlitchData => EMACDCRDBUS27_GlitchData, OutSignalName => "EMACDCRDBUS(27)", OutTemp => EMACDCRDBUS_OUT(27), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(28), GlitchData => EMACDCRDBUS28_GlitchData, OutSignalName => "EMACDCRDBUS(28)", OutTemp => EMACDCRDBUS_OUT(28), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(29), GlitchData => EMACDCRDBUS29_GlitchData, OutSignalName => "EMACDCRDBUS(29)", OutTemp => EMACDCRDBUS_OUT(29), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(30), GlitchData => EMACDCRDBUS30_GlitchData, OutSignalName => "EMACDCRDBUS(30)", OutTemp => EMACDCRDBUS_OUT(30), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => EMACDCRDBUS(31), GlitchData => EMACDCRDBUS31_GlitchData, OutSignalName => "EMACDCRDBUS(31)", OutTemp => EMACDCRDBUS_OUT(31), Paths => (0 => (DCREMACCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTMIIMRDY, GlitchData => HOSTMIIMRDY_GlitchData, OutSignalName => "HOSTMIIMRDY", OutTemp => HOSTMIIMRDY_OUT, Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(0), GlitchData => HOSTRDDATA0_GlitchData, OutSignalName => "HOSTRDDATA(0)", OutTemp => HOSTRDDATA_OUT(0), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(1), GlitchData => HOSTRDDATA1_GlitchData, OutSignalName => "HOSTRDDATA(1)", OutTemp => HOSTRDDATA_OUT(1), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(2), GlitchData => HOSTRDDATA2_GlitchData, OutSignalName => "HOSTRDDATA(2)", OutTemp => HOSTRDDATA_OUT(2), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(3), GlitchData => HOSTRDDATA3_GlitchData, OutSignalName => "HOSTRDDATA(3)", OutTemp => HOSTRDDATA_OUT(3), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(4), GlitchData => HOSTRDDATA4_GlitchData, OutSignalName => "HOSTRDDATA(4)", OutTemp => HOSTRDDATA_OUT(4), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(5), GlitchData => HOSTRDDATA5_GlitchData, OutSignalName => "HOSTRDDATA(5)", OutTemp => HOSTRDDATA_OUT(5), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(6), GlitchData => HOSTRDDATA6_GlitchData, OutSignalName => "HOSTRDDATA(6)", OutTemp => HOSTRDDATA_OUT(6), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(7), GlitchData => HOSTRDDATA7_GlitchData, OutSignalName => "HOSTRDDATA(7)", OutTemp => HOSTRDDATA_OUT(7), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(8), GlitchData => HOSTRDDATA8_GlitchData, OutSignalName => "HOSTRDDATA(8)", OutTemp => HOSTRDDATA_OUT(8), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(9), GlitchData => HOSTRDDATA9_GlitchData, OutSignalName => "HOSTRDDATA(9)", OutTemp => HOSTRDDATA_OUT(9), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(10), GlitchData => HOSTRDDATA10_GlitchData, OutSignalName => "HOSTRDDATA(10)", OutTemp => HOSTRDDATA_OUT(10), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(11), GlitchData => HOSTRDDATA11_GlitchData, OutSignalName => "HOSTRDDATA(11)", OutTemp => HOSTRDDATA_OUT(11), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(12), GlitchData => HOSTRDDATA12_GlitchData, OutSignalName => "HOSTRDDATA(12)", OutTemp => HOSTRDDATA_OUT(12), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(13), GlitchData => HOSTRDDATA13_GlitchData, OutSignalName => "HOSTRDDATA(13)", OutTemp => HOSTRDDATA_OUT(13), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(14), GlitchData => HOSTRDDATA14_GlitchData, OutSignalName => "HOSTRDDATA(14)", OutTemp => HOSTRDDATA_OUT(14), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(15), GlitchData => HOSTRDDATA15_GlitchData, OutSignalName => "HOSTRDDATA(15)", OutTemp => HOSTRDDATA_OUT(15), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(16), GlitchData => HOSTRDDATA16_GlitchData, OutSignalName => "HOSTRDDATA(16)", OutTemp => HOSTRDDATA_OUT(16), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(17), GlitchData => HOSTRDDATA17_GlitchData, OutSignalName => "HOSTRDDATA(17)", OutTemp => HOSTRDDATA_OUT(17), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(18), GlitchData => HOSTRDDATA18_GlitchData, OutSignalName => "HOSTRDDATA(18)", OutTemp => HOSTRDDATA_OUT(18), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(19), GlitchData => HOSTRDDATA19_GlitchData, OutSignalName => "HOSTRDDATA(19)", OutTemp => HOSTRDDATA_OUT(19), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(20), GlitchData => HOSTRDDATA20_GlitchData, OutSignalName => "HOSTRDDATA(20)", OutTemp => HOSTRDDATA_OUT(20), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(21), GlitchData => HOSTRDDATA21_GlitchData, OutSignalName => "HOSTRDDATA(21)", OutTemp => HOSTRDDATA_OUT(21), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(22), GlitchData => HOSTRDDATA22_GlitchData, OutSignalName => "HOSTRDDATA(22)", OutTemp => HOSTRDDATA_OUT(22), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(23), GlitchData => HOSTRDDATA23_GlitchData, OutSignalName => "HOSTRDDATA(23)", OutTemp => HOSTRDDATA_OUT(23), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(24), GlitchData => HOSTRDDATA24_GlitchData, OutSignalName => "HOSTRDDATA(24)", OutTemp => HOSTRDDATA_OUT(24), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(25), GlitchData => HOSTRDDATA25_GlitchData, OutSignalName => "HOSTRDDATA(25)", OutTemp => HOSTRDDATA_OUT(25), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(26), GlitchData => HOSTRDDATA26_GlitchData, OutSignalName => "HOSTRDDATA(26)", OutTemp => HOSTRDDATA_OUT(26), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(27), GlitchData => HOSTRDDATA27_GlitchData, OutSignalName => "HOSTRDDATA(27)", OutTemp => HOSTRDDATA_OUT(27), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(28), GlitchData => HOSTRDDATA28_GlitchData, OutSignalName => "HOSTRDDATA(28)", OutTemp => HOSTRDDATA_OUT(28), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(29), GlitchData => HOSTRDDATA29_GlitchData, OutSignalName => "HOSTRDDATA(29)", OutTemp => HOSTRDDATA_OUT(29), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(30), GlitchData => HOSTRDDATA30_GlitchData, OutSignalName => "HOSTRDDATA(30)", OutTemp => HOSTRDDATA_OUT(30), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => HOSTRDDATA(31), GlitchData => HOSTRDDATA31_GlitchData, OutSignalName => "HOSTRDDATA(31)", OutTemp => HOSTRDDATA_OUT(31), Paths => (0 => (HOSTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); wait on DCRHOSTDONEIR_out, EMAC0CLIENTANINTERRUPT_out, EMAC0CLIENTRXBADFRAME_out, EMAC0CLIENTRXCLIENTCLKOUT_out, EMAC0CLIENTRXDVLDMSW_out, EMAC0CLIENTRXDVLD_out, EMAC0CLIENTRXD_out, EMAC0CLIENTRXFRAMEDROP_out, EMAC0CLIENTRXGOODFRAME_out, EMAC0CLIENTRXSTATSBYTEVLD_out, EMAC0CLIENTRXSTATSVLD_out, EMAC0CLIENTRXSTATS_out, EMAC0CLIENTTXACK_out, EMAC0CLIENTTXCLIENTCLKOUT_out, EMAC0CLIENTTXCOLLISION_out, EMAC0CLIENTTXRETRANSMIT_out, EMAC0CLIENTTXSTATSBYTEVLD_out, EMAC0CLIENTTXSTATSVLD_out, EMAC0CLIENTTXSTATS_out, EMAC0PHYENCOMMAALIGN_out, EMAC0PHYLOOPBACKMSB_out, EMAC0PHYMCLKOUT_out, EMAC0PHYMDOUT_out, EMAC0PHYMDTRI_out, EMAC0PHYMGTRXRESET_out, EMAC0PHYMGTTXRESET_out, EMAC0PHYPOWERDOWN_out, EMAC0PHYSYNCACQSTATUS_out, EMAC0PHYTXCHARDISPMODE_out, EMAC0PHYTXCHARDISPVAL_out, EMAC0PHYTXCHARISK_out, EMAC0PHYTXCLK_out, EMAC0PHYTXD_out, EMAC0PHYTXEN_out, EMAC0PHYTXER_out, EMAC0PHYTXGMIIMIICLKOUT_out, EMAC0SPEEDIS10100_out, EMAC1CLIENTANINTERRUPT_out, EMAC1CLIENTRXBADFRAME_out, EMAC1CLIENTRXCLIENTCLKOUT_out, EMAC1CLIENTRXDVLDMSW_out, EMAC1CLIENTRXDVLD_out, EMAC1CLIENTRXD_out, EMAC1CLIENTRXFRAMEDROP_out, EMAC1CLIENTRXGOODFRAME_out, EMAC1CLIENTRXSTATSBYTEVLD_out, EMAC1CLIENTRXSTATSVLD_out, EMAC1CLIENTRXSTATS_out, EMAC1CLIENTTXACK_out, EMAC1CLIENTTXCLIENTCLKOUT_out, EMAC1CLIENTTXCOLLISION_out, EMAC1CLIENTTXRETRANSMIT_out, EMAC1CLIENTTXSTATSBYTEVLD_out, EMAC1CLIENTTXSTATSVLD_out, EMAC1CLIENTTXSTATS_out, EMAC1PHYENCOMMAALIGN_out, EMAC1PHYLOOPBACKMSB_out, EMAC1PHYMCLKOUT_out, EMAC1PHYMDOUT_out, EMAC1PHYMDTRI_out, EMAC1PHYMGTRXRESET_out, EMAC1PHYMGTTXRESET_out, EMAC1PHYPOWERDOWN_out, EMAC1PHYSYNCACQSTATUS_out, EMAC1PHYTXCHARDISPMODE_out, EMAC1PHYTXCHARDISPVAL_out, EMAC1PHYTXCHARISK_out, EMAC1PHYTXCLK_out, EMAC1PHYTXD_out, EMAC1PHYTXEN_out, EMAC1PHYTXER_out, EMAC1PHYTXGMIIMIICLKOUT_out, EMAC1SPEEDIS10100_out, EMACDCRACK_out, EMACDCRDBUS_out, HOSTMIIMRDY_out, HOSTRDDATA_out, CLIENTEMAC0DCMLOCKED_ipd, CLIENTEMAC0PAUSEREQ_ipd, CLIENTEMAC0PAUSEVAL_ipd, CLIENTEMAC0RXCLIENTCLKIN_ipd, CLIENTEMAC0TXCLIENTCLKIN_ipd, CLIENTEMAC0TXDVLDMSW_ipd, CLIENTEMAC0TXDVLD_ipd, CLIENTEMAC0TXD_ipd, CLIENTEMAC0TXFIRSTBYTE_ipd, CLIENTEMAC0TXIFGDELAY_ipd, CLIENTEMAC0TXUNDERRUN_ipd, CLIENTEMAC1DCMLOCKED_ipd, CLIENTEMAC1PAUSEREQ_ipd, CLIENTEMAC1PAUSEVAL_ipd, CLIENTEMAC1RXCLIENTCLKIN_ipd, CLIENTEMAC1TXCLIENTCLKIN_ipd, CLIENTEMAC1TXDVLDMSW_ipd, CLIENTEMAC1TXDVLD_ipd, CLIENTEMAC1TXD_ipd, CLIENTEMAC1TXFIRSTBYTE_ipd, CLIENTEMAC1TXIFGDELAY_ipd, CLIENTEMAC1TXUNDERRUN_ipd, DCREMACABUS_ipd, DCREMACCLK_ipd, DCREMACDBUS_ipd, DCREMACENABLE_ipd, DCREMACREAD_ipd, DCREMACWRITE_ipd, HOSTADDR_ipd, HOSTCLK_ipd, HOSTEMAC1SEL_ipd, HOSTMIIMSEL_ipd, HOSTOPCODE_ipd, HOSTREQ_ipd, HOSTWRDATA_ipd, PHYEMAC0COL_ipd, PHYEMAC0CRS_ipd, PHYEMAC0GTXCLK_ipd, PHYEMAC0MCLKIN_ipd, PHYEMAC0MDIN_ipd, PHYEMAC0MIITXCLK_ipd, PHYEMAC0PHYAD_ipd, PHYEMAC0RXBUFERR_ipd, PHYEMAC0RXBUFSTATUS_ipd, PHYEMAC0RXCHARISCOMMA_ipd, PHYEMAC0RXCHARISK_ipd, PHYEMAC0RXCHECKINGCRC_ipd, PHYEMAC0RXCLKCORCNT_ipd, PHYEMAC0RXCLK_ipd, PHYEMAC0RXCOMMADET_ipd, PHYEMAC0RXDISPERR_ipd, PHYEMAC0RXDV_ipd, PHYEMAC0RXD_ipd, PHYEMAC0RXER_ipd, PHYEMAC0RXLOSSOFSYNC_ipd, PHYEMAC0RXNOTINTABLE_ipd, PHYEMAC0RXRUNDISP_ipd, PHYEMAC0SIGNALDET_ipd, PHYEMAC0TXBUFERR_ipd, PHYEMAC0TXGMIIMIICLKIN_ipd, PHYEMAC1COL_ipd, PHYEMAC1CRS_ipd, PHYEMAC1GTXCLK_ipd, PHYEMAC1MCLKIN_ipd, PHYEMAC1MDIN_ipd, PHYEMAC1MIITXCLK_ipd, PHYEMAC1PHYAD_ipd, PHYEMAC1RXBUFERR_ipd, PHYEMAC1RXBUFSTATUS_ipd, PHYEMAC1RXCHARISCOMMA_ipd, PHYEMAC1RXCHARISK_ipd, PHYEMAC1RXCHECKINGCRC_ipd, PHYEMAC1RXCLKCORCNT_ipd, PHYEMAC1RXCLK_ipd, PHYEMAC1RXCOMMADET_ipd, PHYEMAC1RXDISPERR_ipd, PHYEMAC1RXDV_ipd, PHYEMAC1RXD_ipd, PHYEMAC1RXER_ipd, PHYEMAC1RXLOSSOFSYNC_ipd, PHYEMAC1RXNOTINTABLE_ipd, PHYEMAC1RXRUNDISP_ipd, PHYEMAC1SIGNALDET_ipd, PHYEMAC1TXBUFERR_ipd, PHYEMAC1TXGMIIMIICLKIN_ipd, RESET_ipd; end process TIMING; end TEMAC_V; ------------------------------------------------------- -- Copyright (c) 1995/2006 Xilinx Inc. -- All Right Reserved. ------------------------------------------------------- -- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : -- / / -- /___/ /\ Filename : GTX_DUAL.vhd -- \ \ / \ Timestamp : Tue Jan 9 10:05:31 2007 -- \__ \/\__ \ -- -- 09/12/06 - CR#423671 - Initial version. -- 12/05/06 - CR#426138 - J.31 spreadsheet update -- 01/23/07 - CR#430426 - J.32 pinTime added -- 02/20/07 - CR#434096 - Parameter default value update PLL_RXDIVSEL_OUT_0/1 -- 06/18/07 - CR#441601 - BT1445 - Test attributes made visible -- 06/18/07 - CR#441576 - BT1488 - Add STEPPING attribute -- 10/05/07 - CR#451343 - BT1514 - Add ES1 (ES1 mapped to 0) as STEPPING value -- 11/05/07 - CR#452590 - BT1514 - Remove STEPPING attribute from unisim/simprim wrapper -- 02/05/08 - CR#459742 - Attribute default changes -- 03/14/08 - CR#468285 - Updated timing checks -- 03/17/08 - CR#467692 - Add SIM_MODE attribute with values LEGACY & FAST model -- 04/24/08 - CR#472011 - OOBDETECT_THRESHOLD_0/1 default from 001 to 110, range changes from 000-111 to 110-111 -- 05/13/08 - CR#472931 - OOBDETECT_THRESHOLD_0/1 case statement updates -- 06/24/08 - CR472608, CR472665 - Update SIM_MODE default to FAST ------------------------------------------------------- ----- CELL GTX_DUAL ----- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; library secureip; use secureip.all; entity GTX_DUAL is generic ( AC_CAP_DIS_0 : boolean := TRUE; AC_CAP_DIS_1 : boolean := TRUE; ALIGN_COMMA_WORD_0 : integer := 1; ALIGN_COMMA_WORD_1 : integer := 1; CB2_INH_CC_PERIOD_0 : integer := 8; CB2_INH_CC_PERIOD_1 : integer := 8; CDR_PH_ADJ_TIME : bit_vector := "01010"; CHAN_BOND_1_MAX_SKEW_0 : integer := 7; CHAN_BOND_1_MAX_SKEW_1 : integer := 7; CHAN_BOND_2_MAX_SKEW_0 : integer := 7; CHAN_BOND_2_MAX_SKEW_1 : integer := 7; CHAN_BOND_KEEP_ALIGN_0 : boolean := FALSE; CHAN_BOND_KEEP_ALIGN_1 : boolean := FALSE; CHAN_BOND_LEVEL_0 : integer := 0; CHAN_BOND_LEVEL_1 : integer := 0; CHAN_BOND_MODE_0 : string := "OFF"; CHAN_BOND_MODE_1 : string := "OFF"; CHAN_BOND_SEQ_1_1_0 : bit_vector := "0101111100"; CHAN_BOND_SEQ_1_1_1 : bit_vector := "0101111100"; CHAN_BOND_SEQ_1_2_0 : bit_vector := "0000000000"; CHAN_BOND_SEQ_1_2_1 : bit_vector := "0000000000"; CHAN_BOND_SEQ_1_3_0 : bit_vector := "0000000000"; CHAN_BOND_SEQ_1_3_1 : bit_vector := "0000000000"; CHAN_BOND_SEQ_1_4_0 : bit_vector := "0000000000"; CHAN_BOND_SEQ_1_4_1 : bit_vector := "0000000000"; CHAN_BOND_SEQ_1_ENABLE_0 : bit_vector := "0001"; CHAN_BOND_SEQ_1_ENABLE_1 : bit_vector := "0001"; CHAN_BOND_SEQ_2_1_0 : bit_vector := "0000000000"; CHAN_BOND_SEQ_2_1_1 : bit_vector := "0000000000"; CHAN_BOND_SEQ_2_2_0 : bit_vector := "0000000000"; CHAN_BOND_SEQ_2_2_1 : bit_vector := "0000000000"; CHAN_BOND_SEQ_2_3_0 : bit_vector := "0000000000"; CHAN_BOND_SEQ_2_3_1 : bit_vector := "0000000000"; CHAN_BOND_SEQ_2_4_0 : bit_vector := "0000000000"; CHAN_BOND_SEQ_2_4_1 : bit_vector := "0000000000"; CHAN_BOND_SEQ_2_ENABLE_0 : bit_vector := "0000"; CHAN_BOND_SEQ_2_ENABLE_1 : bit_vector := "0000"; CHAN_BOND_SEQ_2_USE_0 : boolean := FALSE; CHAN_BOND_SEQ_2_USE_1 : boolean := FALSE; CHAN_BOND_SEQ_LEN_0 : integer := 1; CHAN_BOND_SEQ_LEN_1 : integer := 1; CLK25_DIVIDER : integer := 10; CLKINDC_B : boolean := TRUE; CLKRCV_TRST : boolean := TRUE; CLK_CORRECT_USE_0 : boolean := TRUE; CLK_CORRECT_USE_1 : boolean := TRUE; CLK_COR_ADJ_LEN_0 : integer := 1; CLK_COR_ADJ_LEN_1 : integer := 1; CLK_COR_DET_LEN_0 : integer := 1; CLK_COR_DET_LEN_1 : integer := 1; CLK_COR_INSERT_IDLE_FLAG_0 : boolean := FALSE; CLK_COR_INSERT_IDLE_FLAG_1 : boolean := FALSE; CLK_COR_KEEP_IDLE_0 : boolean := FALSE; CLK_COR_KEEP_IDLE_1 : boolean := FALSE; CLK_COR_MAX_LAT_0 : integer := 20; CLK_COR_MAX_LAT_1 : integer := 20; CLK_COR_MIN_LAT_0 : integer := 18; CLK_COR_MIN_LAT_1 : integer := 18; CLK_COR_PRECEDENCE_0 : boolean := TRUE; CLK_COR_PRECEDENCE_1 : boolean := TRUE; CLK_COR_REPEAT_WAIT_0 : integer := 0; CLK_COR_REPEAT_WAIT_1 : integer := 0; CLK_COR_SEQ_1_1_0 : bit_vector := "0100011100"; CLK_COR_SEQ_1_1_1 : bit_vector := "0100011100"; CLK_COR_SEQ_1_2_0 : bit_vector := "0000000000"; CLK_COR_SEQ_1_2_1 : bit_vector := "0000000000"; CLK_COR_SEQ_1_3_0 : bit_vector := "0000000000"; CLK_COR_SEQ_1_3_1 : bit_vector := "0000000000"; CLK_COR_SEQ_1_4_0 : bit_vector := "0000000000"; CLK_COR_SEQ_1_4_1 : bit_vector := "0000000000"; CLK_COR_SEQ_1_ENABLE_0 : bit_vector := "0001"; CLK_COR_SEQ_1_ENABLE_1 : bit_vector := "0001"; CLK_COR_SEQ_2_1_0 : bit_vector := "0000000000"; CLK_COR_SEQ_2_1_1 : bit_vector := "0000000000"; CLK_COR_SEQ_2_2_0 : bit_vector := "0000000000"; CLK_COR_SEQ_2_2_1 : bit_vector := "0000000000"; CLK_COR_SEQ_2_3_0 : bit_vector := "0000000000"; CLK_COR_SEQ_2_3_1 : bit_vector := "0000000000"; CLK_COR_SEQ_2_4_0 : bit_vector := "0000000000"; CLK_COR_SEQ_2_4_1 : bit_vector := "0000000000"; CLK_COR_SEQ_2_ENABLE_0 : bit_vector := "0000"; CLK_COR_SEQ_2_ENABLE_1 : bit_vector := "0000"; CLK_COR_SEQ_2_USE_0 : boolean := FALSE; CLK_COR_SEQ_2_USE_1 : boolean := FALSE; CM_TRIM_0 : bit_vector := "10"; CM_TRIM_1 : bit_vector := "10"; COMMA_10B_ENABLE_0 : bit_vector := "0001111111"; COMMA_10B_ENABLE_1 : bit_vector := "0001111111"; COMMA_DOUBLE_0 : boolean := FALSE; COMMA_DOUBLE_1 : boolean := FALSE; COM_BURST_VAL_0 : bit_vector := "1111"; COM_BURST_VAL_1 : bit_vector := "1111"; DEC_MCOMMA_DETECT_0 : boolean := TRUE; DEC_MCOMMA_DETECT_1 : boolean := TRUE; DEC_PCOMMA_DETECT_0 : boolean := TRUE; DEC_PCOMMA_DETECT_1 : boolean := TRUE; DEC_VALID_COMMA_ONLY_0 : boolean := TRUE; DEC_VALID_COMMA_ONLY_1 : boolean := TRUE; DFE_CAL_TIME : bit_vector := "00110"; DFE_CFG_0 : bit_vector := "1101111011"; DFE_CFG_1 : bit_vector := "1101111011"; GEARBOX_ENDEC_0 : bit_vector := "000"; GEARBOX_ENDEC_1 : bit_vector := "000"; MCOMMA_10B_VALUE_0 : bit_vector := "1010000011"; MCOMMA_10B_VALUE_1 : bit_vector := "1010000011"; MCOMMA_DETECT_0 : boolean := TRUE; MCOMMA_DETECT_1 : boolean := TRUE; OOBDETECT_THRESHOLD_0 : bit_vector := "110"; OOBDETECT_THRESHOLD_1 : bit_vector := "110"; OOB_CLK_DIVIDER : integer := 6; OVERSAMPLE_MODE : boolean := FALSE; PCI_EXPRESS_MODE_0 : boolean := FALSE; PCI_EXPRESS_MODE_1 : boolean := FALSE; PCOMMA_10B_VALUE_0 : bit_vector := "0101111100"; PCOMMA_10B_VALUE_1 : bit_vector := "0101111100"; PCOMMA_DETECT_0 : boolean := TRUE; PCOMMA_DETECT_1 : boolean := TRUE; PLL_COM_CFG : bit_vector := X"21680a"; PLL_CP_CFG : bit_vector := X"00"; PLL_DIVSEL_FB : integer := 2; PLL_DIVSEL_REF : integer := 1; PLL_FB_DCCEN : boolean := FALSE; PLL_LKDET_CFG : bit_vector := "101"; PLL_RXDIVSEL_OUT_0 : integer := 1; PLL_RXDIVSEL_OUT_1 : integer := 1; PLL_SATA_0 : boolean := FALSE; PLL_SATA_1 : boolean := FALSE; PLL_TDCC_CFG : bit_vector := "000"; PLL_TXDIVSEL_OUT_0 : integer := 1; PLL_TXDIVSEL_OUT_1 : integer := 1; PMA_CDR_SCAN_0 : bit_vector := X"6404035"; PMA_CDR_SCAN_1 : bit_vector := X"6404035"; PMA_COM_CFG : bit_vector := X"000000000000000000"; PMA_RXSYNC_CFG_0 : bit_vector := X"00"; PMA_RXSYNC_CFG_1 : bit_vector := X"00"; PMA_RX_CFG_0 : bit_vector := X"0f44089"; PMA_RX_CFG_1 : bit_vector := X"0f44089"; PMA_TX_CFG_0 : bit_vector := X"80082"; PMA_TX_CFG_1 : bit_vector := X"80082"; PRBS_ERR_THRESHOLD_0 : bit_vector := X"00000001"; PRBS_ERR_THRESHOLD_1 : bit_vector := X"00000001"; RCV_TERM_GND_0 : boolean := FALSE; RCV_TERM_GND_1 : boolean := FALSE; RCV_TERM_VTTRX_0 : boolean := FALSE; RCV_TERM_VTTRX_1 : boolean := FALSE; RXGEARBOX_USE_0 : boolean := FALSE; RXGEARBOX_USE_1 : boolean := FALSE; RX_BUFFER_USE_0 : boolean := TRUE; RX_BUFFER_USE_1 : boolean := TRUE; RX_DECODE_SEQ_MATCH_0 : boolean := TRUE; RX_DECODE_SEQ_MATCH_1 : boolean := TRUE; RX_EN_IDLE_HOLD_CDR : boolean := FALSE; RX_EN_IDLE_HOLD_DFE_0 : boolean := TRUE; RX_EN_IDLE_HOLD_DFE_1 : boolean := TRUE; RX_EN_IDLE_RESET_BUF_0 : boolean := TRUE; RX_EN_IDLE_RESET_BUF_1 : boolean := TRUE; RX_EN_IDLE_RESET_FR : boolean := TRUE; RX_EN_IDLE_RESET_PH : boolean := TRUE; RX_IDLE_HI_CNT_0 : bit_vector := "1000"; RX_IDLE_HI_CNT_1 : bit_vector := "1000"; RX_IDLE_LO_CNT_0 : bit_vector := "0000"; RX_IDLE_LO_CNT_1 : bit_vector := "0000"; RX_LOSS_OF_SYNC_FSM_0 : boolean := FALSE; RX_LOSS_OF_SYNC_FSM_1 : boolean := FALSE; RX_LOS_INVALID_INCR_0 : integer := 1; RX_LOS_INVALID_INCR_1 : integer := 1; RX_LOS_THRESHOLD_0 : integer := 4; RX_LOS_THRESHOLD_1 : integer := 4; RX_SLIDE_MODE_0 : string := "PCS"; RX_SLIDE_MODE_1 : string := "PCS"; RX_STATUS_FMT_0 : string := "PCIE"; RX_STATUS_FMT_1 : string := "PCIE"; RX_XCLK_SEL_0 : string := "RXREC"; RX_XCLK_SEL_1 : string := "RXREC"; SATA_BURST_VAL_0 : bit_vector := "100"; SATA_BURST_VAL_1 : bit_vector := "100"; SATA_IDLE_VAL_0 : bit_vector := "100"; SATA_IDLE_VAL_1 : bit_vector := "100"; SATA_MAX_BURST_0 : integer := 7; SATA_MAX_BURST_1 : integer := 7; SATA_MAX_INIT_0 : integer := 22; SATA_MAX_INIT_1 : integer := 22; SATA_MAX_WAKE_0 : integer := 7; SATA_MAX_WAKE_1 : integer := 7; SATA_MIN_BURST_0 : integer := 4; SATA_MIN_BURST_1 : integer := 4; SATA_MIN_INIT_0 : integer := 12; SATA_MIN_INIT_1 : integer := 12; SATA_MIN_WAKE_0 : integer := 4; SATA_MIN_WAKE_1 : integer := 4; SIM_GTXRESET_SPEEDUP : integer := 1; SIM_MODE : string := "FAST"; SIM_PLL_PERDIV2 : bit_vector := X"140"; SIM_RECEIVER_DETECT_PASS_0 : boolean := TRUE; SIM_RECEIVER_DETECT_PASS_1 : boolean := TRUE; TERMINATION_CTRL : bit_vector := "10100"; TERMINATION_IMP_0 : integer := 50; TERMINATION_IMP_1 : integer := 50; TERMINATION_OVRD : boolean := FALSE; TRANS_TIME_FROM_P2_0 : bit_vector := X"03c"; TRANS_TIME_FROM_P2_1 : bit_vector := X"03c"; TRANS_TIME_NON_P2_0 : bit_vector := X"19"; TRANS_TIME_NON_P2_1 : bit_vector := X"19"; TRANS_TIME_TO_P2_0 : bit_vector := X"064"; TRANS_TIME_TO_P2_1 : bit_vector := X"064"; TXGEARBOX_USE_0 : boolean := FALSE; TXGEARBOX_USE_1 : boolean := FALSE; TXRX_INVERT_0 : bit_vector := "011"; TXRX_INVERT_1 : bit_vector := "011"; TX_BUFFER_USE_0 : boolean := TRUE; TX_BUFFER_USE_1 : boolean := TRUE; TX_DETECT_RX_CFG_0 : bit_vector := X"1832"; TX_DETECT_RX_CFG_1 : bit_vector := X"1832"; TX_IDLE_DELAY_0 : bit_vector := "010"; TX_IDLE_DELAY_1 : bit_vector := "010"; TX_XCLK_SEL_0 : string := "TXOUT"; TX_XCLK_SEL_1 : string := "TXOUT" ); port ( DFECLKDLYADJMONITOR0 : out std_logic_vector(5 downto 0); DFECLKDLYADJMONITOR1 : out std_logic_vector(5 downto 0); DFEEYEDACMONITOR0 : out std_logic_vector(4 downto 0); DFEEYEDACMONITOR1 : out std_logic_vector(4 downto 0); DFESENSCAL0 : out std_logic_vector(2 downto 0); DFESENSCAL1 : out std_logic_vector(2 downto 0); DFETAP1MONITOR0 : out std_logic_vector(4 downto 0); DFETAP1MONITOR1 : out std_logic_vector(4 downto 0); DFETAP2MONITOR0 : out std_logic_vector(4 downto 0); DFETAP2MONITOR1 : out std_logic_vector(4 downto 0); DFETAP3MONITOR0 : out std_logic_vector(3 downto 0); DFETAP3MONITOR1 : out std_logic_vector(3 downto 0); DFETAP4MONITOR0 : out std_logic_vector(3 downto 0); DFETAP4MONITOR1 : out std_logic_vector(3 downto 0); DO : out std_logic_vector(15 downto 0); DRDY : out std_ulogic; PHYSTATUS0 : out std_ulogic; PHYSTATUS1 : out std_ulogic; PLLLKDET : out std_ulogic; REFCLKOUT : out std_ulogic; RESETDONE0 : out std_ulogic; RESETDONE1 : out std_ulogic; RXBUFSTATUS0 : out std_logic_vector(2 downto 0); RXBUFSTATUS1 : out std_logic_vector(2 downto 0); RXBYTEISALIGNED0 : out std_ulogic; RXBYTEISALIGNED1 : out std_ulogic; RXBYTEREALIGN0 : out std_ulogic; RXBYTEREALIGN1 : out std_ulogic; RXCHANBONDSEQ0 : out std_ulogic; RXCHANBONDSEQ1 : out std_ulogic; RXCHANISALIGNED0 : out std_ulogic; RXCHANISALIGNED1 : out std_ulogic; RXCHANREALIGN0 : out std_ulogic; RXCHANREALIGN1 : out std_ulogic; RXCHARISCOMMA0 : out std_logic_vector(3 downto 0); RXCHARISCOMMA1 : out std_logic_vector(3 downto 0); RXCHARISK0 : out std_logic_vector(3 downto 0); RXCHARISK1 : out std_logic_vector(3 downto 0); RXCHBONDO0 : out std_logic_vector(3 downto 0); RXCHBONDO1 : out std_logic_vector(3 downto 0); RXCLKCORCNT0 : out std_logic_vector(2 downto 0); RXCLKCORCNT1 : out std_logic_vector(2 downto 0); RXCOMMADET0 : out std_ulogic; RXCOMMADET1 : out std_ulogic; RXDATA0 : out std_logic_vector(31 downto 0); RXDATA1 : out std_logic_vector(31 downto 0); RXDATAVALID0 : out std_ulogic; RXDATAVALID1 : out std_ulogic; RXDISPERR0 : out std_logic_vector(3 downto 0); RXDISPERR1 : out std_logic_vector(3 downto 0); RXELECIDLE0 : out std_ulogic; RXELECIDLE1 : out std_ulogic; RXHEADER0 : out std_logic_vector(2 downto 0); RXHEADER1 : out std_logic_vector(2 downto 0); RXHEADERVALID0 : out std_ulogic; RXHEADERVALID1 : out std_ulogic; RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); RXNOTINTABLE0 : out std_logic_vector(3 downto 0); RXNOTINTABLE1 : out std_logic_vector(3 downto 0); RXOVERSAMPLEERR0 : out std_ulogic; RXOVERSAMPLEERR1 : out std_ulogic; RXPRBSERR0 : out std_ulogic; RXPRBSERR1 : out std_ulogic; RXRECCLK0 : out std_ulogic; RXRECCLK1 : out std_ulogic; RXRUNDISP0 : out std_logic_vector(3 downto 0); RXRUNDISP1 : out std_logic_vector(3 downto 0); RXSTARTOFSEQ0 : out std_ulogic; RXSTARTOFSEQ1 : out std_ulogic; RXSTATUS0 : out std_logic_vector(2 downto 0); RXSTATUS1 : out std_logic_vector(2 downto 0); RXVALID0 : out std_ulogic; RXVALID1 : out std_ulogic; TXBUFSTATUS0 : out std_logic_vector(1 downto 0); TXBUFSTATUS1 : out std_logic_vector(1 downto 0); TXGEARBOXREADY0 : out std_ulogic; TXGEARBOXREADY1 : out std_ulogic; TXKERR0 : out std_logic_vector(3 downto 0); TXKERR1 : out std_logic_vector(3 downto 0); TXN0 : out std_ulogic; TXN1 : out std_ulogic; TXOUTCLK0 : out std_ulogic; TXOUTCLK1 : out std_ulogic; TXP0 : out std_ulogic; TXP1 : out std_ulogic; TXRUNDISP0 : out std_logic_vector(3 downto 0); TXRUNDISP1 : out std_logic_vector(3 downto 0); CLKIN : in std_ulogic; DADDR : in std_logic_vector(6 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DFECLKDLYADJ0 : in std_logic_vector(5 downto 0); DFECLKDLYADJ1 : in std_logic_vector(5 downto 0); DFETAP10 : in std_logic_vector(4 downto 0); DFETAP11 : in std_logic_vector(4 downto 0); DFETAP20 : in std_logic_vector(4 downto 0); DFETAP21 : in std_logic_vector(4 downto 0); DFETAP30 : in std_logic_vector(3 downto 0); DFETAP31 : in std_logic_vector(3 downto 0); DFETAP40 : in std_logic_vector(3 downto 0); DFETAP41 : in std_logic_vector(3 downto 0); DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; GTXRESET : in std_ulogic; GTXTEST : in std_logic_vector(13 downto 0); INTDATAWIDTH : in std_ulogic; LOOPBACK0 : in std_logic_vector(2 downto 0); LOOPBACK1 : in std_logic_vector(2 downto 0); PLLLKDETEN : in std_ulogic; PLLPOWERDOWN : in std_ulogic; PRBSCNTRESET0 : in std_ulogic; PRBSCNTRESET1 : in std_ulogic; REFCLKPWRDNB : in std_ulogic; RXBUFRESET0 : in std_ulogic; RXBUFRESET1 : in std_ulogic; RXCDRRESET0 : in std_ulogic; RXCDRRESET1 : in std_ulogic; RXCHBONDI0 : in std_logic_vector(3 downto 0); RXCHBONDI1 : in std_logic_vector(3 downto 0); RXCOMMADETUSE0 : in std_ulogic; RXCOMMADETUSE1 : in std_ulogic; RXDATAWIDTH0 : in std_logic_vector(1 downto 0); RXDATAWIDTH1 : in std_logic_vector(1 downto 0); RXDEC8B10BUSE0 : in std_ulogic; RXDEC8B10BUSE1 : in std_ulogic; RXENCHANSYNC0 : in std_ulogic; RXENCHANSYNC1 : in std_ulogic; RXENEQB0 : in std_ulogic; RXENEQB1 : in std_ulogic; RXENMCOMMAALIGN0 : in std_ulogic; RXENMCOMMAALIGN1 : in std_ulogic; RXENPCOMMAALIGN0 : in std_ulogic; RXENPCOMMAALIGN1 : in std_ulogic; RXENPMAPHASEALIGN0 : in std_ulogic; RXENPMAPHASEALIGN1 : in std_ulogic; RXENPRBSTST0 : in std_logic_vector(1 downto 0); RXENPRBSTST1 : in std_logic_vector(1 downto 0); RXENSAMPLEALIGN0 : in std_ulogic; RXENSAMPLEALIGN1 : in std_ulogic; RXEQMIX0 : in std_logic_vector(1 downto 0); RXEQMIX1 : in std_logic_vector(1 downto 0); RXEQPOLE0 : in std_logic_vector(3 downto 0); RXEQPOLE1 : in std_logic_vector(3 downto 0); RXGEARBOXSLIP0 : in std_ulogic; RXGEARBOXSLIP1 : in std_ulogic; RXN0 : in std_ulogic; RXN1 : in std_ulogic; RXP0 : in std_ulogic; RXP1 : in std_ulogic; RXPMASETPHASE0 : in std_ulogic; RXPMASETPHASE1 : in std_ulogic; RXPOLARITY0 : in std_ulogic; RXPOLARITY1 : in std_ulogic; RXPOWERDOWN0 : in std_logic_vector(1 downto 0); RXPOWERDOWN1 : in std_logic_vector(1 downto 0); RXRESET0 : in std_ulogic; RXRESET1 : in std_ulogic; RXSLIDE0 : in std_ulogic; RXSLIDE1 : in std_ulogic; RXUSRCLK0 : in std_ulogic; RXUSRCLK1 : in std_ulogic; RXUSRCLK20 : in std_ulogic; RXUSRCLK21 : in std_ulogic; TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); TXBYPASS8B10B0 : in std_logic_vector(3 downto 0); TXBYPASS8B10B1 : in std_logic_vector(3 downto 0); TXCHARDISPMODE0 : in std_logic_vector(3 downto 0); TXCHARDISPMODE1 : in std_logic_vector(3 downto 0); TXCHARDISPVAL0 : in std_logic_vector(3 downto 0); TXCHARDISPVAL1 : in std_logic_vector(3 downto 0); TXCHARISK0 : in std_logic_vector(3 downto 0); TXCHARISK1 : in std_logic_vector(3 downto 0); TXCOMSTART0 : in std_ulogic; TXCOMSTART1 : in std_ulogic; TXCOMTYPE0 : in std_ulogic; TXCOMTYPE1 : in std_ulogic; TXDATA0 : in std_logic_vector(31 downto 0); TXDATA1 : in std_logic_vector(31 downto 0); TXDATAWIDTH0 : in std_logic_vector(1 downto 0); TXDATAWIDTH1 : in std_logic_vector(1 downto 0); TXDETECTRX0 : in std_ulogic; TXDETECTRX1 : in std_ulogic; TXDIFFCTRL0 : in std_logic_vector(2 downto 0); TXDIFFCTRL1 : in std_logic_vector(2 downto 0); TXELECIDLE0 : in std_ulogic; TXELECIDLE1 : in std_ulogic; TXENC8B10BUSE0 : in std_ulogic; TXENC8B10BUSE1 : in std_ulogic; TXENPMAPHASEALIGN0 : in std_ulogic; TXENPMAPHASEALIGN1 : in std_ulogic; TXENPRBSTST0 : in std_logic_vector(1 downto 0); TXENPRBSTST1 : in std_logic_vector(1 downto 0); TXHEADER0 : in std_logic_vector(2 downto 0); TXHEADER1 : in std_logic_vector(2 downto 0); TXINHIBIT0 : in std_ulogic; TXINHIBIT1 : in std_ulogic; TXPMASETPHASE0 : in std_ulogic; TXPMASETPHASE1 : in std_ulogic; TXPOLARITY0 : in std_ulogic; TXPOLARITY1 : in std_ulogic; TXPOWERDOWN0 : in std_logic_vector(1 downto 0); TXPOWERDOWN1 : in std_logic_vector(1 downto 0); TXPREEMPHASIS0 : in std_logic_vector(3 downto 0); TXPREEMPHASIS1 : in std_logic_vector(3 downto 0); TXRESET0 : in std_ulogic; TXRESET1 : in std_ulogic; TXSEQUENCE0 : in std_logic_vector(6 downto 0); TXSEQUENCE1 : in std_logic_vector(6 downto 0); TXSTARTSEQ0 : in std_ulogic; TXSTARTSEQ1 : in std_ulogic; TXUSRCLK0 : in std_ulogic; TXUSRCLK1 : in std_ulogic; TXUSRCLK20 : in std_ulogic; TXUSRCLK21 : in std_ulogic ); end GTX_DUAL; architecture GTX_DUAL_V of GTX_DUAL is component GTX_DUAL_SWIFT port ( DFECLKDLYADJMONITOR0 : out std_logic_vector(5 downto 0); DFECLKDLYADJMONITOR1 : out std_logic_vector(5 downto 0); DFEEYEDACMONITOR0 : out std_logic_vector(4 downto 0); DFEEYEDACMONITOR1 : out std_logic_vector(4 downto 0); DFESENSCAL0 : out std_logic_vector(2 downto 0); DFESENSCAL1 : out std_logic_vector(2 downto 0); DFETAP1MONITOR0 : out std_logic_vector(4 downto 0); DFETAP1MONITOR1 : out std_logic_vector(4 downto 0); DFETAP2MONITOR0 : out std_logic_vector(4 downto 0); DFETAP2MONITOR1 : out std_logic_vector(4 downto 0); DFETAP3MONITOR0 : out std_logic_vector(3 downto 0); DFETAP3MONITOR1 : out std_logic_vector(3 downto 0); DFETAP4MONITOR0 : out std_logic_vector(3 downto 0); DFETAP4MONITOR1 : out std_logic_vector(3 downto 0); DO : out std_logic_vector(15 downto 0); DRDY : out std_ulogic; PHYSTATUS0 : out std_ulogic; PHYSTATUS1 : out std_ulogic; PLLLKDET : out std_ulogic; REFCLKOUT : out std_ulogic; RESETDONE0 : out std_ulogic; RESETDONE1 : out std_ulogic; RXBUFSTATUS0 : out std_logic_vector(2 downto 0); RXBUFSTATUS1 : out std_logic_vector(2 downto 0); RXBYTEISALIGNED0 : out std_ulogic; RXBYTEISALIGNED1 : out std_ulogic; RXBYTEREALIGN0 : out std_ulogic; RXBYTEREALIGN1 : out std_ulogic; RXCHANBONDSEQ0 : out std_ulogic; RXCHANBONDSEQ1 : out std_ulogic; RXCHANISALIGNED0 : out std_ulogic; RXCHANISALIGNED1 : out std_ulogic; RXCHANREALIGN0 : out std_ulogic; RXCHANREALIGN1 : out std_ulogic; RXCHARISCOMMA0 : out std_logic_vector(3 downto 0); RXCHARISCOMMA1 : out std_logic_vector(3 downto 0); RXCHARISK0 : out std_logic_vector(3 downto 0); RXCHARISK1 : out std_logic_vector(3 downto 0); RXCHBONDO0 : out std_logic_vector(3 downto 0); RXCHBONDO1 : out std_logic_vector(3 downto 0); RXCLKCORCNT0 : out std_logic_vector(2 downto 0); RXCLKCORCNT1 : out std_logic_vector(2 downto 0); RXCOMMADET0 : out std_ulogic; RXCOMMADET1 : out std_ulogic; RXDATA0 : out std_logic_vector(31 downto 0); RXDATA1 : out std_logic_vector(31 downto 0); RXDATAVALID0 : out std_ulogic; RXDATAVALID1 : out std_ulogic; RXDISPERR0 : out std_logic_vector(3 downto 0); RXDISPERR1 : out std_logic_vector(3 downto 0); RXELECIDLE0 : out std_ulogic; RXELECIDLE1 : out std_ulogic; RXHEADER0 : out std_logic_vector(2 downto 0); RXHEADER1 : out std_logic_vector(2 downto 0); RXHEADERVALID0 : out std_ulogic; RXHEADERVALID1 : out std_ulogic; RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); RXNOTINTABLE0 : out std_logic_vector(3 downto 0); RXNOTINTABLE1 : out std_logic_vector(3 downto 0); RXOVERSAMPLEERR0 : out std_ulogic; RXOVERSAMPLEERR1 : out std_ulogic; RXPRBSERR0 : out std_ulogic; RXPRBSERR1 : out std_ulogic; RXRECCLK0 : out std_ulogic; RXRECCLK1 : out std_ulogic; RXRUNDISP0 : out std_logic_vector(3 downto 0); RXRUNDISP1 : out std_logic_vector(3 downto 0); RXSTARTOFSEQ0 : out std_ulogic; RXSTARTOFSEQ1 : out std_ulogic; RXSTATUS0 : out std_logic_vector(2 downto 0); RXSTATUS1 : out std_logic_vector(2 downto 0); RXVALID0 : out std_ulogic; RXVALID1 : out std_ulogic; TXBUFSTATUS0 : out std_logic_vector(1 downto 0); TXBUFSTATUS1 : out std_logic_vector(1 downto 0); TXGEARBOXREADY0 : out std_ulogic; TXGEARBOXREADY1 : out std_ulogic; TXKERR0 : out std_logic_vector(3 downto 0); TXKERR1 : out std_logic_vector(3 downto 0); TXN0 : out std_ulogic; TXN1 : out std_ulogic; TXOUTCLK0 : out std_ulogic; TXOUTCLK1 : out std_ulogic; TXP0 : out std_ulogic; TXP1 : out std_ulogic; TXRUNDISP0 : out std_logic_vector(3 downto 0); TXRUNDISP1 : out std_logic_vector(3 downto 0); CLKIN : in std_ulogic; DADDR : in std_logic_vector(6 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DFECLKDLYADJ0 : in std_logic_vector(5 downto 0); DFECLKDLYADJ1 : in std_logic_vector(5 downto 0); DFETAP10 : in std_logic_vector(4 downto 0); DFETAP11 : in std_logic_vector(4 downto 0); DFETAP20 : in std_logic_vector(4 downto 0); DFETAP21 : in std_logic_vector(4 downto 0); DFETAP30 : in std_logic_vector(3 downto 0); DFETAP31 : in std_logic_vector(3 downto 0); DFETAP40 : in std_logic_vector(3 downto 0); DFETAP41 : in std_logic_vector(3 downto 0); DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; GSR : in std_ulogic; GTXRESET : in std_ulogic; GTXTEST : in std_logic_vector(13 downto 0); INTDATAWIDTH : in std_ulogic; LOOPBACK0 : in std_logic_vector(2 downto 0); LOOPBACK1 : in std_logic_vector(2 downto 0); PLLLKDETEN : in std_ulogic; PLLPOWERDOWN : in std_ulogic; PRBSCNTRESET0 : in std_ulogic; PRBSCNTRESET1 : in std_ulogic; REFCLKPWRDNB : in std_ulogic; RXBUFRESET0 : in std_ulogic; RXBUFRESET1 : in std_ulogic; RXCDRRESET0 : in std_ulogic; RXCDRRESET1 : in std_ulogic; RXCHBONDI0 : in std_logic_vector(3 downto 0); RXCHBONDI1 : in std_logic_vector(3 downto 0); RXCOMMADETUSE0 : in std_ulogic; RXCOMMADETUSE1 : in std_ulogic; RXDATAWIDTH0 : in std_logic_vector(1 downto 0); RXDATAWIDTH1 : in std_logic_vector(1 downto 0); RXDEC8B10BUSE0 : in std_ulogic; RXDEC8B10BUSE1 : in std_ulogic; RXENCHANSYNC0 : in std_ulogic; RXENCHANSYNC1 : in std_ulogic; RXENEQB0 : in std_ulogic; RXENEQB1 : in std_ulogic; RXENMCOMMAALIGN0 : in std_ulogic; RXENMCOMMAALIGN1 : in std_ulogic; RXENPCOMMAALIGN0 : in std_ulogic; RXENPCOMMAALIGN1 : in std_ulogic; RXENPMAPHASEALIGN0 : in std_ulogic; RXENPMAPHASEALIGN1 : in std_ulogic; RXENPRBSTST0 : in std_logic_vector(1 downto 0); RXENPRBSTST1 : in std_logic_vector(1 downto 0); RXENSAMPLEALIGN0 : in std_ulogic; RXENSAMPLEALIGN1 : in std_ulogic; RXEQMIX0 : in std_logic_vector(1 downto 0); RXEQMIX1 : in std_logic_vector(1 downto 0); RXEQPOLE0 : in std_logic_vector(3 downto 0); RXEQPOLE1 : in std_logic_vector(3 downto 0); RXGEARBOXSLIP0 : in std_ulogic; RXGEARBOXSLIP1 : in std_ulogic; RXN0 : in std_ulogic; RXN1 : in std_ulogic; RXP0 : in std_ulogic; RXP1 : in std_ulogic; RXPMASETPHASE0 : in std_ulogic; RXPMASETPHASE1 : in std_ulogic; RXPOLARITY0 : in std_ulogic; RXPOLARITY1 : in std_ulogic; RXPOWERDOWN0 : in std_logic_vector(1 downto 0); RXPOWERDOWN1 : in std_logic_vector(1 downto 0); RXRESET0 : in std_ulogic; RXRESET1 : in std_ulogic; RXSLIDE0 : in std_ulogic; RXSLIDE1 : in std_ulogic; RXUSRCLK0 : in std_ulogic; RXUSRCLK1 : in std_ulogic; RXUSRCLK20 : in std_ulogic; RXUSRCLK21 : in std_ulogic; TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); TXBYPASS8B10B0 : in std_logic_vector(3 downto 0); TXBYPASS8B10B1 : in std_logic_vector(3 downto 0); TXCHARDISPMODE0 : in std_logic_vector(3 downto 0); TXCHARDISPMODE1 : in std_logic_vector(3 downto 0); TXCHARDISPVAL0 : in std_logic_vector(3 downto 0); TXCHARDISPVAL1 : in std_logic_vector(3 downto 0); TXCHARISK0 : in std_logic_vector(3 downto 0); TXCHARISK1 : in std_logic_vector(3 downto 0); TXCOMSTART0 : in std_ulogic; TXCOMSTART1 : in std_ulogic; TXCOMTYPE0 : in std_ulogic; TXCOMTYPE1 : in std_ulogic; TXDATA0 : in std_logic_vector(31 downto 0); TXDATA1 : in std_logic_vector(31 downto 0); TXDATAWIDTH0 : in std_logic_vector(1 downto 0); TXDATAWIDTH1 : in std_logic_vector(1 downto 0); TXDETECTRX0 : in std_ulogic; TXDETECTRX1 : in std_ulogic; TXDIFFCTRL0 : in std_logic_vector(2 downto 0); TXDIFFCTRL1 : in std_logic_vector(2 downto 0); TXELECIDLE0 : in std_ulogic; TXELECIDLE1 : in std_ulogic; TXENC8B10BUSE0 : in std_ulogic; TXENC8B10BUSE1 : in std_ulogic; TXENPMAPHASEALIGN0 : in std_ulogic; TXENPMAPHASEALIGN1 : in std_ulogic; TXENPRBSTST0 : in std_logic_vector(1 downto 0); TXENPRBSTST1 : in std_logic_vector(1 downto 0); TXHEADER0 : in std_logic_vector(2 downto 0); TXHEADER1 : in std_logic_vector(2 downto 0); TXINHIBIT0 : in std_ulogic; TXINHIBIT1 : in std_ulogic; TXPMASETPHASE0 : in std_ulogic; TXPMASETPHASE1 : in std_ulogic; TXPOLARITY0 : in std_ulogic; TXPOLARITY1 : in std_ulogic; TXPOWERDOWN0 : in std_logic_vector(1 downto 0); TXPOWERDOWN1 : in std_logic_vector(1 downto 0); TXPREEMPHASIS0 : in std_logic_vector(3 downto 0); TXPREEMPHASIS1 : in std_logic_vector(3 downto 0); TXRESET0 : in std_ulogic; TXRESET1 : in std_ulogic; TXSEQUENCE0 : in std_logic_vector(6 downto 0); TXSEQUENCE1 : in std_logic_vector(6 downto 0); TXSTARTSEQ0 : in std_ulogic; TXSTARTSEQ1 : in std_ulogic; TXUSRCLK0 : in std_ulogic; TXUSRCLK1 : in std_ulogic; TXUSRCLK20 : in std_ulogic; TXUSRCLK21 : in std_ulogic; STEPPING : in std_ulogic; AC_CAP_DIS_0 : in std_ulogic; AC_CAP_DIS_1 : in std_ulogic; ALIGN_COMMA_WORD_0 : in std_ulogic; ALIGN_COMMA_WORD_1 : in std_ulogic; CB2_INH_CC_PERIOD_0 : in std_logic_vector(3 downto 0); CB2_INH_CC_PERIOD_1 : in std_logic_vector(3 downto 0); CDR_PH_ADJ_TIME : in std_logic_vector(4 downto 0); CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); CHAN_BOND_KEEP_ALIGN_0 : in std_ulogic; CHAN_BOND_KEEP_ALIGN_1 : in std_ulogic; CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); CLK25_DIVIDER : in std_logic_vector(2 downto 0); CLKINDC_B : in std_ulogic; CLKRCV_TRST : in std_ulogic; CLK_CORRECT_USE_0 : in std_ulogic; CLK_CORRECT_USE_1 : in std_ulogic; CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; CLK_COR_KEEP_IDLE_0 : in std_ulogic; CLK_COR_KEEP_IDLE_1 : in std_ulogic; CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); CLK_COR_PRECEDENCE_0 : in std_ulogic; CLK_COR_PRECEDENCE_1 : in std_ulogic; CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_USE_0 : in std_ulogic; CLK_COR_SEQ_2_USE_1 : in std_ulogic; CM_TRIM_0 : in std_logic_vector(1 downto 0); CM_TRIM_1 : in std_logic_vector(1 downto 0); COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); COMMA_DOUBLE_0 : in std_ulogic; COMMA_DOUBLE_1 : in std_ulogic; COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); DEC_MCOMMA_DETECT_0 : in std_ulogic; DEC_MCOMMA_DETECT_1 : in std_ulogic; DEC_PCOMMA_DETECT_0 : in std_ulogic; DEC_PCOMMA_DETECT_1 : in std_ulogic; DEC_VALID_COMMA_ONLY_0 : in std_ulogic; DEC_VALID_COMMA_ONLY_1 : in std_ulogic; DFE_CAL_TIME : in std_logic_vector(4 downto 0); DFE_CFG_0 : in std_logic_vector(9 downto 0); DFE_CFG_1 : in std_logic_vector(9 downto 0); GEARBOX_ENDEC_0 : in std_logic_vector(2 downto 0); GEARBOX_ENDEC_1 : in std_logic_vector(2 downto 0); MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); MCOMMA_DETECT_0 : in std_ulogic; MCOMMA_DETECT_1 : in std_ulogic; OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); OVERSAMPLE_MODE : in std_ulogic; PCI_EXPRESS_MODE_0 : in std_ulogic; PCI_EXPRESS_MODE_1 : in std_ulogic; PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); PCOMMA_DETECT_0 : in std_ulogic; PCOMMA_DETECT_1 : in std_ulogic; PLL_COM_CFG : in std_logic_vector(23 downto 0); PLL_CP_CFG : in std_logic_vector(7 downto 0); PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); PLL_FB_DCCEN : in std_ulogic; PLL_LKDET_CFG : in std_logic_vector(2 downto 0); PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); PLL_SATA_0 : in std_ulogic; PLL_SATA_1 : in std_ulogic; PLL_TDCC_CFG : in std_logic_vector(2 downto 0); PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); PMA_COM_CFG : in std_logic_vector(68 downto 0); PMA_RXSYNC_CFG_0 : in std_logic_vector(6 downto 0); PMA_RXSYNC_CFG_1 : in std_logic_vector(6 downto 0); PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); PMA_TX_CFG_0 : in std_logic_vector(19 downto 0); PMA_TX_CFG_1 : in std_logic_vector(19 downto 0); PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); RCV_TERM_GND_0 : in std_ulogic; RCV_TERM_GND_1 : in std_ulogic; RCV_TERM_VTTRX_0 : in std_ulogic; RCV_TERM_VTTRX_1 : in std_ulogic; RXGEARBOX_USE_0 : in std_ulogic; RXGEARBOX_USE_1 : in std_ulogic; RX_BUFFER_USE_0 : in std_ulogic; RX_BUFFER_USE_1 : in std_ulogic; RX_DECODE_SEQ_MATCH_0 : in std_ulogic; RX_DECODE_SEQ_MATCH_1 : in std_ulogic; RX_EN_IDLE_HOLD_CDR : in std_ulogic; RX_EN_IDLE_HOLD_DFE_0 : in std_ulogic; RX_EN_IDLE_HOLD_DFE_1 : in std_ulogic; RX_EN_IDLE_RESET_BUF_0 : in std_ulogic; RX_EN_IDLE_RESET_BUF_1 : in std_ulogic; RX_EN_IDLE_RESET_FR : in std_ulogic; RX_EN_IDLE_RESET_PH : in std_ulogic; RX_IDLE_HI_CNT_0 : in std_logic_vector(3 downto 0); RX_IDLE_HI_CNT_1 : in std_logic_vector(3 downto 0); RX_IDLE_LO_CNT_0 : in std_logic_vector(3 downto 0); RX_IDLE_LO_CNT_1 : in std_logic_vector(3 downto 0); RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); RX_SLIDE_MODE_0 : in std_ulogic; RX_SLIDE_MODE_1 : in std_ulogic; RX_STATUS_FMT_0 : in std_ulogic; RX_STATUS_FMT_1 : in std_ulogic; RX_XCLK_SEL_0 : in std_ulogic; RX_XCLK_SEL_1 : in std_ulogic; SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); SIM_GTXRESET_SPEEDUP : in std_ulogic; SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); SIM_RECEIVER_DETECT_PASS_0 : in std_ulogic; SIM_RECEIVER_DETECT_PASS_1 : in std_ulogic; TERMINATION_CTRL : in std_logic_vector(4 downto 0); TERMINATION_IMP_0 : in std_ulogic; TERMINATION_IMP_1 : in std_ulogic; TERMINATION_OVRD : in std_ulogic; TRANS_TIME_FROM_P2_0 : in std_logic_vector(11 downto 0); TRANS_TIME_FROM_P2_1 : in std_logic_vector(11 downto 0); TRANS_TIME_NON_P2_0 : in std_logic_vector(7 downto 0); TRANS_TIME_NON_P2_1 : in std_logic_vector(7 downto 0); TRANS_TIME_TO_P2_0 : in std_logic_vector(9 downto 0); TRANS_TIME_TO_P2_1 : in std_logic_vector(9 downto 0); TXGEARBOX_USE_0 : in std_ulogic; TXGEARBOX_USE_1 : in std_ulogic; TXRX_INVERT_0 : in std_logic_vector(2 downto 0); TXRX_INVERT_1 : in std_logic_vector(2 downto 0); TX_BUFFER_USE_0 : in std_ulogic; TX_BUFFER_USE_1 : in std_ulogic; TX_DETECT_RX_CFG_0 : in std_logic_vector(13 downto 0); TX_DETECT_RX_CFG_1 : in std_logic_vector(13 downto 0); TX_IDLE_DELAY_0 : in std_logic_vector(2 downto 0); TX_IDLE_DELAY_1 : in std_logic_vector(2 downto 0); TX_XCLK_SEL_0 : in std_ulogic; TX_XCLK_SEL_1 : in std_ulogic ); end component; component GTX_DUAL_FAST port ( DFECLKDLYADJMONITOR0 : out std_logic_vector(5 downto 0); DFECLKDLYADJMONITOR1 : out std_logic_vector(5 downto 0); DFEEYEDACMONITOR0 : out std_logic_vector(4 downto 0); DFEEYEDACMONITOR1 : out std_logic_vector(4 downto 0); DFESENSCAL0 : out std_logic_vector(2 downto 0); DFESENSCAL1 : out std_logic_vector(2 downto 0); DFETAP1MONITOR0 : out std_logic_vector(4 downto 0); DFETAP1MONITOR1 : out std_logic_vector(4 downto 0); DFETAP2MONITOR0 : out std_logic_vector(4 downto 0); DFETAP2MONITOR1 : out std_logic_vector(4 downto 0); DFETAP3MONITOR0 : out std_logic_vector(3 downto 0); DFETAP3MONITOR1 : out std_logic_vector(3 downto 0); DFETAP4MONITOR0 : out std_logic_vector(3 downto 0); DFETAP4MONITOR1 : out std_logic_vector(3 downto 0); DO : out std_logic_vector(15 downto 0); DRDY : out std_ulogic; PHYSTATUS0 : out std_ulogic; PHYSTATUS1 : out std_ulogic; PLLLKDET : out std_ulogic; REFCLKOUT : out std_ulogic; RESETDONE0 : out std_ulogic; RESETDONE1 : out std_ulogic; RXBUFSTATUS0 : out std_logic_vector(2 downto 0); RXBUFSTATUS1 : out std_logic_vector(2 downto 0); RXBYTEISALIGNED0 : out std_ulogic; RXBYTEISALIGNED1 : out std_ulogic; RXBYTEREALIGN0 : out std_ulogic; RXBYTEREALIGN1 : out std_ulogic; RXCHANBONDSEQ0 : out std_ulogic; RXCHANBONDSEQ1 : out std_ulogic; RXCHANISALIGNED0 : out std_ulogic; RXCHANISALIGNED1 : out std_ulogic; RXCHANREALIGN0 : out std_ulogic; RXCHANREALIGN1 : out std_ulogic; RXCHARISCOMMA0 : out std_logic_vector(3 downto 0); RXCHARISCOMMA1 : out std_logic_vector(3 downto 0); RXCHARISK0 : out std_logic_vector(3 downto 0); RXCHARISK1 : out std_logic_vector(3 downto 0); RXCHBONDO0 : out std_logic_vector(3 downto 0); RXCHBONDO1 : out std_logic_vector(3 downto 0); RXCLKCORCNT0 : out std_logic_vector(2 downto 0); RXCLKCORCNT1 : out std_logic_vector(2 downto 0); RXCOMMADET0 : out std_ulogic; RXCOMMADET1 : out std_ulogic; RXDATA0 : out std_logic_vector(31 downto 0); RXDATA1 : out std_logic_vector(31 downto 0); RXDATAVALID0 : out std_ulogic; RXDATAVALID1 : out std_ulogic; RXDISPERR0 : out std_logic_vector(3 downto 0); RXDISPERR1 : out std_logic_vector(3 downto 0); RXELECIDLE0 : out std_ulogic; RXELECIDLE1 : out std_ulogic; RXHEADER0 : out std_logic_vector(2 downto 0); RXHEADER1 : out std_logic_vector(2 downto 0); RXHEADERVALID0 : out std_ulogic; RXHEADERVALID1 : out std_ulogic; RXLOSSOFSYNC0 : out std_logic_vector(1 downto 0); RXLOSSOFSYNC1 : out std_logic_vector(1 downto 0); RXNOTINTABLE0 : out std_logic_vector(3 downto 0); RXNOTINTABLE1 : out std_logic_vector(3 downto 0); RXOVERSAMPLEERR0 : out std_ulogic; RXOVERSAMPLEERR1 : out std_ulogic; RXPRBSERR0 : out std_ulogic; RXPRBSERR1 : out std_ulogic; RXRECCLK0 : out std_ulogic; RXRECCLK1 : out std_ulogic; RXRUNDISP0 : out std_logic_vector(3 downto 0); RXRUNDISP1 : out std_logic_vector(3 downto 0); RXSTARTOFSEQ0 : out std_ulogic; RXSTARTOFSEQ1 : out std_ulogic; RXSTATUS0 : out std_logic_vector(2 downto 0); RXSTATUS1 : out std_logic_vector(2 downto 0); RXVALID0 : out std_ulogic; RXVALID1 : out std_ulogic; TXBUFSTATUS0 : out std_logic_vector(1 downto 0); TXBUFSTATUS1 : out std_logic_vector(1 downto 0); TXGEARBOXREADY0 : out std_ulogic; TXGEARBOXREADY1 : out std_ulogic; TXKERR0 : out std_logic_vector(3 downto 0); TXKERR1 : out std_logic_vector(3 downto 0); TXN0 : out std_ulogic; TXN1 : out std_ulogic; TXOUTCLK0 : out std_ulogic; TXOUTCLK1 : out std_ulogic; TXP0 : out std_ulogic; TXP1 : out std_ulogic; TXRUNDISP0 : out std_logic_vector(3 downto 0); TXRUNDISP1 : out std_logic_vector(3 downto 0); CLKIN : in std_ulogic; DADDR : in std_logic_vector(6 downto 0); DCLK : in std_ulogic; DEN : in std_ulogic; DFECLKDLYADJ0 : in std_logic_vector(5 downto 0); DFECLKDLYADJ1 : in std_logic_vector(5 downto 0); DFETAP10 : in std_logic_vector(4 downto 0); DFETAP11 : in std_logic_vector(4 downto 0); DFETAP20 : in std_logic_vector(4 downto 0); DFETAP21 : in std_logic_vector(4 downto 0); DFETAP30 : in std_logic_vector(3 downto 0); DFETAP31 : in std_logic_vector(3 downto 0); DFETAP40 : in std_logic_vector(3 downto 0); DFETAP41 : in std_logic_vector(3 downto 0); DI : in std_logic_vector(15 downto 0); DWE : in std_ulogic; GSR : in std_ulogic; GTXRESET : in std_ulogic; GTXTEST : in std_logic_vector(13 downto 0); INTDATAWIDTH : in std_ulogic; LOOPBACK0 : in std_logic_vector(2 downto 0); LOOPBACK1 : in std_logic_vector(2 downto 0); PLLLKDETEN : in std_ulogic; PLLPOWERDOWN : in std_ulogic; PRBSCNTRESET0 : in std_ulogic; PRBSCNTRESET1 : in std_ulogic; REFCLKPWRDNB : in std_ulogic; RXBUFRESET0 : in std_ulogic; RXBUFRESET1 : in std_ulogic; RXCDRRESET0 : in std_ulogic; RXCDRRESET1 : in std_ulogic; RXCHBONDI0 : in std_logic_vector(3 downto 0); RXCHBONDI1 : in std_logic_vector(3 downto 0); RXCOMMADETUSE0 : in std_ulogic; RXCOMMADETUSE1 : in std_ulogic; RXDATAWIDTH0 : in std_logic_vector(1 downto 0); RXDATAWIDTH1 : in std_logic_vector(1 downto 0); RXDEC8B10BUSE0 : in std_ulogic; RXDEC8B10BUSE1 : in std_ulogic; RXENCHANSYNC0 : in std_ulogic; RXENCHANSYNC1 : in std_ulogic; RXENEQB0 : in std_ulogic; RXENEQB1 : in std_ulogic; RXENMCOMMAALIGN0 : in std_ulogic; RXENMCOMMAALIGN1 : in std_ulogic; RXENPCOMMAALIGN0 : in std_ulogic; RXENPCOMMAALIGN1 : in std_ulogic; RXENPMAPHASEALIGN0 : in std_ulogic; RXENPMAPHASEALIGN1 : in std_ulogic; RXENPRBSTST0 : in std_logic_vector(1 downto 0); RXENPRBSTST1 : in std_logic_vector(1 downto 0); RXENSAMPLEALIGN0 : in std_ulogic; RXENSAMPLEALIGN1 : in std_ulogic; RXEQMIX0 : in std_logic_vector(1 downto 0); RXEQMIX1 : in std_logic_vector(1 downto 0); RXEQPOLE0 : in std_logic_vector(3 downto 0); RXEQPOLE1 : in std_logic_vector(3 downto 0); RXGEARBOXSLIP0 : in std_ulogic; RXGEARBOXSLIP1 : in std_ulogic; RXN0 : in std_ulogic; RXN1 : in std_ulogic; RXP0 : in std_ulogic; RXP1 : in std_ulogic; RXPMASETPHASE0 : in std_ulogic; RXPMASETPHASE1 : in std_ulogic; RXPOLARITY0 : in std_ulogic; RXPOLARITY1 : in std_ulogic; RXPOWERDOWN0 : in std_logic_vector(1 downto 0); RXPOWERDOWN1 : in std_logic_vector(1 downto 0); RXRESET0 : in std_ulogic; RXRESET1 : in std_ulogic; RXSLIDE0 : in std_ulogic; RXSLIDE1 : in std_ulogic; RXUSRCLK0 : in std_ulogic; RXUSRCLK1 : in std_ulogic; RXUSRCLK20 : in std_ulogic; RXUSRCLK21 : in std_ulogic; TXBUFDIFFCTRL0 : in std_logic_vector(2 downto 0); TXBUFDIFFCTRL1 : in std_logic_vector(2 downto 0); TXBYPASS8B10B0 : in std_logic_vector(3 downto 0); TXBYPASS8B10B1 : in std_logic_vector(3 downto 0); TXCHARDISPMODE0 : in std_logic_vector(3 downto 0); TXCHARDISPMODE1 : in std_logic_vector(3 downto 0); TXCHARDISPVAL0 : in std_logic_vector(3 downto 0); TXCHARDISPVAL1 : in std_logic_vector(3 downto 0); TXCHARISK0 : in std_logic_vector(3 downto 0); TXCHARISK1 : in std_logic_vector(3 downto 0); TXCOMSTART0 : in std_ulogic; TXCOMSTART1 : in std_ulogic; TXCOMTYPE0 : in std_ulogic; TXCOMTYPE1 : in std_ulogic; TXDATA0 : in std_logic_vector(31 downto 0); TXDATA1 : in std_logic_vector(31 downto 0); TXDATAWIDTH0 : in std_logic_vector(1 downto 0); TXDATAWIDTH1 : in std_logic_vector(1 downto 0); TXDETECTRX0 : in std_ulogic; TXDETECTRX1 : in std_ulogic; TXDIFFCTRL0 : in std_logic_vector(2 downto 0); TXDIFFCTRL1 : in std_logic_vector(2 downto 0); TXELECIDLE0 : in std_ulogic; TXELECIDLE1 : in std_ulogic; TXENC8B10BUSE0 : in std_ulogic; TXENC8B10BUSE1 : in std_ulogic; TXENPMAPHASEALIGN0 : in std_ulogic; TXENPMAPHASEALIGN1 : in std_ulogic; TXENPRBSTST0 : in std_logic_vector(1 downto 0); TXENPRBSTST1 : in std_logic_vector(1 downto 0); TXHEADER0 : in std_logic_vector(2 downto 0); TXHEADER1 : in std_logic_vector(2 downto 0); TXINHIBIT0 : in std_ulogic; TXINHIBIT1 : in std_ulogic; TXPMASETPHASE0 : in std_ulogic; TXPMASETPHASE1 : in std_ulogic; TXPOLARITY0 : in std_ulogic; TXPOLARITY1 : in std_ulogic; TXPOWERDOWN0 : in std_logic_vector(1 downto 0); TXPOWERDOWN1 : in std_logic_vector(1 downto 0); TXPREEMPHASIS0 : in std_logic_vector(3 downto 0); TXPREEMPHASIS1 : in std_logic_vector(3 downto 0); TXRESET0 : in std_ulogic; TXRESET1 : in std_ulogic; TXSEQUENCE0 : in std_logic_vector(6 downto 0); TXSEQUENCE1 : in std_logic_vector(6 downto 0); TXSTARTSEQ0 : in std_ulogic; TXSTARTSEQ1 : in std_ulogic; TXUSRCLK0 : in std_ulogic; TXUSRCLK1 : in std_ulogic; TXUSRCLK20 : in std_ulogic; TXUSRCLK21 : in std_ulogic; STEPPING : in std_ulogic; AC_CAP_DIS_0 : in std_ulogic; AC_CAP_DIS_1 : in std_ulogic; ALIGN_COMMA_WORD_0 : in std_ulogic; ALIGN_COMMA_WORD_1 : in std_ulogic; CB2_INH_CC_PERIOD_0 : in std_logic_vector(3 downto 0); CB2_INH_CC_PERIOD_1 : in std_logic_vector(3 downto 0); CDR_PH_ADJ_TIME : in std_logic_vector(4 downto 0); CHAN_BOND_1_MAX_SKEW_0 : in std_logic_vector(3 downto 0); CHAN_BOND_1_MAX_SKEW_1 : in std_logic_vector(3 downto 0); CHAN_BOND_2_MAX_SKEW_0 : in std_logic_vector(3 downto 0); CHAN_BOND_2_MAX_SKEW_1 : in std_logic_vector(3 downto 0); CHAN_BOND_KEEP_ALIGN_0 : in std_ulogic; CHAN_BOND_KEEP_ALIGN_1 : in std_ulogic; CHAN_BOND_LEVEL_0 : in std_logic_vector(2 downto 0); CHAN_BOND_LEVEL_1 : in std_logic_vector(2 downto 0); CHAN_BOND_MODE_0 : in std_logic_vector(1 downto 0); CHAN_BOND_MODE_1 : in std_logic_vector(1 downto 0); CHAN_BOND_SEQ_1_1_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_1_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_2_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_2_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_3_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_3_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_4_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_4_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_1_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_1_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_2_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_2_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_3_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_3_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_4_0 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_4_1 : in std_logic_vector(9 downto 0); CHAN_BOND_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); CHAN_BOND_SEQ_2_USE_0 : in std_ulogic; CHAN_BOND_SEQ_2_USE_1 : in std_ulogic; CHAN_BOND_SEQ_LEN_0 : in std_logic_vector(1 downto 0); CHAN_BOND_SEQ_LEN_1 : in std_logic_vector(1 downto 0); CLK25_DIVIDER : in std_logic_vector(2 downto 0); CLKINDC_B : in std_ulogic; CLKRCV_TRST : in std_ulogic; CLK_CORRECT_USE_0 : in std_ulogic; CLK_CORRECT_USE_1 : in std_ulogic; CLK_COR_ADJ_LEN_0 : in std_logic_vector(1 downto 0); CLK_COR_ADJ_LEN_1 : in std_logic_vector(1 downto 0); CLK_COR_DET_LEN_0 : in std_logic_vector(1 downto 0); CLK_COR_DET_LEN_1 : in std_logic_vector(1 downto 0); CLK_COR_INSERT_IDLE_FLAG_0 : in std_ulogic; CLK_COR_INSERT_IDLE_FLAG_1 : in std_ulogic; CLK_COR_KEEP_IDLE_0 : in std_ulogic; CLK_COR_KEEP_IDLE_1 : in std_ulogic; CLK_COR_MAX_LAT_0 : in std_logic_vector(5 downto 0); CLK_COR_MAX_LAT_1 : in std_logic_vector(5 downto 0); CLK_COR_MIN_LAT_0 : in std_logic_vector(5 downto 0); CLK_COR_MIN_LAT_1 : in std_logic_vector(5 downto 0); CLK_COR_PRECEDENCE_0 : in std_ulogic; CLK_COR_PRECEDENCE_1 : in std_ulogic; CLK_COR_REPEAT_WAIT_0 : in std_logic_vector(4 downto 0); CLK_COR_REPEAT_WAIT_1 : in std_logic_vector(4 downto 0); CLK_COR_SEQ_1_1_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_1_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_2_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_2_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_3_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_3_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_4_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_4_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_1_ENABLE_0 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_1_ENABLE_1 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_1_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_1_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_2_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_2_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_3_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_3_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_4_0 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_4_1 : in std_logic_vector(9 downto 0); CLK_COR_SEQ_2_ENABLE_0 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_ENABLE_1 : in std_logic_vector(3 downto 0); CLK_COR_SEQ_2_USE_0 : in std_ulogic; CLK_COR_SEQ_2_USE_1 : in std_ulogic; CM_TRIM_0 : in std_logic_vector(1 downto 0); CM_TRIM_1 : in std_logic_vector(1 downto 0); COMMA_10B_ENABLE_0 : in std_logic_vector(9 downto 0); COMMA_10B_ENABLE_1 : in std_logic_vector(9 downto 0); COMMA_DOUBLE_0 : in std_ulogic; COMMA_DOUBLE_1 : in std_ulogic; COM_BURST_VAL_0 : in std_logic_vector(3 downto 0); COM_BURST_VAL_1 : in std_logic_vector(3 downto 0); DEC_MCOMMA_DETECT_0 : in std_ulogic; DEC_MCOMMA_DETECT_1 : in std_ulogic; DEC_PCOMMA_DETECT_0 : in std_ulogic; DEC_PCOMMA_DETECT_1 : in std_ulogic; DEC_VALID_COMMA_ONLY_0 : in std_ulogic; DEC_VALID_COMMA_ONLY_1 : in std_ulogic; DFE_CAL_TIME : in std_logic_vector(4 downto 0); DFE_CFG_0 : in std_logic_vector(9 downto 0); DFE_CFG_1 : in std_logic_vector(9 downto 0); GEARBOX_ENDEC_0 : in std_logic_vector(2 downto 0); GEARBOX_ENDEC_1 : in std_logic_vector(2 downto 0); MCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); MCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); MCOMMA_DETECT_0 : in std_ulogic; MCOMMA_DETECT_1 : in std_ulogic; OOBDETECT_THRESHOLD_0 : in std_logic_vector(2 downto 0); OOBDETECT_THRESHOLD_1 : in std_logic_vector(2 downto 0); OOB_CLK_DIVIDER : in std_logic_vector(2 downto 0); OVERSAMPLE_MODE : in std_ulogic; PCI_EXPRESS_MODE_0 : in std_ulogic; PCI_EXPRESS_MODE_1 : in std_ulogic; PCOMMA_10B_VALUE_0 : in std_logic_vector(9 downto 0); PCOMMA_10B_VALUE_1 : in std_logic_vector(9 downto 0); PCOMMA_DETECT_0 : in std_ulogic; PCOMMA_DETECT_1 : in std_ulogic; PLL_COM_CFG : in std_logic_vector(23 downto 0); PLL_CP_CFG : in std_logic_vector(7 downto 0); PLL_DIVSEL_FB : in std_logic_vector(4 downto 0); PLL_DIVSEL_REF : in std_logic_vector(5 downto 0); PLL_FB_DCCEN : in std_ulogic; PLL_LKDET_CFG : in std_logic_vector(2 downto 0); PLL_RXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); PLL_RXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); PLL_SATA_0 : in std_ulogic; PLL_SATA_1 : in std_ulogic; PLL_TDCC_CFG : in std_logic_vector(2 downto 0); PLL_TXDIVSEL_OUT_0 : in std_logic_vector(1 downto 0); PLL_TXDIVSEL_OUT_1 : in std_logic_vector(1 downto 0); PMA_CDR_SCAN_0 : in std_logic_vector(26 downto 0); PMA_CDR_SCAN_1 : in std_logic_vector(26 downto 0); PMA_COM_CFG : in std_logic_vector(68 downto 0); PMA_RXSYNC_CFG_0 : in std_logic_vector(6 downto 0); PMA_RXSYNC_CFG_1 : in std_logic_vector(6 downto 0); PMA_RX_CFG_0 : in std_logic_vector(24 downto 0); PMA_RX_CFG_1 : in std_logic_vector(24 downto 0); PMA_TX_CFG_0 : in std_logic_vector(19 downto 0); PMA_TX_CFG_1 : in std_logic_vector(19 downto 0); PRBS_ERR_THRESHOLD_0 : in std_logic_vector(31 downto 0); PRBS_ERR_THRESHOLD_1 : in std_logic_vector(31 downto 0); RCV_TERM_GND_0 : in std_ulogic; RCV_TERM_GND_1 : in std_ulogic; RCV_TERM_VTTRX_0 : in std_ulogic; RCV_TERM_VTTRX_1 : in std_ulogic; RXGEARBOX_USE_0 : in std_ulogic; RXGEARBOX_USE_1 : in std_ulogic; RX_BUFFER_USE_0 : in std_ulogic; RX_BUFFER_USE_1 : in std_ulogic; RX_DECODE_SEQ_MATCH_0 : in std_ulogic; RX_DECODE_SEQ_MATCH_1 : in std_ulogic; RX_EN_IDLE_HOLD_CDR : in std_ulogic; RX_EN_IDLE_HOLD_DFE_0 : in std_ulogic; RX_EN_IDLE_HOLD_DFE_1 : in std_ulogic; RX_EN_IDLE_RESET_BUF_0 : in std_ulogic; RX_EN_IDLE_RESET_BUF_1 : in std_ulogic; RX_EN_IDLE_RESET_FR : in std_ulogic; RX_EN_IDLE_RESET_PH : in std_ulogic; RX_IDLE_HI_CNT_0 : in std_logic_vector(3 downto 0); RX_IDLE_HI_CNT_1 : in std_logic_vector(3 downto 0); RX_IDLE_LO_CNT_0 : in std_logic_vector(3 downto 0); RX_IDLE_LO_CNT_1 : in std_logic_vector(3 downto 0); RX_LOSS_OF_SYNC_FSM_0 : in std_ulogic; RX_LOSS_OF_SYNC_FSM_1 : in std_ulogic; RX_LOS_INVALID_INCR_0 : in std_logic_vector(2 downto 0); RX_LOS_INVALID_INCR_1 : in std_logic_vector(2 downto 0); RX_LOS_THRESHOLD_0 : in std_logic_vector(2 downto 0); RX_LOS_THRESHOLD_1 : in std_logic_vector(2 downto 0); RX_SLIDE_MODE_0 : in std_ulogic; RX_SLIDE_MODE_1 : in std_ulogic; RX_STATUS_FMT_0 : in std_ulogic; RX_STATUS_FMT_1 : in std_ulogic; RX_XCLK_SEL_0 : in std_ulogic; RX_XCLK_SEL_1 : in std_ulogic; SATA_BURST_VAL_0 : in std_logic_vector(2 downto 0); SATA_BURST_VAL_1 : in std_logic_vector(2 downto 0); SATA_IDLE_VAL_0 : in std_logic_vector(2 downto 0); SATA_IDLE_VAL_1 : in std_logic_vector(2 downto 0); SATA_MAX_BURST_0 : in std_logic_vector(5 downto 0); SATA_MAX_BURST_1 : in std_logic_vector(5 downto 0); SATA_MAX_INIT_0 : in std_logic_vector(5 downto 0); SATA_MAX_INIT_1 : in std_logic_vector(5 downto 0); SATA_MAX_WAKE_0 : in std_logic_vector(5 downto 0); SATA_MAX_WAKE_1 : in std_logic_vector(5 downto 0); SATA_MIN_BURST_0 : in std_logic_vector(5 downto 0); SATA_MIN_BURST_1 : in std_logic_vector(5 downto 0); SATA_MIN_INIT_0 : in std_logic_vector(5 downto 0); SATA_MIN_INIT_1 : in std_logic_vector(5 downto 0); SATA_MIN_WAKE_0 : in std_logic_vector(5 downto 0); SATA_MIN_WAKE_1 : in std_logic_vector(5 downto 0); SIM_GTXRESET_SPEEDUP : in std_ulogic; SIM_PLL_PERDIV2 : in std_logic_vector(8 downto 0); SIM_RECEIVER_DETECT_PASS_0 : in std_ulogic; SIM_RECEIVER_DETECT_PASS_1 : in std_ulogic; TERMINATION_CTRL : in std_logic_vector(4 downto 0); TERMINATION_IMP_0 : in std_ulogic; TERMINATION_IMP_1 : in std_ulogic; TERMINATION_OVRD : in std_ulogic; TRANS_TIME_FROM_P2_0 : in std_logic_vector(11 downto 0); TRANS_TIME_FROM_P2_1 : in std_logic_vector(11 downto 0); TRANS_TIME_NON_P2_0 : in std_logic_vector(7 downto 0); TRANS_TIME_NON_P2_1 : in std_logic_vector(7 downto 0); TRANS_TIME_TO_P2_0 : in std_logic_vector(9 downto 0); TRANS_TIME_TO_P2_1 : in std_logic_vector(9 downto 0); TXGEARBOX_USE_0 : in std_ulogic; TXGEARBOX_USE_1 : in std_ulogic; TXRX_INVERT_0 : in std_logic_vector(2 downto 0); TXRX_INVERT_1 : in std_logic_vector(2 downto 0); TX_BUFFER_USE_0 : in std_ulogic; TX_BUFFER_USE_1 : in std_ulogic; TX_DETECT_RX_CFG_0 : in std_logic_vector(13 downto 0); TX_DETECT_RX_CFG_1 : in std_logic_vector(13 downto 0); TX_IDLE_DELAY_0 : in std_logic_vector(2 downto 0); TX_IDLE_DELAY_1 : in std_logic_vector(2 downto 0); TX_XCLK_SEL_0 : in std_ulogic; TX_XCLK_SEL_1 : in std_ulogic ); end component; constant IN_DELAY : time := 0 ps; constant OUT_DELAY : time := 0 ps; constant CLK_DELAY : time := 0 ps; constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); signal PLL_TXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); signal PLL_RXDIVSEL_OUT_0_BINARY : std_logic_vector(1 downto 0); signal PLL_TXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); signal PLL_RXDIVSEL_OUT_1_BINARY : std_logic_vector(1 downto 0); signal PLL_DIVSEL_FB_BINARY : std_logic_vector(4 downto 0); signal PLL_DIVSEL_REF_BINARY : std_logic_vector(5 downto 0); signal PLL_SATA_0_BINARY : std_ulogic; signal PLL_SATA_1_BINARY : std_ulogic; signal OOBDETECT_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_0)(2 downto 0); signal OOBDETECT_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(OOBDETECT_THRESHOLD_1)(2 downto 0); signal PMA_CDR_SCAN_0_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_0)(26 downto 0); signal PMA_CDR_SCAN_1_BINARY : std_logic_vector(26 downto 0) := To_StdLogicVector(PMA_CDR_SCAN_1)(26 downto 0); signal PMA_RX_CFG_0_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_0)(24 downto 0); signal PMA_RX_CFG_1_BINARY : std_logic_vector(24 downto 0) := To_StdLogicVector(PMA_RX_CFG_1)(24 downto 0); signal PLL_TDCC_CFG_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PLL_TDCC_CFG); signal PMA_COM_CFG_BINARY : std_logic_vector(68 downto 0) := To_StdLogicVector(PMA_COM_CFG)(68 downto 0); signal PMA_RXSYNC_CFG_0_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(PMA_RXSYNC_CFG_0)(6 downto 0); signal PMA_RXSYNC_CFG_1_BINARY : std_logic_vector(6 downto 0) := To_StdLogicVector(PMA_RXSYNC_CFG_1)(6 downto 0); signal OOB_CLK_DIVIDER_BINARY : std_logic_vector(2 downto 0); signal STEPPING_BINARY : std_ulogic := '0'; signal AC_CAP_DIS_0_BINARY : std_ulogic; signal AC_CAP_DIS_1_BINARY : std_ulogic; signal RCV_TERM_GND_0_BINARY : std_ulogic; signal RCV_TERM_GND_1_BINARY : std_ulogic; signal TERMINATION_IMP_0_BINARY : std_ulogic; signal TERMINATION_IMP_1_BINARY : std_ulogic; signal TERMINATION_OVRD_BINARY : std_ulogic; signal TERMINATION_CTRL_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(TERMINATION_CTRL)(4 downto 0); signal RCV_TERM_VTTRX_0_BINARY : std_ulogic; signal RCV_TERM_VTTRX_1_BINARY : std_ulogic; signal PLL_LKDET_CFG_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(PLL_LKDET_CFG); signal TXRX_INVERT_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXRX_INVERT_0)(2 downto 0); signal TXRX_INVERT_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TXRX_INVERT_1)(2 downto 0); signal CLKINDC_B_BINARY : std_ulogic; signal PCOMMA_DETECT_0_BINARY : std_ulogic; signal MCOMMA_DETECT_0_BINARY : std_ulogic; signal PCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_0)(9 downto 0); signal MCOMMA_10B_VALUE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_0)(9 downto 0); signal COMMA_10B_ENABLE_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_0)(9 downto 0); signal COMMA_DOUBLE_0_BINARY : std_ulogic; signal ALIGN_COMMA_WORD_0_BINARY : std_ulogic; signal DEC_PCOMMA_DETECT_0_BINARY : std_ulogic; signal DEC_MCOMMA_DETECT_0_BINARY : std_ulogic; signal DEC_VALID_COMMA_ONLY_0_BINARY : std_ulogic; signal PCOMMA_DETECT_1_BINARY : std_ulogic; signal MCOMMA_DETECT_1_BINARY : std_ulogic; signal PCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(PCOMMA_10B_VALUE_1)(9 downto 0); signal MCOMMA_10B_VALUE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(MCOMMA_10B_VALUE_1)(9 downto 0); signal COMMA_10B_ENABLE_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(COMMA_10B_ENABLE_1)(9 downto 0); signal COMMA_DOUBLE_1_BINARY : std_ulogic; signal ALIGN_COMMA_WORD_1_BINARY : std_ulogic; signal DEC_PCOMMA_DETECT_1_BINARY : std_ulogic; signal DEC_MCOMMA_DETECT_1_BINARY : std_ulogic; signal DEC_VALID_COMMA_ONLY_1_BINARY : std_ulogic; signal RX_LOSS_OF_SYNC_FSM_0_BINARY : std_ulogic; signal RX_LOS_INVALID_INCR_0_BINARY : std_logic_vector(2 downto 0); signal RX_LOS_THRESHOLD_0_BINARY : std_logic_vector(2 downto 0); signal RX_LOSS_OF_SYNC_FSM_1_BINARY : std_ulogic; signal RX_LOS_INVALID_INCR_1_BINARY : std_logic_vector(2 downto 0); signal RX_LOS_THRESHOLD_1_BINARY : std_logic_vector(2 downto 0); signal RX_BUFFER_USE_0_BINARY : std_ulogic; signal RX_DECODE_SEQ_MATCH_0_BINARY : std_ulogic; signal RX_BUFFER_USE_1_BINARY : std_ulogic; signal RX_DECODE_SEQ_MATCH_1_BINARY : std_ulogic; signal CLK_COR_MIN_LAT_0_BINARY : std_logic_vector(5 downto 0); signal CLK_COR_MAX_LAT_0_BINARY : std_logic_vector(5 downto 0); signal CLK_CORRECT_USE_0_BINARY : std_ulogic; signal CLK_COR_PRECEDENCE_0_BINARY : std_ulogic; signal CLK_COR_DET_LEN_0_BINARY : std_logic_vector(1 downto 0); signal CLK_COR_ADJ_LEN_0_BINARY : std_logic_vector(1 downto 0); signal CLK_COR_KEEP_IDLE_0_BINARY : std_ulogic; signal CLK_COR_INSERT_IDLE_FLAG_0_BINARY : std_ulogic; signal CLK_COR_REPEAT_WAIT_0_BINARY : std_logic_vector(4 downto 0); signal CLK_COR_SEQ_2_USE_0_BINARY : std_ulogic; signal CLK_COR_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_0)(9 downto 0); signal CLK_COR_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_0)(9 downto 0); signal CLK_COR_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_0)(9 downto 0); signal CLK_COR_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_0)(9 downto 0); signal CLK_COR_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_0)(9 downto 0); signal CLK_COR_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_0)(9 downto 0); signal CLK_COR_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_0)(9 downto 0); signal CLK_COR_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_0)(9 downto 0); signal CLK_COR_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_0)(3 downto 0); signal CLK_COR_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_0)(3 downto 0); signal CLK_COR_MIN_LAT_1_BINARY : std_logic_vector(5 downto 0); signal CLK_COR_MAX_LAT_1_BINARY : std_logic_vector(5 downto 0); signal CLK_CORRECT_USE_1_BINARY : std_ulogic; signal CLK_COR_PRECEDENCE_1_BINARY : std_ulogic; signal CLK_COR_DET_LEN_1_BINARY : std_logic_vector(1 downto 0); signal CLK_COR_ADJ_LEN_1_BINARY : std_logic_vector(1 downto 0); signal CLK_COR_KEEP_IDLE_1_BINARY : std_ulogic; signal CLK_COR_INSERT_IDLE_FLAG_1_BINARY : std_ulogic; signal CLK_COR_REPEAT_WAIT_1_BINARY : std_logic_vector(4 downto 0); signal CLK_COR_SEQ_2_USE_1_BINARY : std_ulogic; signal CLK_COR_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_1_1)(9 downto 0); signal CLK_COR_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_2_1)(9 downto 0); signal CLK_COR_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_3_1)(9 downto 0); signal CLK_COR_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_4_1)(9 downto 0); signal CLK_COR_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_1_1)(9 downto 0); signal CLK_COR_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_2_1)(9 downto 0); signal CLK_COR_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_3_1)(9 downto 0); signal CLK_COR_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_4_1)(9 downto 0); signal CLK_COR_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_1_ENABLE_1)(3 downto 0); signal CLK_COR_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CLK_COR_SEQ_2_ENABLE_1)(3 downto 0); signal CHAN_BOND_MODE_0_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_LEVEL_0_BINARY : std_logic_vector(2 downto 0); signal CHAN_BOND_SEQ_LEN_0_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_SEQ_2_USE_0_BINARY : std_ulogic; signal CHAN_BOND_SEQ_1_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_0)(9 downto 0); signal CHAN_BOND_SEQ_1_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_0)(9 downto 0); signal CHAN_BOND_SEQ_1_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_0)(9 downto 0); signal CHAN_BOND_SEQ_1_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_0)(9 downto 0); signal CHAN_BOND_SEQ_2_1_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_0)(9 downto 0); signal CHAN_BOND_SEQ_2_2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_0)(9 downto 0); signal CHAN_BOND_SEQ_2_3_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_0)(9 downto 0); signal CHAN_BOND_SEQ_2_4_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_0)(9 downto 0); signal CHAN_BOND_SEQ_1_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_0)(3 downto 0); signal CHAN_BOND_SEQ_2_ENABLE_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_0)(3 downto 0); signal CHAN_BOND_1_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); signal CHAN_BOND_2_MAX_SKEW_0_BINARY : std_logic_vector(3 downto 0); signal CHAN_BOND_KEEP_ALIGN_0_BINARY : std_ulogic; signal CB2_INH_CC_PERIOD_0_BINARY : std_logic_vector(3 downto 0); signal CHAN_BOND_MODE_1_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_LEVEL_1_BINARY : std_logic_vector(2 downto 0); signal CHAN_BOND_SEQ_LEN_1_BINARY : std_logic_vector(1 downto 0); signal CHAN_BOND_SEQ_2_USE_1_BINARY : std_ulogic; signal CHAN_BOND_SEQ_1_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_1_1)(9 downto 0); signal CHAN_BOND_SEQ_1_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_2_1)(9 downto 0); signal CHAN_BOND_SEQ_1_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_3_1)(9 downto 0); signal CHAN_BOND_SEQ_1_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_4_1)(9 downto 0); signal CHAN_BOND_SEQ_2_1_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_1_1)(9 downto 0); signal CHAN_BOND_SEQ_2_2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_2_1)(9 downto 0); signal CHAN_BOND_SEQ_2_3_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_3_1)(9 downto 0); signal CHAN_BOND_SEQ_2_4_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_4_1)(9 downto 0); signal CHAN_BOND_SEQ_1_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_1_ENABLE_1)(3 downto 0); signal CHAN_BOND_SEQ_2_ENABLE_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(CHAN_BOND_SEQ_2_ENABLE_1)(3 downto 0); signal CHAN_BOND_1_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); signal CHAN_BOND_2_MAX_SKEW_1_BINARY : std_logic_vector(3 downto 0); signal CHAN_BOND_KEEP_ALIGN_1_BINARY : std_ulogic; signal CB2_INH_CC_PERIOD_1_BINARY : std_logic_vector(3 downto 0); signal PCI_EXPRESS_MODE_0_BINARY : std_ulogic; signal TRANS_TIME_FROM_P2_0_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_0)(11 downto 0); signal TRANS_TIME_NON_P2_0_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_0)(7 downto 0); signal TRANS_TIME_TO_P2_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_0)(9 downto 0); signal PCI_EXPRESS_MODE_1_BINARY : std_ulogic; signal TRANS_TIME_FROM_P2_1_BINARY : std_logic_vector(11 downto 0) := To_StdLogicVector(TRANS_TIME_FROM_P2_1)(11 downto 0); signal TRANS_TIME_NON_P2_1_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(TRANS_TIME_NON_P2_1)(7 downto 0); signal TRANS_TIME_TO_P2_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(TRANS_TIME_TO_P2_1)(9 downto 0); signal RX_STATUS_FMT_0_BINARY : std_ulogic; signal TX_BUFFER_USE_0_BINARY : std_ulogic; signal TX_XCLK_SEL_0_BINARY : std_ulogic; signal RX_XCLK_SEL_0_BINARY : std_ulogic; signal RX_STATUS_FMT_1_BINARY : std_ulogic; signal TX_BUFFER_USE_1_BINARY : std_ulogic; signal TX_XCLK_SEL_1_BINARY : std_ulogic; signal RX_XCLK_SEL_1_BINARY : std_ulogic; signal PRBS_ERR_THRESHOLD_0_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_0)(31 downto 0); signal RX_SLIDE_MODE_0_BINARY : std_ulogic; signal PRBS_ERR_THRESHOLD_1_BINARY : std_logic_vector(31 downto 0) := To_StdLogicVector(PRBS_ERR_THRESHOLD_1)(31 downto 0); signal RX_SLIDE_MODE_1_BINARY : std_ulogic; signal SATA_MIN_BURST_0_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_BURST_0_BINARY : std_logic_vector(5 downto 0); signal SATA_MIN_INIT_0_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_INIT_0_BINARY : std_logic_vector(5 downto 0); signal SATA_MIN_WAKE_0_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_WAKE_0_BINARY : std_logic_vector(5 downto 0); signal TX_DETECT_RX_CFG_0_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(TX_DETECT_RX_CFG_0)(13 downto 0); signal SATA_BURST_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_0)(2 downto 0); signal SATA_IDLE_VAL_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_0)(2 downto 0); signal COM_BURST_VAL_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_0)(3 downto 0); signal SATA_MIN_BURST_1_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_BURST_1_BINARY : std_logic_vector(5 downto 0); signal SATA_MIN_INIT_1_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_INIT_1_BINARY : std_logic_vector(5 downto 0); signal SATA_MIN_WAKE_1_BINARY : std_logic_vector(5 downto 0); signal SATA_MAX_WAKE_1_BINARY : std_logic_vector(5 downto 0); signal TX_DETECT_RX_CFG_1_BINARY : std_logic_vector(13 downto 0) := To_StdLogicVector(TX_DETECT_RX_CFG_1)(13 downto 0); signal SATA_BURST_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_BURST_VAL_1)(2 downto 0); signal SATA_IDLE_VAL_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(SATA_IDLE_VAL_1)(2 downto 0); signal COM_BURST_VAL_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(COM_BURST_VAL_1)(3 downto 0); signal CLK25_DIVIDER_BINARY : std_logic_vector(2 downto 0); signal PLL_COM_CFG_BINARY : std_logic_vector(23 downto 0) := To_StdLogicVector(PLL_COM_CFG); signal PLL_CP_CFG_BINARY : std_logic_vector(7 downto 0) := To_StdLogicVector(PLL_CP_CFG); signal OVERSAMPLE_MODE_BINARY : std_ulogic; signal TXGEARBOX_USE_0_BINARY : std_ulogic; signal RXGEARBOX_USE_0_BINARY : std_ulogic; signal GEARBOX_ENDEC_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(GEARBOX_ENDEC_0)(2 downto 0); signal TXGEARBOX_USE_1_BINARY : std_ulogic; signal RXGEARBOX_USE_1_BINARY : std_ulogic; signal GEARBOX_ENDEC_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(GEARBOX_ENDEC_1)(2 downto 0); signal DFE_CFG_0_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(DFE_CFG_0)(9 downto 0); signal DFE_CFG_1_BINARY : std_logic_vector(9 downto 0) := To_StdLogicVector(DFE_CFG_1)(9 downto 0); signal PMA_TX_CFG_0_BINARY : std_logic_vector(19 downto 0) := To_StdLogicVector(PMA_TX_CFG_0)(19 downto 0); signal CM_TRIM_0_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(CM_TRIM_0)(1 downto 0); signal PMA_TX_CFG_1_BINARY : std_logic_vector(19 downto 0) := To_StdLogicVector(PMA_TX_CFG_1)(19 downto 0); signal CM_TRIM_1_BINARY : std_logic_vector(1 downto 0) := To_StdLogicVector(CM_TRIM_1)(1 downto 0); signal PLL_FB_DCCEN_BINARY : std_ulogic; signal CLKRCV_TRST_BINARY : std_ulogic; signal TX_IDLE_DELAY_0_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_IDLE_DELAY_0)(2 downto 0); signal RX_EN_IDLE_HOLD_DFE_0_BINARY : std_ulogic; signal RX_EN_IDLE_RESET_BUF_0_BINARY : std_ulogic; signal RX_IDLE_HI_CNT_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_HI_CNT_0)(3 downto 0); signal RX_IDLE_LO_CNT_0_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_LO_CNT_0)(3 downto 0); signal TX_IDLE_DELAY_1_BINARY : std_logic_vector(2 downto 0) := To_StdLogicVector(TX_IDLE_DELAY_1)(2 downto 0); signal RX_EN_IDLE_HOLD_DFE_1_BINARY : std_ulogic; signal RX_EN_IDLE_RESET_BUF_1_BINARY : std_ulogic; signal RX_IDLE_HI_CNT_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_HI_CNT_1)(3 downto 0); signal RX_IDLE_LO_CNT_1_BINARY : std_logic_vector(3 downto 0) := To_StdLogicVector(RX_IDLE_LO_CNT_1)(3 downto 0); signal RX_EN_IDLE_HOLD_CDR_BINARY : std_ulogic; signal RX_EN_IDLE_RESET_PH_BINARY : std_ulogic; signal RX_EN_IDLE_RESET_FR_BINARY : std_ulogic; signal DFE_CAL_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(DFE_CAL_TIME)(4 downto 0); signal CDR_PH_ADJ_TIME_BINARY : std_logic_vector(4 downto 0) := To_StdLogicVector(CDR_PH_ADJ_TIME)(4 downto 0); signal SIM_GTXRESET_SPEEDUP_BINARY : std_ulogic; signal SIM_MODE_BINARY : std_ulogic; signal SIM_PLL_PERDIV2_BINARY : std_logic_vector(8 downto 0) := To_StdLogicVector(SIM_PLL_PERDIV2)(8 downto 0); signal SIM_RECEIVER_DETECT_PASS_0_BINARY : std_ulogic; signal SIM_RECEIVER_DETECT_PASS_1_BINARY : std_ulogic; signal REFCLKOUT_out : std_ulogic; signal RXRECCLK0_out : std_ulogic; signal TXOUTCLK0_out : std_ulogic; signal RXRECCLK1_out : std_ulogic; signal TXOUTCLK1_out : std_ulogic; signal TXP0_out : std_ulogic; signal TXN0_out : std_ulogic; signal TXP1_out : std_ulogic; signal TXN1_out : std_ulogic; signal RXDATA0_out : std_logic_vector(31 downto 0); signal RXNOTINTABLE0_out : std_logic_vector(3 downto 0); signal RXDISPERR0_out : std_logic_vector(3 downto 0); signal RXCHARISK0_out : std_logic_vector(3 downto 0); signal RXRUNDISP0_out : std_logic_vector(3 downto 0); signal RXCHARISCOMMA0_out : std_logic_vector(3 downto 0); signal RXVALID0_out : std_ulogic; signal RXDATA1_out : std_logic_vector(31 downto 0); signal RXNOTINTABLE1_out : std_logic_vector(3 downto 0); signal RXDISPERR1_out : std_logic_vector(3 downto 0); signal RXCHARISK1_out : std_logic_vector(3 downto 0); signal RXRUNDISP1_out : std_logic_vector(3 downto 0); signal RXCHARISCOMMA1_out : std_logic_vector(3 downto 0); signal RXVALID1_out : std_ulogic; signal RESETDONE0_out : std_ulogic; signal RESETDONE1_out : std_ulogic; signal TXKERR0_out : std_logic_vector(3 downto 0); signal TXRUNDISP0_out : std_logic_vector(3 downto 0); signal TXBUFSTATUS0_out : std_logic_vector(1 downto 0); signal TXKERR1_out : std_logic_vector(3 downto 0); signal TXRUNDISP1_out : std_logic_vector(3 downto 0); signal TXBUFSTATUS1_out : std_logic_vector(1 downto 0); signal RXCOMMADET0_out : std_ulogic; signal RXBYTEREALIGN0_out : std_ulogic; signal RXBYTEISALIGNED0_out : std_ulogic; signal RXLOSSOFSYNC0_out : std_logic_vector(1 downto 0); signal RXCHBONDO0_out : std_logic_vector(3 downto 0); signal RXCHANBONDSEQ0_out : std_ulogic; signal RXCHANREALIGN0_out : std_ulogic; signal RXCHANISALIGNED0_out : std_ulogic; signal RXBUFSTATUS0_out : std_logic_vector(2 downto 0); signal RXCOMMADET1_out : std_ulogic; signal RXBYTEREALIGN1_out : std_ulogic; signal RXBYTEISALIGNED1_out : std_ulogic; signal RXLOSSOFSYNC1_out : std_logic_vector(1 downto 0); signal RXCHBONDO1_out : std_logic_vector(3 downto 0); signal RXCHANBONDSEQ1_out : std_ulogic; signal RXCHANREALIGN1_out : std_ulogic; signal RXCHANISALIGNED1_out : std_ulogic; signal RXBUFSTATUS1_out : std_logic_vector(2 downto 0); signal PHYSTATUS0_out : std_ulogic; signal PHYSTATUS1_out : std_ulogic; signal RXELECIDLE0_out : std_ulogic; signal RXSTATUS0_out : std_logic_vector(2 downto 0); signal RXCLKCORCNT0_out : std_logic_vector(2 downto 0); signal RXELECIDLE1_out : std_ulogic; signal RXSTATUS1_out : std_logic_vector(2 downto 0); signal RXCLKCORCNT1_out : std_logic_vector(2 downto 0); signal PLLLKDET_out : std_ulogic; signal RXPRBSERR0_out : std_ulogic; signal RXPRBSERR1_out : std_ulogic; signal DO_out : std_logic_vector(15 downto 0); signal DRDY_out : std_ulogic; signal RXOVERSAMPLEERR0_out : std_ulogic; signal RXOVERSAMPLEERR1_out : std_ulogic; signal TXGEARBOXREADY0_out : std_ulogic; signal RXHEADER0_out : std_logic_vector(2 downto 0); signal RXHEADERVALID0_out : std_ulogic; signal RXDATAVALID0_out : std_ulogic; signal RXSTARTOFSEQ0_out : std_ulogic; signal TXGEARBOXREADY1_out : std_ulogic; signal RXHEADER1_out : std_logic_vector(2 downto 0); signal RXHEADERVALID1_out : std_ulogic; signal RXDATAVALID1_out : std_ulogic; signal RXSTARTOFSEQ1_out : std_ulogic; signal DFECLKDLYADJMONITOR0_out : std_logic_vector(5 downto 0); signal DFEEYEDACMONITOR0_out : std_logic_vector(4 downto 0); signal DFETAP1MONITOR0_out : std_logic_vector(4 downto 0); signal DFETAP2MONITOR0_out : std_logic_vector(4 downto 0); signal DFETAP3MONITOR0_out : std_logic_vector(3 downto 0); signal DFETAP4MONITOR0_out : std_logic_vector(3 downto 0); signal DFECLKDLYADJMONITOR1_out : std_logic_vector(5 downto 0); signal DFEEYEDACMONITOR1_out : std_logic_vector(4 downto 0); signal DFETAP1MONITOR1_out : std_logic_vector(4 downto 0); signal DFETAP2MONITOR1_out : std_logic_vector(4 downto 0); signal DFETAP3MONITOR1_out : std_logic_vector(3 downto 0); signal DFETAP4MONITOR1_out : std_logic_vector(3 downto 0); signal DFESENSCAL0_out : std_logic_vector(2 downto 0); signal DFESENSCAL1_out : std_logic_vector(2 downto 0); signal REFCLKOUT_outdelay : std_logic; signal RXRECCLK0_outdelay : std_logic; signal TXOUTCLK0_outdelay : std_logic; signal RXRECCLK1_outdelay : std_logic; signal TXOUTCLK1_outdelay : std_logic; signal RXCLKCORCNT0_outdelay : std_logic_vector(2 downto 0); signal RXCLKCORCNT1_outdelay : std_logic_vector(2 downto 0); signal DFECLKDLYADJMONITOR0_outdelay : std_logic_vector(5 downto 0); signal DFECLKDLYADJMONITOR1_outdelay : std_logic_vector(5 downto 0); signal TXP0_outdelay : std_logic; signal TXN0_outdelay : std_logic; signal TXP1_outdelay : std_logic; signal TXN1_outdelay : std_logic; signal RXDATA0_outdelay : std_logic_vector(31 downto 0); signal RXNOTINTABLE0_outdelay : std_logic_vector(3 downto 0); signal RXDISPERR0_outdelay : std_logic_vector(3 downto 0); signal RXCHARISK0_outdelay : std_logic_vector(3 downto 0); signal RXRUNDISP0_outdelay : std_logic_vector(3 downto 0); signal RXCHARISCOMMA0_outdelay : std_logic_vector(3 downto 0); signal RXVALID0_outdelay : std_logic; signal RXDATA1_outdelay : std_logic_vector(31 downto 0); signal RXNOTINTABLE1_outdelay : std_logic_vector(3 downto 0); signal RXDISPERR1_outdelay : std_logic_vector(3 downto 0); signal RXCHARISK1_outdelay : std_logic_vector(3 downto 0); signal RXRUNDISP1_outdelay : std_logic_vector(3 downto 0); signal RXCHARISCOMMA1_outdelay : std_logic_vector(3 downto 0); signal RXVALID1_outdelay : std_logic; signal RESETDONE0_outdelay : std_logic; signal RESETDONE1_outdelay : std_logic; signal TXKERR0_outdelay : std_logic_vector(3 downto 0); signal TXRUNDISP0_outdelay : std_logic_vector(3 downto 0); signal TXBUFSTATUS0_outdelay : std_logic_vector(1 downto 0); signal TXKERR1_outdelay : std_logic_vector(3 downto 0); signal TXRUNDISP1_outdelay : std_logic_vector(3 downto 0); signal TXBUFSTATUS1_outdelay : std_logic_vector(1 downto 0); signal RXCOMMADET0_outdelay : std_logic; signal RXBYTEREALIGN0_outdelay : std_logic; signal RXBYTEISALIGNED0_outdelay : std_logic; signal RXLOSSOFSYNC0_outdelay : std_logic_vector(1 downto 0); signal RXCHBONDO0_outdelay : std_logic_vector(3 downto 0); signal RXCHANBONDSEQ0_outdelay : std_logic; signal RXCHANREALIGN0_outdelay : std_logic; signal RXCHANISALIGNED0_outdelay : std_logic; signal RXBUFSTATUS0_outdelay : std_logic_vector(2 downto 0); signal RXCOMMADET1_outdelay : std_logic; signal RXBYTEREALIGN1_outdelay : std_logic; signal RXBYTEISALIGNED1_outdelay : std_logic; signal RXLOSSOFSYNC1_outdelay : std_logic_vector(1 downto 0); signal RXCHBONDO1_outdelay : std_logic_vector(3 downto 0); signal RXCHANBONDSEQ1_outdelay : std_logic; signal RXCHANREALIGN1_outdelay : std_logic; signal RXCHANISALIGNED1_outdelay : std_logic; signal RXBUFSTATUS1_outdelay : std_logic_vector(2 downto 0); signal PHYSTATUS0_outdelay : std_logic; signal PHYSTATUS1_outdelay : std_logic; signal RXELECIDLE0_outdelay : std_logic; signal RXSTATUS0_outdelay : std_logic_vector(2 downto 0); signal RXELECIDLE1_outdelay : std_logic; signal RXSTATUS1_outdelay : std_logic_vector(2 downto 0); signal PLLLKDET_outdelay : std_logic; signal RXPRBSERR0_outdelay : std_logic; signal RXPRBSERR1_outdelay : std_logic; signal DO_outdelay : std_logic_vector(15 downto 0); signal DRDY_outdelay : std_logic; signal RXOVERSAMPLEERR0_outdelay : std_logic; signal RXOVERSAMPLEERR1_outdelay : std_logic; signal TXGEARBOXREADY0_outdelay : std_logic; signal RXHEADER0_outdelay : std_logic_vector(2 downto 0); signal RXHEADERVALID0_outdelay : std_logic; signal RXDATAVALID0_outdelay : std_logic; signal RXSTARTOFSEQ0_outdelay : std_logic; signal TXGEARBOXREADY1_outdelay : std_logic; signal RXHEADER1_outdelay : std_logic_vector(2 downto 0); signal RXHEADERVALID1_outdelay : std_logic; signal RXDATAVALID1_outdelay : std_logic; signal RXSTARTOFSEQ1_outdelay : std_logic; signal DFEEYEDACMONITOR0_outdelay : std_logic_vector(4 downto 0); signal DFETAP1MONITOR0_outdelay : std_logic_vector(4 downto 0); signal DFETAP2MONITOR0_outdelay : std_logic_vector(4 downto 0); signal DFETAP3MONITOR0_outdelay : std_logic_vector(3 downto 0); signal DFETAP4MONITOR0_outdelay : std_logic_vector(3 downto 0); signal DFEEYEDACMONITOR1_outdelay : std_logic_vector(4 downto 0); signal DFETAP1MONITOR1_outdelay : std_logic_vector(4 downto 0); signal DFETAP2MONITOR1_outdelay : std_logic_vector(4 downto 0); signal DFETAP3MONITOR1_outdelay : std_logic_vector(3 downto 0); signal DFETAP4MONITOR1_outdelay : std_logic_vector(3 downto 0); signal DFESENSCAL0_outdelay : std_logic_vector(2 downto 0); signal DFESENSCAL1_outdelay : std_logic_vector(2 downto 0); signal CLKIN_ipd : std_ulogic; signal TXUSRCLK0_ipd : std_ulogic; signal TXUSRCLK20_ipd : std_ulogic; signal RXUSRCLK0_ipd : std_ulogic; signal RXUSRCLK20_ipd : std_ulogic; signal TXUSRCLK1_ipd : std_ulogic; signal TXUSRCLK21_ipd : std_ulogic; signal RXUSRCLK1_ipd : std_ulogic; signal RXUSRCLK21_ipd : std_ulogic; signal RXP0_ipd : std_ulogic; signal RXN0_ipd : std_ulogic; signal TXDATA0_ipd : std_logic_vector(31 downto 0); signal TXBYPASS8B10B0_ipd : std_logic_vector(3 downto 0); signal TXCHARISK0_ipd : std_logic_vector(3 downto 0); signal TXCHARDISPMODE0_ipd : std_logic_vector(3 downto 0); signal TXCHARDISPVAL0_ipd : std_logic_vector(3 downto 0); signal RXP1_ipd : std_ulogic; signal RXN1_ipd : std_ulogic; signal TXDATA1_ipd : std_logic_vector(31 downto 0); signal TXBYPASS8B10B1_ipd : std_logic_vector(3 downto 0); signal TXCHARISK1_ipd : std_logic_vector(3 downto 0); signal TXCHARDISPMODE1_ipd : std_logic_vector(3 downto 0); signal TXCHARDISPVAL1_ipd : std_logic_vector(3 downto 0); signal GTXRESET_ipd : std_ulogic; signal RXCDRRESET0_ipd : std_ulogic; signal TXRESET0_ipd : std_ulogic; signal RXRESET0_ipd : std_ulogic; signal RXBUFRESET0_ipd : std_ulogic; signal RXCDRRESET1_ipd : std_ulogic; signal TXRESET1_ipd : std_ulogic; signal RXRESET1_ipd : std_ulogic; signal RXBUFRESET1_ipd : std_ulogic; signal TXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); signal RXPOWERDOWN0_ipd : std_logic_vector(1 downto 0); signal TXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); signal RXPOWERDOWN1_ipd : std_logic_vector(1 downto 0); signal PLLPOWERDOWN_ipd : std_ulogic; signal REFCLKPWRDNB_ipd : std_ulogic; signal LOOPBACK0_ipd : std_logic_vector(2 downto 0); signal LOOPBACK1_ipd : std_logic_vector(2 downto 0); signal TXDIFFCTRL0_ipd : std_logic_vector(2 downto 0); signal TXBUFDIFFCTRL0_ipd : std_logic_vector(2 downto 0); signal TXPREEMPHASIS0_ipd : std_logic_vector(3 downto 0); signal TXDIFFCTRL1_ipd : std_logic_vector(2 downto 0); signal TXBUFDIFFCTRL1_ipd : std_logic_vector(2 downto 0); signal TXPREEMPHASIS1_ipd : std_logic_vector(3 downto 0); signal RXENEQB0_ipd : std_ulogic; signal RXEQMIX0_ipd : std_logic_vector(1 downto 0); signal RXEQPOLE0_ipd : std_logic_vector(3 downto 0); signal RXENEQB1_ipd : std_ulogic; signal RXEQMIX1_ipd : std_logic_vector(1 downto 0); signal RXEQPOLE1_ipd : std_logic_vector(3 downto 0); signal INTDATAWIDTH_ipd : std_ulogic; signal TXDATAWIDTH0_ipd : std_logic_vector(1 downto 0); signal TXDATAWIDTH1_ipd : std_logic_vector(1 downto 0); signal TXENPMAPHASEALIGN0_ipd : std_ulogic; signal TXPMASETPHASE0_ipd : std_ulogic; signal RXENPMAPHASEALIGN0_ipd : std_ulogic; signal RXPMASETPHASE0_ipd : std_ulogic; signal TXENPMAPHASEALIGN1_ipd : std_ulogic; signal TXPMASETPHASE1_ipd : std_ulogic; signal RXENPMAPHASEALIGN1_ipd : std_ulogic; signal RXPMASETPHASE1_ipd : std_ulogic; signal TXENC8B10BUSE0_ipd : std_ulogic; signal TXPOLARITY0_ipd : std_ulogic; signal TXINHIBIT0_ipd : std_ulogic; signal TXENC8B10BUSE1_ipd : std_ulogic; signal TXPOLARITY1_ipd : std_ulogic; signal TXINHIBIT1_ipd : std_ulogic; signal RXPOLARITY0_ipd : std_ulogic; signal RXENPCOMMAALIGN0_ipd : std_ulogic; signal RXENMCOMMAALIGN0_ipd : std_ulogic; signal RXSLIDE0_ipd : std_ulogic; signal RXCOMMADETUSE0_ipd : std_ulogic; signal RXDEC8B10BUSE0_ipd : std_ulogic; signal RXENCHANSYNC0_ipd : std_ulogic; signal RXCHBONDI0_ipd : std_logic_vector(3 downto 0); signal RXDATAWIDTH0_ipd : std_logic_vector(1 downto 0); signal RXPOLARITY1_ipd : std_ulogic; signal RXENPCOMMAALIGN1_ipd : std_ulogic; signal RXENMCOMMAALIGN1_ipd : std_ulogic; signal RXSLIDE1_ipd : std_ulogic; signal RXCOMMADETUSE1_ipd : std_ulogic; signal RXDEC8B10BUSE1_ipd : std_ulogic; signal RXENCHANSYNC1_ipd : std_ulogic; signal RXCHBONDI1_ipd : std_logic_vector(3 downto 0); signal RXDATAWIDTH1_ipd : std_logic_vector(1 downto 0); signal TXELECIDLE0_ipd : std_ulogic; signal TXDETECTRX0_ipd : std_ulogic; signal TXELECIDLE1_ipd : std_ulogic; signal TXDETECTRX1_ipd : std_ulogic; signal TXCOMSTART0_ipd : std_ulogic; signal TXCOMTYPE0_ipd : std_ulogic; signal TXCOMSTART1_ipd : std_ulogic; signal TXCOMTYPE1_ipd : std_ulogic; signal PLLLKDETEN_ipd : std_ulogic; signal TXENPRBSTST0_ipd : std_logic_vector(1 downto 0); signal RXENPRBSTST0_ipd : std_logic_vector(1 downto 0); signal PRBSCNTRESET0_ipd : std_ulogic; signal TXENPRBSTST1_ipd : std_logic_vector(1 downto 0); signal RXENPRBSTST1_ipd : std_logic_vector(1 downto 0); signal PRBSCNTRESET1_ipd : std_ulogic; signal DCLK_ipd : std_ulogic; signal DADDR_ipd : std_logic_vector(6 downto 0); signal DI_ipd : std_logic_vector(15 downto 0); signal DEN_ipd : std_ulogic; signal DWE_ipd : std_ulogic; signal RXENSAMPLEALIGN0_ipd : std_ulogic; signal RXENSAMPLEALIGN1_ipd : std_ulogic; signal GTXTEST_ipd : std_logic_vector(13 downto 0); signal TXHEADER0_ipd : std_logic_vector(2 downto 0); signal TXSEQUENCE0_ipd : std_logic_vector(6 downto 0); signal TXSTARTSEQ0_ipd : std_ulogic; signal RXGEARBOXSLIP0_ipd : std_ulogic; signal TXHEADER1_ipd : std_logic_vector(2 downto 0); signal TXSEQUENCE1_ipd : std_logic_vector(6 downto 0); signal TXSTARTSEQ1_ipd : std_ulogic; signal RXGEARBOXSLIP1_ipd : std_ulogic; signal DFECLKDLYADJ0_ipd : std_logic_vector(5 downto 0); signal DFETAP10_ipd : std_logic_vector(4 downto 0); signal DFETAP20_ipd : std_logic_vector(4 downto 0); signal DFETAP30_ipd : std_logic_vector(3 downto 0); signal DFETAP40_ipd : std_logic_vector(3 downto 0); signal DFECLKDLYADJ1_ipd : std_logic_vector(5 downto 0); signal DFETAP11_ipd : std_logic_vector(4 downto 0); signal DFETAP21_ipd : std_logic_vector(4 downto 0); signal DFETAP31_ipd : std_logic_vector(3 downto 0); signal DFETAP41_ipd : std_logic_vector(3 downto 0); signal CLKIN_indelay : std_ulogic; signal TXUSRCLK0_indelay : std_ulogic; signal TXUSRCLK20_indelay : std_ulogic; signal RXUSRCLK0_indelay : std_ulogic; signal RXUSRCLK20_indelay : std_ulogic; signal TXUSRCLK1_indelay : std_ulogic; signal TXUSRCLK21_indelay : std_ulogic; signal RXUSRCLK1_indelay : std_ulogic; signal RXUSRCLK21_indelay : std_ulogic; signal RXP0_indelay : std_ulogic; signal RXN0_indelay : std_ulogic; signal TXDATA0_indelay : std_logic_vector(31 downto 0); signal TXBYPASS8B10B0_indelay : std_logic_vector(3 downto 0); signal TXCHARISK0_indelay : std_logic_vector(3 downto 0); signal TXCHARDISPMODE0_indelay : std_logic_vector(3 downto 0); signal TXCHARDISPVAL0_indelay : std_logic_vector(3 downto 0); signal RXP1_indelay : std_ulogic; signal RXN1_indelay : std_ulogic; signal TXDATA1_indelay : std_logic_vector(31 downto 0); signal TXBYPASS8B10B1_indelay : std_logic_vector(3 downto 0); signal TXCHARISK1_indelay : std_logic_vector(3 downto 0); signal TXCHARDISPMODE1_indelay : std_logic_vector(3 downto 0); signal TXCHARDISPVAL1_indelay : std_logic_vector(3 downto 0); signal GTXRESET_indelay : std_ulogic; signal RXCDRRESET0_indelay : std_ulogic; signal TXRESET0_indelay : std_ulogic; signal RXRESET0_indelay : std_ulogic; signal RXBUFRESET0_indelay : std_ulogic; signal RXCDRRESET1_indelay : std_ulogic; signal TXRESET1_indelay : std_ulogic; signal RXRESET1_indelay : std_ulogic; signal RXBUFRESET1_indelay : std_ulogic; signal TXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); signal RXPOWERDOWN0_indelay : std_logic_vector(1 downto 0); signal TXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); signal RXPOWERDOWN1_indelay : std_logic_vector(1 downto 0); signal PLLPOWERDOWN_indelay : std_ulogic; signal REFCLKPWRDNB_indelay : std_ulogic; signal LOOPBACK0_indelay : std_logic_vector(2 downto 0); signal LOOPBACK1_indelay : std_logic_vector(2 downto 0); signal TXDIFFCTRL0_indelay : std_logic_vector(2 downto 0); signal TXBUFDIFFCTRL0_indelay : std_logic_vector(2 downto 0); signal TXPREEMPHASIS0_indelay : std_logic_vector(3 downto 0); signal TXDIFFCTRL1_indelay : std_logic_vector(2 downto 0); signal TXBUFDIFFCTRL1_indelay : std_logic_vector(2 downto 0); signal TXPREEMPHASIS1_indelay : std_logic_vector(3 downto 0); signal RXENEQB0_indelay : std_ulogic; signal RXEQMIX0_indelay : std_logic_vector(1 downto 0); signal RXEQPOLE0_indelay : std_logic_vector(3 downto 0); signal RXENEQB1_indelay : std_ulogic; signal RXEQMIX1_indelay : std_logic_vector(1 downto 0); signal RXEQPOLE1_indelay : std_logic_vector(3 downto 0); signal INTDATAWIDTH_indelay : std_ulogic; signal TXDATAWIDTH0_indelay : std_logic_vector(1 downto 0); signal TXDATAWIDTH1_indelay : std_logic_vector(1 downto 0); signal TXENPMAPHASEALIGN0_indelay : std_ulogic; signal TXPMASETPHASE0_indelay : std_ulogic; signal RXENPMAPHASEALIGN0_indelay : std_ulogic; signal RXPMASETPHASE0_indelay : std_ulogic; signal TXENPMAPHASEALIGN1_indelay : std_ulogic; signal TXPMASETPHASE1_indelay : std_ulogic; signal RXENPMAPHASEALIGN1_indelay : std_ulogic; signal RXPMASETPHASE1_indelay : std_ulogic; signal TXENC8B10BUSE0_indelay : std_ulogic; signal TXPOLARITY0_indelay : std_ulogic; signal TXINHIBIT0_indelay : std_ulogic; signal TXENC8B10BUSE1_indelay : std_ulogic; signal TXPOLARITY1_indelay : std_ulogic; signal TXINHIBIT1_indelay : std_ulogic; signal RXPOLARITY0_indelay : std_ulogic; signal RXENPCOMMAALIGN0_indelay : std_ulogic; signal RXENMCOMMAALIGN0_indelay : std_ulogic; signal RXSLIDE0_indelay : std_ulogic; signal RXCOMMADETUSE0_indelay : std_ulogic; signal RXDEC8B10BUSE0_indelay : std_ulogic; signal RXENCHANSYNC0_indelay : std_ulogic; signal RXCHBONDI0_indelay : std_logic_vector(3 downto 0); signal RXDATAWIDTH0_indelay : std_logic_vector(1 downto 0); signal RXPOLARITY1_indelay : std_ulogic; signal RXENPCOMMAALIGN1_indelay : std_ulogic; signal RXENMCOMMAALIGN1_indelay : std_ulogic; signal RXSLIDE1_indelay : std_ulogic; signal RXCOMMADETUSE1_indelay : std_ulogic; signal RXDEC8B10BUSE1_indelay : std_ulogic; signal RXENCHANSYNC1_indelay : std_ulogic; signal RXCHBONDI1_indelay : std_logic_vector(3 downto 0); signal RXDATAWIDTH1_indelay : std_logic_vector(1 downto 0); signal TXELECIDLE0_indelay : std_ulogic; signal TXDETECTRX0_indelay : std_ulogic; signal TXELECIDLE1_indelay : std_ulogic; signal TXDETECTRX1_indelay : std_ulogic; signal TXCOMSTART0_indelay : std_ulogic; signal TXCOMTYPE0_indelay : std_ulogic; signal TXCOMSTART1_indelay : std_ulogic; signal TXCOMTYPE1_indelay : std_ulogic; signal PLLLKDETEN_indelay : std_ulogic; signal TXENPRBSTST0_indelay : std_logic_vector(1 downto 0); signal RXENPRBSTST0_indelay : std_logic_vector(1 downto 0); signal PRBSCNTRESET0_indelay : std_ulogic; signal TXENPRBSTST1_indelay : std_logic_vector(1 downto 0); signal RXENPRBSTST1_indelay : std_logic_vector(1 downto 0); signal PRBSCNTRESET1_indelay : std_ulogic; signal DCLK_indelay : std_ulogic; signal DADDR_indelay : std_logic_vector(6 downto 0); signal DI_indelay : std_logic_vector(15 downto 0); signal DEN_indelay : std_ulogic; signal DWE_indelay : std_ulogic; signal RXENSAMPLEALIGN0_indelay : std_ulogic; signal RXENSAMPLEALIGN1_indelay : std_ulogic; signal GTXTEST_indelay : std_logic_vector(13 downto 0); signal TXHEADER0_indelay : std_logic_vector(2 downto 0); signal TXSEQUENCE0_indelay : std_logic_vector(6 downto 0); signal TXSTARTSEQ0_indelay : std_ulogic; signal RXGEARBOXSLIP0_indelay : std_ulogic; signal TXHEADER1_indelay : std_logic_vector(2 downto 0); signal TXSEQUENCE1_indelay : std_logic_vector(6 downto 0); signal TXSTARTSEQ1_indelay : std_ulogic; signal RXGEARBOXSLIP1_indelay : std_ulogic; signal DFECLKDLYADJ0_indelay : std_logic_vector(5 downto 0); signal DFETAP10_indelay : std_logic_vector(4 downto 0); signal DFETAP20_indelay : std_logic_vector(4 downto 0); signal DFETAP30_indelay : std_logic_vector(3 downto 0); signal DFETAP40_indelay : std_logic_vector(3 downto 0); signal DFECLKDLYADJ1_indelay : std_logic_vector(5 downto 0); signal DFETAP11_indelay : std_logic_vector(4 downto 0); signal DFETAP21_indelay : std_logic_vector(4 downto 0); signal DFETAP31_indelay : std_logic_vector(3 downto 0); signal DFETAP41_indelay : std_logic_vector(3 downto 0); begin DFECLKDLYADJMONITOR0_out <= DFECLKDLYADJMONITOR0_outdelay after CLK_DELAY; DFECLKDLYADJMONITOR1_out <= DFECLKDLYADJMONITOR1_outdelay after CLK_DELAY; REFCLKOUT_out <= REFCLKOUT_outdelay after CLK_DELAY; RXCLKCORCNT0_out <= RXCLKCORCNT0_outdelay after CLK_DELAY; RXCLKCORCNT1_out <= RXCLKCORCNT1_outdelay after CLK_DELAY; RXRECCLK0_out <= RXRECCLK0_outdelay after CLK_DELAY; RXRECCLK1_out <= RXRECCLK1_outdelay after CLK_DELAY; TXOUTCLK0_out <= TXOUTCLK0_outdelay after CLK_DELAY; TXOUTCLK1_out <= TXOUTCLK1_outdelay after CLK_DELAY; DFEEYEDACMONITOR0_out <= DFEEYEDACMONITOR0_outdelay after OUT_DELAY; DFEEYEDACMONITOR1_out <= DFEEYEDACMONITOR1_outdelay after OUT_DELAY; DFESENSCAL0_out <= DFESENSCAL0_outdelay after OUT_DELAY; DFESENSCAL1_out <= DFESENSCAL1_outdelay after OUT_DELAY; DFETAP1MONITOR0_out <= DFETAP1MONITOR0_outdelay after OUT_DELAY; DFETAP1MONITOR1_out <= DFETAP1MONITOR1_outdelay after OUT_DELAY; DFETAP2MONITOR0_out <= DFETAP2MONITOR0_outdelay after OUT_DELAY; DFETAP2MONITOR1_out <= DFETAP2MONITOR1_outdelay after OUT_DELAY; DFETAP3MONITOR0_out <= DFETAP3MONITOR0_outdelay after OUT_DELAY; DFETAP3MONITOR1_out <= DFETAP3MONITOR1_outdelay after OUT_DELAY; DFETAP4MONITOR0_out <= DFETAP4MONITOR0_outdelay after OUT_DELAY; DFETAP4MONITOR1_out <= DFETAP4MONITOR1_outdelay after OUT_DELAY; DO_out <= DO_outdelay after OUT_DELAY; DRDY_out <= DRDY_outdelay after OUT_DELAY; PHYSTATUS0_out <= PHYSTATUS0_outdelay after OUT_DELAY; PHYSTATUS1_out <= PHYSTATUS1_outdelay after OUT_DELAY; PLLLKDET_out <= PLLLKDET_outdelay after OUT_DELAY; RESETDONE0_out <= RESETDONE0_outdelay after OUT_DELAY; RESETDONE1_out <= RESETDONE1_outdelay after OUT_DELAY; RXBUFSTATUS0_out <= RXBUFSTATUS0_outdelay after OUT_DELAY; RXBUFSTATUS1_out <= RXBUFSTATUS1_outdelay after OUT_DELAY; RXBYTEISALIGNED0_out <= RXBYTEISALIGNED0_outdelay after OUT_DELAY; RXBYTEISALIGNED1_out <= RXBYTEISALIGNED1_outdelay after OUT_DELAY; RXBYTEREALIGN0_out <= RXBYTEREALIGN0_outdelay after OUT_DELAY; RXBYTEREALIGN1_out <= RXBYTEREALIGN1_outdelay after OUT_DELAY; RXCHANBONDSEQ0_out <= RXCHANBONDSEQ0_outdelay after OUT_DELAY; RXCHANBONDSEQ1_out <= RXCHANBONDSEQ1_outdelay after OUT_DELAY; RXCHANISALIGNED0_out <= RXCHANISALIGNED0_outdelay after OUT_DELAY; RXCHANISALIGNED1_out <= RXCHANISALIGNED1_outdelay after OUT_DELAY; RXCHANREALIGN0_out <= RXCHANREALIGN0_outdelay after OUT_DELAY; RXCHANREALIGN1_out <= RXCHANREALIGN1_outdelay after OUT_DELAY; RXCHARISCOMMA0_out <= RXCHARISCOMMA0_outdelay after OUT_DELAY; RXCHARISCOMMA1_out <= RXCHARISCOMMA1_outdelay after OUT_DELAY; RXCHARISK0_out <= RXCHARISK0_outdelay after OUT_DELAY; RXCHARISK1_out <= RXCHARISK1_outdelay after OUT_DELAY; RXCHBONDO0_out <= RXCHBONDO0_outdelay after OUT_DELAY; RXCHBONDO1_out <= RXCHBONDO1_outdelay after OUT_DELAY; RXCOMMADET0_out <= RXCOMMADET0_outdelay after OUT_DELAY; RXCOMMADET1_out <= RXCOMMADET1_outdelay after OUT_DELAY; RXDATA0_out <= RXDATA0_outdelay after OUT_DELAY; RXDATA1_out <= RXDATA1_outdelay after OUT_DELAY; RXDATAVALID0_out <= RXDATAVALID0_outdelay after OUT_DELAY; RXDATAVALID1_out <= RXDATAVALID1_outdelay after OUT_DELAY; RXDISPERR0_out <= RXDISPERR0_outdelay after OUT_DELAY; RXDISPERR1_out <= RXDISPERR1_outdelay after OUT_DELAY; RXELECIDLE0_out <= RXELECIDLE0_outdelay after OUT_DELAY; RXELECIDLE1_out <= RXELECIDLE1_outdelay after OUT_DELAY; RXHEADER0_out <= RXHEADER0_outdelay after OUT_DELAY; RXHEADER1_out <= RXHEADER1_outdelay after OUT_DELAY; RXHEADERVALID0_out <= RXHEADERVALID0_outdelay after OUT_DELAY; RXHEADERVALID1_out <= RXHEADERVALID1_outdelay after OUT_DELAY; RXLOSSOFSYNC0_out <= RXLOSSOFSYNC0_outdelay after OUT_DELAY; RXLOSSOFSYNC1_out <= RXLOSSOFSYNC1_outdelay after OUT_DELAY; RXNOTINTABLE0_out <= RXNOTINTABLE0_outdelay after OUT_DELAY; RXNOTINTABLE1_out <= RXNOTINTABLE1_outdelay after OUT_DELAY; RXOVERSAMPLEERR0_out <= RXOVERSAMPLEERR0_outdelay after OUT_DELAY; RXOVERSAMPLEERR1_out <= RXOVERSAMPLEERR1_outdelay after OUT_DELAY; RXPRBSERR0_out <= RXPRBSERR0_outdelay after OUT_DELAY; RXPRBSERR1_out <= RXPRBSERR1_outdelay after OUT_DELAY; RXRUNDISP0_out <= RXRUNDISP0_outdelay after OUT_DELAY; RXRUNDISP1_out <= RXRUNDISP1_outdelay after OUT_DELAY; RXSTARTOFSEQ0_out <= RXSTARTOFSEQ0_outdelay after OUT_DELAY; RXSTARTOFSEQ1_out <= RXSTARTOFSEQ1_outdelay after OUT_DELAY; RXSTATUS0_out <= RXSTATUS0_outdelay after OUT_DELAY; RXSTATUS1_out <= RXSTATUS1_outdelay after OUT_DELAY; RXVALID0_out <= RXVALID0_outdelay after OUT_DELAY; RXVALID1_out <= RXVALID1_outdelay after OUT_DELAY; TXBUFSTATUS0_out <= TXBUFSTATUS0_outdelay after OUT_DELAY; TXBUFSTATUS1_out <= TXBUFSTATUS1_outdelay after OUT_DELAY; TXGEARBOXREADY0_out <= TXGEARBOXREADY0_outdelay after OUT_DELAY; TXGEARBOXREADY1_out <= TXGEARBOXREADY1_outdelay after OUT_DELAY; TXKERR0_out <= TXKERR0_outdelay after OUT_DELAY; TXKERR1_out <= TXKERR1_outdelay after OUT_DELAY; TXN0_out <= TXN0_outdelay after OUT_DELAY; TXN1_out <= TXN1_outdelay after OUT_DELAY; TXP0_out <= TXP0_outdelay after OUT_DELAY; TXP1_out <= TXP1_outdelay after OUT_DELAY; TXRUNDISP0_out <= TXRUNDISP0_outdelay after OUT_DELAY; TXRUNDISP1_out <= TXRUNDISP1_outdelay after OUT_DELAY; DCLK_ipd <= DCLK after CLK_DELAY; RXUSRCLK0_ipd <= RXUSRCLK0 after CLK_DELAY; RXUSRCLK1_ipd <= RXUSRCLK1 after CLK_DELAY; RXUSRCLK20_ipd <= RXUSRCLK20 after CLK_DELAY; RXUSRCLK21_ipd <= RXUSRCLK21 after CLK_DELAY; TXUSRCLK0_ipd <= TXUSRCLK0 after CLK_DELAY; TXUSRCLK1_ipd <= TXUSRCLK1 after CLK_DELAY; TXUSRCLK20_ipd <= TXUSRCLK20 after CLK_DELAY; TXUSRCLK21_ipd <= TXUSRCLK21 after CLK_DELAY; CLKIN_ipd <= CLKIN after CLK_DELAY; DADDR_ipd <= DADDR after CLK_DELAY; DEN_ipd <= DEN after CLK_DELAY; DFECLKDLYADJ0_ipd <= DFECLKDLYADJ0 after CLK_DELAY; DFECLKDLYADJ1_ipd <= DFECLKDLYADJ1 after CLK_DELAY; DFETAP10_ipd <= DFETAP10 after CLK_DELAY; DFETAP11_ipd <= DFETAP11 after CLK_DELAY; DFETAP20_ipd <= DFETAP20 after CLK_DELAY; DFETAP21_ipd <= DFETAP21 after CLK_DELAY; DFETAP30_ipd <= DFETAP30 after CLK_DELAY; DFETAP31_ipd <= DFETAP31 after CLK_DELAY; DFETAP40_ipd <= DFETAP40 after CLK_DELAY; DFETAP41_ipd <= DFETAP41 after CLK_DELAY; DI_ipd <= DI after CLK_DELAY; DWE_ipd <= DWE after CLK_DELAY; GTXRESET_ipd <= GTXRESET after CLK_DELAY; GTXTEST_ipd <= GTXTEST after CLK_DELAY; INTDATAWIDTH_ipd <= INTDATAWIDTH after CLK_DELAY; LOOPBACK0_ipd <= LOOPBACK0 after CLK_DELAY; LOOPBACK1_ipd <= LOOPBACK1 after CLK_DELAY; PLLLKDETEN_ipd <= PLLLKDETEN after CLK_DELAY; PLLPOWERDOWN_ipd <= PLLPOWERDOWN after CLK_DELAY; PRBSCNTRESET0_ipd <= PRBSCNTRESET0 after CLK_DELAY; PRBSCNTRESET1_ipd <= PRBSCNTRESET1 after CLK_DELAY; REFCLKPWRDNB_ipd <= REFCLKPWRDNB after CLK_DELAY; RXBUFRESET0_ipd <= RXBUFRESET0 after CLK_DELAY; RXBUFRESET1_ipd <= RXBUFRESET1 after CLK_DELAY; RXCDRRESET0_ipd <= RXCDRRESET0 after CLK_DELAY; RXCDRRESET1_ipd <= RXCDRRESET1 after CLK_DELAY; RXCHBONDI0_ipd <= RXCHBONDI0 after CLK_DELAY; RXCHBONDI1_ipd <= RXCHBONDI1 after CLK_DELAY; RXCOMMADETUSE0_ipd <= RXCOMMADETUSE0 after CLK_DELAY; RXCOMMADETUSE1_ipd <= RXCOMMADETUSE1 after CLK_DELAY; RXDATAWIDTH0_ipd <= RXDATAWIDTH0 after CLK_DELAY; RXDATAWIDTH1_ipd <= RXDATAWIDTH1 after CLK_DELAY; RXDEC8B10BUSE0_ipd <= RXDEC8B10BUSE0 after CLK_DELAY; RXDEC8B10BUSE1_ipd <= RXDEC8B10BUSE1 after CLK_DELAY; RXENCHANSYNC0_ipd <= RXENCHANSYNC0 after CLK_DELAY; RXENCHANSYNC1_ipd <= RXENCHANSYNC1 after CLK_DELAY; RXENEQB0_ipd <= RXENEQB0 after CLK_DELAY; RXENEQB1_ipd <= RXENEQB1 after CLK_DELAY; RXENMCOMMAALIGN0_ipd <= RXENMCOMMAALIGN0 after CLK_DELAY; RXENMCOMMAALIGN1_ipd <= RXENMCOMMAALIGN1 after CLK_DELAY; RXENPCOMMAALIGN0_ipd <= RXENPCOMMAALIGN0 after CLK_DELAY; RXENPCOMMAALIGN1_ipd <= RXENPCOMMAALIGN1 after CLK_DELAY; RXENPMAPHASEALIGN0_ipd <= RXENPMAPHASEALIGN0 after CLK_DELAY; RXENPMAPHASEALIGN1_ipd <= RXENPMAPHASEALIGN1 after CLK_DELAY; RXENPRBSTST0_ipd <= RXENPRBSTST0 after CLK_DELAY; RXENPRBSTST1_ipd <= RXENPRBSTST1 after CLK_DELAY; RXENSAMPLEALIGN0_ipd <= RXENSAMPLEALIGN0 after CLK_DELAY; RXENSAMPLEALIGN1_ipd <= RXENSAMPLEALIGN1 after CLK_DELAY; RXEQMIX0_ipd <= RXEQMIX0 after CLK_DELAY; RXEQMIX1_ipd <= RXEQMIX1 after CLK_DELAY; RXEQPOLE0_ipd <= RXEQPOLE0 after CLK_DELAY; RXEQPOLE1_ipd <= RXEQPOLE1 after CLK_DELAY; RXGEARBOXSLIP0_ipd <= RXGEARBOXSLIP0 after CLK_DELAY; RXGEARBOXSLIP1_ipd <= RXGEARBOXSLIP1 after CLK_DELAY; RXN0_ipd <= RXN0 after CLK_DELAY; RXN1_ipd <= RXN1 after CLK_DELAY; RXP0_ipd <= RXP0 after CLK_DELAY; RXP1_ipd <= RXP1 after CLK_DELAY; RXPMASETPHASE0_ipd <= RXPMASETPHASE0 after CLK_DELAY; RXPMASETPHASE1_ipd <= RXPMASETPHASE1 after CLK_DELAY; RXPOLARITY0_ipd <= RXPOLARITY0 after CLK_DELAY; RXPOLARITY1_ipd <= RXPOLARITY1 after CLK_DELAY; RXPOWERDOWN0_ipd <= RXPOWERDOWN0 after CLK_DELAY; RXPOWERDOWN1_ipd <= RXPOWERDOWN1 after CLK_DELAY; RXRESET0_ipd <= RXRESET0 after CLK_DELAY; RXRESET1_ipd <= RXRESET1 after CLK_DELAY; RXSLIDE0_ipd <= RXSLIDE0 after CLK_DELAY; RXSLIDE1_ipd <= RXSLIDE1 after CLK_DELAY; TXBUFDIFFCTRL0_ipd <= TXBUFDIFFCTRL0 after CLK_DELAY; TXBUFDIFFCTRL1_ipd <= TXBUFDIFFCTRL1 after CLK_DELAY; TXBYPASS8B10B0_ipd <= TXBYPASS8B10B0 after CLK_DELAY; TXBYPASS8B10B1_ipd <= TXBYPASS8B10B1 after CLK_DELAY; TXCHARDISPMODE0_ipd <= TXCHARDISPMODE0 after CLK_DELAY; TXCHARDISPMODE1_ipd <= TXCHARDISPMODE1 after CLK_DELAY; TXCHARDISPVAL0_ipd <= TXCHARDISPVAL0 after CLK_DELAY; TXCHARDISPVAL1_ipd <= TXCHARDISPVAL1 after CLK_DELAY; TXCHARISK0_ipd <= TXCHARISK0 after CLK_DELAY; TXCHARISK1_ipd <= TXCHARISK1 after CLK_DELAY; TXCOMSTART0_ipd <= TXCOMSTART0 after CLK_DELAY; TXCOMSTART1_ipd <= TXCOMSTART1 after CLK_DELAY; TXCOMTYPE0_ipd <= TXCOMTYPE0 after CLK_DELAY; TXCOMTYPE1_ipd <= TXCOMTYPE1 after CLK_DELAY; TXDATA0_ipd <= TXDATA0 after CLK_DELAY; TXDATA1_ipd <= TXDATA1 after CLK_DELAY; TXDATAWIDTH0_ipd <= TXDATAWIDTH0 after CLK_DELAY; TXDATAWIDTH1_ipd <= TXDATAWIDTH1 after CLK_DELAY; TXDETECTRX0_ipd <= TXDETECTRX0 after CLK_DELAY; TXDETECTRX1_ipd <= TXDETECTRX1 after CLK_DELAY; TXDIFFCTRL0_ipd <= TXDIFFCTRL0 after CLK_DELAY; TXDIFFCTRL1_ipd <= TXDIFFCTRL1 after CLK_DELAY; TXELECIDLE0_ipd <= TXELECIDLE0 after CLK_DELAY; TXELECIDLE1_ipd <= TXELECIDLE1 after CLK_DELAY; TXENC8B10BUSE0_ipd <= TXENC8B10BUSE0 after CLK_DELAY; TXENC8B10BUSE1_ipd <= TXENC8B10BUSE1 after CLK_DELAY; TXENPMAPHASEALIGN0_ipd <= TXENPMAPHASEALIGN0 after CLK_DELAY; TXENPMAPHASEALIGN1_ipd <= TXENPMAPHASEALIGN1 after CLK_DELAY; TXENPRBSTST0_ipd <= TXENPRBSTST0 after CLK_DELAY; TXENPRBSTST1_ipd <= TXENPRBSTST1 after CLK_DELAY; TXHEADER0_ipd <= TXHEADER0 after CLK_DELAY; TXHEADER1_ipd <= TXHEADER1 after CLK_DELAY; TXINHIBIT0_ipd <= TXINHIBIT0 after CLK_DELAY; TXINHIBIT1_ipd <= TXINHIBIT1 after CLK_DELAY; TXPMASETPHASE0_ipd <= TXPMASETPHASE0 after CLK_DELAY; TXPMASETPHASE1_ipd <= TXPMASETPHASE1 after CLK_DELAY; TXPOLARITY0_ipd <= TXPOLARITY0 after CLK_DELAY; TXPOLARITY1_ipd <= TXPOLARITY1 after CLK_DELAY; TXPOWERDOWN0_ipd <= TXPOWERDOWN0 after CLK_DELAY; TXPOWERDOWN1_ipd <= TXPOWERDOWN1 after CLK_DELAY; TXPREEMPHASIS0_ipd <= TXPREEMPHASIS0 after CLK_DELAY; TXPREEMPHASIS1_ipd <= TXPREEMPHASIS1 after CLK_DELAY; TXRESET0_ipd <= TXRESET0 after CLK_DELAY; TXRESET1_ipd <= TXRESET1 after CLK_DELAY; TXSEQUENCE0_ipd <= TXSEQUENCE0 after CLK_DELAY; TXSEQUENCE1_ipd <= TXSEQUENCE1 after CLK_DELAY; TXSTARTSEQ0_ipd <= TXSTARTSEQ0 after CLK_DELAY; TXSTARTSEQ1_ipd <= TXSTARTSEQ1 after CLK_DELAY; DCLK_indelay <= DCLK_ipd after CLK_DELAY; RXUSRCLK0_indelay <= RXUSRCLK0_ipd after CLK_DELAY; RXUSRCLK1_indelay <= RXUSRCLK1_ipd after CLK_DELAY; RXUSRCLK20_indelay <= RXUSRCLK20_ipd after CLK_DELAY; RXUSRCLK21_indelay <= RXUSRCLK21_ipd after CLK_DELAY; TXUSRCLK0_indelay <= TXUSRCLK0_ipd after CLK_DELAY; TXUSRCLK1_indelay <= TXUSRCLK1_ipd after CLK_DELAY; TXUSRCLK20_indelay <= TXUSRCLK20_ipd after CLK_DELAY; TXUSRCLK21_indelay <= TXUSRCLK21_ipd after CLK_DELAY; CLKIN_indelay <= CLKIN_ipd after IN_DELAY; DADDR_indelay <= DADDR_ipd after IN_DELAY; DEN_indelay <= DEN_ipd after IN_DELAY; DFECLKDLYADJ0_indelay <= DFECLKDLYADJ0_ipd after IN_DELAY; DFECLKDLYADJ1_indelay <= DFECLKDLYADJ1_ipd after IN_DELAY; DFETAP10_indelay <= DFETAP10_ipd after IN_DELAY; DFETAP11_indelay <= DFETAP11_ipd after IN_DELAY; DFETAP20_indelay <= DFETAP20_ipd after IN_DELAY; DFETAP21_indelay <= DFETAP21_ipd after IN_DELAY; DFETAP30_indelay <= DFETAP30_ipd after IN_DELAY; DFETAP31_indelay <= DFETAP31_ipd after IN_DELAY; DFETAP40_indelay <= DFETAP40_ipd after IN_DELAY; DFETAP41_indelay <= DFETAP41_ipd after IN_DELAY; DI_indelay <= DI_ipd after IN_DELAY; DWE_indelay <= DWE_ipd after IN_DELAY; GTXRESET_indelay <= GTXRESET_ipd after IN_DELAY; GTXTEST_indelay <= GTXTEST_ipd after IN_DELAY; INTDATAWIDTH_indelay <= INTDATAWIDTH_ipd after IN_DELAY; LOOPBACK0_indelay <= LOOPBACK0_ipd after IN_DELAY; LOOPBACK1_indelay <= LOOPBACK1_ipd after IN_DELAY; PLLLKDETEN_indelay <= PLLLKDETEN_ipd after IN_DELAY; PLLPOWERDOWN_indelay <= PLLPOWERDOWN_ipd after IN_DELAY; PRBSCNTRESET0_indelay <= PRBSCNTRESET0_ipd after IN_DELAY; PRBSCNTRESET1_indelay <= PRBSCNTRESET1_ipd after IN_DELAY; REFCLKPWRDNB_indelay <= REFCLKPWRDNB_ipd after IN_DELAY; RXBUFRESET0_indelay <= RXBUFRESET0_ipd after IN_DELAY; RXBUFRESET1_indelay <= RXBUFRESET1_ipd after IN_DELAY; RXCDRRESET0_indelay <= RXCDRRESET0_ipd after IN_DELAY; RXCDRRESET1_indelay <= RXCDRRESET1_ipd after IN_DELAY; RXCHBONDI0_indelay <= RXCHBONDI0_ipd after IN_DELAY; RXCHBONDI1_indelay <= RXCHBONDI1_ipd after IN_DELAY; RXCOMMADETUSE0_indelay <= RXCOMMADETUSE0_ipd after IN_DELAY; RXCOMMADETUSE1_indelay <= RXCOMMADETUSE1_ipd after IN_DELAY; RXDATAWIDTH0_indelay <= RXDATAWIDTH0_ipd after IN_DELAY; RXDATAWIDTH1_indelay <= RXDATAWIDTH1_ipd after IN_DELAY; RXDEC8B10BUSE0_indelay <= RXDEC8B10BUSE0_ipd after IN_DELAY; RXDEC8B10BUSE1_indelay <= RXDEC8B10BUSE1_ipd after IN_DELAY; RXENCHANSYNC0_indelay <= RXENCHANSYNC0_ipd after IN_DELAY; RXENCHANSYNC1_indelay <= RXENCHANSYNC1_ipd after IN_DELAY; RXENEQB0_indelay <= RXENEQB0_ipd after IN_DELAY; RXENEQB1_indelay <= RXENEQB1_ipd after IN_DELAY; RXENMCOMMAALIGN0_indelay <= RXENMCOMMAALIGN0_ipd after IN_DELAY; RXENMCOMMAALIGN1_indelay <= RXENMCOMMAALIGN1_ipd after IN_DELAY; RXENPCOMMAALIGN0_indelay <= RXENPCOMMAALIGN0_ipd after IN_DELAY; RXENPCOMMAALIGN1_indelay <= RXENPCOMMAALIGN1_ipd after IN_DELAY; RXENPMAPHASEALIGN0_indelay <= RXENPMAPHASEALIGN0_ipd after IN_DELAY; RXENPMAPHASEALIGN1_indelay <= RXENPMAPHASEALIGN1_ipd after IN_DELAY; RXENPRBSTST0_indelay <= RXENPRBSTST0_ipd after IN_DELAY; RXENPRBSTST1_indelay <= RXENPRBSTST1_ipd after IN_DELAY; RXENSAMPLEALIGN0_indelay <= RXENSAMPLEALIGN0_ipd after IN_DELAY; RXENSAMPLEALIGN1_indelay <= RXENSAMPLEALIGN1_ipd after IN_DELAY; RXEQMIX0_indelay <= RXEQMIX0_ipd after IN_DELAY; RXEQMIX1_indelay <= RXEQMIX1_ipd after IN_DELAY; RXEQPOLE0_indelay <= RXEQPOLE0_ipd after IN_DELAY; RXEQPOLE1_indelay <= RXEQPOLE1_ipd after IN_DELAY; RXGEARBOXSLIP0_indelay <= RXGEARBOXSLIP0_ipd after IN_DELAY; RXGEARBOXSLIP1_indelay <= RXGEARBOXSLIP1_ipd after IN_DELAY; RXN0_indelay <= RXN0_ipd after IN_DELAY; RXN1_indelay <= RXN1_ipd after IN_DELAY; RXP0_indelay <= RXP0_ipd after IN_DELAY; RXP1_indelay <= RXP1_ipd after IN_DELAY; RXPMASETPHASE0_indelay <= RXPMASETPHASE0_ipd after IN_DELAY; RXPMASETPHASE1_indelay <= RXPMASETPHASE1_ipd after IN_DELAY; RXPOLARITY0_indelay <= RXPOLARITY0_ipd after IN_DELAY; RXPOLARITY1_indelay <= RXPOLARITY1_ipd after IN_DELAY; RXPOWERDOWN0_indelay <= RXPOWERDOWN0_ipd after IN_DELAY; RXPOWERDOWN1_indelay <= RXPOWERDOWN1_ipd after IN_DELAY; RXRESET0_indelay <= RXRESET0_ipd after IN_DELAY; RXRESET1_indelay <= RXRESET1_ipd after IN_DELAY; RXSLIDE0_indelay <= RXSLIDE0_ipd after IN_DELAY; RXSLIDE1_indelay <= RXSLIDE1_ipd after IN_DELAY; TXBUFDIFFCTRL0_indelay <= TXBUFDIFFCTRL0_ipd after IN_DELAY; TXBUFDIFFCTRL1_indelay <= TXBUFDIFFCTRL1_ipd after IN_DELAY; TXBYPASS8B10B0_indelay <= TXBYPASS8B10B0_ipd after IN_DELAY; TXBYPASS8B10B1_indelay <= TXBYPASS8B10B1_ipd after IN_DELAY; TXCHARDISPMODE0_indelay <= TXCHARDISPMODE0_ipd after IN_DELAY; TXCHARDISPMODE1_indelay <= TXCHARDISPMODE1_ipd after IN_DELAY; TXCHARDISPVAL0_indelay <= TXCHARDISPVAL0_ipd after IN_DELAY; TXCHARDISPVAL1_indelay <= TXCHARDISPVAL1_ipd after IN_DELAY; TXCHARISK0_indelay <= TXCHARISK0_ipd after IN_DELAY; TXCHARISK1_indelay <= TXCHARISK1_ipd after IN_DELAY; TXCOMSTART0_indelay <= TXCOMSTART0_ipd after IN_DELAY; TXCOMSTART1_indelay <= TXCOMSTART1_ipd after IN_DELAY; TXCOMTYPE0_indelay <= TXCOMTYPE0_ipd after IN_DELAY; TXCOMTYPE1_indelay <= TXCOMTYPE1_ipd after IN_DELAY; TXDATA0_indelay <= TXDATA0_ipd after IN_DELAY; TXDATA1_indelay <= TXDATA1_ipd after IN_DELAY; TXDATAWIDTH0_indelay <= TXDATAWIDTH0_ipd after IN_DELAY; TXDATAWIDTH1_indelay <= TXDATAWIDTH1_ipd after IN_DELAY; TXDETECTRX0_indelay <= TXDETECTRX0_ipd after IN_DELAY; TXDETECTRX1_indelay <= TXDETECTRX1_ipd after IN_DELAY; TXDIFFCTRL0_indelay <= TXDIFFCTRL0_ipd after IN_DELAY; TXDIFFCTRL1_indelay <= TXDIFFCTRL1_ipd after IN_DELAY; TXELECIDLE0_indelay <= TXELECIDLE0_ipd after IN_DELAY; TXELECIDLE1_indelay <= TXELECIDLE1_ipd after IN_DELAY; TXENC8B10BUSE0_indelay <= TXENC8B10BUSE0_ipd after IN_DELAY; TXENC8B10BUSE1_indelay <= TXENC8B10BUSE1_ipd after IN_DELAY; TXENPMAPHASEALIGN0_indelay <= TXENPMAPHASEALIGN0_ipd after IN_DELAY; TXENPMAPHASEALIGN1_indelay <= TXENPMAPHASEALIGN1_ipd after IN_DELAY; TXENPRBSTST0_indelay <= TXENPRBSTST0_ipd after IN_DELAY; TXENPRBSTST1_indelay <= TXENPRBSTST1_ipd after IN_DELAY; TXHEADER0_indelay <= TXHEADER0_ipd after IN_DELAY; TXHEADER1_indelay <= TXHEADER1_ipd after IN_DELAY; TXINHIBIT0_indelay <= TXINHIBIT0_ipd after IN_DELAY; TXINHIBIT1_indelay <= TXINHIBIT1_ipd after IN_DELAY; TXPMASETPHASE0_indelay <= TXPMASETPHASE0_ipd after IN_DELAY; TXPMASETPHASE1_indelay <= TXPMASETPHASE1_ipd after IN_DELAY; TXPOLARITY0_indelay <= TXPOLARITY0_ipd after IN_DELAY; TXPOLARITY1_indelay <= TXPOLARITY1_ipd after IN_DELAY; TXPOWERDOWN0_indelay <= TXPOWERDOWN0_ipd after IN_DELAY; TXPOWERDOWN1_indelay <= TXPOWERDOWN1_ipd after IN_DELAY; TXPREEMPHASIS0_indelay <= TXPREEMPHASIS0_ipd after IN_DELAY; TXPREEMPHASIS1_indelay <= TXPREEMPHASIS1_ipd after IN_DELAY; TXRESET0_indelay <= TXRESET0_ipd after IN_DELAY; TXRESET1_indelay <= TXRESET1_ipd after IN_DELAY; TXSEQUENCE0_indelay <= TXSEQUENCE0_ipd after IN_DELAY; TXSEQUENCE1_indelay <= TXSEQUENCE1_ipd after IN_DELAY; TXSTARTSEQ0_indelay <= TXSTARTSEQ0_ipd after IN_DELAY; TXSTARTSEQ1_indelay <= TXSTARTSEQ1_ipd after IN_DELAY; legacy_model: if SIM_MODE = "LEGACY" generate gtx_dual_swift_bw_1 : GTX_DUAL_SWIFT port map ( STEPPING => STEPPING_BINARY, AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, CB2_INH_CC_PERIOD_0 => CB2_INH_CC_PERIOD_0_BINARY, CB2_INH_CC_PERIOD_1 => CB2_INH_CC_PERIOD_1_BINARY, CDR_PH_ADJ_TIME => CDR_PH_ADJ_TIME_BINARY, CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, CHAN_BOND_KEEP_ALIGN_0 => CHAN_BOND_KEEP_ALIGN_0_BINARY, CHAN_BOND_KEEP_ALIGN_1 => CHAN_BOND_KEEP_ALIGN_1_BINARY, CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, CLK25_DIVIDER => CLK25_DIVIDER_BINARY, CLKINDC_B => CLKINDC_B_BINARY, CLKRCV_TRST => CLKRCV_TRST_BINARY, CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, CM_TRIM_0 => CM_TRIM_0_BINARY, CM_TRIM_1 => CM_TRIM_1_BINARY, COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, DFE_CAL_TIME => DFE_CAL_TIME_BINARY, DFE_CFG_0 => DFE_CFG_0_BINARY, DFE_CFG_1 => DFE_CFG_1_BINARY, GEARBOX_ENDEC_0 => GEARBOX_ENDEC_0_BINARY, GEARBOX_ENDEC_1 => GEARBOX_ENDEC_1_BINARY, MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, PLL_COM_CFG => PLL_COM_CFG_BINARY, PLL_CP_CFG => PLL_CP_CFG_BINARY, PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, PLL_FB_DCCEN => PLL_FB_DCCEN_BINARY, PLL_LKDET_CFG => PLL_LKDET_CFG_BINARY, PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, PLL_SATA_0 => PLL_SATA_0_BINARY, PLL_SATA_1 => PLL_SATA_1_BINARY, PLL_TDCC_CFG => PLL_TDCC_CFG_BINARY, PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, PMA_COM_CFG => PMA_COM_CFG_BINARY, PMA_RXSYNC_CFG_0 => PMA_RXSYNC_CFG_0_BINARY, PMA_RXSYNC_CFG_1 => PMA_RXSYNC_CFG_1_BINARY, PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, PMA_TX_CFG_0 => PMA_TX_CFG_0_BINARY, PMA_TX_CFG_1 => PMA_TX_CFG_1_BINARY, PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, RXGEARBOX_USE_0 => RXGEARBOX_USE_0_BINARY, RXGEARBOX_USE_1 => RXGEARBOX_USE_1_BINARY, RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, RX_EN_IDLE_HOLD_CDR => RX_EN_IDLE_HOLD_CDR_BINARY, RX_EN_IDLE_HOLD_DFE_0 => RX_EN_IDLE_HOLD_DFE_0_BINARY, RX_EN_IDLE_HOLD_DFE_1 => RX_EN_IDLE_HOLD_DFE_1_BINARY, RX_EN_IDLE_RESET_BUF_0 => RX_EN_IDLE_RESET_BUF_0_BINARY, RX_EN_IDLE_RESET_BUF_1 => RX_EN_IDLE_RESET_BUF_1_BINARY, RX_EN_IDLE_RESET_FR => RX_EN_IDLE_RESET_FR_BINARY, RX_EN_IDLE_RESET_PH => RX_EN_IDLE_RESET_PH_BINARY, RX_IDLE_HI_CNT_0 => RX_IDLE_HI_CNT_0_BINARY, RX_IDLE_HI_CNT_1 => RX_IDLE_HI_CNT_1_BINARY, RX_IDLE_LO_CNT_0 => RX_IDLE_LO_CNT_0_BINARY, RX_IDLE_LO_CNT_1 => RX_IDLE_LO_CNT_1_BINARY, RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, SIM_GTXRESET_SPEEDUP => SIM_GTXRESET_SPEEDUP_BINARY, SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, SIM_RECEIVER_DETECT_PASS_0 => SIM_RECEIVER_DETECT_PASS_0_BINARY, SIM_RECEIVER_DETECT_PASS_1 => SIM_RECEIVER_DETECT_PASS_1_BINARY, TERMINATION_CTRL => TERMINATION_CTRL_BINARY, TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, TERMINATION_OVRD => TERMINATION_OVRD_BINARY, TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, TXGEARBOX_USE_0 => TXGEARBOX_USE_0_BINARY, TXGEARBOX_USE_1 => TXGEARBOX_USE_1_BINARY, TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, TX_DETECT_RX_CFG_0 => TX_DETECT_RX_CFG_0_BINARY, TX_DETECT_RX_CFG_1 => TX_DETECT_RX_CFG_1_BINARY, TX_IDLE_DELAY_0 => TX_IDLE_DELAY_0_BINARY, TX_IDLE_DELAY_1 => TX_IDLE_DELAY_1_BINARY, TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, DFECLKDLYADJMONITOR0 => DFECLKDLYADJMONITOR0_outdelay, DFECLKDLYADJMONITOR1 => DFECLKDLYADJMONITOR1_outdelay, DFEEYEDACMONITOR0 => DFEEYEDACMONITOR0_outdelay, DFEEYEDACMONITOR1 => DFEEYEDACMONITOR1_outdelay, DFESENSCAL0 => DFESENSCAL0_outdelay, DFESENSCAL1 => DFESENSCAL1_outdelay, DFETAP1MONITOR0 => DFETAP1MONITOR0_outdelay, DFETAP1MONITOR1 => DFETAP1MONITOR1_outdelay, DFETAP2MONITOR0 => DFETAP2MONITOR0_outdelay, DFETAP2MONITOR1 => DFETAP2MONITOR1_outdelay, DFETAP3MONITOR0 => DFETAP3MONITOR0_outdelay, DFETAP3MONITOR1 => DFETAP3MONITOR1_outdelay, DFETAP4MONITOR0 => DFETAP4MONITOR0_outdelay, DFETAP4MONITOR1 => DFETAP4MONITOR1_outdelay, DO => DO_outdelay, DRDY => DRDY_outdelay, PHYSTATUS0 => PHYSTATUS0_outdelay, PHYSTATUS1 => PHYSTATUS1_outdelay, PLLLKDET => PLLLKDET_outdelay, REFCLKOUT => REFCLKOUT_outdelay, RESETDONE0 => RESETDONE0_outdelay, RESETDONE1 => RESETDONE1_outdelay, RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, RXCHARISK0 => RXCHARISK0_outdelay, RXCHARISK1 => RXCHARISK1_outdelay, RXCHBONDO0 => RXCHBONDO0_outdelay, RXCHBONDO1 => RXCHBONDO1_outdelay, RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, RXCOMMADET0 => RXCOMMADET0_outdelay, RXCOMMADET1 => RXCOMMADET1_outdelay, RXDATA0 => RXDATA0_outdelay, RXDATA1 => RXDATA1_outdelay, RXDATAVALID0 => RXDATAVALID0_outdelay, RXDATAVALID1 => RXDATAVALID1_outdelay, RXDISPERR0 => RXDISPERR0_outdelay, RXDISPERR1 => RXDISPERR1_outdelay, RXELECIDLE0 => RXELECIDLE0_outdelay, RXELECIDLE1 => RXELECIDLE1_outdelay, RXHEADER0 => RXHEADER0_outdelay, RXHEADER1 => RXHEADER1_outdelay, RXHEADERVALID0 => RXHEADERVALID0_outdelay, RXHEADERVALID1 => RXHEADERVALID1_outdelay, RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, RXPRBSERR0 => RXPRBSERR0_outdelay, RXPRBSERR1 => RXPRBSERR1_outdelay, RXRECCLK0 => RXRECCLK0_outdelay, RXRECCLK1 => RXRECCLK1_outdelay, RXRUNDISP0 => RXRUNDISP0_outdelay, RXRUNDISP1 => RXRUNDISP1_outdelay, RXSTARTOFSEQ0 => RXSTARTOFSEQ0_outdelay, RXSTARTOFSEQ1 => RXSTARTOFSEQ1_outdelay, RXSTATUS0 => RXSTATUS0_outdelay, RXSTATUS1 => RXSTATUS1_outdelay, RXVALID0 => RXVALID0_outdelay, RXVALID1 => RXVALID1_outdelay, TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, TXGEARBOXREADY0 => TXGEARBOXREADY0_outdelay, TXGEARBOXREADY1 => TXGEARBOXREADY1_outdelay, TXKERR0 => TXKERR0_outdelay, TXKERR1 => TXKERR1_outdelay, TXN0 => TXN0_outdelay, TXN1 => TXN1_outdelay, TXOUTCLK0 => TXOUTCLK0_outdelay, TXOUTCLK1 => TXOUTCLK1_outdelay, TXP0 => TXP0_outdelay, TXP1 => TXP1_outdelay, TXRUNDISP0 => TXRUNDISP0_outdelay, TXRUNDISP1 => TXRUNDISP1_outdelay, CLKIN => CLKIN_indelay, DADDR => DADDR_indelay, DCLK => DCLK_indelay, DEN => DEN_indelay, DFECLKDLYADJ0 => DFECLKDLYADJ0_indelay, DFECLKDLYADJ1 => DFECLKDLYADJ1_indelay, DFETAP10 => DFETAP10_indelay, DFETAP11 => DFETAP11_indelay, DFETAP20 => DFETAP20_indelay, DFETAP21 => DFETAP21_indelay, DFETAP30 => DFETAP30_indelay, DFETAP31 => DFETAP31_indelay, DFETAP40 => DFETAP40_indelay, DFETAP41 => DFETAP41_indelay, DI => DI_indelay, DWE => DWE_indelay, GSR => GSR, GTXRESET => GTXRESET_indelay, GTXTEST => GTXTEST_indelay, INTDATAWIDTH => INTDATAWIDTH_indelay, LOOPBACK0 => LOOPBACK0_indelay, LOOPBACK1 => LOOPBACK1_indelay, PLLLKDETEN => PLLLKDETEN_indelay, PLLPOWERDOWN => PLLPOWERDOWN_indelay, PRBSCNTRESET0 => PRBSCNTRESET0_indelay, PRBSCNTRESET1 => PRBSCNTRESET1_indelay, REFCLKPWRDNB => REFCLKPWRDNB_indelay, RXBUFRESET0 => RXBUFRESET0_indelay, RXBUFRESET1 => RXBUFRESET1_indelay, RXCDRRESET0 => RXCDRRESET0_indelay, RXCDRRESET1 => RXCDRRESET1_indelay, RXCHBONDI0 => RXCHBONDI0_indelay, RXCHBONDI1 => RXCHBONDI1_indelay, RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, RXDATAWIDTH0 => RXDATAWIDTH0_indelay, RXDATAWIDTH1 => RXDATAWIDTH1_indelay, RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, RXENCHANSYNC0 => RXENCHANSYNC0_indelay, RXENCHANSYNC1 => RXENCHANSYNC1_indelay, RXENEQB0 => RXENEQB0_indelay, RXENEQB1 => RXENEQB1_indelay, RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, RXENPMAPHASEALIGN0 => RXENPMAPHASEALIGN0_indelay, RXENPMAPHASEALIGN1 => RXENPMAPHASEALIGN1_indelay, RXENPRBSTST0 => RXENPRBSTST0_indelay, RXENPRBSTST1 => RXENPRBSTST1_indelay, RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, RXEQMIX0 => RXEQMIX0_indelay, RXEQMIX1 => RXEQMIX1_indelay, RXEQPOLE0 => RXEQPOLE0_indelay, RXEQPOLE1 => RXEQPOLE1_indelay, RXGEARBOXSLIP0 => RXGEARBOXSLIP0_indelay, RXGEARBOXSLIP1 => RXGEARBOXSLIP1_indelay, RXN0 => RXN0_indelay, RXN1 => RXN1_indelay, RXP0 => RXP0_indelay, RXP1 => RXP1_indelay, RXPMASETPHASE0 => RXPMASETPHASE0_indelay, RXPMASETPHASE1 => RXPMASETPHASE1_indelay, RXPOLARITY0 => RXPOLARITY0_indelay, RXPOLARITY1 => RXPOLARITY1_indelay, RXPOWERDOWN0 => RXPOWERDOWN0_indelay, RXPOWERDOWN1 => RXPOWERDOWN1_indelay, RXRESET0 => RXRESET0_indelay, RXRESET1 => RXRESET1_indelay, RXSLIDE0 => RXSLIDE0_indelay, RXSLIDE1 => RXSLIDE1_indelay, RXUSRCLK0 => RXUSRCLK0_indelay, RXUSRCLK1 => RXUSRCLK1_indelay, RXUSRCLK20 => RXUSRCLK20_indelay, RXUSRCLK21 => RXUSRCLK21_indelay, TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, TXCHARISK0 => TXCHARISK0_indelay, TXCHARISK1 => TXCHARISK1_indelay, TXCOMSTART0 => TXCOMSTART0_indelay, TXCOMSTART1 => TXCOMSTART1_indelay, TXCOMTYPE0 => TXCOMTYPE0_indelay, TXCOMTYPE1 => TXCOMTYPE1_indelay, TXDATA0 => TXDATA0_indelay, TXDATA1 => TXDATA1_indelay, TXDATAWIDTH0 => TXDATAWIDTH0_indelay, TXDATAWIDTH1 => TXDATAWIDTH1_indelay, TXDETECTRX0 => TXDETECTRX0_indelay, TXDETECTRX1 => TXDETECTRX1_indelay, TXDIFFCTRL0 => TXDIFFCTRL0_indelay, TXDIFFCTRL1 => TXDIFFCTRL1_indelay, TXELECIDLE0 => TXELECIDLE0_indelay, TXELECIDLE1 => TXELECIDLE1_indelay, TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, TXENPMAPHASEALIGN0 => TXENPMAPHASEALIGN0_indelay, TXENPMAPHASEALIGN1 => TXENPMAPHASEALIGN1_indelay, TXENPRBSTST0 => TXENPRBSTST0_indelay, TXENPRBSTST1 => TXENPRBSTST1_indelay, TXHEADER0 => TXHEADER0_indelay, TXHEADER1 => TXHEADER1_indelay, TXINHIBIT0 => TXINHIBIT0_indelay, TXINHIBIT1 => TXINHIBIT1_indelay, TXPMASETPHASE0 => TXPMASETPHASE0_indelay, TXPMASETPHASE1 => TXPMASETPHASE1_indelay, TXPOLARITY0 => TXPOLARITY0_indelay, TXPOLARITY1 => TXPOLARITY1_indelay, TXPOWERDOWN0 => TXPOWERDOWN0_indelay, TXPOWERDOWN1 => TXPOWERDOWN1_indelay, TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, TXRESET0 => TXRESET0_indelay, TXRESET1 => TXRESET1_indelay, TXSEQUENCE0 => TXSEQUENCE0_indelay, TXSEQUENCE1 => TXSEQUENCE1_indelay, TXSTARTSEQ0 => TXSTARTSEQ0_indelay, TXSTARTSEQ1 => TXSTARTSEQ1_indelay, TXUSRCLK0 => TXUSRCLK0_indelay, TXUSRCLK1 => TXUSRCLK1_indelay, TXUSRCLK20 => TXUSRCLK20_indelay, TXUSRCLK21 => TXUSRCLK21_indelay ); end generate legacy_model; fast_model: if SIM_MODE = "FAST" generate gtx_dual_fast_bw_1 : GTX_DUAL_FAST port map ( STEPPING => STEPPING_BINARY, AC_CAP_DIS_0 => AC_CAP_DIS_0_BINARY, AC_CAP_DIS_1 => AC_CAP_DIS_1_BINARY, ALIGN_COMMA_WORD_0 => ALIGN_COMMA_WORD_0_BINARY, ALIGN_COMMA_WORD_1 => ALIGN_COMMA_WORD_1_BINARY, CB2_INH_CC_PERIOD_0 => CB2_INH_CC_PERIOD_0_BINARY, CB2_INH_CC_PERIOD_1 => CB2_INH_CC_PERIOD_1_BINARY, CDR_PH_ADJ_TIME => CDR_PH_ADJ_TIME_BINARY, CHAN_BOND_1_MAX_SKEW_0 => CHAN_BOND_1_MAX_SKEW_0_BINARY, CHAN_BOND_1_MAX_SKEW_1 => CHAN_BOND_1_MAX_SKEW_1_BINARY, CHAN_BOND_2_MAX_SKEW_0 => CHAN_BOND_2_MAX_SKEW_0_BINARY, CHAN_BOND_2_MAX_SKEW_1 => CHAN_BOND_2_MAX_SKEW_1_BINARY, CHAN_BOND_KEEP_ALIGN_0 => CHAN_BOND_KEEP_ALIGN_0_BINARY, CHAN_BOND_KEEP_ALIGN_1 => CHAN_BOND_KEEP_ALIGN_1_BINARY, CHAN_BOND_LEVEL_0 => CHAN_BOND_LEVEL_0_BINARY, CHAN_BOND_LEVEL_1 => CHAN_BOND_LEVEL_1_BINARY, CHAN_BOND_MODE_0 => CHAN_BOND_MODE_0_BINARY, CHAN_BOND_MODE_1 => CHAN_BOND_MODE_1_BINARY, CHAN_BOND_SEQ_1_1_0 => CHAN_BOND_SEQ_1_1_0_BINARY, CHAN_BOND_SEQ_1_1_1 => CHAN_BOND_SEQ_1_1_1_BINARY, CHAN_BOND_SEQ_1_2_0 => CHAN_BOND_SEQ_1_2_0_BINARY, CHAN_BOND_SEQ_1_2_1 => CHAN_BOND_SEQ_1_2_1_BINARY, CHAN_BOND_SEQ_1_3_0 => CHAN_BOND_SEQ_1_3_0_BINARY, CHAN_BOND_SEQ_1_3_1 => CHAN_BOND_SEQ_1_3_1_BINARY, CHAN_BOND_SEQ_1_4_0 => CHAN_BOND_SEQ_1_4_0_BINARY, CHAN_BOND_SEQ_1_4_1 => CHAN_BOND_SEQ_1_4_1_BINARY, CHAN_BOND_SEQ_1_ENABLE_0 => CHAN_BOND_SEQ_1_ENABLE_0_BINARY, CHAN_BOND_SEQ_1_ENABLE_1 => CHAN_BOND_SEQ_1_ENABLE_1_BINARY, CHAN_BOND_SEQ_2_1_0 => CHAN_BOND_SEQ_2_1_0_BINARY, CHAN_BOND_SEQ_2_1_1 => CHAN_BOND_SEQ_2_1_1_BINARY, CHAN_BOND_SEQ_2_2_0 => CHAN_BOND_SEQ_2_2_0_BINARY, CHAN_BOND_SEQ_2_2_1 => CHAN_BOND_SEQ_2_2_1_BINARY, CHAN_BOND_SEQ_2_3_0 => CHAN_BOND_SEQ_2_3_0_BINARY, CHAN_BOND_SEQ_2_3_1 => CHAN_BOND_SEQ_2_3_1_BINARY, CHAN_BOND_SEQ_2_4_0 => CHAN_BOND_SEQ_2_4_0_BINARY, CHAN_BOND_SEQ_2_4_1 => CHAN_BOND_SEQ_2_4_1_BINARY, CHAN_BOND_SEQ_2_ENABLE_0 => CHAN_BOND_SEQ_2_ENABLE_0_BINARY, CHAN_BOND_SEQ_2_ENABLE_1 => CHAN_BOND_SEQ_2_ENABLE_1_BINARY, CHAN_BOND_SEQ_2_USE_0 => CHAN_BOND_SEQ_2_USE_0_BINARY, CHAN_BOND_SEQ_2_USE_1 => CHAN_BOND_SEQ_2_USE_1_BINARY, CHAN_BOND_SEQ_LEN_0 => CHAN_BOND_SEQ_LEN_0_BINARY, CHAN_BOND_SEQ_LEN_1 => CHAN_BOND_SEQ_LEN_1_BINARY, CLK25_DIVIDER => CLK25_DIVIDER_BINARY, CLKINDC_B => CLKINDC_B_BINARY, CLKRCV_TRST => CLKRCV_TRST_BINARY, CLK_CORRECT_USE_0 => CLK_CORRECT_USE_0_BINARY, CLK_CORRECT_USE_1 => CLK_CORRECT_USE_1_BINARY, CLK_COR_ADJ_LEN_0 => CLK_COR_ADJ_LEN_0_BINARY, CLK_COR_ADJ_LEN_1 => CLK_COR_ADJ_LEN_1_BINARY, CLK_COR_DET_LEN_0 => CLK_COR_DET_LEN_0_BINARY, CLK_COR_DET_LEN_1 => CLK_COR_DET_LEN_1_BINARY, CLK_COR_INSERT_IDLE_FLAG_0 => CLK_COR_INSERT_IDLE_FLAG_0_BINARY, CLK_COR_INSERT_IDLE_FLAG_1 => CLK_COR_INSERT_IDLE_FLAG_1_BINARY, CLK_COR_KEEP_IDLE_0 => CLK_COR_KEEP_IDLE_0_BINARY, CLK_COR_KEEP_IDLE_1 => CLK_COR_KEEP_IDLE_1_BINARY, CLK_COR_MAX_LAT_0 => CLK_COR_MAX_LAT_0_BINARY, CLK_COR_MAX_LAT_1 => CLK_COR_MAX_LAT_1_BINARY, CLK_COR_MIN_LAT_0 => CLK_COR_MIN_LAT_0_BINARY, CLK_COR_MIN_LAT_1 => CLK_COR_MIN_LAT_1_BINARY, CLK_COR_PRECEDENCE_0 => CLK_COR_PRECEDENCE_0_BINARY, CLK_COR_PRECEDENCE_1 => CLK_COR_PRECEDENCE_1_BINARY, CLK_COR_REPEAT_WAIT_0 => CLK_COR_REPEAT_WAIT_0_BINARY, CLK_COR_REPEAT_WAIT_1 => CLK_COR_REPEAT_WAIT_1_BINARY, CLK_COR_SEQ_1_1_0 => CLK_COR_SEQ_1_1_0_BINARY, CLK_COR_SEQ_1_1_1 => CLK_COR_SEQ_1_1_1_BINARY, CLK_COR_SEQ_1_2_0 => CLK_COR_SEQ_1_2_0_BINARY, CLK_COR_SEQ_1_2_1 => CLK_COR_SEQ_1_2_1_BINARY, CLK_COR_SEQ_1_3_0 => CLK_COR_SEQ_1_3_0_BINARY, CLK_COR_SEQ_1_3_1 => CLK_COR_SEQ_1_3_1_BINARY, CLK_COR_SEQ_1_4_0 => CLK_COR_SEQ_1_4_0_BINARY, CLK_COR_SEQ_1_4_1 => CLK_COR_SEQ_1_4_1_BINARY, CLK_COR_SEQ_1_ENABLE_0 => CLK_COR_SEQ_1_ENABLE_0_BINARY, CLK_COR_SEQ_1_ENABLE_1 => CLK_COR_SEQ_1_ENABLE_1_BINARY, CLK_COR_SEQ_2_1_0 => CLK_COR_SEQ_2_1_0_BINARY, CLK_COR_SEQ_2_1_1 => CLK_COR_SEQ_2_1_1_BINARY, CLK_COR_SEQ_2_2_0 => CLK_COR_SEQ_2_2_0_BINARY, CLK_COR_SEQ_2_2_1 => CLK_COR_SEQ_2_2_1_BINARY, CLK_COR_SEQ_2_3_0 => CLK_COR_SEQ_2_3_0_BINARY, CLK_COR_SEQ_2_3_1 => CLK_COR_SEQ_2_3_1_BINARY, CLK_COR_SEQ_2_4_0 => CLK_COR_SEQ_2_4_0_BINARY, CLK_COR_SEQ_2_4_1 => CLK_COR_SEQ_2_4_1_BINARY, CLK_COR_SEQ_2_ENABLE_0 => CLK_COR_SEQ_2_ENABLE_0_BINARY, CLK_COR_SEQ_2_ENABLE_1 => CLK_COR_SEQ_2_ENABLE_1_BINARY, CLK_COR_SEQ_2_USE_0 => CLK_COR_SEQ_2_USE_0_BINARY, CLK_COR_SEQ_2_USE_1 => CLK_COR_SEQ_2_USE_1_BINARY, CM_TRIM_0 => CM_TRIM_0_BINARY, CM_TRIM_1 => CM_TRIM_1_BINARY, COMMA_10B_ENABLE_0 => COMMA_10B_ENABLE_0_BINARY, COMMA_10B_ENABLE_1 => COMMA_10B_ENABLE_1_BINARY, COMMA_DOUBLE_0 => COMMA_DOUBLE_0_BINARY, COMMA_DOUBLE_1 => COMMA_DOUBLE_1_BINARY, COM_BURST_VAL_0 => COM_BURST_VAL_0_BINARY, COM_BURST_VAL_1 => COM_BURST_VAL_1_BINARY, DEC_MCOMMA_DETECT_0 => DEC_MCOMMA_DETECT_0_BINARY, DEC_MCOMMA_DETECT_1 => DEC_MCOMMA_DETECT_1_BINARY, DEC_PCOMMA_DETECT_0 => DEC_PCOMMA_DETECT_0_BINARY, DEC_PCOMMA_DETECT_1 => DEC_PCOMMA_DETECT_1_BINARY, DEC_VALID_COMMA_ONLY_0 => DEC_VALID_COMMA_ONLY_0_BINARY, DEC_VALID_COMMA_ONLY_1 => DEC_VALID_COMMA_ONLY_1_BINARY, DFE_CAL_TIME => DFE_CAL_TIME_BINARY, DFE_CFG_0 => DFE_CFG_0_BINARY, DFE_CFG_1 => DFE_CFG_1_BINARY, GEARBOX_ENDEC_0 => GEARBOX_ENDEC_0_BINARY, GEARBOX_ENDEC_1 => GEARBOX_ENDEC_1_BINARY, MCOMMA_10B_VALUE_0 => MCOMMA_10B_VALUE_0_BINARY, MCOMMA_10B_VALUE_1 => MCOMMA_10B_VALUE_1_BINARY, MCOMMA_DETECT_0 => MCOMMA_DETECT_0_BINARY, MCOMMA_DETECT_1 => MCOMMA_DETECT_1_BINARY, OOBDETECT_THRESHOLD_0 => OOBDETECT_THRESHOLD_0_BINARY, OOBDETECT_THRESHOLD_1 => OOBDETECT_THRESHOLD_1_BINARY, OOB_CLK_DIVIDER => OOB_CLK_DIVIDER_BINARY, OVERSAMPLE_MODE => OVERSAMPLE_MODE_BINARY, PCI_EXPRESS_MODE_0 => PCI_EXPRESS_MODE_0_BINARY, PCI_EXPRESS_MODE_1 => PCI_EXPRESS_MODE_1_BINARY, PCOMMA_10B_VALUE_0 => PCOMMA_10B_VALUE_0_BINARY, PCOMMA_10B_VALUE_1 => PCOMMA_10B_VALUE_1_BINARY, PCOMMA_DETECT_0 => PCOMMA_DETECT_0_BINARY, PCOMMA_DETECT_1 => PCOMMA_DETECT_1_BINARY, PLL_COM_CFG => PLL_COM_CFG_BINARY, PLL_CP_CFG => PLL_CP_CFG_BINARY, PLL_DIVSEL_FB => PLL_DIVSEL_FB_BINARY, PLL_DIVSEL_REF => PLL_DIVSEL_REF_BINARY, PLL_FB_DCCEN => PLL_FB_DCCEN_BINARY, PLL_LKDET_CFG => PLL_LKDET_CFG_BINARY, PLL_RXDIVSEL_OUT_0 => PLL_RXDIVSEL_OUT_0_BINARY, PLL_RXDIVSEL_OUT_1 => PLL_RXDIVSEL_OUT_1_BINARY, PLL_SATA_0 => PLL_SATA_0_BINARY, PLL_SATA_1 => PLL_SATA_1_BINARY, PLL_TDCC_CFG => PLL_TDCC_CFG_BINARY, PLL_TXDIVSEL_OUT_0 => PLL_TXDIVSEL_OUT_0_BINARY, PLL_TXDIVSEL_OUT_1 => PLL_TXDIVSEL_OUT_1_BINARY, PMA_CDR_SCAN_0 => PMA_CDR_SCAN_0_BINARY, PMA_CDR_SCAN_1 => PMA_CDR_SCAN_1_BINARY, PMA_COM_CFG => PMA_COM_CFG_BINARY, PMA_RXSYNC_CFG_0 => PMA_RXSYNC_CFG_0_BINARY, PMA_RXSYNC_CFG_1 => PMA_RXSYNC_CFG_1_BINARY, PMA_RX_CFG_0 => PMA_RX_CFG_0_BINARY, PMA_RX_CFG_1 => PMA_RX_CFG_1_BINARY, PMA_TX_CFG_0 => PMA_TX_CFG_0_BINARY, PMA_TX_CFG_1 => PMA_TX_CFG_1_BINARY, PRBS_ERR_THRESHOLD_0 => PRBS_ERR_THRESHOLD_0_BINARY, PRBS_ERR_THRESHOLD_1 => PRBS_ERR_THRESHOLD_1_BINARY, RCV_TERM_GND_0 => RCV_TERM_GND_0_BINARY, RCV_TERM_GND_1 => RCV_TERM_GND_1_BINARY, RCV_TERM_VTTRX_0 => RCV_TERM_VTTRX_0_BINARY, RCV_TERM_VTTRX_1 => RCV_TERM_VTTRX_1_BINARY, RXGEARBOX_USE_0 => RXGEARBOX_USE_0_BINARY, RXGEARBOX_USE_1 => RXGEARBOX_USE_1_BINARY, RX_BUFFER_USE_0 => RX_BUFFER_USE_0_BINARY, RX_BUFFER_USE_1 => RX_BUFFER_USE_1_BINARY, RX_DECODE_SEQ_MATCH_0 => RX_DECODE_SEQ_MATCH_0_BINARY, RX_DECODE_SEQ_MATCH_1 => RX_DECODE_SEQ_MATCH_1_BINARY, RX_EN_IDLE_HOLD_CDR => RX_EN_IDLE_HOLD_CDR_BINARY, RX_EN_IDLE_HOLD_DFE_0 => RX_EN_IDLE_HOLD_DFE_0_BINARY, RX_EN_IDLE_HOLD_DFE_1 => RX_EN_IDLE_HOLD_DFE_1_BINARY, RX_EN_IDLE_RESET_BUF_0 => RX_EN_IDLE_RESET_BUF_0_BINARY, RX_EN_IDLE_RESET_BUF_1 => RX_EN_IDLE_RESET_BUF_1_BINARY, RX_EN_IDLE_RESET_FR => RX_EN_IDLE_RESET_FR_BINARY, RX_EN_IDLE_RESET_PH => RX_EN_IDLE_RESET_PH_BINARY, RX_IDLE_HI_CNT_0 => RX_IDLE_HI_CNT_0_BINARY, RX_IDLE_HI_CNT_1 => RX_IDLE_HI_CNT_1_BINARY, RX_IDLE_LO_CNT_0 => RX_IDLE_LO_CNT_0_BINARY, RX_IDLE_LO_CNT_1 => RX_IDLE_LO_CNT_1_BINARY, RX_LOSS_OF_SYNC_FSM_0 => RX_LOSS_OF_SYNC_FSM_0_BINARY, RX_LOSS_OF_SYNC_FSM_1 => RX_LOSS_OF_SYNC_FSM_1_BINARY, RX_LOS_INVALID_INCR_0 => RX_LOS_INVALID_INCR_0_BINARY, RX_LOS_INVALID_INCR_1 => RX_LOS_INVALID_INCR_1_BINARY, RX_LOS_THRESHOLD_0 => RX_LOS_THRESHOLD_0_BINARY, RX_LOS_THRESHOLD_1 => RX_LOS_THRESHOLD_1_BINARY, RX_SLIDE_MODE_0 => RX_SLIDE_MODE_0_BINARY, RX_SLIDE_MODE_1 => RX_SLIDE_MODE_1_BINARY, RX_STATUS_FMT_0 => RX_STATUS_FMT_0_BINARY, RX_STATUS_FMT_1 => RX_STATUS_FMT_1_BINARY, RX_XCLK_SEL_0 => RX_XCLK_SEL_0_BINARY, RX_XCLK_SEL_1 => RX_XCLK_SEL_1_BINARY, SATA_BURST_VAL_0 => SATA_BURST_VAL_0_BINARY, SATA_BURST_VAL_1 => SATA_BURST_VAL_1_BINARY, SATA_IDLE_VAL_0 => SATA_IDLE_VAL_0_BINARY, SATA_IDLE_VAL_1 => SATA_IDLE_VAL_1_BINARY, SATA_MAX_BURST_0 => SATA_MAX_BURST_0_BINARY, SATA_MAX_BURST_1 => SATA_MAX_BURST_1_BINARY, SATA_MAX_INIT_0 => SATA_MAX_INIT_0_BINARY, SATA_MAX_INIT_1 => SATA_MAX_INIT_1_BINARY, SATA_MAX_WAKE_0 => SATA_MAX_WAKE_0_BINARY, SATA_MAX_WAKE_1 => SATA_MAX_WAKE_1_BINARY, SATA_MIN_BURST_0 => SATA_MIN_BURST_0_BINARY, SATA_MIN_BURST_1 => SATA_MIN_BURST_1_BINARY, SATA_MIN_INIT_0 => SATA_MIN_INIT_0_BINARY, SATA_MIN_INIT_1 => SATA_MIN_INIT_1_BINARY, SATA_MIN_WAKE_0 => SATA_MIN_WAKE_0_BINARY, SATA_MIN_WAKE_1 => SATA_MIN_WAKE_1_BINARY, SIM_GTXRESET_SPEEDUP => SIM_GTXRESET_SPEEDUP_BINARY, SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2_BINARY, SIM_RECEIVER_DETECT_PASS_0 => SIM_RECEIVER_DETECT_PASS_0_BINARY, SIM_RECEIVER_DETECT_PASS_1 => SIM_RECEIVER_DETECT_PASS_1_BINARY, TERMINATION_CTRL => TERMINATION_CTRL_BINARY, TERMINATION_IMP_0 => TERMINATION_IMP_0_BINARY, TERMINATION_IMP_1 => TERMINATION_IMP_1_BINARY, TERMINATION_OVRD => TERMINATION_OVRD_BINARY, TRANS_TIME_FROM_P2_0 => TRANS_TIME_FROM_P2_0_BINARY, TRANS_TIME_FROM_P2_1 => TRANS_TIME_FROM_P2_1_BINARY, TRANS_TIME_NON_P2_0 => TRANS_TIME_NON_P2_0_BINARY, TRANS_TIME_NON_P2_1 => TRANS_TIME_NON_P2_1_BINARY, TRANS_TIME_TO_P2_0 => TRANS_TIME_TO_P2_0_BINARY, TRANS_TIME_TO_P2_1 => TRANS_TIME_TO_P2_1_BINARY, TXGEARBOX_USE_0 => TXGEARBOX_USE_0_BINARY, TXGEARBOX_USE_1 => TXGEARBOX_USE_1_BINARY, TXRX_INVERT_0 => TXRX_INVERT_0_BINARY, TXRX_INVERT_1 => TXRX_INVERT_1_BINARY, TX_BUFFER_USE_0 => TX_BUFFER_USE_0_BINARY, TX_BUFFER_USE_1 => TX_BUFFER_USE_1_BINARY, TX_DETECT_RX_CFG_0 => TX_DETECT_RX_CFG_0_BINARY, TX_DETECT_RX_CFG_1 => TX_DETECT_RX_CFG_1_BINARY, TX_IDLE_DELAY_0 => TX_IDLE_DELAY_0_BINARY, TX_IDLE_DELAY_1 => TX_IDLE_DELAY_1_BINARY, TX_XCLK_SEL_0 => TX_XCLK_SEL_0_BINARY, TX_XCLK_SEL_1 => TX_XCLK_SEL_1_BINARY, DFECLKDLYADJMONITOR0 => DFECLKDLYADJMONITOR0_outdelay, DFECLKDLYADJMONITOR1 => DFECLKDLYADJMONITOR1_outdelay, DFEEYEDACMONITOR0 => DFEEYEDACMONITOR0_outdelay, DFEEYEDACMONITOR1 => DFEEYEDACMONITOR1_outdelay, DFESENSCAL0 => DFESENSCAL0_outdelay, DFESENSCAL1 => DFESENSCAL1_outdelay, DFETAP1MONITOR0 => DFETAP1MONITOR0_outdelay, DFETAP1MONITOR1 => DFETAP1MONITOR1_outdelay, DFETAP2MONITOR0 => DFETAP2MONITOR0_outdelay, DFETAP2MONITOR1 => DFETAP2MONITOR1_outdelay, DFETAP3MONITOR0 => DFETAP3MONITOR0_outdelay, DFETAP3MONITOR1 => DFETAP3MONITOR1_outdelay, DFETAP4MONITOR0 => DFETAP4MONITOR0_outdelay, DFETAP4MONITOR1 => DFETAP4MONITOR1_outdelay, DO => DO_outdelay, DRDY => DRDY_outdelay, PHYSTATUS0 => PHYSTATUS0_outdelay, PHYSTATUS1 => PHYSTATUS1_outdelay, PLLLKDET => PLLLKDET_outdelay, REFCLKOUT => REFCLKOUT_outdelay, RESETDONE0 => RESETDONE0_outdelay, RESETDONE1 => RESETDONE1_outdelay, RXBUFSTATUS0 => RXBUFSTATUS0_outdelay, RXBUFSTATUS1 => RXBUFSTATUS1_outdelay, RXBYTEISALIGNED0 => RXBYTEISALIGNED0_outdelay, RXBYTEISALIGNED1 => RXBYTEISALIGNED1_outdelay, RXBYTEREALIGN0 => RXBYTEREALIGN0_outdelay, RXBYTEREALIGN1 => RXBYTEREALIGN1_outdelay, RXCHANBONDSEQ0 => RXCHANBONDSEQ0_outdelay, RXCHANBONDSEQ1 => RXCHANBONDSEQ1_outdelay, RXCHANISALIGNED0 => RXCHANISALIGNED0_outdelay, RXCHANISALIGNED1 => RXCHANISALIGNED1_outdelay, RXCHANREALIGN0 => RXCHANREALIGN0_outdelay, RXCHANREALIGN1 => RXCHANREALIGN1_outdelay, RXCHARISCOMMA0 => RXCHARISCOMMA0_outdelay, RXCHARISCOMMA1 => RXCHARISCOMMA1_outdelay, RXCHARISK0 => RXCHARISK0_outdelay, RXCHARISK1 => RXCHARISK1_outdelay, RXCHBONDO0 => RXCHBONDO0_outdelay, RXCHBONDO1 => RXCHBONDO1_outdelay, RXCLKCORCNT0 => RXCLKCORCNT0_outdelay, RXCLKCORCNT1 => RXCLKCORCNT1_outdelay, RXCOMMADET0 => RXCOMMADET0_outdelay, RXCOMMADET1 => RXCOMMADET1_outdelay, RXDATA0 => RXDATA0_outdelay, RXDATA1 => RXDATA1_outdelay, RXDATAVALID0 => RXDATAVALID0_outdelay, RXDATAVALID1 => RXDATAVALID1_outdelay, RXDISPERR0 => RXDISPERR0_outdelay, RXDISPERR1 => RXDISPERR1_outdelay, RXELECIDLE0 => RXELECIDLE0_outdelay, RXELECIDLE1 => RXELECIDLE1_outdelay, RXHEADER0 => RXHEADER0_outdelay, RXHEADER1 => RXHEADER1_outdelay, RXHEADERVALID0 => RXHEADERVALID0_outdelay, RXHEADERVALID1 => RXHEADERVALID1_outdelay, RXLOSSOFSYNC0 => RXLOSSOFSYNC0_outdelay, RXLOSSOFSYNC1 => RXLOSSOFSYNC1_outdelay, RXNOTINTABLE0 => RXNOTINTABLE0_outdelay, RXNOTINTABLE1 => RXNOTINTABLE1_outdelay, RXOVERSAMPLEERR0 => RXOVERSAMPLEERR0_outdelay, RXOVERSAMPLEERR1 => RXOVERSAMPLEERR1_outdelay, RXPRBSERR0 => RXPRBSERR0_outdelay, RXPRBSERR1 => RXPRBSERR1_outdelay, RXRECCLK0 => RXRECCLK0_outdelay, RXRECCLK1 => RXRECCLK1_outdelay, RXRUNDISP0 => RXRUNDISP0_outdelay, RXRUNDISP1 => RXRUNDISP1_outdelay, RXSTARTOFSEQ0 => RXSTARTOFSEQ0_outdelay, RXSTARTOFSEQ1 => RXSTARTOFSEQ1_outdelay, RXSTATUS0 => RXSTATUS0_outdelay, RXSTATUS1 => RXSTATUS1_outdelay, RXVALID0 => RXVALID0_outdelay, RXVALID1 => RXVALID1_outdelay, TXBUFSTATUS0 => TXBUFSTATUS0_outdelay, TXBUFSTATUS1 => TXBUFSTATUS1_outdelay, TXGEARBOXREADY0 => TXGEARBOXREADY0_outdelay, TXGEARBOXREADY1 => TXGEARBOXREADY1_outdelay, TXKERR0 => TXKERR0_outdelay, TXKERR1 => TXKERR1_outdelay, TXN0 => TXN0_outdelay, TXN1 => TXN1_outdelay, TXOUTCLK0 => TXOUTCLK0_outdelay, TXOUTCLK1 => TXOUTCLK1_outdelay, TXP0 => TXP0_outdelay, TXP1 => TXP1_outdelay, TXRUNDISP0 => TXRUNDISP0_outdelay, TXRUNDISP1 => TXRUNDISP1_outdelay, CLKIN => CLKIN_indelay, DADDR => DADDR_indelay, DCLK => DCLK_indelay, DEN => DEN_indelay, DFECLKDLYADJ0 => DFECLKDLYADJ0_indelay, DFECLKDLYADJ1 => DFECLKDLYADJ1_indelay, DFETAP10 => DFETAP10_indelay, DFETAP11 => DFETAP11_indelay, DFETAP20 => DFETAP20_indelay, DFETAP21 => DFETAP21_indelay, DFETAP30 => DFETAP30_indelay, DFETAP31 => DFETAP31_indelay, DFETAP40 => DFETAP40_indelay, DFETAP41 => DFETAP41_indelay, DI => DI_indelay, DWE => DWE_indelay, GSR => GSR, GTXRESET => GTXRESET_indelay, GTXTEST => GTXTEST_indelay, INTDATAWIDTH => INTDATAWIDTH_indelay, LOOPBACK0 => LOOPBACK0_indelay, LOOPBACK1 => LOOPBACK1_indelay, PLLLKDETEN => PLLLKDETEN_indelay, PLLPOWERDOWN => PLLPOWERDOWN_indelay, PRBSCNTRESET0 => PRBSCNTRESET0_indelay, PRBSCNTRESET1 => PRBSCNTRESET1_indelay, REFCLKPWRDNB => REFCLKPWRDNB_indelay, RXBUFRESET0 => RXBUFRESET0_indelay, RXBUFRESET1 => RXBUFRESET1_indelay, RXCDRRESET0 => RXCDRRESET0_indelay, RXCDRRESET1 => RXCDRRESET1_indelay, RXCHBONDI0 => RXCHBONDI0_indelay, RXCHBONDI1 => RXCHBONDI1_indelay, RXCOMMADETUSE0 => RXCOMMADETUSE0_indelay, RXCOMMADETUSE1 => RXCOMMADETUSE1_indelay, RXDATAWIDTH0 => RXDATAWIDTH0_indelay, RXDATAWIDTH1 => RXDATAWIDTH1_indelay, RXDEC8B10BUSE0 => RXDEC8B10BUSE0_indelay, RXDEC8B10BUSE1 => RXDEC8B10BUSE1_indelay, RXENCHANSYNC0 => RXENCHANSYNC0_indelay, RXENCHANSYNC1 => RXENCHANSYNC1_indelay, RXENEQB0 => RXENEQB0_indelay, RXENEQB1 => RXENEQB1_indelay, RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_indelay, RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_indelay, RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_indelay, RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_indelay, RXENPMAPHASEALIGN0 => RXENPMAPHASEALIGN0_indelay, RXENPMAPHASEALIGN1 => RXENPMAPHASEALIGN1_indelay, RXENPRBSTST0 => RXENPRBSTST0_indelay, RXENPRBSTST1 => RXENPRBSTST1_indelay, RXENSAMPLEALIGN0 => RXENSAMPLEALIGN0_indelay, RXENSAMPLEALIGN1 => RXENSAMPLEALIGN1_indelay, RXEQMIX0 => RXEQMIX0_indelay, RXEQMIX1 => RXEQMIX1_indelay, RXEQPOLE0 => RXEQPOLE0_indelay, RXEQPOLE1 => RXEQPOLE1_indelay, RXGEARBOXSLIP0 => RXGEARBOXSLIP0_indelay, RXGEARBOXSLIP1 => RXGEARBOXSLIP1_indelay, RXN0 => RXN0_indelay, RXN1 => RXN1_indelay, RXP0 => RXP0_indelay, RXP1 => RXP1_indelay, RXPMASETPHASE0 => RXPMASETPHASE0_indelay, RXPMASETPHASE1 => RXPMASETPHASE1_indelay, RXPOLARITY0 => RXPOLARITY0_indelay, RXPOLARITY1 => RXPOLARITY1_indelay, RXPOWERDOWN0 => RXPOWERDOWN0_indelay, RXPOWERDOWN1 => RXPOWERDOWN1_indelay, RXRESET0 => RXRESET0_indelay, RXRESET1 => RXRESET1_indelay, RXSLIDE0 => RXSLIDE0_indelay, RXSLIDE1 => RXSLIDE1_indelay, RXUSRCLK0 => RXUSRCLK0_indelay, RXUSRCLK1 => RXUSRCLK1_indelay, RXUSRCLK20 => RXUSRCLK20_indelay, RXUSRCLK21 => RXUSRCLK21_indelay, TXBUFDIFFCTRL0 => TXBUFDIFFCTRL0_indelay, TXBUFDIFFCTRL1 => TXBUFDIFFCTRL1_indelay, TXBYPASS8B10B0 => TXBYPASS8B10B0_indelay, TXBYPASS8B10B1 => TXBYPASS8B10B1_indelay, TXCHARDISPMODE0 => TXCHARDISPMODE0_indelay, TXCHARDISPMODE1 => TXCHARDISPMODE1_indelay, TXCHARDISPVAL0 => TXCHARDISPVAL0_indelay, TXCHARDISPVAL1 => TXCHARDISPVAL1_indelay, TXCHARISK0 => TXCHARISK0_indelay, TXCHARISK1 => TXCHARISK1_indelay, TXCOMSTART0 => TXCOMSTART0_indelay, TXCOMSTART1 => TXCOMSTART1_indelay, TXCOMTYPE0 => TXCOMTYPE0_indelay, TXCOMTYPE1 => TXCOMTYPE1_indelay, TXDATA0 => TXDATA0_indelay, TXDATA1 => TXDATA1_indelay, TXDATAWIDTH0 => TXDATAWIDTH0_indelay, TXDATAWIDTH1 => TXDATAWIDTH1_indelay, TXDETECTRX0 => TXDETECTRX0_indelay, TXDETECTRX1 => TXDETECTRX1_indelay, TXDIFFCTRL0 => TXDIFFCTRL0_indelay, TXDIFFCTRL1 => TXDIFFCTRL1_indelay, TXELECIDLE0 => TXELECIDLE0_indelay, TXELECIDLE1 => TXELECIDLE1_indelay, TXENC8B10BUSE0 => TXENC8B10BUSE0_indelay, TXENC8B10BUSE1 => TXENC8B10BUSE1_indelay, TXENPMAPHASEALIGN0 => TXENPMAPHASEALIGN0_indelay, TXENPMAPHASEALIGN1 => TXENPMAPHASEALIGN1_indelay, TXENPRBSTST0 => TXENPRBSTST0_indelay, TXENPRBSTST1 => TXENPRBSTST1_indelay, TXHEADER0 => TXHEADER0_indelay, TXHEADER1 => TXHEADER1_indelay, TXINHIBIT0 => TXINHIBIT0_indelay, TXINHIBIT1 => TXINHIBIT1_indelay, TXPMASETPHASE0 => TXPMASETPHASE0_indelay, TXPMASETPHASE1 => TXPMASETPHASE1_indelay, TXPOLARITY0 => TXPOLARITY0_indelay, TXPOLARITY1 => TXPOLARITY1_indelay, TXPOWERDOWN0 => TXPOWERDOWN0_indelay, TXPOWERDOWN1 => TXPOWERDOWN1_indelay, TXPREEMPHASIS0 => TXPREEMPHASIS0_indelay, TXPREEMPHASIS1 => TXPREEMPHASIS1_indelay, TXRESET0 => TXRESET0_indelay, TXRESET1 => TXRESET1_indelay, TXSEQUENCE0 => TXSEQUENCE0_indelay, TXSEQUENCE1 => TXSEQUENCE1_indelay, TXSTARTSEQ0 => TXSTARTSEQ0_indelay, TXSTARTSEQ1 => TXSTARTSEQ1_indelay, TXUSRCLK0 => TXUSRCLK0_indelay, TXUSRCLK1 => TXUSRCLK1_indelay, TXUSRCLK20 => TXUSRCLK20_indelay, TXUSRCLK21 => TXUSRCLK21_indelay ); end generate fast_model; INIPROC : process begin case PLL_TXDIVSEL_OUT_0 is when 1 => PLL_TXDIVSEL_OUT_0_BINARY <= "00"; when 2 => PLL_TXDIVSEL_OUT_0_BINARY <= "01"; when 4 => PLL_TXDIVSEL_OUT_0_BINARY <= "10"; when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; end case; case PLL_RXDIVSEL_OUT_0 is when 1 => PLL_RXDIVSEL_OUT_0_BINARY <= "00"; when 2 => PLL_RXDIVSEL_OUT_0_BINARY <= "01"; when 4 => PLL_RXDIVSEL_OUT_0_BINARY <= "10"; when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_0 is not in 1, 2, 4." severity error; end case; case PLL_TXDIVSEL_OUT_1 is when 1 => PLL_TXDIVSEL_OUT_1_BINARY <= "00"; when 2 => PLL_TXDIVSEL_OUT_1_BINARY <= "01"; when 4 => PLL_TXDIVSEL_OUT_1_BINARY <= "10"; when others => assert FALSE report "Error : PLL_TXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; end case; case PLL_RXDIVSEL_OUT_1 is when 1 => PLL_RXDIVSEL_OUT_1_BINARY <= "00"; when 2 => PLL_RXDIVSEL_OUT_1_BINARY <= "01"; when 4 => PLL_RXDIVSEL_OUT_1_BINARY <= "10"; when others => assert FALSE report "Error : PLL_RXDIVSEL_OUT_1 is not in 1, 2, 4." severity error; end case; case PLL_DIVSEL_FB is when 1 => PLL_DIVSEL_FB_BINARY <= "10000"; when 2 => PLL_DIVSEL_FB_BINARY <= "00000"; when 3 => PLL_DIVSEL_FB_BINARY <= "00001"; when 4 => PLL_DIVSEL_FB_BINARY <= "00010"; when 5 => PLL_DIVSEL_FB_BINARY <= "00011"; when 8 => PLL_DIVSEL_FB_BINARY <= "00110"; when 10 => PLL_DIVSEL_FB_BINARY <= "00111"; when others => assert FALSE report "Error : PLL_DIVSEL_FB is not in 1, 2, 3, 4, 5, 8, 10." severity error; end case; case PLL_DIVSEL_REF is when 1 => PLL_DIVSEL_REF_BINARY <= "010000"; when 2 => PLL_DIVSEL_REF_BINARY <= "000000"; when 3 => PLL_DIVSEL_REF_BINARY <= "000001"; when 4 => PLL_DIVSEL_REF_BINARY <= "000010"; when 5 => PLL_DIVSEL_REF_BINARY <= "000011"; when 6 => PLL_DIVSEL_REF_BINARY <= "000101"; when 8 => PLL_DIVSEL_REF_BINARY <= "000110"; when 10 => PLL_DIVSEL_REF_BINARY <= "000111"; when 12 => PLL_DIVSEL_REF_BINARY <= "001101"; when 16 => PLL_DIVSEL_REF_BINARY <= "001110"; when 20 => PLL_DIVSEL_REF_BINARY <= "001111"; when others => assert FALSE report "Error : PLL_DIVSEL_REF is not in 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20." severity error; end case; case PLL_SATA_0 is when FALSE => PLL_SATA_0_BINARY <= '0'; when TRUE => PLL_SATA_0_BINARY <= '1'; when others => assert FALSE report "Error : PLL_SATA_0 is neither TRUE nor FALSE." severity error; end case; case PLL_SATA_1 is when FALSE => PLL_SATA_1_BINARY <= '0'; when TRUE => PLL_SATA_1_BINARY <= '1'; when others => assert FALSE report "Error : PLL_SATA_1 is neither TRUE nor FALSE." severity error; end case; case OOB_CLK_DIVIDER is when 1 => OOB_CLK_DIVIDER_BINARY <= "000"; when 2 => OOB_CLK_DIVIDER_BINARY <= "001"; when 4 => OOB_CLK_DIVIDER_BINARY <= "010"; when 6 => OOB_CLK_DIVIDER_BINARY <= "011"; when 8 => OOB_CLK_DIVIDER_BINARY <= "100"; when 10 => OOB_CLK_DIVIDER_BINARY <= "101"; when 12 => OOB_CLK_DIVIDER_BINARY <= "110"; when 14 => OOB_CLK_DIVIDER_BINARY <= "111"; when others => assert FALSE report "Error : OOB_CLK_DIVIDER is not in 1, 2, 4, 6, 8, 10, 12, 14." severity error; end case; if (OOBDETECT_THRESHOLD_0 = "110") then OOBDETECT_THRESHOLD_0_BINARY <= "110"; elsif (OOBDETECT_THRESHOLD_0 = "111") then OOBDETECT_THRESHOLD_0_BINARY <= "111"; else assert FALSE report "Warning : OOBDETECT_THRESHOLD_0 is not in 110, 111." severity warning; end if; if (OOBDETECT_THRESHOLD_1 = "110") then OOBDETECT_THRESHOLD_1_BINARY <= "110"; elsif (OOBDETECT_THRESHOLD_1 = "111") then OOBDETECT_THRESHOLD_1_BINARY <= "111"; else assert FALSE report "Warning : OOBDETECT_THRESHOLD_1 is not in 110, 111." severity warning; end if; case AC_CAP_DIS_0 is when FALSE => AC_CAP_DIS_0_BINARY <= '0'; when TRUE => AC_CAP_DIS_0_BINARY <= '1'; when others => assert FALSE report "Error : AC_CAP_DIS_0 is neither TRUE nor FALSE." severity error; end case; case AC_CAP_DIS_1 is when FALSE => AC_CAP_DIS_1_BINARY <= '0'; when TRUE => AC_CAP_DIS_1_BINARY <= '1'; when others => assert FALSE report "Error : AC_CAP_DIS_1 is neither TRUE nor FALSE." severity error; end case; case RCV_TERM_GND_0 is when FALSE => RCV_TERM_GND_0_BINARY <= '0'; when TRUE => RCV_TERM_GND_0_BINARY <= '1'; when others => assert FALSE report "Error : RCV_TERM_GND_0 is neither TRUE nor FALSE." severity error; end case; case RCV_TERM_GND_1 is when FALSE => RCV_TERM_GND_1_BINARY <= '0'; when TRUE => RCV_TERM_GND_1_BINARY <= '1'; when others => assert FALSE report "Error : RCV_TERM_GND_1 is neither TRUE nor FALSE." severity error; end case; case TERMINATION_IMP_0 is when 50 => TERMINATION_IMP_0_BINARY <= '0'; when 75 => TERMINATION_IMP_0_BINARY <= '1'; when others => assert FALSE report "Error : TERMINATION_IMP_0 is not in 50, 75." severity error; end case; case TERMINATION_IMP_1 is when 50 => TERMINATION_IMP_1_BINARY <= '0'; when 75 => TERMINATION_IMP_1_BINARY <= '1'; when others => assert FALSE report "Error : TERMINATION_IMP_1 is not in 50, 75." severity error; end case; case TERMINATION_OVRD is when FALSE => TERMINATION_OVRD_BINARY <= '0'; when TRUE => TERMINATION_OVRD_BINARY <= '1'; when others => assert FALSE report "Error : TERMINATION_OVRD is neither TRUE nor FALSE." severity error; end case; case RCV_TERM_VTTRX_0 is when FALSE => RCV_TERM_VTTRX_0_BINARY <= '0'; when TRUE => RCV_TERM_VTTRX_0_BINARY <= '1'; when others => assert FALSE report "Error : RCV_TERM_VTTRX_0 is neither TRUE nor FALSE." severity error; end case; case RCV_TERM_VTTRX_1 is when FALSE => RCV_TERM_VTTRX_1_BINARY <= '0'; when TRUE => RCV_TERM_VTTRX_1_BINARY <= '1'; when others => assert FALSE report "Error : RCV_TERM_VTTRX_1 is neither TRUE nor FALSE." severity error; end case; case CLKINDC_B is when FALSE => CLKINDC_B_BINARY <= '0'; when TRUE => CLKINDC_B_BINARY <= '1'; when others => assert FALSE report "Error : CLKINDC_B is neither TRUE nor FALSE." severity error; end case; case PCOMMA_DETECT_0 is when FALSE => PCOMMA_DETECT_0_BINARY <= '0'; when TRUE => PCOMMA_DETECT_0_BINARY <= '1'; when others => assert FALSE report "Error : PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; end case; case MCOMMA_DETECT_0 is when FALSE => MCOMMA_DETECT_0_BINARY <= '0'; when TRUE => MCOMMA_DETECT_0_BINARY <= '1'; when others => assert FALSE report "Error : MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; end case; case COMMA_DOUBLE_0 is when FALSE => COMMA_DOUBLE_0_BINARY <= '0'; when TRUE => COMMA_DOUBLE_0_BINARY <= '1'; when others => assert FALSE report "Error : COMMA_DOUBLE_0 is neither TRUE nor FALSE." severity error; end case; case ALIGN_COMMA_WORD_0 is when 1 => ALIGN_COMMA_WORD_0_BINARY <= '0'; when 2 => ALIGN_COMMA_WORD_0_BINARY <= '1'; when others => assert FALSE report "Error : ALIGN_COMMA_WORD_0 is not in 1, 2." severity error; end case; case DEC_PCOMMA_DETECT_0 is when FALSE => DEC_PCOMMA_DETECT_0_BINARY <= '0'; when TRUE => DEC_PCOMMA_DETECT_0_BINARY <= '1'; when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; end case; case DEC_MCOMMA_DETECT_0 is when FALSE => DEC_MCOMMA_DETECT_0_BINARY <= '0'; when TRUE => DEC_MCOMMA_DETECT_0_BINARY <= '1'; when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_0 is neither TRUE nor FALSE." severity error; end case; case DEC_VALID_COMMA_ONLY_0 is when FALSE => DEC_VALID_COMMA_ONLY_0_BINARY <= '0'; when TRUE => DEC_VALID_COMMA_ONLY_0_BINARY <= '1'; when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_0 is neither TRUE nor FALSE." severity error; end case; case PCOMMA_DETECT_1 is when FALSE => PCOMMA_DETECT_1_BINARY <= '0'; when TRUE => PCOMMA_DETECT_1_BINARY <= '1'; when others => assert FALSE report "Error : PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; end case; case MCOMMA_DETECT_1 is when FALSE => MCOMMA_DETECT_1_BINARY <= '0'; when TRUE => MCOMMA_DETECT_1_BINARY <= '1'; when others => assert FALSE report "Error : MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; end case; case COMMA_DOUBLE_1 is when FALSE => COMMA_DOUBLE_1_BINARY <= '0'; when TRUE => COMMA_DOUBLE_1_BINARY <= '1'; when others => assert FALSE report "Error : COMMA_DOUBLE_1 is neither TRUE nor FALSE." severity error; end case; case ALIGN_COMMA_WORD_1 is when 1 => ALIGN_COMMA_WORD_1_BINARY <= '0'; when 2 => ALIGN_COMMA_WORD_1_BINARY <= '1'; when others => assert FALSE report "Error : ALIGN_COMMA_WORD_1 is not in 1, 2." severity error; end case; case DEC_PCOMMA_DETECT_1 is when FALSE => DEC_PCOMMA_DETECT_1_BINARY <= '0'; when TRUE => DEC_PCOMMA_DETECT_1_BINARY <= '1'; when others => assert FALSE report "Error : DEC_PCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; end case; case DEC_MCOMMA_DETECT_1 is when FALSE => DEC_MCOMMA_DETECT_1_BINARY <= '0'; when TRUE => DEC_MCOMMA_DETECT_1_BINARY <= '1'; when others => assert FALSE report "Error : DEC_MCOMMA_DETECT_1 is neither TRUE nor FALSE." severity error; end case; case DEC_VALID_COMMA_ONLY_1 is when FALSE => DEC_VALID_COMMA_ONLY_1_BINARY <= '0'; when TRUE => DEC_VALID_COMMA_ONLY_1_BINARY <= '1'; when others => assert FALSE report "Error : DEC_VALID_COMMA_ONLY_1 is neither TRUE nor FALSE." severity error; end case; case RX_LOSS_OF_SYNC_FSM_0 is when FALSE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '0'; when TRUE => RX_LOSS_OF_SYNC_FSM_0_BINARY <= '1'; when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_0 is neither TRUE nor FALSE." severity error; end case; case RX_LOS_INVALID_INCR_0 is when 1 => RX_LOS_INVALID_INCR_0_BINARY <= "000"; when 2 => RX_LOS_INVALID_INCR_0_BINARY <= "001"; when 4 => RX_LOS_INVALID_INCR_0_BINARY <= "010"; when 8 => RX_LOS_INVALID_INCR_0_BINARY <= "011"; when 16 => RX_LOS_INVALID_INCR_0_BINARY <= "100"; when 32 => RX_LOS_INVALID_INCR_0_BINARY <= "101"; when 64 => RX_LOS_INVALID_INCR_0_BINARY <= "110"; when 128 => RX_LOS_INVALID_INCR_0_BINARY <= "111"; when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_0 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; end case; case RX_LOS_THRESHOLD_0 is when 4 => RX_LOS_THRESHOLD_0_BINARY <= "000"; when 8 => RX_LOS_THRESHOLD_0_BINARY <= "001"; when 16 => RX_LOS_THRESHOLD_0_BINARY <= "010"; when 32 => RX_LOS_THRESHOLD_0_BINARY <= "011"; when 64 => RX_LOS_THRESHOLD_0_BINARY <= "100"; when 128 => RX_LOS_THRESHOLD_0_BINARY <= "101"; when 256 => RX_LOS_THRESHOLD_0_BINARY <= "110"; when 512 => RX_LOS_THRESHOLD_0_BINARY <= "111"; when others => assert FALSE report "Error : RX_LOS_THRESHOLD_0 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; end case; case RX_LOSS_OF_SYNC_FSM_1 is when FALSE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '0'; when TRUE => RX_LOSS_OF_SYNC_FSM_1_BINARY <= '1'; when others => assert FALSE report "Error : RX_LOSS_OF_SYNC_FSM_1 is neither TRUE nor FALSE." severity error; end case; case RX_LOS_INVALID_INCR_1 is when 1 => RX_LOS_INVALID_INCR_1_BINARY <= "000"; when 2 => RX_LOS_INVALID_INCR_1_BINARY <= "001"; when 4 => RX_LOS_INVALID_INCR_1_BINARY <= "010"; when 8 => RX_LOS_INVALID_INCR_1_BINARY <= "011"; when 16 => RX_LOS_INVALID_INCR_1_BINARY <= "100"; when 32 => RX_LOS_INVALID_INCR_1_BINARY <= "101"; when 64 => RX_LOS_INVALID_INCR_1_BINARY <= "110"; when 128 => RX_LOS_INVALID_INCR_1_BINARY <= "111"; when others => assert FALSE report "Error : RX_LOS_INVALID_INCR_1 is not in 1, 2, 4, 8, 16, 32, 64, 128." severity error; end case; case RX_LOS_THRESHOLD_1 is when 4 => RX_LOS_THRESHOLD_1_BINARY <= "000"; when 8 => RX_LOS_THRESHOLD_1_BINARY <= "001"; when 16 => RX_LOS_THRESHOLD_1_BINARY <= "010"; when 32 => RX_LOS_THRESHOLD_1_BINARY <= "011"; when 64 => RX_LOS_THRESHOLD_1_BINARY <= "100"; when 128 => RX_LOS_THRESHOLD_1_BINARY <= "101"; when 256 => RX_LOS_THRESHOLD_1_BINARY <= "110"; when 512 => RX_LOS_THRESHOLD_1_BINARY <= "111"; when others => assert FALSE report "Error : RX_LOS_THRESHOLD_1 is not in 4, 8, 16, 32, 64, 128, 256, 512." severity error; end case; case RX_BUFFER_USE_0 is when FALSE => RX_BUFFER_USE_0_BINARY <= '0'; when TRUE => RX_BUFFER_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : RX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; end case; case RX_DECODE_SEQ_MATCH_0 is when FALSE => RX_DECODE_SEQ_MATCH_0_BINARY <= '0'; when TRUE => RX_DECODE_SEQ_MATCH_0_BINARY <= '1'; when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_0 is neither TRUE nor FALSE." severity error; end case; case RX_BUFFER_USE_1 is when FALSE => RX_BUFFER_USE_1_BINARY <= '0'; when TRUE => RX_BUFFER_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : RX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; end case; case RX_DECODE_SEQ_MATCH_1 is when FALSE => RX_DECODE_SEQ_MATCH_1_BINARY <= '0'; when TRUE => RX_DECODE_SEQ_MATCH_1_BINARY <= '1'; when others => assert FALSE report "Error : RX_DECODE_SEQ_MATCH_1 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_MIN_LAT_0 is when 3 => CLK_COR_MIN_LAT_0_BINARY <= "000011"; when 4 => CLK_COR_MIN_LAT_0_BINARY <= "000100"; when 5 => CLK_COR_MIN_LAT_0_BINARY <= "000101"; when 6 => CLK_COR_MIN_LAT_0_BINARY <= "000110"; when 7 => CLK_COR_MIN_LAT_0_BINARY <= "000111"; when 8 => CLK_COR_MIN_LAT_0_BINARY <= "001000"; when 9 => CLK_COR_MIN_LAT_0_BINARY <= "001001"; when 10 => CLK_COR_MIN_LAT_0_BINARY <= "001010"; when 11 => CLK_COR_MIN_LAT_0_BINARY <= "001011"; when 12 => CLK_COR_MIN_LAT_0_BINARY <= "001100"; when 13 => CLK_COR_MIN_LAT_0_BINARY <= "001101"; when 14 => CLK_COR_MIN_LAT_0_BINARY <= "001110"; when 15 => CLK_COR_MIN_LAT_0_BINARY <= "001111"; when 16 => CLK_COR_MIN_LAT_0_BINARY <= "010000"; when 17 => CLK_COR_MIN_LAT_0_BINARY <= "010001"; when 18 => CLK_COR_MIN_LAT_0_BINARY <= "010010"; when 19 => CLK_COR_MIN_LAT_0_BINARY <= "010011"; when 20 => CLK_COR_MIN_LAT_0_BINARY <= "010100"; when 21 => CLK_COR_MIN_LAT_0_BINARY <= "010101"; when 22 => CLK_COR_MIN_LAT_0_BINARY <= "010110"; when 23 => CLK_COR_MIN_LAT_0_BINARY <= "010111"; when 24 => CLK_COR_MIN_LAT_0_BINARY <= "011000"; when 25 => CLK_COR_MIN_LAT_0_BINARY <= "011001"; when 26 => CLK_COR_MIN_LAT_0_BINARY <= "011010"; when 27 => CLK_COR_MIN_LAT_0_BINARY <= "011011"; when 28 => CLK_COR_MIN_LAT_0_BINARY <= "011100"; when 29 => CLK_COR_MIN_LAT_0_BINARY <= "011101"; when 30 => CLK_COR_MIN_LAT_0_BINARY <= "011110"; when 31 => CLK_COR_MIN_LAT_0_BINARY <= "011111"; when 32 => CLK_COR_MIN_LAT_0_BINARY <= "100000"; when 33 => CLK_COR_MIN_LAT_0_BINARY <= "100001"; when 34 => CLK_COR_MIN_LAT_0_BINARY <= "100010"; when 35 => CLK_COR_MIN_LAT_0_BINARY <= "100011"; when 36 => CLK_COR_MIN_LAT_0_BINARY <= "100100"; when 37 => CLK_COR_MIN_LAT_0_BINARY <= "100101"; when 38 => CLK_COR_MIN_LAT_0_BINARY <= "100110"; when 39 => CLK_COR_MIN_LAT_0_BINARY <= "100111"; when 40 => CLK_COR_MIN_LAT_0_BINARY <= "101000"; when 41 => CLK_COR_MIN_LAT_0_BINARY <= "101001"; when 42 => CLK_COR_MIN_LAT_0_BINARY <= "101010"; when 43 => CLK_COR_MIN_LAT_0_BINARY <= "101011"; when 44 => CLK_COR_MIN_LAT_0_BINARY <= "101100"; when 45 => CLK_COR_MIN_LAT_0_BINARY <= "101101"; when 46 => CLK_COR_MIN_LAT_0_BINARY <= "101110"; when 47 => CLK_COR_MIN_LAT_0_BINARY <= "101111"; when 48 => CLK_COR_MIN_LAT_0_BINARY <= "110000"; when others => assert FALSE report "Error : CLK_COR_MIN_LAT_0 is not in range 3...48." severity error; end case; case CLK_COR_MAX_LAT_0 is when 3 => CLK_COR_MAX_LAT_0_BINARY <= "000011"; when 4 => CLK_COR_MAX_LAT_0_BINARY <= "000100"; when 5 => CLK_COR_MAX_LAT_0_BINARY <= "000101"; when 6 => CLK_COR_MAX_LAT_0_BINARY <= "000110"; when 7 => CLK_COR_MAX_LAT_0_BINARY <= "000111"; when 8 => CLK_COR_MAX_LAT_0_BINARY <= "001000"; when 9 => CLK_COR_MAX_LAT_0_BINARY <= "001001"; when 10 => CLK_COR_MAX_LAT_0_BINARY <= "001010"; when 11 => CLK_COR_MAX_LAT_0_BINARY <= "001011"; when 12 => CLK_COR_MAX_LAT_0_BINARY <= "001100"; when 13 => CLK_COR_MAX_LAT_0_BINARY <= "001101"; when 14 => CLK_COR_MAX_LAT_0_BINARY <= "001110"; when 15 => CLK_COR_MAX_LAT_0_BINARY <= "001111"; when 16 => CLK_COR_MAX_LAT_0_BINARY <= "010000"; when 17 => CLK_COR_MAX_LAT_0_BINARY <= "010001"; when 18 => CLK_COR_MAX_LAT_0_BINARY <= "010010"; when 19 => CLK_COR_MAX_LAT_0_BINARY <= "010011"; when 20 => CLK_COR_MAX_LAT_0_BINARY <= "010100"; when 21 => CLK_COR_MAX_LAT_0_BINARY <= "010101"; when 22 => CLK_COR_MAX_LAT_0_BINARY <= "010110"; when 23 => CLK_COR_MAX_LAT_0_BINARY <= "010111"; when 24 => CLK_COR_MAX_LAT_0_BINARY <= "011000"; when 25 => CLK_COR_MAX_LAT_0_BINARY <= "011001"; when 26 => CLK_COR_MAX_LAT_0_BINARY <= "011010"; when 27 => CLK_COR_MAX_LAT_0_BINARY <= "011011"; when 28 => CLK_COR_MAX_LAT_0_BINARY <= "011100"; when 29 => CLK_COR_MAX_LAT_0_BINARY <= "011101"; when 30 => CLK_COR_MAX_LAT_0_BINARY <= "011110"; when 31 => CLK_COR_MAX_LAT_0_BINARY <= "011111"; when 32 => CLK_COR_MAX_LAT_0_BINARY <= "100000"; when 33 => CLK_COR_MAX_LAT_0_BINARY <= "100001"; when 34 => CLK_COR_MAX_LAT_0_BINARY <= "100010"; when 35 => CLK_COR_MAX_LAT_0_BINARY <= "100011"; when 36 => CLK_COR_MAX_LAT_0_BINARY <= "100100"; when 37 => CLK_COR_MAX_LAT_0_BINARY <= "100101"; when 38 => CLK_COR_MAX_LAT_0_BINARY <= "100110"; when 39 => CLK_COR_MAX_LAT_0_BINARY <= "100111"; when 40 => CLK_COR_MAX_LAT_0_BINARY <= "101000"; when 41 => CLK_COR_MAX_LAT_0_BINARY <= "101001"; when 42 => CLK_COR_MAX_LAT_0_BINARY <= "101010"; when 43 => CLK_COR_MAX_LAT_0_BINARY <= "101011"; when 44 => CLK_COR_MAX_LAT_0_BINARY <= "101100"; when 45 => CLK_COR_MAX_LAT_0_BINARY <= "101101"; when 46 => CLK_COR_MAX_LAT_0_BINARY <= "101110"; when 47 => CLK_COR_MAX_LAT_0_BINARY <= "101111"; when 48 => CLK_COR_MAX_LAT_0_BINARY <= "110000"; when others => assert FALSE report "Error : CLK_COR_MAX_LAT_0 is not in range 3...48." severity error; end case; case CLK_CORRECT_USE_0 is when FALSE => CLK_CORRECT_USE_0_BINARY <= '0'; when TRUE => CLK_CORRECT_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : CLK_CORRECT_USE_0 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_PRECEDENCE_0 is when FALSE => CLK_COR_PRECEDENCE_0_BINARY <= '0'; when TRUE => CLK_COR_PRECEDENCE_0_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_0 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_DET_LEN_0 is when 1 => CLK_COR_DET_LEN_0_BINARY <= "00"; when 2 => CLK_COR_DET_LEN_0_BINARY <= "01"; when 3 => CLK_COR_DET_LEN_0_BINARY <= "10"; when 4 => CLK_COR_DET_LEN_0_BINARY <= "11"; when others => assert FALSE report "Error : CLK_COR_DET_LEN_0 is not in 1, 2, 3, 4." severity error; end case; case CLK_COR_ADJ_LEN_0 is when 1 => CLK_COR_ADJ_LEN_0_BINARY <= "00"; when 2 => CLK_COR_ADJ_LEN_0_BINARY <= "01"; when 3 => CLK_COR_ADJ_LEN_0_BINARY <= "10"; when 4 => CLK_COR_ADJ_LEN_0_BINARY <= "11"; when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_0 is not in 1, 2, 3, 4." severity error; end case; case CLK_COR_KEEP_IDLE_0 is when FALSE => CLK_COR_KEEP_IDLE_0_BINARY <= '0'; when TRUE => CLK_COR_KEEP_IDLE_0_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_0 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_INSERT_IDLE_FLAG_0 is when FALSE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '0'; when TRUE => CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_0 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_REPEAT_WAIT_0 is when 0 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00000"; when 1 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00001"; when 2 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00010"; when 3 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00011"; when 4 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00100"; when 5 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00101"; when 6 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00110"; when 7 => CLK_COR_REPEAT_WAIT_0_BINARY <= "00111"; when 8 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01000"; when 9 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01001"; when 10 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01010"; when 11 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01011"; when 12 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01100"; when 13 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01101"; when 14 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01110"; when 15 => CLK_COR_REPEAT_WAIT_0_BINARY <= "01111"; when 16 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10000"; when 17 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10001"; when 18 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10010"; when 19 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10011"; when 20 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10100"; when 21 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10101"; when 22 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10110"; when 23 => CLK_COR_REPEAT_WAIT_0_BINARY <= "10111"; when 24 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11000"; when 25 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11001"; when 26 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11010"; when 27 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11011"; when 28 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11100"; when 29 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11101"; when 30 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11110"; when 31 => CLK_COR_REPEAT_WAIT_0_BINARY <= "11111"; when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_0 is not in range 0...31." severity error; end case; case CLK_COR_SEQ_2_USE_0 is when FALSE => CLK_COR_SEQ_2_USE_0_BINARY <= '0'; when TRUE => CLK_COR_SEQ_2_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_MIN_LAT_1 is when 3 => CLK_COR_MIN_LAT_1_BINARY <= "000011"; when 4 => CLK_COR_MIN_LAT_1_BINARY <= "000100"; when 5 => CLK_COR_MIN_LAT_1_BINARY <= "000101"; when 6 => CLK_COR_MIN_LAT_1_BINARY <= "000110"; when 7 => CLK_COR_MIN_LAT_1_BINARY <= "000111"; when 8 => CLK_COR_MIN_LAT_1_BINARY <= "001000"; when 9 => CLK_COR_MIN_LAT_1_BINARY <= "001001"; when 10 => CLK_COR_MIN_LAT_1_BINARY <= "001010"; when 11 => CLK_COR_MIN_LAT_1_BINARY <= "001011"; when 12 => CLK_COR_MIN_LAT_1_BINARY <= "001100"; when 13 => CLK_COR_MIN_LAT_1_BINARY <= "001101"; when 14 => CLK_COR_MIN_LAT_1_BINARY <= "001110"; when 15 => CLK_COR_MIN_LAT_1_BINARY <= "001111"; when 16 => CLK_COR_MIN_LAT_1_BINARY <= "010000"; when 17 => CLK_COR_MIN_LAT_1_BINARY <= "010001"; when 18 => CLK_COR_MIN_LAT_1_BINARY <= "010010"; when 19 => CLK_COR_MIN_LAT_1_BINARY <= "010011"; when 20 => CLK_COR_MIN_LAT_1_BINARY <= "010100"; when 21 => CLK_COR_MIN_LAT_1_BINARY <= "010101"; when 22 => CLK_COR_MIN_LAT_1_BINARY <= "010110"; when 23 => CLK_COR_MIN_LAT_1_BINARY <= "010111"; when 24 => CLK_COR_MIN_LAT_1_BINARY <= "011000"; when 25 => CLK_COR_MIN_LAT_1_BINARY <= "011001"; when 26 => CLK_COR_MIN_LAT_1_BINARY <= "011010"; when 27 => CLK_COR_MIN_LAT_1_BINARY <= "011011"; when 28 => CLK_COR_MIN_LAT_1_BINARY <= "011100"; when 29 => CLK_COR_MIN_LAT_1_BINARY <= "011101"; when 30 => CLK_COR_MIN_LAT_1_BINARY <= "011110"; when 31 => CLK_COR_MIN_LAT_1_BINARY <= "011111"; when 32 => CLK_COR_MIN_LAT_1_BINARY <= "100000"; when 33 => CLK_COR_MIN_LAT_1_BINARY <= "100001"; when 34 => CLK_COR_MIN_LAT_1_BINARY <= "100010"; when 35 => CLK_COR_MIN_LAT_1_BINARY <= "100011"; when 36 => CLK_COR_MIN_LAT_1_BINARY <= "100100"; when 37 => CLK_COR_MIN_LAT_1_BINARY <= "100101"; when 38 => CLK_COR_MIN_LAT_1_BINARY <= "100110"; when 39 => CLK_COR_MIN_LAT_1_BINARY <= "100111"; when 40 => CLK_COR_MIN_LAT_1_BINARY <= "101000"; when 41 => CLK_COR_MIN_LAT_1_BINARY <= "101001"; when 42 => CLK_COR_MIN_LAT_1_BINARY <= "101010"; when 43 => CLK_COR_MIN_LAT_1_BINARY <= "101011"; when 44 => CLK_COR_MIN_LAT_1_BINARY <= "101100"; when 45 => CLK_COR_MIN_LAT_1_BINARY <= "101101"; when 46 => CLK_COR_MIN_LAT_1_BINARY <= "101110"; when 47 => CLK_COR_MIN_LAT_1_BINARY <= "101111"; when 48 => CLK_COR_MIN_LAT_1_BINARY <= "110000"; when others => assert FALSE report "Error : CLK_COR_MIN_LAT_1 is not in range 3...48." severity error; end case; case CLK_COR_MAX_LAT_1 is when 3 => CLK_COR_MAX_LAT_1_BINARY <= "000011"; when 4 => CLK_COR_MAX_LAT_1_BINARY <= "000100"; when 5 => CLK_COR_MAX_LAT_1_BINARY <= "000101"; when 6 => CLK_COR_MAX_LAT_1_BINARY <= "000110"; when 7 => CLK_COR_MAX_LAT_1_BINARY <= "000111"; when 8 => CLK_COR_MAX_LAT_1_BINARY <= "001000"; when 9 => CLK_COR_MAX_LAT_1_BINARY <= "001001"; when 10 => CLK_COR_MAX_LAT_1_BINARY <= "001010"; when 11 => CLK_COR_MAX_LAT_1_BINARY <= "001011"; when 12 => CLK_COR_MAX_LAT_1_BINARY <= "001100"; when 13 => CLK_COR_MAX_LAT_1_BINARY <= "001101"; when 14 => CLK_COR_MAX_LAT_1_BINARY <= "001110"; when 15 => CLK_COR_MAX_LAT_1_BINARY <= "001111"; when 16 => CLK_COR_MAX_LAT_1_BINARY <= "010000"; when 17 => CLK_COR_MAX_LAT_1_BINARY <= "010001"; when 18 => CLK_COR_MAX_LAT_1_BINARY <= "010010"; when 19 => CLK_COR_MAX_LAT_1_BINARY <= "010011"; when 20 => CLK_COR_MAX_LAT_1_BINARY <= "010100"; when 21 => CLK_COR_MAX_LAT_1_BINARY <= "010101"; when 22 => CLK_COR_MAX_LAT_1_BINARY <= "010110"; when 23 => CLK_COR_MAX_LAT_1_BINARY <= "010111"; when 24 => CLK_COR_MAX_LAT_1_BINARY <= "011000"; when 25 => CLK_COR_MAX_LAT_1_BINARY <= "011001"; when 26 => CLK_COR_MAX_LAT_1_BINARY <= "011010"; when 27 => CLK_COR_MAX_LAT_1_BINARY <= "011011"; when 28 => CLK_COR_MAX_LAT_1_BINARY <= "011100"; when 29 => CLK_COR_MAX_LAT_1_BINARY <= "011101"; when 30 => CLK_COR_MAX_LAT_1_BINARY <= "011110"; when 31 => CLK_COR_MAX_LAT_1_BINARY <= "011111"; when 32 => CLK_COR_MAX_LAT_1_BINARY <= "100000"; when 33 => CLK_COR_MAX_LAT_1_BINARY <= "100001"; when 34 => CLK_COR_MAX_LAT_1_BINARY <= "100010"; when 35 => CLK_COR_MAX_LAT_1_BINARY <= "100011"; when 36 => CLK_COR_MAX_LAT_1_BINARY <= "100100"; when 37 => CLK_COR_MAX_LAT_1_BINARY <= "100101"; when 38 => CLK_COR_MAX_LAT_1_BINARY <= "100110"; when 39 => CLK_COR_MAX_LAT_1_BINARY <= "100111"; when 40 => CLK_COR_MAX_LAT_1_BINARY <= "101000"; when 41 => CLK_COR_MAX_LAT_1_BINARY <= "101001"; when 42 => CLK_COR_MAX_LAT_1_BINARY <= "101010"; when 43 => CLK_COR_MAX_LAT_1_BINARY <= "101011"; when 44 => CLK_COR_MAX_LAT_1_BINARY <= "101100"; when 45 => CLK_COR_MAX_LAT_1_BINARY <= "101101"; when 46 => CLK_COR_MAX_LAT_1_BINARY <= "101110"; when 47 => CLK_COR_MAX_LAT_1_BINARY <= "101111"; when 48 => CLK_COR_MAX_LAT_1_BINARY <= "110000"; when others => assert FALSE report "Error : CLK_COR_MAX_LAT_1 is not in range 3...48." severity error; end case; case CLK_CORRECT_USE_1 is when FALSE => CLK_CORRECT_USE_1_BINARY <= '0'; when TRUE => CLK_CORRECT_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : CLK_CORRECT_USE_1 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_PRECEDENCE_1 is when FALSE => CLK_COR_PRECEDENCE_1_BINARY <= '0'; when TRUE => CLK_COR_PRECEDENCE_1_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_PRECEDENCE_1 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_DET_LEN_1 is when 1 => CLK_COR_DET_LEN_1_BINARY <= "00"; when 2 => CLK_COR_DET_LEN_1_BINARY <= "01"; when 3 => CLK_COR_DET_LEN_1_BINARY <= "10"; when 4 => CLK_COR_DET_LEN_1_BINARY <= "11"; when others => assert FALSE report "Error : CLK_COR_DET_LEN_1 is not in 1, 2, 3, 4." severity error; end case; case CLK_COR_ADJ_LEN_1 is when 1 => CLK_COR_ADJ_LEN_1_BINARY <= "00"; when 2 => CLK_COR_ADJ_LEN_1_BINARY <= "01"; when 3 => CLK_COR_ADJ_LEN_1_BINARY <= "10"; when 4 => CLK_COR_ADJ_LEN_1_BINARY <= "11"; when others => assert FALSE report "Error : CLK_COR_ADJ_LEN_1 is not in 1, 2, 3, 4." severity error; end case; case CLK_COR_KEEP_IDLE_1 is when FALSE => CLK_COR_KEEP_IDLE_1_BINARY <= '0'; when TRUE => CLK_COR_KEEP_IDLE_1_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_KEEP_IDLE_1 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_INSERT_IDLE_FLAG_1 is when FALSE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '0'; when TRUE => CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_INSERT_IDLE_FLAG_1 is neither TRUE nor FALSE." severity error; end case; case CLK_COR_REPEAT_WAIT_1 is when 0 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00000"; when 1 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00001"; when 2 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00010"; when 3 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00011"; when 4 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00100"; when 5 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00101"; when 6 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00110"; when 7 => CLK_COR_REPEAT_WAIT_1_BINARY <= "00111"; when 8 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01000"; when 9 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01001"; when 10 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01010"; when 11 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01011"; when 12 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01100"; when 13 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01101"; when 14 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01110"; when 15 => CLK_COR_REPEAT_WAIT_1_BINARY <= "01111"; when 16 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10000"; when 17 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10001"; when 18 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10010"; when 19 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10011"; when 20 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10100"; when 21 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10101"; when 22 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10110"; when 23 => CLK_COR_REPEAT_WAIT_1_BINARY <= "10111"; when 24 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11000"; when 25 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11001"; when 26 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11010"; when 27 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11011"; when 28 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11100"; when 29 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11101"; when 30 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11110"; when 31 => CLK_COR_REPEAT_WAIT_1_BINARY <= "11111"; when others => assert FALSE report "Error : CLK_COR_REPEAT_WAIT_1 is not in range 0...31." severity error; end case; case CLK_COR_SEQ_2_USE_1 is when FALSE => CLK_COR_SEQ_2_USE_1_BINARY <= '0'; when TRUE => CLK_COR_SEQ_2_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : CLK_COR_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; end case; -- case CHAN_BOND_MODE_0 is if((CHAN_BOND_MODE_0 = "OFF") or (CHAN_BOND_MODE_0 = "off")) then CHAN_BOND_MODE_0_BINARY <= "00"; elsif((CHAN_BOND_MODE_0 = "MASTER") or (CHAN_BOND_MODE_0 = "master")) then CHAN_BOND_MODE_0_BINARY <= "01"; elsif((CHAN_BOND_MODE_0 = "SLAVE") or (CHAN_BOND_MODE_0 = "slave")) then CHAN_BOND_MODE_0_BINARY <= "10"; else assert FALSE report "Error : CHAN_BOND_MODE_0 = is not OFF, MASTER, SLAVE." severity error; end if; -- end case; case CHAN_BOND_LEVEL_0 is when 0 => CHAN_BOND_LEVEL_0_BINARY <= "000"; when 1 => CHAN_BOND_LEVEL_0_BINARY <= "001"; when 2 => CHAN_BOND_LEVEL_0_BINARY <= "010"; when 3 => CHAN_BOND_LEVEL_0_BINARY <= "011"; when 4 => CHAN_BOND_LEVEL_0_BINARY <= "100"; when 5 => CHAN_BOND_LEVEL_0_BINARY <= "101"; when 6 => CHAN_BOND_LEVEL_0_BINARY <= "110"; when 7 => CHAN_BOND_LEVEL_0_BINARY <= "111"; when others => assert FALSE report "Error : CHAN_BOND_LEVEL_0 is not in range 0...7." severity error; end case; case CHAN_BOND_SEQ_LEN_0 is when 1 => CHAN_BOND_SEQ_LEN_0_BINARY <= "00"; when 2 => CHAN_BOND_SEQ_LEN_0_BINARY <= "01"; when 3 => CHAN_BOND_SEQ_LEN_0_BINARY <= "10"; when 4 => CHAN_BOND_SEQ_LEN_0_BINARY <= "11"; when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_0 is not in 1, 2, 3, 4." severity error; end case; case CHAN_BOND_SEQ_2_USE_0 is when FALSE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '0'; when TRUE => CHAN_BOND_SEQ_2_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_0 is neither TRUE nor FALSE." severity error; end case; case CHAN_BOND_1_MAX_SKEW_0 is when 1 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0001"; when 2 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0010"; when 3 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0011"; when 4 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0100"; when 5 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0101"; when 6 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0110"; when 7 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "0111"; when 8 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1000"; when 9 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1001"; when 10 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1010"; when 11 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1011"; when 12 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1100"; when 13 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1101"; when 14 => CHAN_BOND_1_MAX_SKEW_0_BINARY <= "1110"; when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_0 is not in range 1...14." severity error; end case; case CHAN_BOND_2_MAX_SKEW_0 is when 1 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0001"; when 2 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0010"; when 3 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0011"; when 4 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0100"; when 5 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0101"; when 6 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0110"; when 7 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "0111"; when 8 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1000"; when 9 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1001"; when 10 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1010"; when 11 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1011"; when 12 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1100"; when 13 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1101"; when 14 => CHAN_BOND_2_MAX_SKEW_0_BINARY <= "1110"; when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_0 is not in range 1...14." severity error; end case; case CHAN_BOND_KEEP_ALIGN_0 is when FALSE => CHAN_BOND_KEEP_ALIGN_0_BINARY <= '0'; when TRUE => CHAN_BOND_KEEP_ALIGN_0_BINARY <= '1'; when others => assert FALSE report "Error : CHAN_BOND_KEEP_ALIGN_0 is neither TRUE nor FALSE." severity error; end case; case CB2_INH_CC_PERIOD_0 is when 0 => CB2_INH_CC_PERIOD_0_BINARY <= "0000"; when 1 => CB2_INH_CC_PERIOD_0_BINARY <= "0001"; when 2 => CB2_INH_CC_PERIOD_0_BINARY <= "0010"; when 3 => CB2_INH_CC_PERIOD_0_BINARY <= "0011"; when 4 => CB2_INH_CC_PERIOD_0_BINARY <= "0100"; when 5 => CB2_INH_CC_PERIOD_0_BINARY <= "0101"; when 6 => CB2_INH_CC_PERIOD_0_BINARY <= "0110"; when 7 => CB2_INH_CC_PERIOD_0_BINARY <= "0111"; when 8 => CB2_INH_CC_PERIOD_0_BINARY <= "1000"; when 9 => CB2_INH_CC_PERIOD_0_BINARY <= "1001"; when 10 => CB2_INH_CC_PERIOD_0_BINARY <= "1010"; when 11 => CB2_INH_CC_PERIOD_0_BINARY <= "1011"; when 12 => CB2_INH_CC_PERIOD_0_BINARY <= "1100"; when 13 => CB2_INH_CC_PERIOD_0_BINARY <= "1101"; when 14 => CB2_INH_CC_PERIOD_0_BINARY <= "1110"; when 15 => CB2_INH_CC_PERIOD_0_BINARY <= "1111"; when others => assert FALSE report "Error : CB2_INH_CC_PERIOD_0 is not in range 0...15." severity error; end case; -- case CHAN_BOND_MODE_1 is if((CHAN_BOND_MODE_1 = "OFF") or (CHAN_BOND_MODE_1 = "off")) then CHAN_BOND_MODE_1_BINARY <= "00"; elsif((CHAN_BOND_MODE_1 = "MASTER") or (CHAN_BOND_MODE_1 = "master")) then CHAN_BOND_MODE_1_BINARY <= "01"; elsif((CHAN_BOND_MODE_1 = "SLAVE") or (CHAN_BOND_MODE_1 = "slave")) then CHAN_BOND_MODE_1_BINARY <= "10"; else assert FALSE report "Error : CHAN_BOND_MODE_1 = is not OFF, MASTER, SLAVE." severity error; end if; -- end case; case CHAN_BOND_LEVEL_1 is when 0 => CHAN_BOND_LEVEL_1_BINARY <= "000"; when 1 => CHAN_BOND_LEVEL_1_BINARY <= "001"; when 2 => CHAN_BOND_LEVEL_1_BINARY <= "010"; when 3 => CHAN_BOND_LEVEL_1_BINARY <= "011"; when 4 => CHAN_BOND_LEVEL_1_BINARY <= "100"; when 5 => CHAN_BOND_LEVEL_1_BINARY <= "101"; when 6 => CHAN_BOND_LEVEL_1_BINARY <= "110"; when 7 => CHAN_BOND_LEVEL_1_BINARY <= "111"; when others => assert FALSE report "Error : CHAN_BOND_LEVEL_1 is not in range 0...7." severity error; end case; case CHAN_BOND_SEQ_LEN_1 is when 1 => CHAN_BOND_SEQ_LEN_1_BINARY <= "00"; when 2 => CHAN_BOND_SEQ_LEN_1_BINARY <= "01"; when 3 => CHAN_BOND_SEQ_LEN_1_BINARY <= "10"; when 4 => CHAN_BOND_SEQ_LEN_1_BINARY <= "11"; when others => assert FALSE report "Error : CHAN_BOND_SEQ_LEN_1 is not in 1, 2, 3, 4." severity error; end case; case CHAN_BOND_SEQ_2_USE_1 is when FALSE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '0'; when TRUE => CHAN_BOND_SEQ_2_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : CHAN_BOND_SEQ_2_USE_1 is neither TRUE nor FALSE." severity error; end case; case CHAN_BOND_1_MAX_SKEW_1 is when 1 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0001"; when 2 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0010"; when 3 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0011"; when 4 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0100"; when 5 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0101"; when 6 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0110"; when 7 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "0111"; when 8 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1000"; when 9 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1001"; when 10 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1010"; when 11 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1011"; when 12 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1100"; when 13 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1101"; when 14 => CHAN_BOND_1_MAX_SKEW_1_BINARY <= "1110"; when others => assert FALSE report "Error : CHAN_BOND_1_MAX_SKEW_1 is not in range 1...14." severity error; end case; case CHAN_BOND_2_MAX_SKEW_1 is when 1 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0001"; when 2 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0010"; when 3 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0011"; when 4 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0100"; when 5 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0101"; when 6 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0110"; when 7 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "0111"; when 8 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1000"; when 9 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1001"; when 10 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1010"; when 11 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1011"; when 12 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1100"; when 13 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1101"; when 14 => CHAN_BOND_2_MAX_SKEW_1_BINARY <= "1110"; when others => assert FALSE report "Error : CHAN_BOND_2_MAX_SKEW_1 is not in range 1...14." severity error; end case; case CHAN_BOND_KEEP_ALIGN_1 is when FALSE => CHAN_BOND_KEEP_ALIGN_1_BINARY <= '0'; when TRUE => CHAN_BOND_KEEP_ALIGN_1_BINARY <= '1'; when others => assert FALSE report "Error : CHAN_BOND_KEEP_ALIGN_1 is neither TRUE nor FALSE." severity error; end case; case CB2_INH_CC_PERIOD_1 is when 0 => CB2_INH_CC_PERIOD_1_BINARY <= "0000"; when 1 => CB2_INH_CC_PERIOD_1_BINARY <= "0001"; when 2 => CB2_INH_CC_PERIOD_1_BINARY <= "0010"; when 3 => CB2_INH_CC_PERIOD_1_BINARY <= "0011"; when 4 => CB2_INH_CC_PERIOD_1_BINARY <= "0100"; when 5 => CB2_INH_CC_PERIOD_1_BINARY <= "0101"; when 6 => CB2_INH_CC_PERIOD_1_BINARY <= "0110"; when 7 => CB2_INH_CC_PERIOD_1_BINARY <= "0111"; when 8 => CB2_INH_CC_PERIOD_1_BINARY <= "1000"; when 9 => CB2_INH_CC_PERIOD_1_BINARY <= "1001"; when 10 => CB2_INH_CC_PERIOD_1_BINARY <= "1010"; when 11 => CB2_INH_CC_PERIOD_1_BINARY <= "1011"; when 12 => CB2_INH_CC_PERIOD_1_BINARY <= "1100"; when 13 => CB2_INH_CC_PERIOD_1_BINARY <= "1101"; when 14 => CB2_INH_CC_PERIOD_1_BINARY <= "1110"; when 15 => CB2_INH_CC_PERIOD_1_BINARY <= "1111"; when others => assert FALSE report "Error : CB2_INH_CC_PERIOD_1 is not in range 0...15." severity error; end case; case PCI_EXPRESS_MODE_0 is when FALSE => PCI_EXPRESS_MODE_0_BINARY <= '0'; when TRUE => PCI_EXPRESS_MODE_0_BINARY <= '1'; when others => assert FALSE report "Error : PCI_EXPRESS_MODE_0 is neither TRUE nor FALSE." severity error; end case; case PCI_EXPRESS_MODE_1 is when FALSE => PCI_EXPRESS_MODE_1_BINARY <= '0'; when TRUE => PCI_EXPRESS_MODE_1_BINARY <= '1'; when others => assert FALSE report "Error : PCI_EXPRESS_MODE_1 is neither TRUE nor FALSE." severity error; end case; -- case RX_STATUS_FMT_0 is if((RX_STATUS_FMT_0 = "PCIE") or (RX_STATUS_FMT_0 = "pcie")) then RX_STATUS_FMT_0_BINARY <= '0'; elsif((RX_STATUS_FMT_0 = "SATA") or (RX_STATUS_FMT_0 = "sata")) then RX_STATUS_FMT_0_BINARY <= '1'; else assert FALSE report "Error : RX_STATUS_FMT_0 = is not PCIE, SATA." severity error; end if; -- end case; case TX_BUFFER_USE_0 is when FALSE => TX_BUFFER_USE_0_BINARY <= '0'; when TRUE => TX_BUFFER_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : TX_BUFFER_USE_0 is neither TRUE nor FALSE." severity error; end case; -- case TX_XCLK_SEL_0 is if((TX_XCLK_SEL_0 = "TXUSR") or (TX_XCLK_SEL_0 = "txusr")) then TX_XCLK_SEL_0_BINARY <= '1'; elsif((TX_XCLK_SEL_0 = "TXOUT") or (TX_XCLK_SEL_0 = "txout")) then TX_XCLK_SEL_0_BINARY <= '0'; else assert FALSE report "Error : TX_XCLK_SEL_0 = is not TXUSR, TXOUT." severity error; end if; -- end case; -- case RX_XCLK_SEL_0 is if((RX_XCLK_SEL_0 = "RXREC") or (RX_XCLK_SEL_0 = "rxrec")) then RX_XCLK_SEL_0_BINARY <= '0'; elsif((RX_XCLK_SEL_0 = "RXUSR") or (RX_XCLK_SEL_0 = "rxusr")) then RX_XCLK_SEL_0_BINARY <= '1'; else assert FALSE report "Error : RX_XCLK_SEL_0 = is not RXREC, RXUSR." severity error; end if; -- end case; -- case RX_STATUS_FMT_1 is if((RX_STATUS_FMT_1 = "PCIE") or (RX_STATUS_FMT_1 = "pcie")) then RX_STATUS_FMT_1_BINARY <= '0'; elsif((RX_STATUS_FMT_1 = "SATA") or (RX_STATUS_FMT_1 = "sata")) then RX_STATUS_FMT_1_BINARY <= '1'; else assert FALSE report "Error : RX_STATUS_FMT_1 = is not PCIE, SATA." severity error; end if; -- end case; case TX_BUFFER_USE_1 is when FALSE => TX_BUFFER_USE_1_BINARY <= '0'; when TRUE => TX_BUFFER_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : TX_BUFFER_USE_1 is neither TRUE nor FALSE." severity error; end case; -- case TX_XCLK_SEL_1 is if((TX_XCLK_SEL_1 = "TXUSR") or (TX_XCLK_SEL_1 = "txusr")) then TX_XCLK_SEL_1_BINARY <= '1'; elsif((TX_XCLK_SEL_1 = "TXOUT") or (TX_XCLK_SEL_1 = "txout")) then TX_XCLK_SEL_1_BINARY <= '0'; else assert FALSE report "Error : TX_XCLK_SEL_1 = is not TXUSR, TXOUT." severity error; end if; -- end case; -- case RX_XCLK_SEL_1 is if((RX_XCLK_SEL_1 = "RXREC") or (RX_XCLK_SEL_1 = "rxrec")) then RX_XCLK_SEL_1_BINARY <= '0'; elsif((RX_XCLK_SEL_1 = "RXUSR") or (RX_XCLK_SEL_1 = "rxusr")) then RX_XCLK_SEL_1_BINARY <= '1'; else assert FALSE report "Error : RX_XCLK_SEL_1 = is not RXREC, RXUSR." severity error; end if; -- end case; -- case RX_SLIDE_MODE_0 is if((RX_SLIDE_MODE_0 = "PCS") or (RX_SLIDE_MODE_0 = "pcs")) then RX_SLIDE_MODE_0_BINARY <= '0'; elsif((RX_SLIDE_MODE_0 = "PMA") or (RX_SLIDE_MODE_0 = "pma")) then RX_SLIDE_MODE_0_BINARY <= '1'; else assert FALSE report "Error : RX_SLIDE_MODE_0 = is not PCS, PMA." severity error; end if; -- end case; -- case RX_SLIDE_MODE_1 is if((RX_SLIDE_MODE_1 = "PCS") or (RX_SLIDE_MODE_1 = "pcs")) then RX_SLIDE_MODE_1_BINARY <= '0'; elsif((RX_SLIDE_MODE_1 = "PMA") or (RX_SLIDE_MODE_1 = "pma")) then RX_SLIDE_MODE_1_BINARY <= '1'; else assert FALSE report "Error : RX_SLIDE_MODE_1 = is not PCS, PMA." severity error; end if; -- end case; case SATA_MIN_BURST_0 is when 1 => SATA_MIN_BURST_0_BINARY <= "000001"; when 2 => SATA_MIN_BURST_0_BINARY <= "000010"; when 3 => SATA_MIN_BURST_0_BINARY <= "000011"; when 4 => SATA_MIN_BURST_0_BINARY <= "000100"; when 5 => SATA_MIN_BURST_0_BINARY <= "000101"; when 6 => SATA_MIN_BURST_0_BINARY <= "000110"; when 7 => SATA_MIN_BURST_0_BINARY <= "000111"; when 8 => SATA_MIN_BURST_0_BINARY <= "001000"; when 9 => SATA_MIN_BURST_0_BINARY <= "001001"; when 10 => SATA_MIN_BURST_0_BINARY <= "001010"; when 11 => SATA_MIN_BURST_0_BINARY <= "001011"; when 12 => SATA_MIN_BURST_0_BINARY <= "001100"; when 13 => SATA_MIN_BURST_0_BINARY <= "001101"; when 14 => SATA_MIN_BURST_0_BINARY <= "001110"; when 15 => SATA_MIN_BURST_0_BINARY <= "001111"; when 16 => SATA_MIN_BURST_0_BINARY <= "010000"; when 17 => SATA_MIN_BURST_0_BINARY <= "010001"; when 18 => SATA_MIN_BURST_0_BINARY <= "010010"; when 19 => SATA_MIN_BURST_0_BINARY <= "010011"; when 20 => SATA_MIN_BURST_0_BINARY <= "010100"; when 21 => SATA_MIN_BURST_0_BINARY <= "010101"; when 22 => SATA_MIN_BURST_0_BINARY <= "010110"; when 23 => SATA_MIN_BURST_0_BINARY <= "010111"; when 24 => SATA_MIN_BURST_0_BINARY <= "011000"; when 25 => SATA_MIN_BURST_0_BINARY <= "011001"; when 26 => SATA_MIN_BURST_0_BINARY <= "011010"; when 27 => SATA_MIN_BURST_0_BINARY <= "011011"; when 28 => SATA_MIN_BURST_0_BINARY <= "011100"; when 29 => SATA_MIN_BURST_0_BINARY <= "011101"; when 30 => SATA_MIN_BURST_0_BINARY <= "011110"; when 31 => SATA_MIN_BURST_0_BINARY <= "011111"; when 32 => SATA_MIN_BURST_0_BINARY <= "100000"; when 33 => SATA_MIN_BURST_0_BINARY <= "100001"; when 34 => SATA_MIN_BURST_0_BINARY <= "100010"; when 35 => SATA_MIN_BURST_0_BINARY <= "100011"; when 36 => SATA_MIN_BURST_0_BINARY <= "100100"; when 37 => SATA_MIN_BURST_0_BINARY <= "100101"; when 38 => SATA_MIN_BURST_0_BINARY <= "100110"; when 39 => SATA_MIN_BURST_0_BINARY <= "100111"; when 40 => SATA_MIN_BURST_0_BINARY <= "101000"; when 41 => SATA_MIN_BURST_0_BINARY <= "101001"; when 42 => SATA_MIN_BURST_0_BINARY <= "101010"; when 43 => SATA_MIN_BURST_0_BINARY <= "101011"; when 44 => SATA_MIN_BURST_0_BINARY <= "101100"; when 45 => SATA_MIN_BURST_0_BINARY <= "101101"; when 46 => SATA_MIN_BURST_0_BINARY <= "101110"; when 47 => SATA_MIN_BURST_0_BINARY <= "101111"; when 48 => SATA_MIN_BURST_0_BINARY <= "110000"; when 49 => SATA_MIN_BURST_0_BINARY <= "110001"; when 50 => SATA_MIN_BURST_0_BINARY <= "110010"; when 51 => SATA_MIN_BURST_0_BINARY <= "110011"; when 52 => SATA_MIN_BURST_0_BINARY <= "110100"; when 53 => SATA_MIN_BURST_0_BINARY <= "110101"; when 54 => SATA_MIN_BURST_0_BINARY <= "110110"; when 55 => SATA_MIN_BURST_0_BINARY <= "110111"; when 56 => SATA_MIN_BURST_0_BINARY <= "111000"; when 57 => SATA_MIN_BURST_0_BINARY <= "111001"; when 58 => SATA_MIN_BURST_0_BINARY <= "111010"; when 59 => SATA_MIN_BURST_0_BINARY <= "111011"; when 60 => SATA_MIN_BURST_0_BINARY <= "111100"; when 61 => SATA_MIN_BURST_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_BURST_0 is not in range 1...61." severity error; end case; case SATA_MAX_BURST_0 is when 1 => SATA_MAX_BURST_0_BINARY <= "000001"; when 2 => SATA_MAX_BURST_0_BINARY <= "000010"; when 3 => SATA_MAX_BURST_0_BINARY <= "000011"; when 4 => SATA_MAX_BURST_0_BINARY <= "000100"; when 5 => SATA_MAX_BURST_0_BINARY <= "000101"; when 6 => SATA_MAX_BURST_0_BINARY <= "000110"; when 7 => SATA_MAX_BURST_0_BINARY <= "000111"; when 8 => SATA_MAX_BURST_0_BINARY <= "001000"; when 9 => SATA_MAX_BURST_0_BINARY <= "001001"; when 10 => SATA_MAX_BURST_0_BINARY <= "001010"; when 11 => SATA_MAX_BURST_0_BINARY <= "001011"; when 12 => SATA_MAX_BURST_0_BINARY <= "001100"; when 13 => SATA_MAX_BURST_0_BINARY <= "001101"; when 14 => SATA_MAX_BURST_0_BINARY <= "001110"; when 15 => SATA_MAX_BURST_0_BINARY <= "001111"; when 16 => SATA_MAX_BURST_0_BINARY <= "010000"; when 17 => SATA_MAX_BURST_0_BINARY <= "010001"; when 18 => SATA_MAX_BURST_0_BINARY <= "010010"; when 19 => SATA_MAX_BURST_0_BINARY <= "010011"; when 20 => SATA_MAX_BURST_0_BINARY <= "010100"; when 21 => SATA_MAX_BURST_0_BINARY <= "010101"; when 22 => SATA_MAX_BURST_0_BINARY <= "010110"; when 23 => SATA_MAX_BURST_0_BINARY <= "010111"; when 24 => SATA_MAX_BURST_0_BINARY <= "011000"; when 25 => SATA_MAX_BURST_0_BINARY <= "011001"; when 26 => SATA_MAX_BURST_0_BINARY <= "011010"; when 27 => SATA_MAX_BURST_0_BINARY <= "011011"; when 28 => SATA_MAX_BURST_0_BINARY <= "011100"; when 29 => SATA_MAX_BURST_0_BINARY <= "011101"; when 30 => SATA_MAX_BURST_0_BINARY <= "011110"; when 31 => SATA_MAX_BURST_0_BINARY <= "011111"; when 32 => SATA_MAX_BURST_0_BINARY <= "100000"; when 33 => SATA_MAX_BURST_0_BINARY <= "100001"; when 34 => SATA_MAX_BURST_0_BINARY <= "100010"; when 35 => SATA_MAX_BURST_0_BINARY <= "100011"; when 36 => SATA_MAX_BURST_0_BINARY <= "100100"; when 37 => SATA_MAX_BURST_0_BINARY <= "100101"; when 38 => SATA_MAX_BURST_0_BINARY <= "100110"; when 39 => SATA_MAX_BURST_0_BINARY <= "100111"; when 40 => SATA_MAX_BURST_0_BINARY <= "101000"; when 41 => SATA_MAX_BURST_0_BINARY <= "101001"; when 42 => SATA_MAX_BURST_0_BINARY <= "101010"; when 43 => SATA_MAX_BURST_0_BINARY <= "101011"; when 44 => SATA_MAX_BURST_0_BINARY <= "101100"; when 45 => SATA_MAX_BURST_0_BINARY <= "101101"; when 46 => SATA_MAX_BURST_0_BINARY <= "101110"; when 47 => SATA_MAX_BURST_0_BINARY <= "101111"; when 48 => SATA_MAX_BURST_0_BINARY <= "110000"; when 49 => SATA_MAX_BURST_0_BINARY <= "110001"; when 50 => SATA_MAX_BURST_0_BINARY <= "110010"; when 51 => SATA_MAX_BURST_0_BINARY <= "110011"; when 52 => SATA_MAX_BURST_0_BINARY <= "110100"; when 53 => SATA_MAX_BURST_0_BINARY <= "110101"; when 54 => SATA_MAX_BURST_0_BINARY <= "110110"; when 55 => SATA_MAX_BURST_0_BINARY <= "110111"; when 56 => SATA_MAX_BURST_0_BINARY <= "111000"; when 57 => SATA_MAX_BURST_0_BINARY <= "111001"; when 58 => SATA_MAX_BURST_0_BINARY <= "111010"; when 59 => SATA_MAX_BURST_0_BINARY <= "111011"; when 60 => SATA_MAX_BURST_0_BINARY <= "111100"; when 61 => SATA_MAX_BURST_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_BURST_0 is not in range 1...61." severity error; end case; case SATA_MIN_INIT_0 is when 1 => SATA_MIN_INIT_0_BINARY <= "000001"; when 2 => SATA_MIN_INIT_0_BINARY <= "000010"; when 3 => SATA_MIN_INIT_0_BINARY <= "000011"; when 4 => SATA_MIN_INIT_0_BINARY <= "000100"; when 5 => SATA_MIN_INIT_0_BINARY <= "000101"; when 6 => SATA_MIN_INIT_0_BINARY <= "000110"; when 7 => SATA_MIN_INIT_0_BINARY <= "000111"; when 8 => SATA_MIN_INIT_0_BINARY <= "001000"; when 9 => SATA_MIN_INIT_0_BINARY <= "001001"; when 10 => SATA_MIN_INIT_0_BINARY <= "001010"; when 11 => SATA_MIN_INIT_0_BINARY <= "001011"; when 12 => SATA_MIN_INIT_0_BINARY <= "001100"; when 13 => SATA_MIN_INIT_0_BINARY <= "001101"; when 14 => SATA_MIN_INIT_0_BINARY <= "001110"; when 15 => SATA_MIN_INIT_0_BINARY <= "001111"; when 16 => SATA_MIN_INIT_0_BINARY <= "010000"; when 17 => SATA_MIN_INIT_0_BINARY <= "010001"; when 18 => SATA_MIN_INIT_0_BINARY <= "010010"; when 19 => SATA_MIN_INIT_0_BINARY <= "010011"; when 20 => SATA_MIN_INIT_0_BINARY <= "010100"; when 21 => SATA_MIN_INIT_0_BINARY <= "010101"; when 22 => SATA_MIN_INIT_0_BINARY <= "010110"; when 23 => SATA_MIN_INIT_0_BINARY <= "010111"; when 24 => SATA_MIN_INIT_0_BINARY <= "011000"; when 25 => SATA_MIN_INIT_0_BINARY <= "011001"; when 26 => SATA_MIN_INIT_0_BINARY <= "011010"; when 27 => SATA_MIN_INIT_0_BINARY <= "011011"; when 28 => SATA_MIN_INIT_0_BINARY <= "011100"; when 29 => SATA_MIN_INIT_0_BINARY <= "011101"; when 30 => SATA_MIN_INIT_0_BINARY <= "011110"; when 31 => SATA_MIN_INIT_0_BINARY <= "011111"; when 32 => SATA_MIN_INIT_0_BINARY <= "100000"; when 33 => SATA_MIN_INIT_0_BINARY <= "100001"; when 34 => SATA_MIN_INIT_0_BINARY <= "100010"; when 35 => SATA_MIN_INIT_0_BINARY <= "100011"; when 36 => SATA_MIN_INIT_0_BINARY <= "100100"; when 37 => SATA_MIN_INIT_0_BINARY <= "100101"; when 38 => SATA_MIN_INIT_0_BINARY <= "100110"; when 39 => SATA_MIN_INIT_0_BINARY <= "100111"; when 40 => SATA_MIN_INIT_0_BINARY <= "101000"; when 41 => SATA_MIN_INIT_0_BINARY <= "101001"; when 42 => SATA_MIN_INIT_0_BINARY <= "101010"; when 43 => SATA_MIN_INIT_0_BINARY <= "101011"; when 44 => SATA_MIN_INIT_0_BINARY <= "101100"; when 45 => SATA_MIN_INIT_0_BINARY <= "101101"; when 46 => SATA_MIN_INIT_0_BINARY <= "101110"; when 47 => SATA_MIN_INIT_0_BINARY <= "101111"; when 48 => SATA_MIN_INIT_0_BINARY <= "110000"; when 49 => SATA_MIN_INIT_0_BINARY <= "110001"; when 50 => SATA_MIN_INIT_0_BINARY <= "110010"; when 51 => SATA_MIN_INIT_0_BINARY <= "110011"; when 52 => SATA_MIN_INIT_0_BINARY <= "110100"; when 53 => SATA_MIN_INIT_0_BINARY <= "110101"; when 54 => SATA_MIN_INIT_0_BINARY <= "110110"; when 55 => SATA_MIN_INIT_0_BINARY <= "110111"; when 56 => SATA_MIN_INIT_0_BINARY <= "111000"; when 57 => SATA_MIN_INIT_0_BINARY <= "111001"; when 58 => SATA_MIN_INIT_0_BINARY <= "111010"; when 59 => SATA_MIN_INIT_0_BINARY <= "111011"; when 60 => SATA_MIN_INIT_0_BINARY <= "111100"; when 61 => SATA_MIN_INIT_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_INIT_0 is not in range 1...61." severity error; end case; case SATA_MAX_INIT_0 is when 1 => SATA_MAX_INIT_0_BINARY <= "000001"; when 2 => SATA_MAX_INIT_0_BINARY <= "000010"; when 3 => SATA_MAX_INIT_0_BINARY <= "000011"; when 4 => SATA_MAX_INIT_0_BINARY <= "000100"; when 5 => SATA_MAX_INIT_0_BINARY <= "000101"; when 6 => SATA_MAX_INIT_0_BINARY <= "000110"; when 7 => SATA_MAX_INIT_0_BINARY <= "000111"; when 8 => SATA_MAX_INIT_0_BINARY <= "001000"; when 9 => SATA_MAX_INIT_0_BINARY <= "001001"; when 10 => SATA_MAX_INIT_0_BINARY <= "001010"; when 11 => SATA_MAX_INIT_0_BINARY <= "001011"; when 12 => SATA_MAX_INIT_0_BINARY <= "001100"; when 13 => SATA_MAX_INIT_0_BINARY <= "001101"; when 14 => SATA_MAX_INIT_0_BINARY <= "001110"; when 15 => SATA_MAX_INIT_0_BINARY <= "001111"; when 16 => SATA_MAX_INIT_0_BINARY <= "010000"; when 17 => SATA_MAX_INIT_0_BINARY <= "010001"; when 18 => SATA_MAX_INIT_0_BINARY <= "010010"; when 19 => SATA_MAX_INIT_0_BINARY <= "010011"; when 20 => SATA_MAX_INIT_0_BINARY <= "010100"; when 21 => SATA_MAX_INIT_0_BINARY <= "010101"; when 22 => SATA_MAX_INIT_0_BINARY <= "010110"; when 23 => SATA_MAX_INIT_0_BINARY <= "010111"; when 24 => SATA_MAX_INIT_0_BINARY <= "011000"; when 25 => SATA_MAX_INIT_0_BINARY <= "011001"; when 26 => SATA_MAX_INIT_0_BINARY <= "011010"; when 27 => SATA_MAX_INIT_0_BINARY <= "011011"; when 28 => SATA_MAX_INIT_0_BINARY <= "011100"; when 29 => SATA_MAX_INIT_0_BINARY <= "011101"; when 30 => SATA_MAX_INIT_0_BINARY <= "011110"; when 31 => SATA_MAX_INIT_0_BINARY <= "011111"; when 32 => SATA_MAX_INIT_0_BINARY <= "100000"; when 33 => SATA_MAX_INIT_0_BINARY <= "100001"; when 34 => SATA_MAX_INIT_0_BINARY <= "100010"; when 35 => SATA_MAX_INIT_0_BINARY <= "100011"; when 36 => SATA_MAX_INIT_0_BINARY <= "100100"; when 37 => SATA_MAX_INIT_0_BINARY <= "100101"; when 38 => SATA_MAX_INIT_0_BINARY <= "100110"; when 39 => SATA_MAX_INIT_0_BINARY <= "100111"; when 40 => SATA_MAX_INIT_0_BINARY <= "101000"; when 41 => SATA_MAX_INIT_0_BINARY <= "101001"; when 42 => SATA_MAX_INIT_0_BINARY <= "101010"; when 43 => SATA_MAX_INIT_0_BINARY <= "101011"; when 44 => SATA_MAX_INIT_0_BINARY <= "101100"; when 45 => SATA_MAX_INIT_0_BINARY <= "101101"; when 46 => SATA_MAX_INIT_0_BINARY <= "101110"; when 47 => SATA_MAX_INIT_0_BINARY <= "101111"; when 48 => SATA_MAX_INIT_0_BINARY <= "110000"; when 49 => SATA_MAX_INIT_0_BINARY <= "110001"; when 50 => SATA_MAX_INIT_0_BINARY <= "110010"; when 51 => SATA_MAX_INIT_0_BINARY <= "110011"; when 52 => SATA_MAX_INIT_0_BINARY <= "110100"; when 53 => SATA_MAX_INIT_0_BINARY <= "110101"; when 54 => SATA_MAX_INIT_0_BINARY <= "110110"; when 55 => SATA_MAX_INIT_0_BINARY <= "110111"; when 56 => SATA_MAX_INIT_0_BINARY <= "111000"; when 57 => SATA_MAX_INIT_0_BINARY <= "111001"; when 58 => SATA_MAX_INIT_0_BINARY <= "111010"; when 59 => SATA_MAX_INIT_0_BINARY <= "111011"; when 60 => SATA_MAX_INIT_0_BINARY <= "111100"; when 61 => SATA_MAX_INIT_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_INIT_0 is not in range 1...61." severity error; end case; case SATA_MIN_WAKE_0 is when 1 => SATA_MIN_WAKE_0_BINARY <= "000001"; when 2 => SATA_MIN_WAKE_0_BINARY <= "000010"; when 3 => SATA_MIN_WAKE_0_BINARY <= "000011"; when 4 => SATA_MIN_WAKE_0_BINARY <= "000100"; when 5 => SATA_MIN_WAKE_0_BINARY <= "000101"; when 6 => SATA_MIN_WAKE_0_BINARY <= "000110"; when 7 => SATA_MIN_WAKE_0_BINARY <= "000111"; when 8 => SATA_MIN_WAKE_0_BINARY <= "001000"; when 9 => SATA_MIN_WAKE_0_BINARY <= "001001"; when 10 => SATA_MIN_WAKE_0_BINARY <= "001010"; when 11 => SATA_MIN_WAKE_0_BINARY <= "001011"; when 12 => SATA_MIN_WAKE_0_BINARY <= "001100"; when 13 => SATA_MIN_WAKE_0_BINARY <= "001101"; when 14 => SATA_MIN_WAKE_0_BINARY <= "001110"; when 15 => SATA_MIN_WAKE_0_BINARY <= "001111"; when 16 => SATA_MIN_WAKE_0_BINARY <= "010000"; when 17 => SATA_MIN_WAKE_0_BINARY <= "010001"; when 18 => SATA_MIN_WAKE_0_BINARY <= "010010"; when 19 => SATA_MIN_WAKE_0_BINARY <= "010011"; when 20 => SATA_MIN_WAKE_0_BINARY <= "010100"; when 21 => SATA_MIN_WAKE_0_BINARY <= "010101"; when 22 => SATA_MIN_WAKE_0_BINARY <= "010110"; when 23 => SATA_MIN_WAKE_0_BINARY <= "010111"; when 24 => SATA_MIN_WAKE_0_BINARY <= "011000"; when 25 => SATA_MIN_WAKE_0_BINARY <= "011001"; when 26 => SATA_MIN_WAKE_0_BINARY <= "011010"; when 27 => SATA_MIN_WAKE_0_BINARY <= "011011"; when 28 => SATA_MIN_WAKE_0_BINARY <= "011100"; when 29 => SATA_MIN_WAKE_0_BINARY <= "011101"; when 30 => SATA_MIN_WAKE_0_BINARY <= "011110"; when 31 => SATA_MIN_WAKE_0_BINARY <= "011111"; when 32 => SATA_MIN_WAKE_0_BINARY <= "100000"; when 33 => SATA_MIN_WAKE_0_BINARY <= "100001"; when 34 => SATA_MIN_WAKE_0_BINARY <= "100010"; when 35 => SATA_MIN_WAKE_0_BINARY <= "100011"; when 36 => SATA_MIN_WAKE_0_BINARY <= "100100"; when 37 => SATA_MIN_WAKE_0_BINARY <= "100101"; when 38 => SATA_MIN_WAKE_0_BINARY <= "100110"; when 39 => SATA_MIN_WAKE_0_BINARY <= "100111"; when 40 => SATA_MIN_WAKE_0_BINARY <= "101000"; when 41 => SATA_MIN_WAKE_0_BINARY <= "101001"; when 42 => SATA_MIN_WAKE_0_BINARY <= "101010"; when 43 => SATA_MIN_WAKE_0_BINARY <= "101011"; when 44 => SATA_MIN_WAKE_0_BINARY <= "101100"; when 45 => SATA_MIN_WAKE_0_BINARY <= "101101"; when 46 => SATA_MIN_WAKE_0_BINARY <= "101110"; when 47 => SATA_MIN_WAKE_0_BINARY <= "101111"; when 48 => SATA_MIN_WAKE_0_BINARY <= "110000"; when 49 => SATA_MIN_WAKE_0_BINARY <= "110001"; when 50 => SATA_MIN_WAKE_0_BINARY <= "110010"; when 51 => SATA_MIN_WAKE_0_BINARY <= "110011"; when 52 => SATA_MIN_WAKE_0_BINARY <= "110100"; when 53 => SATA_MIN_WAKE_0_BINARY <= "110101"; when 54 => SATA_MIN_WAKE_0_BINARY <= "110110"; when 55 => SATA_MIN_WAKE_0_BINARY <= "110111"; when 56 => SATA_MIN_WAKE_0_BINARY <= "111000"; when 57 => SATA_MIN_WAKE_0_BINARY <= "111001"; when 58 => SATA_MIN_WAKE_0_BINARY <= "111010"; when 59 => SATA_MIN_WAKE_0_BINARY <= "111011"; when 60 => SATA_MIN_WAKE_0_BINARY <= "111100"; when 61 => SATA_MIN_WAKE_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_WAKE_0 is not in range 1...61." severity error; end case; case SATA_MAX_WAKE_0 is when 1 => SATA_MAX_WAKE_0_BINARY <= "000001"; when 2 => SATA_MAX_WAKE_0_BINARY <= "000010"; when 3 => SATA_MAX_WAKE_0_BINARY <= "000011"; when 4 => SATA_MAX_WAKE_0_BINARY <= "000100"; when 5 => SATA_MAX_WAKE_0_BINARY <= "000101"; when 6 => SATA_MAX_WAKE_0_BINARY <= "000110"; when 7 => SATA_MAX_WAKE_0_BINARY <= "000111"; when 8 => SATA_MAX_WAKE_0_BINARY <= "001000"; when 9 => SATA_MAX_WAKE_0_BINARY <= "001001"; when 10 => SATA_MAX_WAKE_0_BINARY <= "001010"; when 11 => SATA_MAX_WAKE_0_BINARY <= "001011"; when 12 => SATA_MAX_WAKE_0_BINARY <= "001100"; when 13 => SATA_MAX_WAKE_0_BINARY <= "001101"; when 14 => SATA_MAX_WAKE_0_BINARY <= "001110"; when 15 => SATA_MAX_WAKE_0_BINARY <= "001111"; when 16 => SATA_MAX_WAKE_0_BINARY <= "010000"; when 17 => SATA_MAX_WAKE_0_BINARY <= "010001"; when 18 => SATA_MAX_WAKE_0_BINARY <= "010010"; when 19 => SATA_MAX_WAKE_0_BINARY <= "010011"; when 20 => SATA_MAX_WAKE_0_BINARY <= "010100"; when 21 => SATA_MAX_WAKE_0_BINARY <= "010101"; when 22 => SATA_MAX_WAKE_0_BINARY <= "010110"; when 23 => SATA_MAX_WAKE_0_BINARY <= "010111"; when 24 => SATA_MAX_WAKE_0_BINARY <= "011000"; when 25 => SATA_MAX_WAKE_0_BINARY <= "011001"; when 26 => SATA_MAX_WAKE_0_BINARY <= "011010"; when 27 => SATA_MAX_WAKE_0_BINARY <= "011011"; when 28 => SATA_MAX_WAKE_0_BINARY <= "011100"; when 29 => SATA_MAX_WAKE_0_BINARY <= "011101"; when 30 => SATA_MAX_WAKE_0_BINARY <= "011110"; when 31 => SATA_MAX_WAKE_0_BINARY <= "011111"; when 32 => SATA_MAX_WAKE_0_BINARY <= "100000"; when 33 => SATA_MAX_WAKE_0_BINARY <= "100001"; when 34 => SATA_MAX_WAKE_0_BINARY <= "100010"; when 35 => SATA_MAX_WAKE_0_BINARY <= "100011"; when 36 => SATA_MAX_WAKE_0_BINARY <= "100100"; when 37 => SATA_MAX_WAKE_0_BINARY <= "100101"; when 38 => SATA_MAX_WAKE_0_BINARY <= "100110"; when 39 => SATA_MAX_WAKE_0_BINARY <= "100111"; when 40 => SATA_MAX_WAKE_0_BINARY <= "101000"; when 41 => SATA_MAX_WAKE_0_BINARY <= "101001"; when 42 => SATA_MAX_WAKE_0_BINARY <= "101010"; when 43 => SATA_MAX_WAKE_0_BINARY <= "101011"; when 44 => SATA_MAX_WAKE_0_BINARY <= "101100"; when 45 => SATA_MAX_WAKE_0_BINARY <= "101101"; when 46 => SATA_MAX_WAKE_0_BINARY <= "101110"; when 47 => SATA_MAX_WAKE_0_BINARY <= "101111"; when 48 => SATA_MAX_WAKE_0_BINARY <= "110000"; when 49 => SATA_MAX_WAKE_0_BINARY <= "110001"; when 50 => SATA_MAX_WAKE_0_BINARY <= "110010"; when 51 => SATA_MAX_WAKE_0_BINARY <= "110011"; when 52 => SATA_MAX_WAKE_0_BINARY <= "110100"; when 53 => SATA_MAX_WAKE_0_BINARY <= "110101"; when 54 => SATA_MAX_WAKE_0_BINARY <= "110110"; when 55 => SATA_MAX_WAKE_0_BINARY <= "110111"; when 56 => SATA_MAX_WAKE_0_BINARY <= "111000"; when 57 => SATA_MAX_WAKE_0_BINARY <= "111001"; when 58 => SATA_MAX_WAKE_0_BINARY <= "111010"; when 59 => SATA_MAX_WAKE_0_BINARY <= "111011"; when 60 => SATA_MAX_WAKE_0_BINARY <= "111100"; when 61 => SATA_MAX_WAKE_0_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_WAKE_0 is not in range 1...61." severity error; end case; case SATA_MIN_BURST_1 is when 1 => SATA_MIN_BURST_1_BINARY <= "000001"; when 2 => SATA_MIN_BURST_1_BINARY <= "000010"; when 3 => SATA_MIN_BURST_1_BINARY <= "000011"; when 4 => SATA_MIN_BURST_1_BINARY <= "000100"; when 5 => SATA_MIN_BURST_1_BINARY <= "000101"; when 6 => SATA_MIN_BURST_1_BINARY <= "000110"; when 7 => SATA_MIN_BURST_1_BINARY <= "000111"; when 8 => SATA_MIN_BURST_1_BINARY <= "001000"; when 9 => SATA_MIN_BURST_1_BINARY <= "001001"; when 10 => SATA_MIN_BURST_1_BINARY <= "001010"; when 11 => SATA_MIN_BURST_1_BINARY <= "001011"; when 12 => SATA_MIN_BURST_1_BINARY <= "001100"; when 13 => SATA_MIN_BURST_1_BINARY <= "001101"; when 14 => SATA_MIN_BURST_1_BINARY <= "001110"; when 15 => SATA_MIN_BURST_1_BINARY <= "001111"; when 16 => SATA_MIN_BURST_1_BINARY <= "010000"; when 17 => SATA_MIN_BURST_1_BINARY <= "010001"; when 18 => SATA_MIN_BURST_1_BINARY <= "010010"; when 19 => SATA_MIN_BURST_1_BINARY <= "010011"; when 20 => SATA_MIN_BURST_1_BINARY <= "010100"; when 21 => SATA_MIN_BURST_1_BINARY <= "010101"; when 22 => SATA_MIN_BURST_1_BINARY <= "010110"; when 23 => SATA_MIN_BURST_1_BINARY <= "010111"; when 24 => SATA_MIN_BURST_1_BINARY <= "011000"; when 25 => SATA_MIN_BURST_1_BINARY <= "011001"; when 26 => SATA_MIN_BURST_1_BINARY <= "011010"; when 27 => SATA_MIN_BURST_1_BINARY <= "011011"; when 28 => SATA_MIN_BURST_1_BINARY <= "011100"; when 29 => SATA_MIN_BURST_1_BINARY <= "011101"; when 30 => SATA_MIN_BURST_1_BINARY <= "011110"; when 31 => SATA_MIN_BURST_1_BINARY <= "011111"; when 32 => SATA_MIN_BURST_1_BINARY <= "100000"; when 33 => SATA_MIN_BURST_1_BINARY <= "100001"; when 34 => SATA_MIN_BURST_1_BINARY <= "100010"; when 35 => SATA_MIN_BURST_1_BINARY <= "100011"; when 36 => SATA_MIN_BURST_1_BINARY <= "100100"; when 37 => SATA_MIN_BURST_1_BINARY <= "100101"; when 38 => SATA_MIN_BURST_1_BINARY <= "100110"; when 39 => SATA_MIN_BURST_1_BINARY <= "100111"; when 40 => SATA_MIN_BURST_1_BINARY <= "101000"; when 41 => SATA_MIN_BURST_1_BINARY <= "101001"; when 42 => SATA_MIN_BURST_1_BINARY <= "101010"; when 43 => SATA_MIN_BURST_1_BINARY <= "101011"; when 44 => SATA_MIN_BURST_1_BINARY <= "101100"; when 45 => SATA_MIN_BURST_1_BINARY <= "101101"; when 46 => SATA_MIN_BURST_1_BINARY <= "101110"; when 47 => SATA_MIN_BURST_1_BINARY <= "101111"; when 48 => SATA_MIN_BURST_1_BINARY <= "110000"; when 49 => SATA_MIN_BURST_1_BINARY <= "110001"; when 50 => SATA_MIN_BURST_1_BINARY <= "110010"; when 51 => SATA_MIN_BURST_1_BINARY <= "110011"; when 52 => SATA_MIN_BURST_1_BINARY <= "110100"; when 53 => SATA_MIN_BURST_1_BINARY <= "110101"; when 54 => SATA_MIN_BURST_1_BINARY <= "110110"; when 55 => SATA_MIN_BURST_1_BINARY <= "110111"; when 56 => SATA_MIN_BURST_1_BINARY <= "111000"; when 57 => SATA_MIN_BURST_1_BINARY <= "111001"; when 58 => SATA_MIN_BURST_1_BINARY <= "111010"; when 59 => SATA_MIN_BURST_1_BINARY <= "111011"; when 60 => SATA_MIN_BURST_1_BINARY <= "111100"; when 61 => SATA_MIN_BURST_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_BURST_1 is not in range 1...61." severity error; end case; case SATA_MAX_BURST_1 is when 1 => SATA_MAX_BURST_1_BINARY <= "000001"; when 2 => SATA_MAX_BURST_1_BINARY <= "000010"; when 3 => SATA_MAX_BURST_1_BINARY <= "000011"; when 4 => SATA_MAX_BURST_1_BINARY <= "000100"; when 5 => SATA_MAX_BURST_1_BINARY <= "000101"; when 6 => SATA_MAX_BURST_1_BINARY <= "000110"; when 7 => SATA_MAX_BURST_1_BINARY <= "000111"; when 8 => SATA_MAX_BURST_1_BINARY <= "001000"; when 9 => SATA_MAX_BURST_1_BINARY <= "001001"; when 10 => SATA_MAX_BURST_1_BINARY <= "001010"; when 11 => SATA_MAX_BURST_1_BINARY <= "001011"; when 12 => SATA_MAX_BURST_1_BINARY <= "001100"; when 13 => SATA_MAX_BURST_1_BINARY <= "001101"; when 14 => SATA_MAX_BURST_1_BINARY <= "001110"; when 15 => SATA_MAX_BURST_1_BINARY <= "001111"; when 16 => SATA_MAX_BURST_1_BINARY <= "010000"; when 17 => SATA_MAX_BURST_1_BINARY <= "010001"; when 18 => SATA_MAX_BURST_1_BINARY <= "010010"; when 19 => SATA_MAX_BURST_1_BINARY <= "010011"; when 20 => SATA_MAX_BURST_1_BINARY <= "010100"; when 21 => SATA_MAX_BURST_1_BINARY <= "010101"; when 22 => SATA_MAX_BURST_1_BINARY <= "010110"; when 23 => SATA_MAX_BURST_1_BINARY <= "010111"; when 24 => SATA_MAX_BURST_1_BINARY <= "011000"; when 25 => SATA_MAX_BURST_1_BINARY <= "011001"; when 26 => SATA_MAX_BURST_1_BINARY <= "011010"; when 27 => SATA_MAX_BURST_1_BINARY <= "011011"; when 28 => SATA_MAX_BURST_1_BINARY <= "011100"; when 29 => SATA_MAX_BURST_1_BINARY <= "011101"; when 30 => SATA_MAX_BURST_1_BINARY <= "011110"; when 31 => SATA_MAX_BURST_1_BINARY <= "011111"; when 32 => SATA_MAX_BURST_1_BINARY <= "100000"; when 33 => SATA_MAX_BURST_1_BINARY <= "100001"; when 34 => SATA_MAX_BURST_1_BINARY <= "100010"; when 35 => SATA_MAX_BURST_1_BINARY <= "100011"; when 36 => SATA_MAX_BURST_1_BINARY <= "100100"; when 37 => SATA_MAX_BURST_1_BINARY <= "100101"; when 38 => SATA_MAX_BURST_1_BINARY <= "100110"; when 39 => SATA_MAX_BURST_1_BINARY <= "100111"; when 40 => SATA_MAX_BURST_1_BINARY <= "101000"; when 41 => SATA_MAX_BURST_1_BINARY <= "101001"; when 42 => SATA_MAX_BURST_1_BINARY <= "101010"; when 43 => SATA_MAX_BURST_1_BINARY <= "101011"; when 44 => SATA_MAX_BURST_1_BINARY <= "101100"; when 45 => SATA_MAX_BURST_1_BINARY <= "101101"; when 46 => SATA_MAX_BURST_1_BINARY <= "101110"; when 47 => SATA_MAX_BURST_1_BINARY <= "101111"; when 48 => SATA_MAX_BURST_1_BINARY <= "110000"; when 49 => SATA_MAX_BURST_1_BINARY <= "110001"; when 50 => SATA_MAX_BURST_1_BINARY <= "110010"; when 51 => SATA_MAX_BURST_1_BINARY <= "110011"; when 52 => SATA_MAX_BURST_1_BINARY <= "110100"; when 53 => SATA_MAX_BURST_1_BINARY <= "110101"; when 54 => SATA_MAX_BURST_1_BINARY <= "110110"; when 55 => SATA_MAX_BURST_1_BINARY <= "110111"; when 56 => SATA_MAX_BURST_1_BINARY <= "111000"; when 57 => SATA_MAX_BURST_1_BINARY <= "111001"; when 58 => SATA_MAX_BURST_1_BINARY <= "111010"; when 59 => SATA_MAX_BURST_1_BINARY <= "111011"; when 60 => SATA_MAX_BURST_1_BINARY <= "111100"; when 61 => SATA_MAX_BURST_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_BURST_1 is not in range 1...61." severity error; end case; case SATA_MIN_INIT_1 is when 1 => SATA_MIN_INIT_1_BINARY <= "000001"; when 2 => SATA_MIN_INIT_1_BINARY <= "000010"; when 3 => SATA_MIN_INIT_1_BINARY <= "000011"; when 4 => SATA_MIN_INIT_1_BINARY <= "000100"; when 5 => SATA_MIN_INIT_1_BINARY <= "000101"; when 6 => SATA_MIN_INIT_1_BINARY <= "000110"; when 7 => SATA_MIN_INIT_1_BINARY <= "000111"; when 8 => SATA_MIN_INIT_1_BINARY <= "001000"; when 9 => SATA_MIN_INIT_1_BINARY <= "001001"; when 10 => SATA_MIN_INIT_1_BINARY <= "001010"; when 11 => SATA_MIN_INIT_1_BINARY <= "001011"; when 12 => SATA_MIN_INIT_1_BINARY <= "001100"; when 13 => SATA_MIN_INIT_1_BINARY <= "001101"; when 14 => SATA_MIN_INIT_1_BINARY <= "001110"; when 15 => SATA_MIN_INIT_1_BINARY <= "001111"; when 16 => SATA_MIN_INIT_1_BINARY <= "010000"; when 17 => SATA_MIN_INIT_1_BINARY <= "010001"; when 18 => SATA_MIN_INIT_1_BINARY <= "010010"; when 19 => SATA_MIN_INIT_1_BINARY <= "010011"; when 20 => SATA_MIN_INIT_1_BINARY <= "010100"; when 21 => SATA_MIN_INIT_1_BINARY <= "010101"; when 22 => SATA_MIN_INIT_1_BINARY <= "010110"; when 23 => SATA_MIN_INIT_1_BINARY <= "010111"; when 24 => SATA_MIN_INIT_1_BINARY <= "011000"; when 25 => SATA_MIN_INIT_1_BINARY <= "011001"; when 26 => SATA_MIN_INIT_1_BINARY <= "011010"; when 27 => SATA_MIN_INIT_1_BINARY <= "011011"; when 28 => SATA_MIN_INIT_1_BINARY <= "011100"; when 29 => SATA_MIN_INIT_1_BINARY <= "011101"; when 30 => SATA_MIN_INIT_1_BINARY <= "011110"; when 31 => SATA_MIN_INIT_1_BINARY <= "011111"; when 32 => SATA_MIN_INIT_1_BINARY <= "100000"; when 33 => SATA_MIN_INIT_1_BINARY <= "100001"; when 34 => SATA_MIN_INIT_1_BINARY <= "100010"; when 35 => SATA_MIN_INIT_1_BINARY <= "100011"; when 36 => SATA_MIN_INIT_1_BINARY <= "100100"; when 37 => SATA_MIN_INIT_1_BINARY <= "100101"; when 38 => SATA_MIN_INIT_1_BINARY <= "100110"; when 39 => SATA_MIN_INIT_1_BINARY <= "100111"; when 40 => SATA_MIN_INIT_1_BINARY <= "101000"; when 41 => SATA_MIN_INIT_1_BINARY <= "101001"; when 42 => SATA_MIN_INIT_1_BINARY <= "101010"; when 43 => SATA_MIN_INIT_1_BINARY <= "101011"; when 44 => SATA_MIN_INIT_1_BINARY <= "101100"; when 45 => SATA_MIN_INIT_1_BINARY <= "101101"; when 46 => SATA_MIN_INIT_1_BINARY <= "101110"; when 47 => SATA_MIN_INIT_1_BINARY <= "101111"; when 48 => SATA_MIN_INIT_1_BINARY <= "110000"; when 49 => SATA_MIN_INIT_1_BINARY <= "110001"; when 50 => SATA_MIN_INIT_1_BINARY <= "110010"; when 51 => SATA_MIN_INIT_1_BINARY <= "110011"; when 52 => SATA_MIN_INIT_1_BINARY <= "110100"; when 53 => SATA_MIN_INIT_1_BINARY <= "110101"; when 54 => SATA_MIN_INIT_1_BINARY <= "110110"; when 55 => SATA_MIN_INIT_1_BINARY <= "110111"; when 56 => SATA_MIN_INIT_1_BINARY <= "111000"; when 57 => SATA_MIN_INIT_1_BINARY <= "111001"; when 58 => SATA_MIN_INIT_1_BINARY <= "111010"; when 59 => SATA_MIN_INIT_1_BINARY <= "111011"; when 60 => SATA_MIN_INIT_1_BINARY <= "111100"; when 61 => SATA_MIN_INIT_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_INIT_1 is not in range 1...61." severity error; end case; case SATA_MAX_INIT_1 is when 1 => SATA_MAX_INIT_1_BINARY <= "000001"; when 2 => SATA_MAX_INIT_1_BINARY <= "000010"; when 3 => SATA_MAX_INIT_1_BINARY <= "000011"; when 4 => SATA_MAX_INIT_1_BINARY <= "000100"; when 5 => SATA_MAX_INIT_1_BINARY <= "000101"; when 6 => SATA_MAX_INIT_1_BINARY <= "000110"; when 7 => SATA_MAX_INIT_1_BINARY <= "000111"; when 8 => SATA_MAX_INIT_1_BINARY <= "001000"; when 9 => SATA_MAX_INIT_1_BINARY <= "001001"; when 10 => SATA_MAX_INIT_1_BINARY <= "001010"; when 11 => SATA_MAX_INIT_1_BINARY <= "001011"; when 12 => SATA_MAX_INIT_1_BINARY <= "001100"; when 13 => SATA_MAX_INIT_1_BINARY <= "001101"; when 14 => SATA_MAX_INIT_1_BINARY <= "001110"; when 15 => SATA_MAX_INIT_1_BINARY <= "001111"; when 16 => SATA_MAX_INIT_1_BINARY <= "010000"; when 17 => SATA_MAX_INIT_1_BINARY <= "010001"; when 18 => SATA_MAX_INIT_1_BINARY <= "010010"; when 19 => SATA_MAX_INIT_1_BINARY <= "010011"; when 20 => SATA_MAX_INIT_1_BINARY <= "010100"; when 21 => SATA_MAX_INIT_1_BINARY <= "010101"; when 22 => SATA_MAX_INIT_1_BINARY <= "010110"; when 23 => SATA_MAX_INIT_1_BINARY <= "010111"; when 24 => SATA_MAX_INIT_1_BINARY <= "011000"; when 25 => SATA_MAX_INIT_1_BINARY <= "011001"; when 26 => SATA_MAX_INIT_1_BINARY <= "011010"; when 27 => SATA_MAX_INIT_1_BINARY <= "011011"; when 28 => SATA_MAX_INIT_1_BINARY <= "011100"; when 29 => SATA_MAX_INIT_1_BINARY <= "011101"; when 30 => SATA_MAX_INIT_1_BINARY <= "011110"; when 31 => SATA_MAX_INIT_1_BINARY <= "011111"; when 32 => SATA_MAX_INIT_1_BINARY <= "100000"; when 33 => SATA_MAX_INIT_1_BINARY <= "100001"; when 34 => SATA_MAX_INIT_1_BINARY <= "100010"; when 35 => SATA_MAX_INIT_1_BINARY <= "100011"; when 36 => SATA_MAX_INIT_1_BINARY <= "100100"; when 37 => SATA_MAX_INIT_1_BINARY <= "100101"; when 38 => SATA_MAX_INIT_1_BINARY <= "100110"; when 39 => SATA_MAX_INIT_1_BINARY <= "100111"; when 40 => SATA_MAX_INIT_1_BINARY <= "101000"; when 41 => SATA_MAX_INIT_1_BINARY <= "101001"; when 42 => SATA_MAX_INIT_1_BINARY <= "101010"; when 43 => SATA_MAX_INIT_1_BINARY <= "101011"; when 44 => SATA_MAX_INIT_1_BINARY <= "101100"; when 45 => SATA_MAX_INIT_1_BINARY <= "101101"; when 46 => SATA_MAX_INIT_1_BINARY <= "101110"; when 47 => SATA_MAX_INIT_1_BINARY <= "101111"; when 48 => SATA_MAX_INIT_1_BINARY <= "110000"; when 49 => SATA_MAX_INIT_1_BINARY <= "110001"; when 50 => SATA_MAX_INIT_1_BINARY <= "110010"; when 51 => SATA_MAX_INIT_1_BINARY <= "110011"; when 52 => SATA_MAX_INIT_1_BINARY <= "110100"; when 53 => SATA_MAX_INIT_1_BINARY <= "110101"; when 54 => SATA_MAX_INIT_1_BINARY <= "110110"; when 55 => SATA_MAX_INIT_1_BINARY <= "110111"; when 56 => SATA_MAX_INIT_1_BINARY <= "111000"; when 57 => SATA_MAX_INIT_1_BINARY <= "111001"; when 58 => SATA_MAX_INIT_1_BINARY <= "111010"; when 59 => SATA_MAX_INIT_1_BINARY <= "111011"; when 60 => SATA_MAX_INIT_1_BINARY <= "111100"; when 61 => SATA_MAX_INIT_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_INIT_1 is not in range 1...61." severity error; end case; case SATA_MIN_WAKE_1 is when 1 => SATA_MIN_WAKE_1_BINARY <= "000001"; when 2 => SATA_MIN_WAKE_1_BINARY <= "000010"; when 3 => SATA_MIN_WAKE_1_BINARY <= "000011"; when 4 => SATA_MIN_WAKE_1_BINARY <= "000100"; when 5 => SATA_MIN_WAKE_1_BINARY <= "000101"; when 6 => SATA_MIN_WAKE_1_BINARY <= "000110"; when 7 => SATA_MIN_WAKE_1_BINARY <= "000111"; when 8 => SATA_MIN_WAKE_1_BINARY <= "001000"; when 9 => SATA_MIN_WAKE_1_BINARY <= "001001"; when 10 => SATA_MIN_WAKE_1_BINARY <= "001010"; when 11 => SATA_MIN_WAKE_1_BINARY <= "001011"; when 12 => SATA_MIN_WAKE_1_BINARY <= "001100"; when 13 => SATA_MIN_WAKE_1_BINARY <= "001101"; when 14 => SATA_MIN_WAKE_1_BINARY <= "001110"; when 15 => SATA_MIN_WAKE_1_BINARY <= "001111"; when 16 => SATA_MIN_WAKE_1_BINARY <= "010000"; when 17 => SATA_MIN_WAKE_1_BINARY <= "010001"; when 18 => SATA_MIN_WAKE_1_BINARY <= "010010"; when 19 => SATA_MIN_WAKE_1_BINARY <= "010011"; when 20 => SATA_MIN_WAKE_1_BINARY <= "010100"; when 21 => SATA_MIN_WAKE_1_BINARY <= "010101"; when 22 => SATA_MIN_WAKE_1_BINARY <= "010110"; when 23 => SATA_MIN_WAKE_1_BINARY <= "010111"; when 24 => SATA_MIN_WAKE_1_BINARY <= "011000"; when 25 => SATA_MIN_WAKE_1_BINARY <= "011001"; when 26 => SATA_MIN_WAKE_1_BINARY <= "011010"; when 27 => SATA_MIN_WAKE_1_BINARY <= "011011"; when 28 => SATA_MIN_WAKE_1_BINARY <= "011100"; when 29 => SATA_MIN_WAKE_1_BINARY <= "011101"; when 30 => SATA_MIN_WAKE_1_BINARY <= "011110"; when 31 => SATA_MIN_WAKE_1_BINARY <= "011111"; when 32 => SATA_MIN_WAKE_1_BINARY <= "100000"; when 33 => SATA_MIN_WAKE_1_BINARY <= "100001"; when 34 => SATA_MIN_WAKE_1_BINARY <= "100010"; when 35 => SATA_MIN_WAKE_1_BINARY <= "100011"; when 36 => SATA_MIN_WAKE_1_BINARY <= "100100"; when 37 => SATA_MIN_WAKE_1_BINARY <= "100101"; when 38 => SATA_MIN_WAKE_1_BINARY <= "100110"; when 39 => SATA_MIN_WAKE_1_BINARY <= "100111"; when 40 => SATA_MIN_WAKE_1_BINARY <= "101000"; when 41 => SATA_MIN_WAKE_1_BINARY <= "101001"; when 42 => SATA_MIN_WAKE_1_BINARY <= "101010"; when 43 => SATA_MIN_WAKE_1_BINARY <= "101011"; when 44 => SATA_MIN_WAKE_1_BINARY <= "101100"; when 45 => SATA_MIN_WAKE_1_BINARY <= "101101"; when 46 => SATA_MIN_WAKE_1_BINARY <= "101110"; when 47 => SATA_MIN_WAKE_1_BINARY <= "101111"; when 48 => SATA_MIN_WAKE_1_BINARY <= "110000"; when 49 => SATA_MIN_WAKE_1_BINARY <= "110001"; when 50 => SATA_MIN_WAKE_1_BINARY <= "110010"; when 51 => SATA_MIN_WAKE_1_BINARY <= "110011"; when 52 => SATA_MIN_WAKE_1_BINARY <= "110100"; when 53 => SATA_MIN_WAKE_1_BINARY <= "110101"; when 54 => SATA_MIN_WAKE_1_BINARY <= "110110"; when 55 => SATA_MIN_WAKE_1_BINARY <= "110111"; when 56 => SATA_MIN_WAKE_1_BINARY <= "111000"; when 57 => SATA_MIN_WAKE_1_BINARY <= "111001"; when 58 => SATA_MIN_WAKE_1_BINARY <= "111010"; when 59 => SATA_MIN_WAKE_1_BINARY <= "111011"; when 60 => SATA_MIN_WAKE_1_BINARY <= "111100"; when 61 => SATA_MIN_WAKE_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MIN_WAKE_1 is not in range 1...61." severity error; end case; case SATA_MAX_WAKE_1 is when 1 => SATA_MAX_WAKE_1_BINARY <= "000001"; when 2 => SATA_MAX_WAKE_1_BINARY <= "000010"; when 3 => SATA_MAX_WAKE_1_BINARY <= "000011"; when 4 => SATA_MAX_WAKE_1_BINARY <= "000100"; when 5 => SATA_MAX_WAKE_1_BINARY <= "000101"; when 6 => SATA_MAX_WAKE_1_BINARY <= "000110"; when 7 => SATA_MAX_WAKE_1_BINARY <= "000111"; when 8 => SATA_MAX_WAKE_1_BINARY <= "001000"; when 9 => SATA_MAX_WAKE_1_BINARY <= "001001"; when 10 => SATA_MAX_WAKE_1_BINARY <= "001010"; when 11 => SATA_MAX_WAKE_1_BINARY <= "001011"; when 12 => SATA_MAX_WAKE_1_BINARY <= "001100"; when 13 => SATA_MAX_WAKE_1_BINARY <= "001101"; when 14 => SATA_MAX_WAKE_1_BINARY <= "001110"; when 15 => SATA_MAX_WAKE_1_BINARY <= "001111"; when 16 => SATA_MAX_WAKE_1_BINARY <= "010000"; when 17 => SATA_MAX_WAKE_1_BINARY <= "010001"; when 18 => SATA_MAX_WAKE_1_BINARY <= "010010"; when 19 => SATA_MAX_WAKE_1_BINARY <= "010011"; when 20 => SATA_MAX_WAKE_1_BINARY <= "010100"; when 21 => SATA_MAX_WAKE_1_BINARY <= "010101"; when 22 => SATA_MAX_WAKE_1_BINARY <= "010110"; when 23 => SATA_MAX_WAKE_1_BINARY <= "010111"; when 24 => SATA_MAX_WAKE_1_BINARY <= "011000"; when 25 => SATA_MAX_WAKE_1_BINARY <= "011001"; when 26 => SATA_MAX_WAKE_1_BINARY <= "011010"; when 27 => SATA_MAX_WAKE_1_BINARY <= "011011"; when 28 => SATA_MAX_WAKE_1_BINARY <= "011100"; when 29 => SATA_MAX_WAKE_1_BINARY <= "011101"; when 30 => SATA_MAX_WAKE_1_BINARY <= "011110"; when 31 => SATA_MAX_WAKE_1_BINARY <= "011111"; when 32 => SATA_MAX_WAKE_1_BINARY <= "100000"; when 33 => SATA_MAX_WAKE_1_BINARY <= "100001"; when 34 => SATA_MAX_WAKE_1_BINARY <= "100010"; when 35 => SATA_MAX_WAKE_1_BINARY <= "100011"; when 36 => SATA_MAX_WAKE_1_BINARY <= "100100"; when 37 => SATA_MAX_WAKE_1_BINARY <= "100101"; when 38 => SATA_MAX_WAKE_1_BINARY <= "100110"; when 39 => SATA_MAX_WAKE_1_BINARY <= "100111"; when 40 => SATA_MAX_WAKE_1_BINARY <= "101000"; when 41 => SATA_MAX_WAKE_1_BINARY <= "101001"; when 42 => SATA_MAX_WAKE_1_BINARY <= "101010"; when 43 => SATA_MAX_WAKE_1_BINARY <= "101011"; when 44 => SATA_MAX_WAKE_1_BINARY <= "101100"; when 45 => SATA_MAX_WAKE_1_BINARY <= "101101"; when 46 => SATA_MAX_WAKE_1_BINARY <= "101110"; when 47 => SATA_MAX_WAKE_1_BINARY <= "101111"; when 48 => SATA_MAX_WAKE_1_BINARY <= "110000"; when 49 => SATA_MAX_WAKE_1_BINARY <= "110001"; when 50 => SATA_MAX_WAKE_1_BINARY <= "110010"; when 51 => SATA_MAX_WAKE_1_BINARY <= "110011"; when 52 => SATA_MAX_WAKE_1_BINARY <= "110100"; when 53 => SATA_MAX_WAKE_1_BINARY <= "110101"; when 54 => SATA_MAX_WAKE_1_BINARY <= "110110"; when 55 => SATA_MAX_WAKE_1_BINARY <= "110111"; when 56 => SATA_MAX_WAKE_1_BINARY <= "111000"; when 57 => SATA_MAX_WAKE_1_BINARY <= "111001"; when 58 => SATA_MAX_WAKE_1_BINARY <= "111010"; when 59 => SATA_MAX_WAKE_1_BINARY <= "111011"; when 60 => SATA_MAX_WAKE_1_BINARY <= "111100"; when 61 => SATA_MAX_WAKE_1_BINARY <= "111101"; when others => assert FALSE report "Error : SATA_MAX_WAKE_1 is not in range 1...61." severity error; end case; case CLK25_DIVIDER is when 1 => CLK25_DIVIDER_BINARY <= "000"; when 2 => CLK25_DIVIDER_BINARY <= "001"; when 3 => CLK25_DIVIDER_BINARY <= "010"; when 4 => CLK25_DIVIDER_BINARY <= "011"; when 5 => CLK25_DIVIDER_BINARY <= "100"; when 6 => CLK25_DIVIDER_BINARY <= "101"; when 10 => CLK25_DIVIDER_BINARY <= "110"; when 12 => CLK25_DIVIDER_BINARY <= "111"; when others => assert FALSE report "Error : CLK25_DIVIDER is not in 1, 2, 3, 4, 5, 6, 10, 12." severity error; end case; case OVERSAMPLE_MODE is when FALSE => OVERSAMPLE_MODE_BINARY <= '0'; when TRUE => OVERSAMPLE_MODE_BINARY <= '1'; when others => assert FALSE report "Error : OVERSAMPLE_MODE is neither TRUE nor FALSE." severity error; end case; case TXGEARBOX_USE_0 is when FALSE => TXGEARBOX_USE_0_BINARY <= '0'; when TRUE => TXGEARBOX_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : TXGEARBOX_USE_0 is neither TRUE nor FALSE." severity error; end case; case RXGEARBOX_USE_0 is when FALSE => RXGEARBOX_USE_0_BINARY <= '0'; when TRUE => RXGEARBOX_USE_0_BINARY <= '1'; when others => assert FALSE report "Error : RXGEARBOX_USE_0 is neither TRUE nor FALSE." severity error; end case; case TXGEARBOX_USE_1 is when FALSE => TXGEARBOX_USE_1_BINARY <= '0'; when TRUE => TXGEARBOX_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : TXGEARBOX_USE_1 is neither TRUE nor FALSE." severity error; end case; case RXGEARBOX_USE_1 is when FALSE => RXGEARBOX_USE_1_BINARY <= '0'; when TRUE => RXGEARBOX_USE_1_BINARY <= '1'; when others => assert FALSE report "Error : RXGEARBOX_USE_1 is neither TRUE nor FALSE." severity error; end case; case PLL_FB_DCCEN is when FALSE => PLL_FB_DCCEN_BINARY <= '0'; when TRUE => PLL_FB_DCCEN_BINARY <= '1'; when others => assert FALSE report "Error : PLL_FB_DCCEN is neither TRUE nor FALSE." severity error; end case; case CLKRCV_TRST is when FALSE => CLKRCV_TRST_BINARY <= '0'; when TRUE => CLKRCV_TRST_BINARY <= '1'; when others => assert FALSE report "Error : CLKRCV_TRST is neither TRUE nor FALSE." severity error; end case; case RX_EN_IDLE_HOLD_DFE_0 is when FALSE => RX_EN_IDLE_HOLD_DFE_0_BINARY <= '0'; when TRUE => RX_EN_IDLE_HOLD_DFE_0_BINARY <= '1'; when others => assert FALSE report "Error : RX_EN_IDLE_HOLD_DFE_0 is neither TRUE nor FALSE." severity error; end case; case RX_EN_IDLE_RESET_BUF_0 is when FALSE => RX_EN_IDLE_RESET_BUF_0_BINARY <= '0'; when TRUE => RX_EN_IDLE_RESET_BUF_0_BINARY <= '1'; when others => assert FALSE report "Error : RX_EN_IDLE_RESET_BUF_0 is neither TRUE nor FALSE." severity error; end case; case RX_EN_IDLE_HOLD_DFE_1 is when FALSE => RX_EN_IDLE_HOLD_DFE_1_BINARY <= '0'; when TRUE => RX_EN_IDLE_HOLD_DFE_1_BINARY <= '1'; when others => assert FALSE report "Error : RX_EN_IDLE_HOLD_DFE_1 is neither TRUE nor FALSE." severity error; end case; case RX_EN_IDLE_RESET_BUF_1 is when FALSE => RX_EN_IDLE_RESET_BUF_1_BINARY <= '0'; when TRUE => RX_EN_IDLE_RESET_BUF_1_BINARY <= '1'; when others => assert FALSE report "Error : RX_EN_IDLE_RESET_BUF_1 is neither TRUE nor FALSE." severity error; end case; case RX_EN_IDLE_HOLD_CDR is when FALSE => RX_EN_IDLE_HOLD_CDR_BINARY <= '0'; when TRUE => RX_EN_IDLE_HOLD_CDR_BINARY <= '1'; when others => assert FALSE report "Error : RX_EN_IDLE_HOLD_CDR is neither TRUE nor FALSE." severity error; end case; case RX_EN_IDLE_RESET_PH is when FALSE => RX_EN_IDLE_RESET_PH_BINARY <= '0'; when TRUE => RX_EN_IDLE_RESET_PH_BINARY <= '1'; when others => assert FALSE report "Error : RX_EN_IDLE_RESET_PH is neither TRUE nor FALSE." severity error; end case; case RX_EN_IDLE_RESET_FR is when FALSE => RX_EN_IDLE_RESET_FR_BINARY <= '0'; when TRUE => RX_EN_IDLE_RESET_FR_BINARY <= '1'; when others => assert FALSE report "Error : RX_EN_IDLE_RESET_FR is neither TRUE nor FALSE." severity error; end case; case SIM_GTXRESET_SPEEDUP is when 0 => SIM_GTXRESET_SPEEDUP_BINARY <= '0'; when 1 => SIM_GTXRESET_SPEEDUP_BINARY <= '1'; when others => assert FALSE report "Error : SIM_GTXRESET_SPEEDUP is not in 0, 1." severity error; end case; -- case SIM_MODE is if((SIM_MODE = "LEGACY") or (SIM_MODE = "legacy")) then SIM_MODE_BINARY <= '1'; elsif((SIM_MODE = "FAST") or (SIM_MODE = "fast")) then SIM_MODE_BINARY <= '0'; else assert FALSE report "Error : SIM_MODE = is not LEGACY, FAST." severity error; end if; -- end case; case SIM_RECEIVER_DETECT_PASS_0 is when FALSE => SIM_RECEIVER_DETECT_PASS_0_BINARY <= '0'; when TRUE => SIM_RECEIVER_DETECT_PASS_0_BINARY <= '1'; when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS_0 is neither TRUE nor FALSE." severity error; end case; case SIM_RECEIVER_DETECT_PASS_1 is when FALSE => SIM_RECEIVER_DETECT_PASS_1_BINARY <= '0'; when TRUE => SIM_RECEIVER_DETECT_PASS_1_BINARY <= '1'; when others => assert FALSE report "Error : SIM_RECEIVER_DETECT_PASS_1 is neither TRUE nor FALSE." severity error; end case; wait; end process INIPROC; TIMING : process variable REFCLKOUT_GlitchData : VitalGlitchDataType; variable RXRECCLK0_GlitchData : VitalGlitchDataType; variable TXOUTCLK0_GlitchData : VitalGlitchDataType; variable RXRECCLK1_GlitchData : VitalGlitchDataType; variable TXOUTCLK1_GlitchData : VitalGlitchDataType; variable TXP0_GlitchData : VitalGlitchDataType; variable TXN0_GlitchData : VitalGlitchDataType; variable TXP1_GlitchData : VitalGlitchDataType; variable TXN1_GlitchData : VitalGlitchDataType; variable RXDATA00_GlitchData : VitalGlitchDataType; variable RXDATA01_GlitchData : VitalGlitchDataType; variable RXDATA02_GlitchData : VitalGlitchDataType; variable RXDATA03_GlitchData : VitalGlitchDataType; variable RXDATA04_GlitchData : VitalGlitchDataType; variable RXDATA05_GlitchData : VitalGlitchDataType; variable RXDATA06_GlitchData : VitalGlitchDataType; variable RXDATA07_GlitchData : VitalGlitchDataType; variable RXDATA08_GlitchData : VitalGlitchDataType; variable RXDATA09_GlitchData : VitalGlitchDataType; variable RXDATA010_GlitchData : VitalGlitchDataType; variable RXDATA011_GlitchData : VitalGlitchDataType; variable RXDATA012_GlitchData : VitalGlitchDataType; variable RXDATA013_GlitchData : VitalGlitchDataType; variable RXDATA014_GlitchData : VitalGlitchDataType; variable RXDATA015_GlitchData : VitalGlitchDataType; variable RXDATA016_GlitchData : VitalGlitchDataType; variable RXDATA017_GlitchData : VitalGlitchDataType; variable RXDATA018_GlitchData : VitalGlitchDataType; variable RXDATA019_GlitchData : VitalGlitchDataType; variable RXDATA020_GlitchData : VitalGlitchDataType; variable RXDATA021_GlitchData : VitalGlitchDataType; variable RXDATA022_GlitchData : VitalGlitchDataType; variable RXDATA023_GlitchData : VitalGlitchDataType; variable RXDATA024_GlitchData : VitalGlitchDataType; variable RXDATA025_GlitchData : VitalGlitchDataType; variable RXDATA026_GlitchData : VitalGlitchDataType; variable RXDATA027_GlitchData : VitalGlitchDataType; variable RXDATA028_GlitchData : VitalGlitchDataType; variable RXDATA029_GlitchData : VitalGlitchDataType; variable RXDATA030_GlitchData : VitalGlitchDataType; variable RXDATA031_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE00_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE01_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE02_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE03_GlitchData : VitalGlitchDataType; variable RXDISPERR00_GlitchData : VitalGlitchDataType; variable RXDISPERR01_GlitchData : VitalGlitchDataType; variable RXDISPERR02_GlitchData : VitalGlitchDataType; variable RXDISPERR03_GlitchData : VitalGlitchDataType; variable RXCHARISK00_GlitchData : VitalGlitchDataType; variable RXCHARISK01_GlitchData : VitalGlitchDataType; variable RXCHARISK02_GlitchData : VitalGlitchDataType; variable RXCHARISK03_GlitchData : VitalGlitchDataType; variable RXRUNDISP00_GlitchData : VitalGlitchDataType; variable RXRUNDISP01_GlitchData : VitalGlitchDataType; variable RXRUNDISP02_GlitchData : VitalGlitchDataType; variable RXRUNDISP03_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA00_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA01_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA02_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA03_GlitchData : VitalGlitchDataType; variable RXVALID0_GlitchData : VitalGlitchDataType; variable RXDATA10_GlitchData : VitalGlitchDataType; variable RXDATA11_GlitchData : VitalGlitchDataType; variable RXDATA12_GlitchData : VitalGlitchDataType; variable RXDATA13_GlitchData : VitalGlitchDataType; variable RXDATA14_GlitchData : VitalGlitchDataType; variable RXDATA15_GlitchData : VitalGlitchDataType; variable RXDATA16_GlitchData : VitalGlitchDataType; variable RXDATA17_GlitchData : VitalGlitchDataType; variable RXDATA18_GlitchData : VitalGlitchDataType; variable RXDATA19_GlitchData : VitalGlitchDataType; variable RXDATA110_GlitchData : VitalGlitchDataType; variable RXDATA111_GlitchData : VitalGlitchDataType; variable RXDATA112_GlitchData : VitalGlitchDataType; variable RXDATA113_GlitchData : VitalGlitchDataType; variable RXDATA114_GlitchData : VitalGlitchDataType; variable RXDATA115_GlitchData : VitalGlitchDataType; variable RXDATA116_GlitchData : VitalGlitchDataType; variable RXDATA117_GlitchData : VitalGlitchDataType; variable RXDATA118_GlitchData : VitalGlitchDataType; variable RXDATA119_GlitchData : VitalGlitchDataType; variable RXDATA120_GlitchData : VitalGlitchDataType; variable RXDATA121_GlitchData : VitalGlitchDataType; variable RXDATA122_GlitchData : VitalGlitchDataType; variable RXDATA123_GlitchData : VitalGlitchDataType; variable RXDATA124_GlitchData : VitalGlitchDataType; variable RXDATA125_GlitchData : VitalGlitchDataType; variable RXDATA126_GlitchData : VitalGlitchDataType; variable RXDATA127_GlitchData : VitalGlitchDataType; variable RXDATA128_GlitchData : VitalGlitchDataType; variable RXDATA129_GlitchData : VitalGlitchDataType; variable RXDATA130_GlitchData : VitalGlitchDataType; variable RXDATA131_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE10_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE11_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE12_GlitchData : VitalGlitchDataType; variable RXNOTINTABLE13_GlitchData : VitalGlitchDataType; variable RXDISPERR10_GlitchData : VitalGlitchDataType; variable RXDISPERR11_GlitchData : VitalGlitchDataType; variable RXDISPERR12_GlitchData : VitalGlitchDataType; variable RXDISPERR13_GlitchData : VitalGlitchDataType; variable RXCHARISK10_GlitchData : VitalGlitchDataType; variable RXCHARISK11_GlitchData : VitalGlitchDataType; variable RXCHARISK12_GlitchData : VitalGlitchDataType; variable RXCHARISK13_GlitchData : VitalGlitchDataType; variable RXRUNDISP10_GlitchData : VitalGlitchDataType; variable RXRUNDISP11_GlitchData : VitalGlitchDataType; variable RXRUNDISP12_GlitchData : VitalGlitchDataType; variable RXRUNDISP13_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA10_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA11_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA12_GlitchData : VitalGlitchDataType; variable RXCHARISCOMMA13_GlitchData : VitalGlitchDataType; variable RXVALID1_GlitchData : VitalGlitchDataType; variable RESETDONE0_GlitchData : VitalGlitchDataType; variable RESETDONE1_GlitchData : VitalGlitchDataType; variable TXKERR00_GlitchData : VitalGlitchDataType; variable TXKERR01_GlitchData : VitalGlitchDataType; variable TXKERR02_GlitchData : VitalGlitchDataType; variable TXKERR03_GlitchData : VitalGlitchDataType; variable TXRUNDISP00_GlitchData : VitalGlitchDataType; variable TXRUNDISP01_GlitchData : VitalGlitchDataType; variable TXRUNDISP02_GlitchData : VitalGlitchDataType; variable TXRUNDISP03_GlitchData : VitalGlitchDataType; variable TXBUFSTATUS00_GlitchData : VitalGlitchDataType; variable TXBUFSTATUS01_GlitchData : VitalGlitchDataType; variable TXKERR10_GlitchData : VitalGlitchDataType; variable TXKERR11_GlitchData : VitalGlitchDataType; variable TXKERR12_GlitchData : VitalGlitchDataType; variable TXKERR13_GlitchData : VitalGlitchDataType; variable TXRUNDISP10_GlitchData : VitalGlitchDataType; variable TXRUNDISP11_GlitchData : VitalGlitchDataType; variable TXRUNDISP12_GlitchData : VitalGlitchDataType; variable TXRUNDISP13_GlitchData : VitalGlitchDataType; variable TXBUFSTATUS10_GlitchData : VitalGlitchDataType; variable TXBUFSTATUS11_GlitchData : VitalGlitchDataType; variable RXCOMMADET0_GlitchData : VitalGlitchDataType; variable RXBYTEREALIGN0_GlitchData : VitalGlitchDataType; variable RXBYTEISALIGNED0_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC00_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC01_GlitchData : VitalGlitchDataType; variable RXCHBONDO00_GlitchData : VitalGlitchDataType; variable RXCHBONDO01_GlitchData : VitalGlitchDataType; variable RXCHBONDO02_GlitchData : VitalGlitchDataType; variable RXCHBONDO03_GlitchData : VitalGlitchDataType; variable RXCHANBONDSEQ0_GlitchData : VitalGlitchDataType; variable RXCHANREALIGN0_GlitchData : VitalGlitchDataType; variable RXCHANISALIGNED0_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS00_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS01_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS02_GlitchData : VitalGlitchDataType; variable RXCOMMADET1_GlitchData : VitalGlitchDataType; variable RXBYTEREALIGN1_GlitchData : VitalGlitchDataType; variable RXBYTEISALIGNED1_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC10_GlitchData : VitalGlitchDataType; variable RXLOSSOFSYNC11_GlitchData : VitalGlitchDataType; variable RXCHBONDO10_GlitchData : VitalGlitchDataType; variable RXCHBONDO11_GlitchData : VitalGlitchDataType; variable RXCHBONDO12_GlitchData : VitalGlitchDataType; variable RXCHBONDO13_GlitchData : VitalGlitchDataType; variable RXCHANBONDSEQ1_GlitchData : VitalGlitchDataType; variable RXCHANREALIGN1_GlitchData : VitalGlitchDataType; variable RXCHANISALIGNED1_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS10_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS11_GlitchData : VitalGlitchDataType; variable RXBUFSTATUS12_GlitchData : VitalGlitchDataType; variable PHYSTATUS0_GlitchData : VitalGlitchDataType; variable PHYSTATUS1_GlitchData : VitalGlitchDataType; variable RXELECIDLE0_GlitchData : VitalGlitchDataType; variable RXSTATUS00_GlitchData : VitalGlitchDataType; variable RXSTATUS01_GlitchData : VitalGlitchDataType; variable RXSTATUS02_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT00_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT01_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT02_GlitchData : VitalGlitchDataType; variable RXELECIDLE1_GlitchData : VitalGlitchDataType; variable RXSTATUS10_GlitchData : VitalGlitchDataType; variable RXSTATUS11_GlitchData : VitalGlitchDataType; variable RXSTATUS12_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT10_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT11_GlitchData : VitalGlitchDataType; variable RXCLKCORCNT12_GlitchData : VitalGlitchDataType; variable PLLLKDET_GlitchData : VitalGlitchDataType; variable RXPRBSERR0_GlitchData : VitalGlitchDataType; variable RXPRBSERR1_GlitchData : VitalGlitchDataType; variable DO0_GlitchData : VitalGlitchDataType; variable DO1_GlitchData : VitalGlitchDataType; variable DO2_GlitchData : VitalGlitchDataType; variable DO3_GlitchData : VitalGlitchDataType; variable DO4_GlitchData : VitalGlitchDataType; variable DO5_GlitchData : VitalGlitchDataType; variable DO6_GlitchData : VitalGlitchDataType; variable DO7_GlitchData : VitalGlitchDataType; variable DO8_GlitchData : VitalGlitchDataType; variable DO9_GlitchData : VitalGlitchDataType; variable DO10_GlitchData : VitalGlitchDataType; variable DO11_GlitchData : VitalGlitchDataType; variable DO12_GlitchData : VitalGlitchDataType; variable DO13_GlitchData : VitalGlitchDataType; variable DO14_GlitchData : VitalGlitchDataType; variable DO15_GlitchData : VitalGlitchDataType; variable DRDY_GlitchData : VitalGlitchDataType; variable RXOVERSAMPLEERR0_GlitchData : VitalGlitchDataType; variable RXOVERSAMPLEERR1_GlitchData : VitalGlitchDataType; variable TXGEARBOXREADY0_GlitchData : VitalGlitchDataType; variable RXHEADER00_GlitchData : VitalGlitchDataType; variable RXHEADER01_GlitchData : VitalGlitchDataType; variable RXHEADER02_GlitchData : VitalGlitchDataType; variable RXHEADERVALID0_GlitchData : VitalGlitchDataType; variable RXDATAVALID0_GlitchData : VitalGlitchDataType; variable RXSTARTOFSEQ0_GlitchData : VitalGlitchDataType; variable TXGEARBOXREADY1_GlitchData : VitalGlitchDataType; variable RXHEADER10_GlitchData : VitalGlitchDataType; variable RXHEADER11_GlitchData : VitalGlitchDataType; variable RXHEADER12_GlitchData : VitalGlitchDataType; variable RXHEADERVALID1_GlitchData : VitalGlitchDataType; variable RXDATAVALID1_GlitchData : VitalGlitchDataType; variable RXSTARTOFSEQ1_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR00_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR01_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR02_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR03_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR04_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR05_GlitchData : VitalGlitchDataType; variable DFEEYEDACMONITOR00_GlitchData : VitalGlitchDataType; variable DFEEYEDACMONITOR01_GlitchData : VitalGlitchDataType; variable DFEEYEDACMONITOR02_GlitchData : VitalGlitchDataType; variable DFEEYEDACMONITOR03_GlitchData : VitalGlitchDataType; variable DFEEYEDACMONITOR04_GlitchData : VitalGlitchDataType; variable DFETAP1MONITOR00_GlitchData : VitalGlitchDataType; variable DFETAP1MONITOR01_GlitchData : VitalGlitchDataType; variable DFETAP1MONITOR02_GlitchData : VitalGlitchDataType; variable DFETAP1MONITOR03_GlitchData : VitalGlitchDataType; variable DFETAP1MONITOR04_GlitchData : VitalGlitchDataType; variable DFETAP2MONITOR00_GlitchData : VitalGlitchDataType; variable DFETAP2MONITOR01_GlitchData : VitalGlitchDataType; variable DFETAP2MONITOR02_GlitchData : VitalGlitchDataType; variable DFETAP2MONITOR03_GlitchData : VitalGlitchDataType; variable DFETAP2MONITOR04_GlitchData : VitalGlitchDataType; variable DFETAP3MONITOR00_GlitchData : VitalGlitchDataType; variable DFETAP3MONITOR01_GlitchData : VitalGlitchDataType; variable DFETAP3MONITOR02_GlitchData : VitalGlitchDataType; variable DFETAP3MONITOR03_GlitchData : VitalGlitchDataType; variable DFETAP4MONITOR00_GlitchData : VitalGlitchDataType; variable DFETAP4MONITOR01_GlitchData : VitalGlitchDataType; variable DFETAP4MONITOR02_GlitchData : VitalGlitchDataType; variable DFETAP4MONITOR03_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR10_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR11_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR12_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR13_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR14_GlitchData : VitalGlitchDataType; variable DFECLKDLYADJMONITOR15_GlitchData : VitalGlitchDataType; variable DFEEYEDACMONITOR10_GlitchData : VitalGlitchDataType; variable DFEEYEDACMONITOR11_GlitchData : VitalGlitchDataType; variable DFEEYEDACMONITOR12_GlitchData : VitalGlitchDataType; variable DFEEYEDACMONITOR13_GlitchData : VitalGlitchDataType; variable DFEEYEDACMONITOR14_GlitchData : VitalGlitchDataType; variable DFETAP1MONITOR10_GlitchData : VitalGlitchDataType; variable DFETAP1MONITOR11_GlitchData : VitalGlitchDataType; variable DFETAP1MONITOR12_GlitchData : VitalGlitchDataType; variable DFETAP1MONITOR13_GlitchData : VitalGlitchDataType; variable DFETAP1MONITOR14_GlitchData : VitalGlitchDataType; variable DFETAP2MONITOR10_GlitchData : VitalGlitchDataType; variable DFETAP2MONITOR11_GlitchData : VitalGlitchDataType; variable DFETAP2MONITOR12_GlitchData : VitalGlitchDataType; variable DFETAP2MONITOR13_GlitchData : VitalGlitchDataType; variable DFETAP2MONITOR14_GlitchData : VitalGlitchDataType; variable DFETAP3MONITOR10_GlitchData : VitalGlitchDataType; variable DFETAP3MONITOR11_GlitchData : VitalGlitchDataType; variable DFETAP3MONITOR12_GlitchData : VitalGlitchDataType; variable DFETAP3MONITOR13_GlitchData : VitalGlitchDataType; variable DFETAP4MONITOR10_GlitchData : VitalGlitchDataType; variable DFETAP4MONITOR11_GlitchData : VitalGlitchDataType; variable DFETAP4MONITOR12_GlitchData : VitalGlitchDataType; variable DFETAP4MONITOR13_GlitchData : VitalGlitchDataType; variable DFESENSCAL00_GlitchData : VitalGlitchDataType; variable DFESENSCAL01_GlitchData : VitalGlitchDataType; variable DFESENSCAL02_GlitchData : VitalGlitchDataType; variable DFESENSCAL10_GlitchData : VitalGlitchDataType; variable DFESENSCAL11_GlitchData : VitalGlitchDataType; variable DFESENSCAL12_GlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => REFCLKOUT, GlitchData => REFCLKOUT_GlitchData, OutSignalName => "REFCLKOUT", OutTemp => REFCLKOUT_OUT, Paths => (0 => (CLKIN_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(0), GlitchData => RXDATA00_GlitchData, OutSignalName => "RXDATA0(0)", OutTemp => RXDATA0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(1), GlitchData => RXDATA01_GlitchData, OutSignalName => "RXDATA0(1)", OutTemp => RXDATA0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(2), GlitchData => RXDATA02_GlitchData, OutSignalName => "RXDATA0(2)", OutTemp => RXDATA0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(3), GlitchData => RXDATA03_GlitchData, OutSignalName => "RXDATA0(3)", OutTemp => RXDATA0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(4), GlitchData => RXDATA04_GlitchData, OutSignalName => "RXDATA0(4)", OutTemp => RXDATA0_OUT(4), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(5), GlitchData => RXDATA05_GlitchData, OutSignalName => "RXDATA0(5)", OutTemp => RXDATA0_OUT(5), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(6), GlitchData => RXDATA06_GlitchData, OutSignalName => "RXDATA0(6)", OutTemp => RXDATA0_OUT(6), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(7), GlitchData => RXDATA07_GlitchData, OutSignalName => "RXDATA0(7)", OutTemp => RXDATA0_OUT(7), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(8), GlitchData => RXDATA08_GlitchData, OutSignalName => "RXDATA0(8)", OutTemp => RXDATA0_OUT(8), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(9), GlitchData => RXDATA09_GlitchData, OutSignalName => "RXDATA0(9)", OutTemp => RXDATA0_OUT(9), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(10), GlitchData => RXDATA010_GlitchData, OutSignalName => "RXDATA0(10)", OutTemp => RXDATA0_OUT(10), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(11), GlitchData => RXDATA011_GlitchData, OutSignalName => "RXDATA0(11)", OutTemp => RXDATA0_OUT(11), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(12), GlitchData => RXDATA012_GlitchData, OutSignalName => "RXDATA0(12)", OutTemp => RXDATA0_OUT(12), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(13), GlitchData => RXDATA013_GlitchData, OutSignalName => "RXDATA0(13)", OutTemp => RXDATA0_OUT(13), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(14), GlitchData => RXDATA014_GlitchData, OutSignalName => "RXDATA0(14)", OutTemp => RXDATA0_OUT(14), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(15), GlitchData => RXDATA015_GlitchData, OutSignalName => "RXDATA0(15)", OutTemp => RXDATA0_OUT(15), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(16), GlitchData => RXDATA016_GlitchData, OutSignalName => "RXDATA0(16)", OutTemp => RXDATA0_OUT(16), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(17), GlitchData => RXDATA017_GlitchData, OutSignalName => "RXDATA0(17)", OutTemp => RXDATA0_OUT(17), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(18), GlitchData => RXDATA018_GlitchData, OutSignalName => "RXDATA0(18)", OutTemp => RXDATA0_OUT(18), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(19), GlitchData => RXDATA019_GlitchData, OutSignalName => "RXDATA0(19)", OutTemp => RXDATA0_OUT(19), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(20), GlitchData => RXDATA020_GlitchData, OutSignalName => "RXDATA0(20)", OutTemp => RXDATA0_OUT(20), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(21), GlitchData => RXDATA021_GlitchData, OutSignalName => "RXDATA0(21)", OutTemp => RXDATA0_OUT(21), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(22), GlitchData => RXDATA022_GlitchData, OutSignalName => "RXDATA0(22)", OutTemp => RXDATA0_OUT(22), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(23), GlitchData => RXDATA023_GlitchData, OutSignalName => "RXDATA0(23)", OutTemp => RXDATA0_OUT(23), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(24), GlitchData => RXDATA024_GlitchData, OutSignalName => "RXDATA0(24)", OutTemp => RXDATA0_OUT(24), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(25), GlitchData => RXDATA025_GlitchData, OutSignalName => "RXDATA0(25)", OutTemp => RXDATA0_OUT(25), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(26), GlitchData => RXDATA026_GlitchData, OutSignalName => "RXDATA0(26)", OutTemp => RXDATA0_OUT(26), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(27), GlitchData => RXDATA027_GlitchData, OutSignalName => "RXDATA0(27)", OutTemp => RXDATA0_OUT(27), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(28), GlitchData => RXDATA028_GlitchData, OutSignalName => "RXDATA0(28)", OutTemp => RXDATA0_OUT(28), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(29), GlitchData => RXDATA029_GlitchData, OutSignalName => "RXDATA0(29)", OutTemp => RXDATA0_OUT(29), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(30), GlitchData => RXDATA030_GlitchData, OutSignalName => "RXDATA0(30)", OutTemp => RXDATA0_OUT(30), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA0(31), GlitchData => RXDATA031_GlitchData, OutSignalName => "RXDATA0(31)", OutTemp => RXDATA0_OUT(31), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE0(0), GlitchData => RXNOTINTABLE00_GlitchData, OutSignalName => "RXNOTINTABLE0(0)", OutTemp => RXNOTINTABLE0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE0(1), GlitchData => RXNOTINTABLE01_GlitchData, OutSignalName => "RXNOTINTABLE0(1)", OutTemp => RXNOTINTABLE0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE0(2), GlitchData => RXNOTINTABLE02_GlitchData, OutSignalName => "RXNOTINTABLE0(2)", OutTemp => RXNOTINTABLE0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE0(3), GlitchData => RXNOTINTABLE03_GlitchData, OutSignalName => "RXNOTINTABLE0(3)", OutTemp => RXNOTINTABLE0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR0(0), GlitchData => RXDISPERR00_GlitchData, OutSignalName => "RXDISPERR0(0)", OutTemp => RXDISPERR0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR0(1), GlitchData => RXDISPERR01_GlitchData, OutSignalName => "RXDISPERR0(1)", OutTemp => RXDISPERR0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR0(2), GlitchData => RXDISPERR02_GlitchData, OutSignalName => "RXDISPERR0(2)", OutTemp => RXDISPERR0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR0(3), GlitchData => RXDISPERR03_GlitchData, OutSignalName => "RXDISPERR0(3)", OutTemp => RXDISPERR0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK0(0), GlitchData => RXCHARISK00_GlitchData, OutSignalName => "RXCHARISK0(0)", OutTemp => RXCHARISK0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK0(1), GlitchData => RXCHARISK01_GlitchData, OutSignalName => "RXCHARISK0(1)", OutTemp => RXCHARISK0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK0(2), GlitchData => RXCHARISK02_GlitchData, OutSignalName => "RXCHARISK0(2)", OutTemp => RXCHARISK0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK0(3), GlitchData => RXCHARISK03_GlitchData, OutSignalName => "RXCHARISK0(3)", OutTemp => RXCHARISK0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP0(0), GlitchData => RXRUNDISP00_GlitchData, OutSignalName => "RXRUNDISP0(0)", OutTemp => RXRUNDISP0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP0(1), GlitchData => RXRUNDISP01_GlitchData, OutSignalName => "RXRUNDISP0(1)", OutTemp => RXRUNDISP0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP0(2), GlitchData => RXRUNDISP02_GlitchData, OutSignalName => "RXRUNDISP0(2)", OutTemp => RXRUNDISP0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP0(3), GlitchData => RXRUNDISP03_GlitchData, OutSignalName => "RXRUNDISP0(3)", OutTemp => RXRUNDISP0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA0(0), GlitchData => RXCHARISCOMMA00_GlitchData, OutSignalName => "RXCHARISCOMMA0(0)", OutTemp => RXCHARISCOMMA0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA0(1), GlitchData => RXCHARISCOMMA01_GlitchData, OutSignalName => "RXCHARISCOMMA0(1)", OutTemp => RXCHARISCOMMA0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA0(2), GlitchData => RXCHARISCOMMA02_GlitchData, OutSignalName => "RXCHARISCOMMA0(2)", OutTemp => RXCHARISCOMMA0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA0(3), GlitchData => RXCHARISCOMMA03_GlitchData, OutSignalName => "RXCHARISCOMMA0(3)", OutTemp => RXCHARISCOMMA0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXVALID0, GlitchData => RXVALID0_GlitchData, OutSignalName => "RXVALID0", OutTemp => RXVALID0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(0), GlitchData => RXDATA10_GlitchData, OutSignalName => "RXDATA1(0)", OutTemp => RXDATA1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(1), GlitchData => RXDATA11_GlitchData, OutSignalName => "RXDATA1(1)", OutTemp => RXDATA1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(2), GlitchData => RXDATA12_GlitchData, OutSignalName => "RXDATA1(2)", OutTemp => RXDATA1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(3), GlitchData => RXDATA13_GlitchData, OutSignalName => "RXDATA1(3)", OutTemp => RXDATA1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(4), GlitchData => RXDATA14_GlitchData, OutSignalName => "RXDATA1(4)", OutTemp => RXDATA1_OUT(4), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(5), GlitchData => RXDATA15_GlitchData, OutSignalName => "RXDATA1(5)", OutTemp => RXDATA1_OUT(5), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(6), GlitchData => RXDATA16_GlitchData, OutSignalName => "RXDATA1(6)", OutTemp => RXDATA1_OUT(6), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(7), GlitchData => RXDATA17_GlitchData, OutSignalName => "RXDATA1(7)", OutTemp => RXDATA1_OUT(7), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(8), GlitchData => RXDATA18_GlitchData, OutSignalName => "RXDATA1(8)", OutTemp => RXDATA1_OUT(8), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(9), GlitchData => RXDATA19_GlitchData, OutSignalName => "RXDATA1(9)", OutTemp => RXDATA1_OUT(9), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(10), GlitchData => RXDATA110_GlitchData, OutSignalName => "RXDATA1(10)", OutTemp => RXDATA1_OUT(10), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(11), GlitchData => RXDATA111_GlitchData, OutSignalName => "RXDATA1(11)", OutTemp => RXDATA1_OUT(11), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(12), GlitchData => RXDATA112_GlitchData, OutSignalName => "RXDATA1(12)", OutTemp => RXDATA1_OUT(12), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(13), GlitchData => RXDATA113_GlitchData, OutSignalName => "RXDATA1(13)", OutTemp => RXDATA1_OUT(13), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(14), GlitchData => RXDATA114_GlitchData, OutSignalName => "RXDATA1(14)", OutTemp => RXDATA1_OUT(14), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(15), GlitchData => RXDATA115_GlitchData, OutSignalName => "RXDATA1(15)", OutTemp => RXDATA1_OUT(15), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(16), GlitchData => RXDATA116_GlitchData, OutSignalName => "RXDATA1(16)", OutTemp => RXDATA1_OUT(16), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(17), GlitchData => RXDATA117_GlitchData, OutSignalName => "RXDATA1(17)", OutTemp => RXDATA1_OUT(17), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(18), GlitchData => RXDATA118_GlitchData, OutSignalName => "RXDATA1(18)", OutTemp => RXDATA1_OUT(18), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(19), GlitchData => RXDATA119_GlitchData, OutSignalName => "RXDATA1(19)", OutTemp => RXDATA1_OUT(19), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(20), GlitchData => RXDATA120_GlitchData, OutSignalName => "RXDATA1(20)", OutTemp => RXDATA1_OUT(20), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(21), GlitchData => RXDATA121_GlitchData, OutSignalName => "RXDATA1(21)", OutTemp => RXDATA1_OUT(21), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(22), GlitchData => RXDATA122_GlitchData, OutSignalName => "RXDATA1(22)", OutTemp => RXDATA1_OUT(22), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(23), GlitchData => RXDATA123_GlitchData, OutSignalName => "RXDATA1(23)", OutTemp => RXDATA1_OUT(23), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(24), GlitchData => RXDATA124_GlitchData, OutSignalName => "RXDATA1(24)", OutTemp => RXDATA1_OUT(24), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(25), GlitchData => RXDATA125_GlitchData, OutSignalName => "RXDATA1(25)", OutTemp => RXDATA1_OUT(25), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(26), GlitchData => RXDATA126_GlitchData, OutSignalName => "RXDATA1(26)", OutTemp => RXDATA1_OUT(26), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(27), GlitchData => RXDATA127_GlitchData, OutSignalName => "RXDATA1(27)", OutTemp => RXDATA1_OUT(27), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(28), GlitchData => RXDATA128_GlitchData, OutSignalName => "RXDATA1(28)", OutTemp => RXDATA1_OUT(28), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(29), GlitchData => RXDATA129_GlitchData, OutSignalName => "RXDATA1(29)", OutTemp => RXDATA1_OUT(29), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(30), GlitchData => RXDATA130_GlitchData, OutSignalName => "RXDATA1(30)", OutTemp => RXDATA1_OUT(30), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATA1(31), GlitchData => RXDATA131_GlitchData, OutSignalName => "RXDATA1(31)", OutTemp => RXDATA1_OUT(31), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE1(0), GlitchData => RXNOTINTABLE10_GlitchData, OutSignalName => "RXNOTINTABLE1(0)", OutTemp => RXNOTINTABLE1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE1(1), GlitchData => RXNOTINTABLE11_GlitchData, OutSignalName => "RXNOTINTABLE1(1)", OutTemp => RXNOTINTABLE1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE1(2), GlitchData => RXNOTINTABLE12_GlitchData, OutSignalName => "RXNOTINTABLE1(2)", OutTemp => RXNOTINTABLE1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXNOTINTABLE1(3), GlitchData => RXNOTINTABLE13_GlitchData, OutSignalName => "RXNOTINTABLE1(3)", OutTemp => RXNOTINTABLE1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR1(0), GlitchData => RXDISPERR10_GlitchData, OutSignalName => "RXDISPERR1(0)", OutTemp => RXDISPERR1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR1(1), GlitchData => RXDISPERR11_GlitchData, OutSignalName => "RXDISPERR1(1)", OutTemp => RXDISPERR1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR1(2), GlitchData => RXDISPERR12_GlitchData, OutSignalName => "RXDISPERR1(2)", OutTemp => RXDISPERR1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDISPERR1(3), GlitchData => RXDISPERR13_GlitchData, OutSignalName => "RXDISPERR1(3)", OutTemp => RXDISPERR1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK1(0), GlitchData => RXCHARISK10_GlitchData, OutSignalName => "RXCHARISK1(0)", OutTemp => RXCHARISK1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK1(1), GlitchData => RXCHARISK11_GlitchData, OutSignalName => "RXCHARISK1(1)", OutTemp => RXCHARISK1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK1(2), GlitchData => RXCHARISK12_GlitchData, OutSignalName => "RXCHARISK1(2)", OutTemp => RXCHARISK1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISK1(3), GlitchData => RXCHARISK13_GlitchData, OutSignalName => "RXCHARISK1(3)", OutTemp => RXCHARISK1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP1(0), GlitchData => RXRUNDISP10_GlitchData, OutSignalName => "RXRUNDISP1(0)", OutTemp => RXRUNDISP1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP1(1), GlitchData => RXRUNDISP11_GlitchData, OutSignalName => "RXRUNDISP1(1)", OutTemp => RXRUNDISP1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP1(2), GlitchData => RXRUNDISP12_GlitchData, OutSignalName => "RXRUNDISP1(2)", OutTemp => RXRUNDISP1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXRUNDISP1(3), GlitchData => RXRUNDISP13_GlitchData, OutSignalName => "RXRUNDISP1(3)", OutTemp => RXRUNDISP1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA1(0), GlitchData => RXCHARISCOMMA10_GlitchData, OutSignalName => "RXCHARISCOMMA1(0)", OutTemp => RXCHARISCOMMA1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA1(1), GlitchData => RXCHARISCOMMA11_GlitchData, OutSignalName => "RXCHARISCOMMA1(1)", OutTemp => RXCHARISCOMMA1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA1(2), GlitchData => RXCHARISCOMMA12_GlitchData, OutSignalName => "RXCHARISCOMMA1(2)", OutTemp => RXCHARISCOMMA1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHARISCOMMA1(3), GlitchData => RXCHARISCOMMA13_GlitchData, OutSignalName => "RXCHARISCOMMA1(3)", OutTemp => RXCHARISCOMMA1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXVALID1, GlitchData => RXVALID1_GlitchData, OutSignalName => "RXVALID1", OutTemp => RXVALID1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR0(0), GlitchData => TXKERR00_GlitchData, OutSignalName => "TXKERR0(0)", OutTemp => TXKERR0_OUT(0), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR0(1), GlitchData => TXKERR01_GlitchData, OutSignalName => "TXKERR0(1)", OutTemp => TXKERR0_OUT(1), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR0(2), GlitchData => TXKERR02_GlitchData, OutSignalName => "TXKERR0(2)", OutTemp => TXKERR0_OUT(2), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR0(3), GlitchData => TXKERR03_GlitchData, OutSignalName => "TXKERR0(3)", OutTemp => TXKERR0_OUT(3), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP0(0), GlitchData => TXRUNDISP00_GlitchData, OutSignalName => "TXRUNDISP0(0)", OutTemp => TXRUNDISP0_OUT(0), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP0(1), GlitchData => TXRUNDISP01_GlitchData, OutSignalName => "TXRUNDISP0(1)", OutTemp => TXRUNDISP0_OUT(1), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP0(2), GlitchData => TXRUNDISP02_GlitchData, OutSignalName => "TXRUNDISP0(2)", OutTemp => TXRUNDISP0_OUT(2), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP0(3), GlitchData => TXRUNDISP03_GlitchData, OutSignalName => "TXRUNDISP0(3)", OutTemp => TXRUNDISP0_OUT(3), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXBUFSTATUS0(0), GlitchData => TXBUFSTATUS00_GlitchData, OutSignalName => "TXBUFSTATUS0(0)", OutTemp => TXBUFSTATUS0_OUT(0), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXBUFSTATUS0(1), GlitchData => TXBUFSTATUS01_GlitchData, OutSignalName => "TXBUFSTATUS0(1)", OutTemp => TXBUFSTATUS0_OUT(1), Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR1(0), GlitchData => TXKERR10_GlitchData, OutSignalName => "TXKERR1(0)", OutTemp => TXKERR1_OUT(0), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR1(1), GlitchData => TXKERR11_GlitchData, OutSignalName => "TXKERR1(1)", OutTemp => TXKERR1_OUT(1), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR1(2), GlitchData => TXKERR12_GlitchData, OutSignalName => "TXKERR1(2)", OutTemp => TXKERR1_OUT(2), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXKERR1(3), GlitchData => TXKERR13_GlitchData, OutSignalName => "TXKERR1(3)", OutTemp => TXKERR1_OUT(3), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP1(0), GlitchData => TXRUNDISP10_GlitchData, OutSignalName => "TXRUNDISP1(0)", OutTemp => TXRUNDISP1_OUT(0), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP1(1), GlitchData => TXRUNDISP11_GlitchData, OutSignalName => "TXRUNDISP1(1)", OutTemp => TXRUNDISP1_OUT(1), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP1(2), GlitchData => TXRUNDISP12_GlitchData, OutSignalName => "TXRUNDISP1(2)", OutTemp => TXRUNDISP1_OUT(2), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXRUNDISP1(3), GlitchData => TXRUNDISP13_GlitchData, OutSignalName => "TXRUNDISP1(3)", OutTemp => TXRUNDISP1_OUT(3), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXBUFSTATUS1(0), GlitchData => TXBUFSTATUS10_GlitchData, OutSignalName => "TXBUFSTATUS1(0)", OutTemp => TXBUFSTATUS1_OUT(0), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXBUFSTATUS1(1), GlitchData => TXBUFSTATUS11_GlitchData, OutSignalName => "TXBUFSTATUS1(1)", OutTemp => TXBUFSTATUS1_OUT(1), Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCOMMADET0, GlitchData => RXCOMMADET0_GlitchData, OutSignalName => "RXCOMMADET0", OutTemp => RXCOMMADET0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBYTEREALIGN0, GlitchData => RXBYTEREALIGN0_GlitchData, OutSignalName => "RXBYTEREALIGN0", OutTemp => RXBYTEREALIGN0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBYTEISALIGNED0, GlitchData => RXBYTEISALIGNED0_GlitchData, OutSignalName => "RXBYTEISALIGNED0", OutTemp => RXBYTEISALIGNED0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC0(0), GlitchData => RXLOSSOFSYNC00_GlitchData, OutSignalName => "RXLOSSOFSYNC0(0)", OutTemp => RXLOSSOFSYNC0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC0(1), GlitchData => RXLOSSOFSYNC01_GlitchData, OutSignalName => "RXLOSSOFSYNC0(1)", OutTemp => RXLOSSOFSYNC0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO0(0), GlitchData => RXCHBONDO00_GlitchData, OutSignalName => "RXCHBONDO0(0)", OutTemp => RXCHBONDO0_OUT(0), Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO0(1), GlitchData => RXCHBONDO01_GlitchData, OutSignalName => "RXCHBONDO0(1)", OutTemp => RXCHBONDO0_OUT(1), Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO0(2), GlitchData => RXCHBONDO02_GlitchData, OutSignalName => "RXCHBONDO0(2)", OutTemp => RXCHBONDO0_OUT(2), Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO0(3), GlitchData => RXCHBONDO03_GlitchData, OutSignalName => "RXCHBONDO0(3)", OutTemp => RXCHBONDO0_OUT(3), Paths => (0 => (RXUSRCLK0_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANBONDSEQ0, GlitchData => RXCHANBONDSEQ0_GlitchData, OutSignalName => "RXCHANBONDSEQ0", OutTemp => RXCHANBONDSEQ0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANREALIGN0, GlitchData => RXCHANREALIGN0_GlitchData, OutSignalName => "RXCHANREALIGN0", OutTemp => RXCHANREALIGN0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANISALIGNED0, GlitchData => RXCHANISALIGNED0_GlitchData, OutSignalName => "RXCHANISALIGNED0", OutTemp => RXCHANISALIGNED0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS0(0), GlitchData => RXBUFSTATUS00_GlitchData, OutSignalName => "RXBUFSTATUS0(0)", OutTemp => RXBUFSTATUS0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS0(1), GlitchData => RXBUFSTATUS01_GlitchData, OutSignalName => "RXBUFSTATUS0(1)", OutTemp => RXBUFSTATUS0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS0(2), GlitchData => RXBUFSTATUS02_GlitchData, OutSignalName => "RXBUFSTATUS0(2)", OutTemp => RXBUFSTATUS0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCOMMADET1, GlitchData => RXCOMMADET1_GlitchData, OutSignalName => "RXCOMMADET1", OutTemp => RXCOMMADET1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBYTEREALIGN1, GlitchData => RXBYTEREALIGN1_GlitchData, OutSignalName => "RXBYTEREALIGN1", OutTemp => RXBYTEREALIGN1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBYTEISALIGNED1, GlitchData => RXBYTEISALIGNED1_GlitchData, OutSignalName => "RXBYTEISALIGNED1", OutTemp => RXBYTEISALIGNED1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC1(0), GlitchData => RXLOSSOFSYNC10_GlitchData, OutSignalName => "RXLOSSOFSYNC1(0)", OutTemp => RXLOSSOFSYNC1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXLOSSOFSYNC1(1), GlitchData => RXLOSSOFSYNC11_GlitchData, OutSignalName => "RXLOSSOFSYNC1(1)", OutTemp => RXLOSSOFSYNC1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO1(0), GlitchData => RXCHBONDO10_GlitchData, OutSignalName => "RXCHBONDO1(0)", OutTemp => RXCHBONDO1_OUT(0), Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO1(1), GlitchData => RXCHBONDO11_GlitchData, OutSignalName => "RXCHBONDO1(1)", OutTemp => RXCHBONDO1_OUT(1), Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO1(2), GlitchData => RXCHBONDO12_GlitchData, OutSignalName => "RXCHBONDO1(2)", OutTemp => RXCHBONDO1_OUT(2), Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHBONDO1(3), GlitchData => RXCHBONDO13_GlitchData, OutSignalName => "RXCHBONDO1(3)", OutTemp => RXCHBONDO1_OUT(3), Paths => (0 => (RXUSRCLK1_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANBONDSEQ1, GlitchData => RXCHANBONDSEQ1_GlitchData, OutSignalName => "RXCHANBONDSEQ1", OutTemp => RXCHANBONDSEQ1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANREALIGN1, GlitchData => RXCHANREALIGN1_GlitchData, OutSignalName => "RXCHANREALIGN1", OutTemp => RXCHANREALIGN1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCHANISALIGNED1, GlitchData => RXCHANISALIGNED1_GlitchData, OutSignalName => "RXCHANISALIGNED1", OutTemp => RXCHANISALIGNED1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS1(0), GlitchData => RXBUFSTATUS10_GlitchData, OutSignalName => "RXBUFSTATUS1(0)", OutTemp => RXBUFSTATUS1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS1(1), GlitchData => RXBUFSTATUS11_GlitchData, OutSignalName => "RXBUFSTATUS1(1)", OutTemp => RXBUFSTATUS1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXBUFSTATUS1(2), GlitchData => RXBUFSTATUS12_GlitchData, OutSignalName => "RXBUFSTATUS1(2)", OutTemp => RXBUFSTATUS1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PHYSTATUS0, GlitchData => PHYSTATUS0_GlitchData, OutSignalName => "PHYSTATUS0", OutTemp => PHYSTATUS0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PHYSTATUS1, GlitchData => PHYSTATUS1_GlitchData, OutSignalName => "PHYSTATUS1", OutTemp => PHYSTATUS1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS0(0), GlitchData => RXSTATUS00_GlitchData, OutSignalName => "RXSTATUS0(0)", OutTemp => RXSTATUS0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS0(1), GlitchData => RXSTATUS01_GlitchData, OutSignalName => "RXSTATUS0(1)", OutTemp => RXSTATUS0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS0(2), GlitchData => RXSTATUS02_GlitchData, OutSignalName => "RXSTATUS0(2)", OutTemp => RXSTATUS0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT0(0), GlitchData => RXCLKCORCNT00_GlitchData, OutSignalName => "RXCLKCORCNT0(0)", OutTemp => RXCLKCORCNT0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT0(1), GlitchData => RXCLKCORCNT01_GlitchData, OutSignalName => "RXCLKCORCNT0(1)", OutTemp => RXCLKCORCNT0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT0(2), GlitchData => RXCLKCORCNT02_GlitchData, OutSignalName => "RXCLKCORCNT0(2)", OutTemp => RXCLKCORCNT0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS1(0), GlitchData => RXSTATUS10_GlitchData, OutSignalName => "RXSTATUS1(0)", OutTemp => RXSTATUS1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS1(1), GlitchData => RXSTATUS11_GlitchData, OutSignalName => "RXSTATUS1(1)", OutTemp => RXSTATUS1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTATUS1(2), GlitchData => RXSTATUS12_GlitchData, OutSignalName => "RXSTATUS1(2)", OutTemp => RXSTATUS1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT1(0), GlitchData => RXCLKCORCNT10_GlitchData, OutSignalName => "RXCLKCORCNT1(0)", OutTemp => RXCLKCORCNT1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT1(1), GlitchData => RXCLKCORCNT11_GlitchData, OutSignalName => "RXCLKCORCNT1(1)", OutTemp => RXCLKCORCNT1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXCLKCORCNT1(2), GlitchData => RXCLKCORCNT12_GlitchData, OutSignalName => "RXCLKCORCNT1(2)", OutTemp => RXCLKCORCNT1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXPRBSERR0, GlitchData => RXPRBSERR0_GlitchData, OutSignalName => "RXPRBSERR0", OutTemp => RXPRBSERR0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXPRBSERR1, GlitchData => RXPRBSERR1_GlitchData, OutSignalName => "RXPRBSERR1", OutTemp => RXPRBSERR1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(0), GlitchData => DO0_GlitchData, OutSignalName => "DO(0)", OutTemp => DO_OUT(0), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(1), GlitchData => DO1_GlitchData, OutSignalName => "DO(1)", OutTemp => DO_OUT(1), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(2), GlitchData => DO2_GlitchData, OutSignalName => "DO(2)", OutTemp => DO_OUT(2), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(3), GlitchData => DO3_GlitchData, OutSignalName => "DO(3)", OutTemp => DO_OUT(3), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(4), GlitchData => DO4_GlitchData, OutSignalName => "DO(4)", OutTemp => DO_OUT(4), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(5), GlitchData => DO5_GlitchData, OutSignalName => "DO(5)", OutTemp => DO_OUT(5), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(6), GlitchData => DO6_GlitchData, OutSignalName => "DO(6)", OutTemp => DO_OUT(6), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(7), GlitchData => DO7_GlitchData, OutSignalName => "DO(7)", OutTemp => DO_OUT(7), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(8), GlitchData => DO8_GlitchData, OutSignalName => "DO(8)", OutTemp => DO_OUT(8), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(9), GlitchData => DO9_GlitchData, OutSignalName => "DO(9)", OutTemp => DO_OUT(9), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(10), GlitchData => DO10_GlitchData, OutSignalName => "DO(10)", OutTemp => DO_OUT(10), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(11), GlitchData => DO11_GlitchData, OutSignalName => "DO(11)", OutTemp => DO_OUT(11), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(12), GlitchData => DO12_GlitchData, OutSignalName => "DO(12)", OutTemp => DO_OUT(12), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(13), GlitchData => DO13_GlitchData, OutSignalName => "DO(13)", OutTemp => DO_OUT(13), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(14), GlitchData => DO14_GlitchData, OutSignalName => "DO(14)", OutTemp => DO_OUT(14), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DO(15), GlitchData => DO15_GlitchData, OutSignalName => "DO(15)", OutTemp => DO_OUT(15), Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DRDY, GlitchData => DRDY_GlitchData, OutSignalName => "DRDY", OutTemp => DRDY_OUT, Paths => (0 => (DCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXOVERSAMPLEERR0, GlitchData => RXOVERSAMPLEERR0_GlitchData, OutSignalName => "RXOVERSAMPLEERR0", OutTemp => RXOVERSAMPLEERR0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXOVERSAMPLEERR1, GlitchData => RXOVERSAMPLEERR1_GlitchData, OutSignalName => "RXOVERSAMPLEERR1", OutTemp => RXOVERSAMPLEERR1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXGEARBOXREADY0, GlitchData => TXGEARBOXREADY0_GlitchData, OutSignalName => "TXGEARBOXREADY0", OutTemp => TXGEARBOXREADY0_OUT, Paths => (0 => (TXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXHEADER0(0), GlitchData => RXHEADER00_GlitchData, OutSignalName => "RXHEADER0(0)", OutTemp => RXHEADER0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXHEADER0(1), GlitchData => RXHEADER01_GlitchData, OutSignalName => "RXHEADER0(1)", OutTemp => RXHEADER0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXHEADER0(2), GlitchData => RXHEADER02_GlitchData, OutSignalName => "RXHEADER0(2)", OutTemp => RXHEADER0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXHEADERVALID0, GlitchData => RXHEADERVALID0_GlitchData, OutSignalName => "RXHEADERVALID0", OutTemp => RXHEADERVALID0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATAVALID0, GlitchData => RXDATAVALID0_GlitchData, OutSignalName => "RXDATAVALID0", OutTemp => RXDATAVALID0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTARTOFSEQ0, GlitchData => RXSTARTOFSEQ0_GlitchData, OutSignalName => "RXSTARTOFSEQ0", OutTemp => RXSTARTOFSEQ0_OUT, Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => TXGEARBOXREADY1, GlitchData => TXGEARBOXREADY1_GlitchData, OutSignalName => "TXGEARBOXREADY1", OutTemp => TXGEARBOXREADY1_OUT, Paths => (0 => (TXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXHEADER1(0), GlitchData => RXHEADER10_GlitchData, OutSignalName => "RXHEADER1(0)", OutTemp => RXHEADER1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXHEADER1(1), GlitchData => RXHEADER11_GlitchData, OutSignalName => "RXHEADER1(1)", OutTemp => RXHEADER1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXHEADER1(2), GlitchData => RXHEADER12_GlitchData, OutSignalName => "RXHEADER1(2)", OutTemp => RXHEADER1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXHEADERVALID1, GlitchData => RXHEADERVALID1_GlitchData, OutSignalName => "RXHEADERVALID1", OutTemp => RXHEADERVALID1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXDATAVALID1, GlitchData => RXDATAVALID1_GlitchData, OutSignalName => "RXDATAVALID1", OutTemp => RXDATAVALID1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => RXSTARTOFSEQ1, GlitchData => RXSTARTOFSEQ1_GlitchData, OutSignalName => "RXSTARTOFSEQ1", OutTemp => RXSTARTOFSEQ1_OUT, Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR0(0), GlitchData => DFECLKDLYADJMONITOR00_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR0(0)", OutTemp => DFECLKDLYADJMONITOR0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR0(1), GlitchData => DFECLKDLYADJMONITOR01_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR0(1)", OutTemp => DFECLKDLYADJMONITOR0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR0(2), GlitchData => DFECLKDLYADJMONITOR02_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR0(2)", OutTemp => DFECLKDLYADJMONITOR0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR0(3), GlitchData => DFECLKDLYADJMONITOR03_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR0(3)", OutTemp => DFECLKDLYADJMONITOR0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR0(4), GlitchData => DFECLKDLYADJMONITOR04_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR0(4)", OutTemp => DFECLKDLYADJMONITOR0_OUT(4), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR0(5), GlitchData => DFECLKDLYADJMONITOR05_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR0(5)", OutTemp => DFECLKDLYADJMONITOR0_OUT(5), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFEEYEDACMONITOR0(0), GlitchData => DFEEYEDACMONITOR00_GlitchData, OutSignalName => "DFEEYEDACMONITOR0(0)", OutTemp => DFEEYEDACMONITOR0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFEEYEDACMONITOR0(1), GlitchData => DFEEYEDACMONITOR01_GlitchData, OutSignalName => "DFEEYEDACMONITOR0(1)", OutTemp => DFEEYEDACMONITOR0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFEEYEDACMONITOR0(2), GlitchData => DFEEYEDACMONITOR02_GlitchData, OutSignalName => "DFEEYEDACMONITOR0(2)", OutTemp => DFEEYEDACMONITOR0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFEEYEDACMONITOR0(3), GlitchData => DFEEYEDACMONITOR03_GlitchData, OutSignalName => "DFEEYEDACMONITOR0(3)", OutTemp => DFEEYEDACMONITOR0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFEEYEDACMONITOR0(4), GlitchData => DFEEYEDACMONITOR04_GlitchData, OutSignalName => "DFEEYEDACMONITOR0(4)", OutTemp => DFEEYEDACMONITOR0_OUT(4), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP1MONITOR0(0), GlitchData => DFETAP1MONITOR00_GlitchData, OutSignalName => "DFETAP1MONITOR0(0)", OutTemp => DFETAP1MONITOR0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP1MONITOR0(1), GlitchData => DFETAP1MONITOR01_GlitchData, OutSignalName => "DFETAP1MONITOR0(1)", OutTemp => DFETAP1MONITOR0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP1MONITOR0(2), GlitchData => DFETAP1MONITOR02_GlitchData, OutSignalName => "DFETAP1MONITOR0(2)", OutTemp => DFETAP1MONITOR0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP1MONITOR0(3), GlitchData => DFETAP1MONITOR03_GlitchData, OutSignalName => "DFETAP1MONITOR0(3)", OutTemp => DFETAP1MONITOR0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP1MONITOR0(4), GlitchData => DFETAP1MONITOR04_GlitchData, OutSignalName => "DFETAP1MONITOR0(4)", OutTemp => DFETAP1MONITOR0_OUT(4), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP2MONITOR0(0), GlitchData => DFETAP2MONITOR00_GlitchData, OutSignalName => "DFETAP2MONITOR0(0)", OutTemp => DFETAP2MONITOR0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP2MONITOR0(1), GlitchData => DFETAP2MONITOR01_GlitchData, OutSignalName => "DFETAP2MONITOR0(1)", OutTemp => DFETAP2MONITOR0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP2MONITOR0(2), GlitchData => DFETAP2MONITOR02_GlitchData, OutSignalName => "DFETAP2MONITOR0(2)", OutTemp => DFETAP2MONITOR0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP2MONITOR0(3), GlitchData => DFETAP2MONITOR03_GlitchData, OutSignalName => "DFETAP2MONITOR0(3)", OutTemp => DFETAP2MONITOR0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP2MONITOR0(4), GlitchData => DFETAP2MONITOR04_GlitchData, OutSignalName => "DFETAP2MONITOR0(4)", OutTemp => DFETAP2MONITOR0_OUT(4), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP3MONITOR0(0), GlitchData => DFETAP3MONITOR00_GlitchData, OutSignalName => "DFETAP3MONITOR0(0)", OutTemp => DFETAP3MONITOR0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP3MONITOR0(1), GlitchData => DFETAP3MONITOR01_GlitchData, OutSignalName => "DFETAP3MONITOR0(1)", OutTemp => DFETAP3MONITOR0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP3MONITOR0(2), GlitchData => DFETAP3MONITOR02_GlitchData, OutSignalName => "DFETAP3MONITOR0(2)", OutTemp => DFETAP3MONITOR0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP3MONITOR0(3), GlitchData => DFETAP3MONITOR03_GlitchData, OutSignalName => "DFETAP3MONITOR0(3)", OutTemp => DFETAP3MONITOR0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP4MONITOR0(0), GlitchData => DFETAP4MONITOR00_GlitchData, OutSignalName => "DFETAP4MONITOR0(0)", OutTemp => DFETAP4MONITOR0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP4MONITOR0(1), GlitchData => DFETAP4MONITOR01_GlitchData, OutSignalName => "DFETAP4MONITOR0(1)", OutTemp => DFETAP4MONITOR0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP4MONITOR0(2), GlitchData => DFETAP4MONITOR02_GlitchData, OutSignalName => "DFETAP4MONITOR0(2)", OutTemp => DFETAP4MONITOR0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP4MONITOR0(3), GlitchData => DFETAP4MONITOR03_GlitchData, OutSignalName => "DFETAP4MONITOR0(3)", OutTemp => DFETAP4MONITOR0_OUT(3), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR1(0), GlitchData => DFECLKDLYADJMONITOR10_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR1(0)", OutTemp => DFECLKDLYADJMONITOR1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR1(1), GlitchData => DFECLKDLYADJMONITOR11_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR1(1)", OutTemp => DFECLKDLYADJMONITOR1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR1(2), GlitchData => DFECLKDLYADJMONITOR12_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR1(2)", OutTemp => DFECLKDLYADJMONITOR1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR1(3), GlitchData => DFECLKDLYADJMONITOR13_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR1(3)", OutTemp => DFECLKDLYADJMONITOR1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR1(4), GlitchData => DFECLKDLYADJMONITOR14_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR1(4)", OutTemp => DFECLKDLYADJMONITOR1_OUT(4), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFECLKDLYADJMONITOR1(5), GlitchData => DFECLKDLYADJMONITOR15_GlitchData, OutSignalName => "DFECLKDLYADJMONITOR1(5)", OutTemp => DFECLKDLYADJMONITOR1_OUT(5), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFEEYEDACMONITOR1(0), GlitchData => DFEEYEDACMONITOR10_GlitchData, OutSignalName => "DFEEYEDACMONITOR1(0)", OutTemp => DFEEYEDACMONITOR1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFEEYEDACMONITOR1(1), GlitchData => DFEEYEDACMONITOR11_GlitchData, OutSignalName => "DFEEYEDACMONITOR1(1)", OutTemp => DFEEYEDACMONITOR1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFEEYEDACMONITOR1(2), GlitchData => DFEEYEDACMONITOR12_GlitchData, OutSignalName => "DFEEYEDACMONITOR1(2)", OutTemp => DFEEYEDACMONITOR1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFEEYEDACMONITOR1(3), GlitchData => DFEEYEDACMONITOR13_GlitchData, OutSignalName => "DFEEYEDACMONITOR1(3)", OutTemp => DFEEYEDACMONITOR1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFEEYEDACMONITOR1(4), GlitchData => DFEEYEDACMONITOR14_GlitchData, OutSignalName => "DFEEYEDACMONITOR1(4)", OutTemp => DFEEYEDACMONITOR1_OUT(4), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP1MONITOR1(0), GlitchData => DFETAP1MONITOR10_GlitchData, OutSignalName => "DFETAP1MONITOR1(0)", OutTemp => DFETAP1MONITOR1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP1MONITOR1(1), GlitchData => DFETAP1MONITOR11_GlitchData, OutSignalName => "DFETAP1MONITOR1(1)", OutTemp => DFETAP1MONITOR1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP1MONITOR1(2), GlitchData => DFETAP1MONITOR12_GlitchData, OutSignalName => "DFETAP1MONITOR1(2)", OutTemp => DFETAP1MONITOR1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP1MONITOR1(3), GlitchData => DFETAP1MONITOR13_GlitchData, OutSignalName => "DFETAP1MONITOR1(3)", OutTemp => DFETAP1MONITOR1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP1MONITOR1(4), GlitchData => DFETAP1MONITOR14_GlitchData, OutSignalName => "DFETAP1MONITOR1(4)", OutTemp => DFETAP1MONITOR1_OUT(4), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP2MONITOR1(0), GlitchData => DFETAP2MONITOR10_GlitchData, OutSignalName => "DFETAP2MONITOR1(0)", OutTemp => DFETAP2MONITOR1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP2MONITOR1(1), GlitchData => DFETAP2MONITOR11_GlitchData, OutSignalName => "DFETAP2MONITOR1(1)", OutTemp => DFETAP2MONITOR1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP2MONITOR1(2), GlitchData => DFETAP2MONITOR12_GlitchData, OutSignalName => "DFETAP2MONITOR1(2)", OutTemp => DFETAP2MONITOR1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP2MONITOR1(3), GlitchData => DFETAP2MONITOR13_GlitchData, OutSignalName => "DFETAP2MONITOR1(3)", OutTemp => DFETAP2MONITOR1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP2MONITOR1(4), GlitchData => DFETAP2MONITOR14_GlitchData, OutSignalName => "DFETAP2MONITOR1(4)", OutTemp => DFETAP2MONITOR1_OUT(4), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP3MONITOR1(0), GlitchData => DFETAP3MONITOR10_GlitchData, OutSignalName => "DFETAP3MONITOR1(0)", OutTemp => DFETAP3MONITOR1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP3MONITOR1(1), GlitchData => DFETAP3MONITOR11_GlitchData, OutSignalName => "DFETAP3MONITOR1(1)", OutTemp => DFETAP3MONITOR1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP3MONITOR1(2), GlitchData => DFETAP3MONITOR12_GlitchData, OutSignalName => "DFETAP3MONITOR1(2)", OutTemp => DFETAP3MONITOR1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP3MONITOR1(3), GlitchData => DFETAP3MONITOR13_GlitchData, OutSignalName => "DFETAP3MONITOR1(3)", OutTemp => DFETAP3MONITOR1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP4MONITOR1(0), GlitchData => DFETAP4MONITOR10_GlitchData, OutSignalName => "DFETAP4MONITOR1(0)", OutTemp => DFETAP4MONITOR1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP4MONITOR1(1), GlitchData => DFETAP4MONITOR11_GlitchData, OutSignalName => "DFETAP4MONITOR1(1)", OutTemp => DFETAP4MONITOR1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP4MONITOR1(2), GlitchData => DFETAP4MONITOR12_GlitchData, OutSignalName => "DFETAP4MONITOR1(2)", OutTemp => DFETAP4MONITOR1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFETAP4MONITOR1(3), GlitchData => DFETAP4MONITOR13_GlitchData, OutSignalName => "DFETAP4MONITOR1(3)", OutTemp => DFETAP4MONITOR1_OUT(3), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFESENSCAL0(0), GlitchData => DFESENSCAL00_GlitchData, OutSignalName => "DFESENSCAL0(0)", OutTemp => DFESENSCAL0_OUT(0), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFESENSCAL0(1), GlitchData => DFESENSCAL01_GlitchData, OutSignalName => "DFESENSCAL0(1)", OutTemp => DFESENSCAL0_OUT(1), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFESENSCAL0(2), GlitchData => DFESENSCAL02_GlitchData, OutSignalName => "DFESENSCAL0(2)", OutTemp => DFESENSCAL0_OUT(2), Paths => (0 => (RXUSRCLK20_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFESENSCAL1(0), GlitchData => DFESENSCAL10_GlitchData, OutSignalName => "DFESENSCAL1(0)", OutTemp => DFESENSCAL1_OUT(0), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFESENSCAL1(1), GlitchData => DFESENSCAL11_GlitchData, OutSignalName => "DFESENSCAL1(1)", OutTemp => DFESENSCAL1_OUT(1), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DFESENSCAL1(2), GlitchData => DFESENSCAL12_GlitchData, OutSignalName => "DFESENSCAL1(2)", OutTemp => DFESENSCAL1_OUT(2), Paths => (0 => (RXUSRCLK21_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, Xon => false, MsgOn => false, MsgSeverity => WARNING ); wait on DFECLKDLYADJMONITOR0_out, DFECLKDLYADJMONITOR1_out, DFEEYEDACMONITOR0_out, DFEEYEDACMONITOR1_out, DFESENSCAL0_out, DFESENSCAL1_out, DFETAP1MONITOR0_out, DFETAP1MONITOR1_out, DFETAP2MONITOR0_out, DFETAP2MONITOR1_out, DFETAP3MONITOR0_out, DFETAP3MONITOR1_out, DFETAP4MONITOR0_out, DFETAP4MONITOR1_out, DO_out, DRDY_out, REFCLKOUT_out, RXBUFSTATUS0_out, RXBUFSTATUS1_out, RXBYTEISALIGNED0_out, RXBYTEISALIGNED1_out, RXBYTEREALIGN0_out, RXBYTEREALIGN1_out, RXCHANBONDSEQ0_out, RXCHANBONDSEQ1_out, RXCHANISALIGNED0_out, RXCHANISALIGNED1_out, RXCHANREALIGN0_out, RXCHANREALIGN1_out, RXCHARISCOMMA0_out, RXCHARISCOMMA1_out, RXCHARISK0_out, RXCHARISK1_out, RXCHBONDO0_out, RXCHBONDO1_out, RXCLKCORCNT0_out, RXCLKCORCNT1_out, RXCOMMADET0_out, RXCOMMADET1_out, RXDATA0_out, RXDATA1_out, RXDATAVALID0_out, RXDATAVALID1_out, RXDISPERR0_out, RXDISPERR1_out, RXHEADER0_out, RXHEADER1_out, RXHEADERVALID0_out, RXHEADERVALID1_out, RXLOSSOFSYNC0_out, RXLOSSOFSYNC1_out, RXNOTINTABLE0_out, RXNOTINTABLE1_out, RXOVERSAMPLEERR0_out, RXOVERSAMPLEERR1_out, RXPRBSERR0_out, RXPRBSERR1_out, RXRUNDISP0_out, RXRUNDISP1_out, RXSTARTOFSEQ0_out, RXSTARTOFSEQ1_out, RXSTATUS0_out, RXSTATUS1_out, RXVALID0_out, RXVALID1_out, TXBUFSTATUS0_out, TXBUFSTATUS1_out, TXGEARBOXREADY0_out, TXGEARBOXREADY1_out, TXKERR0_out, TXKERR1_out, TXRUNDISP0_out, TXRUNDISP1_out, CLKIN_ipd, DADDR_ipd, DCLK_ipd, DEN_ipd, DFECLKDLYADJ0_ipd, DFECLKDLYADJ1_ipd, DFETAP10_ipd, DFETAP11_ipd, DFETAP20_ipd, DFETAP21_ipd, DFETAP30_ipd, DFETAP31_ipd, DFETAP40_ipd, DFETAP41_ipd, DI_ipd, DWE_ipd, GTXRESET_ipd, GTXTEST_ipd, INTDATAWIDTH_ipd, LOOPBACK0_ipd, LOOPBACK1_ipd, PLLLKDETEN_ipd, PLLPOWERDOWN_ipd, PRBSCNTRESET0_ipd, PRBSCNTRESET1_ipd, REFCLKPWRDNB_ipd, RXBUFRESET0_ipd, RXBUFRESET1_ipd, RXCDRRESET0_ipd, RXCDRRESET1_ipd, RXCHBONDI0_ipd, RXCHBONDI1_ipd, RXCOMMADETUSE0_ipd, RXCOMMADETUSE1_ipd, RXDATAWIDTH0_ipd, RXDATAWIDTH1_ipd, RXDEC8B10BUSE0_ipd, RXDEC8B10BUSE1_ipd, RXENCHANSYNC0_ipd, RXENCHANSYNC1_ipd, RXENEQB0_ipd, RXENEQB1_ipd, RXENMCOMMAALIGN0_ipd, RXENMCOMMAALIGN1_ipd, RXENPCOMMAALIGN0_ipd, RXENPCOMMAALIGN1_ipd, RXENPMAPHASEALIGN0_ipd, RXENPMAPHASEALIGN1_ipd, RXENPRBSTST0_ipd, RXENPRBSTST1_ipd, RXENSAMPLEALIGN0_ipd, RXENSAMPLEALIGN1_ipd, RXEQMIX0_ipd, RXEQMIX1_ipd, RXEQPOLE0_ipd, RXEQPOLE1_ipd, RXGEARBOXSLIP0_ipd, RXGEARBOXSLIP1_ipd, RXN0_ipd, RXN1_ipd, RXP0_ipd, RXP1_ipd, RXPMASETPHASE0_ipd, RXPMASETPHASE1_ipd, RXPOLARITY0_ipd, RXPOLARITY1_ipd, RXPOWERDOWN0_ipd, RXPOWERDOWN1_ipd, RXRESET0_ipd, RXRESET1_ipd, RXSLIDE0_ipd, RXSLIDE1_ipd, RXUSRCLK0_ipd, RXUSRCLK1_ipd, RXUSRCLK20_ipd, RXUSRCLK21_ipd, TXBUFDIFFCTRL0_ipd, TXBUFDIFFCTRL1_ipd, TXBYPASS8B10B0_ipd, TXBYPASS8B10B1_ipd, TXCHARDISPMODE0_ipd, TXCHARDISPMODE1_ipd, TXCHARDISPVAL0_ipd, TXCHARDISPVAL1_ipd, TXCHARISK0_ipd, TXCHARISK1_ipd, TXCOMSTART0_ipd, TXCOMSTART1_ipd, TXCOMTYPE0_ipd, TXCOMTYPE1_ipd, TXDATA0_ipd, TXDATA1_ipd, TXDATAWIDTH0_ipd, TXDATAWIDTH1_ipd, TXDETECTRX0_ipd, TXDETECTRX1_ipd, TXDIFFCTRL0_ipd, TXDIFFCTRL1_ipd, TXELECIDLE0_ipd, TXELECIDLE1_ipd, TXENC8B10BUSE0_ipd, TXENC8B10BUSE1_ipd, TXENPMAPHASEALIGN0_ipd, TXENPMAPHASEALIGN1_ipd, TXENPRBSTST0_ipd, TXENPRBSTST1_ipd, TXHEADER0_ipd, TXHEADER1_ipd, TXINHIBIT0_ipd, TXINHIBIT1_ipd, TXPMASETPHASE0_ipd, TXPMASETPHASE1_ipd, TXPOLARITY0_ipd, TXPOLARITY1_ipd, TXPOWERDOWN0_ipd, TXPOWERDOWN1_ipd, TXPREEMPHASIS0_ipd, TXPREEMPHASIS1_ipd, TXRESET0_ipd, TXRESET1_ipd, TXSEQUENCE0_ipd, TXSEQUENCE1_ipd, TXSTARTSEQ0_ipd, TXSTARTSEQ1_ipd, TXUSRCLK0_ipd, TXUSRCLK1_ipd, TXUSRCLK20_ipd, TXUSRCLK21_ipd; end process TIMING; PLLLKDET <= PLLLKDET_out; RESETDONE0 <= RESETDONE0_out; RESETDONE1 <= RESETDONE1_out; RXELECIDLE0 <= RXELECIDLE0_out; RXELECIDLE1 <= RXELECIDLE1_out; RXRECCLK0 <= RXRECCLK0_out; RXRECCLK1 <= RXRECCLK1_out; TXN0 <= TXN0_out; TXN1 <= TXN1_out; TXOUTCLK0 <= TXOUTCLK0_out; TXOUTCLK1 <= TXOUTCLK1_out; TXP0 <= TXP0_out; TXP1 <= TXP1_out; end GTX_DUAL_V; -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/virtex5fxt/SMODEL/Attic/jtagppc440.vhd,v 1.1 2006/09/18 21:16:09 sranade Exp $ ------------------------------------------------------------------------------- -- Copyright (c) 1995/2004 Xilinx, Inc. -- All Right Reserved. ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : Xilinx Functional Simulation Library Component -- / / JTAG Primitive for Virtex5 Power PC -- /___/ /\ Filename : JTAGPPC440.vhd -- \ \ / \ Timestamp : hu Aug 18 13:47:04 PDT 2005 -- \___\/\___\ -- -- Revision: -- 08/19/05 - Initial version. ----- CELL JTAGPPC440 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library unisim; use unisim.VCOMPONENTS.all; library secureip; use secureip.all; entity JTAGPPC440 is port ( TCK : out std_ulogic; TDIPPC : out std_ulogic; TMS : out std_ulogic; TDOPPC : in std_ulogic ); end JTAGPPC440; architecture JTAGPPC440_v of JTAGPPC440 is begin TCK <= '1'; TDIPPC <= '1'; TMS <= '1'; end JTAGPPC440_v; ------------------------------------------------------- -- Copyright (c) 1995/2006 Xilinx Inc. -- All Right Reserved. ------------------------------------------------------- -- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 10.1i -- \ \ Description : -- / / -- /___/ /\ Filename : PPC440.vhd -- \ \ / \ Timestamp : Thu Apr 19 15:56:12 2007 -- \__ \/\__ \ -- -- Generated by : write_vhdl -- Revision: ------------------------------------------------------- ----- CELL PPC440 ----- library IEEE; use IEEE.STD_LOGIC_1164.all; library IEEE; use IEEE.VITAL_Timing.all; library unisim; use unisim.VCOMPONENTS.all; library secureip; use secureip.all; entity PPC440 is generic ( APU_CONTROL : bit_vector := X"02000"; APU_UDI0 : bit_vector := X"000000"; APU_UDI1 : bit_vector := X"000000"; APU_UDI10 : bit_vector := X"000000"; APU_UDI11 : bit_vector := X"000000"; APU_UDI12 : bit_vector := X"000000"; APU_UDI13 : bit_vector := X"000000"; APU_UDI14 : bit_vector := X"000000"; APU_UDI15 : bit_vector := X"000000"; APU_UDI2 : bit_vector := X"000000"; APU_UDI3 : bit_vector := X"000000"; APU_UDI4 : bit_vector := X"000000"; APU_UDI5 : bit_vector := X"000000"; APU_UDI6 : bit_vector := X"000000"; APU_UDI7 : bit_vector := X"000000"; APU_UDI8 : bit_vector := X"000000"; APU_UDI9 : bit_vector := X"000000"; CLOCK_DELAY : boolean := FALSE; DCR_AUTOLOCK_ENABLE : boolean := TRUE; DMA0_CONTROL : bit_vector := X"00"; DMA0_RXCHANNELCTRL : bit_vector := X"01010000"; DMA0_RXIRQTIMER : bit_vector := X"3FF"; DMA0_TXCHANNELCTRL : bit_vector := X"01010000"; DMA0_TXIRQTIMER : bit_vector := X"3FF"; DMA1_CONTROL : bit_vector := X"00"; DMA1_RXCHANNELCTRL : bit_vector := X"01010000"; DMA1_RXIRQTIMER : bit_vector := X"3FF"; DMA1_TXCHANNELCTRL : bit_vector := X"01010000"; DMA1_TXIRQTIMER : bit_vector := X"3FF"; DMA2_CONTROL : bit_vector := X"00"; DMA2_RXCHANNELCTRL : bit_vector := X"01010000"; DMA2_RXIRQTIMER : bit_vector := X"3FF"; DMA2_TXCHANNELCTRL : bit_vector := X"01010000"; DMA2_TXIRQTIMER : bit_vector := X"3FF"; DMA3_CONTROL : bit_vector := X"00"; DMA3_RXCHANNELCTRL : bit_vector := X"01010000"; DMA3_RXIRQTIMER : bit_vector := X"3FF"; DMA3_TXCHANNELCTRL : bit_vector := X"01010000"; DMA3_TXIRQTIMER : bit_vector := X"3FF"; INTERCONNECT_IMASK : bit_vector := X"FFFFFFFF"; INTERCONNECT_TMPL_SEL : bit_vector := X"3FFFFFFF"; MI_ARBCONFIG : bit_vector := X"00432010"; MI_BANKCONFLICT_MASK : bit_vector := X"00000000"; MI_CONTROL : bit_vector := X"0000008F"; MI_ROWCONFLICT_MASK : bit_vector := X"00000000"; PPCDM_ASYNCMODE : boolean := FALSE; PPCDS_ASYNCMODE : boolean := FALSE; PPCM_ARBCONFIG : bit_vector := X"00432010"; PPCM_CONTROL : bit_vector := X"8000009F"; PPCM_COUNTER : bit_vector := X"00000500"; PPCS0_ADDRMAP_TMPL0 : bit_vector := X"FFFFFFFF"; PPCS0_ADDRMAP_TMPL1 : bit_vector := X"FFFFFFFF"; PPCS0_ADDRMAP_TMPL2 : bit_vector := X"FFFFFFFF"; PPCS0_ADDRMAP_TMPL3 : bit_vector := X"FFFFFFFF"; PPCS0_CONTROL : bit_vector := X"8033336C"; PPCS0_WIDTH_128N64 : boolean := TRUE; PPCS1_ADDRMAP_TMPL0 : bit_vector := X"FFFFFFFF"; PPCS1_ADDRMAP_TMPL1 : bit_vector := X"FFFFFFFF"; PPCS1_ADDRMAP_TMPL2 : bit_vector := X"FFFFFFFF"; PPCS1_ADDRMAP_TMPL3 : bit_vector := X"FFFFFFFF"; PPCS1_CONTROL : bit_vector := X"8033336C"; PPCS1_WIDTH_128N64 : boolean := TRUE; XBAR_ADDRMAP_TMPL0 : bit_vector := X"FFFF0000"; XBAR_ADDRMAP_TMPL1 : bit_vector := X"00000000"; XBAR_ADDRMAP_TMPL2 : bit_vector := X"00000000"; XBAR_ADDRMAP_TMPL3 : bit_vector := X"00000000" ); port ( APUFCMDECFPUOP : out std_ulogic; APUFCMDECLDSTXFERSIZE : out std_logic_vector(0 to 2); APUFCMDECLOAD : out std_ulogic; APUFCMDECNONAUTON : out std_ulogic; APUFCMDECSTORE : out std_ulogic; APUFCMDECUDI : out std_logic_vector(0 to 3); APUFCMDECUDIVALID : out std_ulogic; APUFCMENDIAN : out std_ulogic; APUFCMFLUSH : out std_ulogic; APUFCMINSTRUCTION : out std_logic_vector(0 to 31); APUFCMINSTRVALID : out std_ulogic; APUFCMLOADBYTEADDR : out std_logic_vector(0 to 3); APUFCMLOADDATA : out std_logic_vector(0 to 127); APUFCMLOADDVALID : out std_ulogic; APUFCMMSRFE0 : out std_ulogic; APUFCMMSRFE1 : out std_ulogic; APUFCMNEXTINSTRREADY : out std_ulogic; APUFCMOPERANDVALID : out std_ulogic; APUFCMRADATA : out std_logic_vector(0 to 31); APUFCMRBDATA : out std_logic_vector(0 to 31); APUFCMWRITEBACKOK : out std_ulogic; C440CPMCORESLEEPREQ : out std_ulogic; C440CPMDECIRPTREQ : out std_ulogic; C440CPMFITIRPTREQ : out std_ulogic; C440CPMMSRCE : out std_ulogic; C440CPMMSREE : out std_ulogic; C440CPMTIMERRESETREQ : out std_ulogic; C440CPMWDIRPTREQ : out std_ulogic; C440DBGSYSTEMCONTROL : out std_logic_vector(0 to 7); C440JTGTDO : out std_ulogic; C440JTGTDOEN : out std_ulogic; C440MACHINECHECK : out std_ulogic; C440RSTCHIPRESETREQ : out std_ulogic; C440RSTCORERESETREQ : out std_ulogic; C440RSTSYSTEMRESETREQ : out std_ulogic; C440TRCBRANCHSTATUS : out std_logic_vector(0 to 2); C440TRCCYCLE : out std_ulogic; C440TRCEXECUTIONSTATUS : out std_logic_vector(0 to 4); C440TRCTRACESTATUS : out std_logic_vector(0 to 6); C440TRCTRIGGEREVENTOUT : out std_ulogic; C440TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 13); DMA0LLRSTENGINEACK : out std_ulogic; DMA0LLRXDSTRDYN : out std_ulogic; DMA0LLTXD : out std_logic_vector(0 to 31); DMA0LLTXEOFN : out std_ulogic; DMA0LLTXEOPN : out std_ulogic; DMA0LLTXREM : out std_logic_vector(0 to 3); DMA0LLTXSOFN : out std_ulogic; DMA0LLTXSOPN : out std_ulogic; DMA0LLTXSRCRDYN : out std_ulogic; DMA0RXIRQ : out std_ulogic; DMA0TXIRQ : out std_ulogic; DMA1LLRSTENGINEACK : out std_ulogic; DMA1LLRXDSTRDYN : out std_ulogic; DMA1LLTXD : out std_logic_vector(0 to 31); DMA1LLTXEOFN : out std_ulogic; DMA1LLTXEOPN : out std_ulogic; DMA1LLTXREM : out std_logic_vector(0 to 3); DMA1LLTXSOFN : out std_ulogic; DMA1LLTXSOPN : out std_ulogic; DMA1LLTXSRCRDYN : out std_ulogic; DMA1RXIRQ : out std_ulogic; DMA1TXIRQ : out std_ulogic; DMA2LLRSTENGINEACK : out std_ulogic; DMA2LLRXDSTRDYN : out std_ulogic; DMA2LLTXD : out std_logic_vector(0 to 31); DMA2LLTXEOFN : out std_ulogic; DMA2LLTXEOPN : out std_ulogic; DMA2LLTXREM : out std_logic_vector(0 to 3); DMA2LLTXSOFN : out std_ulogic; DMA2LLTXSOPN : out std_ulogic; DMA2LLTXSRCRDYN : out std_ulogic; DMA2RXIRQ : out std_ulogic; DMA2TXIRQ : out std_ulogic; DMA3LLRSTENGINEACK : out std_ulogic; DMA3LLRXDSTRDYN : out std_ulogic; DMA3LLTXD : out std_logic_vector(0 to 31); DMA3LLTXEOFN : out std_ulogic; DMA3LLTXEOPN : out std_ulogic; DMA3LLTXREM : out std_logic_vector(0 to 3); DMA3LLTXSOFN : out std_ulogic; DMA3LLTXSOPN : out std_ulogic; DMA3LLTXSRCRDYN : out std_ulogic; DMA3RXIRQ : out std_ulogic; DMA3TXIRQ : out std_ulogic; MIMCADDRESS : out std_logic_vector(0 to 35); MIMCADDRESSVALID : out std_ulogic; MIMCBANKCONFLICT : out std_ulogic; MIMCBYTEENABLE : out std_logic_vector(0 to 15); MIMCREADNOTWRITE : out std_ulogic; MIMCROWCONFLICT : out std_ulogic; MIMCWRITEDATA : out std_logic_vector(0 to 127); MIMCWRITEDATAVALID : out std_ulogic; PPCCPMINTERCONNECTBUSY : out std_ulogic; PPCDMDCRABUS : out std_logic_vector(0 to 9); PPCDMDCRDBUSOUT : out std_logic_vector(0 to 31); PPCDMDCRREAD : out std_ulogic; PPCDMDCRUABUS : out std_logic_vector(20 to 21); PPCDMDCRWRITE : out std_ulogic; PPCDSDCRACK : out std_ulogic; PPCDSDCRDBUSIN : out std_logic_vector(0 to 31); PPCDSDCRTIMEOUTWAIT : out std_ulogic; PPCEICINTERCONNECTIRQ : out std_ulogic; PPCMPLBABORT : out std_ulogic; PPCMPLBABUS : out std_logic_vector(0 to 31); PPCMPLBBE : out std_logic_vector(0 to 15); PPCMPLBBUSLOCK : out std_ulogic; PPCMPLBLOCKERR : out std_ulogic; PPCMPLBPRIORITY : out std_logic_vector(0 to 1); PPCMPLBRDBURST : out std_ulogic; PPCMPLBREQUEST : out std_ulogic; PPCMPLBRNW : out std_ulogic; PPCMPLBSIZE : out std_logic_vector(0 to 3); PPCMPLBTATTRIBUTE : out std_logic_vector(0 to 15); PPCMPLBTYPE : out std_logic_vector(0 to 2); PPCMPLBUABUS : out std_logic_vector(28 to 31); PPCMPLBWRBURST : out std_ulogic; PPCMPLBWRDBUS : out std_logic_vector(0 to 127); PPCS0PLBADDRACK : out std_ulogic; PPCS0PLBMBUSY : out std_logic_vector(0 to 3); PPCS0PLBMIRQ : out std_logic_vector(0 to 3); PPCS0PLBMRDERR : out std_logic_vector(0 to 3); PPCS0PLBMWRERR : out std_logic_vector(0 to 3); PPCS0PLBRDBTERM : out std_ulogic; PPCS0PLBRDCOMP : out std_ulogic; PPCS0PLBRDDACK : out std_ulogic; PPCS0PLBRDDBUS : out std_logic_vector(0 to 127); PPCS0PLBRDWDADDR : out std_logic_vector(0 to 3); PPCS0PLBREARBITRATE : out std_ulogic; PPCS0PLBSSIZE : out std_logic_vector(0 to 1); PPCS0PLBWAIT : out std_ulogic; PPCS0PLBWRBTERM : out std_ulogic; PPCS0PLBWRCOMP : out std_ulogic; PPCS0PLBWRDACK : out std_ulogic; PPCS1PLBADDRACK : out std_ulogic; PPCS1PLBMBUSY : out std_logic_vector(0 to 3); PPCS1PLBMIRQ : out std_logic_vector(0 to 3); PPCS1PLBMRDERR : out std_logic_vector(0 to 3); PPCS1PLBMWRERR : out std_logic_vector(0 to 3); PPCS1PLBRDBTERM : out std_ulogic; PPCS1PLBRDCOMP : out std_ulogic; PPCS1PLBRDDACK : out std_ulogic; PPCS1PLBRDDBUS : out std_logic_vector(0 to 127); PPCS1PLBRDWDADDR : out std_logic_vector(0 to 3); PPCS1PLBREARBITRATE : out std_ulogic; PPCS1PLBSSIZE : out std_logic_vector(0 to 1); PPCS1PLBWAIT : out std_ulogic; PPCS1PLBWRBTERM : out std_ulogic; PPCS1PLBWRCOMP : out std_ulogic; PPCS1PLBWRDACK : out std_ulogic; CPMC440CLK : in std_ulogic; CPMC440CLKEN : in std_ulogic; CPMC440CORECLOCKINACTIVE : in std_ulogic; CPMC440TIMERCLOCK : in std_ulogic; CPMDCRCLK : in std_ulogic; CPMDMA0LLCLK : in std_ulogic; CPMDMA1LLCLK : in std_ulogic; CPMDMA2LLCLK : in std_ulogic; CPMDMA3LLCLK : in std_ulogic; CPMFCMCLK : in std_ulogic; CPMINTERCONNECTCLK : in std_ulogic; CPMINTERCONNECTCLKEN : in std_ulogic; CPMINTERCONNECTCLKNTO1 : in std_ulogic; CPMMCCLK : in std_ulogic; CPMPPCMPLBCLK : in std_ulogic; CPMPPCS0PLBCLK : in std_ulogic; CPMPPCS1PLBCLK : in std_ulogic; DBGC440DEBUGHALT : in std_ulogic; DBGC440SYSTEMSTATUS : in std_logic_vector(0 to 4); DBGC440UNCONDDEBUGEVENT : in std_ulogic; DCRPPCDMACK : in std_ulogic; DCRPPCDMDBUSIN : in std_logic_vector(0 to 31); DCRPPCDMTIMEOUTWAIT : in std_ulogic; DCRPPCDSABUS : in std_logic_vector(0 to 9); DCRPPCDSDBUSOUT : in std_logic_vector(0 to 31); DCRPPCDSREAD : in std_ulogic; DCRPPCDSWRITE : in std_ulogic; EICC440CRITIRQ : in std_ulogic; EICC440EXTIRQ : in std_ulogic; FCMAPUCONFIRMINSTR : in std_ulogic; FCMAPUCR : in std_logic_vector(0 to 3); FCMAPUDONE : in std_ulogic; FCMAPUEXCEPTION : in std_ulogic; FCMAPUFPSCRFEX : in std_ulogic; FCMAPURESULT : in std_logic_vector(0 to 31); FCMAPURESULTVALID : in std_ulogic; FCMAPUSLEEPNOTREADY : in std_ulogic; FCMAPUSTOREDATA : in std_logic_vector(0 to 127); JTGC440TCK : in std_ulogic; JTGC440TDI : in std_ulogic; JTGC440TMS : in std_ulogic; JTGC440TRSTNEG : in std_ulogic; LLDMA0RSTENGINEREQ : in std_ulogic; LLDMA0RXD : in std_logic_vector(0 to 31); LLDMA0RXEOFN : in std_ulogic; LLDMA0RXEOPN : in std_ulogic; LLDMA0RXREM : in std_logic_vector(0 to 3); LLDMA0RXSOFN : in std_ulogic; LLDMA0RXSOPN : in std_ulogic; LLDMA0RXSRCRDYN : in std_ulogic; LLDMA0TXDSTRDYN : in std_ulogic; LLDMA1RSTENGINEREQ : in std_ulogic; LLDMA1RXD : in std_logic_vector(0 to 31); LLDMA1RXEOFN : in std_ulogic; LLDMA1RXEOPN : in std_ulogic; LLDMA1RXREM : in std_logic_vector(0 to 3); LLDMA1RXSOFN : in std_ulogic; LLDMA1RXSOPN : in std_ulogic; LLDMA1RXSRCRDYN : in std_ulogic; LLDMA1TXDSTRDYN : in std_ulogic; LLDMA2RSTENGINEREQ : in std_ulogic; LLDMA2RXD : in std_logic_vector(0 to 31); LLDMA2RXEOFN : in std_ulogic; LLDMA2RXEOPN : in std_ulogic; LLDMA2RXREM : in std_logic_vector(0 to 3); LLDMA2RXSOFN : in std_ulogic; LLDMA2RXSOPN : in std_ulogic; LLDMA2RXSRCRDYN : in std_ulogic; LLDMA2TXDSTRDYN : in std_ulogic; LLDMA3RSTENGINEREQ : in std_ulogic; LLDMA3RXD : in std_logic_vector(0 to 31); LLDMA3RXEOFN : in std_ulogic; LLDMA3RXEOPN : in std_ulogic; LLDMA3RXREM : in std_logic_vector(0 to 3); LLDMA3RXSOFN : in std_ulogic; LLDMA3RXSOPN : in std_ulogic; LLDMA3RXSRCRDYN : in std_ulogic; LLDMA3TXDSTRDYN : in std_ulogic; MCMIADDRREADYTOACCEPT : in std_ulogic; MCMIREADDATA : in std_logic_vector(0 to 127); MCMIREADDATAERR : in std_ulogic; MCMIREADDATAVALID : in std_ulogic; PLBPPCMADDRACK : in std_ulogic; PLBPPCMMBUSY : in std_ulogic; PLBPPCMMIRQ : in std_ulogic; PLBPPCMMRDERR : in std_ulogic; PLBPPCMMWRERR : in std_ulogic; PLBPPCMRDBTERM : in std_ulogic; PLBPPCMRDDACK : in std_ulogic; PLBPPCMRDDBUS : in std_logic_vector(0 to 127); PLBPPCMRDPENDPRI : in std_logic_vector(0 to 1); PLBPPCMRDPENDREQ : in std_ulogic; PLBPPCMRDWDADDR : in std_logic_vector(0 to 3); PLBPPCMREARBITRATE : in std_ulogic; PLBPPCMREQPRI : in std_logic_vector(0 to 1); PLBPPCMSSIZE : in std_logic_vector(0 to 1); PLBPPCMTIMEOUT : in std_ulogic; PLBPPCMWRBTERM : in std_ulogic; PLBPPCMWRDACK : in std_ulogic; PLBPPCMWRPENDPRI : in std_logic_vector(0 to 1); PLBPPCMWRPENDREQ : in std_ulogic; PLBPPCS0ABORT : in std_ulogic; PLBPPCS0ABUS : in std_logic_vector(0 to 31); PLBPPCS0BE : in std_logic_vector(0 to 15); PLBPPCS0BUSLOCK : in std_ulogic; PLBPPCS0LOCKERR : in std_ulogic; PLBPPCS0MASTERID : in std_logic_vector(0 to 1); PLBPPCS0MSIZE : in std_logic_vector(0 to 1); PLBPPCS0PAVALID : in std_ulogic; PLBPPCS0RDBURST : in std_ulogic; PLBPPCS0RDPENDPRI : in std_logic_vector(0 to 1); PLBPPCS0RDPENDREQ : in std_ulogic; PLBPPCS0RDPRIM : in std_ulogic; PLBPPCS0REQPRI : in std_logic_vector(0 to 1); PLBPPCS0RNW : in std_ulogic; PLBPPCS0SAVALID : in std_ulogic; PLBPPCS0SIZE : in std_logic_vector(0 to 3); PLBPPCS0TATTRIBUTE : in std_logic_vector(0 to 15); PLBPPCS0TYPE : in std_logic_vector(0 to 2); PLBPPCS0UABUS : in std_logic_vector(28 to 31); PLBPPCS0WRBURST : in std_ulogic; PLBPPCS0WRDBUS : in std_logic_vector(0 to 127); PLBPPCS0WRPENDPRI : in std_logic_vector(0 to 1); PLBPPCS0WRPENDREQ : in std_ulogic; PLBPPCS0WRPRIM : in std_ulogic; PLBPPCS1ABORT : in std_ulogic; PLBPPCS1ABUS : in std_logic_vector(0 to 31); PLBPPCS1BE : in std_logic_vector(0 to 15); PLBPPCS1BUSLOCK : in std_ulogic; PLBPPCS1LOCKERR : in std_ulogic; PLBPPCS1MASTERID : in std_logic_vector(0 to 1); PLBPPCS1MSIZE : in std_logic_vector(0 to 1); PLBPPCS1PAVALID : in std_ulogic; PLBPPCS1RDBURST : in std_ulogic; PLBPPCS1RDPENDPRI : in std_logic_vector(0 to 1); PLBPPCS1RDPENDREQ : in std_ulogic; PLBPPCS1RDPRIM : in std_ulogic; PLBPPCS1REQPRI : in std_logic_vector(0 to 1); PLBPPCS1RNW : in std_ulogic; PLBPPCS1SAVALID : in std_ulogic; PLBPPCS1SIZE : in std_logic_vector(0 to 3); PLBPPCS1TATTRIBUTE : in std_logic_vector(0 to 15); PLBPPCS1TYPE : in std_logic_vector(0 to 2); PLBPPCS1UABUS : in std_logic_vector(28 to 31); PLBPPCS1WRBURST : in std_ulogic; PLBPPCS1WRDBUS : in std_logic_vector(0 to 127); PLBPPCS1WRPENDPRI : in std_logic_vector(0 to 1); PLBPPCS1WRPENDREQ : in std_ulogic; PLBPPCS1WRPRIM : in std_ulogic; RSTC440RESETCHIP : in std_ulogic; RSTC440RESETCORE : in std_ulogic; RSTC440RESETSYSTEM : in std_ulogic; TIEC440DCURDLDCACHEPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCURDNONCACHEPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCURDURGENTPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCUWRFLUSHPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCUWRSTOREPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCUWRURGENTPLBPRIO : in std_logic_vector(0 to 1); TIEC440ENDIANRESET : in std_ulogic; TIEC440ERPNRESET : in std_logic_vector(0 to 3); TIEC440ICURDFETCHPLBPRIO : in std_logic_vector(0 to 1); TIEC440ICURDSPECPLBPRIO : in std_logic_vector(0 to 1); TIEC440ICURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); TIEC440PIR : in std_logic_vector(28 to 31); TIEC440PVR : in std_logic_vector(28 to 31); TIEC440USERRESET : in std_logic_vector(0 to 3); TIEDCRBASEADDR : in std_logic_vector(0 to 1); TRCC440TRACEDISABLE : in std_ulogic; TRCC440TRIGGEREVENTIN : in std_ulogic ); end PPC440; architecture PPC440_V of PPC440 is component PPC440_SWIFT port ( APUFCMDECFPUOP : out std_ulogic; APUFCMDECLDSTXFERSIZE : out std_logic_vector(0 to 2); APUFCMDECLOAD : out std_ulogic; APUFCMDECNONAUTON : out std_ulogic; APUFCMDECSTORE : out std_ulogic; APUFCMDECUDI : out std_logic_vector(0 to 3); APUFCMDECUDIVALID : out std_ulogic; APUFCMENDIAN : out std_ulogic; APUFCMFLUSH : out std_ulogic; APUFCMINSTRUCTION : out std_logic_vector(0 to 31); APUFCMINSTRVALID : out std_ulogic; APUFCMLOADBYTEADDR : out std_logic_vector(0 to 3); APUFCMLOADDATA : out std_logic_vector(0 to 127); APUFCMLOADDVALID : out std_ulogic; APUFCMMSRFE0 : out std_ulogic; APUFCMMSRFE1 : out std_ulogic; APUFCMNEXTINSTRREADY : out std_ulogic; APUFCMOPERANDVALID : out std_ulogic; APUFCMRADATA : out std_logic_vector(0 to 31); APUFCMRBDATA : out std_logic_vector(0 to 31); APUFCMWRITEBACKOK : out std_ulogic; C440CPMCORESLEEPREQ : out std_ulogic; C440CPMDECIRPTREQ : out std_ulogic; C440CPMFITIRPTREQ : out std_ulogic; C440CPMMSRCE : out std_ulogic; C440CPMMSREE : out std_ulogic; C440CPMTIMERRESETREQ : out std_ulogic; C440CPMWDIRPTREQ : out std_ulogic; C440DBGSYSTEMCONTROL : out std_logic_vector(0 to 7); C440JTGTDO : out std_ulogic; C440JTGTDOEN : out std_ulogic; C440MACHINECHECK : out std_ulogic; C440RSTCHIPRESETREQ : out std_ulogic; C440RSTCORERESETREQ : out std_ulogic; C440RSTSYSTEMRESETREQ : out std_ulogic; C440TRCBRANCHSTATUS : out std_logic_vector(0 to 2); C440TRCCYCLE : out std_ulogic; C440TRCEXECUTIONSTATUS : out std_logic_vector(0 to 4); C440TRCTRACESTATUS : out std_logic_vector(0 to 6); C440TRCTRIGGEREVENTOUT : out std_ulogic; C440TRCTRIGGEREVENTTYPE : out std_logic_vector(0 to 13); DMA0LLRSTENGINEACK : out std_ulogic; DMA0LLRXDSTRDYN : out std_ulogic; DMA0LLTXD : out std_logic_vector(0 to 31); DMA0LLTXEOFN : out std_ulogic; DMA0LLTXEOPN : out std_ulogic; DMA0LLTXREM : out std_logic_vector(0 to 3); DMA0LLTXSOFN : out std_ulogic; DMA0LLTXSOPN : out std_ulogic; DMA0LLTXSRCRDYN : out std_ulogic; DMA0RXIRQ : out std_ulogic; DMA0TXIRQ : out std_ulogic; DMA1LLRSTENGINEACK : out std_ulogic; DMA1LLRXDSTRDYN : out std_ulogic; DMA1LLTXD : out std_logic_vector(0 to 31); DMA1LLTXEOFN : out std_ulogic; DMA1LLTXEOPN : out std_ulogic; DMA1LLTXREM : out std_logic_vector(0 to 3); DMA1LLTXSOFN : out std_ulogic; DMA1LLTXSOPN : out std_ulogic; DMA1LLTXSRCRDYN : out std_ulogic; DMA1RXIRQ : out std_ulogic; DMA1TXIRQ : out std_ulogic; DMA2LLRSTENGINEACK : out std_ulogic; DMA2LLRXDSTRDYN : out std_ulogic; DMA2LLTXD : out std_logic_vector(0 to 31); DMA2LLTXEOFN : out std_ulogic; DMA2LLTXEOPN : out std_ulogic; DMA2LLTXREM : out std_logic_vector(0 to 3); DMA2LLTXSOFN : out std_ulogic; DMA2LLTXSOPN : out std_ulogic; DMA2LLTXSRCRDYN : out std_ulogic; DMA2RXIRQ : out std_ulogic; DMA2TXIRQ : out std_ulogic; DMA3LLRSTENGINEACK : out std_ulogic; DMA3LLRXDSTRDYN : out std_ulogic; DMA3LLTXD : out std_logic_vector(0 to 31); DMA3LLTXEOFN : out std_ulogic; DMA3LLTXEOPN : out std_ulogic; DMA3LLTXREM : out std_logic_vector(0 to 3); DMA3LLTXSOFN : out std_ulogic; DMA3LLTXSOPN : out std_ulogic; DMA3LLTXSRCRDYN : out std_ulogic; DMA3RXIRQ : out std_ulogic; DMA3TXIRQ : out std_ulogic; MIMCADDRESS : out std_logic_vector(0 to 35); MIMCADDRESSVALID : out std_ulogic; MIMCBANKCONFLICT : out std_ulogic; MIMCBYTEENABLE : out std_logic_vector(0 to 15); MIMCREADNOTWRITE : out std_ulogic; MIMCROWCONFLICT : out std_ulogic; MIMCWRITEDATA : out std_logic_vector(0 to 127); MIMCWRITEDATAVALID : out std_ulogic; PPCCPMINTERCONNECTBUSY : out std_ulogic; PPCDMDCRABUS : out std_logic_vector(0 to 9); PPCDMDCRDBUSOUT : out std_logic_vector(0 to 31); PPCDMDCRREAD : out std_ulogic; PPCDMDCRUABUS : out std_logic_vector(20 to 21); PPCDMDCRWRITE : out std_ulogic; PPCDSDCRACK : out std_ulogic; PPCDSDCRDBUSIN : out std_logic_vector(0 to 31); PPCDSDCRTIMEOUTWAIT : out std_ulogic; PPCEICINTERCONNECTIRQ : out std_ulogic; PPCMPLBABORT : out std_ulogic; PPCMPLBABUS : out std_logic_vector(0 to 31); PPCMPLBBE : out std_logic_vector(0 to 15); PPCMPLBBUSLOCK : out std_ulogic; PPCMPLBLOCKERR : out std_ulogic; PPCMPLBPRIORITY : out std_logic_vector(0 to 1); PPCMPLBRDBURST : out std_ulogic; PPCMPLBREQUEST : out std_ulogic; PPCMPLBRNW : out std_ulogic; PPCMPLBSIZE : out std_logic_vector(0 to 3); PPCMPLBTATTRIBUTE : out std_logic_vector(0 to 15); PPCMPLBTYPE : out std_logic_vector(0 to 2); PPCMPLBUABUS : out std_logic_vector(28 to 31); PPCMPLBWRBURST : out std_ulogic; PPCMPLBWRDBUS : out std_logic_vector(0 to 127); PPCS0PLBADDRACK : out std_ulogic; PPCS0PLBMBUSY : out std_logic_vector(0 to 3); PPCS0PLBMIRQ : out std_logic_vector(0 to 3); PPCS0PLBMRDERR : out std_logic_vector(0 to 3); PPCS0PLBMWRERR : out std_logic_vector(0 to 3); PPCS0PLBRDBTERM : out std_ulogic; PPCS0PLBRDCOMP : out std_ulogic; PPCS0PLBRDDACK : out std_ulogic; PPCS0PLBRDDBUS : out std_logic_vector(0 to 127); PPCS0PLBRDWDADDR : out std_logic_vector(0 to 3); PPCS0PLBREARBITRATE : out std_ulogic; PPCS0PLBSSIZE : out std_logic_vector(0 to 1); PPCS0PLBWAIT : out std_ulogic; PPCS0PLBWRBTERM : out std_ulogic; PPCS0PLBWRCOMP : out std_ulogic; PPCS0PLBWRDACK : out std_ulogic; PPCS1PLBADDRACK : out std_ulogic; PPCS1PLBMBUSY : out std_logic_vector(0 to 3); PPCS1PLBMIRQ : out std_logic_vector(0 to 3); PPCS1PLBMRDERR : out std_logic_vector(0 to 3); PPCS1PLBMWRERR : out std_logic_vector(0 to 3); PPCS1PLBRDBTERM : out std_ulogic; PPCS1PLBRDCOMP : out std_ulogic; PPCS1PLBRDDACK : out std_ulogic; PPCS1PLBRDDBUS : out std_logic_vector(0 to 127); PPCS1PLBRDWDADDR : out std_logic_vector(0 to 3); PPCS1PLBREARBITRATE : out std_ulogic; PPCS1PLBSSIZE : out std_logic_vector(0 to 1); PPCS1PLBWAIT : out std_ulogic; PPCS1PLBWRBTERM : out std_ulogic; PPCS1PLBWRCOMP : out std_ulogic; PPCS1PLBWRDACK : out std_ulogic; CPMC440CLK : in std_ulogic; CPMC440CLKEN : in std_ulogic; CPMC440CORECLOCKINACTIVE : in std_ulogic; CPMC440TIMERCLOCK : in std_ulogic; CPMDCRCLK : in std_ulogic; CPMDMA0LLCLK : in std_ulogic; CPMDMA1LLCLK : in std_ulogic; CPMDMA2LLCLK : in std_ulogic; CPMDMA3LLCLK : in std_ulogic; CPMFCMCLK : in std_ulogic; CPMINTERCONNECTCLK : in std_ulogic; CPMINTERCONNECTCLKEN : in std_ulogic; CPMINTERCONNECTCLKNTO1 : in std_ulogic; CPMMCCLK : in std_ulogic; CPMPPCMPLBCLK : in std_ulogic; CPMPPCS0PLBCLK : in std_ulogic; CPMPPCS1PLBCLK : in std_ulogic; DBGC440DEBUGHALT : in std_ulogic; DBGC440SYSTEMSTATUS : in std_logic_vector(0 to 4); DBGC440UNCONDDEBUGEVENT : in std_ulogic; DCRPPCDMACK : in std_ulogic; DCRPPCDMDBUSIN : in std_logic_vector(0 to 31); DCRPPCDMTIMEOUTWAIT : in std_ulogic; DCRPPCDSABUS : in std_logic_vector(0 to 9); DCRPPCDSDBUSOUT : in std_logic_vector(0 to 31); DCRPPCDSREAD : in std_ulogic; DCRPPCDSWRITE : in std_ulogic; EICC440CRITIRQ : in std_ulogic; EICC440EXTIRQ : in std_ulogic; FCMAPUCONFIRMINSTR : in std_ulogic; FCMAPUCR : in std_logic_vector(0 to 3); FCMAPUDONE : in std_ulogic; FCMAPUEXCEPTION : in std_ulogic; FCMAPUFPSCRFEX : in std_ulogic; FCMAPURESULT : in std_logic_vector(0 to 31); FCMAPURESULTVALID : in std_ulogic; FCMAPUSLEEPNOTREADY : in std_ulogic; FCMAPUSTOREDATA : in std_logic_vector(0 to 127); GSR : in std_ulogic; JTGC440TCK : in std_ulogic; JTGC440TDI : in std_ulogic; JTGC440TMS : in std_ulogic; JTGC440TRSTNEG : in std_ulogic; LLDMA0RSTENGINEREQ : in std_ulogic; LLDMA0RXD : in std_logic_vector(0 to 31); LLDMA0RXEOFN : in std_ulogic; LLDMA0RXEOPN : in std_ulogic; LLDMA0RXREM : in std_logic_vector(0 to 3); LLDMA0RXSOFN : in std_ulogic; LLDMA0RXSOPN : in std_ulogic; LLDMA0RXSRCRDYN : in std_ulogic; LLDMA0TXDSTRDYN : in std_ulogic; LLDMA1RSTENGINEREQ : in std_ulogic; LLDMA1RXD : in std_logic_vector(0 to 31); LLDMA1RXEOFN : in std_ulogic; LLDMA1RXEOPN : in std_ulogic; LLDMA1RXREM : in std_logic_vector(0 to 3); LLDMA1RXSOFN : in std_ulogic; LLDMA1RXSOPN : in std_ulogic; LLDMA1RXSRCRDYN : in std_ulogic; LLDMA1TXDSTRDYN : in std_ulogic; LLDMA2RSTENGINEREQ : in std_ulogic; LLDMA2RXD : in std_logic_vector(0 to 31); LLDMA2RXEOFN : in std_ulogic; LLDMA2RXEOPN : in std_ulogic; LLDMA2RXREM : in std_logic_vector(0 to 3); LLDMA2RXSOFN : in std_ulogic; LLDMA2RXSOPN : in std_ulogic; LLDMA2RXSRCRDYN : in std_ulogic; LLDMA2TXDSTRDYN : in std_ulogic; LLDMA3RSTENGINEREQ : in std_ulogic; LLDMA3RXD : in std_logic_vector(0 to 31); LLDMA3RXEOFN : in std_ulogic; LLDMA3RXEOPN : in std_ulogic; LLDMA3RXREM : in std_logic_vector(0 to 3); LLDMA3RXSOFN : in std_ulogic; LLDMA3RXSOPN : in std_ulogic; LLDMA3RXSRCRDYN : in std_ulogic; LLDMA3TXDSTRDYN : in std_ulogic; MCMIADDRREADYTOACCEPT : in std_ulogic; MCMIREADDATA : in std_logic_vector(0 to 127); MCMIREADDATAERR : in std_ulogic; MCMIREADDATAVALID : in std_ulogic; PLBPPCMADDRACK : in std_ulogic; PLBPPCMMBUSY : in std_ulogic; PLBPPCMMIRQ : in std_ulogic; PLBPPCMMRDERR : in std_ulogic; PLBPPCMMWRERR : in std_ulogic; PLBPPCMRDBTERM : in std_ulogic; PLBPPCMRDDACK : in std_ulogic; PLBPPCMRDDBUS : in std_logic_vector(0 to 127); PLBPPCMRDPENDPRI : in std_logic_vector(0 to 1); PLBPPCMRDPENDREQ : in std_ulogic; PLBPPCMRDWDADDR : in std_logic_vector(0 to 3); PLBPPCMREARBITRATE : in std_ulogic; PLBPPCMREQPRI : in std_logic_vector(0 to 1); PLBPPCMSSIZE : in std_logic_vector(0 to 1); PLBPPCMTIMEOUT : in std_ulogic; PLBPPCMWRBTERM : in std_ulogic; PLBPPCMWRDACK : in std_ulogic; PLBPPCMWRPENDPRI : in std_logic_vector(0 to 1); PLBPPCMWRPENDREQ : in std_ulogic; PLBPPCS0ABORT : in std_ulogic; PLBPPCS0ABUS : in std_logic_vector(0 to 31); PLBPPCS0BE : in std_logic_vector(0 to 15); PLBPPCS0BUSLOCK : in std_ulogic; PLBPPCS0LOCKERR : in std_ulogic; PLBPPCS0MASTERID : in std_logic_vector(0 to 1); PLBPPCS0MSIZE : in std_logic_vector(0 to 1); PLBPPCS0PAVALID : in std_ulogic; PLBPPCS0RDBURST : in std_ulogic; PLBPPCS0RDPENDPRI : in std_logic_vector(0 to 1); PLBPPCS0RDPENDREQ : in std_ulogic; PLBPPCS0RDPRIM : in std_ulogic; PLBPPCS0REQPRI : in std_logic_vector(0 to 1); PLBPPCS0RNW : in std_ulogic; PLBPPCS0SAVALID : in std_ulogic; PLBPPCS0SIZE : in std_logic_vector(0 to 3); PLBPPCS0TATTRIBUTE : in std_logic_vector(0 to 15); PLBPPCS0TYPE : in std_logic_vector(0 to 2); PLBPPCS0UABUS : in std_logic_vector(28 to 31); PLBPPCS0WRBURST : in std_ulogic; PLBPPCS0WRDBUS : in std_logic_vector(0 to 127); PLBPPCS0WRPENDPRI : in std_logic_vector(0 to 1); PLBPPCS0WRPENDREQ : in std_ulogic; PLBPPCS0WRPRIM : in std_ulogic; PLBPPCS1ABORT : in std_ulogic; PLBPPCS1ABUS : in std_logic_vector(0 to 31); PLBPPCS1BE : in std_logic_vector(0 to 15); PLBPPCS1BUSLOCK : in std_ulogic; PLBPPCS1LOCKERR : in std_ulogic; PLBPPCS1MASTERID : in std_logic_vector(0 to 1); PLBPPCS1MSIZE : in std_logic_vector(0 to 1); PLBPPCS1PAVALID : in std_ulogic; PLBPPCS1RDBURST : in std_ulogic; PLBPPCS1RDPENDPRI : in std_logic_vector(0 to 1); PLBPPCS1RDPENDREQ : in std_ulogic; PLBPPCS1RDPRIM : in std_ulogic; PLBPPCS1REQPRI : in std_logic_vector(0 to 1); PLBPPCS1RNW : in std_ulogic; PLBPPCS1SAVALID : in std_ulogic; PLBPPCS1SIZE : in std_logic_vector(0 to 3); PLBPPCS1TATTRIBUTE : in std_logic_vector(0 to 15); PLBPPCS1TYPE : in std_logic_vector(0 to 2); PLBPPCS1UABUS : in std_logic_vector(28 to 31); PLBPPCS1WRBURST : in std_ulogic; PLBPPCS1WRDBUS : in std_logic_vector(0 to 127); PLBPPCS1WRPENDPRI : in std_logic_vector(0 to 1); PLBPPCS1WRPENDREQ : in std_ulogic; PLBPPCS1WRPRIM : in std_ulogic; RSTC440RESETCHIP : in std_ulogic; RSTC440RESETCORE : in std_ulogic; RSTC440RESETSYSTEM : in std_ulogic; TIEC440DCURDLDCACHEPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCURDNONCACHEPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCURDURGENTPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCUWRFLUSHPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCUWRSTOREPLBPRIO : in std_logic_vector(0 to 1); TIEC440DCUWRURGENTPLBPRIO : in std_logic_vector(0 to 1); TIEC440ENDIANRESET : in std_ulogic; TIEC440ERPNRESET : in std_logic_vector(0 to 3); TIEC440ICURDFETCHPLBPRIO : in std_logic_vector(0 to 1); TIEC440ICURDSPECPLBPRIO : in std_logic_vector(0 to 1); TIEC440ICURDTOUCHPLBPRIO : in std_logic_vector(0 to 1); TIEC440PIR : in std_logic_vector(28 to 31); TIEC440PVR : in std_logic_vector(28 to 31); TIEC440USERRESET : in std_logic_vector(0 to 3); TIEDCRBASEADDR : in std_logic_vector(0 to 1); TRCC440TRACEDISABLE : in std_ulogic; TRCC440TRIGGEREVENTIN : in std_ulogic; APU_CONTROL : in std_logic_vector(0 to 16); APU_UDI0 : in std_logic_vector(0 to 23); APU_UDI1 : in std_logic_vector(0 to 23); APU_UDI10 : in std_logic_vector(0 to 23); APU_UDI11 : in std_logic_vector(0 to 23); APU_UDI12 : in std_logic_vector(0 to 23); APU_UDI13 : in std_logic_vector(0 to 23); APU_UDI14 : in std_logic_vector(0 to 23); APU_UDI15 : in std_logic_vector(0 to 23); APU_UDI2 : in std_logic_vector(0 to 23); APU_UDI3 : in std_logic_vector(0 to 23); APU_UDI4 : in std_logic_vector(0 to 23); APU_UDI5 : in std_logic_vector(0 to 23); APU_UDI6 : in std_logic_vector(0 to 23); APU_UDI7 : in std_logic_vector(0 to 23); APU_UDI8 : in std_logic_vector(0 to 23); APU_UDI9 : in std_logic_vector(0 to 23); -- CLOCK_DELAY : in std_ulogic; CLOCK_DELAY : in std_logic_vector(0 to 4); DCR_AUTOLOCK_ENABLE : in std_ulogic; DMA0_CONTROL : in std_logic_vector(0 to 7); DMA0_RXCHANNELCTRL : in std_logic_vector(0 to 31); DMA0_RXIRQTIMER : in std_logic_vector(0 to 9); DMA0_TXCHANNELCTRL : in std_logic_vector(0 to 31); DMA0_TXIRQTIMER : in std_logic_vector(0 to 9); DMA1_CONTROL : in std_logic_vector(0 to 7); DMA1_RXCHANNELCTRL : in std_logic_vector(0 to 31); DMA1_RXIRQTIMER : in std_logic_vector(0 to 9); DMA1_TXCHANNELCTRL : in std_logic_vector(0 to 31); DMA1_TXIRQTIMER : in std_logic_vector(0 to 9); DMA2_CONTROL : in std_logic_vector(0 to 7); DMA2_RXCHANNELCTRL : in std_logic_vector(0 to 31); DMA2_RXIRQTIMER : in std_logic_vector(0 to 9); DMA2_TXCHANNELCTRL : in std_logic_vector(0 to 31); DMA2_TXIRQTIMER : in std_logic_vector(0 to 9); DMA3_CONTROL : in std_logic_vector(0 to 7); DMA3_RXCHANNELCTRL : in std_logic_vector(0 to 31); DMA3_RXIRQTIMER : in std_logic_vector(0 to 9); DMA3_TXCHANNELCTRL : in std_logic_vector(0 to 31); DMA3_TXIRQTIMER : in std_logic_vector(0 to 9); INTERCONNECT_IMASK : in std_logic_vector(0 to 31); INTERCONNECT_TMPL_SEL : in std_logic_vector(0 to 31); MI_ARBCONFIG : in std_logic_vector(0 to 31); MI_BANKCONFLICT_MASK : in std_logic_vector(0 to 31); MI_CONTROL : in std_logic_vector(0 to 31); MI_ROWCONFLICT_MASK : in std_logic_vector(0 to 31); PPCDM_ASYNCMODE : in std_ulogic; PPCDS_ASYNCMODE : in std_ulogic; PPCM_ARBCONFIG : in std_logic_vector(0 to 31); PPCM_CONTROL : in std_logic_vector(0 to 31); PPCM_COUNTER : in std_logic_vector(0 to 31); PPCS0_ADDRMAP_TMPL0 : in std_logic_vector(0 to 31); PPCS0_ADDRMAP_TMPL1 : in std_logic_vector(0 to 31); PPCS0_ADDRMAP_TMPL2 : in std_logic_vector(0 to 31); PPCS0_ADDRMAP_TMPL3 : in std_logic_vector(0 to 31); PPCS0_CONTROL : in std_logic_vector(0 to 31); PPCS0_WIDTH_128N64 : in std_ulogic; PPCS1_ADDRMAP_TMPL0 : in std_logic_vector(0 to 31); PPCS1_ADDRMAP_TMPL1 : in std_logic_vector(0 to 31); PPCS1_ADDRMAP_TMPL2 : in std_logic_vector(0 to 31); PPCS1_ADDRMAP_TMPL3 : in std_logic_vector(0 to 31); PPCS1_CONTROL : in std_logic_vector(0 to 31); PPCS1_WIDTH_128N64 : in std_ulogic; XBAR_ADDRMAP_TMPL0 : in std_logic_vector(0 to 31); XBAR_ADDRMAP_TMPL1 : in std_logic_vector(0 to 31); XBAR_ADDRMAP_TMPL2 : in std_logic_vector(0 to 31); XBAR_ADDRMAP_TMPL3 : in std_logic_vector(0 to 31) ); end component; constant IN_DELAY : time := 1 ps; constant OUT_DELAY : time := 0 ps; constant CLK_DELAY : time := 0 ps; constant ZERO_DELAY : time := 0 ps; constant PATH_DELAY : VitalDelayType01 := (100 ps, 100 ps); signal DMA3_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA3_TXCHANNELCTRL); signal DMA3_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA3_CONTROL); signal DMA3_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA3_RXCHANNELCTRL); signal DMA3_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA3_TXIRQTIMER)(9 downto 0); signal DMA3_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA3_RXIRQTIMER)(9 downto 0); signal DMA2_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA2_TXCHANNELCTRL); signal DMA2_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA2_CONTROL); signal DMA2_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA2_RXCHANNELCTRL); signal DMA2_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA2_TXIRQTIMER)(9 downto 0); signal DMA2_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA2_RXIRQTIMER)(9 downto 0); signal PPCM_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCM_CONTROL); signal PPCM_COUNTER_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCM_COUNTER); signal PPCM_ARBCONFIG_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCM_ARBCONFIG); signal DMA1_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA1_RXIRQTIMER)(9 downto 0); signal DMA1_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA1_TXIRQTIMER)(9 downto 0); signal DMA1_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA1_RXCHANNELCTRL); signal DMA1_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA1_CONTROL); signal DMA1_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA1_TXCHANNELCTRL); signal DMA0_RXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA0_RXIRQTIMER)(9 downto 0); signal DMA0_TXIRQTIMER_BINARY : std_logic_vector(0 to 9) := To_StdLogicVector(DMA0_TXIRQTIMER)(9 downto 0); signal DMA0_RXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA0_RXCHANNELCTRL); signal DMA0_CONTROL_BINARY : std_logic_vector(0 to 7) := To_StdLogicVector(DMA0_CONTROL); signal DMA0_TXCHANNELCTRL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(DMA0_TXCHANNELCTRL); signal MI_ROWCONFLICT_MASK_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_ROWCONFLICT_MASK); signal MI_BANKCONFLICT_MASK_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_BANKCONFLICT_MASK); signal MI_ARBCONFIG_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_ARBCONFIG); signal MI_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(MI_CONTROL); signal APU_UDI0_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI0); signal APU_UDI1_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI1); signal APU_UDI2_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI2); signal APU_UDI3_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI3); signal APU_UDI4_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI4); signal APU_UDI5_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI5); signal APU_UDI6_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI6); signal APU_UDI7_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI7); signal APU_UDI8_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI8); signal APU_UDI9_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI9); signal APU_UDI10_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI10); signal APU_UDI11_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI11); signal APU_UDI12_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI12); signal APU_UDI13_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI13); signal APU_UDI14_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI14); signal APU_UDI15_BINARY : std_logic_vector(0 to 23) := To_StdLogicVector(APU_UDI15); signal APU_CONTROL_BINARY : std_logic_vector(0 to 16) := To_StdLogicVector(APU_CONTROL)(16 downto 0); signal INTERCONNECT_IMASK_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(INTERCONNECT_IMASK); signal XBAR_ADDRMAP_TMPL0_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL0); signal XBAR_ADDRMAP_TMPL1_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL1); signal XBAR_ADDRMAP_TMPL2_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL2); signal XBAR_ADDRMAP_TMPL3_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(XBAR_ADDRMAP_TMPL3); signal INTERCONNECT_TMPL_SEL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(INTERCONNECT_TMPL_SEL); signal PPCS0_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_CONTROL); signal PPCS0_WIDTH_128N64_BINARY : std_ulogic; signal PPCS0_ADDRMAP_TMPL0_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL0); signal PPCS0_ADDRMAP_TMPL1_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL1); signal PPCS0_ADDRMAP_TMPL2_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL2); signal PPCS0_ADDRMAP_TMPL3_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS0_ADDRMAP_TMPL3); signal PPCS1_CONTROL_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_CONTROL); signal PPCS1_WIDTH_128N64_BINARY : std_ulogic; signal PPCS1_ADDRMAP_TMPL0_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL0); signal PPCS1_ADDRMAP_TMPL1_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL1); signal PPCS1_ADDRMAP_TMPL2_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL2); signal PPCS1_ADDRMAP_TMPL3_BINARY : std_logic_vector(0 to 31) := To_StdLogicVector(PPCS1_ADDRMAP_TMPL3); signal PPCDM_ASYNCMODE_BINARY : std_ulogic; signal PPCDS_ASYNCMODE_BINARY : std_ulogic; signal DCR_AUTOLOCK_ENABLE_BINARY : std_ulogic; signal CLOCK_DELAY_BINARY : std_logic_vector(0 to 4); signal DMA0LLRSTENGINEACK_out : std_ulogic; signal DMA0LLRXDSTRDYN_out : std_ulogic; signal DMA0LLTXD_out : std_logic_vector(0 to 31); signal DMA0LLTXEOFN_out : std_ulogic; signal DMA0LLTXEOPN_out : std_ulogic; signal DMA0LLTXREM_out : std_logic_vector(0 to 3); signal DMA0LLTXSOFN_out : std_ulogic; signal DMA0LLTXSOPN_out : std_ulogic; signal DMA0LLTXSRCRDYN_out : std_ulogic; signal DMA0RXIRQ_out : std_ulogic; signal DMA0TXIRQ_out : std_ulogic; signal DMA1LLRSTENGINEACK_out : std_ulogic; signal DMA1LLRXDSTRDYN_out : std_ulogic; signal DMA1LLTXD_out : std_logic_vector(0 to 31); signal DMA1LLTXEOFN_out : std_ulogic; signal DMA1LLTXEOPN_out : std_ulogic; signal DMA1LLTXREM_out : std_logic_vector(0 to 3); signal DMA1LLTXSOFN_out : std_ulogic; signal DMA1LLTXSOPN_out : std_ulogic; signal DMA1LLTXSRCRDYN_out : std_ulogic; signal DMA1RXIRQ_out : std_ulogic; signal DMA1TXIRQ_out : std_ulogic; signal DMA2LLRSTENGINEACK_out : std_ulogic; signal DMA2LLRXDSTRDYN_out : std_ulogic; signal DMA2LLTXD_out : std_logic_vector(0 to 31); signal DMA2LLTXEOFN_out : std_ulogic; signal DMA2LLTXEOPN_out : std_ulogic; signal DMA2LLTXREM_out : std_logic_vector(0 to 3); signal DMA2LLTXSOFN_out : std_ulogic; signal DMA2LLTXSOPN_out : std_ulogic; signal DMA2LLTXSRCRDYN_out : std_ulogic; signal DMA2RXIRQ_out : std_ulogic; signal DMA2TXIRQ_out : std_ulogic; signal DMA3LLRSTENGINEACK_out : std_ulogic; signal DMA3LLRXDSTRDYN_out : std_ulogic; signal DMA3LLTXD_out : std_logic_vector(0 to 31); signal DMA3LLTXEOFN_out : std_ulogic; signal DMA3LLTXEOPN_out : std_ulogic; signal DMA3LLTXREM_out : std_logic_vector(0 to 3); signal DMA3LLTXSOFN_out : std_ulogic; signal DMA3LLTXSOPN_out : std_ulogic; signal DMA3LLTXSRCRDYN_out : std_ulogic; signal DMA3RXIRQ_out : std_ulogic; signal DMA3TXIRQ_out : std_ulogic; signal PPCDMDCRABUS_out : std_logic_vector(0 to 9); signal PPCDMDCRDBUSOUT_out : std_logic_vector(0 to 31); signal PPCDMDCRREAD_out : std_ulogic; signal PPCDMDCRUABUS_out : std_logic_vector(20 to 21); signal PPCDMDCRWRITE_out : std_ulogic; signal PPCMPLBABORT_out : std_ulogic; signal PPCMPLBABUS_out : std_logic_vector(0 to 31); signal PPCMPLBBE_out : std_logic_vector(0 to 15); signal PPCMPLBBUSLOCK_out : std_ulogic; signal PPCMPLBLOCKERR_out : std_ulogic; signal PPCMPLBPRIORITY_out : std_logic_vector(0 to 1); signal PPCMPLBRDBURST_out : std_ulogic; signal PPCMPLBREQUEST_out : std_ulogic; signal PPCMPLBRNW_out : std_ulogic; signal PPCMPLBSIZE_out : std_logic_vector(0 to 3); signal PPCMPLBTATTRIBUTE_out : std_logic_vector(0 to 15); signal PPCMPLBTYPE_out : std_logic_vector(0 to 2); signal PPCMPLBUABUS_out : std_logic_vector(28 to 31); signal PPCMPLBWRBURST_out : std_ulogic; signal PPCMPLBWRDBUS_out : std_logic_vector(0 to 127); signal PPCS0PLBADDRACK_out : std_ulogic; signal PPCS0PLBMBUSY_out : std_logic_vector(0 to 3); signal PPCS0PLBMIRQ_out : std_logic_vector(0 to 3); signal PPCS0PLBMRDERR_out : std_logic_vector(0 to 3); signal PPCS0PLBMWRERR_out : std_logic_vector(0 to 3); signal PPCS0PLBRDBTERM_out : std_ulogic; signal PPCS0PLBRDCOMP_out : std_ulogic; signal PPCS0PLBRDDACK_out : std_ulogic; signal PPCS0PLBRDDBUS_out : std_logic_vector(0 to 127); signal PPCS0PLBRDWDADDR_out : std_logic_vector(0 to 3); signal PPCS0PLBREARBITRATE_out : std_ulogic; signal PPCS0PLBSSIZE_out : std_logic_vector(0 to 1); signal PPCS0PLBWAIT_out : std_ulogic; signal PPCS0PLBWRBTERM_out : std_ulogic; signal PPCS0PLBWRCOMP_out : std_ulogic; signal PPCS0PLBWRDACK_out : std_ulogic; signal PPCS1PLBADDRACK_out : std_ulogic; signal PPCS1PLBMBUSY_out : std_logic_vector(0 to 3); signal PPCS1PLBMIRQ_out : std_logic_vector(0 to 3); signal PPCS1PLBMRDERR_out : std_logic_vector(0 to 3); signal PPCS1PLBMWRERR_out : std_logic_vector(0 to 3); signal PPCS1PLBRDBTERM_out : std_ulogic; signal PPCS1PLBRDCOMP_out : std_ulogic; signal PPCS1PLBRDDACK_out : std_ulogic; signal PPCS1PLBRDDBUS_out : std_logic_vector(0 to 127); signal PPCS1PLBRDWDADDR_out : std_logic_vector(0 to 3); signal PPCS1PLBREARBITRATE_out : std_ulogic; signal PPCS1PLBSSIZE_out : std_logic_vector(0 to 1); signal PPCS1PLBWAIT_out : std_ulogic; signal PPCS1PLBWRBTERM_out : std_ulogic; signal PPCS1PLBWRCOMP_out : std_ulogic; signal PPCS1PLBWRDACK_out : std_ulogic; signal APUFCMDECFPUOP_out : std_ulogic; signal APUFCMDECLDSTXFERSIZE_out : std_logic_vector(0 to 2); signal APUFCMDECLOAD_out : std_ulogic; signal APUFCMDECNONAUTON_out : std_ulogic; signal APUFCMDECSTORE_out : std_ulogic; signal APUFCMDECUDI_out : std_logic_vector(0 to 3); signal APUFCMDECUDIVALID_out : std_ulogic; signal APUFCMENDIAN_out : std_ulogic; signal APUFCMFLUSH_out : std_ulogic; signal APUFCMINSTRUCTION_out : std_logic_vector(0 to 31); signal APUFCMINSTRVALID_out : std_ulogic; signal APUFCMLOADBYTEADDR_out : std_logic_vector(0 to 3); signal APUFCMLOADDATA_out : std_logic_vector(0 to 127); signal APUFCMLOADDVALID_out : std_ulogic; signal APUFCMMSRFE0_out : std_ulogic; signal APUFCMMSRFE1_out : std_ulogic; signal APUFCMNEXTINSTRREADY_out : std_ulogic; signal APUFCMOPERANDVALID_out : std_ulogic; signal APUFCMRADATA_out : std_logic_vector(0 to 31); signal APUFCMRBDATA_out : std_logic_vector(0 to 31); signal APUFCMWRITEBACKOK_out : std_ulogic; signal C440CPMCORESLEEPREQ_out : std_ulogic; signal C440CPMDECIRPTREQ_out : std_ulogic; signal C440CPMFITIRPTREQ_out : std_ulogic; signal C440CPMMSRCE_out : std_ulogic; signal C440CPMMSREE_out : std_ulogic; signal C440CPMTIMERRESETREQ_out : std_ulogic; signal C440CPMWDIRPTREQ_out : std_ulogic; signal C440DBGSYSTEMCONTROL_out : std_logic_vector(0 to 7); signal C440JTGTDO_out : std_ulogic; signal C440JTGTDOEN_out : std_ulogic; signal C440MACHINECHECK_out : std_ulogic; signal C440RSTCHIPRESETREQ_out : std_ulogic; signal C440RSTCORERESETREQ_out : std_ulogic; signal C440RSTSYSTEMRESETREQ_out : std_ulogic; signal C440TRCBRANCHSTATUS_out : std_logic_vector(0 to 2); signal C440TRCCYCLE_out : std_ulogic; signal C440TRCEXECUTIONSTATUS_out : std_logic_vector(0 to 4); signal C440TRCTRACESTATUS_out : std_logic_vector(0 to 6); signal C440TRCTRIGGEREVENTOUT_out : std_ulogic; signal C440TRCTRIGGEREVENTTYPE_out : std_logic_vector(0 to 13); signal MIMCADDRESS_out : std_logic_vector(0 to 35); signal MIMCADDRESSVALID_out : std_ulogic; signal MIMCBANKCONFLICT_out : std_ulogic; signal MIMCBYTEENABLE_out : std_logic_vector(0 to 15); signal MIMCREADNOTWRITE_out : std_ulogic; signal MIMCROWCONFLICT_out : std_ulogic; signal MIMCWRITEDATA_out : std_logic_vector(0 to 127); signal MIMCWRITEDATAVALID_out : std_ulogic; signal PPCCPMINTERCONNECTBUSY_out : std_ulogic; signal PPCDSDCRACK_out : std_ulogic; signal PPCDSDCRTIMEOUTWAIT_out : std_ulogic; signal PPCDSDCRDBUSIN_out : std_logic_vector(0 to 31); signal PPCEICINTERCONNECTIRQ_out : std_ulogic; signal DMA0LLRSTENGINEACK_outdelay : std_ulogic; signal DMA0LLRXDSTRDYN_outdelay : std_ulogic; signal DMA0LLTXD_outdelay : std_logic_vector(0 to 31); signal DMA0LLTXEOFN_outdelay : std_ulogic; signal DMA0LLTXEOPN_outdelay : std_ulogic; signal DMA0LLTXREM_outdelay : std_logic_vector(0 to 3); signal DMA0LLTXSOFN_outdelay : std_ulogic; signal DMA0LLTXSOPN_outdelay : std_ulogic; signal DMA0LLTXSRCRDYN_outdelay : std_ulogic; signal DMA0RXIRQ_outdelay : std_ulogic; signal DMA0TXIRQ_outdelay : std_ulogic; signal DMA1LLRSTENGINEACK_outdelay : std_ulogic; signal DMA1LLRXDSTRDYN_outdelay : std_ulogic; signal DMA1LLTXD_outdelay : std_logic_vector(0 to 31); signal DMA1LLTXEOFN_outdelay : std_ulogic; signal DMA1LLTXEOPN_outdelay : std_ulogic; signal DMA1LLTXREM_outdelay : std_logic_vector(0 to 3); signal DMA1LLTXSOFN_outdelay : std_ulogic; signal DMA1LLTXSOPN_outdelay : std_ulogic; signal DMA1LLTXSRCRDYN_outdelay : std_ulogic; signal DMA1RXIRQ_outdelay : std_ulogic; signal DMA1TXIRQ_outdelay : std_ulogic; signal DMA2LLRSTENGINEACK_outdelay : std_ulogic; signal DMA2LLRXDSTRDYN_outdelay : std_ulogic; signal DMA2LLTXD_outdelay : std_logic_vector(0 to 31); signal DMA2LLTXEOFN_outdelay : std_ulogic; signal DMA2LLTXEOPN_outdelay : std_ulogic; signal DMA2LLTXREM_outdelay : std_logic_vector(0 to 3); signal DMA2LLTXSOFN_outdelay : std_ulogic; signal DMA2LLTXSOPN_outdelay : std_ulogic; signal DMA2LLTXSRCRDYN_outdelay : std_ulogic; signal DMA2RXIRQ_outdelay : std_ulogic; signal DMA2TXIRQ_outdelay : std_ulogic; signal DMA3LLRSTENGINEACK_outdelay : std_ulogic; signal DMA3LLRXDSTRDYN_outdelay : std_ulogic; signal DMA3LLTXD_outdelay : std_logic_vector(0 to 31); signal DMA3LLTXEOFN_outdelay : std_ulogic; signal DMA3LLTXEOPN_outdelay : std_ulogic; signal DMA3LLTXREM_outdelay : std_logic_vector(0 to 3); signal DMA3LLTXSOFN_outdelay : std_ulogic; signal DMA3LLTXSOPN_outdelay : std_ulogic; signal DMA3LLTXSRCRDYN_outdelay : std_ulogic; signal DMA3RXIRQ_outdelay : std_ulogic; signal DMA3TXIRQ_outdelay : std_ulogic; signal PPCDMDCRABUS_outdelay : std_logic_vector(0 to 9); signal PPCDMDCRDBUSOUT_outdelay : std_logic_vector(0 to 31); signal PPCDMDCRREAD_outdelay : std_ulogic; signal PPCDMDCRUABUS_outdelay : std_logic_vector(20 to 21); signal PPCDMDCRWRITE_outdelay : std_ulogic; signal PPCMPLBABORT_outdelay : std_ulogic; signal PPCMPLBABUS_outdelay : std_logic_vector(0 to 31); signal PPCMPLBBE_outdelay : std_logic_vector(0 to 15); signal PPCMPLBBUSLOCK_outdelay : std_ulogic; signal PPCMPLBLOCKERR_outdelay : std_ulogic; signal PPCMPLBPRIORITY_outdelay : std_logic_vector(0 to 1); signal PPCMPLBRDBURST_outdelay : std_ulogic; signal PPCMPLBREQUEST_outdelay : std_ulogic; signal PPCMPLBRNW_outdelay : std_ulogic; signal PPCMPLBSIZE_outdelay : std_logic_vector(0 to 3); signal PPCMPLBTATTRIBUTE_outdelay : std_logic_vector(0 to 15); signal PPCMPLBTYPE_outdelay : std_logic_vector(0 to 2); signal PPCMPLBUABUS_outdelay : std_logic_vector(28 to 31); signal PPCMPLBWRBURST_outdelay : std_ulogic; signal PPCMPLBWRDBUS_outdelay : std_logic_vector(0 to 127); signal PPCS0PLBADDRACK_outdelay : std_ulogic; signal PPCS0PLBMBUSY_outdelay : std_logic_vector(0 to 3); signal PPCS0PLBMIRQ_outdelay : std_logic_vector(0 to 3); signal PPCS0PLBMRDERR_outdelay : std_logic_vector(0 to 3); signal PPCS0PLBMWRERR_outdelay : std_logic_vector(0 to 3); signal PPCS0PLBRDBTERM_outdelay : std_ulogic; signal PPCS0PLBRDCOMP_outdelay : std_ulogic; signal PPCS0PLBRDDACK_outdelay : std_ulogic; signal PPCS0PLBRDDBUS_outdelay : std_logic_vector(0 to 127); signal PPCS0PLBRDWDADDR_outdelay : std_logic_vector(0 to 3); signal PPCS0PLBREARBITRATE_outdelay : std_ulogic; signal PPCS0PLBSSIZE_outdelay : std_logic_vector(0 to 1); signal PPCS0PLBWAIT_outdelay : std_ulogic; signal PPCS0PLBWRBTERM_outdelay : std_ulogic; signal PPCS0PLBWRCOMP_outdelay : std_ulogic; signal PPCS0PLBWRDACK_outdelay : std_ulogic; signal PPCS1PLBADDRACK_outdelay : std_ulogic; signal PPCS1PLBMBUSY_outdelay : std_logic_vector(0 to 3); signal PPCS1PLBMIRQ_outdelay : std_logic_vector(0 to 3); signal PPCS1PLBMRDERR_outdelay : std_logic_vector(0 to 3); signal PPCS1PLBMWRERR_outdelay : std_logic_vector(0 to 3); signal PPCS1PLBRDBTERM_outdelay : std_ulogic; signal PPCS1PLBRDCOMP_outdelay : std_ulogic; signal PPCS1PLBRDDACK_outdelay : std_ulogic; signal PPCS1PLBRDDBUS_outdelay : std_logic_vector(0 to 127); signal PPCS1PLBRDWDADDR_outdelay : std_logic_vector(0 to 3); signal PPCS1PLBREARBITRATE_outdelay : std_ulogic; signal PPCS1PLBSSIZE_outdelay : std_logic_vector(0 to 1); signal PPCS1PLBWAIT_outdelay : std_ulogic; signal PPCS1PLBWRBTERM_outdelay : std_ulogic; signal PPCS1PLBWRCOMP_outdelay : std_ulogic; signal PPCS1PLBWRDACK_outdelay : std_ulogic; signal APUFCMDECFPUOP_outdelay : std_ulogic; signal APUFCMDECLDSTXFERSIZE_outdelay : std_logic_vector(0 to 2); signal APUFCMDECLOAD_outdelay : std_ulogic; signal APUFCMDECNONAUTON_outdelay : std_ulogic; signal APUFCMDECSTORE_outdelay : std_ulogic; signal APUFCMDECUDI_outdelay : std_logic_vector(0 to 3); signal APUFCMDECUDIVALID_outdelay : std_ulogic; signal APUFCMENDIAN_outdelay : std_ulogic; signal APUFCMFLUSH_outdelay : std_ulogic; signal APUFCMINSTRUCTION_outdelay : std_logic_vector(0 to 31); signal APUFCMINSTRVALID_outdelay : std_ulogic; signal APUFCMLOADBYTEADDR_outdelay : std_logic_vector(0 to 3); signal APUFCMLOADDATA_outdelay : std_logic_vector(0 to 127); signal APUFCMLOADDVALID_outdelay : std_ulogic; signal APUFCMMSRFE0_outdelay : std_ulogic; signal APUFCMMSRFE1_outdelay : std_ulogic; signal APUFCMNEXTINSTRREADY_outdelay : std_ulogic; signal APUFCMOPERANDVALID_outdelay : std_ulogic; signal APUFCMRADATA_outdelay : std_logic_vector(0 to 31); signal APUFCMRBDATA_outdelay : std_logic_vector(0 to 31); signal APUFCMWRITEBACKOK_outdelay : std_ulogic; signal C440CPMCORESLEEPREQ_outdelay : std_ulogic; signal C440CPMDECIRPTREQ_outdelay : std_ulogic; signal C440CPMFITIRPTREQ_outdelay : std_ulogic; signal C440CPMMSRCE_outdelay : std_ulogic; signal C440CPMMSREE_outdelay : std_ulogic; signal C440CPMTIMERRESETREQ_outdelay : std_ulogic; signal C440CPMWDIRPTREQ_outdelay : std_ulogic; signal C440DBGSYSTEMCONTROL_outdelay : std_logic_vector(0 to 7); signal C440JTGTDO_outdelay : std_ulogic; signal C440JTGTDOEN_outdelay : std_ulogic; signal C440MACHINECHECK_outdelay : std_ulogic; signal C440RSTCHIPRESETREQ_outdelay : std_ulogic; signal C440RSTCORERESETREQ_outdelay : std_ulogic; signal C440RSTSYSTEMRESETREQ_outdelay : std_ulogic; signal C440TRCBRANCHSTATUS_outdelay : std_logic_vector(0 to 2); signal C440TRCCYCLE_outdelay : std_ulogic; signal C440TRCEXECUTIONSTATUS_outdelay : std_logic_vector(0 to 4); signal C440TRCTRACESTATUS_outdelay : std_logic_vector(0 to 6); signal C440TRCTRIGGEREVENTOUT_outdelay : std_ulogic; signal C440TRCTRIGGEREVENTTYPE_outdelay : std_logic_vector(0 to 13); signal MIMCADDRESS_outdelay : std_logic_vector(0 to 35); signal MIMCADDRESSVALID_outdelay : std_ulogic; signal MIMCBANKCONFLICT_outdelay : std_ulogic; signal MIMCBYTEENABLE_outdelay : std_logic_vector(0 to 15); signal MIMCREADNOTWRITE_outdelay : std_ulogic; signal MIMCROWCONFLICT_outdelay : std_ulogic; signal MIMCWRITEDATA_outdelay : std_logic_vector(0 to 127); signal MIMCWRITEDATAVALID_outdelay : std_ulogic; signal PPCCPMINTERCONNECTBUSY_outdelay : std_ulogic; signal PPCDSDCRACK_outdelay : std_ulogic; signal PPCDSDCRTIMEOUTWAIT_outdelay : std_ulogic; signal PPCDSDCRDBUSIN_outdelay : std_logic_vector(0 to 31); signal PPCEICINTERCONNECTIRQ_outdelay : std_ulogic; signal PLBPPCS0RNW_ipd : std_ulogic; signal PLBPPCS1RNW_ipd : std_ulogic; signal CPMDCRCLK_ipd : std_ulogic; signal CPMDMA0LLCLK_ipd : std_ulogic; signal CPMDMA1LLCLK_ipd : std_ulogic; signal CPMDMA2LLCLK_ipd : std_ulogic; signal CPMDMA3LLCLK_ipd : std_ulogic; signal CPMINTERCONNECTCLKNTO1_ipd : std_ulogic; signal CPMPPCMPLBCLK_ipd : std_ulogic; signal CPMPPCS0PLBCLK_ipd : std_ulogic; signal CPMPPCS1PLBCLK_ipd : std_ulogic; signal DCRPPCDMACK_ipd : std_ulogic; signal DCRPPCDMDBUSIN_ipd : std_logic_vector(0 to 31); signal DCRPPCDMTIMEOUTWAIT_ipd : std_ulogic; signal LLDMA0RSTENGINEREQ_ipd : std_ulogic; signal LLDMA0RXD_ipd : std_logic_vector(0 to 31); signal LLDMA0RXEOFN_ipd : std_ulogic; signal LLDMA0RXEOPN_ipd : std_ulogic; signal LLDMA0RXREM_ipd : std_logic_vector(0 to 3); signal LLDMA0RXSOFN_ipd : std_ulogic; signal LLDMA0RXSOPN_ipd : std_ulogic; signal LLDMA0RXSRCRDYN_ipd : std_ulogic; signal LLDMA0TXDSTRDYN_ipd : std_ulogic; signal LLDMA1RSTENGINEREQ_ipd : std_ulogic; signal LLDMA1RXD_ipd : std_logic_vector(0 to 31); signal LLDMA1RXEOFN_ipd : std_ulogic; signal LLDMA1RXEOPN_ipd : std_ulogic; signal LLDMA1RXREM_ipd : std_logic_vector(0 to 3); signal LLDMA1RXSOFN_ipd : std_ulogic; signal LLDMA1RXSOPN_ipd : std_ulogic; signal LLDMA1RXSRCRDYN_ipd : std_ulogic; signal LLDMA1TXDSTRDYN_ipd : std_ulogic; signal LLDMA2RSTENGINEREQ_ipd : std_ulogic; signal LLDMA2RXD_ipd : std_logic_vector(0 to 31); signal LLDMA2RXEOFN_ipd : std_ulogic; signal LLDMA2RXEOPN_ipd : std_ulogic; signal LLDMA2RXREM_ipd : std_logic_vector(0 to 3); signal LLDMA2RXSOFN_ipd : std_ulogic; signal LLDMA2RXSOPN_ipd : std_ulogic; signal LLDMA2RXSRCRDYN_ipd : std_ulogic; signal LLDMA2TXDSTRDYN_ipd : std_ulogic; signal LLDMA3RSTENGINEREQ_ipd : std_ulogic; signal LLDMA3RXD_ipd : std_logic_vector(0 to 31); signal LLDMA3RXEOFN_ipd : std_ulogic; signal LLDMA3RXEOPN_ipd : std_ulogic; signal LLDMA3RXREM_ipd : std_logic_vector(0 to 3); signal LLDMA3RXSOFN_ipd : std_ulogic; signal LLDMA3RXSOPN_ipd : std_ulogic; signal LLDMA3RXSRCRDYN_ipd : std_ulogic; signal LLDMA3TXDSTRDYN_ipd : std_ulogic; signal PLBPPCMADDRACK_ipd : std_ulogic; signal PLBPPCMMBUSY_ipd : std_ulogic; signal PLBPPCMMIRQ_ipd : std_ulogic; signal PLBPPCMMRDERR_ipd : std_ulogic; signal PLBPPCMMWRERR_ipd : std_ulogic; signal PLBPPCMRDBTERM_ipd : std_ulogic; signal PLBPPCMRDDACK_ipd : std_ulogic; signal PLBPPCMRDDBUS_ipd : std_logic_vector(0 to 127); signal PLBPPCMRDPENDPRI_ipd : std_logic_vector(0 to 1); signal PLBPPCMRDPENDREQ_ipd : std_ulogic; signal PLBPPCMRDWDADDR_ipd : std_logic_vector(0 to 3); signal PLBPPCMREARBITRATE_ipd : std_ulogic; signal PLBPPCMREQPRI_ipd : std_logic_vector(0 to 1); signal PLBPPCMSSIZE_ipd : std_logic_vector(0 to 1); signal PLBPPCMTIMEOUT_ipd : std_ulogic; signal PLBPPCMWRBTERM_ipd : std_ulogic; signal PLBPPCMWRDACK_ipd : std_ulogic; signal PLBPPCMWRPENDPRI_ipd : std_logic_vector(0 to 1); signal PLBPPCMWRPENDREQ_ipd : std_ulogic; signal PLBPPCS0ABORT_ipd : std_ulogic; signal PLBPPCS0ABUS_ipd : std_logic_vector(0 to 31); signal PLBPPCS0BE_ipd : std_logic_vector(0 to 15); signal PLBPPCS0BUSLOCK_ipd : std_ulogic; signal PLBPPCS0LOCKERR_ipd : std_ulogic; signal PLBPPCS0MASTERID_ipd : std_logic_vector(0 to 1); signal PLBPPCS0MSIZE_ipd : std_logic_vector(0 to 1); signal PLBPPCS0PAVALID_ipd : std_ulogic; signal PLBPPCS0RDBURST_ipd : std_ulogic; signal PLBPPCS0RDPENDPRI_ipd : std_logic_vector(0 to 1); signal PLBPPCS0RDPENDREQ_ipd : std_ulogic; signal PLBPPCS0RDPRIM_ipd : std_ulogic; signal PLBPPCS0REQPRI_ipd : std_logic_vector(0 to 1); signal PLBPPCS0SAVALID_ipd : std_ulogic; signal PLBPPCS0SIZE_ipd : std_logic_vector(0 to 3); signal PLBPPCS0TATTRIBUTE_ipd : std_logic_vector(0 to 15); signal PLBPPCS0TYPE_ipd : std_logic_vector(0 to 2); signal PLBPPCS0UABUS_ipd : std_logic_vector(28 to 31); signal PLBPPCS0WRBURST_ipd : std_ulogic; signal PLBPPCS0WRDBUS_ipd : std_logic_vector(0 to 127); signal PLBPPCS0WRPENDPRI_ipd : std_logic_vector(0 to 1); signal PLBPPCS0WRPENDREQ_ipd : std_ulogic; signal PLBPPCS0WRPRIM_ipd : std_ulogic; signal PLBPPCS1ABORT_ipd : std_ulogic; signal PLBPPCS1ABUS_ipd : std_logic_vector(0 to 31); signal PLBPPCS1BE_ipd : std_logic_vector(0 to 15); signal PLBPPCS1BUSLOCK_ipd : std_ulogic; signal PLBPPCS1LOCKERR_ipd : std_ulogic; signal PLBPPCS1MASTERID_ipd : std_logic_vector(0 to 1); signal PLBPPCS1MSIZE_ipd : std_logic_vector(0 to 1); signal PLBPPCS1PAVALID_ipd : std_ulogic; signal PLBPPCS1RDBURST_ipd : std_ulogic; signal PLBPPCS1RDPENDPRI_ipd : std_logic_vector(0 to 1); signal PLBPPCS1RDPENDREQ_ipd : std_ulogic; signal PLBPPCS1RDPRIM_ipd : std_ulogic; signal PLBPPCS1REQPRI_ipd : std_logic_vector(0 to 1); signal PLBPPCS1SAVALID_ipd : std_ulogic; signal PLBPPCS1SIZE_ipd : std_logic_vector(0 to 3); signal PLBPPCS1TATTRIBUTE_ipd : std_logic_vector(0 to 15); signal PLBPPCS1TYPE_ipd : std_logic_vector(0 to 2); signal PLBPPCS1UABUS_ipd : std_logic_vector(28 to 31); signal PLBPPCS1WRBURST_ipd : std_ulogic; signal PLBPPCS1WRDBUS_ipd : std_logic_vector(0 to 127); signal PLBPPCS1WRPENDPRI_ipd : std_logic_vector(0 to 1); signal PLBPPCS1WRPENDREQ_ipd : std_ulogic; signal PLBPPCS1WRPRIM_ipd : std_ulogic; signal TIEDCRBASEADDR_ipd : std_logic_vector(0 to 1); signal CPMC440CLK_ipd : std_ulogic; signal CPMC440CLKEN_ipd : std_ulogic; signal CPMC440CORECLOCKINACTIVE_ipd : std_ulogic; signal CPMC440TIMERCLOCK_ipd : std_ulogic; signal CPMFCMCLK_ipd : std_ulogic; signal CPMINTERCONNECTCLK_ipd : std_ulogic; signal CPMINTERCONNECTCLKEN_ipd : std_ulogic; signal CPMMCCLK_ipd : std_ulogic; signal DBGC440DEBUGHALT_ipd : std_ulogic; signal DBGC440SYSTEMSTATUS_ipd : std_logic_vector(0 to 4); signal DBGC440UNCONDDEBUGEVENT_ipd : std_ulogic; signal DCRPPCDSABUS_ipd : std_logic_vector(0 to 9); signal DCRPPCDSDBUSOUT_ipd : std_logic_vector(0 to 31); signal DCRPPCDSREAD_ipd : std_ulogic; signal DCRPPCDSWRITE_ipd : std_ulogic; signal EICC440CRITIRQ_ipd : std_ulogic; signal EICC440EXTIRQ_ipd : std_ulogic; signal FCMAPUCONFIRMINSTR_ipd : std_ulogic; signal FCMAPUCR_ipd : std_logic_vector(0 to 3); signal FCMAPUDONE_ipd : std_ulogic; signal FCMAPUEXCEPTION_ipd : std_ulogic; signal FCMAPUFPSCRFEX_ipd : std_ulogic; signal FCMAPURESULT_ipd : std_logic_vector(0 to 31); signal FCMAPURESULTVALID_ipd : std_ulogic; signal FCMAPUSLEEPNOTREADY_ipd : std_ulogic; signal FCMAPUSTOREDATA_ipd : std_logic_vector(0 to 127); signal JTGC440TCK_ipd : std_ulogic; signal JTGC440TDI_ipd : std_ulogic; signal JTGC440TMS_ipd : std_ulogic; signal JTGC440TRSTNEG_ipd : std_ulogic; signal MCMIADDRREADYTOACCEPT_ipd : std_ulogic; signal MCMIREADDATA_ipd : std_logic_vector(0 to 127); signal MCMIREADDATAERR_ipd : std_ulogic; signal MCMIREADDATAVALID_ipd : std_ulogic; signal RSTC440RESETCHIP_ipd : std_ulogic; signal RSTC440RESETCORE_ipd : std_ulogic; signal RSTC440RESETSYSTEM_ipd : std_ulogic; signal TIEC440DCURDLDCACHEPLBPRIO_ipd : std_logic_vector(0 to 1); signal TIEC440DCURDNONCACHEPLBPRIO_ipd : std_logic_vector(0 to 1); signal TIEC440DCURDTOUCHPLBPRIO_ipd : std_logic_vector(0 to 1); signal TIEC440DCURDURGENTPLBPRIO_ipd : std_logic_vector(0 to 1); signal TIEC440DCUWRFLUSHPLBPRIO_ipd : std_logic_vector(0 to 1); signal TIEC440DCUWRSTOREPLBPRIO_ipd : std_logic_vector(0 to 1); signal TIEC440DCUWRURGENTPLBPRIO_ipd : std_logic_vector(0 to 1); signal TIEC440ENDIANRESET_ipd : std_ulogic; signal TIEC440ERPNRESET_ipd : std_logic_vector(0 to 3); signal TIEC440ICURDFETCHPLBPRIO_ipd : std_logic_vector(0 to 1); signal TIEC440ICURDSPECPLBPRIO_ipd : std_logic_vector(0 to 1); signal TIEC440ICURDTOUCHPLBPRIO_ipd : std_logic_vector(0 to 1); signal TIEC440PIR_ipd : std_logic_vector(28 to 31); signal TIEC440PVR_ipd : std_logic_vector(28 to 31); signal TIEC440USERRESET_ipd : std_logic_vector(0 to 3); signal TRCC440TRACEDISABLE_ipd : std_ulogic; signal TRCC440TRIGGEREVENTIN_ipd : std_ulogic; signal PLBPPCS0RNW_indelay : std_ulogic; signal PLBPPCS1RNW_indelay : std_ulogic; signal CPMDCRCLK_indelay : std_ulogic; signal CPMDMA0LLCLK_indelay : std_ulogic; signal CPMDMA1LLCLK_indelay : std_ulogic; signal CPMDMA2LLCLK_indelay : std_ulogic; signal CPMDMA3LLCLK_indelay : std_ulogic; signal CPMINTERCONNECTCLKNTO1_indelay : std_ulogic; signal CPMPPCMPLBCLK_indelay : std_ulogic; signal CPMPPCS0PLBCLK_indelay : std_ulogic; signal CPMPPCS1PLBCLK_indelay : std_ulogic; signal DCRPPCDMACK_indelay : std_ulogic; signal DCRPPCDMDBUSIN_indelay : std_logic_vector(0 to 31); signal DCRPPCDMTIMEOUTWAIT_indelay : std_ulogic; signal LLDMA0RSTENGINEREQ_indelay : std_ulogic; signal LLDMA0RXD_indelay : std_logic_vector(0 to 31); signal LLDMA0RXEOFN_indelay : std_ulogic; signal LLDMA0RXEOPN_indelay : std_ulogic; signal LLDMA0RXREM_indelay : std_logic_vector(0 to 3); signal LLDMA0RXSOFN_indelay : std_ulogic; signal LLDMA0RXSOPN_indelay : std_ulogic; signal LLDMA0RXSRCRDYN_indelay : std_ulogic; signal LLDMA0TXDSTRDYN_indelay : std_ulogic; signal LLDMA1RSTENGINEREQ_indelay : std_ulogic; signal LLDMA1RXD_indelay : std_logic_vector(0 to 31); signal LLDMA1RXEOFN_indelay : std_ulogic; signal LLDMA1RXEOPN_indelay : std_ulogic; signal LLDMA1RXREM_indelay : std_logic_vector(0 to 3); signal LLDMA1RXSOFN_indelay : std_ulogic; signal LLDMA1RXSOPN_indelay : std_ulogic; signal LLDMA1RXSRCRDYN_indelay : std_ulogic; signal LLDMA1TXDSTRDYN_indelay : std_ulogic; signal LLDMA2RSTENGINEREQ_indelay : std_ulogic; signal LLDMA2RXD_indelay : std_logic_vector(0 to 31); signal LLDMA2RXEOFN_indelay : std_ulogic; signal LLDMA2RXEOPN_indelay : std_ulogic; signal LLDMA2RXREM_indelay : std_logic_vector(0 to 3); signal LLDMA2RXSOFN_indelay : std_ulogic; signal LLDMA2RXSOPN_indelay : std_ulogic; signal LLDMA2RXSRCRDYN_indelay : std_ulogic; signal LLDMA2TXDSTRDYN_indelay : std_ulogic; signal LLDMA3RSTENGINEREQ_indelay : std_ulogic; signal LLDMA3RXD_indelay : std_logic_vector(0 to 31); signal LLDMA3RXEOFN_indelay : std_ulogic; signal LLDMA3RXEOPN_indelay : std_ulogic; signal LLDMA3RXREM_indelay : std_logic_vector(0 to 3); signal LLDMA3RXSOFN_indelay : std_ulogic; signal LLDMA3RXSOPN_indelay : std_ulogic; signal LLDMA3RXSRCRDYN_indelay : std_ulogic; signal LLDMA3TXDSTRDYN_indelay : std_ulogic; signal PLBPPCMADDRACK_indelay : std_ulogic; signal PLBPPCMMBUSY_indelay : std_ulogic; signal PLBPPCMMIRQ_indelay : std_ulogic; signal PLBPPCMMRDERR_indelay : std_ulogic; signal PLBPPCMMWRERR_indelay : std_ulogic; signal PLBPPCMRDBTERM_indelay : std_ulogic; signal PLBPPCMRDDACK_indelay : std_ulogic; signal PLBPPCMRDDBUS_indelay : std_logic_vector(0 to 127); signal PLBPPCMRDPENDPRI_indelay : std_logic_vector(0 to 1); signal PLBPPCMRDPENDREQ_indelay : std_ulogic; signal PLBPPCMRDWDADDR_indelay : std_logic_vector(0 to 3); signal PLBPPCMREARBITRATE_indelay : std_ulogic; signal PLBPPCMREQPRI_indelay : std_logic_vector(0 to 1); signal PLBPPCMSSIZE_indelay : std_logic_vector(0 to 1); signal PLBPPCMTIMEOUT_indelay : std_ulogic; signal PLBPPCMWRBTERM_indelay : std_ulogic; signal PLBPPCMWRDACK_indelay : std_ulogic; signal PLBPPCMWRPENDPRI_indelay : std_logic_vector(0 to 1); signal PLBPPCMWRPENDREQ_indelay : std_ulogic; signal PLBPPCS0ABORT_indelay : std_ulogic; signal PLBPPCS0ABUS_indelay : std_logic_vector(0 to 31); signal PLBPPCS0BE_indelay : std_logic_vector(0 to 15); signal PLBPPCS0BUSLOCK_indelay : std_ulogic; signal PLBPPCS0LOCKERR_indelay : std_ulogic; signal PLBPPCS0MASTERID_indelay : std_logic_vector(0 to 1); signal PLBPPCS0MSIZE_indelay : std_logic_vector(0 to 1); signal PLBPPCS0PAVALID_indelay : std_ulogic; signal PLBPPCS0RDBURST_indelay : std_ulogic; signal PLBPPCS0RDPENDPRI_indelay : std_logic_vector(0 to 1); signal PLBPPCS0RDPENDREQ_indelay : std_ulogic; signal PLBPPCS0RDPRIM_indelay : std_ulogic; signal PLBPPCS0REQPRI_indelay : std_logic_vector(0 to 1); signal PLBPPCS0SAVALID_indelay : std_ulogic; signal PLBPPCS0SIZE_indelay : std_logic_vector(0 to 3); signal PLBPPCS0TATTRIBUTE_indelay : std_logic_vector(0 to 15); signal PLBPPCS0TYPE_indelay : std_logic_vector(0 to 2); signal PLBPPCS0UABUS_indelay : std_logic_vector(28 to 31); signal PLBPPCS0WRBURST_indelay : std_ulogic; signal PLBPPCS0WRDBUS_indelay : std_logic_vector(0 to 127); signal PLBPPCS0WRPENDPRI_indelay : std_logic_vector(0 to 1); signal PLBPPCS0WRPENDREQ_indelay : std_ulogic; signal PLBPPCS0WRPRIM_indelay : std_ulogic; signal PLBPPCS1ABORT_indelay : std_ulogic; signal PLBPPCS1ABUS_indelay : std_logic_vector(0 to 31); signal PLBPPCS1BE_indelay : std_logic_vector(0 to 15); signal PLBPPCS1BUSLOCK_indelay : std_ulogic; signal PLBPPCS1LOCKERR_indelay : std_ulogic; signal PLBPPCS1MASTERID_indelay : std_logic_vector(0 to 1); signal PLBPPCS1MSIZE_indelay : std_logic_vector(0 to 1); signal PLBPPCS1PAVALID_indelay : std_ulogic; signal PLBPPCS1RDBURST_indelay : std_ulogic; signal PLBPPCS1RDPENDPRI_indelay : std_logic_vector(0 to 1); signal PLBPPCS1RDPENDREQ_indelay : std_ulogic; signal PLBPPCS1RDPRIM_indelay : std_ulogic; signal PLBPPCS1REQPRI_indelay : std_logic_vector(0 to 1); signal PLBPPCS1SAVALID_indelay : std_ulogic; signal PLBPPCS1SIZE_indelay : std_logic_vector(0 to 3); signal PLBPPCS1TATTRIBUTE_indelay : std_logic_vector(0 to 15); signal PLBPPCS1TYPE_indelay : std_logic_vector(0 to 2); signal PLBPPCS1UABUS_indelay : std_logic_vector(28 to 31); signal PLBPPCS1WRBURST_indelay : std_ulogic; signal PLBPPCS1WRDBUS_indelay : std_logic_vector(0 to 127); signal PLBPPCS1WRPENDPRI_indelay : std_logic_vector(0 to 1); signal PLBPPCS1WRPENDREQ_indelay : std_ulogic; signal PLBPPCS1WRPRIM_indelay : std_ulogic; signal TIEDCRBASEADDR_indelay : std_logic_vector(0 to 1); signal CPMC440CLK_indelay : std_ulogic; signal CPMC440CLKEN_indelay : std_ulogic; signal CPMC440CORECLOCKINACTIVE_indelay : std_ulogic; signal CPMC440TIMERCLOCK_indelay : std_ulogic; signal CPMFCMCLK_indelay : std_ulogic; signal CPMINTERCONNECTCLK_indelay : std_ulogic; signal CPMINTERCONNECTCLKEN_indelay : std_ulogic; signal CPMMCCLK_indelay : std_ulogic; signal DBGC440DEBUGHALT_indelay : std_ulogic; signal DBGC440SYSTEMSTATUS_indelay : std_logic_vector(0 to 4); signal DBGC440UNCONDDEBUGEVENT_indelay : std_ulogic; signal DCRPPCDSABUS_indelay : std_logic_vector(0 to 9); signal DCRPPCDSDBUSOUT_indelay : std_logic_vector(0 to 31); signal DCRPPCDSREAD_indelay : std_ulogic; signal DCRPPCDSWRITE_indelay : std_ulogic; signal EICC440CRITIRQ_indelay : std_ulogic; signal EICC440EXTIRQ_indelay : std_ulogic; signal FCMAPUCONFIRMINSTR_indelay : std_ulogic; signal FCMAPUCR_indelay : std_logic_vector(0 to 3); signal FCMAPUDONE_indelay : std_ulogic; signal FCMAPUEXCEPTION_indelay : std_ulogic; signal FCMAPUFPSCRFEX_indelay : std_ulogic; signal FCMAPURESULT_indelay : std_logic_vector(0 to 31); signal FCMAPURESULTVALID_indelay : std_ulogic; signal FCMAPUSLEEPNOTREADY_indelay : std_ulogic; signal FCMAPUSTOREDATA_indelay : std_logic_vector(0 to 127); signal JTGC440TCK_indelay : std_ulogic; signal JTGC440TDI_indelay : std_ulogic; signal JTGC440TMS_indelay : std_ulogic; signal JTGC440TRSTNEG_indelay : std_ulogic; signal MCMIADDRREADYTOACCEPT_indelay : std_ulogic; signal MCMIREADDATA_indelay : std_logic_vector(0 to 127); signal MCMIREADDATAERR_indelay : std_ulogic; signal MCMIREADDATAVALID_indelay : std_ulogic; signal RSTC440RESETCHIP_indelay : std_ulogic; signal RSTC440RESETCORE_indelay : std_ulogic; signal RSTC440RESETSYSTEM_indelay : std_ulogic; signal TIEC440DCURDLDCACHEPLBPRIO_indelay : std_logic_vector(0 to 1); signal TIEC440DCURDNONCACHEPLBPRIO_indelay : std_logic_vector(0 to 1); signal TIEC440DCURDTOUCHPLBPRIO_indelay : std_logic_vector(0 to 1); signal TIEC440DCURDURGENTPLBPRIO_indelay : std_logic_vector(0 to 1); signal TIEC440DCUWRFLUSHPLBPRIO_indelay : std_logic_vector(0 to 1); signal TIEC440DCUWRSTOREPLBPRIO_indelay : std_logic_vector(0 to 1); signal TIEC440DCUWRURGENTPLBPRIO_indelay : std_logic_vector(0 to 1); signal TIEC440ENDIANRESET_indelay : std_ulogic; signal TIEC440ERPNRESET_indelay : std_logic_vector(0 to 3); signal TIEC440ICURDFETCHPLBPRIO_indelay : std_logic_vector(0 to 1); signal TIEC440ICURDSPECPLBPRIO_indelay : std_logic_vector(0 to 1); signal TIEC440ICURDTOUCHPLBPRIO_indelay : std_logic_vector(0 to 1); signal TIEC440PIR_indelay : std_logic_vector(28 to 31); signal TIEC440PVR_indelay : std_logic_vector(28 to 31); signal TIEC440USERRESET_indelay : std_logic_vector(0 to 3); signal TRCC440TRACEDISABLE_indelay : std_ulogic; signal TRCC440TRIGGEREVENTIN_indelay : std_ulogic; begin APUFCMDECFPUOP_out <= APUFCMDECFPUOP_outdelay after OUT_DELAY; APUFCMDECLDSTXFERSIZE_out <= APUFCMDECLDSTXFERSIZE_outdelay after OUT_DELAY; APUFCMDECLOAD_out <= APUFCMDECLOAD_outdelay after OUT_DELAY; APUFCMDECNONAUTON_out <= APUFCMDECNONAUTON_outdelay after OUT_DELAY; APUFCMDECSTORE_out <= APUFCMDECSTORE_outdelay after OUT_DELAY; APUFCMDECUDIVALID_out <= APUFCMDECUDIVALID_outdelay after OUT_DELAY; APUFCMDECUDI_out <= APUFCMDECUDI_outdelay after OUT_DELAY; APUFCMENDIAN_out <= APUFCMENDIAN_outdelay after OUT_DELAY; APUFCMFLUSH_out <= APUFCMFLUSH_outdelay after OUT_DELAY; APUFCMINSTRUCTION_out <= APUFCMINSTRUCTION_outdelay after OUT_DELAY; APUFCMINSTRVALID_out <= APUFCMINSTRVALID_outdelay after OUT_DELAY; APUFCMLOADBYTEADDR_out <= APUFCMLOADBYTEADDR_outdelay after OUT_DELAY; APUFCMLOADDATA_out <= APUFCMLOADDATA_outdelay after OUT_DELAY; APUFCMLOADDVALID_out <= APUFCMLOADDVALID_outdelay after OUT_DELAY; APUFCMMSRFE0_out <= APUFCMMSRFE0_outdelay after OUT_DELAY; APUFCMMSRFE1_out <= APUFCMMSRFE1_outdelay after OUT_DELAY; APUFCMNEXTINSTRREADY_out <= APUFCMNEXTINSTRREADY_outdelay after OUT_DELAY; APUFCMOPERANDVALID_out <= APUFCMOPERANDVALID_outdelay after OUT_DELAY; APUFCMRADATA_out <= APUFCMRADATA_outdelay after OUT_DELAY; APUFCMRBDATA_out <= APUFCMRBDATA_outdelay after OUT_DELAY; APUFCMWRITEBACKOK_out <= APUFCMWRITEBACKOK_outdelay after OUT_DELAY; C440CPMCORESLEEPREQ_out <= C440CPMCORESLEEPREQ_outdelay after OUT_DELAY; C440CPMDECIRPTREQ_out <= C440CPMDECIRPTREQ_outdelay after OUT_DELAY; C440CPMFITIRPTREQ_out <= C440CPMFITIRPTREQ_outdelay after OUT_DELAY; C440CPMMSRCE_out <= C440CPMMSRCE_outdelay after OUT_DELAY; C440CPMMSREE_out <= C440CPMMSREE_outdelay after OUT_DELAY; C440CPMTIMERRESETREQ_out <= C440CPMTIMERRESETREQ_outdelay after OUT_DELAY; C440CPMWDIRPTREQ_out <= C440CPMWDIRPTREQ_outdelay after OUT_DELAY; C440DBGSYSTEMCONTROL_out <= C440DBGSYSTEMCONTROL_outdelay after OUT_DELAY; C440JTGTDOEN_out <= C440JTGTDOEN_outdelay after OUT_DELAY; C440JTGTDO_out <= C440JTGTDO_outdelay after OUT_DELAY; C440MACHINECHECK_out <= C440MACHINECHECK_outdelay after OUT_DELAY; C440RSTCHIPRESETREQ_out <= C440RSTCHIPRESETREQ_outdelay after OUT_DELAY; C440RSTCORERESETREQ_out <= C440RSTCORERESETREQ_outdelay after OUT_DELAY; C440RSTSYSTEMRESETREQ_out <= C440RSTSYSTEMRESETREQ_outdelay after OUT_DELAY; C440TRCBRANCHSTATUS_out <= C440TRCBRANCHSTATUS_outdelay after OUT_DELAY; C440TRCCYCLE_out <= C440TRCCYCLE_outdelay after OUT_DELAY; C440TRCEXECUTIONSTATUS_out <= C440TRCEXECUTIONSTATUS_outdelay after OUT_DELAY; C440TRCTRACESTATUS_out <= C440TRCTRACESTATUS_outdelay after OUT_DELAY; C440TRCTRIGGEREVENTOUT_out <= C440TRCTRIGGEREVENTOUT_outdelay after OUT_DELAY; C440TRCTRIGGEREVENTTYPE_out <= C440TRCTRIGGEREVENTTYPE_outdelay after OUT_DELAY; DMA0LLRSTENGINEACK_out <= DMA0LLRSTENGINEACK_outdelay after OUT_DELAY; DMA0LLRXDSTRDYN_out <= DMA0LLRXDSTRDYN_outdelay after OUT_DELAY; DMA0LLTXD_out <= DMA0LLTXD_outdelay after OUT_DELAY; DMA0LLTXEOFN_out <= DMA0LLTXEOFN_outdelay after OUT_DELAY; DMA0LLTXEOPN_out <= DMA0LLTXEOPN_outdelay after OUT_DELAY; DMA0LLTXREM_out <= DMA0LLTXREM_outdelay after OUT_DELAY; DMA0LLTXSOFN_out <= DMA0LLTXSOFN_outdelay after OUT_DELAY; DMA0LLTXSOPN_out <= DMA0LLTXSOPN_outdelay after OUT_DELAY; DMA0LLTXSRCRDYN_out <= DMA0LLTXSRCRDYN_outdelay after OUT_DELAY; DMA0RXIRQ_out <= DMA0RXIRQ_outdelay after OUT_DELAY; DMA0TXIRQ_out <= DMA0TXIRQ_outdelay after OUT_DELAY; DMA1LLRSTENGINEACK_out <= DMA1LLRSTENGINEACK_outdelay after OUT_DELAY; DMA1LLRXDSTRDYN_out <= DMA1LLRXDSTRDYN_outdelay after OUT_DELAY; DMA1LLTXD_out <= DMA1LLTXD_outdelay after OUT_DELAY; DMA1LLTXEOFN_out <= DMA1LLTXEOFN_outdelay after OUT_DELAY; DMA1LLTXEOPN_out <= DMA1LLTXEOPN_outdelay after OUT_DELAY; DMA1LLTXREM_out <= DMA1LLTXREM_outdelay after OUT_DELAY; DMA1LLTXSOFN_out <= DMA1LLTXSOFN_outdelay after OUT_DELAY; DMA1LLTXSOPN_out <= DMA1LLTXSOPN_outdelay after OUT_DELAY; DMA1LLTXSRCRDYN_out <= DMA1LLTXSRCRDYN_outdelay after OUT_DELAY; DMA1RXIRQ_out <= DMA1RXIRQ_outdelay after OUT_DELAY; DMA1TXIRQ_out <= DMA1TXIRQ_outdelay after OUT_DELAY; DMA2LLRSTENGINEACK_out <= DMA2LLRSTENGINEACK_outdelay after OUT_DELAY; DMA2LLRXDSTRDYN_out <= DMA2LLRXDSTRDYN_outdelay after OUT_DELAY; DMA2LLTXD_out <= DMA2LLTXD_outdelay after OUT_DELAY; DMA2LLTXEOFN_out <= DMA2LLTXEOFN_outdelay after OUT_DELAY; DMA2LLTXEOPN_out <= DMA2LLTXEOPN_outdelay after OUT_DELAY; DMA2LLTXREM_out <= DMA2LLTXREM_outdelay after OUT_DELAY; DMA2LLTXSOFN_out <= DMA2LLTXSOFN_outdelay after OUT_DELAY; DMA2LLTXSOPN_out <= DMA2LLTXSOPN_outdelay after OUT_DELAY; DMA2LLTXSRCRDYN_out <= DMA2LLTXSRCRDYN_outdelay after OUT_DELAY; DMA2RXIRQ_out <= DMA2RXIRQ_outdelay after OUT_DELAY; DMA2TXIRQ_out <= DMA2TXIRQ_outdelay after OUT_DELAY; DMA3LLRSTENGINEACK_out <= DMA3LLRSTENGINEACK_outdelay after OUT_DELAY; DMA3LLRXDSTRDYN_out <= DMA3LLRXDSTRDYN_outdelay after OUT_DELAY; DMA3LLTXD_out <= DMA3LLTXD_outdelay after OUT_DELAY; DMA3LLTXEOFN_out <= DMA3LLTXEOFN_outdelay after OUT_DELAY; DMA3LLTXEOPN_out <= DMA3LLTXEOPN_outdelay after OUT_DELAY; DMA3LLTXREM_out <= DMA3LLTXREM_outdelay after OUT_DELAY; DMA3LLTXSOFN_out <= DMA3LLTXSOFN_outdelay after OUT_DELAY; DMA3LLTXSOPN_out <= DMA3LLTXSOPN_outdelay after OUT_DELAY; DMA3LLTXSRCRDYN_out <= DMA3LLTXSRCRDYN_outdelay after OUT_DELAY; DMA3RXIRQ_out <= DMA3RXIRQ_outdelay after OUT_DELAY; DMA3TXIRQ_out <= DMA3TXIRQ_outdelay after OUT_DELAY; MIMCADDRESSVALID_out <= MIMCADDRESSVALID_outdelay after OUT_DELAY; MIMCADDRESS_out <= MIMCADDRESS_outdelay after OUT_DELAY; MIMCBANKCONFLICT_out <= MIMCBANKCONFLICT_outdelay after OUT_DELAY; MIMCBYTEENABLE_out <= MIMCBYTEENABLE_outdelay after OUT_DELAY; MIMCREADNOTWRITE_out <= MIMCREADNOTWRITE_outdelay after OUT_DELAY; MIMCROWCONFLICT_out <= MIMCROWCONFLICT_outdelay after OUT_DELAY; MIMCWRITEDATAVALID_out <= MIMCWRITEDATAVALID_outdelay after OUT_DELAY; MIMCWRITEDATA_out <= MIMCWRITEDATA_outdelay after OUT_DELAY; PPCCPMINTERCONNECTBUSY_out <= PPCCPMINTERCONNECTBUSY_outdelay after OUT_DELAY; PPCDMDCRABUS_out <= PPCDMDCRABUS_outdelay after OUT_DELAY; PPCDMDCRDBUSOUT_out <= PPCDMDCRDBUSOUT_outdelay after OUT_DELAY; PPCDMDCRREAD_out <= PPCDMDCRREAD_outdelay after OUT_DELAY; PPCDMDCRUABUS_out <= PPCDMDCRUABUS_outdelay after OUT_DELAY; PPCDMDCRWRITE_out <= PPCDMDCRWRITE_outdelay after OUT_DELAY; PPCDSDCRACK_out <= PPCDSDCRACK_outdelay after OUT_DELAY; PPCDSDCRDBUSIN_out <= PPCDSDCRDBUSIN_outdelay after OUT_DELAY; PPCDSDCRTIMEOUTWAIT_out <= PPCDSDCRTIMEOUTWAIT_outdelay after OUT_DELAY; PPCEICINTERCONNECTIRQ_out <= PPCEICINTERCONNECTIRQ_outdelay after OUT_DELAY; PPCMPLBABORT_out <= PPCMPLBABORT_outdelay after OUT_DELAY; PPCMPLBABUS_out <= PPCMPLBABUS_outdelay after OUT_DELAY; PPCMPLBBE_out <= PPCMPLBBE_outdelay after OUT_DELAY; PPCMPLBBUSLOCK_out <= PPCMPLBBUSLOCK_outdelay after OUT_DELAY; PPCMPLBLOCKERR_out <= PPCMPLBLOCKERR_outdelay after OUT_DELAY; PPCMPLBPRIORITY_out <= PPCMPLBPRIORITY_outdelay after OUT_DELAY; PPCMPLBRDBURST_out <= PPCMPLBRDBURST_outdelay after OUT_DELAY; PPCMPLBREQUEST_out <= PPCMPLBREQUEST_outdelay after OUT_DELAY; PPCMPLBRNW_out <= PPCMPLBRNW_outdelay after OUT_DELAY; PPCMPLBSIZE_out <= PPCMPLBSIZE_outdelay after OUT_DELAY; PPCMPLBTATTRIBUTE_out <= PPCMPLBTATTRIBUTE_outdelay after OUT_DELAY; PPCMPLBTYPE_out <= PPCMPLBTYPE_outdelay after OUT_DELAY; PPCMPLBUABUS_out <= PPCMPLBUABUS_outdelay after OUT_DELAY; PPCMPLBWRBURST_out <= PPCMPLBWRBURST_outdelay after OUT_DELAY; PPCMPLBWRDBUS_out <= PPCMPLBWRDBUS_outdelay after OUT_DELAY; PPCS0PLBADDRACK_out <= PPCS0PLBADDRACK_outdelay after OUT_DELAY; PPCS0PLBMBUSY_out <= PPCS0PLBMBUSY_outdelay after OUT_DELAY; PPCS0PLBMIRQ_out <= PPCS0PLBMIRQ_outdelay after OUT_DELAY; PPCS0PLBMRDERR_out <= PPCS0PLBMRDERR_outdelay after OUT_DELAY; PPCS0PLBMWRERR_out <= PPCS0PLBMWRERR_outdelay after OUT_DELAY; PPCS0PLBRDBTERM_out <= PPCS0PLBRDBTERM_outdelay after OUT_DELAY; PPCS0PLBRDCOMP_out <= PPCS0PLBRDCOMP_outdelay after OUT_DELAY; PPCS0PLBRDDACK_out <= PPCS0PLBRDDACK_outdelay after OUT_DELAY; PPCS0PLBRDDBUS_out <= PPCS0PLBRDDBUS_outdelay after OUT_DELAY; PPCS0PLBRDWDADDR_out <= PPCS0PLBRDWDADDR_outdelay after OUT_DELAY; PPCS0PLBREARBITRATE_out <= PPCS0PLBREARBITRATE_outdelay after OUT_DELAY; PPCS0PLBSSIZE_out <= PPCS0PLBSSIZE_outdelay after OUT_DELAY; PPCS0PLBWAIT_out <= PPCS0PLBWAIT_outdelay after OUT_DELAY; PPCS0PLBWRBTERM_out <= PPCS0PLBWRBTERM_outdelay after OUT_DELAY; PPCS0PLBWRCOMP_out <= PPCS0PLBWRCOMP_outdelay after OUT_DELAY; PPCS0PLBWRDACK_out <= PPCS0PLBWRDACK_outdelay after OUT_DELAY; PPCS1PLBADDRACK_out <= PPCS1PLBADDRACK_outdelay after OUT_DELAY; PPCS1PLBMBUSY_out <= PPCS1PLBMBUSY_outdelay after OUT_DELAY; PPCS1PLBMIRQ_out <= PPCS1PLBMIRQ_outdelay after OUT_DELAY; PPCS1PLBMRDERR_out <= PPCS1PLBMRDERR_outdelay after OUT_DELAY; PPCS1PLBMWRERR_out <= PPCS1PLBMWRERR_outdelay after OUT_DELAY; PPCS1PLBRDBTERM_out <= PPCS1PLBRDBTERM_outdelay after OUT_DELAY; PPCS1PLBRDCOMP_out <= PPCS1PLBRDCOMP_outdelay after OUT_DELAY; PPCS1PLBRDDACK_out <= PPCS1PLBRDDACK_outdelay after OUT_DELAY; PPCS1PLBRDDBUS_out <= PPCS1PLBRDDBUS_outdelay after OUT_DELAY; PPCS1PLBRDWDADDR_out <= PPCS1PLBRDWDADDR_outdelay after OUT_DELAY; PPCS1PLBREARBITRATE_out <= PPCS1PLBREARBITRATE_outdelay after OUT_DELAY; PPCS1PLBSSIZE_out <= PPCS1PLBSSIZE_outdelay after OUT_DELAY; PPCS1PLBWAIT_out <= PPCS1PLBWAIT_outdelay after OUT_DELAY; PPCS1PLBWRBTERM_out <= PPCS1PLBWRBTERM_outdelay after OUT_DELAY; PPCS1PLBWRCOMP_out <= PPCS1PLBWRCOMP_outdelay after OUT_DELAY; PPCS1PLBWRDACK_out <= PPCS1PLBWRDACK_outdelay after OUT_DELAY; CPMC440CLK_ipd <= CPMC440CLK after ZERO_DELAY; CPMC440TIMERCLOCK_ipd <= CPMC440TIMERCLOCK after ZERO_DELAY; CPMDCRCLK_ipd <= CPMDCRCLK after ZERO_DELAY; CPMDMA0LLCLK_ipd <= CPMDMA0LLCLK after ZERO_DELAY; CPMDMA1LLCLK_ipd <= CPMDMA1LLCLK after ZERO_DELAY; CPMDMA2LLCLK_ipd <= CPMDMA2LLCLK after ZERO_DELAY; CPMDMA3LLCLK_ipd <= CPMDMA3LLCLK after ZERO_DELAY; CPMFCMCLK_ipd <= CPMFCMCLK after ZERO_DELAY; CPMINTERCONNECTCLK_ipd <= CPMINTERCONNECTCLK after ZERO_DELAY; CPMMCCLK_ipd <= CPMMCCLK after ZERO_DELAY; CPMPPCMPLBCLK_ipd <= CPMPPCMPLBCLK after ZERO_DELAY; CPMPPCS0PLBCLK_ipd <= CPMPPCS0PLBCLK after ZERO_DELAY; CPMPPCS1PLBCLK_ipd <= CPMPPCS1PLBCLK after ZERO_DELAY; JTGC440TCK_ipd <= JTGC440TCK after ZERO_DELAY; CPMC440CLKEN_ipd <= CPMC440CLKEN after ZERO_DELAY; CPMC440CORECLOCKINACTIVE_ipd <= CPMC440CORECLOCKINACTIVE after ZERO_DELAY; CPMINTERCONNECTCLKEN_ipd <= CPMINTERCONNECTCLKEN after ZERO_DELAY; CPMINTERCONNECTCLKNTO1_ipd <= CPMINTERCONNECTCLKNTO1 after ZERO_DELAY; DBGC440DEBUGHALT_ipd <= DBGC440DEBUGHALT after ZERO_DELAY; DBGC440SYSTEMSTATUS_ipd <= DBGC440SYSTEMSTATUS after ZERO_DELAY; DBGC440UNCONDDEBUGEVENT_ipd <= DBGC440UNCONDDEBUGEVENT after ZERO_DELAY; DCRPPCDMACK_ipd <= DCRPPCDMACK after ZERO_DELAY; DCRPPCDMDBUSIN_ipd <= DCRPPCDMDBUSIN after ZERO_DELAY; DCRPPCDMTIMEOUTWAIT_ipd <= DCRPPCDMTIMEOUTWAIT after ZERO_DELAY; DCRPPCDSABUS_ipd <= DCRPPCDSABUS after ZERO_DELAY; DCRPPCDSDBUSOUT_ipd <= DCRPPCDSDBUSOUT after ZERO_DELAY; DCRPPCDSREAD_ipd <= DCRPPCDSREAD after ZERO_DELAY; DCRPPCDSWRITE_ipd <= DCRPPCDSWRITE after ZERO_DELAY; EICC440CRITIRQ_ipd <= EICC440CRITIRQ after ZERO_DELAY; EICC440EXTIRQ_ipd <= EICC440EXTIRQ after ZERO_DELAY; FCMAPUCONFIRMINSTR_ipd <= FCMAPUCONFIRMINSTR after ZERO_DELAY; FCMAPUCR_ipd <= FCMAPUCR after ZERO_DELAY; FCMAPUDONE_ipd <= FCMAPUDONE after ZERO_DELAY; FCMAPUEXCEPTION_ipd <= FCMAPUEXCEPTION after ZERO_DELAY; FCMAPUFPSCRFEX_ipd <= FCMAPUFPSCRFEX after ZERO_DELAY; FCMAPURESULTVALID_ipd <= FCMAPURESULTVALID after ZERO_DELAY; FCMAPURESULT_ipd <= FCMAPURESULT after ZERO_DELAY; FCMAPUSLEEPNOTREADY_ipd <= FCMAPUSLEEPNOTREADY after ZERO_DELAY; FCMAPUSTOREDATA_ipd <= FCMAPUSTOREDATA after ZERO_DELAY; JTGC440TDI_ipd <= JTGC440TDI after ZERO_DELAY; JTGC440TMS_ipd <= JTGC440TMS after ZERO_DELAY; JTGC440TRSTNEG_ipd <= JTGC440TRSTNEG after ZERO_DELAY; LLDMA0RSTENGINEREQ_ipd <= LLDMA0RSTENGINEREQ after ZERO_DELAY; LLDMA0RXD_ipd <= LLDMA0RXD after ZERO_DELAY; LLDMA0RXEOFN_ipd <= LLDMA0RXEOFN after ZERO_DELAY; LLDMA0RXEOPN_ipd <= LLDMA0RXEOPN after ZERO_DELAY; LLDMA0RXREM_ipd <= LLDMA0RXREM after ZERO_DELAY; LLDMA0RXSOFN_ipd <= LLDMA0RXSOFN after ZERO_DELAY; LLDMA0RXSOPN_ipd <= LLDMA0RXSOPN after ZERO_DELAY; LLDMA0RXSRCRDYN_ipd <= LLDMA0RXSRCRDYN after ZERO_DELAY; LLDMA0TXDSTRDYN_ipd <= LLDMA0TXDSTRDYN after ZERO_DELAY; LLDMA1RSTENGINEREQ_ipd <= LLDMA1RSTENGINEREQ after ZERO_DELAY; LLDMA1RXD_ipd <= LLDMA1RXD after ZERO_DELAY; LLDMA1RXEOFN_ipd <= LLDMA1RXEOFN after ZERO_DELAY; LLDMA1RXEOPN_ipd <= LLDMA1RXEOPN after ZERO_DELAY; LLDMA1RXREM_ipd <= LLDMA1RXREM after ZERO_DELAY; LLDMA1RXSOFN_ipd <= LLDMA1RXSOFN after ZERO_DELAY; LLDMA1RXSOPN_ipd <= LLDMA1RXSOPN after ZERO_DELAY; LLDMA1RXSRCRDYN_ipd <= LLDMA1RXSRCRDYN after ZERO_DELAY; LLDMA1TXDSTRDYN_ipd <= LLDMA1TXDSTRDYN after ZERO_DELAY; LLDMA2RSTENGINEREQ_ipd <= LLDMA2RSTENGINEREQ after ZERO_DELAY; LLDMA2RXD_ipd <= LLDMA2RXD after ZERO_DELAY; LLDMA2RXEOFN_ipd <= LLDMA2RXEOFN after ZERO_DELAY; LLDMA2RXEOPN_ipd <= LLDMA2RXEOPN after ZERO_DELAY; LLDMA2RXREM_ipd <= LLDMA2RXREM after ZERO_DELAY; LLDMA2RXSOFN_ipd <= LLDMA2RXSOFN after ZERO_DELAY; LLDMA2RXSOPN_ipd <= LLDMA2RXSOPN after ZERO_DELAY; LLDMA2RXSRCRDYN_ipd <= LLDMA2RXSRCRDYN after ZERO_DELAY; LLDMA2TXDSTRDYN_ipd <= LLDMA2TXDSTRDYN after ZERO_DELAY; LLDMA3RSTENGINEREQ_ipd <= LLDMA3RSTENGINEREQ after ZERO_DELAY; LLDMA3RXD_ipd <= LLDMA3RXD after ZERO_DELAY; LLDMA3RXEOFN_ipd <= LLDMA3RXEOFN after ZERO_DELAY; LLDMA3RXEOPN_ipd <= LLDMA3RXEOPN after ZERO_DELAY; LLDMA3RXREM_ipd <= LLDMA3RXREM after ZERO_DELAY; LLDMA3RXSOFN_ipd <= LLDMA3RXSOFN after ZERO_DELAY; LLDMA3RXSOPN_ipd <= LLDMA3RXSOPN after ZERO_DELAY; LLDMA3RXSRCRDYN_ipd <= LLDMA3RXSRCRDYN after ZERO_DELAY; LLDMA3TXDSTRDYN_ipd <= LLDMA3TXDSTRDYN after ZERO_DELAY; MCMIADDRREADYTOACCEPT_ipd <= MCMIADDRREADYTOACCEPT after ZERO_DELAY; MCMIREADDATAERR_ipd <= MCMIREADDATAERR after ZERO_DELAY; MCMIREADDATAVALID_ipd <= MCMIREADDATAVALID after ZERO_DELAY; MCMIREADDATA_ipd <= MCMIREADDATA after ZERO_DELAY; PLBPPCMADDRACK_ipd <= PLBPPCMADDRACK after ZERO_DELAY; PLBPPCMMBUSY_ipd <= PLBPPCMMBUSY after ZERO_DELAY; PLBPPCMMIRQ_ipd <= PLBPPCMMIRQ after ZERO_DELAY; PLBPPCMMRDERR_ipd <= PLBPPCMMRDERR after ZERO_DELAY; PLBPPCMMWRERR_ipd <= PLBPPCMMWRERR after ZERO_DELAY; PLBPPCMRDBTERM_ipd <= PLBPPCMRDBTERM after ZERO_DELAY; PLBPPCMRDDACK_ipd <= PLBPPCMRDDACK after ZERO_DELAY; PLBPPCMRDDBUS_ipd <= PLBPPCMRDDBUS after ZERO_DELAY; PLBPPCMRDPENDPRI_ipd <= PLBPPCMRDPENDPRI after ZERO_DELAY; PLBPPCMRDPENDREQ_ipd <= PLBPPCMRDPENDREQ after ZERO_DELAY; PLBPPCMRDWDADDR_ipd <= PLBPPCMRDWDADDR after ZERO_DELAY; PLBPPCMREARBITRATE_ipd <= PLBPPCMREARBITRATE after ZERO_DELAY; PLBPPCMREQPRI_ipd <= PLBPPCMREQPRI after ZERO_DELAY; PLBPPCMSSIZE_ipd <= PLBPPCMSSIZE after ZERO_DELAY; PLBPPCMTIMEOUT_ipd <= PLBPPCMTIMEOUT after ZERO_DELAY; PLBPPCMWRBTERM_ipd <= PLBPPCMWRBTERM after ZERO_DELAY; PLBPPCMWRDACK_ipd <= PLBPPCMWRDACK after ZERO_DELAY; PLBPPCMWRPENDPRI_ipd <= PLBPPCMWRPENDPRI after ZERO_DELAY; PLBPPCMWRPENDREQ_ipd <= PLBPPCMWRPENDREQ after ZERO_DELAY; PLBPPCS0ABORT_ipd <= PLBPPCS0ABORT after ZERO_DELAY; PLBPPCS0ABUS_ipd <= PLBPPCS0ABUS after ZERO_DELAY; PLBPPCS0BE_ipd <= PLBPPCS0BE after ZERO_DELAY; PLBPPCS0BUSLOCK_ipd <= PLBPPCS0BUSLOCK after ZERO_DELAY; PLBPPCS0LOCKERR_ipd <= PLBPPCS0LOCKERR after ZERO_DELAY; PLBPPCS0MASTERID_ipd <= PLBPPCS0MASTERID after ZERO_DELAY; PLBPPCS0MSIZE_ipd <= PLBPPCS0MSIZE after ZERO_DELAY; PLBPPCS0PAVALID_ipd <= PLBPPCS0PAVALID after ZERO_DELAY; PLBPPCS0RDBURST_ipd <= PLBPPCS0RDBURST after ZERO_DELAY; PLBPPCS0RDPENDPRI_ipd <= PLBPPCS0RDPENDPRI after ZERO_DELAY; PLBPPCS0RDPENDREQ_ipd <= PLBPPCS0RDPENDREQ after ZERO_DELAY; PLBPPCS0RDPRIM_ipd <= PLBPPCS0RDPRIM after ZERO_DELAY; PLBPPCS0REQPRI_ipd <= PLBPPCS0REQPRI after ZERO_DELAY; PLBPPCS0RNW_ipd <= PLBPPCS0RNW after ZERO_DELAY; PLBPPCS0SAVALID_ipd <= PLBPPCS0SAVALID after ZERO_DELAY; PLBPPCS0SIZE_ipd <= PLBPPCS0SIZE after ZERO_DELAY; PLBPPCS0TATTRIBUTE_ipd <= PLBPPCS0TATTRIBUTE after ZERO_DELAY; PLBPPCS0TYPE_ipd <= PLBPPCS0TYPE after ZERO_DELAY; PLBPPCS0UABUS_ipd <= PLBPPCS0UABUS after ZERO_DELAY; PLBPPCS0WRBURST_ipd <= PLBPPCS0WRBURST after ZERO_DELAY; PLBPPCS0WRDBUS_ipd <= PLBPPCS0WRDBUS after ZERO_DELAY; PLBPPCS0WRPENDPRI_ipd <= PLBPPCS0WRPENDPRI after ZERO_DELAY; PLBPPCS0WRPENDREQ_ipd <= PLBPPCS0WRPENDREQ after ZERO_DELAY; PLBPPCS0WRPRIM_ipd <= PLBPPCS0WRPRIM after ZERO_DELAY; PLBPPCS1ABORT_ipd <= PLBPPCS1ABORT after ZERO_DELAY; PLBPPCS1ABUS_ipd <= PLBPPCS1ABUS after ZERO_DELAY; PLBPPCS1BE_ipd <= PLBPPCS1BE after ZERO_DELAY; PLBPPCS1BUSLOCK_ipd <= PLBPPCS1BUSLOCK after ZERO_DELAY; PLBPPCS1LOCKERR_ipd <= PLBPPCS1LOCKERR after ZERO_DELAY; PLBPPCS1MASTERID_ipd <= PLBPPCS1MASTERID after ZERO_DELAY; PLBPPCS1MSIZE_ipd <= PLBPPCS1MSIZE after ZERO_DELAY; PLBPPCS1PAVALID_ipd <= PLBPPCS1PAVALID after ZERO_DELAY; PLBPPCS1RDBURST_ipd <= PLBPPCS1RDBURST after ZERO_DELAY; PLBPPCS1RDPENDPRI_ipd <= PLBPPCS1RDPENDPRI after ZERO_DELAY; PLBPPCS1RDPENDREQ_ipd <= PLBPPCS1RDPENDREQ after ZERO_DELAY; PLBPPCS1RDPRIM_ipd <= PLBPPCS1RDPRIM after ZERO_DELAY; PLBPPCS1REQPRI_ipd <= PLBPPCS1REQPRI after ZERO_DELAY; PLBPPCS1RNW_ipd <= PLBPPCS1RNW after ZERO_DELAY; PLBPPCS1SAVALID_ipd <= PLBPPCS1SAVALID after ZERO_DELAY; PLBPPCS1SIZE_ipd <= PLBPPCS1SIZE after ZERO_DELAY; PLBPPCS1TATTRIBUTE_ipd <= PLBPPCS1TATTRIBUTE after ZERO_DELAY; PLBPPCS1TYPE_ipd <= PLBPPCS1TYPE after ZERO_DELAY; PLBPPCS1UABUS_ipd <= PLBPPCS1UABUS after ZERO_DELAY; PLBPPCS1WRBURST_ipd <= PLBPPCS1WRBURST after ZERO_DELAY; PLBPPCS1WRDBUS_ipd <= PLBPPCS1WRDBUS after ZERO_DELAY; PLBPPCS1WRPENDPRI_ipd <= PLBPPCS1WRPENDPRI after ZERO_DELAY; PLBPPCS1WRPENDREQ_ipd <= PLBPPCS1WRPENDREQ after ZERO_DELAY; PLBPPCS1WRPRIM_ipd <= PLBPPCS1WRPRIM after ZERO_DELAY; RSTC440RESETCHIP_ipd <= RSTC440RESETCHIP after ZERO_DELAY; RSTC440RESETCORE_ipd <= RSTC440RESETCORE after ZERO_DELAY; RSTC440RESETSYSTEM_ipd <= RSTC440RESETSYSTEM after ZERO_DELAY; TIEC440DCURDLDCACHEPLBPRIO_ipd <= TIEC440DCURDLDCACHEPLBPRIO after ZERO_DELAY; TIEC440DCURDNONCACHEPLBPRIO_ipd <= TIEC440DCURDNONCACHEPLBPRIO after ZERO_DELAY; TIEC440DCURDTOUCHPLBPRIO_ipd <= TIEC440DCURDTOUCHPLBPRIO after ZERO_DELAY; TIEC440DCURDURGENTPLBPRIO_ipd <= TIEC440DCURDURGENTPLBPRIO after ZERO_DELAY; TIEC440DCUWRFLUSHPLBPRIO_ipd <= TIEC440DCUWRFLUSHPLBPRIO after ZERO_DELAY; TIEC440DCUWRSTOREPLBPRIO_ipd <= TIEC440DCUWRSTOREPLBPRIO after ZERO_DELAY; TIEC440DCUWRURGENTPLBPRIO_ipd <= TIEC440DCUWRURGENTPLBPRIO after ZERO_DELAY; TIEC440ENDIANRESET_ipd <= TIEC440ENDIANRESET after ZERO_DELAY; TIEC440ERPNRESET_ipd <= TIEC440ERPNRESET after ZERO_DELAY; TIEC440ICURDFETCHPLBPRIO_ipd <= TIEC440ICURDFETCHPLBPRIO after ZERO_DELAY; TIEC440ICURDSPECPLBPRIO_ipd <= TIEC440ICURDSPECPLBPRIO after ZERO_DELAY; TIEC440ICURDTOUCHPLBPRIO_ipd <= TIEC440ICURDTOUCHPLBPRIO after ZERO_DELAY; TIEC440PIR_ipd <= TIEC440PIR after ZERO_DELAY; TIEC440PVR_ipd <= TIEC440PVR after ZERO_DELAY; TIEC440USERRESET_ipd <= TIEC440USERRESET after ZERO_DELAY; TIEDCRBASEADDR_ipd <= TIEDCRBASEADDR after ZERO_DELAY; TRCC440TRACEDISABLE_ipd <= TRCC440TRACEDISABLE after ZERO_DELAY; TRCC440TRIGGEREVENTIN_ipd <= TRCC440TRIGGEREVENTIN after ZERO_DELAY; CPMC440CLK_indelay <= CPMC440CLK_ipd after CLK_DELAY; CPMC440TIMERCLOCK_indelay <= CPMC440TIMERCLOCK_ipd after CLK_DELAY; CPMDCRCLK_indelay <= CPMDCRCLK_ipd after CLK_DELAY; CPMDMA0LLCLK_indelay <= CPMDMA0LLCLK_ipd after CLK_DELAY; CPMDMA1LLCLK_indelay <= CPMDMA1LLCLK_ipd after CLK_DELAY; CPMDMA2LLCLK_indelay <= CPMDMA2LLCLK_ipd after CLK_DELAY; CPMDMA3LLCLK_indelay <= CPMDMA3LLCLK_ipd after CLK_DELAY; CPMFCMCLK_indelay <= CPMFCMCLK_ipd after CLK_DELAY; CPMINTERCONNECTCLK_indelay <= CPMINTERCONNECTCLK_ipd after CLK_DELAY; CPMMCCLK_indelay <= CPMMCCLK_ipd after CLK_DELAY; CPMPPCMPLBCLK_indelay <= CPMPPCMPLBCLK_ipd after CLK_DELAY; CPMPPCS0PLBCLK_indelay <= CPMPPCS0PLBCLK_ipd after CLK_DELAY; CPMPPCS1PLBCLK_indelay <= CPMPPCS1PLBCLK_ipd after CLK_DELAY; JTGC440TCK_indelay <= JTGC440TCK_ipd after CLK_DELAY; CPMC440CLKEN_indelay <= CPMC440CLKEN_ipd after IN_DELAY; CPMC440CORECLOCKINACTIVE_indelay <= CPMC440CORECLOCKINACTIVE_ipd after IN_DELAY; CPMINTERCONNECTCLKEN_indelay <= CPMINTERCONNECTCLKEN_ipd after IN_DELAY; CPMINTERCONNECTCLKNTO1_indelay <= CPMINTERCONNECTCLKNTO1_ipd after IN_DELAY; DBGC440DEBUGHALT_indelay <= DBGC440DEBUGHALT_ipd after IN_DELAY; DBGC440SYSTEMSTATUS_indelay <= DBGC440SYSTEMSTATUS_ipd after IN_DELAY; DBGC440UNCONDDEBUGEVENT_indelay <= DBGC440UNCONDDEBUGEVENT_ipd after IN_DELAY; DCRPPCDMACK_indelay <= DCRPPCDMACK_ipd after IN_DELAY; DCRPPCDMDBUSIN_indelay <= DCRPPCDMDBUSIN_ipd after IN_DELAY; DCRPPCDMTIMEOUTWAIT_indelay <= DCRPPCDMTIMEOUTWAIT_ipd after IN_DELAY; DCRPPCDSABUS_indelay <= DCRPPCDSABUS_ipd after IN_DELAY; DCRPPCDSDBUSOUT_indelay <= DCRPPCDSDBUSOUT_ipd after IN_DELAY; DCRPPCDSREAD_indelay <= DCRPPCDSREAD_ipd after IN_DELAY; DCRPPCDSWRITE_indelay <= DCRPPCDSWRITE_ipd after IN_DELAY; EICC440CRITIRQ_indelay <= EICC440CRITIRQ_ipd after IN_DELAY; EICC440EXTIRQ_indelay <= EICC440EXTIRQ_ipd after IN_DELAY; FCMAPUCONFIRMINSTR_indelay <= FCMAPUCONFIRMINSTR_ipd after IN_DELAY; FCMAPUCR_indelay <= FCMAPUCR_ipd after IN_DELAY; FCMAPUDONE_indelay <= FCMAPUDONE_ipd after IN_DELAY; FCMAPUEXCEPTION_indelay <= FCMAPUEXCEPTION_ipd after IN_DELAY; FCMAPUFPSCRFEX_indelay <= FCMAPUFPSCRFEX_ipd after IN_DELAY; FCMAPURESULTVALID_indelay <= FCMAPURESULTVALID_ipd after IN_DELAY; FCMAPURESULT_indelay <= FCMAPURESULT_ipd after IN_DELAY; FCMAPUSLEEPNOTREADY_indelay <= FCMAPUSLEEPNOTREADY_ipd after IN_DELAY; FCMAPUSTOREDATA_indelay <= FCMAPUSTOREDATA_ipd after IN_DELAY; JTGC440TDI_indelay <= JTGC440TDI_ipd after IN_DELAY; JTGC440TMS_indelay <= JTGC440TMS_ipd after IN_DELAY; JTGC440TRSTNEG_indelay <= JTGC440TRSTNEG_ipd after IN_DELAY; LLDMA0RSTENGINEREQ_indelay <= LLDMA0RSTENGINEREQ_ipd after IN_DELAY; LLDMA0RXD_indelay <= LLDMA0RXD_ipd after IN_DELAY; LLDMA0RXEOFN_indelay <= LLDMA0RXEOFN_ipd after IN_DELAY; LLDMA0RXEOPN_indelay <= LLDMA0RXEOPN_ipd after IN_DELAY; LLDMA0RXREM_indelay <= LLDMA0RXREM_ipd after IN_DELAY; LLDMA0RXSOFN_indelay <= LLDMA0RXSOFN_ipd after IN_DELAY; LLDMA0RXSOPN_indelay <= LLDMA0RXSOPN_ipd after IN_DELAY; LLDMA0RXSRCRDYN_indelay <= LLDMA0RXSRCRDYN_ipd after IN_DELAY; LLDMA0TXDSTRDYN_indelay <= LLDMA0TXDSTRDYN_ipd after IN_DELAY; LLDMA1RSTENGINEREQ_indelay <= LLDMA1RSTENGINEREQ_ipd after IN_DELAY; LLDMA1RXD_indelay <= LLDMA1RXD_ipd after IN_DELAY; LLDMA1RXEOFN_indelay <= LLDMA1RXEOFN_ipd after IN_DELAY; LLDMA1RXEOPN_indelay <= LLDMA1RXEOPN_ipd after IN_DELAY; LLDMA1RXREM_indelay <= LLDMA1RXREM_ipd after IN_DELAY; LLDMA1RXSOFN_indelay <= LLDMA1RXSOFN_ipd after IN_DELAY; LLDMA1RXSOPN_indelay <= LLDMA1RXSOPN_ipd after IN_DELAY; LLDMA1RXSRCRDYN_indelay <= LLDMA1RXSRCRDYN_ipd after IN_DELAY; LLDMA1TXDSTRDYN_indelay <= LLDMA1TXDSTRDYN_ipd after IN_DELAY; LLDMA2RSTENGINEREQ_indelay <= LLDMA2RSTENGINEREQ_ipd after IN_DELAY; LLDMA2RXD_indelay <= LLDMA2RXD_ipd after IN_DELAY; LLDMA2RXEOFN_indelay <= LLDMA2RXEOFN_ipd after IN_DELAY; LLDMA2RXEOPN_indelay <= LLDMA2RXEOPN_ipd after IN_DELAY; LLDMA2RXREM_indelay <= LLDMA2RXREM_ipd after IN_DELAY; LLDMA2RXSOFN_indelay <= LLDMA2RXSOFN_ipd after IN_DELAY; LLDMA2RXSOPN_indelay <= LLDMA2RXSOPN_ipd after IN_DELAY; LLDMA2RXSRCRDYN_indelay <= LLDMA2RXSRCRDYN_ipd after IN_DELAY; LLDMA2TXDSTRDYN_indelay <= LLDMA2TXDSTRDYN_ipd after IN_DELAY; LLDMA3RSTENGINEREQ_indelay <= LLDMA3RSTENGINEREQ_ipd after IN_DELAY; LLDMA3RXD_indelay <= LLDMA3RXD_ipd after IN_DELAY; LLDMA3RXEOFN_indelay <= LLDMA3RXEOFN_ipd after IN_DELAY; LLDMA3RXEOPN_indelay <= LLDMA3RXEOPN_ipd after IN_DELAY; LLDMA3RXREM_indelay <= LLDMA3RXREM_ipd after IN_DELAY; LLDMA3RXSOFN_indelay <= LLDMA3RXSOFN_ipd after IN_DELAY; LLDMA3RXSOPN_indelay <= LLDMA3RXSOPN_ipd after IN_DELAY; LLDMA3RXSRCRDYN_indelay <= LLDMA3RXSRCRDYN_ipd after IN_DELAY; LLDMA3TXDSTRDYN_indelay <= LLDMA3TXDSTRDYN_ipd after IN_DELAY; MCMIADDRREADYTOACCEPT_indelay <= MCMIADDRREADYTOACCEPT_ipd after IN_DELAY; MCMIREADDATAERR_indelay <= MCMIREADDATAERR_ipd after IN_DELAY; MCMIREADDATAVALID_indelay <= MCMIREADDATAVALID_ipd after IN_DELAY; MCMIREADDATA_indelay <= MCMIREADDATA_ipd after IN_DELAY; PLBPPCMADDRACK_indelay <= PLBPPCMADDRACK_ipd after IN_DELAY; PLBPPCMMBUSY_indelay <= PLBPPCMMBUSY_ipd after IN_DELAY; PLBPPCMMIRQ_indelay <= PLBPPCMMIRQ_ipd after IN_DELAY; PLBPPCMMRDERR_indelay <= PLBPPCMMRDERR_ipd after IN_DELAY; PLBPPCMMWRERR_indelay <= PLBPPCMMWRERR_ipd after IN_DELAY; PLBPPCMRDBTERM_indelay <= PLBPPCMRDBTERM_ipd after IN_DELAY; PLBPPCMRDDACK_indelay <= PLBPPCMRDDACK_ipd after IN_DELAY; PLBPPCMRDDBUS_indelay <= PLBPPCMRDDBUS_ipd after IN_DELAY; PLBPPCMRDPENDPRI_indelay <= PLBPPCMRDPENDPRI_ipd after IN_DELAY; PLBPPCMRDPENDREQ_indelay <= PLBPPCMRDPENDREQ_ipd after IN_DELAY; PLBPPCMRDWDADDR_indelay <= PLBPPCMRDWDADDR_ipd after IN_DELAY; PLBPPCMREARBITRATE_indelay <= PLBPPCMREARBITRATE_ipd after IN_DELAY; PLBPPCMREQPRI_indelay <= PLBPPCMREQPRI_ipd after IN_DELAY; PLBPPCMSSIZE_indelay <= PLBPPCMSSIZE_ipd after IN_DELAY; PLBPPCMTIMEOUT_indelay <= PLBPPCMTIMEOUT_ipd after IN_DELAY; PLBPPCMWRBTERM_indelay <= PLBPPCMWRBTERM_ipd after IN_DELAY; PLBPPCMWRDACK_indelay <= PLBPPCMWRDACK_ipd after IN_DELAY; PLBPPCMWRPENDPRI_indelay <= PLBPPCMWRPENDPRI_ipd after IN_DELAY; PLBPPCMWRPENDREQ_indelay <= PLBPPCMWRPENDREQ_ipd after IN_DELAY; PLBPPCS0ABORT_indelay <= PLBPPCS0ABORT_ipd after IN_DELAY; PLBPPCS0ABUS_indelay <= PLBPPCS0ABUS_ipd after IN_DELAY; PLBPPCS0BE_indelay <= PLBPPCS0BE_ipd after IN_DELAY; PLBPPCS0BUSLOCK_indelay <= PLBPPCS0BUSLOCK_ipd after IN_DELAY; PLBPPCS0LOCKERR_indelay <= PLBPPCS0LOCKERR_ipd after IN_DELAY; PLBPPCS0MASTERID_indelay <= PLBPPCS0MASTERID_ipd after IN_DELAY; PLBPPCS0MSIZE_indelay <= PLBPPCS0MSIZE_ipd after IN_DELAY; PLBPPCS0PAVALID_indelay <= PLBPPCS0PAVALID_ipd after IN_DELAY; PLBPPCS0RDBURST_indelay <= PLBPPCS0RDBURST_ipd after IN_DELAY; PLBPPCS0RDPENDPRI_indelay <= PLBPPCS0RDPENDPRI_ipd after IN_DELAY; PLBPPCS0RDPENDREQ_indelay <= PLBPPCS0RDPENDREQ_ipd after IN_DELAY; PLBPPCS0RDPRIM_indelay <= PLBPPCS0RDPRIM_ipd after IN_DELAY; PLBPPCS0REQPRI_indelay <= PLBPPCS0REQPRI_ipd after IN_DELAY; PLBPPCS0RNW_indelay <= PLBPPCS0RNW_ipd after IN_DELAY; PLBPPCS0SAVALID_indelay <= PLBPPCS0SAVALID_ipd after IN_DELAY; PLBPPCS0SIZE_indelay <= PLBPPCS0SIZE_ipd after IN_DELAY; PLBPPCS0TATTRIBUTE_indelay <= PLBPPCS0TATTRIBUTE_ipd after IN_DELAY; PLBPPCS0TYPE_indelay <= PLBPPCS0TYPE_ipd after IN_DELAY; PLBPPCS0UABUS_indelay <= PLBPPCS0UABUS_ipd after IN_DELAY; PLBPPCS0WRBURST_indelay <= PLBPPCS0WRBURST_ipd after IN_DELAY; PLBPPCS0WRDBUS_indelay <= PLBPPCS0WRDBUS_ipd after IN_DELAY; PLBPPCS0WRPENDPRI_indelay <= PLBPPCS0WRPENDPRI_ipd after IN_DELAY; PLBPPCS0WRPENDREQ_indelay <= PLBPPCS0WRPENDREQ_ipd after IN_DELAY; PLBPPCS0WRPRIM_indelay <= PLBPPCS0WRPRIM_ipd after IN_DELAY; PLBPPCS1ABORT_indelay <= PLBPPCS1ABORT_ipd after IN_DELAY; PLBPPCS1ABUS_indelay <= PLBPPCS1ABUS_ipd after IN_DELAY; PLBPPCS1BE_indelay <= PLBPPCS1BE_ipd after IN_DELAY; PLBPPCS1BUSLOCK_indelay <= PLBPPCS1BUSLOCK_ipd after IN_DELAY; PLBPPCS1LOCKERR_indelay <= PLBPPCS1LOCKERR_ipd after IN_DELAY; PLBPPCS1MASTERID_indelay <= PLBPPCS1MASTERID_ipd after IN_DELAY; PLBPPCS1MSIZE_indelay <= PLBPPCS1MSIZE_ipd after IN_DELAY; PLBPPCS1PAVALID_indelay <= PLBPPCS1PAVALID_ipd after IN_DELAY; PLBPPCS1RDBURST_indelay <= PLBPPCS1RDBURST_ipd after IN_DELAY; PLBPPCS1RDPENDPRI_indelay <= PLBPPCS1RDPENDPRI_ipd after IN_DELAY; PLBPPCS1RDPENDREQ_indelay <= PLBPPCS1RDPENDREQ_ipd after IN_DELAY; PLBPPCS1RDPRIM_indelay <= PLBPPCS1RDPRIM_ipd after IN_DELAY; PLBPPCS1REQPRI_indelay <= PLBPPCS1REQPRI_ipd after IN_DELAY; PLBPPCS1RNW_indelay <= PLBPPCS1RNW_ipd after IN_DELAY; PLBPPCS1SAVALID_indelay <= PLBPPCS1SAVALID_ipd after IN_DELAY; PLBPPCS1SIZE_indelay <= PLBPPCS1SIZE_ipd after IN_DELAY; PLBPPCS1TATTRIBUTE_indelay <= PLBPPCS1TATTRIBUTE_ipd after IN_DELAY; PLBPPCS1TYPE_indelay <= PLBPPCS1TYPE_ipd after IN_DELAY; PLBPPCS1UABUS_indelay <= PLBPPCS1UABUS_ipd after IN_DELAY; PLBPPCS1WRBURST_indelay <= PLBPPCS1WRBURST_ipd after IN_DELAY; PLBPPCS1WRDBUS_indelay <= PLBPPCS1WRDBUS_ipd after IN_DELAY; PLBPPCS1WRPENDPRI_indelay <= PLBPPCS1WRPENDPRI_ipd after IN_DELAY; PLBPPCS1WRPENDREQ_indelay <= PLBPPCS1WRPENDREQ_ipd after IN_DELAY; PLBPPCS1WRPRIM_indelay <= PLBPPCS1WRPRIM_ipd after IN_DELAY; RSTC440RESETCHIP_indelay <= RSTC440RESETCHIP_ipd after IN_DELAY; RSTC440RESETCORE_indelay <= RSTC440RESETCORE_ipd after IN_DELAY; RSTC440RESETSYSTEM_indelay <= RSTC440RESETSYSTEM_ipd after IN_DELAY; TIEC440DCURDLDCACHEPLBPRIO_indelay <= TIEC440DCURDLDCACHEPLBPRIO_ipd after IN_DELAY; TIEC440DCURDNONCACHEPLBPRIO_indelay <= TIEC440DCURDNONCACHEPLBPRIO_ipd after IN_DELAY; TIEC440DCURDTOUCHPLBPRIO_indelay <= TIEC440DCURDTOUCHPLBPRIO_ipd after IN_DELAY; TIEC440DCURDURGENTPLBPRIO_indelay <= TIEC440DCURDURGENTPLBPRIO_ipd after IN_DELAY; TIEC440DCUWRFLUSHPLBPRIO_indelay <= TIEC440DCUWRFLUSHPLBPRIO_ipd after IN_DELAY; TIEC440DCUWRSTOREPLBPRIO_indelay <= TIEC440DCUWRSTOREPLBPRIO_ipd after IN_DELAY; TIEC440DCUWRURGENTPLBPRIO_indelay <= TIEC440DCUWRURGENTPLBPRIO_ipd after IN_DELAY; TIEC440ENDIANRESET_indelay <= TIEC440ENDIANRESET_ipd after IN_DELAY; TIEC440ERPNRESET_indelay <= TIEC440ERPNRESET_ipd after IN_DELAY; TIEC440ICURDFETCHPLBPRIO_indelay <= TIEC440ICURDFETCHPLBPRIO_ipd after IN_DELAY; TIEC440ICURDSPECPLBPRIO_indelay <= TIEC440ICURDSPECPLBPRIO_ipd after IN_DELAY; TIEC440ICURDTOUCHPLBPRIO_indelay <= TIEC440ICURDTOUCHPLBPRIO_ipd after IN_DELAY; TIEC440PIR_indelay <= TIEC440PIR_ipd after IN_DELAY; TIEC440PVR_indelay <= TIEC440PVR_ipd after IN_DELAY; TIEC440USERRESET_indelay <= TIEC440USERRESET_ipd after IN_DELAY; TIEDCRBASEADDR_indelay <= TIEDCRBASEADDR_ipd after IN_DELAY; TRCC440TRACEDISABLE_indelay <= TRCC440TRACEDISABLE_ipd after IN_DELAY; TRCC440TRIGGEREVENTIN_indelay <= TRCC440TRIGGEREVENTIN_ipd after IN_DELAY; ppc440_swift_1 : PPC440_SWIFT port map ( APU_CONTROL => APU_CONTROL_BINARY, APU_UDI0 => APU_UDI0_BINARY, APU_UDI1 => APU_UDI1_BINARY, APU_UDI10 => APU_UDI10_BINARY, APU_UDI11 => APU_UDI11_BINARY, APU_UDI12 => APU_UDI12_BINARY, APU_UDI13 => APU_UDI13_BINARY, APU_UDI14 => APU_UDI14_BINARY, APU_UDI15 => APU_UDI15_BINARY, APU_UDI2 => APU_UDI2_BINARY, APU_UDI3 => APU_UDI3_BINARY, APU_UDI4 => APU_UDI4_BINARY, APU_UDI5 => APU_UDI5_BINARY, APU_UDI6 => APU_UDI6_BINARY, APU_UDI7 => APU_UDI7_BINARY, APU_UDI8 => APU_UDI8_BINARY, APU_UDI9 => APU_UDI9_BINARY, CLOCK_DELAY => CLOCK_DELAY_BINARY, DCR_AUTOLOCK_ENABLE => DCR_AUTOLOCK_ENABLE_BINARY, DMA0_CONTROL => DMA0_CONTROL_BINARY, DMA0_RXCHANNELCTRL => DMA0_RXCHANNELCTRL_BINARY, DMA0_RXIRQTIMER => DMA0_RXIRQTIMER_BINARY, DMA0_TXCHANNELCTRL => DMA0_TXCHANNELCTRL_BINARY, DMA0_TXIRQTIMER => DMA0_TXIRQTIMER_BINARY, DMA1_CONTROL => DMA1_CONTROL_BINARY, DMA1_RXCHANNELCTRL => DMA1_RXCHANNELCTRL_BINARY, DMA1_RXIRQTIMER => DMA1_RXIRQTIMER_BINARY, DMA1_TXCHANNELCTRL => DMA1_TXCHANNELCTRL_BINARY, DMA1_TXIRQTIMER => DMA1_TXIRQTIMER_BINARY, DMA2_CONTROL => DMA2_CONTROL_BINARY, DMA2_RXCHANNELCTRL => DMA2_RXCHANNELCTRL_BINARY, DMA2_RXIRQTIMER => DMA2_RXIRQTIMER_BINARY, DMA2_TXCHANNELCTRL => DMA2_TXCHANNELCTRL_BINARY, DMA2_TXIRQTIMER => DMA2_TXIRQTIMER_BINARY, DMA3_CONTROL => DMA3_CONTROL_BINARY, DMA3_RXCHANNELCTRL => DMA3_RXCHANNELCTRL_BINARY, DMA3_RXIRQTIMER => DMA3_RXIRQTIMER_BINARY, DMA3_TXCHANNELCTRL => DMA3_TXCHANNELCTRL_BINARY, DMA3_TXIRQTIMER => DMA3_TXIRQTIMER_BINARY, INTERCONNECT_IMASK => INTERCONNECT_IMASK_BINARY, INTERCONNECT_TMPL_SEL => INTERCONNECT_TMPL_SEL_BINARY, MI_ARBCONFIG => MI_ARBCONFIG_BINARY, MI_BANKCONFLICT_MASK => MI_BANKCONFLICT_MASK_BINARY, MI_CONTROL => MI_CONTROL_BINARY, MI_ROWCONFLICT_MASK => MI_ROWCONFLICT_MASK_BINARY, PPCDM_ASYNCMODE => PPCDM_ASYNCMODE_BINARY, PPCDS_ASYNCMODE => PPCDS_ASYNCMODE_BINARY, PPCM_ARBCONFIG => PPCM_ARBCONFIG_BINARY, PPCM_CONTROL => PPCM_CONTROL_BINARY, PPCM_COUNTER => PPCM_COUNTER_BINARY, PPCS0_ADDRMAP_TMPL0 => PPCS0_ADDRMAP_TMPL0_BINARY, PPCS0_ADDRMAP_TMPL1 => PPCS0_ADDRMAP_TMPL1_BINARY, PPCS0_ADDRMAP_TMPL2 => PPCS0_ADDRMAP_TMPL2_BINARY, PPCS0_ADDRMAP_TMPL3 => PPCS0_ADDRMAP_TMPL3_BINARY, PPCS0_CONTROL => PPCS0_CONTROL_BINARY, PPCS0_WIDTH_128N64 => PPCS0_WIDTH_128N64_BINARY, PPCS1_ADDRMAP_TMPL0 => PPCS1_ADDRMAP_TMPL0_BINARY, PPCS1_ADDRMAP_TMPL1 => PPCS1_ADDRMAP_TMPL1_BINARY, PPCS1_ADDRMAP_TMPL2 => PPCS1_ADDRMAP_TMPL2_BINARY, PPCS1_ADDRMAP_TMPL3 => PPCS1_ADDRMAP_TMPL3_BINARY, PPCS1_CONTROL => PPCS1_CONTROL_BINARY, PPCS1_WIDTH_128N64 => PPCS1_WIDTH_128N64_BINARY, XBAR_ADDRMAP_TMPL0 => XBAR_ADDRMAP_TMPL0_BINARY, XBAR_ADDRMAP_TMPL1 => XBAR_ADDRMAP_TMPL1_BINARY, XBAR_ADDRMAP_TMPL2 => XBAR_ADDRMAP_TMPL2_BINARY, XBAR_ADDRMAP_TMPL3 => XBAR_ADDRMAP_TMPL3_BINARY, APUFCMDECFPUOP => APUFCMDECFPUOP_outdelay, APUFCMDECLDSTXFERSIZE => APUFCMDECLDSTXFERSIZE_outdelay, APUFCMDECLOAD => APUFCMDECLOAD_outdelay, APUFCMDECNONAUTON => APUFCMDECNONAUTON_outdelay, APUFCMDECSTORE => APUFCMDECSTORE_outdelay, APUFCMDECUDI => APUFCMDECUDI_outdelay, APUFCMDECUDIVALID => APUFCMDECUDIVALID_outdelay, APUFCMENDIAN => APUFCMENDIAN_outdelay, APUFCMFLUSH => APUFCMFLUSH_outdelay, APUFCMINSTRUCTION => APUFCMINSTRUCTION_outdelay, APUFCMINSTRVALID => APUFCMINSTRVALID_outdelay, APUFCMLOADBYTEADDR => APUFCMLOADBYTEADDR_outdelay, APUFCMLOADDATA => APUFCMLOADDATA_outdelay, APUFCMLOADDVALID => APUFCMLOADDVALID_outdelay, APUFCMMSRFE0 => APUFCMMSRFE0_outdelay, APUFCMMSRFE1 => APUFCMMSRFE1_outdelay, APUFCMNEXTINSTRREADY => APUFCMNEXTINSTRREADY_outdelay, APUFCMOPERANDVALID => APUFCMOPERANDVALID_outdelay, APUFCMRADATA => APUFCMRADATA_outdelay, APUFCMRBDATA => APUFCMRBDATA_outdelay, APUFCMWRITEBACKOK => APUFCMWRITEBACKOK_outdelay, C440CPMCORESLEEPREQ => C440CPMCORESLEEPREQ_outdelay, C440CPMDECIRPTREQ => C440CPMDECIRPTREQ_outdelay, C440CPMFITIRPTREQ => C440CPMFITIRPTREQ_outdelay, C440CPMMSRCE => C440CPMMSRCE_outdelay, C440CPMMSREE => C440CPMMSREE_outdelay, C440CPMTIMERRESETREQ => C440CPMTIMERRESETREQ_outdelay, C440CPMWDIRPTREQ => C440CPMWDIRPTREQ_outdelay, C440DBGSYSTEMCONTROL => C440DBGSYSTEMCONTROL_outdelay, C440JTGTDO => C440JTGTDO_outdelay, C440JTGTDOEN => C440JTGTDOEN_outdelay, C440MACHINECHECK => C440MACHINECHECK_outdelay, C440RSTCHIPRESETREQ => C440RSTCHIPRESETREQ_outdelay, C440RSTCORERESETREQ => C440RSTCORERESETREQ_outdelay, C440RSTSYSTEMRESETREQ => C440RSTSYSTEMRESETREQ_outdelay, C440TRCBRANCHSTATUS => C440TRCBRANCHSTATUS_outdelay, C440TRCCYCLE => C440TRCCYCLE_outdelay, C440TRCEXECUTIONSTATUS => C440TRCEXECUTIONSTATUS_outdelay, C440TRCTRACESTATUS => C440TRCTRACESTATUS_outdelay, C440TRCTRIGGEREVENTOUT => C440TRCTRIGGEREVENTOUT_outdelay, C440TRCTRIGGEREVENTTYPE => C440TRCTRIGGEREVENTTYPE_outdelay, DMA0LLRSTENGINEACK => DMA0LLRSTENGINEACK_outdelay, DMA0LLRXDSTRDYN => DMA0LLRXDSTRDYN_outdelay, DMA0LLTXD => DMA0LLTXD_outdelay, DMA0LLTXEOFN => DMA0LLTXEOFN_outdelay, DMA0LLTXEOPN => DMA0LLTXEOPN_outdelay, DMA0LLTXREM => DMA0LLTXREM_outdelay, DMA0LLTXSOFN => DMA0LLTXSOFN_outdelay, DMA0LLTXSOPN => DMA0LLTXSOPN_outdelay, DMA0LLTXSRCRDYN => DMA0LLTXSRCRDYN_outdelay, DMA0RXIRQ => DMA0RXIRQ_outdelay, DMA0TXIRQ => DMA0TXIRQ_outdelay, DMA1LLRSTENGINEACK => DMA1LLRSTENGINEACK_outdelay, DMA1LLRXDSTRDYN => DMA1LLRXDSTRDYN_outdelay, DMA1LLTXD => DMA1LLTXD_outdelay, DMA1LLTXEOFN => DMA1LLTXEOFN_outdelay, DMA1LLTXEOPN => DMA1LLTXEOPN_outdelay, DMA1LLTXREM => DMA1LLTXREM_outdelay, DMA1LLTXSOFN => DMA1LLTXSOFN_outdelay, DMA1LLTXSOPN => DMA1LLTXSOPN_outdelay, DMA1LLTXSRCRDYN => DMA1LLTXSRCRDYN_outdelay, DMA1RXIRQ => DMA1RXIRQ_outdelay, DMA1TXIRQ => DMA1TXIRQ_outdelay, DMA2LLRSTENGINEACK => DMA2LLRSTENGINEACK_outdelay, DMA2LLRXDSTRDYN => DMA2LLRXDSTRDYN_outdelay, DMA2LLTXD => DMA2LLTXD_outdelay, DMA2LLTXEOFN => DMA2LLTXEOFN_outdelay, DMA2LLTXEOPN => DMA2LLTXEOPN_outdelay, DMA2LLTXREM => DMA2LLTXREM_outdelay, DMA2LLTXSOFN => DMA2LLTXSOFN_outdelay, DMA2LLTXSOPN => DMA2LLTXSOPN_outdelay, DMA2LLTXSRCRDYN => DMA2LLTXSRCRDYN_outdelay, DMA2RXIRQ => DMA2RXIRQ_outdelay, DMA2TXIRQ => DMA2TXIRQ_outdelay, DMA3LLRSTENGINEACK => DMA3LLRSTENGINEACK_outdelay, DMA3LLRXDSTRDYN => DMA3LLRXDSTRDYN_outdelay, DMA3LLTXD => DMA3LLTXD_outdelay, DMA3LLTXEOFN => DMA3LLTXEOFN_outdelay, DMA3LLTXEOPN => DMA3LLTXEOPN_outdelay, DMA3LLTXREM => DMA3LLTXREM_outdelay, DMA3LLTXSOFN => DMA3LLTXSOFN_outdelay, DMA3LLTXSOPN => DMA3LLTXSOPN_outdelay, DMA3LLTXSRCRDYN => DMA3LLTXSRCRDYN_outdelay, DMA3RXIRQ => DMA3RXIRQ_outdelay, DMA3TXIRQ => DMA3TXIRQ_outdelay, MIMCADDRESS => MIMCADDRESS_outdelay, MIMCADDRESSVALID => MIMCADDRESSVALID_outdelay, MIMCBANKCONFLICT => MIMCBANKCONFLICT_outdelay, MIMCBYTEENABLE => MIMCBYTEENABLE_outdelay, MIMCREADNOTWRITE => MIMCREADNOTWRITE_outdelay, MIMCROWCONFLICT => MIMCROWCONFLICT_outdelay, MIMCWRITEDATA => MIMCWRITEDATA_outdelay, MIMCWRITEDATAVALID => MIMCWRITEDATAVALID_outdelay, PPCCPMINTERCONNECTBUSY => PPCCPMINTERCONNECTBUSY_outdelay, PPCDMDCRABUS => PPCDMDCRABUS_outdelay, PPCDMDCRDBUSOUT => PPCDMDCRDBUSOUT_outdelay, PPCDMDCRREAD => PPCDMDCRREAD_outdelay, PPCDMDCRUABUS => PPCDMDCRUABUS_outdelay, PPCDMDCRWRITE => PPCDMDCRWRITE_outdelay, PPCDSDCRACK => PPCDSDCRACK_outdelay, PPCDSDCRDBUSIN => PPCDSDCRDBUSIN_outdelay, PPCDSDCRTIMEOUTWAIT => PPCDSDCRTIMEOUTWAIT_outdelay, PPCEICINTERCONNECTIRQ => PPCEICINTERCONNECTIRQ_outdelay, PPCMPLBABORT => PPCMPLBABORT_outdelay, PPCMPLBABUS => PPCMPLBABUS_outdelay, PPCMPLBBE => PPCMPLBBE_outdelay, PPCMPLBBUSLOCK => PPCMPLBBUSLOCK_outdelay, PPCMPLBLOCKERR => PPCMPLBLOCKERR_outdelay, PPCMPLBPRIORITY => PPCMPLBPRIORITY_outdelay, PPCMPLBRDBURST => PPCMPLBRDBURST_outdelay, PPCMPLBREQUEST => PPCMPLBREQUEST_outdelay, PPCMPLBRNW => PPCMPLBRNW_outdelay, PPCMPLBSIZE => PPCMPLBSIZE_outdelay, PPCMPLBTATTRIBUTE => PPCMPLBTATTRIBUTE_outdelay, PPCMPLBTYPE => PPCMPLBTYPE_outdelay, PPCMPLBUABUS => PPCMPLBUABUS_outdelay, PPCMPLBWRBURST => PPCMPLBWRBURST_outdelay, PPCMPLBWRDBUS => PPCMPLBWRDBUS_outdelay, PPCS0PLBADDRACK => PPCS0PLBADDRACK_outdelay, PPCS0PLBMBUSY => PPCS0PLBMBUSY_outdelay, PPCS0PLBMIRQ => PPCS0PLBMIRQ_outdelay, PPCS0PLBMRDERR => PPCS0PLBMRDERR_outdelay, PPCS0PLBMWRERR => PPCS0PLBMWRERR_outdelay, PPCS0PLBRDBTERM => PPCS0PLBRDBTERM_outdelay, PPCS0PLBRDCOMP => PPCS0PLBRDCOMP_outdelay, PPCS0PLBRDDACK => PPCS0PLBRDDACK_outdelay, PPCS0PLBRDDBUS => PPCS0PLBRDDBUS_outdelay, PPCS0PLBRDWDADDR => PPCS0PLBRDWDADDR_outdelay, PPCS0PLBREARBITRATE => PPCS0PLBREARBITRATE_outdelay, PPCS0PLBSSIZE => PPCS0PLBSSIZE_outdelay, PPCS0PLBWAIT => PPCS0PLBWAIT_outdelay, PPCS0PLBWRBTERM => PPCS0PLBWRBTERM_outdelay, PPCS0PLBWRCOMP => PPCS0PLBWRCOMP_outdelay, PPCS0PLBWRDACK => PPCS0PLBWRDACK_outdelay, PPCS1PLBADDRACK => PPCS1PLBADDRACK_outdelay, PPCS1PLBMBUSY => PPCS1PLBMBUSY_outdelay, PPCS1PLBMIRQ => PPCS1PLBMIRQ_outdelay, PPCS1PLBMRDERR => PPCS1PLBMRDERR_outdelay, PPCS1PLBMWRERR => PPCS1PLBMWRERR_outdelay, PPCS1PLBRDBTERM => PPCS1PLBRDBTERM_outdelay, PPCS1PLBRDCOMP => PPCS1PLBRDCOMP_outdelay, PPCS1PLBRDDACK => PPCS1PLBRDDACK_outdelay, PPCS1PLBRDDBUS => PPCS1PLBRDDBUS_outdelay, PPCS1PLBRDWDADDR => PPCS1PLBRDWDADDR_outdelay, PPCS1PLBREARBITRATE => PPCS1PLBREARBITRATE_outdelay, PPCS1PLBSSIZE => PPCS1PLBSSIZE_outdelay, PPCS1PLBWAIT => PPCS1PLBWAIT_outdelay, PPCS1PLBWRBTERM => PPCS1PLBWRBTERM_outdelay, PPCS1PLBWRCOMP => PPCS1PLBWRCOMP_outdelay, PPCS1PLBWRDACK => PPCS1PLBWRDACK_outdelay, CPMC440CLK => CPMC440CLK_indelay, CPMC440CLKEN => CPMC440CLKEN_indelay, CPMC440CORECLOCKINACTIVE => CPMC440CORECLOCKINACTIVE_indelay, CPMC440TIMERCLOCK => CPMC440TIMERCLOCK_indelay, CPMDCRCLK => CPMDCRCLK_indelay, CPMDMA0LLCLK => CPMDMA0LLCLK_indelay, CPMDMA1LLCLK => CPMDMA1LLCLK_indelay, CPMDMA2LLCLK => CPMDMA2LLCLK_indelay, CPMDMA3LLCLK => CPMDMA3LLCLK_indelay, CPMFCMCLK => CPMFCMCLK_indelay, CPMINTERCONNECTCLK => CPMINTERCONNECTCLK_indelay, CPMINTERCONNECTCLKEN => CPMINTERCONNECTCLKEN_indelay, CPMINTERCONNECTCLKNTO1 => CPMINTERCONNECTCLKNTO1_indelay, CPMMCCLK => CPMMCCLK_indelay, CPMPPCMPLBCLK => CPMPPCMPLBCLK_indelay, CPMPPCS0PLBCLK => CPMPPCS0PLBCLK_indelay, CPMPPCS1PLBCLK => CPMPPCS1PLBCLK_indelay, DBGC440DEBUGHALT => DBGC440DEBUGHALT_indelay, DBGC440SYSTEMSTATUS => DBGC440SYSTEMSTATUS_indelay, DBGC440UNCONDDEBUGEVENT => DBGC440UNCONDDEBUGEVENT_indelay, DCRPPCDMACK => DCRPPCDMACK_indelay, DCRPPCDMDBUSIN => DCRPPCDMDBUSIN_indelay, DCRPPCDMTIMEOUTWAIT => DCRPPCDMTIMEOUTWAIT_indelay, DCRPPCDSABUS => DCRPPCDSABUS_indelay, DCRPPCDSDBUSOUT => DCRPPCDSDBUSOUT_indelay, DCRPPCDSREAD => DCRPPCDSREAD_indelay, DCRPPCDSWRITE => DCRPPCDSWRITE_indelay, EICC440CRITIRQ => EICC440CRITIRQ_indelay, EICC440EXTIRQ => EICC440EXTIRQ_indelay, FCMAPUCONFIRMINSTR => FCMAPUCONFIRMINSTR_indelay, FCMAPUCR => FCMAPUCR_indelay, FCMAPUDONE => FCMAPUDONE_indelay, FCMAPUEXCEPTION => FCMAPUEXCEPTION_indelay, FCMAPUFPSCRFEX => FCMAPUFPSCRFEX_indelay, FCMAPURESULT => FCMAPURESULT_indelay, FCMAPURESULTVALID => FCMAPURESULTVALID_indelay, FCMAPUSLEEPNOTREADY => FCMAPUSLEEPNOTREADY_indelay, FCMAPUSTOREDATA => FCMAPUSTOREDATA_indelay, GSR => GSR, JTGC440TCK => JTGC440TCK_indelay, JTGC440TDI => JTGC440TDI_indelay, JTGC440TMS => JTGC440TMS_indelay, JTGC440TRSTNEG => JTGC440TRSTNEG_indelay, LLDMA0RSTENGINEREQ => LLDMA0RSTENGINEREQ_indelay, LLDMA0RXD => LLDMA0RXD_indelay, LLDMA0RXEOFN => LLDMA0RXEOFN_indelay, LLDMA0RXEOPN => LLDMA0RXEOPN_indelay, LLDMA0RXREM => LLDMA0RXREM_indelay, LLDMA0RXSOFN => LLDMA0RXSOFN_indelay, LLDMA0RXSOPN => LLDMA0RXSOPN_indelay, LLDMA0RXSRCRDYN => LLDMA0RXSRCRDYN_indelay, LLDMA0TXDSTRDYN => LLDMA0TXDSTRDYN_indelay, LLDMA1RSTENGINEREQ => LLDMA1RSTENGINEREQ_indelay, LLDMA1RXD => LLDMA1RXD_indelay, LLDMA1RXEOFN => LLDMA1RXEOFN_indelay, LLDMA1RXEOPN => LLDMA1RXEOPN_indelay, LLDMA1RXREM => LLDMA1RXREM_indelay, LLDMA1RXSOFN => LLDMA1RXSOFN_indelay, LLDMA1RXSOPN => LLDMA1RXSOPN_indelay, LLDMA1RXSRCRDYN => LLDMA1RXSRCRDYN_indelay, LLDMA1TXDSTRDYN => LLDMA1TXDSTRDYN_indelay, LLDMA2RSTENGINEREQ => LLDMA2RSTENGINEREQ_indelay, LLDMA2RXD => LLDMA2RXD_indelay, LLDMA2RXEOFN => LLDMA2RXEOFN_indelay, LLDMA2RXEOPN => LLDMA2RXEOPN_indelay, LLDMA2RXREM => LLDMA2RXREM_indelay, LLDMA2RXSOFN => LLDMA2RXSOFN_indelay, LLDMA2RXSOPN => LLDMA2RXSOPN_indelay, LLDMA2RXSRCRDYN => LLDMA2RXSRCRDYN_indelay, LLDMA2TXDSTRDYN => LLDMA2TXDSTRDYN_indelay, LLDMA3RSTENGINEREQ => LLDMA3RSTENGINEREQ_indelay, LLDMA3RXD => LLDMA3RXD_indelay, LLDMA3RXEOFN => LLDMA3RXEOFN_indelay, LLDMA3RXEOPN => LLDMA3RXEOPN_indelay, LLDMA3RXREM => LLDMA3RXREM_indelay, LLDMA3RXSOFN => LLDMA3RXSOFN_indelay, LLDMA3RXSOPN => LLDMA3RXSOPN_indelay, LLDMA3RXSRCRDYN => LLDMA3RXSRCRDYN_indelay, LLDMA3TXDSTRDYN => LLDMA3TXDSTRDYN_indelay, MCMIADDRREADYTOACCEPT => MCMIADDRREADYTOACCEPT_indelay, MCMIREADDATA => MCMIREADDATA_indelay, MCMIREADDATAERR => MCMIREADDATAERR_indelay, MCMIREADDATAVALID => MCMIREADDATAVALID_indelay, PLBPPCMADDRACK => PLBPPCMADDRACK_indelay, PLBPPCMMBUSY => PLBPPCMMBUSY_indelay, PLBPPCMMIRQ => PLBPPCMMIRQ_indelay, PLBPPCMMRDERR => PLBPPCMMRDERR_indelay, PLBPPCMMWRERR => PLBPPCMMWRERR_indelay, PLBPPCMRDBTERM => PLBPPCMRDBTERM_indelay, PLBPPCMRDDACK => PLBPPCMRDDACK_indelay, PLBPPCMRDDBUS => PLBPPCMRDDBUS_indelay, PLBPPCMRDPENDPRI => PLBPPCMRDPENDPRI_indelay, PLBPPCMRDPENDREQ => PLBPPCMRDPENDREQ_indelay, PLBPPCMRDWDADDR => PLBPPCMRDWDADDR_indelay, PLBPPCMREARBITRATE => PLBPPCMREARBITRATE_indelay, PLBPPCMREQPRI => PLBPPCMREQPRI_indelay, PLBPPCMSSIZE => PLBPPCMSSIZE_indelay, PLBPPCMTIMEOUT => PLBPPCMTIMEOUT_indelay, PLBPPCMWRBTERM => PLBPPCMWRBTERM_indelay, PLBPPCMWRDACK => PLBPPCMWRDACK_indelay, PLBPPCMWRPENDPRI => PLBPPCMWRPENDPRI_indelay, PLBPPCMWRPENDREQ => PLBPPCMWRPENDREQ_indelay, PLBPPCS0ABORT => PLBPPCS0ABORT_indelay, PLBPPCS0ABUS => PLBPPCS0ABUS_indelay, PLBPPCS0BE => PLBPPCS0BE_indelay, PLBPPCS0BUSLOCK => PLBPPCS0BUSLOCK_indelay, PLBPPCS0LOCKERR => PLBPPCS0LOCKERR_indelay, PLBPPCS0MASTERID => PLBPPCS0MASTERID_indelay, PLBPPCS0MSIZE => PLBPPCS0MSIZE_indelay, PLBPPCS0PAVALID => PLBPPCS0PAVALID_indelay, PLBPPCS0RDBURST => PLBPPCS0RDBURST_indelay, PLBPPCS0RDPENDPRI => PLBPPCS0RDPENDPRI_indelay, PLBPPCS0RDPENDREQ => PLBPPCS0RDPENDREQ_indelay, PLBPPCS0RDPRIM => PLBPPCS0RDPRIM_indelay, PLBPPCS0REQPRI => PLBPPCS0REQPRI_indelay, PLBPPCS0RNW => PLBPPCS0RNW_indelay, PLBPPCS0SAVALID => PLBPPCS0SAVALID_indelay, PLBPPCS0SIZE => PLBPPCS0SIZE_indelay, PLBPPCS0TATTRIBUTE => PLBPPCS0TATTRIBUTE_indelay, PLBPPCS0TYPE => PLBPPCS0TYPE_indelay, PLBPPCS0UABUS => PLBPPCS0UABUS_indelay, PLBPPCS0WRBURST => PLBPPCS0WRBURST_indelay, PLBPPCS0WRDBUS => PLBPPCS0WRDBUS_indelay, PLBPPCS0WRPENDPRI => PLBPPCS0WRPENDPRI_indelay, PLBPPCS0WRPENDREQ => PLBPPCS0WRPENDREQ_indelay, PLBPPCS0WRPRIM => PLBPPCS0WRPRIM_indelay, PLBPPCS1ABORT => PLBPPCS1ABORT_indelay, PLBPPCS1ABUS => PLBPPCS1ABUS_indelay, PLBPPCS1BE => PLBPPCS1BE_indelay, PLBPPCS1BUSLOCK => PLBPPCS1BUSLOCK_indelay, PLBPPCS1LOCKERR => PLBPPCS1LOCKERR_indelay, PLBPPCS1MASTERID => PLBPPCS1MASTERID_indelay, PLBPPCS1MSIZE => PLBPPCS1MSIZE_indelay, PLBPPCS1PAVALID => PLBPPCS1PAVALID_indelay, PLBPPCS1RDBURST => PLBPPCS1RDBURST_indelay, PLBPPCS1RDPENDPRI => PLBPPCS1RDPENDPRI_indelay, PLBPPCS1RDPENDREQ => PLBPPCS1RDPENDREQ_indelay, PLBPPCS1RDPRIM => PLBPPCS1RDPRIM_indelay, PLBPPCS1REQPRI => PLBPPCS1REQPRI_indelay, PLBPPCS1RNW => PLBPPCS1RNW_indelay, PLBPPCS1SAVALID => PLBPPCS1SAVALID_indelay, PLBPPCS1SIZE => PLBPPCS1SIZE_indelay, PLBPPCS1TATTRIBUTE => PLBPPCS1TATTRIBUTE_indelay, PLBPPCS1TYPE => PLBPPCS1TYPE_indelay, PLBPPCS1UABUS => PLBPPCS1UABUS_indelay, PLBPPCS1WRBURST => PLBPPCS1WRBURST_indelay, PLBPPCS1WRDBUS => PLBPPCS1WRDBUS_indelay, PLBPPCS1WRPENDPRI => PLBPPCS1WRPENDPRI_indelay, PLBPPCS1WRPENDREQ => PLBPPCS1WRPENDREQ_indelay, PLBPPCS1WRPRIM => PLBPPCS1WRPRIM_indelay, RSTC440RESETCHIP => RSTC440RESETCHIP_indelay, RSTC440RESETCORE => RSTC440RESETCORE_indelay, RSTC440RESETSYSTEM => RSTC440RESETSYSTEM_indelay, TIEC440DCURDLDCACHEPLBPRIO => TIEC440DCURDLDCACHEPLBPRIO_indelay, TIEC440DCURDNONCACHEPLBPRIO => TIEC440DCURDNONCACHEPLBPRIO_indelay, TIEC440DCURDTOUCHPLBPRIO => TIEC440DCURDTOUCHPLBPRIO_indelay, TIEC440DCURDURGENTPLBPRIO => TIEC440DCURDURGENTPLBPRIO_indelay, TIEC440DCUWRFLUSHPLBPRIO => TIEC440DCUWRFLUSHPLBPRIO_indelay, TIEC440DCUWRSTOREPLBPRIO => TIEC440DCUWRSTOREPLBPRIO_indelay, TIEC440DCUWRURGENTPLBPRIO => TIEC440DCUWRURGENTPLBPRIO_indelay, TIEC440ENDIANRESET => TIEC440ENDIANRESET_indelay, TIEC440ERPNRESET => TIEC440ERPNRESET_indelay, TIEC440ICURDFETCHPLBPRIO => TIEC440ICURDFETCHPLBPRIO_indelay, TIEC440ICURDSPECPLBPRIO => TIEC440ICURDSPECPLBPRIO_indelay, TIEC440ICURDTOUCHPLBPRIO => TIEC440ICURDTOUCHPLBPRIO_indelay, TIEC440PIR => TIEC440PIR_indelay, TIEC440PVR => TIEC440PVR_indelay, TIEC440USERRESET => TIEC440USERRESET_indelay, TIEDCRBASEADDR => TIEDCRBASEADDR_indelay, TRCC440TRACEDISABLE => TRCC440TRACEDISABLE_indelay, TRCC440TRIGGEREVENTIN => TRCC440TRIGGEREVENTIN_indelay ); INIPROC : process begin case PPCS0_WIDTH_128N64 is when FALSE => PPCS0_WIDTH_128N64_BINARY <= '0'; when TRUE => PPCS0_WIDTH_128N64_BINARY <= '1'; when others => assert FALSE report "Error : PPCS0_WIDTH_128N64 is neither TRUE nor FALSE." severity error; end case; case PPCS1_WIDTH_128N64 is when FALSE => PPCS1_WIDTH_128N64_BINARY <= '0'; when TRUE => PPCS1_WIDTH_128N64_BINARY <= '1'; when others => assert FALSE report "Error : PPCS1_WIDTH_128N64 is neither TRUE nor FALSE." severity error; end case; case PPCDM_ASYNCMODE is when FALSE => PPCDM_ASYNCMODE_BINARY <= '0'; when TRUE => PPCDM_ASYNCMODE_BINARY <= '1'; when others => assert FALSE report "Error : PPCDM_ASYNCMODE is neither TRUE nor FALSE." severity error; end case; case PPCDS_ASYNCMODE is when FALSE => PPCDS_ASYNCMODE_BINARY <= '0'; when TRUE => PPCDS_ASYNCMODE_BINARY <= '1'; when others => assert FALSE report "Error : PPCDS_ASYNCMODE is neither TRUE nor FALSE." severity error; end case; case DCR_AUTOLOCK_ENABLE is when FALSE => DCR_AUTOLOCK_ENABLE_BINARY <= '0'; when TRUE => DCR_AUTOLOCK_ENABLE_BINARY <= '1'; when others => assert FALSE report "Error : DCR_AUTOLOCK_ENABLE is neither TRUE nor FALSE." severity error; end case; case CLOCK_DELAY is when FALSE => CLOCK_DELAY_BINARY <= "10000"; when TRUE => CLOCK_DELAY_BINARY <= "00000"; when others => assert FALSE report "Error : CLOCK_DELAY is neither TRUE nor FALSE." severity error; end case; wait; end process INIPROC; TIMING : process variable DMA0LLRSTENGINEACK_GlitchData : VitalGlitchDataType; variable DMA0LLRXDSTRDYN_GlitchData : VitalGlitchDataType; variable DMA0LLTXD0_GlitchData : VitalGlitchDataType; variable DMA0LLTXD1_GlitchData : VitalGlitchDataType; variable DMA0LLTXD2_GlitchData : VitalGlitchDataType; variable DMA0LLTXD3_GlitchData : VitalGlitchDataType; variable DMA0LLTXD4_GlitchData : VitalGlitchDataType; variable DMA0LLTXD5_GlitchData : VitalGlitchDataType; variable DMA0LLTXD6_GlitchData : VitalGlitchDataType; variable DMA0LLTXD7_GlitchData : VitalGlitchDataType; variable DMA0LLTXD8_GlitchData : VitalGlitchDataType; variable DMA0LLTXD9_GlitchData : VitalGlitchDataType; variable DMA0LLTXD10_GlitchData : VitalGlitchDataType; variable DMA0LLTXD11_GlitchData : VitalGlitchDataType; variable DMA0LLTXD12_GlitchData : VitalGlitchDataType; variable DMA0LLTXD13_GlitchData : VitalGlitchDataType; variable DMA0LLTXD14_GlitchData : VitalGlitchDataType; variable DMA0LLTXD15_GlitchData : VitalGlitchDataType; variable DMA0LLTXD16_GlitchData : VitalGlitchDataType; variable DMA0LLTXD17_GlitchData : VitalGlitchDataType; variable DMA0LLTXD18_GlitchData : VitalGlitchDataType; variable DMA0LLTXD19_GlitchData : VitalGlitchDataType; variable DMA0LLTXD20_GlitchData : VitalGlitchDataType; variable DMA0LLTXD21_GlitchData : VitalGlitchDataType; variable DMA0LLTXD22_GlitchData : VitalGlitchDataType; variable DMA0LLTXD23_GlitchData : VitalGlitchDataType; variable DMA0LLTXD24_GlitchData : VitalGlitchDataType; variable DMA0LLTXD25_GlitchData : VitalGlitchDataType; variable DMA0LLTXD26_GlitchData : VitalGlitchDataType; variable DMA0LLTXD27_GlitchData : VitalGlitchDataType; variable DMA0LLTXD28_GlitchData : VitalGlitchDataType; variable DMA0LLTXD29_GlitchData : VitalGlitchDataType; variable DMA0LLTXD30_GlitchData : VitalGlitchDataType; variable DMA0LLTXD31_GlitchData : VitalGlitchDataType; variable DMA0LLTXEOFN_GlitchData : VitalGlitchDataType; variable DMA0LLTXEOPN_GlitchData : VitalGlitchDataType; variable DMA0LLTXREM0_GlitchData : VitalGlitchDataType; variable DMA0LLTXREM1_GlitchData : VitalGlitchDataType; variable DMA0LLTXREM2_GlitchData : VitalGlitchDataType; variable DMA0LLTXREM3_GlitchData : VitalGlitchDataType; variable DMA0LLTXSOFN_GlitchData : VitalGlitchDataType; variable DMA0LLTXSOPN_GlitchData : VitalGlitchDataType; variable DMA0LLTXSRCRDYN_GlitchData : VitalGlitchDataType; variable DMA0RXIRQ_GlitchData : VitalGlitchDataType; variable DMA0TXIRQ_GlitchData : VitalGlitchDataType; variable DMA1LLRSTENGINEACK_GlitchData : VitalGlitchDataType; variable DMA1LLRXDSTRDYN_GlitchData : VitalGlitchDataType; variable DMA1LLTXD0_GlitchData : VitalGlitchDataType; variable DMA1LLTXD1_GlitchData : VitalGlitchDataType; variable DMA1LLTXD2_GlitchData : VitalGlitchDataType; variable DMA1LLTXD3_GlitchData : VitalGlitchDataType; variable DMA1LLTXD4_GlitchData : VitalGlitchDataType; variable DMA1LLTXD5_GlitchData : VitalGlitchDataType; variable DMA1LLTXD6_GlitchData : VitalGlitchDataType; variable DMA1LLTXD7_GlitchData : VitalGlitchDataType; variable DMA1LLTXD8_GlitchData : VitalGlitchDataType; variable DMA1LLTXD9_GlitchData : VitalGlitchDataType; variable DMA1LLTXD10_GlitchData : VitalGlitchDataType; variable DMA1LLTXD11_GlitchData : VitalGlitchDataType; variable DMA1LLTXD12_GlitchData : VitalGlitchDataType; variable DMA1LLTXD13_GlitchData : VitalGlitchDataType; variable DMA1LLTXD14_GlitchData : VitalGlitchDataType; variable DMA1LLTXD15_GlitchData : VitalGlitchDataType; variable DMA1LLTXD16_GlitchData : VitalGlitchDataType; variable DMA1LLTXD17_GlitchData : VitalGlitchDataType; variable DMA1LLTXD18_GlitchData : VitalGlitchDataType; variable DMA1LLTXD19_GlitchData : VitalGlitchDataType; variable DMA1LLTXD20_GlitchData : VitalGlitchDataType; variable DMA1LLTXD21_GlitchData : VitalGlitchDataType; variable DMA1LLTXD22_GlitchData : VitalGlitchDataType; variable DMA1LLTXD23_GlitchData : VitalGlitchDataType; variable DMA1LLTXD24_GlitchData : VitalGlitchDataType; variable DMA1LLTXD25_GlitchData : VitalGlitchDataType; variable DMA1LLTXD26_GlitchData : VitalGlitchDataType; variable DMA1LLTXD27_GlitchData : VitalGlitchDataType; variable DMA1LLTXD28_GlitchData : VitalGlitchDataType; variable DMA1LLTXD29_GlitchData : VitalGlitchDataType; variable DMA1LLTXD30_GlitchData : VitalGlitchDataType; variable DMA1LLTXD31_GlitchData : VitalGlitchDataType; variable DMA1LLTXEOFN_GlitchData : VitalGlitchDataType; variable DMA1LLTXEOPN_GlitchData : VitalGlitchDataType; variable DMA1LLTXREM0_GlitchData : VitalGlitchDataType; variable DMA1LLTXREM1_GlitchData : VitalGlitchDataType; variable DMA1LLTXREM2_GlitchData : VitalGlitchDataType; variable DMA1LLTXREM3_GlitchData : VitalGlitchDataType; variable DMA1LLTXSOFN_GlitchData : VitalGlitchDataType; variable DMA1LLTXSOPN_GlitchData : VitalGlitchDataType; variable DMA1LLTXSRCRDYN_GlitchData : VitalGlitchDataType; variable DMA1RXIRQ_GlitchData : VitalGlitchDataType; variable DMA1TXIRQ_GlitchData : VitalGlitchDataType; variable DMA2LLRSTENGINEACK_GlitchData : VitalGlitchDataType; variable DMA2LLRXDSTRDYN_GlitchData : VitalGlitchDataType; variable DMA2LLTXD0_GlitchData : VitalGlitchDataType; variable DMA2LLTXD1_GlitchData : VitalGlitchDataType; variable DMA2LLTXD2_GlitchData : VitalGlitchDataType; variable DMA2LLTXD3_GlitchData : VitalGlitchDataType; variable DMA2LLTXD4_GlitchData : VitalGlitchDataType; variable DMA2LLTXD5_GlitchData : VitalGlitchDataType; variable DMA2LLTXD6_GlitchData : VitalGlitchDataType; variable DMA2LLTXD7_GlitchData : VitalGlitchDataType; variable DMA2LLTXD8_GlitchData : VitalGlitchDataType; variable DMA2LLTXD9_GlitchData : VitalGlitchDataType; variable DMA2LLTXD10_GlitchData : VitalGlitchDataType; variable DMA2LLTXD11_GlitchData : VitalGlitchDataType; variable DMA2LLTXD12_GlitchData : VitalGlitchDataType; variable DMA2LLTXD13_GlitchData : VitalGlitchDataType; variable DMA2LLTXD14_GlitchData : VitalGlitchDataType; variable DMA2LLTXD15_GlitchData : VitalGlitchDataType; variable DMA2LLTXD16_GlitchData : VitalGlitchDataType; variable DMA2LLTXD17_GlitchData : VitalGlitchDataType; variable DMA2LLTXD18_GlitchData : VitalGlitchDataType; variable DMA2LLTXD19_GlitchData : VitalGlitchDataType; variable DMA2LLTXD20_GlitchData : VitalGlitchDataType; variable DMA2LLTXD21_GlitchData : VitalGlitchDataType; variable DMA2LLTXD22_GlitchData : VitalGlitchDataType; variable DMA2LLTXD23_GlitchData : VitalGlitchDataType; variable DMA2LLTXD24_GlitchData : VitalGlitchDataType; variable DMA2LLTXD25_GlitchData : VitalGlitchDataType; variable DMA2LLTXD26_GlitchData : VitalGlitchDataType; variable DMA2LLTXD27_GlitchData : VitalGlitchDataType; variable DMA2LLTXD28_GlitchData : VitalGlitchDataType; variable DMA2LLTXD29_GlitchData : VitalGlitchDataType; variable DMA2LLTXD30_GlitchData : VitalGlitchDataType; variable DMA2LLTXD31_GlitchData : VitalGlitchDataType; variable DMA2LLTXEOFN_GlitchData : VitalGlitchDataType; variable DMA2LLTXEOPN_GlitchData : VitalGlitchDataType; variable DMA2LLTXREM0_GlitchData : VitalGlitchDataType; variable DMA2LLTXREM1_GlitchData : VitalGlitchDataType; variable DMA2LLTXREM2_GlitchData : VitalGlitchDataType; variable DMA2LLTXREM3_GlitchData : VitalGlitchDataType; variable DMA2LLTXSOFN_GlitchData : VitalGlitchDataType; variable DMA2LLTXSOPN_GlitchData : VitalGlitchDataType; variable DMA2LLTXSRCRDYN_GlitchData : VitalGlitchDataType; variable DMA2RXIRQ_GlitchData : VitalGlitchDataType; variable DMA2TXIRQ_GlitchData : VitalGlitchDataType; variable DMA3LLRSTENGINEACK_GlitchData : VitalGlitchDataType; variable DMA3LLRXDSTRDYN_GlitchData : VitalGlitchDataType; variable DMA3LLTXD0_GlitchData : VitalGlitchDataType; variable DMA3LLTXD1_GlitchData : VitalGlitchDataType; variable DMA3LLTXD2_GlitchData : VitalGlitchDataType; variable DMA3LLTXD3_GlitchData : VitalGlitchDataType; variable DMA3LLTXD4_GlitchData : VitalGlitchDataType; variable DMA3LLTXD5_GlitchData : VitalGlitchDataType; variable DMA3LLTXD6_GlitchData : VitalGlitchDataType; variable DMA3LLTXD7_GlitchData : VitalGlitchDataType; variable DMA3LLTXD8_GlitchData : VitalGlitchDataType; variable DMA3LLTXD9_GlitchData : VitalGlitchDataType; variable DMA3LLTXD10_GlitchData : VitalGlitchDataType; variable DMA3LLTXD11_GlitchData : VitalGlitchDataType; variable DMA3LLTXD12_GlitchData : VitalGlitchDataType; variable DMA3LLTXD13_GlitchData : VitalGlitchDataType; variable DMA3LLTXD14_GlitchData : VitalGlitchDataType; variable DMA3LLTXD15_GlitchData : VitalGlitchDataType; variable DMA3LLTXD16_GlitchData : VitalGlitchDataType; variable DMA3LLTXD17_GlitchData : VitalGlitchDataType; variable DMA3LLTXD18_GlitchData : VitalGlitchDataType; variable DMA3LLTXD19_GlitchData : VitalGlitchDataType; variable DMA3LLTXD20_GlitchData : VitalGlitchDataType; variable DMA3LLTXD21_GlitchData : VitalGlitchDataType; variable DMA3LLTXD22_GlitchData : VitalGlitchDataType; variable DMA3LLTXD23_GlitchData : VitalGlitchDataType; variable DMA3LLTXD24_GlitchData : VitalGlitchDataType; variable DMA3LLTXD25_GlitchData : VitalGlitchDataType; variable DMA3LLTXD26_GlitchData : VitalGlitchDataType; variable DMA3LLTXD27_GlitchData : VitalGlitchDataType; variable DMA3LLTXD28_GlitchData : VitalGlitchDataType; variable DMA3LLTXD29_GlitchData : VitalGlitchDataType; variable DMA3LLTXD30_GlitchData : VitalGlitchDataType; variable DMA3LLTXD31_GlitchData : VitalGlitchDataType; variable DMA3LLTXEOFN_GlitchData : VitalGlitchDataType; variable DMA3LLTXEOPN_GlitchData : VitalGlitchDataType; variable DMA3LLTXREM0_GlitchData : VitalGlitchDataType; variable DMA3LLTXREM1_GlitchData : VitalGlitchDataType; variable DMA3LLTXREM2_GlitchData : VitalGlitchDataType; variable DMA3LLTXREM3_GlitchData : VitalGlitchDataType; variable DMA3LLTXSOFN_GlitchData : VitalGlitchDataType; variable DMA3LLTXSOPN_GlitchData : VitalGlitchDataType; variable DMA3LLTXSRCRDYN_GlitchData : VitalGlitchDataType; variable DMA3RXIRQ_GlitchData : VitalGlitchDataType; variable DMA3TXIRQ_GlitchData : VitalGlitchDataType; variable PPCDMDCRABUS0_GlitchData : VitalGlitchDataType; variable PPCDMDCRABUS1_GlitchData : VitalGlitchDataType; variable PPCDMDCRABUS2_GlitchData : VitalGlitchDataType; variable PPCDMDCRABUS3_GlitchData : VitalGlitchDataType; variable PPCDMDCRABUS4_GlitchData : VitalGlitchDataType; variable PPCDMDCRABUS5_GlitchData : VitalGlitchDataType; variable PPCDMDCRABUS6_GlitchData : VitalGlitchDataType; variable PPCDMDCRABUS7_GlitchData : VitalGlitchDataType; variable PPCDMDCRABUS8_GlitchData : VitalGlitchDataType; variable PPCDMDCRABUS9_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT0_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT1_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT2_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT3_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT4_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT5_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT6_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT7_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT8_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT9_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT10_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT11_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT12_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT13_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT14_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT15_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT16_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT17_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT18_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT19_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT20_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT21_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT22_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT23_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT24_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT25_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT26_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT27_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT28_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT29_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT30_GlitchData : VitalGlitchDataType; variable PPCDMDCRDBUSOUT31_GlitchData : VitalGlitchDataType; variable PPCDMDCRREAD_GlitchData : VitalGlitchDataType; variable PPCDMDCRUABUS20_GlitchData : VitalGlitchDataType; variable PPCDMDCRUABUS21_GlitchData : VitalGlitchDataType; variable PPCDMDCRWRITE_GlitchData : VitalGlitchDataType; variable PPCMPLBABORT_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS0_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS1_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS2_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS3_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS4_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS5_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS6_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS7_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS8_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS9_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS10_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS11_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS12_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS13_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS14_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS15_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS16_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS17_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS18_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS19_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS20_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS21_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS22_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS23_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS24_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS25_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS26_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS27_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS28_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS29_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS30_GlitchData : VitalGlitchDataType; variable PPCMPLBABUS31_GlitchData : VitalGlitchDataType; variable PPCMPLBBE0_GlitchData : VitalGlitchDataType; variable PPCMPLBBE1_GlitchData : VitalGlitchDataType; variable PPCMPLBBE2_GlitchData : VitalGlitchDataType; variable PPCMPLBBE3_GlitchData : VitalGlitchDataType; variable PPCMPLBBE4_GlitchData : VitalGlitchDataType; variable PPCMPLBBE5_GlitchData : VitalGlitchDataType; variable PPCMPLBBE6_GlitchData : VitalGlitchDataType; variable PPCMPLBBE7_GlitchData : VitalGlitchDataType; variable PPCMPLBBE8_GlitchData : VitalGlitchDataType; variable PPCMPLBBE9_GlitchData : VitalGlitchDataType; variable PPCMPLBBE10_GlitchData : VitalGlitchDataType; variable PPCMPLBBE11_GlitchData : VitalGlitchDataType; variable PPCMPLBBE12_GlitchData : VitalGlitchDataType; variable PPCMPLBBE13_GlitchData : VitalGlitchDataType; variable PPCMPLBBE14_GlitchData : VitalGlitchDataType; variable PPCMPLBBE15_GlitchData : VitalGlitchDataType; variable PPCMPLBBUSLOCK_GlitchData : VitalGlitchDataType; variable PPCMPLBLOCKERR_GlitchData : VitalGlitchDataType; variable PPCMPLBPRIORITY0_GlitchData : VitalGlitchDataType; variable PPCMPLBPRIORITY1_GlitchData : VitalGlitchDataType; variable PPCMPLBRDBURST_GlitchData : VitalGlitchDataType; variable PPCMPLBREQUEST_GlitchData : VitalGlitchDataType; variable PPCMPLBRNW_GlitchData : VitalGlitchDataType; variable PPCMPLBSIZE0_GlitchData : VitalGlitchDataType; variable PPCMPLBSIZE1_GlitchData : VitalGlitchDataType; variable PPCMPLBSIZE2_GlitchData : VitalGlitchDataType; variable PPCMPLBSIZE3_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE0_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE1_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE2_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE3_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE4_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE5_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE6_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE7_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE8_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE9_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE10_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE11_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE12_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE13_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE14_GlitchData : VitalGlitchDataType; variable PPCMPLBTATTRIBUTE15_GlitchData : VitalGlitchDataType; variable PPCMPLBTYPE0_GlitchData : VitalGlitchDataType; variable PPCMPLBTYPE1_GlitchData : VitalGlitchDataType; variable PPCMPLBTYPE2_GlitchData : VitalGlitchDataType; variable PPCMPLBUABUS28_GlitchData : VitalGlitchDataType; variable PPCMPLBUABUS29_GlitchData : VitalGlitchDataType; variable PPCMPLBUABUS30_GlitchData : VitalGlitchDataType; variable PPCMPLBUABUS31_GlitchData : VitalGlitchDataType; variable PPCMPLBWRBURST_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS0_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS1_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS2_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS3_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS4_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS5_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS6_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS7_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS8_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS9_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS10_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS11_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS12_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS13_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS14_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS15_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS16_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS17_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS18_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS19_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS20_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS21_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS22_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS23_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS24_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS25_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS26_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS27_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS28_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS29_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS30_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS31_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS32_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS33_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS34_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS35_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS36_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS37_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS38_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS39_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS40_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS41_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS42_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS43_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS44_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS45_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS46_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS47_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS48_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS49_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS50_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS51_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS52_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS53_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS54_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS55_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS56_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS57_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS58_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS59_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS60_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS61_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS62_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS63_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS64_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS65_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS66_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS67_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS68_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS69_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS70_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS71_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS72_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS73_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS74_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS75_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS76_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS77_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS78_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS79_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS80_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS81_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS82_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS83_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS84_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS85_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS86_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS87_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS88_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS89_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS90_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS91_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS92_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS93_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS94_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS95_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS96_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS97_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS98_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS99_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS100_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS101_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS102_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS103_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS104_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS105_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS106_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS107_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS108_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS109_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS110_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS111_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS112_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS113_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS114_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS115_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS116_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS117_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS118_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS119_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS120_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS121_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS122_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS123_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS124_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS125_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS126_GlitchData : VitalGlitchDataType; variable PPCMPLBWRDBUS127_GlitchData : VitalGlitchDataType; variable PPCS0PLBADDRACK_GlitchData : VitalGlitchDataType; variable PPCS0PLBMBUSY0_GlitchData : VitalGlitchDataType; variable PPCS0PLBMBUSY1_GlitchData : VitalGlitchDataType; variable PPCS0PLBMBUSY2_GlitchData : VitalGlitchDataType; variable PPCS0PLBMBUSY3_GlitchData : VitalGlitchDataType; variable PPCS0PLBMIRQ0_GlitchData : VitalGlitchDataType; variable PPCS0PLBMIRQ1_GlitchData : VitalGlitchDataType; variable PPCS0PLBMIRQ2_GlitchData : VitalGlitchDataType; variable PPCS0PLBMIRQ3_GlitchData : VitalGlitchDataType; variable PPCS0PLBMRDERR0_GlitchData : VitalGlitchDataType; variable PPCS0PLBMRDERR1_GlitchData : VitalGlitchDataType; variable PPCS0PLBMRDERR2_GlitchData : VitalGlitchDataType; variable PPCS0PLBMRDERR3_GlitchData : VitalGlitchDataType; variable PPCS0PLBMWRERR0_GlitchData : VitalGlitchDataType; variable PPCS0PLBMWRERR1_GlitchData : VitalGlitchDataType; variable PPCS0PLBMWRERR2_GlitchData : VitalGlitchDataType; variable PPCS0PLBMWRERR3_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDBTERM_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDCOMP_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDACK_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS0_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS1_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS2_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS3_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS4_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS5_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS6_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS7_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS8_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS9_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS10_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS11_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS12_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS13_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS14_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS15_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS16_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS17_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS18_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS19_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS20_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS21_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS22_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS23_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS24_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS25_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS26_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS27_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS28_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS29_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS30_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS31_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS32_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS33_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS34_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS35_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS36_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS37_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS38_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS39_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS40_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS41_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS42_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS43_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS44_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS45_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS46_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS47_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS48_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS49_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS50_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS51_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS52_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS53_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS54_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS55_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS56_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS57_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS58_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS59_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS60_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS61_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS62_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS63_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS64_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS65_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS66_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS67_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS68_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS69_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS70_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS71_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS72_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS73_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS74_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS75_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS76_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS77_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS78_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS79_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS80_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS81_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS82_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS83_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS84_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS85_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS86_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS87_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS88_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS89_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS90_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS91_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS92_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS93_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS94_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS95_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS96_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS97_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS98_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS99_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS100_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS101_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS102_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS103_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS104_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS105_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS106_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS107_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS108_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS109_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS110_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS111_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS112_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS113_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS114_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS115_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS116_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS117_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS118_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS119_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS120_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS121_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS122_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS123_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS124_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS125_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS126_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDDBUS127_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDWDADDR0_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDWDADDR1_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDWDADDR2_GlitchData : VitalGlitchDataType; variable PPCS0PLBRDWDADDR3_GlitchData : VitalGlitchDataType; variable PPCS0PLBREARBITRATE_GlitchData : VitalGlitchDataType; variable PPCS0PLBSSIZE0_GlitchData : VitalGlitchDataType; variable PPCS0PLBSSIZE1_GlitchData : VitalGlitchDataType; variable PPCS0PLBWAIT_GlitchData : VitalGlitchDataType; variable PPCS0PLBWRBTERM_GlitchData : VitalGlitchDataType; variable PPCS0PLBWRCOMP_GlitchData : VitalGlitchDataType; variable PPCS0PLBWRDACK_GlitchData : VitalGlitchDataType; variable PPCS1PLBADDRACK_GlitchData : VitalGlitchDataType; variable PPCS1PLBMBUSY0_GlitchData : VitalGlitchDataType; variable PPCS1PLBMBUSY1_GlitchData : VitalGlitchDataType; variable PPCS1PLBMBUSY2_GlitchData : VitalGlitchDataType; variable PPCS1PLBMBUSY3_GlitchData : VitalGlitchDataType; variable PPCS1PLBMIRQ0_GlitchData : VitalGlitchDataType; variable PPCS1PLBMIRQ1_GlitchData : VitalGlitchDataType; variable PPCS1PLBMIRQ2_GlitchData : VitalGlitchDataType; variable PPCS1PLBMIRQ3_GlitchData : VitalGlitchDataType; variable PPCS1PLBMRDERR0_GlitchData : VitalGlitchDataType; variable PPCS1PLBMRDERR1_GlitchData : VitalGlitchDataType; variable PPCS1PLBMRDERR2_GlitchData : VitalGlitchDataType; variable PPCS1PLBMRDERR3_GlitchData : VitalGlitchDataType; variable PPCS1PLBMWRERR0_GlitchData : VitalGlitchDataType; variable PPCS1PLBMWRERR1_GlitchData : VitalGlitchDataType; variable PPCS1PLBMWRERR2_GlitchData : VitalGlitchDataType; variable PPCS1PLBMWRERR3_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDBTERM_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDCOMP_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDACK_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS0_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS1_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS2_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS3_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS4_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS5_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS6_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS7_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS8_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS9_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS10_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS11_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS12_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS13_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS14_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS15_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS16_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS17_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS18_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS19_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS20_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS21_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS22_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS23_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS24_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS25_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS26_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS27_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS28_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS29_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS30_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS31_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS32_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS33_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS34_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS35_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS36_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS37_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS38_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS39_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS40_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS41_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS42_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS43_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS44_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS45_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS46_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS47_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS48_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS49_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS50_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS51_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS52_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS53_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS54_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS55_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS56_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS57_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS58_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS59_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS60_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS61_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS62_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS63_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS64_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS65_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS66_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS67_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS68_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS69_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS70_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS71_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS72_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS73_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS74_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS75_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS76_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS77_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS78_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS79_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS80_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS81_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS82_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS83_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS84_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS85_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS86_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS87_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS88_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS89_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS90_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS91_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS92_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS93_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS94_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS95_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS96_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS97_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS98_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS99_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS100_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS101_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS102_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS103_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS104_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS105_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS106_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS107_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS108_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS109_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS110_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS111_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS112_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS113_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS114_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS115_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS116_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS117_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS118_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS119_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS120_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS121_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS122_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS123_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS124_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS125_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS126_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDDBUS127_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDWDADDR0_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDWDADDR1_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDWDADDR2_GlitchData : VitalGlitchDataType; variable PPCS1PLBRDWDADDR3_GlitchData : VitalGlitchDataType; variable PPCS1PLBREARBITRATE_GlitchData : VitalGlitchDataType; variable PPCS1PLBSSIZE0_GlitchData : VitalGlitchDataType; variable PPCS1PLBSSIZE1_GlitchData : VitalGlitchDataType; variable PPCS1PLBWAIT_GlitchData : VitalGlitchDataType; variable PPCS1PLBWRBTERM_GlitchData : VitalGlitchDataType; variable PPCS1PLBWRCOMP_GlitchData : VitalGlitchDataType; variable PPCS1PLBWRDACK_GlitchData : VitalGlitchDataType; variable APUFCMDECFPUOP_GlitchData : VitalGlitchDataType; variable APUFCMDECLDSTXFERSIZE0_GlitchData : VitalGlitchDataType; variable APUFCMDECLDSTXFERSIZE1_GlitchData : VitalGlitchDataType; variable APUFCMDECLDSTXFERSIZE2_GlitchData : VitalGlitchDataType; variable APUFCMDECLOAD_GlitchData : VitalGlitchDataType; variable APUFCMDECNONAUTON_GlitchData : VitalGlitchDataType; variable APUFCMDECSTORE_GlitchData : VitalGlitchDataType; variable APUFCMDECUDI0_GlitchData : VitalGlitchDataType; variable APUFCMDECUDI1_GlitchData : VitalGlitchDataType; variable APUFCMDECUDI2_GlitchData : VitalGlitchDataType; variable APUFCMDECUDI3_GlitchData : VitalGlitchDataType; variable APUFCMDECUDIVALID_GlitchData : VitalGlitchDataType; variable APUFCMENDIAN_GlitchData : VitalGlitchDataType; variable APUFCMFLUSH_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION0_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION1_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION2_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION3_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION4_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION5_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION6_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION7_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION8_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION9_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION10_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION11_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION12_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION13_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION14_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION15_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION16_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION17_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION18_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION19_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION20_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION21_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION22_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION23_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION24_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION25_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION26_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION27_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION28_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION29_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION30_GlitchData : VitalGlitchDataType; variable APUFCMINSTRUCTION31_GlitchData : VitalGlitchDataType; variable APUFCMINSTRVALID_GlitchData : VitalGlitchDataType; variable APUFCMLOADBYTEADDR0_GlitchData : VitalGlitchDataType; variable APUFCMLOADBYTEADDR1_GlitchData : VitalGlitchDataType; variable APUFCMLOADBYTEADDR2_GlitchData : VitalGlitchDataType; variable APUFCMLOADBYTEADDR3_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA0_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA1_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA2_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA3_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA4_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA5_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA6_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA7_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA8_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA9_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA10_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA11_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA12_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA13_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA14_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA15_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA16_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA17_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA18_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA19_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA20_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA21_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA22_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA23_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA24_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA25_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA26_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA27_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA28_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA29_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA30_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA31_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA32_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA33_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA34_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA35_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA36_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA37_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA38_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA39_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA40_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA41_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA42_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA43_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA44_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA45_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA46_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA47_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA48_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA49_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA50_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA51_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA52_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA53_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA54_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA55_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA56_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA57_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA58_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA59_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA60_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA61_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA62_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA63_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA64_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA65_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA66_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA67_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA68_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA69_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA70_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA71_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA72_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA73_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA74_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA75_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA76_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA77_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA78_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA79_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA80_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA81_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA82_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA83_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA84_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA85_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA86_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA87_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA88_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA89_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA90_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA91_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA92_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA93_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA94_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA95_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA96_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA97_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA98_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA99_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA100_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA101_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA102_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA103_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA104_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA105_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA106_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA107_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA108_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA109_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA110_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA111_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA112_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA113_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA114_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA115_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA116_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA117_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA118_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA119_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA120_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA121_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA122_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA123_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA124_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA125_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA126_GlitchData : VitalGlitchDataType; variable APUFCMLOADDATA127_GlitchData : VitalGlitchDataType; variable APUFCMLOADDVALID_GlitchData : VitalGlitchDataType; variable APUFCMMSRFE0_GlitchData : VitalGlitchDataType; variable APUFCMMSRFE1_GlitchData : VitalGlitchDataType; variable APUFCMNEXTINSTRREADY_GlitchData : VitalGlitchDataType; variable APUFCMOPERANDVALID_GlitchData : VitalGlitchDataType; variable APUFCMRADATA0_GlitchData : VitalGlitchDataType; variable APUFCMRADATA1_GlitchData : VitalGlitchDataType; variable APUFCMRADATA2_GlitchData : VitalGlitchDataType; variable APUFCMRADATA3_GlitchData : VitalGlitchDataType; variable APUFCMRADATA4_GlitchData : VitalGlitchDataType; variable APUFCMRADATA5_GlitchData : VitalGlitchDataType; variable APUFCMRADATA6_GlitchData : VitalGlitchDataType; variable APUFCMRADATA7_GlitchData : VitalGlitchDataType; variable APUFCMRADATA8_GlitchData : VitalGlitchDataType; variable APUFCMRADATA9_GlitchData : VitalGlitchDataType; variable APUFCMRADATA10_GlitchData : VitalGlitchDataType; variable APUFCMRADATA11_GlitchData : VitalGlitchDataType; variable APUFCMRADATA12_GlitchData : VitalGlitchDataType; variable APUFCMRADATA13_GlitchData : VitalGlitchDataType; variable APUFCMRADATA14_GlitchData : VitalGlitchDataType; variable APUFCMRADATA15_GlitchData : VitalGlitchDataType; variable APUFCMRADATA16_GlitchData : VitalGlitchDataType; variable APUFCMRADATA17_GlitchData : VitalGlitchDataType; variable APUFCMRADATA18_GlitchData : VitalGlitchDataType; variable APUFCMRADATA19_GlitchData : VitalGlitchDataType; variable APUFCMRADATA20_GlitchData : VitalGlitchDataType; variable APUFCMRADATA21_GlitchData : VitalGlitchDataType; variable APUFCMRADATA22_GlitchData : VitalGlitchDataType; variable APUFCMRADATA23_GlitchData : VitalGlitchDataType; variable APUFCMRADATA24_GlitchData : VitalGlitchDataType; variable APUFCMRADATA25_GlitchData : VitalGlitchDataType; variable APUFCMRADATA26_GlitchData : VitalGlitchDataType; variable APUFCMRADATA27_GlitchData : VitalGlitchDataType; variable APUFCMRADATA28_GlitchData : VitalGlitchDataType; variable APUFCMRADATA29_GlitchData : VitalGlitchDataType; variable APUFCMRADATA30_GlitchData : VitalGlitchDataType; variable APUFCMRADATA31_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA0_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA1_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA2_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA3_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA4_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA5_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA6_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA7_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA8_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA9_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA10_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA11_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA12_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA13_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA14_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA15_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA16_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA17_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA18_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA19_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA20_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA21_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA22_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA23_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA24_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA25_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA26_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA27_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA28_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA29_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA30_GlitchData : VitalGlitchDataType; variable APUFCMRBDATA31_GlitchData : VitalGlitchDataType; variable APUFCMWRITEBACKOK_GlitchData : VitalGlitchDataType; variable C440CPMCORESLEEPREQ_GlitchData : VitalGlitchDataType; variable C440CPMDECIRPTREQ_GlitchData : VitalGlitchDataType; variable C440CPMFITIRPTREQ_GlitchData : VitalGlitchDataType; variable C440CPMMSRCE_GlitchData : VitalGlitchDataType; variable C440CPMMSREE_GlitchData : VitalGlitchDataType; variable C440CPMTIMERRESETREQ_GlitchData : VitalGlitchDataType; variable C440CPMWDIRPTREQ_GlitchData : VitalGlitchDataType; variable C440DBGSYSTEMCONTROL0_GlitchData : VitalGlitchDataType; variable C440DBGSYSTEMCONTROL1_GlitchData : VitalGlitchDataType; variable C440DBGSYSTEMCONTROL2_GlitchData : VitalGlitchDataType; variable C440DBGSYSTEMCONTROL3_GlitchData : VitalGlitchDataType; variable C440DBGSYSTEMCONTROL4_GlitchData : VitalGlitchDataType; variable C440DBGSYSTEMCONTROL5_GlitchData : VitalGlitchDataType; variable C440DBGSYSTEMCONTROL6_GlitchData : VitalGlitchDataType; variable C440DBGSYSTEMCONTROL7_GlitchData : VitalGlitchDataType; variable C440JTGTDO_GlitchData : VitalGlitchDataType; variable C440JTGTDOEN_GlitchData : VitalGlitchDataType; variable C440MACHINECHECK_GlitchData : VitalGlitchDataType; variable C440RSTCHIPRESETREQ_GlitchData : VitalGlitchDataType; variable C440RSTCORERESETREQ_GlitchData : VitalGlitchDataType; variable C440RSTSYSTEMRESETREQ_GlitchData : VitalGlitchDataType; variable C440TRCBRANCHSTATUS0_GlitchData : VitalGlitchDataType; variable C440TRCBRANCHSTATUS1_GlitchData : VitalGlitchDataType; variable C440TRCBRANCHSTATUS2_GlitchData : VitalGlitchDataType; variable C440TRCCYCLE_GlitchData : VitalGlitchDataType; variable C440TRCEXECUTIONSTATUS0_GlitchData : VitalGlitchDataType; variable C440TRCEXECUTIONSTATUS1_GlitchData : VitalGlitchDataType; variable C440TRCEXECUTIONSTATUS2_GlitchData : VitalGlitchDataType; variable C440TRCEXECUTIONSTATUS3_GlitchData : VitalGlitchDataType; variable C440TRCEXECUTIONSTATUS4_GlitchData : VitalGlitchDataType; variable C440TRCTRACESTATUS0_GlitchData : VitalGlitchDataType; variable C440TRCTRACESTATUS1_GlitchData : VitalGlitchDataType; variable C440TRCTRACESTATUS2_GlitchData : VitalGlitchDataType; variable C440TRCTRACESTATUS3_GlitchData : VitalGlitchDataType; variable C440TRCTRACESTATUS4_GlitchData : VitalGlitchDataType; variable C440TRCTRACESTATUS5_GlitchData : VitalGlitchDataType; variable C440TRCTRACESTATUS6_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTOUT_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE0_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE1_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE2_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE3_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE4_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE5_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE6_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE7_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE8_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE9_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE10_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE11_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE12_GlitchData : VitalGlitchDataType; variable C440TRCTRIGGEREVENTTYPE13_GlitchData : VitalGlitchDataType; variable MIMCADDRESS0_GlitchData : VitalGlitchDataType; variable MIMCADDRESS1_GlitchData : VitalGlitchDataType; variable MIMCADDRESS2_GlitchData : VitalGlitchDataType; variable MIMCADDRESS3_GlitchData : VitalGlitchDataType; variable MIMCADDRESS4_GlitchData : VitalGlitchDataType; variable MIMCADDRESS5_GlitchData : VitalGlitchDataType; variable MIMCADDRESS6_GlitchData : VitalGlitchDataType; variable MIMCADDRESS7_GlitchData : VitalGlitchDataType; variable MIMCADDRESS8_GlitchData : VitalGlitchDataType; variable MIMCADDRESS9_GlitchData : VitalGlitchDataType; variable MIMCADDRESS10_GlitchData : VitalGlitchDataType; variable MIMCADDRESS11_GlitchData : VitalGlitchDataType; variable MIMCADDRESS12_GlitchData : VitalGlitchDataType; variable MIMCADDRESS13_GlitchData : VitalGlitchDataType; variable MIMCADDRESS14_GlitchData : VitalGlitchDataType; variable MIMCADDRESS15_GlitchData : VitalGlitchDataType; variable MIMCADDRESS16_GlitchData : VitalGlitchDataType; variable MIMCADDRESS17_GlitchData : VitalGlitchDataType; variable MIMCADDRESS18_GlitchData : VitalGlitchDataType; variable MIMCADDRESS19_GlitchData : VitalGlitchDataType; variable MIMCADDRESS20_GlitchData : VitalGlitchDataType; variable MIMCADDRESS21_GlitchData : VitalGlitchDataType; variable MIMCADDRESS22_GlitchData : VitalGlitchDataType; variable MIMCADDRESS23_GlitchData : VitalGlitchDataType; variable MIMCADDRESS24_GlitchData : VitalGlitchDataType; variable MIMCADDRESS25_GlitchData : VitalGlitchDataType; variable MIMCADDRESS26_GlitchData : VitalGlitchDataType; variable MIMCADDRESS27_GlitchData : VitalGlitchDataType; variable MIMCADDRESS28_GlitchData : VitalGlitchDataType; variable MIMCADDRESS29_GlitchData : VitalGlitchDataType; variable MIMCADDRESS30_GlitchData : VitalGlitchDataType; variable MIMCADDRESS31_GlitchData : VitalGlitchDataType; variable MIMCADDRESS32_GlitchData : VitalGlitchDataType; variable MIMCADDRESS33_GlitchData : VitalGlitchDataType; variable MIMCADDRESS34_GlitchData : VitalGlitchDataType; variable MIMCADDRESS35_GlitchData : VitalGlitchDataType; variable MIMCADDRESSVALID_GlitchData : VitalGlitchDataType; variable MIMCBANKCONFLICT_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE0_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE1_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE2_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE3_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE4_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE5_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE6_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE7_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE8_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE9_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE10_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE11_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE12_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE13_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE14_GlitchData : VitalGlitchDataType; variable MIMCBYTEENABLE15_GlitchData : VitalGlitchDataType; variable MIMCREADNOTWRITE_GlitchData : VitalGlitchDataType; variable MIMCROWCONFLICT_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA0_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA1_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA2_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA3_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA4_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA5_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA6_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA7_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA8_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA9_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA10_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA11_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA12_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA13_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA14_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA15_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA16_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA17_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA18_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA19_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA20_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA21_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA22_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA23_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA24_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA25_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA26_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA27_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA28_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA29_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA30_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA31_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA32_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA33_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA34_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA35_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA36_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA37_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA38_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA39_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA40_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA41_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA42_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA43_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA44_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA45_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA46_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA47_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA48_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA49_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA50_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA51_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA52_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA53_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA54_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA55_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA56_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA57_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA58_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA59_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA60_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA61_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA62_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA63_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA64_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA65_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA66_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA67_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA68_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA69_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA70_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA71_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA72_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA73_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA74_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA75_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA76_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA77_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA78_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA79_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA80_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA81_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA82_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA83_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA84_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA85_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA86_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA87_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA88_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA89_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA90_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA91_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA92_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA93_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA94_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA95_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA96_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA97_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA98_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA99_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA100_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA101_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA102_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA103_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA104_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA105_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA106_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA107_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA108_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA109_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA110_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA111_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA112_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA113_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA114_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA115_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA116_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA117_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA118_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA119_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA120_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA121_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA122_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA123_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA124_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA125_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA126_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATA127_GlitchData : VitalGlitchDataType; variable MIMCWRITEDATAVALID_GlitchData : VitalGlitchDataType; variable PPCCPMINTERCONNECTBUSY_GlitchData : VitalGlitchDataType; variable PPCDSDCRACK_GlitchData : VitalGlitchDataType; variable PPCDSDCRTIMEOUTWAIT_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN0_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN1_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN2_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN3_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN4_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN5_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN6_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN7_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN8_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN9_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN10_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN11_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN12_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN13_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN14_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN15_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN16_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN17_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN18_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN19_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN20_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN21_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN22_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN23_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN24_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN25_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN26_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN27_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN28_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN29_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN30_GlitchData : VitalGlitchDataType; variable PPCDSDCRDBUSIN31_GlitchData : VitalGlitchDataType; variable PPCEICINTERCONNECTIRQ_GlitchData : VitalGlitchDataType; begin VitalPathDelay01 ( OutSignal => DMA0LLRSTENGINEACK, GlitchData => DMA0LLRSTENGINEACK_GlitchData, OutSignalName => "DMA0LLRSTENGINEACK", OutTemp => DMA0LLRSTENGINEACK_OUT, Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLRXDSTRDYN, GlitchData => DMA0LLRXDSTRDYN_GlitchData, OutSignalName => "DMA0LLRXDSTRDYN", OutTemp => DMA0LLRXDSTRDYN_OUT, Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(0), GlitchData => DMA0LLTXD0_GlitchData, OutSignalName => "DMA0LLTXD(0)", OutTemp => DMA0LLTXD_OUT(0), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(1), GlitchData => DMA0LLTXD1_GlitchData, OutSignalName => "DMA0LLTXD(1)", OutTemp => DMA0LLTXD_OUT(1), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(2), GlitchData => DMA0LLTXD2_GlitchData, OutSignalName => "DMA0LLTXD(2)", OutTemp => DMA0LLTXD_OUT(2), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(3), GlitchData => DMA0LLTXD3_GlitchData, OutSignalName => "DMA0LLTXD(3)", OutTemp => DMA0LLTXD_OUT(3), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(4), GlitchData => DMA0LLTXD4_GlitchData, OutSignalName => "DMA0LLTXD(4)", OutTemp => DMA0LLTXD_OUT(4), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(5), GlitchData => DMA0LLTXD5_GlitchData, OutSignalName => "DMA0LLTXD(5)", OutTemp => DMA0LLTXD_OUT(5), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(6), GlitchData => DMA0LLTXD6_GlitchData, OutSignalName => "DMA0LLTXD(6)", OutTemp => DMA0LLTXD_OUT(6), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(7), GlitchData => DMA0LLTXD7_GlitchData, OutSignalName => "DMA0LLTXD(7)", OutTemp => DMA0LLTXD_OUT(7), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(8), GlitchData => DMA0LLTXD8_GlitchData, OutSignalName => "DMA0LLTXD(8)", OutTemp => DMA0LLTXD_OUT(8), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(9), GlitchData => DMA0LLTXD9_GlitchData, OutSignalName => "DMA0LLTXD(9)", OutTemp => DMA0LLTXD_OUT(9), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(10), GlitchData => DMA0LLTXD10_GlitchData, OutSignalName => "DMA0LLTXD(10)", OutTemp => DMA0LLTXD_OUT(10), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(11), GlitchData => DMA0LLTXD11_GlitchData, OutSignalName => "DMA0LLTXD(11)", OutTemp => DMA0LLTXD_OUT(11), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(12), GlitchData => DMA0LLTXD12_GlitchData, OutSignalName => "DMA0LLTXD(12)", OutTemp => DMA0LLTXD_OUT(12), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(13), GlitchData => DMA0LLTXD13_GlitchData, OutSignalName => "DMA0LLTXD(13)", OutTemp => DMA0LLTXD_OUT(13), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(14), GlitchData => DMA0LLTXD14_GlitchData, OutSignalName => "DMA0LLTXD(14)", OutTemp => DMA0LLTXD_OUT(14), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(15), GlitchData => DMA0LLTXD15_GlitchData, OutSignalName => "DMA0LLTXD(15)", OutTemp => DMA0LLTXD_OUT(15), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(16), GlitchData => DMA0LLTXD16_GlitchData, OutSignalName => "DMA0LLTXD(16)", OutTemp => DMA0LLTXD_OUT(16), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(17), GlitchData => DMA0LLTXD17_GlitchData, OutSignalName => "DMA0LLTXD(17)", OutTemp => DMA0LLTXD_OUT(17), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(18), GlitchData => DMA0LLTXD18_GlitchData, OutSignalName => "DMA0LLTXD(18)", OutTemp => DMA0LLTXD_OUT(18), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(19), GlitchData => DMA0LLTXD19_GlitchData, OutSignalName => "DMA0LLTXD(19)", OutTemp => DMA0LLTXD_OUT(19), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(20), GlitchData => DMA0LLTXD20_GlitchData, OutSignalName => "DMA0LLTXD(20)", OutTemp => DMA0LLTXD_OUT(20), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(21), GlitchData => DMA0LLTXD21_GlitchData, OutSignalName => "DMA0LLTXD(21)", OutTemp => DMA0LLTXD_OUT(21), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(22), GlitchData => DMA0LLTXD22_GlitchData, OutSignalName => "DMA0LLTXD(22)", OutTemp => DMA0LLTXD_OUT(22), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(23), GlitchData => DMA0LLTXD23_GlitchData, OutSignalName => "DMA0LLTXD(23)", OutTemp => DMA0LLTXD_OUT(23), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(24), GlitchData => DMA0LLTXD24_GlitchData, OutSignalName => "DMA0LLTXD(24)", OutTemp => DMA0LLTXD_OUT(24), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(25), GlitchData => DMA0LLTXD25_GlitchData, OutSignalName => "DMA0LLTXD(25)", OutTemp => DMA0LLTXD_OUT(25), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(26), GlitchData => DMA0LLTXD26_GlitchData, OutSignalName => "DMA0LLTXD(26)", OutTemp => DMA0LLTXD_OUT(26), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(27), GlitchData => DMA0LLTXD27_GlitchData, OutSignalName => "DMA0LLTXD(27)", OutTemp => DMA0LLTXD_OUT(27), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(28), GlitchData => DMA0LLTXD28_GlitchData, OutSignalName => "DMA0LLTXD(28)", OutTemp => DMA0LLTXD_OUT(28), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(29), GlitchData => DMA0LLTXD29_GlitchData, OutSignalName => "DMA0LLTXD(29)", OutTemp => DMA0LLTXD_OUT(29), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(30), GlitchData => DMA0LLTXD30_GlitchData, OutSignalName => "DMA0LLTXD(30)", OutTemp => DMA0LLTXD_OUT(30), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXD(31), GlitchData => DMA0LLTXD31_GlitchData, OutSignalName => "DMA0LLTXD(31)", OutTemp => DMA0LLTXD_OUT(31), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXEOFN, GlitchData => DMA0LLTXEOFN_GlitchData, OutSignalName => "DMA0LLTXEOFN", OutTemp => DMA0LLTXEOFN_OUT, Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXEOPN, GlitchData => DMA0LLTXEOPN_GlitchData, OutSignalName => "DMA0LLTXEOPN", OutTemp => DMA0LLTXEOPN_OUT, Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXREM(0), GlitchData => DMA0LLTXREM0_GlitchData, OutSignalName => "DMA0LLTXREM(0)", OutTemp => DMA0LLTXREM_OUT(0), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXREM(1), GlitchData => DMA0LLTXREM1_GlitchData, OutSignalName => "DMA0LLTXREM(1)", OutTemp => DMA0LLTXREM_OUT(1), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXREM(2), GlitchData => DMA0LLTXREM2_GlitchData, OutSignalName => "DMA0LLTXREM(2)", OutTemp => DMA0LLTXREM_OUT(2), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXREM(3), GlitchData => DMA0LLTXREM3_GlitchData, OutSignalName => "DMA0LLTXREM(3)", OutTemp => DMA0LLTXREM_OUT(3), Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXSOFN, GlitchData => DMA0LLTXSOFN_GlitchData, OutSignalName => "DMA0LLTXSOFN", OutTemp => DMA0LLTXSOFN_OUT, Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXSOPN, GlitchData => DMA0LLTXSOPN_GlitchData, OutSignalName => "DMA0LLTXSOPN", OutTemp => DMA0LLTXSOPN_OUT, Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0LLTXSRCRDYN, GlitchData => DMA0LLTXSRCRDYN_GlitchData, OutSignalName => "DMA0LLTXSRCRDYN", OutTemp => DMA0LLTXSRCRDYN_OUT, Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0RXIRQ, GlitchData => DMA0RXIRQ_GlitchData, OutSignalName => "DMA0RXIRQ", OutTemp => DMA0RXIRQ_OUT, Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA0TXIRQ, GlitchData => DMA0TXIRQ_GlitchData, OutSignalName => "DMA0TXIRQ", OutTemp => DMA0TXIRQ_OUT, Paths => (0 => (CPMDMA0LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLRSTENGINEACK, GlitchData => DMA1LLRSTENGINEACK_GlitchData, OutSignalName => "DMA1LLRSTENGINEACK", OutTemp => DMA1LLRSTENGINEACK_OUT, Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLRXDSTRDYN, GlitchData => DMA1LLRXDSTRDYN_GlitchData, OutSignalName => "DMA1LLRXDSTRDYN", OutTemp => DMA1LLRXDSTRDYN_OUT, Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(0), GlitchData => DMA1LLTXD0_GlitchData, OutSignalName => "DMA1LLTXD(0)", OutTemp => DMA1LLTXD_OUT(0), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(1), GlitchData => DMA1LLTXD1_GlitchData, OutSignalName => "DMA1LLTXD(1)", OutTemp => DMA1LLTXD_OUT(1), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(2), GlitchData => DMA1LLTXD2_GlitchData, OutSignalName => "DMA1LLTXD(2)", OutTemp => DMA1LLTXD_OUT(2), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(3), GlitchData => DMA1LLTXD3_GlitchData, OutSignalName => "DMA1LLTXD(3)", OutTemp => DMA1LLTXD_OUT(3), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(4), GlitchData => DMA1LLTXD4_GlitchData, OutSignalName => "DMA1LLTXD(4)", OutTemp => DMA1LLTXD_OUT(4), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(5), GlitchData => DMA1LLTXD5_GlitchData, OutSignalName => "DMA1LLTXD(5)", OutTemp => DMA1LLTXD_OUT(5), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(6), GlitchData => DMA1LLTXD6_GlitchData, OutSignalName => "DMA1LLTXD(6)", OutTemp => DMA1LLTXD_OUT(6), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(7), GlitchData => DMA1LLTXD7_GlitchData, OutSignalName => "DMA1LLTXD(7)", OutTemp => DMA1LLTXD_OUT(7), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(8), GlitchData => DMA1LLTXD8_GlitchData, OutSignalName => "DMA1LLTXD(8)", OutTemp => DMA1LLTXD_OUT(8), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(9), GlitchData => DMA1LLTXD9_GlitchData, OutSignalName => "DMA1LLTXD(9)", OutTemp => DMA1LLTXD_OUT(9), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(10), GlitchData => DMA1LLTXD10_GlitchData, OutSignalName => "DMA1LLTXD(10)", OutTemp => DMA1LLTXD_OUT(10), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(11), GlitchData => DMA1LLTXD11_GlitchData, OutSignalName => "DMA1LLTXD(11)", OutTemp => DMA1LLTXD_OUT(11), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(12), GlitchData => DMA1LLTXD12_GlitchData, OutSignalName => "DMA1LLTXD(12)", OutTemp => DMA1LLTXD_OUT(12), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(13), GlitchData => DMA1LLTXD13_GlitchData, OutSignalName => "DMA1LLTXD(13)", OutTemp => DMA1LLTXD_OUT(13), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(14), GlitchData => DMA1LLTXD14_GlitchData, OutSignalName => "DMA1LLTXD(14)", OutTemp => DMA1LLTXD_OUT(14), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(15), GlitchData => DMA1LLTXD15_GlitchData, OutSignalName => "DMA1LLTXD(15)", OutTemp => DMA1LLTXD_OUT(15), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(16), GlitchData => DMA1LLTXD16_GlitchData, OutSignalName => "DMA1LLTXD(16)", OutTemp => DMA1LLTXD_OUT(16), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(17), GlitchData => DMA1LLTXD17_GlitchData, OutSignalName => "DMA1LLTXD(17)", OutTemp => DMA1LLTXD_OUT(17), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(18), GlitchData => DMA1LLTXD18_GlitchData, OutSignalName => "DMA1LLTXD(18)", OutTemp => DMA1LLTXD_OUT(18), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(19), GlitchData => DMA1LLTXD19_GlitchData, OutSignalName => "DMA1LLTXD(19)", OutTemp => DMA1LLTXD_OUT(19), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(20), GlitchData => DMA1LLTXD20_GlitchData, OutSignalName => "DMA1LLTXD(20)", OutTemp => DMA1LLTXD_OUT(20), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(21), GlitchData => DMA1LLTXD21_GlitchData, OutSignalName => "DMA1LLTXD(21)", OutTemp => DMA1LLTXD_OUT(21), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(22), GlitchData => DMA1LLTXD22_GlitchData, OutSignalName => "DMA1LLTXD(22)", OutTemp => DMA1LLTXD_OUT(22), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(23), GlitchData => DMA1LLTXD23_GlitchData, OutSignalName => "DMA1LLTXD(23)", OutTemp => DMA1LLTXD_OUT(23), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(24), GlitchData => DMA1LLTXD24_GlitchData, OutSignalName => "DMA1LLTXD(24)", OutTemp => DMA1LLTXD_OUT(24), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(25), GlitchData => DMA1LLTXD25_GlitchData, OutSignalName => "DMA1LLTXD(25)", OutTemp => DMA1LLTXD_OUT(25), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(26), GlitchData => DMA1LLTXD26_GlitchData, OutSignalName => "DMA1LLTXD(26)", OutTemp => DMA1LLTXD_OUT(26), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(27), GlitchData => DMA1LLTXD27_GlitchData, OutSignalName => "DMA1LLTXD(27)", OutTemp => DMA1LLTXD_OUT(27), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(28), GlitchData => DMA1LLTXD28_GlitchData, OutSignalName => "DMA1LLTXD(28)", OutTemp => DMA1LLTXD_OUT(28), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(29), GlitchData => DMA1LLTXD29_GlitchData, OutSignalName => "DMA1LLTXD(29)", OutTemp => DMA1LLTXD_OUT(29), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(30), GlitchData => DMA1LLTXD30_GlitchData, OutSignalName => "DMA1LLTXD(30)", OutTemp => DMA1LLTXD_OUT(30), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXD(31), GlitchData => DMA1LLTXD31_GlitchData, OutSignalName => "DMA1LLTXD(31)", OutTemp => DMA1LLTXD_OUT(31), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXEOFN, GlitchData => DMA1LLTXEOFN_GlitchData, OutSignalName => "DMA1LLTXEOFN", OutTemp => DMA1LLTXEOFN_OUT, Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXEOPN, GlitchData => DMA1LLTXEOPN_GlitchData, OutSignalName => "DMA1LLTXEOPN", OutTemp => DMA1LLTXEOPN_OUT, Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXREM(0), GlitchData => DMA1LLTXREM0_GlitchData, OutSignalName => "DMA1LLTXREM(0)", OutTemp => DMA1LLTXREM_OUT(0), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXREM(1), GlitchData => DMA1LLTXREM1_GlitchData, OutSignalName => "DMA1LLTXREM(1)", OutTemp => DMA1LLTXREM_OUT(1), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXREM(2), GlitchData => DMA1LLTXREM2_GlitchData, OutSignalName => "DMA1LLTXREM(2)", OutTemp => DMA1LLTXREM_OUT(2), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXREM(3), GlitchData => DMA1LLTXREM3_GlitchData, OutSignalName => "DMA1LLTXREM(3)", OutTemp => DMA1LLTXREM_OUT(3), Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXSOFN, GlitchData => DMA1LLTXSOFN_GlitchData, OutSignalName => "DMA1LLTXSOFN", OutTemp => DMA1LLTXSOFN_OUT, Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXSOPN, GlitchData => DMA1LLTXSOPN_GlitchData, OutSignalName => "DMA1LLTXSOPN", OutTemp => DMA1LLTXSOPN_OUT, Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1LLTXSRCRDYN, GlitchData => DMA1LLTXSRCRDYN_GlitchData, OutSignalName => "DMA1LLTXSRCRDYN", OutTemp => DMA1LLTXSRCRDYN_OUT, Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1RXIRQ, GlitchData => DMA1RXIRQ_GlitchData, OutSignalName => "DMA1RXIRQ", OutTemp => DMA1RXIRQ_OUT, Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA1TXIRQ, GlitchData => DMA1TXIRQ_GlitchData, OutSignalName => "DMA1TXIRQ", OutTemp => DMA1TXIRQ_OUT, Paths => (0 => (CPMDMA1LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLRSTENGINEACK, GlitchData => DMA2LLRSTENGINEACK_GlitchData, OutSignalName => "DMA2LLRSTENGINEACK", OutTemp => DMA2LLRSTENGINEACK_OUT, Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLRXDSTRDYN, GlitchData => DMA2LLRXDSTRDYN_GlitchData, OutSignalName => "DMA2LLRXDSTRDYN", OutTemp => DMA2LLRXDSTRDYN_OUT, Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(0), GlitchData => DMA2LLTXD0_GlitchData, OutSignalName => "DMA2LLTXD(0)", OutTemp => DMA2LLTXD_OUT(0), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(1), GlitchData => DMA2LLTXD1_GlitchData, OutSignalName => "DMA2LLTXD(1)", OutTemp => DMA2LLTXD_OUT(1), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(2), GlitchData => DMA2LLTXD2_GlitchData, OutSignalName => "DMA2LLTXD(2)", OutTemp => DMA2LLTXD_OUT(2), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(3), GlitchData => DMA2LLTXD3_GlitchData, OutSignalName => "DMA2LLTXD(3)", OutTemp => DMA2LLTXD_OUT(3), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(4), GlitchData => DMA2LLTXD4_GlitchData, OutSignalName => "DMA2LLTXD(4)", OutTemp => DMA2LLTXD_OUT(4), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(5), GlitchData => DMA2LLTXD5_GlitchData, OutSignalName => "DMA2LLTXD(5)", OutTemp => DMA2LLTXD_OUT(5), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(6), GlitchData => DMA2LLTXD6_GlitchData, OutSignalName => "DMA2LLTXD(6)", OutTemp => DMA2LLTXD_OUT(6), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(7), GlitchData => DMA2LLTXD7_GlitchData, OutSignalName => "DMA2LLTXD(7)", OutTemp => DMA2LLTXD_OUT(7), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(8), GlitchData => DMA2LLTXD8_GlitchData, OutSignalName => "DMA2LLTXD(8)", OutTemp => DMA2LLTXD_OUT(8), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(9), GlitchData => DMA2LLTXD9_GlitchData, OutSignalName => "DMA2LLTXD(9)", OutTemp => DMA2LLTXD_OUT(9), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(10), GlitchData => DMA2LLTXD10_GlitchData, OutSignalName => "DMA2LLTXD(10)", OutTemp => DMA2LLTXD_OUT(10), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(11), GlitchData => DMA2LLTXD11_GlitchData, OutSignalName => "DMA2LLTXD(11)", OutTemp => DMA2LLTXD_OUT(11), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(12), GlitchData => DMA2LLTXD12_GlitchData, OutSignalName => "DMA2LLTXD(12)", OutTemp => DMA2LLTXD_OUT(12), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(13), GlitchData => DMA2LLTXD13_GlitchData, OutSignalName => "DMA2LLTXD(13)", OutTemp => DMA2LLTXD_OUT(13), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(14), GlitchData => DMA2LLTXD14_GlitchData, OutSignalName => "DMA2LLTXD(14)", OutTemp => DMA2LLTXD_OUT(14), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(15), GlitchData => DMA2LLTXD15_GlitchData, OutSignalName => "DMA2LLTXD(15)", OutTemp => DMA2LLTXD_OUT(15), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(16), GlitchData => DMA2LLTXD16_GlitchData, OutSignalName => "DMA2LLTXD(16)", OutTemp => DMA2LLTXD_OUT(16), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(17), GlitchData => DMA2LLTXD17_GlitchData, OutSignalName => "DMA2LLTXD(17)", OutTemp => DMA2LLTXD_OUT(17), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(18), GlitchData => DMA2LLTXD18_GlitchData, OutSignalName => "DMA2LLTXD(18)", OutTemp => DMA2LLTXD_OUT(18), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(19), GlitchData => DMA2LLTXD19_GlitchData, OutSignalName => "DMA2LLTXD(19)", OutTemp => DMA2LLTXD_OUT(19), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(20), GlitchData => DMA2LLTXD20_GlitchData, OutSignalName => "DMA2LLTXD(20)", OutTemp => DMA2LLTXD_OUT(20), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(21), GlitchData => DMA2LLTXD21_GlitchData, OutSignalName => "DMA2LLTXD(21)", OutTemp => DMA2LLTXD_OUT(21), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(22), GlitchData => DMA2LLTXD22_GlitchData, OutSignalName => "DMA2LLTXD(22)", OutTemp => DMA2LLTXD_OUT(22), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(23), GlitchData => DMA2LLTXD23_GlitchData, OutSignalName => "DMA2LLTXD(23)", OutTemp => DMA2LLTXD_OUT(23), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(24), GlitchData => DMA2LLTXD24_GlitchData, OutSignalName => "DMA2LLTXD(24)", OutTemp => DMA2LLTXD_OUT(24), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(25), GlitchData => DMA2LLTXD25_GlitchData, OutSignalName => "DMA2LLTXD(25)", OutTemp => DMA2LLTXD_OUT(25), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(26), GlitchData => DMA2LLTXD26_GlitchData, OutSignalName => "DMA2LLTXD(26)", OutTemp => DMA2LLTXD_OUT(26), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(27), GlitchData => DMA2LLTXD27_GlitchData, OutSignalName => "DMA2LLTXD(27)", OutTemp => DMA2LLTXD_OUT(27), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(28), GlitchData => DMA2LLTXD28_GlitchData, OutSignalName => "DMA2LLTXD(28)", OutTemp => DMA2LLTXD_OUT(28), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(29), GlitchData => DMA2LLTXD29_GlitchData, OutSignalName => "DMA2LLTXD(29)", OutTemp => DMA2LLTXD_OUT(29), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(30), GlitchData => DMA2LLTXD30_GlitchData, OutSignalName => "DMA2LLTXD(30)", OutTemp => DMA2LLTXD_OUT(30), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXD(31), GlitchData => DMA2LLTXD31_GlitchData, OutSignalName => "DMA2LLTXD(31)", OutTemp => DMA2LLTXD_OUT(31), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXEOFN, GlitchData => DMA2LLTXEOFN_GlitchData, OutSignalName => "DMA2LLTXEOFN", OutTemp => DMA2LLTXEOFN_OUT, Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXEOPN, GlitchData => DMA2LLTXEOPN_GlitchData, OutSignalName => "DMA2LLTXEOPN", OutTemp => DMA2LLTXEOPN_OUT, Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXREM(0), GlitchData => DMA2LLTXREM0_GlitchData, OutSignalName => "DMA2LLTXREM(0)", OutTemp => DMA2LLTXREM_OUT(0), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXREM(1), GlitchData => DMA2LLTXREM1_GlitchData, OutSignalName => "DMA2LLTXREM(1)", OutTemp => DMA2LLTXREM_OUT(1), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXREM(2), GlitchData => DMA2LLTXREM2_GlitchData, OutSignalName => "DMA2LLTXREM(2)", OutTemp => DMA2LLTXREM_OUT(2), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXREM(3), GlitchData => DMA2LLTXREM3_GlitchData, OutSignalName => "DMA2LLTXREM(3)", OutTemp => DMA2LLTXREM_OUT(3), Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXSOFN, GlitchData => DMA2LLTXSOFN_GlitchData, OutSignalName => "DMA2LLTXSOFN", OutTemp => DMA2LLTXSOFN_OUT, Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXSOPN, GlitchData => DMA2LLTXSOPN_GlitchData, OutSignalName => "DMA2LLTXSOPN", OutTemp => DMA2LLTXSOPN_OUT, Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2LLTXSRCRDYN, GlitchData => DMA2LLTXSRCRDYN_GlitchData, OutSignalName => "DMA2LLTXSRCRDYN", OutTemp => DMA2LLTXSRCRDYN_OUT, Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2RXIRQ, GlitchData => DMA2RXIRQ_GlitchData, OutSignalName => "DMA2RXIRQ", OutTemp => DMA2RXIRQ_OUT, Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA2TXIRQ, GlitchData => DMA2TXIRQ_GlitchData, OutSignalName => "DMA2TXIRQ", OutTemp => DMA2TXIRQ_OUT, Paths => (0 => (CPMDMA2LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLRSTENGINEACK, GlitchData => DMA3LLRSTENGINEACK_GlitchData, OutSignalName => "DMA3LLRSTENGINEACK", OutTemp => DMA3LLRSTENGINEACK_OUT, Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLRXDSTRDYN, GlitchData => DMA3LLRXDSTRDYN_GlitchData, OutSignalName => "DMA3LLRXDSTRDYN", OutTemp => DMA3LLRXDSTRDYN_OUT, Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(0), GlitchData => DMA3LLTXD0_GlitchData, OutSignalName => "DMA3LLTXD(0)", OutTemp => DMA3LLTXD_OUT(0), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(1), GlitchData => DMA3LLTXD1_GlitchData, OutSignalName => "DMA3LLTXD(1)", OutTemp => DMA3LLTXD_OUT(1), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(2), GlitchData => DMA3LLTXD2_GlitchData, OutSignalName => "DMA3LLTXD(2)", OutTemp => DMA3LLTXD_OUT(2), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(3), GlitchData => DMA3LLTXD3_GlitchData, OutSignalName => "DMA3LLTXD(3)", OutTemp => DMA3LLTXD_OUT(3), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(4), GlitchData => DMA3LLTXD4_GlitchData, OutSignalName => "DMA3LLTXD(4)", OutTemp => DMA3LLTXD_OUT(4), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(5), GlitchData => DMA3LLTXD5_GlitchData, OutSignalName => "DMA3LLTXD(5)", OutTemp => DMA3LLTXD_OUT(5), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(6), GlitchData => DMA3LLTXD6_GlitchData, OutSignalName => "DMA3LLTXD(6)", OutTemp => DMA3LLTXD_OUT(6), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(7), GlitchData => DMA3LLTXD7_GlitchData, OutSignalName => "DMA3LLTXD(7)", OutTemp => DMA3LLTXD_OUT(7), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(8), GlitchData => DMA3LLTXD8_GlitchData, OutSignalName => "DMA3LLTXD(8)", OutTemp => DMA3LLTXD_OUT(8), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(9), GlitchData => DMA3LLTXD9_GlitchData, OutSignalName => "DMA3LLTXD(9)", OutTemp => DMA3LLTXD_OUT(9), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(10), GlitchData => DMA3LLTXD10_GlitchData, OutSignalName => "DMA3LLTXD(10)", OutTemp => DMA3LLTXD_OUT(10), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(11), GlitchData => DMA3LLTXD11_GlitchData, OutSignalName => "DMA3LLTXD(11)", OutTemp => DMA3LLTXD_OUT(11), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(12), GlitchData => DMA3LLTXD12_GlitchData, OutSignalName => "DMA3LLTXD(12)", OutTemp => DMA3LLTXD_OUT(12), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(13), GlitchData => DMA3LLTXD13_GlitchData, OutSignalName => "DMA3LLTXD(13)", OutTemp => DMA3LLTXD_OUT(13), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(14), GlitchData => DMA3LLTXD14_GlitchData, OutSignalName => "DMA3LLTXD(14)", OutTemp => DMA3LLTXD_OUT(14), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(15), GlitchData => DMA3LLTXD15_GlitchData, OutSignalName => "DMA3LLTXD(15)", OutTemp => DMA3LLTXD_OUT(15), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(16), GlitchData => DMA3LLTXD16_GlitchData, OutSignalName => "DMA3LLTXD(16)", OutTemp => DMA3LLTXD_OUT(16), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(17), GlitchData => DMA3LLTXD17_GlitchData, OutSignalName => "DMA3LLTXD(17)", OutTemp => DMA3LLTXD_OUT(17), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(18), GlitchData => DMA3LLTXD18_GlitchData, OutSignalName => "DMA3LLTXD(18)", OutTemp => DMA3LLTXD_OUT(18), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(19), GlitchData => DMA3LLTXD19_GlitchData, OutSignalName => "DMA3LLTXD(19)", OutTemp => DMA3LLTXD_OUT(19), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(20), GlitchData => DMA3LLTXD20_GlitchData, OutSignalName => "DMA3LLTXD(20)", OutTemp => DMA3LLTXD_OUT(20), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(21), GlitchData => DMA3LLTXD21_GlitchData, OutSignalName => "DMA3LLTXD(21)", OutTemp => DMA3LLTXD_OUT(21), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(22), GlitchData => DMA3LLTXD22_GlitchData, OutSignalName => "DMA3LLTXD(22)", OutTemp => DMA3LLTXD_OUT(22), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(23), GlitchData => DMA3LLTXD23_GlitchData, OutSignalName => "DMA3LLTXD(23)", OutTemp => DMA3LLTXD_OUT(23), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(24), GlitchData => DMA3LLTXD24_GlitchData, OutSignalName => "DMA3LLTXD(24)", OutTemp => DMA3LLTXD_OUT(24), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(25), GlitchData => DMA3LLTXD25_GlitchData, OutSignalName => "DMA3LLTXD(25)", OutTemp => DMA3LLTXD_OUT(25), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(26), GlitchData => DMA3LLTXD26_GlitchData, OutSignalName => "DMA3LLTXD(26)", OutTemp => DMA3LLTXD_OUT(26), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(27), GlitchData => DMA3LLTXD27_GlitchData, OutSignalName => "DMA3LLTXD(27)", OutTemp => DMA3LLTXD_OUT(27), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(28), GlitchData => DMA3LLTXD28_GlitchData, OutSignalName => "DMA3LLTXD(28)", OutTemp => DMA3LLTXD_OUT(28), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(29), GlitchData => DMA3LLTXD29_GlitchData, OutSignalName => "DMA3LLTXD(29)", OutTemp => DMA3LLTXD_OUT(29), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(30), GlitchData => DMA3LLTXD30_GlitchData, OutSignalName => "DMA3LLTXD(30)", OutTemp => DMA3LLTXD_OUT(30), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXD(31), GlitchData => DMA3LLTXD31_GlitchData, OutSignalName => "DMA3LLTXD(31)", OutTemp => DMA3LLTXD_OUT(31), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXEOFN, GlitchData => DMA3LLTXEOFN_GlitchData, OutSignalName => "DMA3LLTXEOFN", OutTemp => DMA3LLTXEOFN_OUT, Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXEOPN, GlitchData => DMA3LLTXEOPN_GlitchData, OutSignalName => "DMA3LLTXEOPN", OutTemp => DMA3LLTXEOPN_OUT, Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXREM(0), GlitchData => DMA3LLTXREM0_GlitchData, OutSignalName => "DMA3LLTXREM(0)", OutTemp => DMA3LLTXREM_OUT(0), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXREM(1), GlitchData => DMA3LLTXREM1_GlitchData, OutSignalName => "DMA3LLTXREM(1)", OutTemp => DMA3LLTXREM_OUT(1), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXREM(2), GlitchData => DMA3LLTXREM2_GlitchData, OutSignalName => "DMA3LLTXREM(2)", OutTemp => DMA3LLTXREM_OUT(2), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXREM(3), GlitchData => DMA3LLTXREM3_GlitchData, OutSignalName => "DMA3LLTXREM(3)", OutTemp => DMA3LLTXREM_OUT(3), Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXSOFN, GlitchData => DMA3LLTXSOFN_GlitchData, OutSignalName => "DMA3LLTXSOFN", OutTemp => DMA3LLTXSOFN_OUT, Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXSOPN, GlitchData => DMA3LLTXSOPN_GlitchData, OutSignalName => "DMA3LLTXSOPN", OutTemp => DMA3LLTXSOPN_OUT, Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3LLTXSRCRDYN, GlitchData => DMA3LLTXSRCRDYN_GlitchData, OutSignalName => "DMA3LLTXSRCRDYN", OutTemp => DMA3LLTXSRCRDYN_OUT, Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3RXIRQ, GlitchData => DMA3RXIRQ_GlitchData, OutSignalName => "DMA3RXIRQ", OutTemp => DMA3RXIRQ_OUT, Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => DMA3TXIRQ, GlitchData => DMA3TXIRQ_GlitchData, OutSignalName => "DMA3TXIRQ", OutTemp => DMA3TXIRQ_OUT, Paths => (0 => (CPMDMA3LLCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRABUS(0), GlitchData => PPCDMDCRABUS0_GlitchData, OutSignalName => "PPCDMDCRABUS(0)", OutTemp => PPCDMDCRABUS_OUT(0), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRABUS(1), GlitchData => PPCDMDCRABUS1_GlitchData, OutSignalName => "PPCDMDCRABUS(1)", OutTemp => PPCDMDCRABUS_OUT(1), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRABUS(2), GlitchData => PPCDMDCRABUS2_GlitchData, OutSignalName => "PPCDMDCRABUS(2)", OutTemp => PPCDMDCRABUS_OUT(2), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRABUS(3), GlitchData => PPCDMDCRABUS3_GlitchData, OutSignalName => "PPCDMDCRABUS(3)", OutTemp => PPCDMDCRABUS_OUT(3), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRABUS(4), GlitchData => PPCDMDCRABUS4_GlitchData, OutSignalName => "PPCDMDCRABUS(4)", OutTemp => PPCDMDCRABUS_OUT(4), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRABUS(5), GlitchData => PPCDMDCRABUS5_GlitchData, OutSignalName => "PPCDMDCRABUS(5)", OutTemp => PPCDMDCRABUS_OUT(5), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRABUS(6), GlitchData => PPCDMDCRABUS6_GlitchData, OutSignalName => "PPCDMDCRABUS(6)", OutTemp => PPCDMDCRABUS_OUT(6), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRABUS(7), GlitchData => PPCDMDCRABUS7_GlitchData, OutSignalName => "PPCDMDCRABUS(7)", OutTemp => PPCDMDCRABUS_OUT(7), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRABUS(8), GlitchData => PPCDMDCRABUS8_GlitchData, OutSignalName => "PPCDMDCRABUS(8)", OutTemp => PPCDMDCRABUS_OUT(8), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRABUS(9), GlitchData => PPCDMDCRABUS9_GlitchData, OutSignalName => "PPCDMDCRABUS(9)", OutTemp => PPCDMDCRABUS_OUT(9), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(0), GlitchData => PPCDMDCRDBUSOUT0_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(0)", OutTemp => PPCDMDCRDBUSOUT_OUT(0), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(1), GlitchData => PPCDMDCRDBUSOUT1_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(1)", OutTemp => PPCDMDCRDBUSOUT_OUT(1), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(2), GlitchData => PPCDMDCRDBUSOUT2_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(2)", OutTemp => PPCDMDCRDBUSOUT_OUT(2), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(3), GlitchData => PPCDMDCRDBUSOUT3_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(3)", OutTemp => PPCDMDCRDBUSOUT_OUT(3), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(4), GlitchData => PPCDMDCRDBUSOUT4_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(4)", OutTemp => PPCDMDCRDBUSOUT_OUT(4), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(5), GlitchData => PPCDMDCRDBUSOUT5_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(5)", OutTemp => PPCDMDCRDBUSOUT_OUT(5), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(6), GlitchData => PPCDMDCRDBUSOUT6_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(6)", OutTemp => PPCDMDCRDBUSOUT_OUT(6), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(7), GlitchData => PPCDMDCRDBUSOUT7_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(7)", OutTemp => PPCDMDCRDBUSOUT_OUT(7), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(8), GlitchData => PPCDMDCRDBUSOUT8_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(8)", OutTemp => PPCDMDCRDBUSOUT_OUT(8), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(9), GlitchData => PPCDMDCRDBUSOUT9_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(9)", OutTemp => PPCDMDCRDBUSOUT_OUT(9), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(10), GlitchData => PPCDMDCRDBUSOUT10_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(10)", OutTemp => PPCDMDCRDBUSOUT_OUT(10), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(11), GlitchData => PPCDMDCRDBUSOUT11_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(11)", OutTemp => PPCDMDCRDBUSOUT_OUT(11), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(12), GlitchData => PPCDMDCRDBUSOUT12_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(12)", OutTemp => PPCDMDCRDBUSOUT_OUT(12), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(13), GlitchData => PPCDMDCRDBUSOUT13_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(13)", OutTemp => PPCDMDCRDBUSOUT_OUT(13), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(14), GlitchData => PPCDMDCRDBUSOUT14_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(14)", OutTemp => PPCDMDCRDBUSOUT_OUT(14), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(15), GlitchData => PPCDMDCRDBUSOUT15_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(15)", OutTemp => PPCDMDCRDBUSOUT_OUT(15), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(16), GlitchData => PPCDMDCRDBUSOUT16_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(16)", OutTemp => PPCDMDCRDBUSOUT_OUT(16), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(17), GlitchData => PPCDMDCRDBUSOUT17_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(17)", OutTemp => PPCDMDCRDBUSOUT_OUT(17), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(18), GlitchData => PPCDMDCRDBUSOUT18_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(18)", OutTemp => PPCDMDCRDBUSOUT_OUT(18), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(19), GlitchData => PPCDMDCRDBUSOUT19_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(19)", OutTemp => PPCDMDCRDBUSOUT_OUT(19), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(20), GlitchData => PPCDMDCRDBUSOUT20_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(20)", OutTemp => PPCDMDCRDBUSOUT_OUT(20), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(21), GlitchData => PPCDMDCRDBUSOUT21_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(21)", OutTemp => PPCDMDCRDBUSOUT_OUT(21), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(22), GlitchData => PPCDMDCRDBUSOUT22_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(22)", OutTemp => PPCDMDCRDBUSOUT_OUT(22), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(23), GlitchData => PPCDMDCRDBUSOUT23_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(23)", OutTemp => PPCDMDCRDBUSOUT_OUT(23), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(24), GlitchData => PPCDMDCRDBUSOUT24_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(24)", OutTemp => PPCDMDCRDBUSOUT_OUT(24), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(25), GlitchData => PPCDMDCRDBUSOUT25_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(25)", OutTemp => PPCDMDCRDBUSOUT_OUT(25), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(26), GlitchData => PPCDMDCRDBUSOUT26_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(26)", OutTemp => PPCDMDCRDBUSOUT_OUT(26), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(27), GlitchData => PPCDMDCRDBUSOUT27_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(27)", OutTemp => PPCDMDCRDBUSOUT_OUT(27), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(28), GlitchData => PPCDMDCRDBUSOUT28_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(28)", OutTemp => PPCDMDCRDBUSOUT_OUT(28), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(29), GlitchData => PPCDMDCRDBUSOUT29_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(29)", OutTemp => PPCDMDCRDBUSOUT_OUT(29), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(30), GlitchData => PPCDMDCRDBUSOUT30_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(30)", OutTemp => PPCDMDCRDBUSOUT_OUT(30), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRDBUSOUT(31), GlitchData => PPCDMDCRDBUSOUT31_GlitchData, OutSignalName => "PPCDMDCRDBUSOUT(31)", OutTemp => PPCDMDCRDBUSOUT_OUT(31), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRREAD, GlitchData => PPCDMDCRREAD_GlitchData, OutSignalName => "PPCDMDCRREAD", OutTemp => PPCDMDCRREAD_OUT, Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRUABUS(20), GlitchData => PPCDMDCRUABUS20_GlitchData, OutSignalName => "PPCDMDCRUABUS(20)", OutTemp => PPCDMDCRUABUS_OUT(20), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRUABUS(21), GlitchData => PPCDMDCRUABUS21_GlitchData, OutSignalName => "PPCDMDCRUABUS(21)", OutTemp => PPCDMDCRUABUS_OUT(21), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDMDCRWRITE, GlitchData => PPCDMDCRWRITE_GlitchData, OutSignalName => "PPCDMDCRWRITE", OutTemp => PPCDMDCRWRITE_OUT, Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABORT, GlitchData => PPCMPLBABORT_GlitchData, OutSignalName => "PPCMPLBABORT", OutTemp => PPCMPLBABORT_OUT, Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(0), GlitchData => PPCMPLBABUS0_GlitchData, OutSignalName => "PPCMPLBABUS(0)", OutTemp => PPCMPLBABUS_OUT(0), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(1), GlitchData => PPCMPLBABUS1_GlitchData, OutSignalName => "PPCMPLBABUS(1)", OutTemp => PPCMPLBABUS_OUT(1), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(2), GlitchData => PPCMPLBABUS2_GlitchData, OutSignalName => "PPCMPLBABUS(2)", OutTemp => PPCMPLBABUS_OUT(2), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(3), GlitchData => PPCMPLBABUS3_GlitchData, OutSignalName => "PPCMPLBABUS(3)", OutTemp => PPCMPLBABUS_OUT(3), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(4), GlitchData => PPCMPLBABUS4_GlitchData, OutSignalName => "PPCMPLBABUS(4)", OutTemp => PPCMPLBABUS_OUT(4), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(5), GlitchData => PPCMPLBABUS5_GlitchData, OutSignalName => "PPCMPLBABUS(5)", OutTemp => PPCMPLBABUS_OUT(5), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(6), GlitchData => PPCMPLBABUS6_GlitchData, OutSignalName => "PPCMPLBABUS(6)", OutTemp => PPCMPLBABUS_OUT(6), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(7), GlitchData => PPCMPLBABUS7_GlitchData, OutSignalName => "PPCMPLBABUS(7)", OutTemp => PPCMPLBABUS_OUT(7), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(8), GlitchData => PPCMPLBABUS8_GlitchData, OutSignalName => "PPCMPLBABUS(8)", OutTemp => PPCMPLBABUS_OUT(8), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(9), GlitchData => PPCMPLBABUS9_GlitchData, OutSignalName => "PPCMPLBABUS(9)", OutTemp => PPCMPLBABUS_OUT(9), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(10), GlitchData => PPCMPLBABUS10_GlitchData, OutSignalName => "PPCMPLBABUS(10)", OutTemp => PPCMPLBABUS_OUT(10), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(11), GlitchData => PPCMPLBABUS11_GlitchData, OutSignalName => "PPCMPLBABUS(11)", OutTemp => PPCMPLBABUS_OUT(11), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(12), GlitchData => PPCMPLBABUS12_GlitchData, OutSignalName => "PPCMPLBABUS(12)", OutTemp => PPCMPLBABUS_OUT(12), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(13), GlitchData => PPCMPLBABUS13_GlitchData, OutSignalName => "PPCMPLBABUS(13)", OutTemp => PPCMPLBABUS_OUT(13), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(14), GlitchData => PPCMPLBABUS14_GlitchData, OutSignalName => "PPCMPLBABUS(14)", OutTemp => PPCMPLBABUS_OUT(14), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(15), GlitchData => PPCMPLBABUS15_GlitchData, OutSignalName => "PPCMPLBABUS(15)", OutTemp => PPCMPLBABUS_OUT(15), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(16), GlitchData => PPCMPLBABUS16_GlitchData, OutSignalName => "PPCMPLBABUS(16)", OutTemp => PPCMPLBABUS_OUT(16), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(17), GlitchData => PPCMPLBABUS17_GlitchData, OutSignalName => "PPCMPLBABUS(17)", OutTemp => PPCMPLBABUS_OUT(17), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(18), GlitchData => PPCMPLBABUS18_GlitchData, OutSignalName => "PPCMPLBABUS(18)", OutTemp => PPCMPLBABUS_OUT(18), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(19), GlitchData => PPCMPLBABUS19_GlitchData, OutSignalName => "PPCMPLBABUS(19)", OutTemp => PPCMPLBABUS_OUT(19), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(20), GlitchData => PPCMPLBABUS20_GlitchData, OutSignalName => "PPCMPLBABUS(20)", OutTemp => PPCMPLBABUS_OUT(20), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(21), GlitchData => PPCMPLBABUS21_GlitchData, OutSignalName => "PPCMPLBABUS(21)", OutTemp => PPCMPLBABUS_OUT(21), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(22), GlitchData => PPCMPLBABUS22_GlitchData, OutSignalName => "PPCMPLBABUS(22)", OutTemp => PPCMPLBABUS_OUT(22), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(23), GlitchData => PPCMPLBABUS23_GlitchData, OutSignalName => "PPCMPLBABUS(23)", OutTemp => PPCMPLBABUS_OUT(23), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(24), GlitchData => PPCMPLBABUS24_GlitchData, OutSignalName => "PPCMPLBABUS(24)", OutTemp => PPCMPLBABUS_OUT(24), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(25), GlitchData => PPCMPLBABUS25_GlitchData, OutSignalName => "PPCMPLBABUS(25)", OutTemp => PPCMPLBABUS_OUT(25), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(26), GlitchData => PPCMPLBABUS26_GlitchData, OutSignalName => "PPCMPLBABUS(26)", OutTemp => PPCMPLBABUS_OUT(26), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(27), GlitchData => PPCMPLBABUS27_GlitchData, OutSignalName => "PPCMPLBABUS(27)", OutTemp => PPCMPLBABUS_OUT(27), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(28), GlitchData => PPCMPLBABUS28_GlitchData, OutSignalName => "PPCMPLBABUS(28)", OutTemp => PPCMPLBABUS_OUT(28), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(29), GlitchData => PPCMPLBABUS29_GlitchData, OutSignalName => "PPCMPLBABUS(29)", OutTemp => PPCMPLBABUS_OUT(29), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(30), GlitchData => PPCMPLBABUS30_GlitchData, OutSignalName => "PPCMPLBABUS(30)", OutTemp => PPCMPLBABUS_OUT(30), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBABUS(31), GlitchData => PPCMPLBABUS31_GlitchData, OutSignalName => "PPCMPLBABUS(31)", OutTemp => PPCMPLBABUS_OUT(31), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(0), GlitchData => PPCMPLBBE0_GlitchData, OutSignalName => "PPCMPLBBE(0)", OutTemp => PPCMPLBBE_OUT(0), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(1), GlitchData => PPCMPLBBE1_GlitchData, OutSignalName => "PPCMPLBBE(1)", OutTemp => PPCMPLBBE_OUT(1), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(2), GlitchData => PPCMPLBBE2_GlitchData, OutSignalName => "PPCMPLBBE(2)", OutTemp => PPCMPLBBE_OUT(2), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(3), GlitchData => PPCMPLBBE3_GlitchData, OutSignalName => "PPCMPLBBE(3)", OutTemp => PPCMPLBBE_OUT(3), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(4), GlitchData => PPCMPLBBE4_GlitchData, OutSignalName => "PPCMPLBBE(4)", OutTemp => PPCMPLBBE_OUT(4), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(5), GlitchData => PPCMPLBBE5_GlitchData, OutSignalName => "PPCMPLBBE(5)", OutTemp => PPCMPLBBE_OUT(5), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(6), GlitchData => PPCMPLBBE6_GlitchData, OutSignalName => "PPCMPLBBE(6)", OutTemp => PPCMPLBBE_OUT(6), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(7), GlitchData => PPCMPLBBE7_GlitchData, OutSignalName => "PPCMPLBBE(7)", OutTemp => PPCMPLBBE_OUT(7), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(8), GlitchData => PPCMPLBBE8_GlitchData, OutSignalName => "PPCMPLBBE(8)", OutTemp => PPCMPLBBE_OUT(8), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(9), GlitchData => PPCMPLBBE9_GlitchData, OutSignalName => "PPCMPLBBE(9)", OutTemp => PPCMPLBBE_OUT(9), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(10), GlitchData => PPCMPLBBE10_GlitchData, OutSignalName => "PPCMPLBBE(10)", OutTemp => PPCMPLBBE_OUT(10), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(11), GlitchData => PPCMPLBBE11_GlitchData, OutSignalName => "PPCMPLBBE(11)", OutTemp => PPCMPLBBE_OUT(11), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(12), GlitchData => PPCMPLBBE12_GlitchData, OutSignalName => "PPCMPLBBE(12)", OutTemp => PPCMPLBBE_OUT(12), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(13), GlitchData => PPCMPLBBE13_GlitchData, OutSignalName => "PPCMPLBBE(13)", OutTemp => PPCMPLBBE_OUT(13), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(14), GlitchData => PPCMPLBBE14_GlitchData, OutSignalName => "PPCMPLBBE(14)", OutTemp => PPCMPLBBE_OUT(14), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBE(15), GlitchData => PPCMPLBBE15_GlitchData, OutSignalName => "PPCMPLBBE(15)", OutTemp => PPCMPLBBE_OUT(15), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBBUSLOCK, GlitchData => PPCMPLBBUSLOCK_GlitchData, OutSignalName => "PPCMPLBBUSLOCK", OutTemp => PPCMPLBBUSLOCK_OUT, Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBLOCKERR, GlitchData => PPCMPLBLOCKERR_GlitchData, OutSignalName => "PPCMPLBLOCKERR", OutTemp => PPCMPLBLOCKERR_OUT, Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBPRIORITY(0), GlitchData => PPCMPLBPRIORITY0_GlitchData, OutSignalName => "PPCMPLBPRIORITY(0)", OutTemp => PPCMPLBPRIORITY_OUT(0), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBPRIORITY(1), GlitchData => PPCMPLBPRIORITY1_GlitchData, OutSignalName => "PPCMPLBPRIORITY(1)", OutTemp => PPCMPLBPRIORITY_OUT(1), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBRDBURST, GlitchData => PPCMPLBRDBURST_GlitchData, OutSignalName => "PPCMPLBRDBURST", OutTemp => PPCMPLBRDBURST_OUT, Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBREQUEST, GlitchData => PPCMPLBREQUEST_GlitchData, OutSignalName => "PPCMPLBREQUEST", OutTemp => PPCMPLBREQUEST_OUT, Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBRNW, GlitchData => PPCMPLBRNW_GlitchData, OutSignalName => "PPCMPLBRNW", OutTemp => PPCMPLBRNW_OUT, Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBSIZE(0), GlitchData => PPCMPLBSIZE0_GlitchData, OutSignalName => "PPCMPLBSIZE(0)", OutTemp => PPCMPLBSIZE_OUT(0), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBSIZE(1), GlitchData => PPCMPLBSIZE1_GlitchData, OutSignalName => "PPCMPLBSIZE(1)", OutTemp => PPCMPLBSIZE_OUT(1), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBSIZE(2), GlitchData => PPCMPLBSIZE2_GlitchData, OutSignalName => "PPCMPLBSIZE(2)", OutTemp => PPCMPLBSIZE_OUT(2), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBSIZE(3), GlitchData => PPCMPLBSIZE3_GlitchData, OutSignalName => "PPCMPLBSIZE(3)", OutTemp => PPCMPLBSIZE_OUT(3), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(0), GlitchData => PPCMPLBTATTRIBUTE0_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(0)", OutTemp => PPCMPLBTATTRIBUTE_OUT(0), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(1), GlitchData => PPCMPLBTATTRIBUTE1_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(1)", OutTemp => PPCMPLBTATTRIBUTE_OUT(1), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(2), GlitchData => PPCMPLBTATTRIBUTE2_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(2)", OutTemp => PPCMPLBTATTRIBUTE_OUT(2), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(3), GlitchData => PPCMPLBTATTRIBUTE3_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(3)", OutTemp => PPCMPLBTATTRIBUTE_OUT(3), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(4), GlitchData => PPCMPLBTATTRIBUTE4_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(4)", OutTemp => PPCMPLBTATTRIBUTE_OUT(4), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(5), GlitchData => PPCMPLBTATTRIBUTE5_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(5)", OutTemp => PPCMPLBTATTRIBUTE_OUT(5), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(6), GlitchData => PPCMPLBTATTRIBUTE6_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(6)", OutTemp => PPCMPLBTATTRIBUTE_OUT(6), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(7), GlitchData => PPCMPLBTATTRIBUTE7_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(7)", OutTemp => PPCMPLBTATTRIBUTE_OUT(7), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(8), GlitchData => PPCMPLBTATTRIBUTE8_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(8)", OutTemp => PPCMPLBTATTRIBUTE_OUT(8), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(9), GlitchData => PPCMPLBTATTRIBUTE9_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(9)", OutTemp => PPCMPLBTATTRIBUTE_OUT(9), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(10), GlitchData => PPCMPLBTATTRIBUTE10_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(10)", OutTemp => PPCMPLBTATTRIBUTE_OUT(10), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(11), GlitchData => PPCMPLBTATTRIBUTE11_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(11)", OutTemp => PPCMPLBTATTRIBUTE_OUT(11), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(12), GlitchData => PPCMPLBTATTRIBUTE12_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(12)", OutTemp => PPCMPLBTATTRIBUTE_OUT(12), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(13), GlitchData => PPCMPLBTATTRIBUTE13_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(13)", OutTemp => PPCMPLBTATTRIBUTE_OUT(13), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(14), GlitchData => PPCMPLBTATTRIBUTE14_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(14)", OutTemp => PPCMPLBTATTRIBUTE_OUT(14), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTATTRIBUTE(15), GlitchData => PPCMPLBTATTRIBUTE15_GlitchData, OutSignalName => "PPCMPLBTATTRIBUTE(15)", OutTemp => PPCMPLBTATTRIBUTE_OUT(15), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTYPE(0), GlitchData => PPCMPLBTYPE0_GlitchData, OutSignalName => "PPCMPLBTYPE(0)", OutTemp => PPCMPLBTYPE_OUT(0), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTYPE(1), GlitchData => PPCMPLBTYPE1_GlitchData, OutSignalName => "PPCMPLBTYPE(1)", OutTemp => PPCMPLBTYPE_OUT(1), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBTYPE(2), GlitchData => PPCMPLBTYPE2_GlitchData, OutSignalName => "PPCMPLBTYPE(2)", OutTemp => PPCMPLBTYPE_OUT(2), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBUABUS(28), GlitchData => PPCMPLBUABUS28_GlitchData, OutSignalName => "PPCMPLBUABUS(28)", OutTemp => PPCMPLBUABUS_OUT(28), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBUABUS(29), GlitchData => PPCMPLBUABUS29_GlitchData, OutSignalName => "PPCMPLBUABUS(29)", OutTemp => PPCMPLBUABUS_OUT(29), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBUABUS(30), GlitchData => PPCMPLBUABUS30_GlitchData, OutSignalName => "PPCMPLBUABUS(30)", OutTemp => PPCMPLBUABUS_OUT(30), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBUABUS(31), GlitchData => PPCMPLBUABUS31_GlitchData, OutSignalName => "PPCMPLBUABUS(31)", OutTemp => PPCMPLBUABUS_OUT(31), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRBURST, GlitchData => PPCMPLBWRBURST_GlitchData, OutSignalName => "PPCMPLBWRBURST", OutTemp => PPCMPLBWRBURST_OUT, Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(0), GlitchData => PPCMPLBWRDBUS0_GlitchData, OutSignalName => "PPCMPLBWRDBUS(0)", OutTemp => PPCMPLBWRDBUS_OUT(0), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(1), GlitchData => PPCMPLBWRDBUS1_GlitchData, OutSignalName => "PPCMPLBWRDBUS(1)", OutTemp => PPCMPLBWRDBUS_OUT(1), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(2), GlitchData => PPCMPLBWRDBUS2_GlitchData, OutSignalName => "PPCMPLBWRDBUS(2)", OutTemp => PPCMPLBWRDBUS_OUT(2), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(3), GlitchData => PPCMPLBWRDBUS3_GlitchData, OutSignalName => "PPCMPLBWRDBUS(3)", OutTemp => PPCMPLBWRDBUS_OUT(3), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(4), GlitchData => PPCMPLBWRDBUS4_GlitchData, OutSignalName => "PPCMPLBWRDBUS(4)", OutTemp => PPCMPLBWRDBUS_OUT(4), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(5), GlitchData => PPCMPLBWRDBUS5_GlitchData, OutSignalName => "PPCMPLBWRDBUS(5)", OutTemp => PPCMPLBWRDBUS_OUT(5), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(6), GlitchData => PPCMPLBWRDBUS6_GlitchData, OutSignalName => "PPCMPLBWRDBUS(6)", OutTemp => PPCMPLBWRDBUS_OUT(6), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(7), GlitchData => PPCMPLBWRDBUS7_GlitchData, OutSignalName => "PPCMPLBWRDBUS(7)", OutTemp => PPCMPLBWRDBUS_OUT(7), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(8), GlitchData => PPCMPLBWRDBUS8_GlitchData, OutSignalName => "PPCMPLBWRDBUS(8)", OutTemp => PPCMPLBWRDBUS_OUT(8), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(9), GlitchData => PPCMPLBWRDBUS9_GlitchData, OutSignalName => "PPCMPLBWRDBUS(9)", OutTemp => PPCMPLBWRDBUS_OUT(9), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(10), GlitchData => PPCMPLBWRDBUS10_GlitchData, OutSignalName => "PPCMPLBWRDBUS(10)", OutTemp => PPCMPLBWRDBUS_OUT(10), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(11), GlitchData => PPCMPLBWRDBUS11_GlitchData, OutSignalName => "PPCMPLBWRDBUS(11)", OutTemp => PPCMPLBWRDBUS_OUT(11), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(12), GlitchData => PPCMPLBWRDBUS12_GlitchData, OutSignalName => "PPCMPLBWRDBUS(12)", OutTemp => PPCMPLBWRDBUS_OUT(12), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(13), GlitchData => PPCMPLBWRDBUS13_GlitchData, OutSignalName => "PPCMPLBWRDBUS(13)", OutTemp => PPCMPLBWRDBUS_OUT(13), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(14), GlitchData => PPCMPLBWRDBUS14_GlitchData, OutSignalName => "PPCMPLBWRDBUS(14)", OutTemp => PPCMPLBWRDBUS_OUT(14), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(15), GlitchData => PPCMPLBWRDBUS15_GlitchData, OutSignalName => "PPCMPLBWRDBUS(15)", OutTemp => PPCMPLBWRDBUS_OUT(15), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(16), GlitchData => PPCMPLBWRDBUS16_GlitchData, OutSignalName => "PPCMPLBWRDBUS(16)", OutTemp => PPCMPLBWRDBUS_OUT(16), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(17), GlitchData => PPCMPLBWRDBUS17_GlitchData, OutSignalName => "PPCMPLBWRDBUS(17)", OutTemp => PPCMPLBWRDBUS_OUT(17), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(18), GlitchData => PPCMPLBWRDBUS18_GlitchData, OutSignalName => "PPCMPLBWRDBUS(18)", OutTemp => PPCMPLBWRDBUS_OUT(18), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(19), GlitchData => PPCMPLBWRDBUS19_GlitchData, OutSignalName => "PPCMPLBWRDBUS(19)", OutTemp => PPCMPLBWRDBUS_OUT(19), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(20), GlitchData => PPCMPLBWRDBUS20_GlitchData, OutSignalName => "PPCMPLBWRDBUS(20)", OutTemp => PPCMPLBWRDBUS_OUT(20), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(21), GlitchData => PPCMPLBWRDBUS21_GlitchData, OutSignalName => "PPCMPLBWRDBUS(21)", OutTemp => PPCMPLBWRDBUS_OUT(21), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(22), GlitchData => PPCMPLBWRDBUS22_GlitchData, OutSignalName => "PPCMPLBWRDBUS(22)", OutTemp => PPCMPLBWRDBUS_OUT(22), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(23), GlitchData => PPCMPLBWRDBUS23_GlitchData, OutSignalName => "PPCMPLBWRDBUS(23)", OutTemp => PPCMPLBWRDBUS_OUT(23), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(24), GlitchData => PPCMPLBWRDBUS24_GlitchData, OutSignalName => "PPCMPLBWRDBUS(24)", OutTemp => PPCMPLBWRDBUS_OUT(24), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(25), GlitchData => PPCMPLBWRDBUS25_GlitchData, OutSignalName => "PPCMPLBWRDBUS(25)", OutTemp => PPCMPLBWRDBUS_OUT(25), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(26), GlitchData => PPCMPLBWRDBUS26_GlitchData, OutSignalName => "PPCMPLBWRDBUS(26)", OutTemp => PPCMPLBWRDBUS_OUT(26), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(27), GlitchData => PPCMPLBWRDBUS27_GlitchData, OutSignalName => "PPCMPLBWRDBUS(27)", OutTemp => PPCMPLBWRDBUS_OUT(27), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(28), GlitchData => PPCMPLBWRDBUS28_GlitchData, OutSignalName => "PPCMPLBWRDBUS(28)", OutTemp => PPCMPLBWRDBUS_OUT(28), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(29), GlitchData => PPCMPLBWRDBUS29_GlitchData, OutSignalName => "PPCMPLBWRDBUS(29)", OutTemp => PPCMPLBWRDBUS_OUT(29), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(30), GlitchData => PPCMPLBWRDBUS30_GlitchData, OutSignalName => "PPCMPLBWRDBUS(30)", OutTemp => PPCMPLBWRDBUS_OUT(30), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(31), GlitchData => PPCMPLBWRDBUS31_GlitchData, OutSignalName => "PPCMPLBWRDBUS(31)", OutTemp => PPCMPLBWRDBUS_OUT(31), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(32), GlitchData => PPCMPLBWRDBUS32_GlitchData, OutSignalName => "PPCMPLBWRDBUS(32)", OutTemp => PPCMPLBWRDBUS_OUT(32), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(33), GlitchData => PPCMPLBWRDBUS33_GlitchData, OutSignalName => "PPCMPLBWRDBUS(33)", OutTemp => PPCMPLBWRDBUS_OUT(33), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(34), GlitchData => PPCMPLBWRDBUS34_GlitchData, OutSignalName => "PPCMPLBWRDBUS(34)", OutTemp => PPCMPLBWRDBUS_OUT(34), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(35), GlitchData => PPCMPLBWRDBUS35_GlitchData, OutSignalName => "PPCMPLBWRDBUS(35)", OutTemp => PPCMPLBWRDBUS_OUT(35), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(36), GlitchData => PPCMPLBWRDBUS36_GlitchData, OutSignalName => "PPCMPLBWRDBUS(36)", OutTemp => PPCMPLBWRDBUS_OUT(36), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(37), GlitchData => PPCMPLBWRDBUS37_GlitchData, OutSignalName => "PPCMPLBWRDBUS(37)", OutTemp => PPCMPLBWRDBUS_OUT(37), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(38), GlitchData => PPCMPLBWRDBUS38_GlitchData, OutSignalName => "PPCMPLBWRDBUS(38)", OutTemp => PPCMPLBWRDBUS_OUT(38), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(39), GlitchData => PPCMPLBWRDBUS39_GlitchData, OutSignalName => "PPCMPLBWRDBUS(39)", OutTemp => PPCMPLBWRDBUS_OUT(39), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(40), GlitchData => PPCMPLBWRDBUS40_GlitchData, OutSignalName => "PPCMPLBWRDBUS(40)", OutTemp => PPCMPLBWRDBUS_OUT(40), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(41), GlitchData => PPCMPLBWRDBUS41_GlitchData, OutSignalName => "PPCMPLBWRDBUS(41)", OutTemp => PPCMPLBWRDBUS_OUT(41), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(42), GlitchData => PPCMPLBWRDBUS42_GlitchData, OutSignalName => "PPCMPLBWRDBUS(42)", OutTemp => PPCMPLBWRDBUS_OUT(42), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(43), GlitchData => PPCMPLBWRDBUS43_GlitchData, OutSignalName => "PPCMPLBWRDBUS(43)", OutTemp => PPCMPLBWRDBUS_OUT(43), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(44), GlitchData => PPCMPLBWRDBUS44_GlitchData, OutSignalName => "PPCMPLBWRDBUS(44)", OutTemp => PPCMPLBWRDBUS_OUT(44), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(45), GlitchData => PPCMPLBWRDBUS45_GlitchData, OutSignalName => "PPCMPLBWRDBUS(45)", OutTemp => PPCMPLBWRDBUS_OUT(45), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(46), GlitchData => PPCMPLBWRDBUS46_GlitchData, OutSignalName => "PPCMPLBWRDBUS(46)", OutTemp => PPCMPLBWRDBUS_OUT(46), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(47), GlitchData => PPCMPLBWRDBUS47_GlitchData, OutSignalName => "PPCMPLBWRDBUS(47)", OutTemp => PPCMPLBWRDBUS_OUT(47), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(48), GlitchData => PPCMPLBWRDBUS48_GlitchData, OutSignalName => "PPCMPLBWRDBUS(48)", OutTemp => PPCMPLBWRDBUS_OUT(48), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(49), GlitchData => PPCMPLBWRDBUS49_GlitchData, OutSignalName => "PPCMPLBWRDBUS(49)", OutTemp => PPCMPLBWRDBUS_OUT(49), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(50), GlitchData => PPCMPLBWRDBUS50_GlitchData, OutSignalName => "PPCMPLBWRDBUS(50)", OutTemp => PPCMPLBWRDBUS_OUT(50), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(51), GlitchData => PPCMPLBWRDBUS51_GlitchData, OutSignalName => "PPCMPLBWRDBUS(51)", OutTemp => PPCMPLBWRDBUS_OUT(51), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(52), GlitchData => PPCMPLBWRDBUS52_GlitchData, OutSignalName => "PPCMPLBWRDBUS(52)", OutTemp => PPCMPLBWRDBUS_OUT(52), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(53), GlitchData => PPCMPLBWRDBUS53_GlitchData, OutSignalName => "PPCMPLBWRDBUS(53)", OutTemp => PPCMPLBWRDBUS_OUT(53), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(54), GlitchData => PPCMPLBWRDBUS54_GlitchData, OutSignalName => "PPCMPLBWRDBUS(54)", OutTemp => PPCMPLBWRDBUS_OUT(54), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(55), GlitchData => PPCMPLBWRDBUS55_GlitchData, OutSignalName => "PPCMPLBWRDBUS(55)", OutTemp => PPCMPLBWRDBUS_OUT(55), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(56), GlitchData => PPCMPLBWRDBUS56_GlitchData, OutSignalName => "PPCMPLBWRDBUS(56)", OutTemp => PPCMPLBWRDBUS_OUT(56), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(57), GlitchData => PPCMPLBWRDBUS57_GlitchData, OutSignalName => "PPCMPLBWRDBUS(57)", OutTemp => PPCMPLBWRDBUS_OUT(57), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(58), GlitchData => PPCMPLBWRDBUS58_GlitchData, OutSignalName => "PPCMPLBWRDBUS(58)", OutTemp => PPCMPLBWRDBUS_OUT(58), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(59), GlitchData => PPCMPLBWRDBUS59_GlitchData, OutSignalName => "PPCMPLBWRDBUS(59)", OutTemp => PPCMPLBWRDBUS_OUT(59), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(60), GlitchData => PPCMPLBWRDBUS60_GlitchData, OutSignalName => "PPCMPLBWRDBUS(60)", OutTemp => PPCMPLBWRDBUS_OUT(60), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(61), GlitchData => PPCMPLBWRDBUS61_GlitchData, OutSignalName => "PPCMPLBWRDBUS(61)", OutTemp => PPCMPLBWRDBUS_OUT(61), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(62), GlitchData => PPCMPLBWRDBUS62_GlitchData, OutSignalName => "PPCMPLBWRDBUS(62)", OutTemp => PPCMPLBWRDBUS_OUT(62), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(63), GlitchData => PPCMPLBWRDBUS63_GlitchData, OutSignalName => "PPCMPLBWRDBUS(63)", OutTemp => PPCMPLBWRDBUS_OUT(63), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(64), GlitchData => PPCMPLBWRDBUS64_GlitchData, OutSignalName => "PPCMPLBWRDBUS(64)", OutTemp => PPCMPLBWRDBUS_OUT(64), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(65), GlitchData => PPCMPLBWRDBUS65_GlitchData, OutSignalName => "PPCMPLBWRDBUS(65)", OutTemp => PPCMPLBWRDBUS_OUT(65), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(66), GlitchData => PPCMPLBWRDBUS66_GlitchData, OutSignalName => "PPCMPLBWRDBUS(66)", OutTemp => PPCMPLBWRDBUS_OUT(66), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(67), GlitchData => PPCMPLBWRDBUS67_GlitchData, OutSignalName => "PPCMPLBWRDBUS(67)", OutTemp => PPCMPLBWRDBUS_OUT(67), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(68), GlitchData => PPCMPLBWRDBUS68_GlitchData, OutSignalName => "PPCMPLBWRDBUS(68)", OutTemp => PPCMPLBWRDBUS_OUT(68), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(69), GlitchData => PPCMPLBWRDBUS69_GlitchData, OutSignalName => "PPCMPLBWRDBUS(69)", OutTemp => PPCMPLBWRDBUS_OUT(69), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(70), GlitchData => PPCMPLBWRDBUS70_GlitchData, OutSignalName => "PPCMPLBWRDBUS(70)", OutTemp => PPCMPLBWRDBUS_OUT(70), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(71), GlitchData => PPCMPLBWRDBUS71_GlitchData, OutSignalName => "PPCMPLBWRDBUS(71)", OutTemp => PPCMPLBWRDBUS_OUT(71), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(72), GlitchData => PPCMPLBWRDBUS72_GlitchData, OutSignalName => "PPCMPLBWRDBUS(72)", OutTemp => PPCMPLBWRDBUS_OUT(72), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(73), GlitchData => PPCMPLBWRDBUS73_GlitchData, OutSignalName => "PPCMPLBWRDBUS(73)", OutTemp => PPCMPLBWRDBUS_OUT(73), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(74), GlitchData => PPCMPLBWRDBUS74_GlitchData, OutSignalName => "PPCMPLBWRDBUS(74)", OutTemp => PPCMPLBWRDBUS_OUT(74), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(75), GlitchData => PPCMPLBWRDBUS75_GlitchData, OutSignalName => "PPCMPLBWRDBUS(75)", OutTemp => PPCMPLBWRDBUS_OUT(75), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(76), GlitchData => PPCMPLBWRDBUS76_GlitchData, OutSignalName => "PPCMPLBWRDBUS(76)", OutTemp => PPCMPLBWRDBUS_OUT(76), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(77), GlitchData => PPCMPLBWRDBUS77_GlitchData, OutSignalName => "PPCMPLBWRDBUS(77)", OutTemp => PPCMPLBWRDBUS_OUT(77), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(78), GlitchData => PPCMPLBWRDBUS78_GlitchData, OutSignalName => "PPCMPLBWRDBUS(78)", OutTemp => PPCMPLBWRDBUS_OUT(78), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(79), GlitchData => PPCMPLBWRDBUS79_GlitchData, OutSignalName => "PPCMPLBWRDBUS(79)", OutTemp => PPCMPLBWRDBUS_OUT(79), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(80), GlitchData => PPCMPLBWRDBUS80_GlitchData, OutSignalName => "PPCMPLBWRDBUS(80)", OutTemp => PPCMPLBWRDBUS_OUT(80), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(81), GlitchData => PPCMPLBWRDBUS81_GlitchData, OutSignalName => "PPCMPLBWRDBUS(81)", OutTemp => PPCMPLBWRDBUS_OUT(81), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(82), GlitchData => PPCMPLBWRDBUS82_GlitchData, OutSignalName => "PPCMPLBWRDBUS(82)", OutTemp => PPCMPLBWRDBUS_OUT(82), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(83), GlitchData => PPCMPLBWRDBUS83_GlitchData, OutSignalName => "PPCMPLBWRDBUS(83)", OutTemp => PPCMPLBWRDBUS_OUT(83), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(84), GlitchData => PPCMPLBWRDBUS84_GlitchData, OutSignalName => "PPCMPLBWRDBUS(84)", OutTemp => PPCMPLBWRDBUS_OUT(84), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(85), GlitchData => PPCMPLBWRDBUS85_GlitchData, OutSignalName => "PPCMPLBWRDBUS(85)", OutTemp => PPCMPLBWRDBUS_OUT(85), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(86), GlitchData => PPCMPLBWRDBUS86_GlitchData, OutSignalName => "PPCMPLBWRDBUS(86)", OutTemp => PPCMPLBWRDBUS_OUT(86), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(87), GlitchData => PPCMPLBWRDBUS87_GlitchData, OutSignalName => "PPCMPLBWRDBUS(87)", OutTemp => PPCMPLBWRDBUS_OUT(87), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(88), GlitchData => PPCMPLBWRDBUS88_GlitchData, OutSignalName => "PPCMPLBWRDBUS(88)", OutTemp => PPCMPLBWRDBUS_OUT(88), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(89), GlitchData => PPCMPLBWRDBUS89_GlitchData, OutSignalName => "PPCMPLBWRDBUS(89)", OutTemp => PPCMPLBWRDBUS_OUT(89), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(90), GlitchData => PPCMPLBWRDBUS90_GlitchData, OutSignalName => "PPCMPLBWRDBUS(90)", OutTemp => PPCMPLBWRDBUS_OUT(90), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(91), GlitchData => PPCMPLBWRDBUS91_GlitchData, OutSignalName => "PPCMPLBWRDBUS(91)", OutTemp => PPCMPLBWRDBUS_OUT(91), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(92), GlitchData => PPCMPLBWRDBUS92_GlitchData, OutSignalName => "PPCMPLBWRDBUS(92)", OutTemp => PPCMPLBWRDBUS_OUT(92), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(93), GlitchData => PPCMPLBWRDBUS93_GlitchData, OutSignalName => "PPCMPLBWRDBUS(93)", OutTemp => PPCMPLBWRDBUS_OUT(93), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(94), GlitchData => PPCMPLBWRDBUS94_GlitchData, OutSignalName => "PPCMPLBWRDBUS(94)", OutTemp => PPCMPLBWRDBUS_OUT(94), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(95), GlitchData => PPCMPLBWRDBUS95_GlitchData, OutSignalName => "PPCMPLBWRDBUS(95)", OutTemp => PPCMPLBWRDBUS_OUT(95), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(96), GlitchData => PPCMPLBWRDBUS96_GlitchData, OutSignalName => "PPCMPLBWRDBUS(96)", OutTemp => PPCMPLBWRDBUS_OUT(96), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(97), GlitchData => PPCMPLBWRDBUS97_GlitchData, OutSignalName => "PPCMPLBWRDBUS(97)", OutTemp => PPCMPLBWRDBUS_OUT(97), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(98), GlitchData => PPCMPLBWRDBUS98_GlitchData, OutSignalName => "PPCMPLBWRDBUS(98)", OutTemp => PPCMPLBWRDBUS_OUT(98), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(99), GlitchData => PPCMPLBWRDBUS99_GlitchData, OutSignalName => "PPCMPLBWRDBUS(99)", OutTemp => PPCMPLBWRDBUS_OUT(99), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(100), GlitchData => PPCMPLBWRDBUS100_GlitchData, OutSignalName => "PPCMPLBWRDBUS(100)", OutTemp => PPCMPLBWRDBUS_OUT(100), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(101), GlitchData => PPCMPLBWRDBUS101_GlitchData, OutSignalName => "PPCMPLBWRDBUS(101)", OutTemp => PPCMPLBWRDBUS_OUT(101), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(102), GlitchData => PPCMPLBWRDBUS102_GlitchData, OutSignalName => "PPCMPLBWRDBUS(102)", OutTemp => PPCMPLBWRDBUS_OUT(102), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(103), GlitchData => PPCMPLBWRDBUS103_GlitchData, OutSignalName => "PPCMPLBWRDBUS(103)", OutTemp => PPCMPLBWRDBUS_OUT(103), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(104), GlitchData => PPCMPLBWRDBUS104_GlitchData, OutSignalName => "PPCMPLBWRDBUS(104)", OutTemp => PPCMPLBWRDBUS_OUT(104), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(105), GlitchData => PPCMPLBWRDBUS105_GlitchData, OutSignalName => "PPCMPLBWRDBUS(105)", OutTemp => PPCMPLBWRDBUS_OUT(105), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(106), GlitchData => PPCMPLBWRDBUS106_GlitchData, OutSignalName => "PPCMPLBWRDBUS(106)", OutTemp => PPCMPLBWRDBUS_OUT(106), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(107), GlitchData => PPCMPLBWRDBUS107_GlitchData, OutSignalName => "PPCMPLBWRDBUS(107)", OutTemp => PPCMPLBWRDBUS_OUT(107), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(108), GlitchData => PPCMPLBWRDBUS108_GlitchData, OutSignalName => "PPCMPLBWRDBUS(108)", OutTemp => PPCMPLBWRDBUS_OUT(108), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(109), GlitchData => PPCMPLBWRDBUS109_GlitchData, OutSignalName => "PPCMPLBWRDBUS(109)", OutTemp => PPCMPLBWRDBUS_OUT(109), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(110), GlitchData => PPCMPLBWRDBUS110_GlitchData, OutSignalName => "PPCMPLBWRDBUS(110)", OutTemp => PPCMPLBWRDBUS_OUT(110), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(111), GlitchData => PPCMPLBWRDBUS111_GlitchData, OutSignalName => "PPCMPLBWRDBUS(111)", OutTemp => PPCMPLBWRDBUS_OUT(111), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(112), GlitchData => PPCMPLBWRDBUS112_GlitchData, OutSignalName => "PPCMPLBWRDBUS(112)", OutTemp => PPCMPLBWRDBUS_OUT(112), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(113), GlitchData => PPCMPLBWRDBUS113_GlitchData, OutSignalName => "PPCMPLBWRDBUS(113)", OutTemp => PPCMPLBWRDBUS_OUT(113), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(114), GlitchData => PPCMPLBWRDBUS114_GlitchData, OutSignalName => "PPCMPLBWRDBUS(114)", OutTemp => PPCMPLBWRDBUS_OUT(114), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(115), GlitchData => PPCMPLBWRDBUS115_GlitchData, OutSignalName => "PPCMPLBWRDBUS(115)", OutTemp => PPCMPLBWRDBUS_OUT(115), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(116), GlitchData => PPCMPLBWRDBUS116_GlitchData, OutSignalName => "PPCMPLBWRDBUS(116)", OutTemp => PPCMPLBWRDBUS_OUT(116), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(117), GlitchData => PPCMPLBWRDBUS117_GlitchData, OutSignalName => "PPCMPLBWRDBUS(117)", OutTemp => PPCMPLBWRDBUS_OUT(117), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(118), GlitchData => PPCMPLBWRDBUS118_GlitchData, OutSignalName => "PPCMPLBWRDBUS(118)", OutTemp => PPCMPLBWRDBUS_OUT(118), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(119), GlitchData => PPCMPLBWRDBUS119_GlitchData, OutSignalName => "PPCMPLBWRDBUS(119)", OutTemp => PPCMPLBWRDBUS_OUT(119), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(120), GlitchData => PPCMPLBWRDBUS120_GlitchData, OutSignalName => "PPCMPLBWRDBUS(120)", OutTemp => PPCMPLBWRDBUS_OUT(120), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(121), GlitchData => PPCMPLBWRDBUS121_GlitchData, OutSignalName => "PPCMPLBWRDBUS(121)", OutTemp => PPCMPLBWRDBUS_OUT(121), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(122), GlitchData => PPCMPLBWRDBUS122_GlitchData, OutSignalName => "PPCMPLBWRDBUS(122)", OutTemp => PPCMPLBWRDBUS_OUT(122), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(123), GlitchData => PPCMPLBWRDBUS123_GlitchData, OutSignalName => "PPCMPLBWRDBUS(123)", OutTemp => PPCMPLBWRDBUS_OUT(123), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(124), GlitchData => PPCMPLBWRDBUS124_GlitchData, OutSignalName => "PPCMPLBWRDBUS(124)", OutTemp => PPCMPLBWRDBUS_OUT(124), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(125), GlitchData => PPCMPLBWRDBUS125_GlitchData, OutSignalName => "PPCMPLBWRDBUS(125)", OutTemp => PPCMPLBWRDBUS_OUT(125), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(126), GlitchData => PPCMPLBWRDBUS126_GlitchData, OutSignalName => "PPCMPLBWRDBUS(126)", OutTemp => PPCMPLBWRDBUS_OUT(126), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCMPLBWRDBUS(127), GlitchData => PPCMPLBWRDBUS127_GlitchData, OutSignalName => "PPCMPLBWRDBUS(127)", OutTemp => PPCMPLBWRDBUS_OUT(127), Paths => (0 => (CPMPPCMPLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBADDRACK, GlitchData => PPCS0PLBADDRACK_GlitchData, OutSignalName => "PPCS0PLBADDRACK", OutTemp => PPCS0PLBADDRACK_OUT, Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMBUSY(0), GlitchData => PPCS0PLBMBUSY0_GlitchData, OutSignalName => "PPCS0PLBMBUSY(0)", OutTemp => PPCS0PLBMBUSY_OUT(0), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMBUSY(1), GlitchData => PPCS0PLBMBUSY1_GlitchData, OutSignalName => "PPCS0PLBMBUSY(1)", OutTemp => PPCS0PLBMBUSY_OUT(1), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMBUSY(2), GlitchData => PPCS0PLBMBUSY2_GlitchData, OutSignalName => "PPCS0PLBMBUSY(2)", OutTemp => PPCS0PLBMBUSY_OUT(2), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMBUSY(3), GlitchData => PPCS0PLBMBUSY3_GlitchData, OutSignalName => "PPCS0PLBMBUSY(3)", OutTemp => PPCS0PLBMBUSY_OUT(3), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMIRQ(0), GlitchData => PPCS0PLBMIRQ0_GlitchData, OutSignalName => "PPCS0PLBMIRQ(0)", OutTemp => PPCS0PLBMIRQ_OUT(0), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMIRQ(1), GlitchData => PPCS0PLBMIRQ1_GlitchData, OutSignalName => "PPCS0PLBMIRQ(1)", OutTemp => PPCS0PLBMIRQ_OUT(1), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMIRQ(2), GlitchData => PPCS0PLBMIRQ2_GlitchData, OutSignalName => "PPCS0PLBMIRQ(2)", OutTemp => PPCS0PLBMIRQ_OUT(2), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMIRQ(3), GlitchData => PPCS0PLBMIRQ3_GlitchData, OutSignalName => "PPCS0PLBMIRQ(3)", OutTemp => PPCS0PLBMIRQ_OUT(3), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMRDERR(0), GlitchData => PPCS0PLBMRDERR0_GlitchData, OutSignalName => "PPCS0PLBMRDERR(0)", OutTemp => PPCS0PLBMRDERR_OUT(0), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMRDERR(1), GlitchData => PPCS0PLBMRDERR1_GlitchData, OutSignalName => "PPCS0PLBMRDERR(1)", OutTemp => PPCS0PLBMRDERR_OUT(1), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMRDERR(2), GlitchData => PPCS0PLBMRDERR2_GlitchData, OutSignalName => "PPCS0PLBMRDERR(2)", OutTemp => PPCS0PLBMRDERR_OUT(2), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMRDERR(3), GlitchData => PPCS0PLBMRDERR3_GlitchData, OutSignalName => "PPCS0PLBMRDERR(3)", OutTemp => PPCS0PLBMRDERR_OUT(3), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMWRERR(0), GlitchData => PPCS0PLBMWRERR0_GlitchData, OutSignalName => "PPCS0PLBMWRERR(0)", OutTemp => PPCS0PLBMWRERR_OUT(0), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMWRERR(1), GlitchData => PPCS0PLBMWRERR1_GlitchData, OutSignalName => "PPCS0PLBMWRERR(1)", OutTemp => PPCS0PLBMWRERR_OUT(1), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMWRERR(2), GlitchData => PPCS0PLBMWRERR2_GlitchData, OutSignalName => "PPCS0PLBMWRERR(2)", OutTemp => PPCS0PLBMWRERR_OUT(2), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBMWRERR(3), GlitchData => PPCS0PLBMWRERR3_GlitchData, OutSignalName => "PPCS0PLBMWRERR(3)", OutTemp => PPCS0PLBMWRERR_OUT(3), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDBTERM, GlitchData => PPCS0PLBRDBTERM_GlitchData, OutSignalName => "PPCS0PLBRDBTERM", OutTemp => PPCS0PLBRDBTERM_OUT, Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDCOMP, GlitchData => PPCS0PLBRDCOMP_GlitchData, OutSignalName => "PPCS0PLBRDCOMP", OutTemp => PPCS0PLBRDCOMP_OUT, Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDACK, GlitchData => PPCS0PLBRDDACK_GlitchData, OutSignalName => "PPCS0PLBRDDACK", OutTemp => PPCS0PLBRDDACK_OUT, Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(0), GlitchData => PPCS0PLBRDDBUS0_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(0)", OutTemp => PPCS0PLBRDDBUS_OUT(0), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(1), GlitchData => PPCS0PLBRDDBUS1_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(1)", OutTemp => PPCS0PLBRDDBUS_OUT(1), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(2), GlitchData => PPCS0PLBRDDBUS2_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(2)", OutTemp => PPCS0PLBRDDBUS_OUT(2), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(3), GlitchData => PPCS0PLBRDDBUS3_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(3)", OutTemp => PPCS0PLBRDDBUS_OUT(3), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(4), GlitchData => PPCS0PLBRDDBUS4_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(4)", OutTemp => PPCS0PLBRDDBUS_OUT(4), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(5), GlitchData => PPCS0PLBRDDBUS5_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(5)", OutTemp => PPCS0PLBRDDBUS_OUT(5), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(6), GlitchData => PPCS0PLBRDDBUS6_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(6)", OutTemp => PPCS0PLBRDDBUS_OUT(6), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(7), GlitchData => PPCS0PLBRDDBUS7_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(7)", OutTemp => PPCS0PLBRDDBUS_OUT(7), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(8), GlitchData => PPCS0PLBRDDBUS8_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(8)", OutTemp => PPCS0PLBRDDBUS_OUT(8), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(9), GlitchData => PPCS0PLBRDDBUS9_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(9)", OutTemp => PPCS0PLBRDDBUS_OUT(9), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(10), GlitchData => PPCS0PLBRDDBUS10_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(10)", OutTemp => PPCS0PLBRDDBUS_OUT(10), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(11), GlitchData => PPCS0PLBRDDBUS11_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(11)", OutTemp => PPCS0PLBRDDBUS_OUT(11), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(12), GlitchData => PPCS0PLBRDDBUS12_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(12)", OutTemp => PPCS0PLBRDDBUS_OUT(12), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(13), GlitchData => PPCS0PLBRDDBUS13_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(13)", OutTemp => PPCS0PLBRDDBUS_OUT(13), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(14), GlitchData => PPCS0PLBRDDBUS14_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(14)", OutTemp => PPCS0PLBRDDBUS_OUT(14), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(15), GlitchData => PPCS0PLBRDDBUS15_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(15)", OutTemp => PPCS0PLBRDDBUS_OUT(15), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(16), GlitchData => PPCS0PLBRDDBUS16_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(16)", OutTemp => PPCS0PLBRDDBUS_OUT(16), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(17), GlitchData => PPCS0PLBRDDBUS17_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(17)", OutTemp => PPCS0PLBRDDBUS_OUT(17), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(18), GlitchData => PPCS0PLBRDDBUS18_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(18)", OutTemp => PPCS0PLBRDDBUS_OUT(18), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(19), GlitchData => PPCS0PLBRDDBUS19_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(19)", OutTemp => PPCS0PLBRDDBUS_OUT(19), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(20), GlitchData => PPCS0PLBRDDBUS20_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(20)", OutTemp => PPCS0PLBRDDBUS_OUT(20), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(21), GlitchData => PPCS0PLBRDDBUS21_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(21)", OutTemp => PPCS0PLBRDDBUS_OUT(21), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(22), GlitchData => PPCS0PLBRDDBUS22_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(22)", OutTemp => PPCS0PLBRDDBUS_OUT(22), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(23), GlitchData => PPCS0PLBRDDBUS23_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(23)", OutTemp => PPCS0PLBRDDBUS_OUT(23), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(24), GlitchData => PPCS0PLBRDDBUS24_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(24)", OutTemp => PPCS0PLBRDDBUS_OUT(24), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(25), GlitchData => PPCS0PLBRDDBUS25_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(25)", OutTemp => PPCS0PLBRDDBUS_OUT(25), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(26), GlitchData => PPCS0PLBRDDBUS26_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(26)", OutTemp => PPCS0PLBRDDBUS_OUT(26), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(27), GlitchData => PPCS0PLBRDDBUS27_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(27)", OutTemp => PPCS0PLBRDDBUS_OUT(27), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(28), GlitchData => PPCS0PLBRDDBUS28_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(28)", OutTemp => PPCS0PLBRDDBUS_OUT(28), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(29), GlitchData => PPCS0PLBRDDBUS29_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(29)", OutTemp => PPCS0PLBRDDBUS_OUT(29), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(30), GlitchData => PPCS0PLBRDDBUS30_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(30)", OutTemp => PPCS0PLBRDDBUS_OUT(30), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(31), GlitchData => PPCS0PLBRDDBUS31_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(31)", OutTemp => PPCS0PLBRDDBUS_OUT(31), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(32), GlitchData => PPCS0PLBRDDBUS32_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(32)", OutTemp => PPCS0PLBRDDBUS_OUT(32), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(33), GlitchData => PPCS0PLBRDDBUS33_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(33)", OutTemp => PPCS0PLBRDDBUS_OUT(33), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(34), GlitchData => PPCS0PLBRDDBUS34_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(34)", OutTemp => PPCS0PLBRDDBUS_OUT(34), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(35), GlitchData => PPCS0PLBRDDBUS35_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(35)", OutTemp => PPCS0PLBRDDBUS_OUT(35), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(36), GlitchData => PPCS0PLBRDDBUS36_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(36)", OutTemp => PPCS0PLBRDDBUS_OUT(36), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(37), GlitchData => PPCS0PLBRDDBUS37_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(37)", OutTemp => PPCS0PLBRDDBUS_OUT(37), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(38), GlitchData => PPCS0PLBRDDBUS38_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(38)", OutTemp => PPCS0PLBRDDBUS_OUT(38), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(39), GlitchData => PPCS0PLBRDDBUS39_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(39)", OutTemp => PPCS0PLBRDDBUS_OUT(39), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(40), GlitchData => PPCS0PLBRDDBUS40_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(40)", OutTemp => PPCS0PLBRDDBUS_OUT(40), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(41), GlitchData => PPCS0PLBRDDBUS41_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(41)", OutTemp => PPCS0PLBRDDBUS_OUT(41), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(42), GlitchData => PPCS0PLBRDDBUS42_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(42)", OutTemp => PPCS0PLBRDDBUS_OUT(42), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(43), GlitchData => PPCS0PLBRDDBUS43_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(43)", OutTemp => PPCS0PLBRDDBUS_OUT(43), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(44), GlitchData => PPCS0PLBRDDBUS44_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(44)", OutTemp => PPCS0PLBRDDBUS_OUT(44), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(45), GlitchData => PPCS0PLBRDDBUS45_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(45)", OutTemp => PPCS0PLBRDDBUS_OUT(45), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(46), GlitchData => PPCS0PLBRDDBUS46_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(46)", OutTemp => PPCS0PLBRDDBUS_OUT(46), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(47), GlitchData => PPCS0PLBRDDBUS47_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(47)", OutTemp => PPCS0PLBRDDBUS_OUT(47), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(48), GlitchData => PPCS0PLBRDDBUS48_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(48)", OutTemp => PPCS0PLBRDDBUS_OUT(48), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(49), GlitchData => PPCS0PLBRDDBUS49_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(49)", OutTemp => PPCS0PLBRDDBUS_OUT(49), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(50), GlitchData => PPCS0PLBRDDBUS50_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(50)", OutTemp => PPCS0PLBRDDBUS_OUT(50), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(51), GlitchData => PPCS0PLBRDDBUS51_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(51)", OutTemp => PPCS0PLBRDDBUS_OUT(51), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(52), GlitchData => PPCS0PLBRDDBUS52_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(52)", OutTemp => PPCS0PLBRDDBUS_OUT(52), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(53), GlitchData => PPCS0PLBRDDBUS53_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(53)", OutTemp => PPCS0PLBRDDBUS_OUT(53), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(54), GlitchData => PPCS0PLBRDDBUS54_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(54)", OutTemp => PPCS0PLBRDDBUS_OUT(54), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(55), GlitchData => PPCS0PLBRDDBUS55_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(55)", OutTemp => PPCS0PLBRDDBUS_OUT(55), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(56), GlitchData => PPCS0PLBRDDBUS56_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(56)", OutTemp => PPCS0PLBRDDBUS_OUT(56), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(57), GlitchData => PPCS0PLBRDDBUS57_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(57)", OutTemp => PPCS0PLBRDDBUS_OUT(57), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(58), GlitchData => PPCS0PLBRDDBUS58_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(58)", OutTemp => PPCS0PLBRDDBUS_OUT(58), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(59), GlitchData => PPCS0PLBRDDBUS59_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(59)", OutTemp => PPCS0PLBRDDBUS_OUT(59), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(60), GlitchData => PPCS0PLBRDDBUS60_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(60)", OutTemp => PPCS0PLBRDDBUS_OUT(60), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(61), GlitchData => PPCS0PLBRDDBUS61_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(61)", OutTemp => PPCS0PLBRDDBUS_OUT(61), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(62), GlitchData => PPCS0PLBRDDBUS62_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(62)", OutTemp => PPCS0PLBRDDBUS_OUT(62), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(63), GlitchData => PPCS0PLBRDDBUS63_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(63)", OutTemp => PPCS0PLBRDDBUS_OUT(63), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(64), GlitchData => PPCS0PLBRDDBUS64_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(64)", OutTemp => PPCS0PLBRDDBUS_OUT(64), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(65), GlitchData => PPCS0PLBRDDBUS65_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(65)", OutTemp => PPCS0PLBRDDBUS_OUT(65), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(66), GlitchData => PPCS0PLBRDDBUS66_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(66)", OutTemp => PPCS0PLBRDDBUS_OUT(66), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(67), GlitchData => PPCS0PLBRDDBUS67_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(67)", OutTemp => PPCS0PLBRDDBUS_OUT(67), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(68), GlitchData => PPCS0PLBRDDBUS68_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(68)", OutTemp => PPCS0PLBRDDBUS_OUT(68), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(69), GlitchData => PPCS0PLBRDDBUS69_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(69)", OutTemp => PPCS0PLBRDDBUS_OUT(69), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(70), GlitchData => PPCS0PLBRDDBUS70_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(70)", OutTemp => PPCS0PLBRDDBUS_OUT(70), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(71), GlitchData => PPCS0PLBRDDBUS71_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(71)", OutTemp => PPCS0PLBRDDBUS_OUT(71), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(72), GlitchData => PPCS0PLBRDDBUS72_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(72)", OutTemp => PPCS0PLBRDDBUS_OUT(72), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(73), GlitchData => PPCS0PLBRDDBUS73_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(73)", OutTemp => PPCS0PLBRDDBUS_OUT(73), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(74), GlitchData => PPCS0PLBRDDBUS74_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(74)", OutTemp => PPCS0PLBRDDBUS_OUT(74), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(75), GlitchData => PPCS0PLBRDDBUS75_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(75)", OutTemp => PPCS0PLBRDDBUS_OUT(75), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(76), GlitchData => PPCS0PLBRDDBUS76_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(76)", OutTemp => PPCS0PLBRDDBUS_OUT(76), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(77), GlitchData => PPCS0PLBRDDBUS77_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(77)", OutTemp => PPCS0PLBRDDBUS_OUT(77), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(78), GlitchData => PPCS0PLBRDDBUS78_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(78)", OutTemp => PPCS0PLBRDDBUS_OUT(78), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(79), GlitchData => PPCS0PLBRDDBUS79_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(79)", OutTemp => PPCS0PLBRDDBUS_OUT(79), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(80), GlitchData => PPCS0PLBRDDBUS80_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(80)", OutTemp => PPCS0PLBRDDBUS_OUT(80), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(81), GlitchData => PPCS0PLBRDDBUS81_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(81)", OutTemp => PPCS0PLBRDDBUS_OUT(81), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(82), GlitchData => PPCS0PLBRDDBUS82_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(82)", OutTemp => PPCS0PLBRDDBUS_OUT(82), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(83), GlitchData => PPCS0PLBRDDBUS83_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(83)", OutTemp => PPCS0PLBRDDBUS_OUT(83), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(84), GlitchData => PPCS0PLBRDDBUS84_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(84)", OutTemp => PPCS0PLBRDDBUS_OUT(84), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(85), GlitchData => PPCS0PLBRDDBUS85_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(85)", OutTemp => PPCS0PLBRDDBUS_OUT(85), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(86), GlitchData => PPCS0PLBRDDBUS86_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(86)", OutTemp => PPCS0PLBRDDBUS_OUT(86), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(87), GlitchData => PPCS0PLBRDDBUS87_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(87)", OutTemp => PPCS0PLBRDDBUS_OUT(87), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(88), GlitchData => PPCS0PLBRDDBUS88_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(88)", OutTemp => PPCS0PLBRDDBUS_OUT(88), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(89), GlitchData => PPCS0PLBRDDBUS89_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(89)", OutTemp => PPCS0PLBRDDBUS_OUT(89), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(90), GlitchData => PPCS0PLBRDDBUS90_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(90)", OutTemp => PPCS0PLBRDDBUS_OUT(90), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(91), GlitchData => PPCS0PLBRDDBUS91_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(91)", OutTemp => PPCS0PLBRDDBUS_OUT(91), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(92), GlitchData => PPCS0PLBRDDBUS92_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(92)", OutTemp => PPCS0PLBRDDBUS_OUT(92), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(93), GlitchData => PPCS0PLBRDDBUS93_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(93)", OutTemp => PPCS0PLBRDDBUS_OUT(93), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(94), GlitchData => PPCS0PLBRDDBUS94_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(94)", OutTemp => PPCS0PLBRDDBUS_OUT(94), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(95), GlitchData => PPCS0PLBRDDBUS95_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(95)", OutTemp => PPCS0PLBRDDBUS_OUT(95), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(96), GlitchData => PPCS0PLBRDDBUS96_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(96)", OutTemp => PPCS0PLBRDDBUS_OUT(96), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(97), GlitchData => PPCS0PLBRDDBUS97_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(97)", OutTemp => PPCS0PLBRDDBUS_OUT(97), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(98), GlitchData => PPCS0PLBRDDBUS98_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(98)", OutTemp => PPCS0PLBRDDBUS_OUT(98), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(99), GlitchData => PPCS0PLBRDDBUS99_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(99)", OutTemp => PPCS0PLBRDDBUS_OUT(99), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(100), GlitchData => PPCS0PLBRDDBUS100_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(100)", OutTemp => PPCS0PLBRDDBUS_OUT(100), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(101), GlitchData => PPCS0PLBRDDBUS101_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(101)", OutTemp => PPCS0PLBRDDBUS_OUT(101), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(102), GlitchData => PPCS0PLBRDDBUS102_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(102)", OutTemp => PPCS0PLBRDDBUS_OUT(102), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(103), GlitchData => PPCS0PLBRDDBUS103_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(103)", OutTemp => PPCS0PLBRDDBUS_OUT(103), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(104), GlitchData => PPCS0PLBRDDBUS104_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(104)", OutTemp => PPCS0PLBRDDBUS_OUT(104), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(105), GlitchData => PPCS0PLBRDDBUS105_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(105)", OutTemp => PPCS0PLBRDDBUS_OUT(105), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(106), GlitchData => PPCS0PLBRDDBUS106_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(106)", OutTemp => PPCS0PLBRDDBUS_OUT(106), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(107), GlitchData => PPCS0PLBRDDBUS107_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(107)", OutTemp => PPCS0PLBRDDBUS_OUT(107), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(108), GlitchData => PPCS0PLBRDDBUS108_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(108)", OutTemp => PPCS0PLBRDDBUS_OUT(108), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(109), GlitchData => PPCS0PLBRDDBUS109_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(109)", OutTemp => PPCS0PLBRDDBUS_OUT(109), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(110), GlitchData => PPCS0PLBRDDBUS110_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(110)", OutTemp => PPCS0PLBRDDBUS_OUT(110), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(111), GlitchData => PPCS0PLBRDDBUS111_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(111)", OutTemp => PPCS0PLBRDDBUS_OUT(111), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(112), GlitchData => PPCS0PLBRDDBUS112_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(112)", OutTemp => PPCS0PLBRDDBUS_OUT(112), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(113), GlitchData => PPCS0PLBRDDBUS113_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(113)", OutTemp => PPCS0PLBRDDBUS_OUT(113), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(114), GlitchData => PPCS0PLBRDDBUS114_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(114)", OutTemp => PPCS0PLBRDDBUS_OUT(114), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(115), GlitchData => PPCS0PLBRDDBUS115_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(115)", OutTemp => PPCS0PLBRDDBUS_OUT(115), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(116), GlitchData => PPCS0PLBRDDBUS116_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(116)", OutTemp => PPCS0PLBRDDBUS_OUT(116), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(117), GlitchData => PPCS0PLBRDDBUS117_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(117)", OutTemp => PPCS0PLBRDDBUS_OUT(117), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(118), GlitchData => PPCS0PLBRDDBUS118_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(118)", OutTemp => PPCS0PLBRDDBUS_OUT(118), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(119), GlitchData => PPCS0PLBRDDBUS119_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(119)", OutTemp => PPCS0PLBRDDBUS_OUT(119), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(120), GlitchData => PPCS0PLBRDDBUS120_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(120)", OutTemp => PPCS0PLBRDDBUS_OUT(120), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(121), GlitchData => PPCS0PLBRDDBUS121_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(121)", OutTemp => PPCS0PLBRDDBUS_OUT(121), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(122), GlitchData => PPCS0PLBRDDBUS122_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(122)", OutTemp => PPCS0PLBRDDBUS_OUT(122), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(123), GlitchData => PPCS0PLBRDDBUS123_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(123)", OutTemp => PPCS0PLBRDDBUS_OUT(123), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(124), GlitchData => PPCS0PLBRDDBUS124_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(124)", OutTemp => PPCS0PLBRDDBUS_OUT(124), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(125), GlitchData => PPCS0PLBRDDBUS125_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(125)", OutTemp => PPCS0PLBRDDBUS_OUT(125), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(126), GlitchData => PPCS0PLBRDDBUS126_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(126)", OutTemp => PPCS0PLBRDDBUS_OUT(126), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDDBUS(127), GlitchData => PPCS0PLBRDDBUS127_GlitchData, OutSignalName => "PPCS0PLBRDDBUS(127)", OutTemp => PPCS0PLBRDDBUS_OUT(127), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDWDADDR(0), GlitchData => PPCS0PLBRDWDADDR0_GlitchData, OutSignalName => "PPCS0PLBRDWDADDR(0)", OutTemp => PPCS0PLBRDWDADDR_OUT(0), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDWDADDR(1), GlitchData => PPCS0PLBRDWDADDR1_GlitchData, OutSignalName => "PPCS0PLBRDWDADDR(1)", OutTemp => PPCS0PLBRDWDADDR_OUT(1), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDWDADDR(2), GlitchData => PPCS0PLBRDWDADDR2_GlitchData, OutSignalName => "PPCS0PLBRDWDADDR(2)", OutTemp => PPCS0PLBRDWDADDR_OUT(2), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBRDWDADDR(3), GlitchData => PPCS0PLBRDWDADDR3_GlitchData, OutSignalName => "PPCS0PLBRDWDADDR(3)", OutTemp => PPCS0PLBRDWDADDR_OUT(3), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBREARBITRATE, GlitchData => PPCS0PLBREARBITRATE_GlitchData, OutSignalName => "PPCS0PLBREARBITRATE", OutTemp => PPCS0PLBREARBITRATE_OUT, Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBSSIZE(0), GlitchData => PPCS0PLBSSIZE0_GlitchData, OutSignalName => "PPCS0PLBSSIZE(0)", OutTemp => PPCS0PLBSSIZE_OUT(0), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBSSIZE(1), GlitchData => PPCS0PLBSSIZE1_GlitchData, OutSignalName => "PPCS0PLBSSIZE(1)", OutTemp => PPCS0PLBSSIZE_OUT(1), Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBWAIT, GlitchData => PPCS0PLBWAIT_GlitchData, OutSignalName => "PPCS0PLBWAIT", OutTemp => PPCS0PLBWAIT_OUT, Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBWRBTERM, GlitchData => PPCS0PLBWRBTERM_GlitchData, OutSignalName => "PPCS0PLBWRBTERM", OutTemp => PPCS0PLBWRBTERM_OUT, Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBWRCOMP, GlitchData => PPCS0PLBWRCOMP_GlitchData, OutSignalName => "PPCS0PLBWRCOMP", OutTemp => PPCS0PLBWRCOMP_OUT, Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS0PLBWRDACK, GlitchData => PPCS0PLBWRDACK_GlitchData, OutSignalName => "PPCS0PLBWRDACK", OutTemp => PPCS0PLBWRDACK_OUT, Paths => (0 => (CPMPPCS0PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBADDRACK, GlitchData => PPCS1PLBADDRACK_GlitchData, OutSignalName => "PPCS1PLBADDRACK", OutTemp => PPCS1PLBADDRACK_OUT, Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMBUSY(0), GlitchData => PPCS1PLBMBUSY0_GlitchData, OutSignalName => "PPCS1PLBMBUSY(0)", OutTemp => PPCS1PLBMBUSY_OUT(0), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMBUSY(1), GlitchData => PPCS1PLBMBUSY1_GlitchData, OutSignalName => "PPCS1PLBMBUSY(1)", OutTemp => PPCS1PLBMBUSY_OUT(1), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMBUSY(2), GlitchData => PPCS1PLBMBUSY2_GlitchData, OutSignalName => "PPCS1PLBMBUSY(2)", OutTemp => PPCS1PLBMBUSY_OUT(2), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMBUSY(3), GlitchData => PPCS1PLBMBUSY3_GlitchData, OutSignalName => "PPCS1PLBMBUSY(3)", OutTemp => PPCS1PLBMBUSY_OUT(3), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMIRQ(0), GlitchData => PPCS1PLBMIRQ0_GlitchData, OutSignalName => "PPCS1PLBMIRQ(0)", OutTemp => PPCS1PLBMIRQ_OUT(0), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMIRQ(1), GlitchData => PPCS1PLBMIRQ1_GlitchData, OutSignalName => "PPCS1PLBMIRQ(1)", OutTemp => PPCS1PLBMIRQ_OUT(1), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMIRQ(2), GlitchData => PPCS1PLBMIRQ2_GlitchData, OutSignalName => "PPCS1PLBMIRQ(2)", OutTemp => PPCS1PLBMIRQ_OUT(2), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMIRQ(3), GlitchData => PPCS1PLBMIRQ3_GlitchData, OutSignalName => "PPCS1PLBMIRQ(3)", OutTemp => PPCS1PLBMIRQ_OUT(3), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMRDERR(0), GlitchData => PPCS1PLBMRDERR0_GlitchData, OutSignalName => "PPCS1PLBMRDERR(0)", OutTemp => PPCS1PLBMRDERR_OUT(0), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMRDERR(1), GlitchData => PPCS1PLBMRDERR1_GlitchData, OutSignalName => "PPCS1PLBMRDERR(1)", OutTemp => PPCS1PLBMRDERR_OUT(1), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMRDERR(2), GlitchData => PPCS1PLBMRDERR2_GlitchData, OutSignalName => "PPCS1PLBMRDERR(2)", OutTemp => PPCS1PLBMRDERR_OUT(2), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMRDERR(3), GlitchData => PPCS1PLBMRDERR3_GlitchData, OutSignalName => "PPCS1PLBMRDERR(3)", OutTemp => PPCS1PLBMRDERR_OUT(3), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMWRERR(0), GlitchData => PPCS1PLBMWRERR0_GlitchData, OutSignalName => "PPCS1PLBMWRERR(0)", OutTemp => PPCS1PLBMWRERR_OUT(0), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMWRERR(1), GlitchData => PPCS1PLBMWRERR1_GlitchData, OutSignalName => "PPCS1PLBMWRERR(1)", OutTemp => PPCS1PLBMWRERR_OUT(1), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMWRERR(2), GlitchData => PPCS1PLBMWRERR2_GlitchData, OutSignalName => "PPCS1PLBMWRERR(2)", OutTemp => PPCS1PLBMWRERR_OUT(2), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBMWRERR(3), GlitchData => PPCS1PLBMWRERR3_GlitchData, OutSignalName => "PPCS1PLBMWRERR(3)", OutTemp => PPCS1PLBMWRERR_OUT(3), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDBTERM, GlitchData => PPCS1PLBRDBTERM_GlitchData, OutSignalName => "PPCS1PLBRDBTERM", OutTemp => PPCS1PLBRDBTERM_OUT, Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDCOMP, GlitchData => PPCS1PLBRDCOMP_GlitchData, OutSignalName => "PPCS1PLBRDCOMP", OutTemp => PPCS1PLBRDCOMP_OUT, Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDACK, GlitchData => PPCS1PLBRDDACK_GlitchData, OutSignalName => "PPCS1PLBRDDACK", OutTemp => PPCS1PLBRDDACK_OUT, Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(0), GlitchData => PPCS1PLBRDDBUS0_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(0)", OutTemp => PPCS1PLBRDDBUS_OUT(0), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(1), GlitchData => PPCS1PLBRDDBUS1_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(1)", OutTemp => PPCS1PLBRDDBUS_OUT(1), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(2), GlitchData => PPCS1PLBRDDBUS2_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(2)", OutTemp => PPCS1PLBRDDBUS_OUT(2), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(3), GlitchData => PPCS1PLBRDDBUS3_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(3)", OutTemp => PPCS1PLBRDDBUS_OUT(3), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(4), GlitchData => PPCS1PLBRDDBUS4_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(4)", OutTemp => PPCS1PLBRDDBUS_OUT(4), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(5), GlitchData => PPCS1PLBRDDBUS5_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(5)", OutTemp => PPCS1PLBRDDBUS_OUT(5), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(6), GlitchData => PPCS1PLBRDDBUS6_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(6)", OutTemp => PPCS1PLBRDDBUS_OUT(6), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(7), GlitchData => PPCS1PLBRDDBUS7_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(7)", OutTemp => PPCS1PLBRDDBUS_OUT(7), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(8), GlitchData => PPCS1PLBRDDBUS8_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(8)", OutTemp => PPCS1PLBRDDBUS_OUT(8), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(9), GlitchData => PPCS1PLBRDDBUS9_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(9)", OutTemp => PPCS1PLBRDDBUS_OUT(9), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(10), GlitchData => PPCS1PLBRDDBUS10_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(10)", OutTemp => PPCS1PLBRDDBUS_OUT(10), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(11), GlitchData => PPCS1PLBRDDBUS11_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(11)", OutTemp => PPCS1PLBRDDBUS_OUT(11), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(12), GlitchData => PPCS1PLBRDDBUS12_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(12)", OutTemp => PPCS1PLBRDDBUS_OUT(12), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(13), GlitchData => PPCS1PLBRDDBUS13_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(13)", OutTemp => PPCS1PLBRDDBUS_OUT(13), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(14), GlitchData => PPCS1PLBRDDBUS14_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(14)", OutTemp => PPCS1PLBRDDBUS_OUT(14), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(15), GlitchData => PPCS1PLBRDDBUS15_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(15)", OutTemp => PPCS1PLBRDDBUS_OUT(15), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(16), GlitchData => PPCS1PLBRDDBUS16_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(16)", OutTemp => PPCS1PLBRDDBUS_OUT(16), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(17), GlitchData => PPCS1PLBRDDBUS17_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(17)", OutTemp => PPCS1PLBRDDBUS_OUT(17), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(18), GlitchData => PPCS1PLBRDDBUS18_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(18)", OutTemp => PPCS1PLBRDDBUS_OUT(18), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(19), GlitchData => PPCS1PLBRDDBUS19_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(19)", OutTemp => PPCS1PLBRDDBUS_OUT(19), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(20), GlitchData => PPCS1PLBRDDBUS20_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(20)", OutTemp => PPCS1PLBRDDBUS_OUT(20), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(21), GlitchData => PPCS1PLBRDDBUS21_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(21)", OutTemp => PPCS1PLBRDDBUS_OUT(21), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(22), GlitchData => PPCS1PLBRDDBUS22_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(22)", OutTemp => PPCS1PLBRDDBUS_OUT(22), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(23), GlitchData => PPCS1PLBRDDBUS23_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(23)", OutTemp => PPCS1PLBRDDBUS_OUT(23), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(24), GlitchData => PPCS1PLBRDDBUS24_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(24)", OutTemp => PPCS1PLBRDDBUS_OUT(24), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(25), GlitchData => PPCS1PLBRDDBUS25_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(25)", OutTemp => PPCS1PLBRDDBUS_OUT(25), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(26), GlitchData => PPCS1PLBRDDBUS26_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(26)", OutTemp => PPCS1PLBRDDBUS_OUT(26), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(27), GlitchData => PPCS1PLBRDDBUS27_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(27)", OutTemp => PPCS1PLBRDDBUS_OUT(27), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(28), GlitchData => PPCS1PLBRDDBUS28_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(28)", OutTemp => PPCS1PLBRDDBUS_OUT(28), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(29), GlitchData => PPCS1PLBRDDBUS29_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(29)", OutTemp => PPCS1PLBRDDBUS_OUT(29), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(30), GlitchData => PPCS1PLBRDDBUS30_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(30)", OutTemp => PPCS1PLBRDDBUS_OUT(30), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(31), GlitchData => PPCS1PLBRDDBUS31_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(31)", OutTemp => PPCS1PLBRDDBUS_OUT(31), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(32), GlitchData => PPCS1PLBRDDBUS32_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(32)", OutTemp => PPCS1PLBRDDBUS_OUT(32), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(33), GlitchData => PPCS1PLBRDDBUS33_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(33)", OutTemp => PPCS1PLBRDDBUS_OUT(33), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(34), GlitchData => PPCS1PLBRDDBUS34_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(34)", OutTemp => PPCS1PLBRDDBUS_OUT(34), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(35), GlitchData => PPCS1PLBRDDBUS35_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(35)", OutTemp => PPCS1PLBRDDBUS_OUT(35), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(36), GlitchData => PPCS1PLBRDDBUS36_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(36)", OutTemp => PPCS1PLBRDDBUS_OUT(36), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(37), GlitchData => PPCS1PLBRDDBUS37_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(37)", OutTemp => PPCS1PLBRDDBUS_OUT(37), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(38), GlitchData => PPCS1PLBRDDBUS38_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(38)", OutTemp => PPCS1PLBRDDBUS_OUT(38), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(39), GlitchData => PPCS1PLBRDDBUS39_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(39)", OutTemp => PPCS1PLBRDDBUS_OUT(39), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(40), GlitchData => PPCS1PLBRDDBUS40_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(40)", OutTemp => PPCS1PLBRDDBUS_OUT(40), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(41), GlitchData => PPCS1PLBRDDBUS41_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(41)", OutTemp => PPCS1PLBRDDBUS_OUT(41), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(42), GlitchData => PPCS1PLBRDDBUS42_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(42)", OutTemp => PPCS1PLBRDDBUS_OUT(42), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(43), GlitchData => PPCS1PLBRDDBUS43_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(43)", OutTemp => PPCS1PLBRDDBUS_OUT(43), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(44), GlitchData => PPCS1PLBRDDBUS44_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(44)", OutTemp => PPCS1PLBRDDBUS_OUT(44), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(45), GlitchData => PPCS1PLBRDDBUS45_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(45)", OutTemp => PPCS1PLBRDDBUS_OUT(45), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(46), GlitchData => PPCS1PLBRDDBUS46_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(46)", OutTemp => PPCS1PLBRDDBUS_OUT(46), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(47), GlitchData => PPCS1PLBRDDBUS47_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(47)", OutTemp => PPCS1PLBRDDBUS_OUT(47), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(48), GlitchData => PPCS1PLBRDDBUS48_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(48)", OutTemp => PPCS1PLBRDDBUS_OUT(48), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(49), GlitchData => PPCS1PLBRDDBUS49_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(49)", OutTemp => PPCS1PLBRDDBUS_OUT(49), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(50), GlitchData => PPCS1PLBRDDBUS50_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(50)", OutTemp => PPCS1PLBRDDBUS_OUT(50), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(51), GlitchData => PPCS1PLBRDDBUS51_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(51)", OutTemp => PPCS1PLBRDDBUS_OUT(51), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(52), GlitchData => PPCS1PLBRDDBUS52_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(52)", OutTemp => PPCS1PLBRDDBUS_OUT(52), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(53), GlitchData => PPCS1PLBRDDBUS53_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(53)", OutTemp => PPCS1PLBRDDBUS_OUT(53), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(54), GlitchData => PPCS1PLBRDDBUS54_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(54)", OutTemp => PPCS1PLBRDDBUS_OUT(54), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(55), GlitchData => PPCS1PLBRDDBUS55_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(55)", OutTemp => PPCS1PLBRDDBUS_OUT(55), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(56), GlitchData => PPCS1PLBRDDBUS56_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(56)", OutTemp => PPCS1PLBRDDBUS_OUT(56), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(57), GlitchData => PPCS1PLBRDDBUS57_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(57)", OutTemp => PPCS1PLBRDDBUS_OUT(57), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(58), GlitchData => PPCS1PLBRDDBUS58_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(58)", OutTemp => PPCS1PLBRDDBUS_OUT(58), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(59), GlitchData => PPCS1PLBRDDBUS59_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(59)", OutTemp => PPCS1PLBRDDBUS_OUT(59), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(60), GlitchData => PPCS1PLBRDDBUS60_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(60)", OutTemp => PPCS1PLBRDDBUS_OUT(60), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(61), GlitchData => PPCS1PLBRDDBUS61_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(61)", OutTemp => PPCS1PLBRDDBUS_OUT(61), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(62), GlitchData => PPCS1PLBRDDBUS62_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(62)", OutTemp => PPCS1PLBRDDBUS_OUT(62), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(63), GlitchData => PPCS1PLBRDDBUS63_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(63)", OutTemp => PPCS1PLBRDDBUS_OUT(63), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(64), GlitchData => PPCS1PLBRDDBUS64_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(64)", OutTemp => PPCS1PLBRDDBUS_OUT(64), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(65), GlitchData => PPCS1PLBRDDBUS65_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(65)", OutTemp => PPCS1PLBRDDBUS_OUT(65), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(66), GlitchData => PPCS1PLBRDDBUS66_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(66)", OutTemp => PPCS1PLBRDDBUS_OUT(66), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(67), GlitchData => PPCS1PLBRDDBUS67_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(67)", OutTemp => PPCS1PLBRDDBUS_OUT(67), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(68), GlitchData => PPCS1PLBRDDBUS68_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(68)", OutTemp => PPCS1PLBRDDBUS_OUT(68), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(69), GlitchData => PPCS1PLBRDDBUS69_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(69)", OutTemp => PPCS1PLBRDDBUS_OUT(69), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(70), GlitchData => PPCS1PLBRDDBUS70_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(70)", OutTemp => PPCS1PLBRDDBUS_OUT(70), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(71), GlitchData => PPCS1PLBRDDBUS71_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(71)", OutTemp => PPCS1PLBRDDBUS_OUT(71), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(72), GlitchData => PPCS1PLBRDDBUS72_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(72)", OutTemp => PPCS1PLBRDDBUS_OUT(72), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(73), GlitchData => PPCS1PLBRDDBUS73_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(73)", OutTemp => PPCS1PLBRDDBUS_OUT(73), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(74), GlitchData => PPCS1PLBRDDBUS74_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(74)", OutTemp => PPCS1PLBRDDBUS_OUT(74), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(75), GlitchData => PPCS1PLBRDDBUS75_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(75)", OutTemp => PPCS1PLBRDDBUS_OUT(75), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(76), GlitchData => PPCS1PLBRDDBUS76_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(76)", OutTemp => PPCS1PLBRDDBUS_OUT(76), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(77), GlitchData => PPCS1PLBRDDBUS77_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(77)", OutTemp => PPCS1PLBRDDBUS_OUT(77), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(78), GlitchData => PPCS1PLBRDDBUS78_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(78)", OutTemp => PPCS1PLBRDDBUS_OUT(78), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(79), GlitchData => PPCS1PLBRDDBUS79_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(79)", OutTemp => PPCS1PLBRDDBUS_OUT(79), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(80), GlitchData => PPCS1PLBRDDBUS80_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(80)", OutTemp => PPCS1PLBRDDBUS_OUT(80), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(81), GlitchData => PPCS1PLBRDDBUS81_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(81)", OutTemp => PPCS1PLBRDDBUS_OUT(81), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(82), GlitchData => PPCS1PLBRDDBUS82_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(82)", OutTemp => PPCS1PLBRDDBUS_OUT(82), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(83), GlitchData => PPCS1PLBRDDBUS83_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(83)", OutTemp => PPCS1PLBRDDBUS_OUT(83), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(84), GlitchData => PPCS1PLBRDDBUS84_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(84)", OutTemp => PPCS1PLBRDDBUS_OUT(84), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(85), GlitchData => PPCS1PLBRDDBUS85_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(85)", OutTemp => PPCS1PLBRDDBUS_OUT(85), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(86), GlitchData => PPCS1PLBRDDBUS86_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(86)", OutTemp => PPCS1PLBRDDBUS_OUT(86), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(87), GlitchData => PPCS1PLBRDDBUS87_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(87)", OutTemp => PPCS1PLBRDDBUS_OUT(87), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(88), GlitchData => PPCS1PLBRDDBUS88_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(88)", OutTemp => PPCS1PLBRDDBUS_OUT(88), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(89), GlitchData => PPCS1PLBRDDBUS89_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(89)", OutTemp => PPCS1PLBRDDBUS_OUT(89), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(90), GlitchData => PPCS1PLBRDDBUS90_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(90)", OutTemp => PPCS1PLBRDDBUS_OUT(90), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(91), GlitchData => PPCS1PLBRDDBUS91_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(91)", OutTemp => PPCS1PLBRDDBUS_OUT(91), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(92), GlitchData => PPCS1PLBRDDBUS92_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(92)", OutTemp => PPCS1PLBRDDBUS_OUT(92), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(93), GlitchData => PPCS1PLBRDDBUS93_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(93)", OutTemp => PPCS1PLBRDDBUS_OUT(93), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(94), GlitchData => PPCS1PLBRDDBUS94_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(94)", OutTemp => PPCS1PLBRDDBUS_OUT(94), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(95), GlitchData => PPCS1PLBRDDBUS95_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(95)", OutTemp => PPCS1PLBRDDBUS_OUT(95), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(96), GlitchData => PPCS1PLBRDDBUS96_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(96)", OutTemp => PPCS1PLBRDDBUS_OUT(96), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(97), GlitchData => PPCS1PLBRDDBUS97_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(97)", OutTemp => PPCS1PLBRDDBUS_OUT(97), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(98), GlitchData => PPCS1PLBRDDBUS98_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(98)", OutTemp => PPCS1PLBRDDBUS_OUT(98), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(99), GlitchData => PPCS1PLBRDDBUS99_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(99)", OutTemp => PPCS1PLBRDDBUS_OUT(99), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(100), GlitchData => PPCS1PLBRDDBUS100_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(100)", OutTemp => PPCS1PLBRDDBUS_OUT(100), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(101), GlitchData => PPCS1PLBRDDBUS101_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(101)", OutTemp => PPCS1PLBRDDBUS_OUT(101), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(102), GlitchData => PPCS1PLBRDDBUS102_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(102)", OutTemp => PPCS1PLBRDDBUS_OUT(102), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(103), GlitchData => PPCS1PLBRDDBUS103_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(103)", OutTemp => PPCS1PLBRDDBUS_OUT(103), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(104), GlitchData => PPCS1PLBRDDBUS104_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(104)", OutTemp => PPCS1PLBRDDBUS_OUT(104), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(105), GlitchData => PPCS1PLBRDDBUS105_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(105)", OutTemp => PPCS1PLBRDDBUS_OUT(105), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(106), GlitchData => PPCS1PLBRDDBUS106_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(106)", OutTemp => PPCS1PLBRDDBUS_OUT(106), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(107), GlitchData => PPCS1PLBRDDBUS107_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(107)", OutTemp => PPCS1PLBRDDBUS_OUT(107), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(108), GlitchData => PPCS1PLBRDDBUS108_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(108)", OutTemp => PPCS1PLBRDDBUS_OUT(108), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(109), GlitchData => PPCS1PLBRDDBUS109_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(109)", OutTemp => PPCS1PLBRDDBUS_OUT(109), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(110), GlitchData => PPCS1PLBRDDBUS110_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(110)", OutTemp => PPCS1PLBRDDBUS_OUT(110), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(111), GlitchData => PPCS1PLBRDDBUS111_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(111)", OutTemp => PPCS1PLBRDDBUS_OUT(111), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(112), GlitchData => PPCS1PLBRDDBUS112_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(112)", OutTemp => PPCS1PLBRDDBUS_OUT(112), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(113), GlitchData => PPCS1PLBRDDBUS113_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(113)", OutTemp => PPCS1PLBRDDBUS_OUT(113), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(114), GlitchData => PPCS1PLBRDDBUS114_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(114)", OutTemp => PPCS1PLBRDDBUS_OUT(114), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(115), GlitchData => PPCS1PLBRDDBUS115_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(115)", OutTemp => PPCS1PLBRDDBUS_OUT(115), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(116), GlitchData => PPCS1PLBRDDBUS116_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(116)", OutTemp => PPCS1PLBRDDBUS_OUT(116), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(117), GlitchData => PPCS1PLBRDDBUS117_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(117)", OutTemp => PPCS1PLBRDDBUS_OUT(117), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(118), GlitchData => PPCS1PLBRDDBUS118_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(118)", OutTemp => PPCS1PLBRDDBUS_OUT(118), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(119), GlitchData => PPCS1PLBRDDBUS119_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(119)", OutTemp => PPCS1PLBRDDBUS_OUT(119), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(120), GlitchData => PPCS1PLBRDDBUS120_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(120)", OutTemp => PPCS1PLBRDDBUS_OUT(120), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(121), GlitchData => PPCS1PLBRDDBUS121_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(121)", OutTemp => PPCS1PLBRDDBUS_OUT(121), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(122), GlitchData => PPCS1PLBRDDBUS122_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(122)", OutTemp => PPCS1PLBRDDBUS_OUT(122), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(123), GlitchData => PPCS1PLBRDDBUS123_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(123)", OutTemp => PPCS1PLBRDDBUS_OUT(123), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(124), GlitchData => PPCS1PLBRDDBUS124_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(124)", OutTemp => PPCS1PLBRDDBUS_OUT(124), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(125), GlitchData => PPCS1PLBRDDBUS125_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(125)", OutTemp => PPCS1PLBRDDBUS_OUT(125), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(126), GlitchData => PPCS1PLBRDDBUS126_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(126)", OutTemp => PPCS1PLBRDDBUS_OUT(126), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDDBUS(127), GlitchData => PPCS1PLBRDDBUS127_GlitchData, OutSignalName => "PPCS1PLBRDDBUS(127)", OutTemp => PPCS1PLBRDDBUS_OUT(127), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDWDADDR(0), GlitchData => PPCS1PLBRDWDADDR0_GlitchData, OutSignalName => "PPCS1PLBRDWDADDR(0)", OutTemp => PPCS1PLBRDWDADDR_OUT(0), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDWDADDR(1), GlitchData => PPCS1PLBRDWDADDR1_GlitchData, OutSignalName => "PPCS1PLBRDWDADDR(1)", OutTemp => PPCS1PLBRDWDADDR_OUT(1), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDWDADDR(2), GlitchData => PPCS1PLBRDWDADDR2_GlitchData, OutSignalName => "PPCS1PLBRDWDADDR(2)", OutTemp => PPCS1PLBRDWDADDR_OUT(2), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBRDWDADDR(3), GlitchData => PPCS1PLBRDWDADDR3_GlitchData, OutSignalName => "PPCS1PLBRDWDADDR(3)", OutTemp => PPCS1PLBRDWDADDR_OUT(3), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBREARBITRATE, GlitchData => PPCS1PLBREARBITRATE_GlitchData, OutSignalName => "PPCS1PLBREARBITRATE", OutTemp => PPCS1PLBREARBITRATE_OUT, Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBSSIZE(0), GlitchData => PPCS1PLBSSIZE0_GlitchData, OutSignalName => "PPCS1PLBSSIZE(0)", OutTemp => PPCS1PLBSSIZE_OUT(0), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBSSIZE(1), GlitchData => PPCS1PLBSSIZE1_GlitchData, OutSignalName => "PPCS1PLBSSIZE(1)", OutTemp => PPCS1PLBSSIZE_OUT(1), Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBWAIT, GlitchData => PPCS1PLBWAIT_GlitchData, OutSignalName => "PPCS1PLBWAIT", OutTemp => PPCS1PLBWAIT_OUT, Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBWRBTERM, GlitchData => PPCS1PLBWRBTERM_GlitchData, OutSignalName => "PPCS1PLBWRBTERM", OutTemp => PPCS1PLBWRBTERM_OUT, Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBWRCOMP, GlitchData => PPCS1PLBWRCOMP_GlitchData, OutSignalName => "PPCS1PLBWRCOMP", OutTemp => PPCS1PLBWRCOMP_OUT, Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCS1PLBWRDACK, GlitchData => PPCS1PLBWRDACK_GlitchData, OutSignalName => "PPCS1PLBWRDACK", OutTemp => PPCS1PLBWRDACK_OUT, Paths => (0 => (CPMPPCS1PLBCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECFPUOP, GlitchData => APUFCMDECFPUOP_GlitchData, OutSignalName => "APUFCMDECFPUOP", OutTemp => APUFCMDECFPUOP_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECLDSTXFERSIZE(0), GlitchData => APUFCMDECLDSTXFERSIZE0_GlitchData, OutSignalName => "APUFCMDECLDSTXFERSIZE(0)", OutTemp => APUFCMDECLDSTXFERSIZE_OUT(0), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECLDSTXFERSIZE(1), GlitchData => APUFCMDECLDSTXFERSIZE1_GlitchData, OutSignalName => "APUFCMDECLDSTXFERSIZE(1)", OutTemp => APUFCMDECLDSTXFERSIZE_OUT(1), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECLDSTXFERSIZE(2), GlitchData => APUFCMDECLDSTXFERSIZE2_GlitchData, OutSignalName => "APUFCMDECLDSTXFERSIZE(2)", OutTemp => APUFCMDECLDSTXFERSIZE_OUT(2), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECLOAD, GlitchData => APUFCMDECLOAD_GlitchData, OutSignalName => "APUFCMDECLOAD", OutTemp => APUFCMDECLOAD_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECNONAUTON, GlitchData => APUFCMDECNONAUTON_GlitchData, OutSignalName => "APUFCMDECNONAUTON", OutTemp => APUFCMDECNONAUTON_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECSTORE, GlitchData => APUFCMDECSTORE_GlitchData, OutSignalName => "APUFCMDECSTORE", OutTemp => APUFCMDECSTORE_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECUDI(0), GlitchData => APUFCMDECUDI0_GlitchData, OutSignalName => "APUFCMDECUDI(0)", OutTemp => APUFCMDECUDI_OUT(0), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECUDI(1), GlitchData => APUFCMDECUDI1_GlitchData, OutSignalName => "APUFCMDECUDI(1)", OutTemp => APUFCMDECUDI_OUT(1), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECUDI(2), GlitchData => APUFCMDECUDI2_GlitchData, OutSignalName => "APUFCMDECUDI(2)", OutTemp => APUFCMDECUDI_OUT(2), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECUDI(3), GlitchData => APUFCMDECUDI3_GlitchData, OutSignalName => "APUFCMDECUDI(3)", OutTemp => APUFCMDECUDI_OUT(3), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMDECUDIVALID, GlitchData => APUFCMDECUDIVALID_GlitchData, OutSignalName => "APUFCMDECUDIVALID", OutTemp => APUFCMDECUDIVALID_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMENDIAN, GlitchData => APUFCMENDIAN_GlitchData, OutSignalName => "APUFCMENDIAN", OutTemp => APUFCMENDIAN_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMFLUSH, GlitchData => APUFCMFLUSH_GlitchData, OutSignalName => "APUFCMFLUSH", OutTemp => APUFCMFLUSH_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(0), GlitchData => APUFCMINSTRUCTION0_GlitchData, OutSignalName => "APUFCMINSTRUCTION(0)", OutTemp => APUFCMINSTRUCTION_OUT(0), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(1), GlitchData => APUFCMINSTRUCTION1_GlitchData, OutSignalName => "APUFCMINSTRUCTION(1)", OutTemp => APUFCMINSTRUCTION_OUT(1), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(2), GlitchData => APUFCMINSTRUCTION2_GlitchData, OutSignalName => "APUFCMINSTRUCTION(2)", OutTemp => APUFCMINSTRUCTION_OUT(2), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(3), GlitchData => APUFCMINSTRUCTION3_GlitchData, OutSignalName => "APUFCMINSTRUCTION(3)", OutTemp => APUFCMINSTRUCTION_OUT(3), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(4), GlitchData => APUFCMINSTRUCTION4_GlitchData, OutSignalName => "APUFCMINSTRUCTION(4)", OutTemp => APUFCMINSTRUCTION_OUT(4), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(5), GlitchData => APUFCMINSTRUCTION5_GlitchData, OutSignalName => "APUFCMINSTRUCTION(5)", OutTemp => APUFCMINSTRUCTION_OUT(5), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(6), GlitchData => APUFCMINSTRUCTION6_GlitchData, OutSignalName => "APUFCMINSTRUCTION(6)", OutTemp => APUFCMINSTRUCTION_OUT(6), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(7), GlitchData => APUFCMINSTRUCTION7_GlitchData, OutSignalName => "APUFCMINSTRUCTION(7)", OutTemp => APUFCMINSTRUCTION_OUT(7), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(8), GlitchData => APUFCMINSTRUCTION8_GlitchData, OutSignalName => "APUFCMINSTRUCTION(8)", OutTemp => APUFCMINSTRUCTION_OUT(8), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(9), GlitchData => APUFCMINSTRUCTION9_GlitchData, OutSignalName => "APUFCMINSTRUCTION(9)", OutTemp => APUFCMINSTRUCTION_OUT(9), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(10), GlitchData => APUFCMINSTRUCTION10_GlitchData, OutSignalName => "APUFCMINSTRUCTION(10)", OutTemp => APUFCMINSTRUCTION_OUT(10), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(11), GlitchData => APUFCMINSTRUCTION11_GlitchData, OutSignalName => "APUFCMINSTRUCTION(11)", OutTemp => APUFCMINSTRUCTION_OUT(11), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(12), GlitchData => APUFCMINSTRUCTION12_GlitchData, OutSignalName => "APUFCMINSTRUCTION(12)", OutTemp => APUFCMINSTRUCTION_OUT(12), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(13), GlitchData => APUFCMINSTRUCTION13_GlitchData, OutSignalName => "APUFCMINSTRUCTION(13)", OutTemp => APUFCMINSTRUCTION_OUT(13), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(14), GlitchData => APUFCMINSTRUCTION14_GlitchData, OutSignalName => "APUFCMINSTRUCTION(14)", OutTemp => APUFCMINSTRUCTION_OUT(14), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(15), GlitchData => APUFCMINSTRUCTION15_GlitchData, OutSignalName => "APUFCMINSTRUCTION(15)", OutTemp => APUFCMINSTRUCTION_OUT(15), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(16), GlitchData => APUFCMINSTRUCTION16_GlitchData, OutSignalName => "APUFCMINSTRUCTION(16)", OutTemp => APUFCMINSTRUCTION_OUT(16), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(17), GlitchData => APUFCMINSTRUCTION17_GlitchData, OutSignalName => "APUFCMINSTRUCTION(17)", OutTemp => APUFCMINSTRUCTION_OUT(17), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(18), GlitchData => APUFCMINSTRUCTION18_GlitchData, OutSignalName => "APUFCMINSTRUCTION(18)", OutTemp => APUFCMINSTRUCTION_OUT(18), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(19), GlitchData => APUFCMINSTRUCTION19_GlitchData, OutSignalName => "APUFCMINSTRUCTION(19)", OutTemp => APUFCMINSTRUCTION_OUT(19), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(20), GlitchData => APUFCMINSTRUCTION20_GlitchData, OutSignalName => "APUFCMINSTRUCTION(20)", OutTemp => APUFCMINSTRUCTION_OUT(20), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(21), GlitchData => APUFCMINSTRUCTION21_GlitchData, OutSignalName => "APUFCMINSTRUCTION(21)", OutTemp => APUFCMINSTRUCTION_OUT(21), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(22), GlitchData => APUFCMINSTRUCTION22_GlitchData, OutSignalName => "APUFCMINSTRUCTION(22)", OutTemp => APUFCMINSTRUCTION_OUT(22), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(23), GlitchData => APUFCMINSTRUCTION23_GlitchData, OutSignalName => "APUFCMINSTRUCTION(23)", OutTemp => APUFCMINSTRUCTION_OUT(23), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(24), GlitchData => APUFCMINSTRUCTION24_GlitchData, OutSignalName => "APUFCMINSTRUCTION(24)", OutTemp => APUFCMINSTRUCTION_OUT(24), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(25), GlitchData => APUFCMINSTRUCTION25_GlitchData, OutSignalName => "APUFCMINSTRUCTION(25)", OutTemp => APUFCMINSTRUCTION_OUT(25), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(26), GlitchData => APUFCMINSTRUCTION26_GlitchData, OutSignalName => "APUFCMINSTRUCTION(26)", OutTemp => APUFCMINSTRUCTION_OUT(26), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(27), GlitchData => APUFCMINSTRUCTION27_GlitchData, OutSignalName => "APUFCMINSTRUCTION(27)", OutTemp => APUFCMINSTRUCTION_OUT(27), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(28), GlitchData => APUFCMINSTRUCTION28_GlitchData, OutSignalName => "APUFCMINSTRUCTION(28)", OutTemp => APUFCMINSTRUCTION_OUT(28), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(29), GlitchData => APUFCMINSTRUCTION29_GlitchData, OutSignalName => "APUFCMINSTRUCTION(29)", OutTemp => APUFCMINSTRUCTION_OUT(29), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(30), GlitchData => APUFCMINSTRUCTION30_GlitchData, OutSignalName => "APUFCMINSTRUCTION(30)", OutTemp => APUFCMINSTRUCTION_OUT(30), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRUCTION(31), GlitchData => APUFCMINSTRUCTION31_GlitchData, OutSignalName => "APUFCMINSTRUCTION(31)", OutTemp => APUFCMINSTRUCTION_OUT(31), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMINSTRVALID, GlitchData => APUFCMINSTRVALID_GlitchData, OutSignalName => "APUFCMINSTRVALID", OutTemp => APUFCMINSTRVALID_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADBYTEADDR(0), GlitchData => APUFCMLOADBYTEADDR0_GlitchData, OutSignalName => "APUFCMLOADBYTEADDR(0)", OutTemp => APUFCMLOADBYTEADDR_OUT(0), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADBYTEADDR(1), GlitchData => APUFCMLOADBYTEADDR1_GlitchData, OutSignalName => "APUFCMLOADBYTEADDR(1)", OutTemp => APUFCMLOADBYTEADDR_OUT(1), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADBYTEADDR(2), GlitchData => APUFCMLOADBYTEADDR2_GlitchData, OutSignalName => "APUFCMLOADBYTEADDR(2)", OutTemp => APUFCMLOADBYTEADDR_OUT(2), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADBYTEADDR(3), GlitchData => APUFCMLOADBYTEADDR3_GlitchData, OutSignalName => "APUFCMLOADBYTEADDR(3)", OutTemp => APUFCMLOADBYTEADDR_OUT(3), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(0), GlitchData => APUFCMLOADDATA0_GlitchData, OutSignalName => "APUFCMLOADDATA(0)", OutTemp => APUFCMLOADDATA_OUT(0), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(1), GlitchData => APUFCMLOADDATA1_GlitchData, OutSignalName => "APUFCMLOADDATA(1)", OutTemp => APUFCMLOADDATA_OUT(1), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(2), GlitchData => APUFCMLOADDATA2_GlitchData, OutSignalName => "APUFCMLOADDATA(2)", OutTemp => APUFCMLOADDATA_OUT(2), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(3), GlitchData => APUFCMLOADDATA3_GlitchData, OutSignalName => "APUFCMLOADDATA(3)", OutTemp => APUFCMLOADDATA_OUT(3), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(4), GlitchData => APUFCMLOADDATA4_GlitchData, OutSignalName => "APUFCMLOADDATA(4)", OutTemp => APUFCMLOADDATA_OUT(4), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(5), GlitchData => APUFCMLOADDATA5_GlitchData, OutSignalName => "APUFCMLOADDATA(5)", OutTemp => APUFCMLOADDATA_OUT(5), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(6), GlitchData => APUFCMLOADDATA6_GlitchData, OutSignalName => "APUFCMLOADDATA(6)", OutTemp => APUFCMLOADDATA_OUT(6), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(7), GlitchData => APUFCMLOADDATA7_GlitchData, OutSignalName => "APUFCMLOADDATA(7)", OutTemp => APUFCMLOADDATA_OUT(7), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(8), GlitchData => APUFCMLOADDATA8_GlitchData, OutSignalName => "APUFCMLOADDATA(8)", OutTemp => APUFCMLOADDATA_OUT(8), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(9), GlitchData => APUFCMLOADDATA9_GlitchData, OutSignalName => "APUFCMLOADDATA(9)", OutTemp => APUFCMLOADDATA_OUT(9), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(10), GlitchData => APUFCMLOADDATA10_GlitchData, OutSignalName => "APUFCMLOADDATA(10)", OutTemp => APUFCMLOADDATA_OUT(10), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(11), GlitchData => APUFCMLOADDATA11_GlitchData, OutSignalName => "APUFCMLOADDATA(11)", OutTemp => APUFCMLOADDATA_OUT(11), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(12), GlitchData => APUFCMLOADDATA12_GlitchData, OutSignalName => "APUFCMLOADDATA(12)", OutTemp => APUFCMLOADDATA_OUT(12), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(13), GlitchData => APUFCMLOADDATA13_GlitchData, OutSignalName => "APUFCMLOADDATA(13)", OutTemp => APUFCMLOADDATA_OUT(13), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(14), GlitchData => APUFCMLOADDATA14_GlitchData, OutSignalName => "APUFCMLOADDATA(14)", OutTemp => APUFCMLOADDATA_OUT(14), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(15), GlitchData => APUFCMLOADDATA15_GlitchData, OutSignalName => "APUFCMLOADDATA(15)", OutTemp => APUFCMLOADDATA_OUT(15), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(16), GlitchData => APUFCMLOADDATA16_GlitchData, OutSignalName => "APUFCMLOADDATA(16)", OutTemp => APUFCMLOADDATA_OUT(16), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(17), GlitchData => APUFCMLOADDATA17_GlitchData, OutSignalName => "APUFCMLOADDATA(17)", OutTemp => APUFCMLOADDATA_OUT(17), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(18), GlitchData => APUFCMLOADDATA18_GlitchData, OutSignalName => "APUFCMLOADDATA(18)", OutTemp => APUFCMLOADDATA_OUT(18), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(19), GlitchData => APUFCMLOADDATA19_GlitchData, OutSignalName => "APUFCMLOADDATA(19)", OutTemp => APUFCMLOADDATA_OUT(19), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(20), GlitchData => APUFCMLOADDATA20_GlitchData, OutSignalName => "APUFCMLOADDATA(20)", OutTemp => APUFCMLOADDATA_OUT(20), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(21), GlitchData => APUFCMLOADDATA21_GlitchData, OutSignalName => "APUFCMLOADDATA(21)", OutTemp => APUFCMLOADDATA_OUT(21), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(22), GlitchData => APUFCMLOADDATA22_GlitchData, OutSignalName => "APUFCMLOADDATA(22)", OutTemp => APUFCMLOADDATA_OUT(22), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(23), GlitchData => APUFCMLOADDATA23_GlitchData, OutSignalName => "APUFCMLOADDATA(23)", OutTemp => APUFCMLOADDATA_OUT(23), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(24), GlitchData => APUFCMLOADDATA24_GlitchData, OutSignalName => "APUFCMLOADDATA(24)", OutTemp => APUFCMLOADDATA_OUT(24), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(25), GlitchData => APUFCMLOADDATA25_GlitchData, OutSignalName => "APUFCMLOADDATA(25)", OutTemp => APUFCMLOADDATA_OUT(25), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(26), GlitchData => APUFCMLOADDATA26_GlitchData, OutSignalName => "APUFCMLOADDATA(26)", OutTemp => APUFCMLOADDATA_OUT(26), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(27), GlitchData => APUFCMLOADDATA27_GlitchData, OutSignalName => "APUFCMLOADDATA(27)", OutTemp => APUFCMLOADDATA_OUT(27), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(28), GlitchData => APUFCMLOADDATA28_GlitchData, OutSignalName => "APUFCMLOADDATA(28)", OutTemp => APUFCMLOADDATA_OUT(28), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(29), GlitchData => APUFCMLOADDATA29_GlitchData, OutSignalName => "APUFCMLOADDATA(29)", OutTemp => APUFCMLOADDATA_OUT(29), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(30), GlitchData => APUFCMLOADDATA30_GlitchData, OutSignalName => "APUFCMLOADDATA(30)", OutTemp => APUFCMLOADDATA_OUT(30), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(31), GlitchData => APUFCMLOADDATA31_GlitchData, OutSignalName => "APUFCMLOADDATA(31)", OutTemp => APUFCMLOADDATA_OUT(31), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(32), GlitchData => APUFCMLOADDATA32_GlitchData, OutSignalName => "APUFCMLOADDATA(32)", OutTemp => APUFCMLOADDATA_OUT(32), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(33), GlitchData => APUFCMLOADDATA33_GlitchData, OutSignalName => "APUFCMLOADDATA(33)", OutTemp => APUFCMLOADDATA_OUT(33), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(34), GlitchData => APUFCMLOADDATA34_GlitchData, OutSignalName => "APUFCMLOADDATA(34)", OutTemp => APUFCMLOADDATA_OUT(34), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(35), GlitchData => APUFCMLOADDATA35_GlitchData, OutSignalName => "APUFCMLOADDATA(35)", OutTemp => APUFCMLOADDATA_OUT(35), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(36), GlitchData => APUFCMLOADDATA36_GlitchData, OutSignalName => "APUFCMLOADDATA(36)", OutTemp => APUFCMLOADDATA_OUT(36), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(37), GlitchData => APUFCMLOADDATA37_GlitchData, OutSignalName => "APUFCMLOADDATA(37)", OutTemp => APUFCMLOADDATA_OUT(37), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(38), GlitchData => APUFCMLOADDATA38_GlitchData, OutSignalName => "APUFCMLOADDATA(38)", OutTemp => APUFCMLOADDATA_OUT(38), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(39), GlitchData => APUFCMLOADDATA39_GlitchData, OutSignalName => "APUFCMLOADDATA(39)", OutTemp => APUFCMLOADDATA_OUT(39), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(40), GlitchData => APUFCMLOADDATA40_GlitchData, OutSignalName => "APUFCMLOADDATA(40)", OutTemp => APUFCMLOADDATA_OUT(40), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(41), GlitchData => APUFCMLOADDATA41_GlitchData, OutSignalName => "APUFCMLOADDATA(41)", OutTemp => APUFCMLOADDATA_OUT(41), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(42), GlitchData => APUFCMLOADDATA42_GlitchData, OutSignalName => "APUFCMLOADDATA(42)", OutTemp => APUFCMLOADDATA_OUT(42), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(43), GlitchData => APUFCMLOADDATA43_GlitchData, OutSignalName => "APUFCMLOADDATA(43)", OutTemp => APUFCMLOADDATA_OUT(43), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(44), GlitchData => APUFCMLOADDATA44_GlitchData, OutSignalName => "APUFCMLOADDATA(44)", OutTemp => APUFCMLOADDATA_OUT(44), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(45), GlitchData => APUFCMLOADDATA45_GlitchData, OutSignalName => "APUFCMLOADDATA(45)", OutTemp => APUFCMLOADDATA_OUT(45), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(46), GlitchData => APUFCMLOADDATA46_GlitchData, OutSignalName => "APUFCMLOADDATA(46)", OutTemp => APUFCMLOADDATA_OUT(46), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(47), GlitchData => APUFCMLOADDATA47_GlitchData, OutSignalName => "APUFCMLOADDATA(47)", OutTemp => APUFCMLOADDATA_OUT(47), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(48), GlitchData => APUFCMLOADDATA48_GlitchData, OutSignalName => "APUFCMLOADDATA(48)", OutTemp => APUFCMLOADDATA_OUT(48), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(49), GlitchData => APUFCMLOADDATA49_GlitchData, OutSignalName => "APUFCMLOADDATA(49)", OutTemp => APUFCMLOADDATA_OUT(49), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(50), GlitchData => APUFCMLOADDATA50_GlitchData, OutSignalName => "APUFCMLOADDATA(50)", OutTemp => APUFCMLOADDATA_OUT(50), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(51), GlitchData => APUFCMLOADDATA51_GlitchData, OutSignalName => "APUFCMLOADDATA(51)", OutTemp => APUFCMLOADDATA_OUT(51), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(52), GlitchData => APUFCMLOADDATA52_GlitchData, OutSignalName => "APUFCMLOADDATA(52)", OutTemp => APUFCMLOADDATA_OUT(52), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(53), GlitchData => APUFCMLOADDATA53_GlitchData, OutSignalName => "APUFCMLOADDATA(53)", OutTemp => APUFCMLOADDATA_OUT(53), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(54), GlitchData => APUFCMLOADDATA54_GlitchData, OutSignalName => "APUFCMLOADDATA(54)", OutTemp => APUFCMLOADDATA_OUT(54), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(55), GlitchData => APUFCMLOADDATA55_GlitchData, OutSignalName => "APUFCMLOADDATA(55)", OutTemp => APUFCMLOADDATA_OUT(55), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(56), GlitchData => APUFCMLOADDATA56_GlitchData, OutSignalName => "APUFCMLOADDATA(56)", OutTemp => APUFCMLOADDATA_OUT(56), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(57), GlitchData => APUFCMLOADDATA57_GlitchData, OutSignalName => "APUFCMLOADDATA(57)", OutTemp => APUFCMLOADDATA_OUT(57), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(58), GlitchData => APUFCMLOADDATA58_GlitchData, OutSignalName => "APUFCMLOADDATA(58)", OutTemp => APUFCMLOADDATA_OUT(58), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(59), GlitchData => APUFCMLOADDATA59_GlitchData, OutSignalName => "APUFCMLOADDATA(59)", OutTemp => APUFCMLOADDATA_OUT(59), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(60), GlitchData => APUFCMLOADDATA60_GlitchData, OutSignalName => "APUFCMLOADDATA(60)", OutTemp => APUFCMLOADDATA_OUT(60), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(61), GlitchData => APUFCMLOADDATA61_GlitchData, OutSignalName => "APUFCMLOADDATA(61)", OutTemp => APUFCMLOADDATA_OUT(61), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(62), GlitchData => APUFCMLOADDATA62_GlitchData, OutSignalName => "APUFCMLOADDATA(62)", OutTemp => APUFCMLOADDATA_OUT(62), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(63), GlitchData => APUFCMLOADDATA63_GlitchData, OutSignalName => "APUFCMLOADDATA(63)", OutTemp => APUFCMLOADDATA_OUT(63), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(64), GlitchData => APUFCMLOADDATA64_GlitchData, OutSignalName => "APUFCMLOADDATA(64)", OutTemp => APUFCMLOADDATA_OUT(64), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(65), GlitchData => APUFCMLOADDATA65_GlitchData, OutSignalName => "APUFCMLOADDATA(65)", OutTemp => APUFCMLOADDATA_OUT(65), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(66), GlitchData => APUFCMLOADDATA66_GlitchData, OutSignalName => "APUFCMLOADDATA(66)", OutTemp => APUFCMLOADDATA_OUT(66), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(67), GlitchData => APUFCMLOADDATA67_GlitchData, OutSignalName => "APUFCMLOADDATA(67)", OutTemp => APUFCMLOADDATA_OUT(67), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(68), GlitchData => APUFCMLOADDATA68_GlitchData, OutSignalName => "APUFCMLOADDATA(68)", OutTemp => APUFCMLOADDATA_OUT(68), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(69), GlitchData => APUFCMLOADDATA69_GlitchData, OutSignalName => "APUFCMLOADDATA(69)", OutTemp => APUFCMLOADDATA_OUT(69), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(70), GlitchData => APUFCMLOADDATA70_GlitchData, OutSignalName => "APUFCMLOADDATA(70)", OutTemp => APUFCMLOADDATA_OUT(70), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(71), GlitchData => APUFCMLOADDATA71_GlitchData, OutSignalName => "APUFCMLOADDATA(71)", OutTemp => APUFCMLOADDATA_OUT(71), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(72), GlitchData => APUFCMLOADDATA72_GlitchData, OutSignalName => "APUFCMLOADDATA(72)", OutTemp => APUFCMLOADDATA_OUT(72), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(73), GlitchData => APUFCMLOADDATA73_GlitchData, OutSignalName => "APUFCMLOADDATA(73)", OutTemp => APUFCMLOADDATA_OUT(73), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(74), GlitchData => APUFCMLOADDATA74_GlitchData, OutSignalName => "APUFCMLOADDATA(74)", OutTemp => APUFCMLOADDATA_OUT(74), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(75), GlitchData => APUFCMLOADDATA75_GlitchData, OutSignalName => "APUFCMLOADDATA(75)", OutTemp => APUFCMLOADDATA_OUT(75), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(76), GlitchData => APUFCMLOADDATA76_GlitchData, OutSignalName => "APUFCMLOADDATA(76)", OutTemp => APUFCMLOADDATA_OUT(76), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(77), GlitchData => APUFCMLOADDATA77_GlitchData, OutSignalName => "APUFCMLOADDATA(77)", OutTemp => APUFCMLOADDATA_OUT(77), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(78), GlitchData => APUFCMLOADDATA78_GlitchData, OutSignalName => "APUFCMLOADDATA(78)", OutTemp => APUFCMLOADDATA_OUT(78), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(79), GlitchData => APUFCMLOADDATA79_GlitchData, OutSignalName => "APUFCMLOADDATA(79)", OutTemp => APUFCMLOADDATA_OUT(79), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(80), GlitchData => APUFCMLOADDATA80_GlitchData, OutSignalName => "APUFCMLOADDATA(80)", OutTemp => APUFCMLOADDATA_OUT(80), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(81), GlitchData => APUFCMLOADDATA81_GlitchData, OutSignalName => "APUFCMLOADDATA(81)", OutTemp => APUFCMLOADDATA_OUT(81), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(82), GlitchData => APUFCMLOADDATA82_GlitchData, OutSignalName => "APUFCMLOADDATA(82)", OutTemp => APUFCMLOADDATA_OUT(82), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(83), GlitchData => APUFCMLOADDATA83_GlitchData, OutSignalName => "APUFCMLOADDATA(83)", OutTemp => APUFCMLOADDATA_OUT(83), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(84), GlitchData => APUFCMLOADDATA84_GlitchData, OutSignalName => "APUFCMLOADDATA(84)", OutTemp => APUFCMLOADDATA_OUT(84), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(85), GlitchData => APUFCMLOADDATA85_GlitchData, OutSignalName => "APUFCMLOADDATA(85)", OutTemp => APUFCMLOADDATA_OUT(85), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(86), GlitchData => APUFCMLOADDATA86_GlitchData, OutSignalName => "APUFCMLOADDATA(86)", OutTemp => APUFCMLOADDATA_OUT(86), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(87), GlitchData => APUFCMLOADDATA87_GlitchData, OutSignalName => "APUFCMLOADDATA(87)", OutTemp => APUFCMLOADDATA_OUT(87), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(88), GlitchData => APUFCMLOADDATA88_GlitchData, OutSignalName => "APUFCMLOADDATA(88)", OutTemp => APUFCMLOADDATA_OUT(88), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(89), GlitchData => APUFCMLOADDATA89_GlitchData, OutSignalName => "APUFCMLOADDATA(89)", OutTemp => APUFCMLOADDATA_OUT(89), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(90), GlitchData => APUFCMLOADDATA90_GlitchData, OutSignalName => "APUFCMLOADDATA(90)", OutTemp => APUFCMLOADDATA_OUT(90), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(91), GlitchData => APUFCMLOADDATA91_GlitchData, OutSignalName => "APUFCMLOADDATA(91)", OutTemp => APUFCMLOADDATA_OUT(91), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(92), GlitchData => APUFCMLOADDATA92_GlitchData, OutSignalName => "APUFCMLOADDATA(92)", OutTemp => APUFCMLOADDATA_OUT(92), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(93), GlitchData => APUFCMLOADDATA93_GlitchData, OutSignalName => "APUFCMLOADDATA(93)", OutTemp => APUFCMLOADDATA_OUT(93), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(94), GlitchData => APUFCMLOADDATA94_GlitchData, OutSignalName => "APUFCMLOADDATA(94)", OutTemp => APUFCMLOADDATA_OUT(94), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(95), GlitchData => APUFCMLOADDATA95_GlitchData, OutSignalName => "APUFCMLOADDATA(95)", OutTemp => APUFCMLOADDATA_OUT(95), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(96), GlitchData => APUFCMLOADDATA96_GlitchData, OutSignalName => "APUFCMLOADDATA(96)", OutTemp => APUFCMLOADDATA_OUT(96), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(97), GlitchData => APUFCMLOADDATA97_GlitchData, OutSignalName => "APUFCMLOADDATA(97)", OutTemp => APUFCMLOADDATA_OUT(97), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(98), GlitchData => APUFCMLOADDATA98_GlitchData, OutSignalName => "APUFCMLOADDATA(98)", OutTemp => APUFCMLOADDATA_OUT(98), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(99), GlitchData => APUFCMLOADDATA99_GlitchData, OutSignalName => "APUFCMLOADDATA(99)", OutTemp => APUFCMLOADDATA_OUT(99), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(100), GlitchData => APUFCMLOADDATA100_GlitchData, OutSignalName => "APUFCMLOADDATA(100)", OutTemp => APUFCMLOADDATA_OUT(100), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(101), GlitchData => APUFCMLOADDATA101_GlitchData, OutSignalName => "APUFCMLOADDATA(101)", OutTemp => APUFCMLOADDATA_OUT(101), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(102), GlitchData => APUFCMLOADDATA102_GlitchData, OutSignalName => "APUFCMLOADDATA(102)", OutTemp => APUFCMLOADDATA_OUT(102), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(103), GlitchData => APUFCMLOADDATA103_GlitchData, OutSignalName => "APUFCMLOADDATA(103)", OutTemp => APUFCMLOADDATA_OUT(103), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(104), GlitchData => APUFCMLOADDATA104_GlitchData, OutSignalName => "APUFCMLOADDATA(104)", OutTemp => APUFCMLOADDATA_OUT(104), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(105), GlitchData => APUFCMLOADDATA105_GlitchData, OutSignalName => "APUFCMLOADDATA(105)", OutTemp => APUFCMLOADDATA_OUT(105), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(106), GlitchData => APUFCMLOADDATA106_GlitchData, OutSignalName => "APUFCMLOADDATA(106)", OutTemp => APUFCMLOADDATA_OUT(106), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(107), GlitchData => APUFCMLOADDATA107_GlitchData, OutSignalName => "APUFCMLOADDATA(107)", OutTemp => APUFCMLOADDATA_OUT(107), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(108), GlitchData => APUFCMLOADDATA108_GlitchData, OutSignalName => "APUFCMLOADDATA(108)", OutTemp => APUFCMLOADDATA_OUT(108), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(109), GlitchData => APUFCMLOADDATA109_GlitchData, OutSignalName => "APUFCMLOADDATA(109)", OutTemp => APUFCMLOADDATA_OUT(109), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(110), GlitchData => APUFCMLOADDATA110_GlitchData, OutSignalName => "APUFCMLOADDATA(110)", OutTemp => APUFCMLOADDATA_OUT(110), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(111), GlitchData => APUFCMLOADDATA111_GlitchData, OutSignalName => "APUFCMLOADDATA(111)", OutTemp => APUFCMLOADDATA_OUT(111), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(112), GlitchData => APUFCMLOADDATA112_GlitchData, OutSignalName => "APUFCMLOADDATA(112)", OutTemp => APUFCMLOADDATA_OUT(112), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(113), GlitchData => APUFCMLOADDATA113_GlitchData, OutSignalName => "APUFCMLOADDATA(113)", OutTemp => APUFCMLOADDATA_OUT(113), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(114), GlitchData => APUFCMLOADDATA114_GlitchData, OutSignalName => "APUFCMLOADDATA(114)", OutTemp => APUFCMLOADDATA_OUT(114), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(115), GlitchData => APUFCMLOADDATA115_GlitchData, OutSignalName => "APUFCMLOADDATA(115)", OutTemp => APUFCMLOADDATA_OUT(115), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(116), GlitchData => APUFCMLOADDATA116_GlitchData, OutSignalName => "APUFCMLOADDATA(116)", OutTemp => APUFCMLOADDATA_OUT(116), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(117), GlitchData => APUFCMLOADDATA117_GlitchData, OutSignalName => "APUFCMLOADDATA(117)", OutTemp => APUFCMLOADDATA_OUT(117), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(118), GlitchData => APUFCMLOADDATA118_GlitchData, OutSignalName => "APUFCMLOADDATA(118)", OutTemp => APUFCMLOADDATA_OUT(118), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(119), GlitchData => APUFCMLOADDATA119_GlitchData, OutSignalName => "APUFCMLOADDATA(119)", OutTemp => APUFCMLOADDATA_OUT(119), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(120), GlitchData => APUFCMLOADDATA120_GlitchData, OutSignalName => "APUFCMLOADDATA(120)", OutTemp => APUFCMLOADDATA_OUT(120), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(121), GlitchData => APUFCMLOADDATA121_GlitchData, OutSignalName => "APUFCMLOADDATA(121)", OutTemp => APUFCMLOADDATA_OUT(121), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(122), GlitchData => APUFCMLOADDATA122_GlitchData, OutSignalName => "APUFCMLOADDATA(122)", OutTemp => APUFCMLOADDATA_OUT(122), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(123), GlitchData => APUFCMLOADDATA123_GlitchData, OutSignalName => "APUFCMLOADDATA(123)", OutTemp => APUFCMLOADDATA_OUT(123), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(124), GlitchData => APUFCMLOADDATA124_GlitchData, OutSignalName => "APUFCMLOADDATA(124)", OutTemp => APUFCMLOADDATA_OUT(124), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(125), GlitchData => APUFCMLOADDATA125_GlitchData, OutSignalName => "APUFCMLOADDATA(125)", OutTemp => APUFCMLOADDATA_OUT(125), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(126), GlitchData => APUFCMLOADDATA126_GlitchData, OutSignalName => "APUFCMLOADDATA(126)", OutTemp => APUFCMLOADDATA_OUT(126), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDATA(127), GlitchData => APUFCMLOADDATA127_GlitchData, OutSignalName => "APUFCMLOADDATA(127)", OutTemp => APUFCMLOADDATA_OUT(127), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMLOADDVALID, GlitchData => APUFCMLOADDVALID_GlitchData, OutSignalName => "APUFCMLOADDVALID", OutTemp => APUFCMLOADDVALID_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMMSRFE0, GlitchData => APUFCMMSRFE0_GlitchData, OutSignalName => "APUFCMMSRFE0", OutTemp => APUFCMMSRFE0_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMMSRFE1, GlitchData => APUFCMMSRFE1_GlitchData, OutSignalName => "APUFCMMSRFE1", OutTemp => APUFCMMSRFE1_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMNEXTINSTRREADY, GlitchData => APUFCMNEXTINSTRREADY_GlitchData, OutSignalName => "APUFCMNEXTINSTRREADY", OutTemp => APUFCMNEXTINSTRREADY_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMOPERANDVALID, GlitchData => APUFCMOPERANDVALID_GlitchData, OutSignalName => "APUFCMOPERANDVALID", OutTemp => APUFCMOPERANDVALID_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(0), GlitchData => APUFCMRADATA0_GlitchData, OutSignalName => "APUFCMRADATA(0)", OutTemp => APUFCMRADATA_OUT(0), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(1), GlitchData => APUFCMRADATA1_GlitchData, OutSignalName => "APUFCMRADATA(1)", OutTemp => APUFCMRADATA_OUT(1), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(2), GlitchData => APUFCMRADATA2_GlitchData, OutSignalName => "APUFCMRADATA(2)", OutTemp => APUFCMRADATA_OUT(2), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(3), GlitchData => APUFCMRADATA3_GlitchData, OutSignalName => "APUFCMRADATA(3)", OutTemp => APUFCMRADATA_OUT(3), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(4), GlitchData => APUFCMRADATA4_GlitchData, OutSignalName => "APUFCMRADATA(4)", OutTemp => APUFCMRADATA_OUT(4), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(5), GlitchData => APUFCMRADATA5_GlitchData, OutSignalName => "APUFCMRADATA(5)", OutTemp => APUFCMRADATA_OUT(5), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(6), GlitchData => APUFCMRADATA6_GlitchData, OutSignalName => "APUFCMRADATA(6)", OutTemp => APUFCMRADATA_OUT(6), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(7), GlitchData => APUFCMRADATA7_GlitchData, OutSignalName => "APUFCMRADATA(7)", OutTemp => APUFCMRADATA_OUT(7), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(8), GlitchData => APUFCMRADATA8_GlitchData, OutSignalName => "APUFCMRADATA(8)", OutTemp => APUFCMRADATA_OUT(8), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(9), GlitchData => APUFCMRADATA9_GlitchData, OutSignalName => "APUFCMRADATA(9)", OutTemp => APUFCMRADATA_OUT(9), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(10), GlitchData => APUFCMRADATA10_GlitchData, OutSignalName => "APUFCMRADATA(10)", OutTemp => APUFCMRADATA_OUT(10), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(11), GlitchData => APUFCMRADATA11_GlitchData, OutSignalName => "APUFCMRADATA(11)", OutTemp => APUFCMRADATA_OUT(11), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(12), GlitchData => APUFCMRADATA12_GlitchData, OutSignalName => "APUFCMRADATA(12)", OutTemp => APUFCMRADATA_OUT(12), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(13), GlitchData => APUFCMRADATA13_GlitchData, OutSignalName => "APUFCMRADATA(13)", OutTemp => APUFCMRADATA_OUT(13), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(14), GlitchData => APUFCMRADATA14_GlitchData, OutSignalName => "APUFCMRADATA(14)", OutTemp => APUFCMRADATA_OUT(14), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(15), GlitchData => APUFCMRADATA15_GlitchData, OutSignalName => "APUFCMRADATA(15)", OutTemp => APUFCMRADATA_OUT(15), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(16), GlitchData => APUFCMRADATA16_GlitchData, OutSignalName => "APUFCMRADATA(16)", OutTemp => APUFCMRADATA_OUT(16), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(17), GlitchData => APUFCMRADATA17_GlitchData, OutSignalName => "APUFCMRADATA(17)", OutTemp => APUFCMRADATA_OUT(17), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(18), GlitchData => APUFCMRADATA18_GlitchData, OutSignalName => "APUFCMRADATA(18)", OutTemp => APUFCMRADATA_OUT(18), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(19), GlitchData => APUFCMRADATA19_GlitchData, OutSignalName => "APUFCMRADATA(19)", OutTemp => APUFCMRADATA_OUT(19), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(20), GlitchData => APUFCMRADATA20_GlitchData, OutSignalName => "APUFCMRADATA(20)", OutTemp => APUFCMRADATA_OUT(20), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(21), GlitchData => APUFCMRADATA21_GlitchData, OutSignalName => "APUFCMRADATA(21)", OutTemp => APUFCMRADATA_OUT(21), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(22), GlitchData => APUFCMRADATA22_GlitchData, OutSignalName => "APUFCMRADATA(22)", OutTemp => APUFCMRADATA_OUT(22), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(23), GlitchData => APUFCMRADATA23_GlitchData, OutSignalName => "APUFCMRADATA(23)", OutTemp => APUFCMRADATA_OUT(23), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(24), GlitchData => APUFCMRADATA24_GlitchData, OutSignalName => "APUFCMRADATA(24)", OutTemp => APUFCMRADATA_OUT(24), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(25), GlitchData => APUFCMRADATA25_GlitchData, OutSignalName => "APUFCMRADATA(25)", OutTemp => APUFCMRADATA_OUT(25), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(26), GlitchData => APUFCMRADATA26_GlitchData, OutSignalName => "APUFCMRADATA(26)", OutTemp => APUFCMRADATA_OUT(26), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(27), GlitchData => APUFCMRADATA27_GlitchData, OutSignalName => "APUFCMRADATA(27)", OutTemp => APUFCMRADATA_OUT(27), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(28), GlitchData => APUFCMRADATA28_GlitchData, OutSignalName => "APUFCMRADATA(28)", OutTemp => APUFCMRADATA_OUT(28), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(29), GlitchData => APUFCMRADATA29_GlitchData, OutSignalName => "APUFCMRADATA(29)", OutTemp => APUFCMRADATA_OUT(29), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(30), GlitchData => APUFCMRADATA30_GlitchData, OutSignalName => "APUFCMRADATA(30)", OutTemp => APUFCMRADATA_OUT(30), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRADATA(31), GlitchData => APUFCMRADATA31_GlitchData, OutSignalName => "APUFCMRADATA(31)", OutTemp => APUFCMRADATA_OUT(31), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(0), GlitchData => APUFCMRBDATA0_GlitchData, OutSignalName => "APUFCMRBDATA(0)", OutTemp => APUFCMRBDATA_OUT(0), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(1), GlitchData => APUFCMRBDATA1_GlitchData, OutSignalName => "APUFCMRBDATA(1)", OutTemp => APUFCMRBDATA_OUT(1), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(2), GlitchData => APUFCMRBDATA2_GlitchData, OutSignalName => "APUFCMRBDATA(2)", OutTemp => APUFCMRBDATA_OUT(2), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(3), GlitchData => APUFCMRBDATA3_GlitchData, OutSignalName => "APUFCMRBDATA(3)", OutTemp => APUFCMRBDATA_OUT(3), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(4), GlitchData => APUFCMRBDATA4_GlitchData, OutSignalName => "APUFCMRBDATA(4)", OutTemp => APUFCMRBDATA_OUT(4), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(5), GlitchData => APUFCMRBDATA5_GlitchData, OutSignalName => "APUFCMRBDATA(5)", OutTemp => APUFCMRBDATA_OUT(5), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(6), GlitchData => APUFCMRBDATA6_GlitchData, OutSignalName => "APUFCMRBDATA(6)", OutTemp => APUFCMRBDATA_OUT(6), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(7), GlitchData => APUFCMRBDATA7_GlitchData, OutSignalName => "APUFCMRBDATA(7)", OutTemp => APUFCMRBDATA_OUT(7), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(8), GlitchData => APUFCMRBDATA8_GlitchData, OutSignalName => "APUFCMRBDATA(8)", OutTemp => APUFCMRBDATA_OUT(8), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(9), GlitchData => APUFCMRBDATA9_GlitchData, OutSignalName => "APUFCMRBDATA(9)", OutTemp => APUFCMRBDATA_OUT(9), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(10), GlitchData => APUFCMRBDATA10_GlitchData, OutSignalName => "APUFCMRBDATA(10)", OutTemp => APUFCMRBDATA_OUT(10), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(11), GlitchData => APUFCMRBDATA11_GlitchData, OutSignalName => "APUFCMRBDATA(11)", OutTemp => APUFCMRBDATA_OUT(11), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(12), GlitchData => APUFCMRBDATA12_GlitchData, OutSignalName => "APUFCMRBDATA(12)", OutTemp => APUFCMRBDATA_OUT(12), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(13), GlitchData => APUFCMRBDATA13_GlitchData, OutSignalName => "APUFCMRBDATA(13)", OutTemp => APUFCMRBDATA_OUT(13), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(14), GlitchData => APUFCMRBDATA14_GlitchData, OutSignalName => "APUFCMRBDATA(14)", OutTemp => APUFCMRBDATA_OUT(14), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(15), GlitchData => APUFCMRBDATA15_GlitchData, OutSignalName => "APUFCMRBDATA(15)", OutTemp => APUFCMRBDATA_OUT(15), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(16), GlitchData => APUFCMRBDATA16_GlitchData, OutSignalName => "APUFCMRBDATA(16)", OutTemp => APUFCMRBDATA_OUT(16), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(17), GlitchData => APUFCMRBDATA17_GlitchData, OutSignalName => "APUFCMRBDATA(17)", OutTemp => APUFCMRBDATA_OUT(17), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(18), GlitchData => APUFCMRBDATA18_GlitchData, OutSignalName => "APUFCMRBDATA(18)", OutTemp => APUFCMRBDATA_OUT(18), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(19), GlitchData => APUFCMRBDATA19_GlitchData, OutSignalName => "APUFCMRBDATA(19)", OutTemp => APUFCMRBDATA_OUT(19), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(20), GlitchData => APUFCMRBDATA20_GlitchData, OutSignalName => "APUFCMRBDATA(20)", OutTemp => APUFCMRBDATA_OUT(20), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(21), GlitchData => APUFCMRBDATA21_GlitchData, OutSignalName => "APUFCMRBDATA(21)", OutTemp => APUFCMRBDATA_OUT(21), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(22), GlitchData => APUFCMRBDATA22_GlitchData, OutSignalName => "APUFCMRBDATA(22)", OutTemp => APUFCMRBDATA_OUT(22), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(23), GlitchData => APUFCMRBDATA23_GlitchData, OutSignalName => "APUFCMRBDATA(23)", OutTemp => APUFCMRBDATA_OUT(23), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(24), GlitchData => APUFCMRBDATA24_GlitchData, OutSignalName => "APUFCMRBDATA(24)", OutTemp => APUFCMRBDATA_OUT(24), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(25), GlitchData => APUFCMRBDATA25_GlitchData, OutSignalName => "APUFCMRBDATA(25)", OutTemp => APUFCMRBDATA_OUT(25), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(26), GlitchData => APUFCMRBDATA26_GlitchData, OutSignalName => "APUFCMRBDATA(26)", OutTemp => APUFCMRBDATA_OUT(26), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(27), GlitchData => APUFCMRBDATA27_GlitchData, OutSignalName => "APUFCMRBDATA(27)", OutTemp => APUFCMRBDATA_OUT(27), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(28), GlitchData => APUFCMRBDATA28_GlitchData, OutSignalName => "APUFCMRBDATA(28)", OutTemp => APUFCMRBDATA_OUT(28), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(29), GlitchData => APUFCMRBDATA29_GlitchData, OutSignalName => "APUFCMRBDATA(29)", OutTemp => APUFCMRBDATA_OUT(29), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(30), GlitchData => APUFCMRBDATA30_GlitchData, OutSignalName => "APUFCMRBDATA(30)", OutTemp => APUFCMRBDATA_OUT(30), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMRBDATA(31), GlitchData => APUFCMRBDATA31_GlitchData, OutSignalName => "APUFCMRBDATA(31)", OutTemp => APUFCMRBDATA_OUT(31), Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => APUFCMWRITEBACKOK, GlitchData => APUFCMWRITEBACKOK_GlitchData, OutSignalName => "APUFCMWRITEBACKOK", OutTemp => APUFCMWRITEBACKOK_OUT, Paths => (0 => (CPMFCMCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440CPMCORESLEEPREQ, GlitchData => C440CPMCORESLEEPREQ_GlitchData, OutSignalName => "C440CPMCORESLEEPREQ", OutTemp => C440CPMCORESLEEPREQ_OUT, Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440CPMDECIRPTREQ, GlitchData => C440CPMDECIRPTREQ_GlitchData, OutSignalName => "C440CPMDECIRPTREQ", OutTemp => C440CPMDECIRPTREQ_OUT, Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440CPMFITIRPTREQ, GlitchData => C440CPMFITIRPTREQ_GlitchData, OutSignalName => "C440CPMFITIRPTREQ", OutTemp => C440CPMFITIRPTREQ_OUT, Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440CPMMSRCE, GlitchData => C440CPMMSRCE_GlitchData, OutSignalName => "C440CPMMSRCE", OutTemp => C440CPMMSRCE_OUT, Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440CPMMSREE, GlitchData => C440CPMMSREE_GlitchData, OutSignalName => "C440CPMMSREE", OutTemp => C440CPMMSREE_OUT, Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440CPMTIMERRESETREQ, GlitchData => C440CPMTIMERRESETREQ_GlitchData, OutSignalName => "C440CPMTIMERRESETREQ", OutTemp => C440CPMTIMERRESETREQ_OUT, Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440CPMWDIRPTREQ, GlitchData => C440CPMWDIRPTREQ_GlitchData, OutSignalName => "C440CPMWDIRPTREQ", OutTemp => C440CPMWDIRPTREQ_OUT, Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440DBGSYSTEMCONTROL(0), GlitchData => C440DBGSYSTEMCONTROL0_GlitchData, OutSignalName => "C440DBGSYSTEMCONTROL(0)", OutTemp => C440DBGSYSTEMCONTROL_OUT(0), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440DBGSYSTEMCONTROL(1), GlitchData => C440DBGSYSTEMCONTROL1_GlitchData, OutSignalName => "C440DBGSYSTEMCONTROL(1)", OutTemp => C440DBGSYSTEMCONTROL_OUT(1), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440DBGSYSTEMCONTROL(2), GlitchData => C440DBGSYSTEMCONTROL2_GlitchData, OutSignalName => "C440DBGSYSTEMCONTROL(2)", OutTemp => C440DBGSYSTEMCONTROL_OUT(2), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440DBGSYSTEMCONTROL(3), GlitchData => C440DBGSYSTEMCONTROL3_GlitchData, OutSignalName => "C440DBGSYSTEMCONTROL(3)", OutTemp => C440DBGSYSTEMCONTROL_OUT(3), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440DBGSYSTEMCONTROL(4), GlitchData => C440DBGSYSTEMCONTROL4_GlitchData, OutSignalName => "C440DBGSYSTEMCONTROL(4)", OutTemp => C440DBGSYSTEMCONTROL_OUT(4), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440DBGSYSTEMCONTROL(5), GlitchData => C440DBGSYSTEMCONTROL5_GlitchData, OutSignalName => "C440DBGSYSTEMCONTROL(5)", OutTemp => C440DBGSYSTEMCONTROL_OUT(5), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440DBGSYSTEMCONTROL(6), GlitchData => C440DBGSYSTEMCONTROL6_GlitchData, OutSignalName => "C440DBGSYSTEMCONTROL(6)", OutTemp => C440DBGSYSTEMCONTROL_OUT(6), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440DBGSYSTEMCONTROL(7), GlitchData => C440DBGSYSTEMCONTROL7_GlitchData, OutSignalName => "C440DBGSYSTEMCONTROL(7)", OutTemp => C440DBGSYSTEMCONTROL_OUT(7), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440JTGTDO, GlitchData => C440JTGTDO_GlitchData, OutSignalName => "C440JTGTDO", OutTemp => C440JTGTDO_OUT, Paths => (0 => (JTGC440TCK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440JTGTDOEN, GlitchData => C440JTGTDOEN_GlitchData, OutSignalName => "C440JTGTDOEN", OutTemp => C440JTGTDOEN_OUT, Paths => (0 => (JTGC440TCK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440MACHINECHECK, GlitchData => C440MACHINECHECK_GlitchData, OutSignalName => "C440MACHINECHECK", OutTemp => C440MACHINECHECK_OUT, Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440RSTCHIPRESETREQ, GlitchData => C440RSTCHIPRESETREQ_GlitchData, OutSignalName => "C440RSTCHIPRESETREQ", OutTemp => C440RSTCHIPRESETREQ_OUT, Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440RSTCORERESETREQ, GlitchData => C440RSTCORERESETREQ_GlitchData, OutSignalName => "C440RSTCORERESETREQ", OutTemp => C440RSTCORERESETREQ_OUT, Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440RSTSYSTEMRESETREQ, GlitchData => C440RSTSYSTEMRESETREQ_GlitchData, OutSignalName => "C440RSTSYSTEMRESETREQ", OutTemp => C440RSTSYSTEMRESETREQ_OUT, Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCBRANCHSTATUS(0), GlitchData => C440TRCBRANCHSTATUS0_GlitchData, OutSignalName => "C440TRCBRANCHSTATUS(0)", OutTemp => C440TRCBRANCHSTATUS_OUT(0), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCBRANCHSTATUS(1), GlitchData => C440TRCBRANCHSTATUS1_GlitchData, OutSignalName => "C440TRCBRANCHSTATUS(1)", OutTemp => C440TRCBRANCHSTATUS_OUT(1), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCBRANCHSTATUS(2), GlitchData => C440TRCBRANCHSTATUS2_GlitchData, OutSignalName => "C440TRCBRANCHSTATUS(2)", OutTemp => C440TRCBRANCHSTATUS_OUT(2), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCCYCLE, GlitchData => C440TRCCYCLE_GlitchData, OutSignalName => "C440TRCCYCLE", OutTemp => C440TRCCYCLE_OUT, Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCEXECUTIONSTATUS(0), GlitchData => C440TRCEXECUTIONSTATUS0_GlitchData, OutSignalName => "C440TRCEXECUTIONSTATUS(0)", OutTemp => C440TRCEXECUTIONSTATUS_OUT(0), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCEXECUTIONSTATUS(1), GlitchData => C440TRCEXECUTIONSTATUS1_GlitchData, OutSignalName => "C440TRCEXECUTIONSTATUS(1)", OutTemp => C440TRCEXECUTIONSTATUS_OUT(1), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCEXECUTIONSTATUS(2), GlitchData => C440TRCEXECUTIONSTATUS2_GlitchData, OutSignalName => "C440TRCEXECUTIONSTATUS(2)", OutTemp => C440TRCEXECUTIONSTATUS_OUT(2), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCEXECUTIONSTATUS(3), GlitchData => C440TRCEXECUTIONSTATUS3_GlitchData, OutSignalName => "C440TRCEXECUTIONSTATUS(3)", OutTemp => C440TRCEXECUTIONSTATUS_OUT(3), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCEXECUTIONSTATUS(4), GlitchData => C440TRCEXECUTIONSTATUS4_GlitchData, OutSignalName => "C440TRCEXECUTIONSTATUS(4)", OutTemp => C440TRCEXECUTIONSTATUS_OUT(4), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRACESTATUS(0), GlitchData => C440TRCTRACESTATUS0_GlitchData, OutSignalName => "C440TRCTRACESTATUS(0)", OutTemp => C440TRCTRACESTATUS_OUT(0), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRACESTATUS(1), GlitchData => C440TRCTRACESTATUS1_GlitchData, OutSignalName => "C440TRCTRACESTATUS(1)", OutTemp => C440TRCTRACESTATUS_OUT(1), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRACESTATUS(2), GlitchData => C440TRCTRACESTATUS2_GlitchData, OutSignalName => "C440TRCTRACESTATUS(2)", OutTemp => C440TRCTRACESTATUS_OUT(2), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRACESTATUS(3), GlitchData => C440TRCTRACESTATUS3_GlitchData, OutSignalName => "C440TRCTRACESTATUS(3)", OutTemp => C440TRCTRACESTATUS_OUT(3), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRACESTATUS(4), GlitchData => C440TRCTRACESTATUS4_GlitchData, OutSignalName => "C440TRCTRACESTATUS(4)", OutTemp => C440TRCTRACESTATUS_OUT(4), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRACESTATUS(5), GlitchData => C440TRCTRACESTATUS5_GlitchData, OutSignalName => "C440TRCTRACESTATUS(5)", OutTemp => C440TRCTRACESTATUS_OUT(5), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRACESTATUS(6), GlitchData => C440TRCTRACESTATUS6_GlitchData, OutSignalName => "C440TRCTRACESTATUS(6)", OutTemp => C440TRCTRACESTATUS_OUT(6), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTOUT, GlitchData => C440TRCTRIGGEREVENTOUT_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTOUT", OutTemp => C440TRCTRIGGEREVENTOUT_OUT, Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(0), GlitchData => C440TRCTRIGGEREVENTTYPE0_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(0)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(0), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(1), GlitchData => C440TRCTRIGGEREVENTTYPE1_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(1)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(1), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(2), GlitchData => C440TRCTRIGGEREVENTTYPE2_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(2)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(2), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(3), GlitchData => C440TRCTRIGGEREVENTTYPE3_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(3)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(3), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(4), GlitchData => C440TRCTRIGGEREVENTTYPE4_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(4)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(4), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(5), GlitchData => C440TRCTRIGGEREVENTTYPE5_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(5)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(5), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(6), GlitchData => C440TRCTRIGGEREVENTTYPE6_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(6)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(6), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(7), GlitchData => C440TRCTRIGGEREVENTTYPE7_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(7)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(7), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(8), GlitchData => C440TRCTRIGGEREVENTTYPE8_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(8)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(8), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(9), GlitchData => C440TRCTRIGGEREVENTTYPE9_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(9)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(9), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(10), GlitchData => C440TRCTRIGGEREVENTTYPE10_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(10)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(10), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(11), GlitchData => C440TRCTRIGGEREVENTTYPE11_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(11)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(11), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(12), GlitchData => C440TRCTRIGGEREVENTTYPE12_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(12)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(12), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => C440TRCTRIGGEREVENTTYPE(13), GlitchData => C440TRCTRIGGEREVENTTYPE13_GlitchData, OutSignalName => "C440TRCTRIGGEREVENTTYPE(13)", OutTemp => C440TRCTRIGGEREVENTTYPE_OUT(13), Paths => (0 => (CPMC440CLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(0), GlitchData => MIMCADDRESS0_GlitchData, OutSignalName => "MIMCADDRESS(0)", OutTemp => MIMCADDRESS_OUT(0), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(1), GlitchData => MIMCADDRESS1_GlitchData, OutSignalName => "MIMCADDRESS(1)", OutTemp => MIMCADDRESS_OUT(1), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(2), GlitchData => MIMCADDRESS2_GlitchData, OutSignalName => "MIMCADDRESS(2)", OutTemp => MIMCADDRESS_OUT(2), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(3), GlitchData => MIMCADDRESS3_GlitchData, OutSignalName => "MIMCADDRESS(3)", OutTemp => MIMCADDRESS_OUT(3), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(4), GlitchData => MIMCADDRESS4_GlitchData, OutSignalName => "MIMCADDRESS(4)", OutTemp => MIMCADDRESS_OUT(4), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(5), GlitchData => MIMCADDRESS5_GlitchData, OutSignalName => "MIMCADDRESS(5)", OutTemp => MIMCADDRESS_OUT(5), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(6), GlitchData => MIMCADDRESS6_GlitchData, OutSignalName => "MIMCADDRESS(6)", OutTemp => MIMCADDRESS_OUT(6), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(7), GlitchData => MIMCADDRESS7_GlitchData, OutSignalName => "MIMCADDRESS(7)", OutTemp => MIMCADDRESS_OUT(7), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(8), GlitchData => MIMCADDRESS8_GlitchData, OutSignalName => "MIMCADDRESS(8)", OutTemp => MIMCADDRESS_OUT(8), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(9), GlitchData => MIMCADDRESS9_GlitchData, OutSignalName => "MIMCADDRESS(9)", OutTemp => MIMCADDRESS_OUT(9), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(10), GlitchData => MIMCADDRESS10_GlitchData, OutSignalName => "MIMCADDRESS(10)", OutTemp => MIMCADDRESS_OUT(10), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(11), GlitchData => MIMCADDRESS11_GlitchData, OutSignalName => "MIMCADDRESS(11)", OutTemp => MIMCADDRESS_OUT(11), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(12), GlitchData => MIMCADDRESS12_GlitchData, OutSignalName => "MIMCADDRESS(12)", OutTemp => MIMCADDRESS_OUT(12), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(13), GlitchData => MIMCADDRESS13_GlitchData, OutSignalName => "MIMCADDRESS(13)", OutTemp => MIMCADDRESS_OUT(13), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(14), GlitchData => MIMCADDRESS14_GlitchData, OutSignalName => "MIMCADDRESS(14)", OutTemp => MIMCADDRESS_OUT(14), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(15), GlitchData => MIMCADDRESS15_GlitchData, OutSignalName => "MIMCADDRESS(15)", OutTemp => MIMCADDRESS_OUT(15), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(16), GlitchData => MIMCADDRESS16_GlitchData, OutSignalName => "MIMCADDRESS(16)", OutTemp => MIMCADDRESS_OUT(16), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(17), GlitchData => MIMCADDRESS17_GlitchData, OutSignalName => "MIMCADDRESS(17)", OutTemp => MIMCADDRESS_OUT(17), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(18), GlitchData => MIMCADDRESS18_GlitchData, OutSignalName => "MIMCADDRESS(18)", OutTemp => MIMCADDRESS_OUT(18), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(19), GlitchData => MIMCADDRESS19_GlitchData, OutSignalName => "MIMCADDRESS(19)", OutTemp => MIMCADDRESS_OUT(19), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(20), GlitchData => MIMCADDRESS20_GlitchData, OutSignalName => "MIMCADDRESS(20)", OutTemp => MIMCADDRESS_OUT(20), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(21), GlitchData => MIMCADDRESS21_GlitchData, OutSignalName => "MIMCADDRESS(21)", OutTemp => MIMCADDRESS_OUT(21), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(22), GlitchData => MIMCADDRESS22_GlitchData, OutSignalName => "MIMCADDRESS(22)", OutTemp => MIMCADDRESS_OUT(22), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(23), GlitchData => MIMCADDRESS23_GlitchData, OutSignalName => "MIMCADDRESS(23)", OutTemp => MIMCADDRESS_OUT(23), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(24), GlitchData => MIMCADDRESS24_GlitchData, OutSignalName => "MIMCADDRESS(24)", OutTemp => MIMCADDRESS_OUT(24), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(25), GlitchData => MIMCADDRESS25_GlitchData, OutSignalName => "MIMCADDRESS(25)", OutTemp => MIMCADDRESS_OUT(25), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(26), GlitchData => MIMCADDRESS26_GlitchData, OutSignalName => "MIMCADDRESS(26)", OutTemp => MIMCADDRESS_OUT(26), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(27), GlitchData => MIMCADDRESS27_GlitchData, OutSignalName => "MIMCADDRESS(27)", OutTemp => MIMCADDRESS_OUT(27), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(28), GlitchData => MIMCADDRESS28_GlitchData, OutSignalName => "MIMCADDRESS(28)", OutTemp => MIMCADDRESS_OUT(28), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(29), GlitchData => MIMCADDRESS29_GlitchData, OutSignalName => "MIMCADDRESS(29)", OutTemp => MIMCADDRESS_OUT(29), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(30), GlitchData => MIMCADDRESS30_GlitchData, OutSignalName => "MIMCADDRESS(30)", OutTemp => MIMCADDRESS_OUT(30), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(31), GlitchData => MIMCADDRESS31_GlitchData, OutSignalName => "MIMCADDRESS(31)", OutTemp => MIMCADDRESS_OUT(31), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(32), GlitchData => MIMCADDRESS32_GlitchData, OutSignalName => "MIMCADDRESS(32)", OutTemp => MIMCADDRESS_OUT(32), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(33), GlitchData => MIMCADDRESS33_GlitchData, OutSignalName => "MIMCADDRESS(33)", OutTemp => MIMCADDRESS_OUT(33), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(34), GlitchData => MIMCADDRESS34_GlitchData, OutSignalName => "MIMCADDRESS(34)", OutTemp => MIMCADDRESS_OUT(34), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESS(35), GlitchData => MIMCADDRESS35_GlitchData, OutSignalName => "MIMCADDRESS(35)", OutTemp => MIMCADDRESS_OUT(35), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCADDRESSVALID, GlitchData => MIMCADDRESSVALID_GlitchData, OutSignalName => "MIMCADDRESSVALID", OutTemp => MIMCADDRESSVALID_OUT, Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBANKCONFLICT, GlitchData => MIMCBANKCONFLICT_GlitchData, OutSignalName => "MIMCBANKCONFLICT", OutTemp => MIMCBANKCONFLICT_OUT, Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(0), GlitchData => MIMCBYTEENABLE0_GlitchData, OutSignalName => "MIMCBYTEENABLE(0)", OutTemp => MIMCBYTEENABLE_OUT(0), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(1), GlitchData => MIMCBYTEENABLE1_GlitchData, OutSignalName => "MIMCBYTEENABLE(1)", OutTemp => MIMCBYTEENABLE_OUT(1), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(2), GlitchData => MIMCBYTEENABLE2_GlitchData, OutSignalName => "MIMCBYTEENABLE(2)", OutTemp => MIMCBYTEENABLE_OUT(2), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(3), GlitchData => MIMCBYTEENABLE3_GlitchData, OutSignalName => "MIMCBYTEENABLE(3)", OutTemp => MIMCBYTEENABLE_OUT(3), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(4), GlitchData => MIMCBYTEENABLE4_GlitchData, OutSignalName => "MIMCBYTEENABLE(4)", OutTemp => MIMCBYTEENABLE_OUT(4), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(5), GlitchData => MIMCBYTEENABLE5_GlitchData, OutSignalName => "MIMCBYTEENABLE(5)", OutTemp => MIMCBYTEENABLE_OUT(5), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(6), GlitchData => MIMCBYTEENABLE6_GlitchData, OutSignalName => "MIMCBYTEENABLE(6)", OutTemp => MIMCBYTEENABLE_OUT(6), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(7), GlitchData => MIMCBYTEENABLE7_GlitchData, OutSignalName => "MIMCBYTEENABLE(7)", OutTemp => MIMCBYTEENABLE_OUT(7), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(8), GlitchData => MIMCBYTEENABLE8_GlitchData, OutSignalName => "MIMCBYTEENABLE(8)", OutTemp => MIMCBYTEENABLE_OUT(8), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(9), GlitchData => MIMCBYTEENABLE9_GlitchData, OutSignalName => "MIMCBYTEENABLE(9)", OutTemp => MIMCBYTEENABLE_OUT(9), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(10), GlitchData => MIMCBYTEENABLE10_GlitchData, OutSignalName => "MIMCBYTEENABLE(10)", OutTemp => MIMCBYTEENABLE_OUT(10), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(11), GlitchData => MIMCBYTEENABLE11_GlitchData, OutSignalName => "MIMCBYTEENABLE(11)", OutTemp => MIMCBYTEENABLE_OUT(11), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(12), GlitchData => MIMCBYTEENABLE12_GlitchData, OutSignalName => "MIMCBYTEENABLE(12)", OutTemp => MIMCBYTEENABLE_OUT(12), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(13), GlitchData => MIMCBYTEENABLE13_GlitchData, OutSignalName => "MIMCBYTEENABLE(13)", OutTemp => MIMCBYTEENABLE_OUT(13), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(14), GlitchData => MIMCBYTEENABLE14_GlitchData, OutSignalName => "MIMCBYTEENABLE(14)", OutTemp => MIMCBYTEENABLE_OUT(14), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCBYTEENABLE(15), GlitchData => MIMCBYTEENABLE15_GlitchData, OutSignalName => "MIMCBYTEENABLE(15)", OutTemp => MIMCBYTEENABLE_OUT(15), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCREADNOTWRITE, GlitchData => MIMCREADNOTWRITE_GlitchData, OutSignalName => "MIMCREADNOTWRITE", OutTemp => MIMCREADNOTWRITE_OUT, Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCROWCONFLICT, GlitchData => MIMCROWCONFLICT_GlitchData, OutSignalName => "MIMCROWCONFLICT", OutTemp => MIMCROWCONFLICT_OUT, Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(0), GlitchData => MIMCWRITEDATA0_GlitchData, OutSignalName => "MIMCWRITEDATA(0)", OutTemp => MIMCWRITEDATA_OUT(0), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(1), GlitchData => MIMCWRITEDATA1_GlitchData, OutSignalName => "MIMCWRITEDATA(1)", OutTemp => MIMCWRITEDATA_OUT(1), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(2), GlitchData => MIMCWRITEDATA2_GlitchData, OutSignalName => "MIMCWRITEDATA(2)", OutTemp => MIMCWRITEDATA_OUT(2), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(3), GlitchData => MIMCWRITEDATA3_GlitchData, OutSignalName => "MIMCWRITEDATA(3)", OutTemp => MIMCWRITEDATA_OUT(3), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(4), GlitchData => MIMCWRITEDATA4_GlitchData, OutSignalName => "MIMCWRITEDATA(4)", OutTemp => MIMCWRITEDATA_OUT(4), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(5), GlitchData => MIMCWRITEDATA5_GlitchData, OutSignalName => "MIMCWRITEDATA(5)", OutTemp => MIMCWRITEDATA_OUT(5), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(6), GlitchData => MIMCWRITEDATA6_GlitchData, OutSignalName => "MIMCWRITEDATA(6)", OutTemp => MIMCWRITEDATA_OUT(6), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(7), GlitchData => MIMCWRITEDATA7_GlitchData, OutSignalName => "MIMCWRITEDATA(7)", OutTemp => MIMCWRITEDATA_OUT(7), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(8), GlitchData => MIMCWRITEDATA8_GlitchData, OutSignalName => "MIMCWRITEDATA(8)", OutTemp => MIMCWRITEDATA_OUT(8), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(9), GlitchData => MIMCWRITEDATA9_GlitchData, OutSignalName => "MIMCWRITEDATA(9)", OutTemp => MIMCWRITEDATA_OUT(9), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(10), GlitchData => MIMCWRITEDATA10_GlitchData, OutSignalName => "MIMCWRITEDATA(10)", OutTemp => MIMCWRITEDATA_OUT(10), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(11), GlitchData => MIMCWRITEDATA11_GlitchData, OutSignalName => "MIMCWRITEDATA(11)", OutTemp => MIMCWRITEDATA_OUT(11), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(12), GlitchData => MIMCWRITEDATA12_GlitchData, OutSignalName => "MIMCWRITEDATA(12)", OutTemp => MIMCWRITEDATA_OUT(12), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(13), GlitchData => MIMCWRITEDATA13_GlitchData, OutSignalName => "MIMCWRITEDATA(13)", OutTemp => MIMCWRITEDATA_OUT(13), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(14), GlitchData => MIMCWRITEDATA14_GlitchData, OutSignalName => "MIMCWRITEDATA(14)", OutTemp => MIMCWRITEDATA_OUT(14), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(15), GlitchData => MIMCWRITEDATA15_GlitchData, OutSignalName => "MIMCWRITEDATA(15)", OutTemp => MIMCWRITEDATA_OUT(15), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(16), GlitchData => MIMCWRITEDATA16_GlitchData, OutSignalName => "MIMCWRITEDATA(16)", OutTemp => MIMCWRITEDATA_OUT(16), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(17), GlitchData => MIMCWRITEDATA17_GlitchData, OutSignalName => "MIMCWRITEDATA(17)", OutTemp => MIMCWRITEDATA_OUT(17), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(18), GlitchData => MIMCWRITEDATA18_GlitchData, OutSignalName => "MIMCWRITEDATA(18)", OutTemp => MIMCWRITEDATA_OUT(18), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(19), GlitchData => MIMCWRITEDATA19_GlitchData, OutSignalName => "MIMCWRITEDATA(19)", OutTemp => MIMCWRITEDATA_OUT(19), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(20), GlitchData => MIMCWRITEDATA20_GlitchData, OutSignalName => "MIMCWRITEDATA(20)", OutTemp => MIMCWRITEDATA_OUT(20), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(21), GlitchData => MIMCWRITEDATA21_GlitchData, OutSignalName => "MIMCWRITEDATA(21)", OutTemp => MIMCWRITEDATA_OUT(21), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(22), GlitchData => MIMCWRITEDATA22_GlitchData, OutSignalName => "MIMCWRITEDATA(22)", OutTemp => MIMCWRITEDATA_OUT(22), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(23), GlitchData => MIMCWRITEDATA23_GlitchData, OutSignalName => "MIMCWRITEDATA(23)", OutTemp => MIMCWRITEDATA_OUT(23), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(24), GlitchData => MIMCWRITEDATA24_GlitchData, OutSignalName => "MIMCWRITEDATA(24)", OutTemp => MIMCWRITEDATA_OUT(24), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(25), GlitchData => MIMCWRITEDATA25_GlitchData, OutSignalName => "MIMCWRITEDATA(25)", OutTemp => MIMCWRITEDATA_OUT(25), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(26), GlitchData => MIMCWRITEDATA26_GlitchData, OutSignalName => "MIMCWRITEDATA(26)", OutTemp => MIMCWRITEDATA_OUT(26), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(27), GlitchData => MIMCWRITEDATA27_GlitchData, OutSignalName => "MIMCWRITEDATA(27)", OutTemp => MIMCWRITEDATA_OUT(27), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(28), GlitchData => MIMCWRITEDATA28_GlitchData, OutSignalName => "MIMCWRITEDATA(28)", OutTemp => MIMCWRITEDATA_OUT(28), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(29), GlitchData => MIMCWRITEDATA29_GlitchData, OutSignalName => "MIMCWRITEDATA(29)", OutTemp => MIMCWRITEDATA_OUT(29), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(30), GlitchData => MIMCWRITEDATA30_GlitchData, OutSignalName => "MIMCWRITEDATA(30)", OutTemp => MIMCWRITEDATA_OUT(30), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(31), GlitchData => MIMCWRITEDATA31_GlitchData, OutSignalName => "MIMCWRITEDATA(31)", OutTemp => MIMCWRITEDATA_OUT(31), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(32), GlitchData => MIMCWRITEDATA32_GlitchData, OutSignalName => "MIMCWRITEDATA(32)", OutTemp => MIMCWRITEDATA_OUT(32), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(33), GlitchData => MIMCWRITEDATA33_GlitchData, OutSignalName => "MIMCWRITEDATA(33)", OutTemp => MIMCWRITEDATA_OUT(33), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(34), GlitchData => MIMCWRITEDATA34_GlitchData, OutSignalName => "MIMCWRITEDATA(34)", OutTemp => MIMCWRITEDATA_OUT(34), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(35), GlitchData => MIMCWRITEDATA35_GlitchData, OutSignalName => "MIMCWRITEDATA(35)", OutTemp => MIMCWRITEDATA_OUT(35), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(36), GlitchData => MIMCWRITEDATA36_GlitchData, OutSignalName => "MIMCWRITEDATA(36)", OutTemp => MIMCWRITEDATA_OUT(36), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(37), GlitchData => MIMCWRITEDATA37_GlitchData, OutSignalName => "MIMCWRITEDATA(37)", OutTemp => MIMCWRITEDATA_OUT(37), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(38), GlitchData => MIMCWRITEDATA38_GlitchData, OutSignalName => "MIMCWRITEDATA(38)", OutTemp => MIMCWRITEDATA_OUT(38), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(39), GlitchData => MIMCWRITEDATA39_GlitchData, OutSignalName => "MIMCWRITEDATA(39)", OutTemp => MIMCWRITEDATA_OUT(39), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(40), GlitchData => MIMCWRITEDATA40_GlitchData, OutSignalName => "MIMCWRITEDATA(40)", OutTemp => MIMCWRITEDATA_OUT(40), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(41), GlitchData => MIMCWRITEDATA41_GlitchData, OutSignalName => "MIMCWRITEDATA(41)", OutTemp => MIMCWRITEDATA_OUT(41), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(42), GlitchData => MIMCWRITEDATA42_GlitchData, OutSignalName => "MIMCWRITEDATA(42)", OutTemp => MIMCWRITEDATA_OUT(42), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(43), GlitchData => MIMCWRITEDATA43_GlitchData, OutSignalName => "MIMCWRITEDATA(43)", OutTemp => MIMCWRITEDATA_OUT(43), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(44), GlitchData => MIMCWRITEDATA44_GlitchData, OutSignalName => "MIMCWRITEDATA(44)", OutTemp => MIMCWRITEDATA_OUT(44), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(45), GlitchData => MIMCWRITEDATA45_GlitchData, OutSignalName => "MIMCWRITEDATA(45)", OutTemp => MIMCWRITEDATA_OUT(45), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(46), GlitchData => MIMCWRITEDATA46_GlitchData, OutSignalName => "MIMCWRITEDATA(46)", OutTemp => MIMCWRITEDATA_OUT(46), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(47), GlitchData => MIMCWRITEDATA47_GlitchData, OutSignalName => "MIMCWRITEDATA(47)", OutTemp => MIMCWRITEDATA_OUT(47), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(48), GlitchData => MIMCWRITEDATA48_GlitchData, OutSignalName => "MIMCWRITEDATA(48)", OutTemp => MIMCWRITEDATA_OUT(48), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(49), GlitchData => MIMCWRITEDATA49_GlitchData, OutSignalName => "MIMCWRITEDATA(49)", OutTemp => MIMCWRITEDATA_OUT(49), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(50), GlitchData => MIMCWRITEDATA50_GlitchData, OutSignalName => "MIMCWRITEDATA(50)", OutTemp => MIMCWRITEDATA_OUT(50), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(51), GlitchData => MIMCWRITEDATA51_GlitchData, OutSignalName => "MIMCWRITEDATA(51)", OutTemp => MIMCWRITEDATA_OUT(51), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(52), GlitchData => MIMCWRITEDATA52_GlitchData, OutSignalName => "MIMCWRITEDATA(52)", OutTemp => MIMCWRITEDATA_OUT(52), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(53), GlitchData => MIMCWRITEDATA53_GlitchData, OutSignalName => "MIMCWRITEDATA(53)", OutTemp => MIMCWRITEDATA_OUT(53), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(54), GlitchData => MIMCWRITEDATA54_GlitchData, OutSignalName => "MIMCWRITEDATA(54)", OutTemp => MIMCWRITEDATA_OUT(54), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(55), GlitchData => MIMCWRITEDATA55_GlitchData, OutSignalName => "MIMCWRITEDATA(55)", OutTemp => MIMCWRITEDATA_OUT(55), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(56), GlitchData => MIMCWRITEDATA56_GlitchData, OutSignalName => "MIMCWRITEDATA(56)", OutTemp => MIMCWRITEDATA_OUT(56), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(57), GlitchData => MIMCWRITEDATA57_GlitchData, OutSignalName => "MIMCWRITEDATA(57)", OutTemp => MIMCWRITEDATA_OUT(57), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(58), GlitchData => MIMCWRITEDATA58_GlitchData, OutSignalName => "MIMCWRITEDATA(58)", OutTemp => MIMCWRITEDATA_OUT(58), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(59), GlitchData => MIMCWRITEDATA59_GlitchData, OutSignalName => "MIMCWRITEDATA(59)", OutTemp => MIMCWRITEDATA_OUT(59), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(60), GlitchData => MIMCWRITEDATA60_GlitchData, OutSignalName => "MIMCWRITEDATA(60)", OutTemp => MIMCWRITEDATA_OUT(60), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(61), GlitchData => MIMCWRITEDATA61_GlitchData, OutSignalName => "MIMCWRITEDATA(61)", OutTemp => MIMCWRITEDATA_OUT(61), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(62), GlitchData => MIMCWRITEDATA62_GlitchData, OutSignalName => "MIMCWRITEDATA(62)", OutTemp => MIMCWRITEDATA_OUT(62), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(63), GlitchData => MIMCWRITEDATA63_GlitchData, OutSignalName => "MIMCWRITEDATA(63)", OutTemp => MIMCWRITEDATA_OUT(63), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(64), GlitchData => MIMCWRITEDATA64_GlitchData, OutSignalName => "MIMCWRITEDATA(64)", OutTemp => MIMCWRITEDATA_OUT(64), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(65), GlitchData => MIMCWRITEDATA65_GlitchData, OutSignalName => "MIMCWRITEDATA(65)", OutTemp => MIMCWRITEDATA_OUT(65), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(66), GlitchData => MIMCWRITEDATA66_GlitchData, OutSignalName => "MIMCWRITEDATA(66)", OutTemp => MIMCWRITEDATA_OUT(66), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(67), GlitchData => MIMCWRITEDATA67_GlitchData, OutSignalName => "MIMCWRITEDATA(67)", OutTemp => MIMCWRITEDATA_OUT(67), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(68), GlitchData => MIMCWRITEDATA68_GlitchData, OutSignalName => "MIMCWRITEDATA(68)", OutTemp => MIMCWRITEDATA_OUT(68), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(69), GlitchData => MIMCWRITEDATA69_GlitchData, OutSignalName => "MIMCWRITEDATA(69)", OutTemp => MIMCWRITEDATA_OUT(69), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(70), GlitchData => MIMCWRITEDATA70_GlitchData, OutSignalName => "MIMCWRITEDATA(70)", OutTemp => MIMCWRITEDATA_OUT(70), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(71), GlitchData => MIMCWRITEDATA71_GlitchData, OutSignalName => "MIMCWRITEDATA(71)", OutTemp => MIMCWRITEDATA_OUT(71), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(72), GlitchData => MIMCWRITEDATA72_GlitchData, OutSignalName => "MIMCWRITEDATA(72)", OutTemp => MIMCWRITEDATA_OUT(72), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(73), GlitchData => MIMCWRITEDATA73_GlitchData, OutSignalName => "MIMCWRITEDATA(73)", OutTemp => MIMCWRITEDATA_OUT(73), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(74), GlitchData => MIMCWRITEDATA74_GlitchData, OutSignalName => "MIMCWRITEDATA(74)", OutTemp => MIMCWRITEDATA_OUT(74), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(75), GlitchData => MIMCWRITEDATA75_GlitchData, OutSignalName => "MIMCWRITEDATA(75)", OutTemp => MIMCWRITEDATA_OUT(75), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(76), GlitchData => MIMCWRITEDATA76_GlitchData, OutSignalName => "MIMCWRITEDATA(76)", OutTemp => MIMCWRITEDATA_OUT(76), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(77), GlitchData => MIMCWRITEDATA77_GlitchData, OutSignalName => "MIMCWRITEDATA(77)", OutTemp => MIMCWRITEDATA_OUT(77), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(78), GlitchData => MIMCWRITEDATA78_GlitchData, OutSignalName => "MIMCWRITEDATA(78)", OutTemp => MIMCWRITEDATA_OUT(78), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(79), GlitchData => MIMCWRITEDATA79_GlitchData, OutSignalName => "MIMCWRITEDATA(79)", OutTemp => MIMCWRITEDATA_OUT(79), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(80), GlitchData => MIMCWRITEDATA80_GlitchData, OutSignalName => "MIMCWRITEDATA(80)", OutTemp => MIMCWRITEDATA_OUT(80), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(81), GlitchData => MIMCWRITEDATA81_GlitchData, OutSignalName => "MIMCWRITEDATA(81)", OutTemp => MIMCWRITEDATA_OUT(81), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(82), GlitchData => MIMCWRITEDATA82_GlitchData, OutSignalName => "MIMCWRITEDATA(82)", OutTemp => MIMCWRITEDATA_OUT(82), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(83), GlitchData => MIMCWRITEDATA83_GlitchData, OutSignalName => "MIMCWRITEDATA(83)", OutTemp => MIMCWRITEDATA_OUT(83), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(84), GlitchData => MIMCWRITEDATA84_GlitchData, OutSignalName => "MIMCWRITEDATA(84)", OutTemp => MIMCWRITEDATA_OUT(84), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(85), GlitchData => MIMCWRITEDATA85_GlitchData, OutSignalName => "MIMCWRITEDATA(85)", OutTemp => MIMCWRITEDATA_OUT(85), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(86), GlitchData => MIMCWRITEDATA86_GlitchData, OutSignalName => "MIMCWRITEDATA(86)", OutTemp => MIMCWRITEDATA_OUT(86), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(87), GlitchData => MIMCWRITEDATA87_GlitchData, OutSignalName => "MIMCWRITEDATA(87)", OutTemp => MIMCWRITEDATA_OUT(87), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(88), GlitchData => MIMCWRITEDATA88_GlitchData, OutSignalName => "MIMCWRITEDATA(88)", OutTemp => MIMCWRITEDATA_OUT(88), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(89), GlitchData => MIMCWRITEDATA89_GlitchData, OutSignalName => "MIMCWRITEDATA(89)", OutTemp => MIMCWRITEDATA_OUT(89), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(90), GlitchData => MIMCWRITEDATA90_GlitchData, OutSignalName => "MIMCWRITEDATA(90)", OutTemp => MIMCWRITEDATA_OUT(90), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(91), GlitchData => MIMCWRITEDATA91_GlitchData, OutSignalName => "MIMCWRITEDATA(91)", OutTemp => MIMCWRITEDATA_OUT(91), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(92), GlitchData => MIMCWRITEDATA92_GlitchData, OutSignalName => "MIMCWRITEDATA(92)", OutTemp => MIMCWRITEDATA_OUT(92), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(93), GlitchData => MIMCWRITEDATA93_GlitchData, OutSignalName => "MIMCWRITEDATA(93)", OutTemp => MIMCWRITEDATA_OUT(93), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(94), GlitchData => MIMCWRITEDATA94_GlitchData, OutSignalName => "MIMCWRITEDATA(94)", OutTemp => MIMCWRITEDATA_OUT(94), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(95), GlitchData => MIMCWRITEDATA95_GlitchData, OutSignalName => "MIMCWRITEDATA(95)", OutTemp => MIMCWRITEDATA_OUT(95), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(96), GlitchData => MIMCWRITEDATA96_GlitchData, OutSignalName => "MIMCWRITEDATA(96)", OutTemp => MIMCWRITEDATA_OUT(96), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(97), GlitchData => MIMCWRITEDATA97_GlitchData, OutSignalName => "MIMCWRITEDATA(97)", OutTemp => MIMCWRITEDATA_OUT(97), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(98), GlitchData => MIMCWRITEDATA98_GlitchData, OutSignalName => "MIMCWRITEDATA(98)", OutTemp => MIMCWRITEDATA_OUT(98), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(99), GlitchData => MIMCWRITEDATA99_GlitchData, OutSignalName => "MIMCWRITEDATA(99)", OutTemp => MIMCWRITEDATA_OUT(99), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(100), GlitchData => MIMCWRITEDATA100_GlitchData, OutSignalName => "MIMCWRITEDATA(100)", OutTemp => MIMCWRITEDATA_OUT(100), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(101), GlitchData => MIMCWRITEDATA101_GlitchData, OutSignalName => "MIMCWRITEDATA(101)", OutTemp => MIMCWRITEDATA_OUT(101), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(102), GlitchData => MIMCWRITEDATA102_GlitchData, OutSignalName => "MIMCWRITEDATA(102)", OutTemp => MIMCWRITEDATA_OUT(102), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(103), GlitchData => MIMCWRITEDATA103_GlitchData, OutSignalName => "MIMCWRITEDATA(103)", OutTemp => MIMCWRITEDATA_OUT(103), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(104), GlitchData => MIMCWRITEDATA104_GlitchData, OutSignalName => "MIMCWRITEDATA(104)", OutTemp => MIMCWRITEDATA_OUT(104), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(105), GlitchData => MIMCWRITEDATA105_GlitchData, OutSignalName => "MIMCWRITEDATA(105)", OutTemp => MIMCWRITEDATA_OUT(105), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(106), GlitchData => MIMCWRITEDATA106_GlitchData, OutSignalName => "MIMCWRITEDATA(106)", OutTemp => MIMCWRITEDATA_OUT(106), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(107), GlitchData => MIMCWRITEDATA107_GlitchData, OutSignalName => "MIMCWRITEDATA(107)", OutTemp => MIMCWRITEDATA_OUT(107), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(108), GlitchData => MIMCWRITEDATA108_GlitchData, OutSignalName => "MIMCWRITEDATA(108)", OutTemp => MIMCWRITEDATA_OUT(108), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(109), GlitchData => MIMCWRITEDATA109_GlitchData, OutSignalName => "MIMCWRITEDATA(109)", OutTemp => MIMCWRITEDATA_OUT(109), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(110), GlitchData => MIMCWRITEDATA110_GlitchData, OutSignalName => "MIMCWRITEDATA(110)", OutTemp => MIMCWRITEDATA_OUT(110), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(111), GlitchData => MIMCWRITEDATA111_GlitchData, OutSignalName => "MIMCWRITEDATA(111)", OutTemp => MIMCWRITEDATA_OUT(111), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(112), GlitchData => MIMCWRITEDATA112_GlitchData, OutSignalName => "MIMCWRITEDATA(112)", OutTemp => MIMCWRITEDATA_OUT(112), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(113), GlitchData => MIMCWRITEDATA113_GlitchData, OutSignalName => "MIMCWRITEDATA(113)", OutTemp => MIMCWRITEDATA_OUT(113), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(114), GlitchData => MIMCWRITEDATA114_GlitchData, OutSignalName => "MIMCWRITEDATA(114)", OutTemp => MIMCWRITEDATA_OUT(114), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(115), GlitchData => MIMCWRITEDATA115_GlitchData, OutSignalName => "MIMCWRITEDATA(115)", OutTemp => MIMCWRITEDATA_OUT(115), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(116), GlitchData => MIMCWRITEDATA116_GlitchData, OutSignalName => "MIMCWRITEDATA(116)", OutTemp => MIMCWRITEDATA_OUT(116), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(117), GlitchData => MIMCWRITEDATA117_GlitchData, OutSignalName => "MIMCWRITEDATA(117)", OutTemp => MIMCWRITEDATA_OUT(117), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(118), GlitchData => MIMCWRITEDATA118_GlitchData, OutSignalName => "MIMCWRITEDATA(118)", OutTemp => MIMCWRITEDATA_OUT(118), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(119), GlitchData => MIMCWRITEDATA119_GlitchData, OutSignalName => "MIMCWRITEDATA(119)", OutTemp => MIMCWRITEDATA_OUT(119), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(120), GlitchData => MIMCWRITEDATA120_GlitchData, OutSignalName => "MIMCWRITEDATA(120)", OutTemp => MIMCWRITEDATA_OUT(120), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(121), GlitchData => MIMCWRITEDATA121_GlitchData, OutSignalName => "MIMCWRITEDATA(121)", OutTemp => MIMCWRITEDATA_OUT(121), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(122), GlitchData => MIMCWRITEDATA122_GlitchData, OutSignalName => "MIMCWRITEDATA(122)", OutTemp => MIMCWRITEDATA_OUT(122), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(123), GlitchData => MIMCWRITEDATA123_GlitchData, OutSignalName => "MIMCWRITEDATA(123)", OutTemp => MIMCWRITEDATA_OUT(123), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(124), GlitchData => MIMCWRITEDATA124_GlitchData, OutSignalName => "MIMCWRITEDATA(124)", OutTemp => MIMCWRITEDATA_OUT(124), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(125), GlitchData => MIMCWRITEDATA125_GlitchData, OutSignalName => "MIMCWRITEDATA(125)", OutTemp => MIMCWRITEDATA_OUT(125), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(126), GlitchData => MIMCWRITEDATA126_GlitchData, OutSignalName => "MIMCWRITEDATA(126)", OutTemp => MIMCWRITEDATA_OUT(126), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATA(127), GlitchData => MIMCWRITEDATA127_GlitchData, OutSignalName => "MIMCWRITEDATA(127)", OutTemp => MIMCWRITEDATA_OUT(127), Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => MIMCWRITEDATAVALID, GlitchData => MIMCWRITEDATAVALID_GlitchData, OutSignalName => "MIMCWRITEDATAVALID", OutTemp => MIMCWRITEDATAVALID_OUT, Paths => (0 => (CPMMCCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCCPMINTERCONNECTBUSY, GlitchData => PPCCPMINTERCONNECTBUSY_GlitchData, OutSignalName => "PPCCPMINTERCONNECTBUSY", OutTemp => PPCCPMINTERCONNECTBUSY_OUT, Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRACK, GlitchData => PPCDSDCRACK_GlitchData, OutSignalName => "PPCDSDCRACK", OutTemp => PPCDSDCRACK_OUT, Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRTIMEOUTWAIT, GlitchData => PPCDSDCRTIMEOUTWAIT_GlitchData, OutSignalName => "PPCDSDCRTIMEOUTWAIT", OutTemp => PPCDSDCRTIMEOUTWAIT_OUT, Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(0), GlitchData => PPCDSDCRDBUSIN0_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(0)", OutTemp => PPCDSDCRDBUSIN_OUT(0), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(1), GlitchData => PPCDSDCRDBUSIN1_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(1)", OutTemp => PPCDSDCRDBUSIN_OUT(1), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(2), GlitchData => PPCDSDCRDBUSIN2_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(2)", OutTemp => PPCDSDCRDBUSIN_OUT(2), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(3), GlitchData => PPCDSDCRDBUSIN3_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(3)", OutTemp => PPCDSDCRDBUSIN_OUT(3), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(4), GlitchData => PPCDSDCRDBUSIN4_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(4)", OutTemp => PPCDSDCRDBUSIN_OUT(4), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(5), GlitchData => PPCDSDCRDBUSIN5_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(5)", OutTemp => PPCDSDCRDBUSIN_OUT(5), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(6), GlitchData => PPCDSDCRDBUSIN6_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(6)", OutTemp => PPCDSDCRDBUSIN_OUT(6), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(7), GlitchData => PPCDSDCRDBUSIN7_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(7)", OutTemp => PPCDSDCRDBUSIN_OUT(7), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(8), GlitchData => PPCDSDCRDBUSIN8_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(8)", OutTemp => PPCDSDCRDBUSIN_OUT(8), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(9), GlitchData => PPCDSDCRDBUSIN9_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(9)", OutTemp => PPCDSDCRDBUSIN_OUT(9), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(10), GlitchData => PPCDSDCRDBUSIN10_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(10)", OutTemp => PPCDSDCRDBUSIN_OUT(10), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(11), GlitchData => PPCDSDCRDBUSIN11_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(11)", OutTemp => PPCDSDCRDBUSIN_OUT(11), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(12), GlitchData => PPCDSDCRDBUSIN12_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(12)", OutTemp => PPCDSDCRDBUSIN_OUT(12), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(13), GlitchData => PPCDSDCRDBUSIN13_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(13)", OutTemp => PPCDSDCRDBUSIN_OUT(13), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(14), GlitchData => PPCDSDCRDBUSIN14_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(14)", OutTemp => PPCDSDCRDBUSIN_OUT(14), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(15), GlitchData => PPCDSDCRDBUSIN15_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(15)", OutTemp => PPCDSDCRDBUSIN_OUT(15), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(16), GlitchData => PPCDSDCRDBUSIN16_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(16)", OutTemp => PPCDSDCRDBUSIN_OUT(16), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(17), GlitchData => PPCDSDCRDBUSIN17_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(17)", OutTemp => PPCDSDCRDBUSIN_OUT(17), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(18), GlitchData => PPCDSDCRDBUSIN18_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(18)", OutTemp => PPCDSDCRDBUSIN_OUT(18), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(19), GlitchData => PPCDSDCRDBUSIN19_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(19)", OutTemp => PPCDSDCRDBUSIN_OUT(19), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(20), GlitchData => PPCDSDCRDBUSIN20_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(20)", OutTemp => PPCDSDCRDBUSIN_OUT(20), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(21), GlitchData => PPCDSDCRDBUSIN21_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(21)", OutTemp => PPCDSDCRDBUSIN_OUT(21), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(22), GlitchData => PPCDSDCRDBUSIN22_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(22)", OutTemp => PPCDSDCRDBUSIN_OUT(22), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(23), GlitchData => PPCDSDCRDBUSIN23_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(23)", OutTemp => PPCDSDCRDBUSIN_OUT(23), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(24), GlitchData => PPCDSDCRDBUSIN24_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(24)", OutTemp => PPCDSDCRDBUSIN_OUT(24), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(25), GlitchData => PPCDSDCRDBUSIN25_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(25)", OutTemp => PPCDSDCRDBUSIN_OUT(25), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(26), GlitchData => PPCDSDCRDBUSIN26_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(26)", OutTemp => PPCDSDCRDBUSIN_OUT(26), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(27), GlitchData => PPCDSDCRDBUSIN27_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(27)", OutTemp => PPCDSDCRDBUSIN_OUT(27), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(28), GlitchData => PPCDSDCRDBUSIN28_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(28)", OutTemp => PPCDSDCRDBUSIN_OUT(28), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(29), GlitchData => PPCDSDCRDBUSIN29_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(29)", OutTemp => PPCDSDCRDBUSIN_OUT(29), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(30), GlitchData => PPCDSDCRDBUSIN30_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(30)", OutTemp => PPCDSDCRDBUSIN_OUT(30), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCDSDCRDBUSIN(31), GlitchData => PPCDSDCRDBUSIN31_GlitchData, OutSignalName => "PPCDSDCRDBUSIN(31)", OutTemp => PPCDSDCRDBUSIN_OUT(31), Paths => (0 => (CPMDCRCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); VitalPathDelay01 ( OutSignal => PPCEICINTERCONNECTIRQ, GlitchData => PPCEICINTERCONNECTIRQ_GlitchData, OutSignalName => "PPCEICINTERCONNECTIRQ", OutTemp => PPCEICINTERCONNECTIRQ_OUT, Paths => (0 => (CPMINTERCONNECTCLK_ipd'last_event, PATH_DELAY,TRUE)), Mode => VitalTransport, DefaultDelay => PATH_DELAY, Xon => false, MsgOn => false, MsgSeverity => WARNING ); wait on APUFCMDECFPUOP_out, APUFCMDECLDSTXFERSIZE_out, APUFCMDECLOAD_out, APUFCMDECNONAUTON_out, APUFCMDECSTORE_out, APUFCMDECUDIVALID_out, APUFCMDECUDI_out, APUFCMENDIAN_out, APUFCMFLUSH_out, APUFCMINSTRUCTION_out, APUFCMINSTRVALID_out, APUFCMLOADBYTEADDR_out, APUFCMLOADDATA_out, APUFCMLOADDVALID_out, APUFCMMSRFE0_out, APUFCMMSRFE1_out, APUFCMNEXTINSTRREADY_out, APUFCMOPERANDVALID_out, APUFCMRADATA_out, APUFCMRBDATA_out, APUFCMWRITEBACKOK_out, C440CPMCORESLEEPREQ_out, C440CPMDECIRPTREQ_out, C440CPMFITIRPTREQ_out, C440CPMMSRCE_out, C440CPMMSREE_out, C440CPMTIMERRESETREQ_out, C440CPMWDIRPTREQ_out, C440DBGSYSTEMCONTROL_out, C440JTGTDOEN_out, C440JTGTDO_out, C440MACHINECHECK_out, C440RSTCHIPRESETREQ_out, C440RSTCORERESETREQ_out, C440RSTSYSTEMRESETREQ_out, C440TRCBRANCHSTATUS_out, C440TRCCYCLE_out, C440TRCEXECUTIONSTATUS_out, C440TRCTRACESTATUS_out, C440TRCTRIGGEREVENTOUT_out, C440TRCTRIGGEREVENTTYPE_out, DMA0LLRSTENGINEACK_out, DMA0LLRXDSTRDYN_out, DMA0LLTXD_out, DMA0LLTXEOFN_out, DMA0LLTXEOPN_out, DMA0LLTXREM_out, DMA0LLTXSOFN_out, DMA0LLTXSOPN_out, DMA0LLTXSRCRDYN_out, DMA0RXIRQ_out, DMA0TXIRQ_out, DMA1LLRSTENGINEACK_out, DMA1LLRXDSTRDYN_out, DMA1LLTXD_out, DMA1LLTXEOFN_out, DMA1LLTXEOPN_out, DMA1LLTXREM_out, DMA1LLTXSOFN_out, DMA1LLTXSOPN_out, DMA1LLTXSRCRDYN_out, DMA1RXIRQ_out, DMA1TXIRQ_out, DMA2LLRSTENGINEACK_out, DMA2LLRXDSTRDYN_out, DMA2LLTXD_out, DMA2LLTXEOFN_out, DMA2LLTXEOPN_out, DMA2LLTXREM_out, DMA2LLTXSOFN_out, DMA2LLTXSOPN_out, DMA2LLTXSRCRDYN_out, DMA2RXIRQ_out, DMA2TXIRQ_out, DMA3LLRSTENGINEACK_out, DMA3LLRXDSTRDYN_out, DMA3LLTXD_out, DMA3LLTXEOFN_out, DMA3LLTXEOPN_out, DMA3LLTXREM_out, DMA3LLTXSOFN_out, DMA3LLTXSOPN_out, DMA3LLTXSRCRDYN_out, DMA3RXIRQ_out, DMA3TXIRQ_out, MIMCADDRESSVALID_out, MIMCADDRESS_out, MIMCBANKCONFLICT_out, MIMCBYTEENABLE_out, MIMCREADNOTWRITE_out, MIMCROWCONFLICT_out, MIMCWRITEDATAVALID_out, MIMCWRITEDATA_out, PPCCPMINTERCONNECTBUSY_out, PPCDMDCRABUS_out, PPCDMDCRDBUSOUT_out, PPCDMDCRREAD_out, PPCDMDCRUABUS_out, PPCDMDCRWRITE_out, PPCDSDCRACK_out, PPCDSDCRDBUSIN_out, PPCDSDCRTIMEOUTWAIT_out, PPCEICINTERCONNECTIRQ_out, PPCMPLBABORT_out, PPCMPLBABUS_out, PPCMPLBBE_out, PPCMPLBBUSLOCK_out, PPCMPLBLOCKERR_out, PPCMPLBPRIORITY_out, PPCMPLBRDBURST_out, PPCMPLBREQUEST_out, PPCMPLBRNW_out, PPCMPLBSIZE_out, PPCMPLBTATTRIBUTE_out, PPCMPLBTYPE_out, PPCMPLBUABUS_out, PPCMPLBWRBURST_out, PPCMPLBWRDBUS_out, PPCS0PLBADDRACK_out, PPCS0PLBMBUSY_out, PPCS0PLBMIRQ_out, PPCS0PLBMRDERR_out, PPCS0PLBMWRERR_out, PPCS0PLBRDBTERM_out, PPCS0PLBRDCOMP_out, PPCS0PLBRDDACK_out, PPCS0PLBRDDBUS_out, PPCS0PLBRDWDADDR_out, PPCS0PLBREARBITRATE_out, PPCS0PLBSSIZE_out, PPCS0PLBWAIT_out, PPCS0PLBWRBTERM_out, PPCS0PLBWRCOMP_out, PPCS0PLBWRDACK_out, PPCS1PLBADDRACK_out, PPCS1PLBMBUSY_out, PPCS1PLBMIRQ_out, PPCS1PLBMRDERR_out, PPCS1PLBMWRERR_out, PPCS1PLBRDBTERM_out, PPCS1PLBRDCOMP_out, PPCS1PLBRDDACK_out, PPCS1PLBRDDBUS_out, PPCS1PLBRDWDADDR_out, PPCS1PLBREARBITRATE_out, PPCS1PLBSSIZE_out, PPCS1PLBWAIT_out, PPCS1PLBWRBTERM_out, PPCS1PLBWRCOMP_out, PPCS1PLBWRDACK_out, CPMC440CLKEN_ipd, CPMC440CLK_ipd, CPMC440CORECLOCKINACTIVE_ipd, CPMC440TIMERCLOCK_ipd, CPMDCRCLK_ipd, CPMDMA0LLCLK_ipd, CPMDMA1LLCLK_ipd, CPMDMA2LLCLK_ipd, CPMDMA3LLCLK_ipd, CPMFCMCLK_ipd, CPMINTERCONNECTCLKEN_ipd, CPMINTERCONNECTCLKNTO1_ipd, CPMINTERCONNECTCLK_ipd, CPMMCCLK_ipd, CPMPPCMPLBCLK_ipd, CPMPPCS0PLBCLK_ipd, CPMPPCS1PLBCLK_ipd, DBGC440DEBUGHALT_ipd, DBGC440SYSTEMSTATUS_ipd, DBGC440UNCONDDEBUGEVENT_ipd, DCRPPCDMACK_ipd, DCRPPCDMDBUSIN_ipd, DCRPPCDMTIMEOUTWAIT_ipd, DCRPPCDSABUS_ipd, DCRPPCDSDBUSOUT_ipd, DCRPPCDSREAD_ipd, DCRPPCDSWRITE_ipd, EICC440CRITIRQ_ipd, EICC440EXTIRQ_ipd, FCMAPUCONFIRMINSTR_ipd, FCMAPUCR_ipd, FCMAPUDONE_ipd, FCMAPUEXCEPTION_ipd, FCMAPUFPSCRFEX_ipd, FCMAPURESULTVALID_ipd, FCMAPURESULT_ipd, FCMAPUSLEEPNOTREADY_ipd, FCMAPUSTOREDATA_ipd, JTGC440TCK_ipd, JTGC440TDI_ipd, JTGC440TMS_ipd, JTGC440TRSTNEG_ipd, LLDMA0RSTENGINEREQ_ipd, LLDMA0RXD_ipd, LLDMA0RXEOFN_ipd, LLDMA0RXEOPN_ipd, LLDMA0RXREM_ipd, LLDMA0RXSOFN_ipd, LLDMA0RXSOPN_ipd, LLDMA0RXSRCRDYN_ipd, LLDMA0TXDSTRDYN_ipd, LLDMA1RSTENGINEREQ_ipd, LLDMA1RXD_ipd, LLDMA1RXEOFN_ipd, LLDMA1RXEOPN_ipd, LLDMA1RXREM_ipd, LLDMA1RXSOFN_ipd, LLDMA1RXSOPN_ipd, LLDMA1RXSRCRDYN_ipd, LLDMA1TXDSTRDYN_ipd, LLDMA2RSTENGINEREQ_ipd, LLDMA2RXD_ipd, LLDMA2RXEOFN_ipd, LLDMA2RXEOPN_ipd, LLDMA2RXREM_ipd, LLDMA2RXSOFN_ipd, LLDMA2RXSOPN_ipd, LLDMA2RXSRCRDYN_ipd, LLDMA2TXDSTRDYN_ipd, LLDMA3RSTENGINEREQ_ipd, LLDMA3RXD_ipd, LLDMA3RXEOFN_ipd, LLDMA3RXEOPN_ipd, LLDMA3RXREM_ipd, LLDMA3RXSOFN_ipd, LLDMA3RXSOPN_ipd, LLDMA3RXSRCRDYN_ipd, LLDMA3TXDSTRDYN_ipd, MCMIADDRREADYTOACCEPT_ipd, MCMIREADDATAERR_ipd, MCMIREADDATAVALID_ipd, MCMIREADDATA_ipd, PLBPPCMADDRACK_ipd, PLBPPCMMBUSY_ipd, PLBPPCMMIRQ_ipd, PLBPPCMMRDERR_ipd, PLBPPCMMWRERR_ipd, PLBPPCMRDBTERM_ipd, PLBPPCMRDDACK_ipd, PLBPPCMRDDBUS_ipd, PLBPPCMRDPENDPRI_ipd, PLBPPCMRDPENDREQ_ipd, PLBPPCMRDWDADDR_ipd, PLBPPCMREARBITRATE_ipd, PLBPPCMREQPRI_ipd, PLBPPCMSSIZE_ipd, PLBPPCMTIMEOUT_ipd, PLBPPCMWRBTERM_ipd, PLBPPCMWRDACK_ipd, PLBPPCMWRPENDPRI_ipd, PLBPPCMWRPENDREQ_ipd, PLBPPCS0ABORT_ipd, PLBPPCS0ABUS_ipd, PLBPPCS0BE_ipd, PLBPPCS0BUSLOCK_ipd, PLBPPCS0LOCKERR_ipd, PLBPPCS0MASTERID_ipd, PLBPPCS0MSIZE_ipd, PLBPPCS0PAVALID_ipd, PLBPPCS0RDBURST_ipd, PLBPPCS0RDPENDPRI_ipd, PLBPPCS0RDPENDREQ_ipd, PLBPPCS0RDPRIM_ipd, PLBPPCS0REQPRI_ipd, PLBPPCS0RNW_ipd, PLBPPCS0SAVALID_ipd, PLBPPCS0SIZE_ipd, PLBPPCS0TATTRIBUTE_ipd, PLBPPCS0TYPE_ipd, PLBPPCS0UABUS_ipd, PLBPPCS0WRBURST_ipd, PLBPPCS0WRDBUS_ipd, PLBPPCS0WRPENDPRI_ipd, PLBPPCS0WRPENDREQ_ipd, PLBPPCS0WRPRIM_ipd, PLBPPCS1ABORT_ipd, PLBPPCS1ABUS_ipd, PLBPPCS1BE_ipd, PLBPPCS1BUSLOCK_ipd, PLBPPCS1LOCKERR_ipd, PLBPPCS1MASTERID_ipd, PLBPPCS1MSIZE_ipd, PLBPPCS1PAVALID_ipd, PLBPPCS1RDBURST_ipd, PLBPPCS1RDPENDPRI_ipd, PLBPPCS1RDPENDREQ_ipd, PLBPPCS1RDPRIM_ipd, PLBPPCS1REQPRI_ipd, PLBPPCS1RNW_ipd, PLBPPCS1SAVALID_ipd, PLBPPCS1SIZE_ipd, PLBPPCS1TATTRIBUTE_ipd, PLBPPCS1TYPE_ipd, PLBPPCS1UABUS_ipd, PLBPPCS1WRBURST_ipd, PLBPPCS1WRDBUS_ipd, PLBPPCS1WRPENDPRI_ipd, PLBPPCS1WRPENDREQ_ipd, PLBPPCS1WRPRIM_ipd, RSTC440RESETCHIP_ipd, RSTC440RESETCORE_ipd, RSTC440RESETSYSTEM_ipd, TIEC440DCURDLDCACHEPLBPRIO_ipd, TIEC440DCURDNONCACHEPLBPRIO_ipd, TIEC440DCURDTOUCHPLBPRIO_ipd, TIEC440DCURDURGENTPLBPRIO_ipd, TIEC440DCUWRFLUSHPLBPRIO_ipd, TIEC440DCUWRSTOREPLBPRIO_ipd, TIEC440DCUWRURGENTPLBPRIO_ipd, TIEC440ENDIANRESET_ipd, TIEC440ERPNRESET_ipd, TIEC440ICURDFETCHPLBPRIO_ipd, TIEC440ICURDSPECPLBPRIO_ipd, TIEC440ICURDTOUCHPLBPRIO_ipd, TIEC440PIR_ipd, TIEC440PVR_ipd, TIEC440USERRESET_ipd, TIEDCRBASEADDR_ipd, TRCC440TRACEDISABLE_ipd, TRCC440TRIGGEREVENTIN_ipd; end process TIMING; end PPC440_V;