-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: system test using Xilinx ML-402

-- Copyright (C) 2007 J. Ahrensfeld

-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.

-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- Lesser General Public License for more details.

-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA

-- For questions and ideas, please contact the author at jens@jayfield.org

-----------------------------------------------------------------------

LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; --  Imports the standard textio package.

Library UNISIM;
use UNISIM.vcomponents.all;

library work;
use work.mips_types.all;
--use work.fifo_ctrl_pkg.all;
use work.sdram_config.all;
use work.sdram_types.all;
use work.vga_types.all;
use work.sys_types.all;


ENTITY mips_sys IS
GENERIC
(
	sys_freq			: integer		    := 100E6;
	ddr_phaseshift		: integer			:= 0;
	ddr_frequency_hz	: integer			:= 100E6
);
PORT
(
	sys_rst_n_in		: in std_logic;
	sys_clk_in			: in std_logic;

	-- Buttons and LEDs
	sys_btn				: in unsigned(4 downto 0);
	sys_dip				: in unsigned(7 downto 0);
	sys_led				: out unsigned(8 downto 0);

	-- UART
	sys_rx				: in std_logic;
	sys_tx				: out std_logic;

	-- User ROM
	sys_user_rom_addr	: out word_t;
	sys_user_rom_din	: in  word_t;
	sys_user_rom_clk	: out std_logic;
	sys_user_rom_en		: out std_logic;

	-- LCD
	sys_lcd_d			: inout unsigned(3 downto 0);
	sys_lcd_e			: out std_logic;
	sys_lcd_rs			: out std_logic;
	sys_lcd_rw			: out std_logic;

	-- DDR SDRAM
	sys_sdr_clk_p		: out std_logic;    -- ddr_sdram_clock
	sys_sdr_clk_n		: out std_logic;    -- /ddr_sdram_clock
	sys_sdr_cke_q		: out std_logic;    -- clock enable
	sys_sdr_cs_qn		: out std_logic;    -- /chip select
	sys_sdr_ras_qn		: out std_logic;    -- /ras
	sys_sdr_cas_qn		: out std_logic;    -- /cas
	sys_sdr_we_qn		: out std_logic;    -- /write enable
	sys_sdr_dm_q		: out unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
	sys_sdr_dqs_q		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
	sys_sdr_ba_q		: out unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
	sys_sdr_a_q			: out unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
	sys_sdr_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
	sys_sdr_clk_fb		: in std_logic;
	
	-- VGA
	sys_vga_clk			: out std_logic;
	sys_vga_red			: out unsigned(7 downto 0);
	sys_vga_green		: out unsigned(7 downto 0);
	sys_vga_blue		: out unsigned(7 downto 0);
	sys_vga_blank_n		: out std_logic;
	sys_vga_sync_n		: out std_logic;
	sys_vga_hsync		: out std_logic;
	sys_vga_vsync		: out std_logic;

	sys_usb_d			: inout unsigned(15 downto 0);
	sys_usb_a			: out unsigned(1 downto 0);
	sys_usb_csn			: out std_logic;
	sys_usb_wrn			: out std_logic;
	sys_usb_rdn			: out std_logic;
	sys_usb_rstn		: out std_logic;
	sys_usb_int			: in std_logic;

	sys_flash_ssram_d		: inout unsigned(31 downto 0);
	sys_flash_ssram_a		: out unsigned(24 downto 0);
	sys_flash_ce			: out std_logic;
	sys_flash_ssram_we_n	: out std_logic;
	sys_flash_ssram_oe_n	: out std_logic;
	sys_flash_rstn			: out std_logic;
	sys_flash_byten			: out std_logic;	
	
	sys_ssram_clk			: out std_logic;
	sys_ssram_clk_fb		: in std_logic;
	sys_ssram_cke_n			: out std_logic;
	sys_ssram_ce_n			: out std_logic;
	sys_ssram_bw_n			: out unsigned(3 downto 0);
	sys_ssram_dp			: inout unsigned(3 downto 0);
	sys_ssram_adv			: out std_logic;
	sys_ssram_mode			: out std_logic;
	sys_ssram_zz			: out std_logic;
	
	sys_error				: out unsigned(1 downto 0) -- indicates Errors
	
);
--	attribute BUFFER_TYPE : string;
--	attribute BUFFER_TYPE of sys_clk_in			: signal is "BUFG";
--	attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb	: signal is "BUFG";

END mips_sys;

ARCHITECTURE behavior OF mips_sys IS 

	COMPONENT mips_top
	Port 
	(
		debug		: out unsigned(1 downto 0);
		RST_I		: in  STD_LOGIC;
		CLK_I		: in  STD_LOGIC;
		ACK_I		: in  STD_LOGIC;
		SRDY_I		: in  STD_LOGIC;
		ADDR_O		: out word_t;
		DAT_I		: in  word_t;
		DAT_O		: out word_t;
		WE_O		: out STD_LOGIC;
		SEL_O		: out unsigned(3 downto 0);
		CYC_O		: out STD_LOGIC;
		STB_O		: out STD_LOGIC;
		MRDY_O		: out STD_LOGIC;
		INT			: in  unsigned (5 downto 0)
		
	);
	END COMPONENT;
	
	COMPONENT rom_wb
	PORT
	(
		CLK_I		: in  STD_LOGIC;
		RST_I		: in  STD_LOGIC;
		CYC_I		: in  STD_LOGIC;
		STB_I		: in  STD_LOGIC;
		ACK_O		: out STD_LOGIC;
		MRDY_I		: in  STD_LOGIC;
		SRDY_O		: out STD_LOGIC;
		ADDR_I		: in  unsigned(31 downto 0);
		DAT_O		: out unsigned(31 downto 0)
	);
	END COMPONENT;

	COMPONENT ram_wb
	PORT
	(
		CLK_I		: in  STD_LOGIC;
		RST_I		: in  STD_LOGIC;
		CYC_I		: in  STD_LOGIC;
		STB_I		: in  STD_LOGIC;
		SEL_I		: in  unsigned(3 downto 0);
		WE_I		: in  STD_LOGIC;
		ACK_O		: out STD_LOGIC;
		SRDY_O		: out STD_LOGIC;
		MRDY_I		: in  STD_LOGIC;
		ADDR_I		: in  unsigned(31 downto 0);
		DAT_I		: in  unsigned(31 downto 0);
		DAT_O		: out unsigned(31 downto 0)
	);
	END COMPONENT;

	COMPONENT lcd_port
	PORT 
	(
		rst			: in std_logic;
		clk			: in std_logic;
		we			: in std_logic;
		din			: in unsigned(7 downto 0);
		dout		: out unsigned(7 downto 0);
		lcd_d		: inout unsigned(3 downto 0);
		lcd_e		: out std_logic;
		lcd_rs		: out std_logic;
		lcd_rw		: out std_logic
	);
	END COMPONENT;

	COMPONENT async_port_wb
	GENERIC
	(
		addr_width		: natural := 32;
		data_width		: natural := 32;
		async_timespec	: async_timespec_t
	);
	PORT
	(
		CLK_I		: in  STD_LOGIC;
		RST_I		: in  STD_LOGIC;
		CYC_I		: in  STD_LOGIC;
		STB_I		: in  STD_LOGIC;
		WE_I		: in  STD_LOGIC;
		ACK_O		: out STD_LOGIC;
		SRDY_O		: out STD_LOGIC;
		MRDY_I		: in  STD_LOGIC;
		ADDR_I		: in  unsigned(31 downto 0);
		DAT_I		: in  unsigned(31 downto 0);
		DAT_O		: out unsigned(31 downto 0);
		async_a		: out unsigned(addr_width-1 downto 0);
		async_d		: inout unsigned(data_width-1 downto 0);
		async_cs	: out std_logic;
		async_wr	: out std_logic;
		async_rd	: out std_logic;
		async_rst	: out std_logic
	);
	END COMPONENT;

	COMPONENT uart_wb
	PORT
	(
		CLK_I		: in  STD_LOGIC;
		RST_I		: in  STD_LOGIC;
		CYC_I		: in  STD_LOGIC;
		STB_I		: in  STD_LOGIC;
		SEL_I		: in  unsigned(3 downto 0);
		WE_I		: in  STD_LOGIC;
		ACK_O		: out STD_LOGIC;
		SRDY_O		: out STD_LOGIC;
		MRDY_I		: in  STD_LOGIC;
		ADDR_I		: in  unsigned(31 downto 0);
		DAT_I		: in  unsigned(31 downto 0);
		DAT_O		: out unsigned(31 downto 0);
		INT_RX_O	: out STD_LOGIC;
		INT_TX_O	: out STD_LOGIC;
		ser_rx		: in std_logic;
		ser_tx		: out std_logic
	);
	END COMPONENT;

	COMPONENT gpio_wb
	PORT
	(
		CLK_I		: in  STD_LOGIC;
		RST_I		: in  STD_LOGIC;
		CYC_I		: in  STD_LOGIC;
		STB_I		: in  STD_LOGIC;
		SEL_I		: in  unsigned(3 downto 0);
		WE_I		: in  STD_LOGIC;
		ACK_O		: out STD_LOGIC;
		SRDY_O		: out STD_LOGIC;
		MRDY_I		: in  STD_LOGIC;
		ADDR_I		: in  unsigned(31 downto 0);
		DAT_I		: in  unsigned(31 downto 0);
		DAT_O		: out unsigned(31 downto 0);

		sys_gpo0	: out unsigned(31 downto 0);
		sys_gpo1	: out unsigned(31 downto 0);
		sys_gpi0	: in  unsigned(31 downto 0);
		sys_gpi1	: in  unsigned(31 downto 0)
	);
	END COMPONENT;

	COMPONENT vga_frontend
	GENERIC
	(
		sys_freq					: integer;
		fifo_depth					: integer;
		fifo_almost_full_thresh		: natural;
		fifo_almost_empty_thresh	: natural;
		tsvga						: vga_timespec_t
	);
	PORT
	(
		-- System signals
		RST_I			: in  STD_LOGIC;
		CLK_I			: in  STD_LOGIC;

		-- JBUS Master signals
		CYC_O			: out STD_LOGIC;
		STB_O			: out STD_LOGIC;
		WE_O			: out STD_LOGIC;
		SEL_O			: out unsigned(3 downto 0);
		ACK_I			: in  STD_LOGIC;
		SRDY_I			: in  STD_LOGIC;
		MRDY_O			: out STD_LOGIC;
		ADDR_O			: out unsigned(31 downto 0);
		MDAT_I			: in  unsigned(31 downto 0);
		MDAT_O			: out unsigned(31 downto 0);

		-- JBUS Slave signals
		CYC_I			: in  STD_LOGIC;
		STB_I			: in  STD_LOGIC;
		WE_I			: in  STD_LOGIC;
		SEL_I			: in  unsigned(3 downto 0);
		ACK_O			: out STD_LOGIC;
		SRDY_O			: out STD_LOGIC;
		MRDY_I			: in  STD_LOGIC;
		ADDR_I			: in  unsigned(31 downto 0);
		SDAT_I			: in  unsigned(31 downto 0);
		SDAT_O			: out unsigned(31 downto 0);
		
		-- VGA signals
		vga_clk_out		: out std_logic;
		vga_red			: out unsigned(7 downto 0);
		vga_green		: out unsigned(7 downto 0);
		vga_blue		: out unsigned(7 downto 0);
		vga_blank_n		: out std_logic;
		vga_sync_n		: out std_logic;
		vga_hsync		: out std_logic;
		vga_vsync		: out std_logic
	);
	END COMPONENT;

	signal rst			: std_logic;
	signal clk			: std_logic;
	signal clk270		: std_logic;
	signal clk270var	: std_logic;
	signal rst_in		: std_logic;
	signal int_uart_rx	: std_logic;
	signal locked		: std_logic;
	signal ADDR_I_usb 	: unsigned(31 downto 0);
	signal ADDR_I_flash	: unsigned(31 downto 0);
	signal ADDR_I_ssram	: unsigned(31 downto 0);
	signal flash_a		: unsigned(24 downto 0);
	signal ssram_a		: unsigned(24 downto 0);
	signal ssram_clk	: std_logic;
	signal ssram_oe_n	: std_logic;
	signal ssram_we_n	: std_logic;
	signal flash_oe_n	: std_logic;
	signal flash_we_n	: std_logic;
	signal dcm_locked	: std_logic;
	signal dcm_clk0		: std_logic;
	
	-- Arbiter
	constant ARB_MAX_MASTER	: natural := 2;
	signal arb_idx		: natural range 0 to ARB_MAX_MASTER-1;
	signal arb_req		: unsigned (ARB_MAX_MASTER-1 downto 0);
	signal arb_gnt		: unsigned (ARB_MAX_MASTER-1 downto 0);
	
	-- J-Bus signals
	signal INT	 		: unsigned(5 downto 0);
	signal MDAT_I		: word_t;
	signal MDAT_O 		: word_t;
	signal ADDR_O 		: word_t;
	signal SEL_O 		: unsigned(3 downto 0);
	signal WE_O 		: std_logic;
	signal CYC_O 		: std_logic;
	signal STB_O 		: std_logic;
	signal ACK_I		: std_logic;
	signal SRDY_I		: std_logic;
	signal MRDY_O		: std_logic;

	-- CPU Master
	signal MRDY_O_cpu	: std_logic;
	signal MDAT_O_cpu	: word_t;
	signal ADDR_O_cpu	: word_t;
	signal SEL_O_cpu	: unsigned(3 downto 0);
	signal WE_O_cpu		: std_logic;
	signal CYC_O_cpu	: std_logic;
	signal STB_O_cpu	: std_logic;
	signal SRDY_I_cpu	: std_logic;
	signal ACK_I_cpu	: std_logic;

	-- VGA Master
	signal MRDY_O_vga	: std_logic;
	signal MDAT_O_vga	: word_t;
	signal ADDR_O_vga	: word_t;
	signal SEL_O_vga	: unsigned(3 downto 0);
	signal WE_O_vga		: std_logic;
	signal CYC_O_vga	: std_logic;
	signal STB_O_vga	: std_logic;
	signal SRDY_I_vga	: std_logic;
	signal ACK_I_vga	: std_logic;

	-- Slaves
	signal CYC_I_flash	: std_logic;
	signal ACK_O_flash	: std_logic;
	signal SRDY_O_flash	: std_logic;
	signal SDAT_O_flash	: unsigned(31 downto 0);

	signal CYC_I_usb	: std_logic;
	signal ACK_O_usb	: std_logic;
	signal SRDY_O_usb	: std_logic;
	signal SDAT_O_usb	: unsigned(31 downto 0);

	signal CYC_I_sdram	: std_logic;
	signal ACK_O_sdram	: std_logic;
	signal SRDY_O_sdram	: std_logic;
	signal SDAT_O_sdram	: unsigned(31 downto 0);

	signal CYC_I_ram	: std_logic;
	signal ACK_O_ram	: std_logic;
	signal SRDY_O_ram	: std_logic;
	signal SDAT_O_ram	: unsigned(31 downto 0);

	signal CYC_I_rom	: std_logic;
	signal ACK_O_rom	: std_logic;
	signal SRDY_O_rom	: std_logic;
	signal SDAT_O_rom	: unsigned(31 downto 0);

	signal CYC_I_gpio	: std_logic;
	signal ACK_O_gpio	: std_logic;
	signal SRDY_O_gpio	: std_logic;
	signal SDAT_O_gpio	: unsigned(31 downto 0);

	signal CYC_I_urom	: std_logic;
	signal ACK_O_urom	: std_logic;
	signal SRDY_O_urom	: std_logic;
	signal SDAT_O_urom	: unsigned(31 downto 0);

	signal CYC_I_uart	: std_logic;
	signal ACK_O_uart	: std_logic;
	signal SRDY_O_uart	: std_logic;
	signal SDAT_O_uart	: unsigned(31 downto 0);

	signal CYC_I_vga	: std_logic;
	signal ACK_O_vga	: std_logic;
	signal SRDY_O_vga	: std_logic;
	signal SDAT_O_vga	: unsigned(31 downto 0);

	signal CYC_I_ssram	: std_logic;
	signal ACK_O_ssram	: std_logic;
	signal SRDY_O_ssram	: std_logic;
	signal SDAT_O_ssram	: unsigned(31 downto 0);

	signal gpo0			: unsigned(31 downto 0);
	signal gpo1			: unsigned(31 downto 0);
	signal gpi0			: unsigned(31 downto 0);
	signal gpi1			: unsigned(31 downto 0);

	signal debug		: unsigned(1 downto 0);

	-- DDR SDRAM
	constant BURST_LEN	: natural := 2;

	
--	attribute rom_style: string;
--	attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
--	attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
--	attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";

	type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_ssram, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga);
	signal mem_area : mem_area_t;

BEGIN

	gpi0(4 downto 0)	<= sys_btn;
	gpi1(7 downto 0)	<= sys_dip;
	sys_led				<= gpo0(8 downto 0);
	sys_error			<= debug;
	rst_in 				<= not sys_rst_n_in;
	rst					<= not locked;
	sys_usb_rstn		<= not gpo1(0);
	sys_flash_byten		<= '1';
	ADDR_I_usb			<= X"0000000" & "00" & ADDR_O(3 downto 2);
	ADDR_I_flash		<= "0000000" & ADDR_O(25 downto 2) & '0';
	ADDR_I_ssram		<= ("0000000000000" & ADDR_O(19 downto 2)) & '0';

	sys_flash_ssram_a		<= flash_a when CYC_I_flash = '1' else ssram_a;
	sys_flash_ssram_we_n	<= ssram_we_n and flash_we_n;
	sys_flash_ssram_oe_n	<= ssram_oe_n and flash_oe_n;
	sys_ssram_clk			<= clk;
	
	---------------------------------------------------------------
	-- Arbiter
	MRDY_O		<= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
	MDAT_O		<= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0');
	ADDR_O		<= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
	SEL_O		<= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0');
	WE_O		<= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
	CYC_O		<= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
	STB_O		<= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
	SRDY_I_cpu	<= SRDY_I and arb_gnt(0);
	SRDY_I_vga	<= SRDY_I and arb_gnt(1);
	ACK_I_cpu	<= ACK_I and arb_gnt(0);
	ACK_I_vga	<= ACK_I and arb_gnt(1);
	
	arb_req(0)	<= CYC_O_cpu;
	arb_req(1)	<= CYC_O_vga;
	
	
arbiter_proc:
	process(clk)
	begin
		if rising_edge(clk) then
			if rst = '1' then
				arb_gnt	<= (others => '0');
				arb_idx	<= 0;
			elsif arb_req(arb_idx) = '0' then
				if arb_idx /= ARB_MAX_MASTER-1 then
					arb_idx	<= arb_idx + 1;
				else
					arb_idx	<= 0;
				end if;
			else	
				arb_gnt	<= (others => '0');
				arb_gnt(arb_idx)	<= '1';
			end if;	
		end if;
	end process;
	
int_sample:
	process(clk)
	begin
		if rising_edge(clk) then
			int <= "000" & sys_usb_int & int_uart_rx & sys_btn(4);
		end if;
	end process;
	
mem_mux:
	process(ADDR_O)
	begin
		mem_area	<= mem_dead;
		if ADDR_O(31 downto 28) = X"0" then
			mem_area	<= mem_urom;
		elsif ADDR_O(31 downto 28) = X"A" then
			if ADDR_O(26) = '1' then
				mem_area	<= mem_flash;
			elsif ADDR_O(17 downto 16) = "00" then
				mem_area	<= mem_gpio;
			elsif ADDR_O(17 downto 16) = "01" then
				mem_area	<= mem_uart;
			elsif ADDR_O(17 downto 16) = "10" then
				mem_area	<= mem_usb;
			elsif ADDR_O(17 downto 16) = "11" then
				mem_area	<= mem_vga;
			end if;	
		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
			mem_area	<= mem_rom;
		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
			mem_area	<= mem_ssram;
--			mem_area	<= mem_ram;
		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
			mem_area	<= mem_sdram;
		end if;
	end process;	

signal_mux:
	process(mem_area, CYC_O)
	begin
	
		CYC_I_urom		<= '0';
		CYC_I_uart		<= '0';
		CYC_I_gpio		<= '0';
		CYC_I_flash		<= '0';
		CYC_I_usb		<= '0';
		CYC_I_rom		<= '0';
		CYC_I_ram		<= '0';
		CYC_I_sdram		<= '0';
		CYC_I_vga		<= '0';
		CYC_I_ssram		<= '0';
		
		case mem_area is

		when mem_urom =>
			CYC_I_urom		<= CYC_O;
			
		when mem_gpio =>
			CYC_I_gpio		<= CYC_O;

		when mem_uart =>
			CYC_I_uart		<= CYC_O;

		when mem_flash =>
			CYC_I_flash		<= CYC_O;

		when mem_usb =>
			CYC_I_usb		<= CYC_O;

		when mem_rom =>
			CYC_I_rom		<= CYC_O;

		when mem_ram =>
			CYC_I_ram		<= CYC_O;

		when mem_sdram =>
			CYC_I_sdram		<= CYC_O;
		
		when mem_vga =>
			CYC_I_vga		<= CYC_O;

		when mem_ssram =>
			CYC_I_ssram		<= CYC_O;

		when others => null;
		
		end case;
		
	end process;

	sys_user_rom_addr	<= ADDR_O;
	sys_user_rom_clk	<= clk;
	sys_user_rom_en		<= CYC_I_urom and STB_O;
	SDAT_O_urom			<= sys_user_rom_din;
	SRDY_O_urom			<= CYC_I_urom;
	
urom_ack_register:
	process(clk)
	begin
		if rising_edge(clk) then
			ACK_O_urom	<= CYC_I_urom and STB_O;
		end if;
	end process;
	
------------------------------------------------------------------
 	SRDY_I		<=	SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_urom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga;
 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_ram or ACK_O_rom or ACK_O_urom or ACK_O_uart or ACK_O_gpio or ACK_O_vga;
 	MDAT_I		<=	SDAT_O_ssram when CYC_I_ssram = '1' else
 					SDAT_O_sdram when CYC_I_sdram = '1' else
					SDAT_O_ram when CYC_I_ram = '1' else
					SDAT_O_rom when CYC_I_rom = '1' else
					SDAT_O_urom when CYC_I_urom = '1' else
					SDAT_O_flash when CYC_I_flash = '1' else
					SDAT_O_usb when CYC_I_usb = '1' else
					SDAT_O_uart when CYC_I_uart = '1' else
					SDAT_O_vga when CYC_I_vga = '1' else
					SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";

------------------------------------------------------------------
inst_mips_top: mips_top
	PORT MAP
	(
		debug			=> debug,
		RST_I			=> rst,
		CLK_I			=> clk,
		ACK_I			=> ACK_I_cpu,
		SRDY_I			=> SRDY_I_cpu,
		MRDY_O			=> MRDY_O_cpu,
		CYC_O			=> CYC_O_cpu,
		STB_O			=> STB_O_cpu,
		WE_O			=> WE_O_cpu,
		SEL_O			=> SEL_O_cpu,
		DAT_I			=> MDAT_I,
		DAT_O			=> MDAT_O_cpu,
		ADDR_O			=> ADDR_O_cpu,
		INT				=> INT
	);

inst_ram_wb : ram_wb
	PORT MAP
	(
		CLK_I	=> clk,
		RST_I	=> rst,
		CYC_I	=> CYC_I_ram,
		STB_I	=> STB_O,
		SEL_I	=> SEL_O,
		WE_I	=> WE_O,
		ACK_O	=> ACK_O_ram,
		SRDY_O	=> SRDY_O_ram,
		MRDY_I	=> MRDY_O,
		ADDR_I	=> ADDR_O,
		DAT_I	=> MDAT_O,
		DAT_O	=> SDAT_O_ram
	);

inst_rom_wb : rom_wb
	PORT MAP
	(
		CLK_I	=> clk,
		RST_I	=> rst,
		CYC_I	=> CYC_I_rom,
		STB_I	=> STB_O,
		ACK_O	=> ACK_O_rom,
		MRDY_I	=> MRDY_O,
		SRDY_O	=> SRDY_O_rom,
		ADDR_I	=> ADDR_O,
		DAT_O	=> SDAT_O_rom
	);


inst_lcd_port: lcd_port
	PORT MAP
	(
		clk => clk,
		rst => rst,
		we => '0',
		din => X"00",
		dout => open,
		lcd_d => sys_lcd_d,
		lcd_e => sys_lcd_e,
		lcd_rs => sys_lcd_rs,
		lcd_rw => sys_lcd_rw
	);
	
inst_gpio_wb : gpio_wb
	PORT MAP
	(
		CLK_I		=> clk,
		RST_I		=> rst,
		CYC_I		=> CYC_I_gpio,
		STB_I		=> STB_O,
		SEL_I		=> SEL_O,
		WE_I		=> WE_O,
		ACK_O		=> ACK_O_gpio,
		SRDY_O		=> SRDY_O_gpio,
		MRDY_I		=> MRDY_O,
		ADDR_I		=> ADDR_O,
		DAT_I		=> MDAT_O,
		DAT_O		=> SDAT_O_gpio,

		sys_gpo0	=> gpo0,
		sys_gpo1	=> gpo1,
		sys_gpi0	=> gpi0,
		sys_gpi1	=> gpi1
	);


inst_flash_port : async_port_wb
	GENERIC MAP
	(
		addr_width		=> 25,
		data_width		=> 32,
		async_timespec	=> ts_flash
	)
	PORT MAP
	(
		CLK_I		=> clk,
		RST_I		=> rst,
		CYC_I		=> CYC_I_flash,
		STB_I		=> STB_O,
		WE_I		=> WE_O,
		ACK_O		=> ACK_O_flash,
		SRDY_O		=> SRDY_O_flash,
		MRDY_I		=> MRDY_O,
		ADDR_I		=> ADDR_I_flash,
		DAT_I		=> MDAT_O,
		DAT_O		=> SDAT_O_flash,
		async_a		=> flash_a,
		async_d		=> sys_flash_ssram_d,
		async_cs	=> sys_flash_ce,
		async_wr	=> flash_we_n,
		async_rd	=> flash_oe_n,
		async_rst	=> sys_flash_rstn
	);

inst_usb_port : async_port_wb
	GENERIC MAP
	(
		addr_width		=> 2,
		data_width		=> 16,
		async_timespec	=> ts_usb
	)
	PORT MAP
	(
		CLK_I		=> clk,
		RST_I		=> rst,
		CYC_I		=> CYC_I_usb,
		STB_I		=> STB_O,
		WE_I		=> WE_O,
		ACK_O		=> ACK_O_usb,
		SRDY_O		=> SRDY_O_usb,
		MRDY_I		=> MRDY_O,
		ADDR_I		=> ADDR_I_usb,
		DAT_I		=> MDAT_O,
		DAT_O		=> SDAT_O_usb,
		async_a		=> sys_usb_a,
		async_d		=> sys_usb_d,
		async_cs	=> sys_usb_csn,
		async_wr	=> sys_usb_wrn,
		async_rd	=> sys_usb_rdn,
		async_rst	=> open
	);

inst_uart_wb : uart_wb
	PORT MAP
	(
		CLK_I		=> clk,
		RST_I		=> rst,
		CYC_I		=> CYC_I_uart,
		STB_I		=> STB_O,
		SEL_I		=> SEL_O,
		WE_I		=> WE_O,
		ACK_O		=> ACK_O_uart,
		SRDY_O		=> SRDY_O_uart,
		MRDY_I		=> MRDY_O,
		ADDR_I		=> ADDR_O,
		DAT_I		=> MDAT_O,
		DAT_O		=> SDAT_O_uart,
		INT_RX_O	=> int_uart_rx,
		INT_TX_O	=> open,
		ser_rx		=> sys_rx,
		ser_tx		=> sys_tx
	);


inst_ssram_frontend_wb : entity work.ssram_frontend_wb
	GENERIC MAP
	(
		addr_width		=> 25,
		data_width		=> 32,
		parity_width	=> 4
	)
	PORT MAP
	(
		-- J-Bus domain
		RST_I		=> rst,
		CLK_I		=> clk,
		CYC_I		=> CYC_I_ssram,
		STB_I		=> STB_O,
		SEL_I		=> SEL_O,
		WE_I		=> WE_O,
		ACK_O		=> ACK_O_ssram,
		SRDY_O		=> SRDY_O_ssram,
		MRDY_I		=> MRDY_O,
		ADDR_I		=> ADDR_I_ssram,
		DAT_I		=> MDAT_O,
		DAT_O		=> SDAT_O_ssram,
		
		-- Sync SRAM domain
		ssram_clk_i	=> ssram_clk,
		ssram_cke_n	=> sys_ssram_cke_n,
		ssram_ce_n	=> sys_ssram_ce_n,
		ssram_oe_n	=> ssram_oe_n,
		ssram_we_n	=> ssram_we_n,
		ssram_adv	=> sys_ssram_adv,
		ssram_mode	=> sys_ssram_mode,
		ssram_zz	=> sys_ssram_zz,
		ssram_a		=> ssram_a,
		ssram_d		=> sys_flash_ssram_d,
		ssram_dp	=> sys_ssram_dp,
		ssram_bw_n	=> sys_ssram_bw_n
	);

inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
	GENERIC MAP
	(
		BL			=> BURST_LEN,
		f_sysclk	=> ddr_frequency_hz,
		fifo_depth	=> 6
	)
	PORT MAP
	(
		RST_I			=> rst,
		CLK_I			=> clk,
		CLK270_I		=> clk270,
		CLK270VAR_I		=> clk270var,
		
		CYC_I			=> CYC_I_sdram,
		STB_I			=> STB_O,
		SEL_I			=> SEL_O,
		WE_I			=> WE_O,
		ACK_O			=> ACK_O_sdram,
		MRDY_I			=> MRDY_O,
		SRDY_O			=> SRDY_O_sdram,
		ADDR_I			=> ADDR_O,
		DAT_I			=> MDAT_O,
		DAT_O			=> SDAT_O_sdram,

		-- SDRAM signals
		sd_clk_p		=> sys_sdr_clk_p,
		sd_clk_n		=> sys_sdr_clk_n,
		sd_cke			=> sys_sdr_cke_q,
		sd_cs_n			=> sys_sdr_cs_qn,
		sd_cas_n		=> sys_sdr_cas_qn,
		sd_ras_n		=> sys_sdr_ras_qn,
		sd_we_n			=> sys_sdr_we_qn,
		sd_addr			=> sys_sdr_a_q,
		sd_ba			=> sys_sdr_ba_q,
		sd_dm			=> sys_sdr_dm_q,
		sd_dqs			=> sys_sdr_dqs_q,
		sd_data			=> sys_sdr_data
		
	);

inst_clockgen : entity work.clockgen
	GENERIC MAP
	(
		sys1_phaseshift	=> 0,
		frequency_hz	=> 100E6
	)
	PORT MAP 
	(
		-- Clocks and Reset
		rst				=> rst_in,   -- external async reset, low active
		clk_in			=> sys_clk_in,   -- system clock (e.g. 100MHz), from board
		clk_fb_in		=> sys_sdr_clk_fb,   -- feedback clock
		sys1_clk0_out	=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
		sys1_clk270_out	=> clk270var,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
		sys0_clk0_out	=> clk,  -- System clock #0, dcm#0 output 0°
		sys0_clk270_out	=> clk270,  -- System clock #0, dcm#0 output 270°
		locked_out		=> locked,  -- DCM locked status
		error_out		=> open
	);

inst_vga_frontend : vga_frontend
	GENERIC MAP
	(
		sys_freq					=> 100E6,
		fifo_depth					=> 2048,
		fifo_almost_full_thresh		=> 1920,
		fifo_almost_empty_thresh	=> 128,
		tsvga						=> ts_vga_testbench
	)
	PORT MAP
	(
		-- System signals
		RST_I			=> rst,
		CLK_I			=> clk,

		-- JBUS Master signals
		CYC_O			=> CYC_O_vga,
		STB_O			=> STB_O_vga,
		WE_O			=> WE_O_vga,
		SEL_O			=> SEL_O_vga,
		ACK_I			=> ACK_I_vga,
		SRDY_I			=> SRDY_I_vga,
		MRDY_O			=> MRDY_O_vga,
		ADDR_O			=> ADDR_O_vga,
		MDAT_I			=> MDAT_I,
		MDAT_O			=> MDAT_O_vga,

		-- JBUS Slave signals
		CYC_I			=> CYC_I_vga,
		STB_I			=> STB_O,
		WE_I			=> WE_O,
		SEL_I			=> SEL_O,
		ACK_O			=> ACK_O_vga,
		SRDY_O			=> SRDY_O_vga,
		MRDY_I			=> MRDY_O,
		ADDR_I			=> ADDR_O,
		SDAT_I			=> MDAT_O,
		SDAT_O			=> SDAT_O_vga,

		-- VGA signals
		vga_clk_out		=> sys_vga_clk,
		vga_red			=> sys_vga_red,
		vga_green		=> sys_vga_green,
		vga_blue		=> sys_vga_blue,
		vga_blank_n		=> sys_vga_blank_n,
		vga_sync_n		=> sys_vga_sync_n,
		vga_hsync		=> sys_vga_hsync,
		vga_vsync		=> sys_vga_vsync	
	);

ssram_bufg: bufg
	port map
	(
		o  => ssram_clk,  
		i  => dcm_clk0
	);

inst_DCM_BASE_0 : DCM_BASE
	generic map (
		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
		CLKIN_PERIOD => 10.0 , -- Specify period of input clock in ns from 1.25 to 1000.00
		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
									 --   an integer from 0 to 15
		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
	port map (
		CLK0 => dcm_clk0,         -- 0 degree DCM CLK ouptput
		CLK180 => open,     -- 180 degree DCM CLK output
		CLK270 => open,     -- 270 degree DCM CLK output
		CLK2X => open,       -- 2X DCM CLK output
		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
		CLK90 => open,       -- 90 degree DCM CLK output
		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
		CLKFX => open,       -- DCM CLK synthesis out (M/D)
		CLKFX180 => open, -- 180 degree CLK synthesis out
		LOCKED => dcm_locked,     -- DCM LOCK status output
		CLKFB => sys_ssram_clk_fb,       -- DCM clock feedback
		CLKIN => clk,       -- Clock input (from IBUFG, BUFG or DCM)
		RST => rst            -- DCM asynchronous reset input
	);

	------------------------------------------------------------------
END;