# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, the Altera Quartus II License Agreement, # the Altera MegaCore Function License Agreement, or other # applicable license agreement, including, without limitation, # that your use is for the sole purpose of programming logic # devices manufactured by Altera and sold by Altera or its # authorized distributors. Please refer to the applicable # agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 15.0.0 Build 145 04/22/2015 SJ Web Edition # Date created = 15:44:09 November 26, 2016 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # JMips_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # # -------------------------------------------------------------------------- # # # Copyright (C) 1991-2014 Altera Corporation. All rights reserved. # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, the Altera Quartus II License Agreement, # the Altera MegaCore Function License Agreement, or other # applicable license agreement, including, without limitation, # that your use is for the sole purpose of programming logic # devices manufactured by Altera and sold by Altera or its # authorized distributors. Please refer to the applicable # agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 14.0.0 Build 200 06/17/2014 SJ Web Edition # Date created = 08:21:44 May 14, 2015 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # JMips_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE EP4CE22F17C6 set_global_assignment -name TOP_LEVEL_ENTITY mips_sys set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:21:44 MAY 14, 2015" set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (VHDL)" set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id eda_simulation set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH TestBench -section_id eda_simulation set_global_assignment -name EDA_TEST_BENCH_NAME TestBench -section_id eda_simulation set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id TestBench set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_mips_top -section_id TestBench set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY OFF -section_id eda_simulation set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id eda_simulation set_global_assignment -name EDA_FLATTEN_BUSES OFF -section_id eda_simulation set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/run_msim_gate_vhdl.do -section_id eda_simulation set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT simulation/modelsim/run_msim_gate_vhdl.do -section_id eda_simulation set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/CPUs/MIPS/src/bootloader.ROM.vhd -section_id TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/misc/async_types.vhd -section_id TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/CPUs/MIPS/src/async_defs.vhd -section_id TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/misc/async_port_wb.vhd -section_id TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/misc/gpio_wb.vhd -section_id TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/misc/rom_wb.vhd -section_id TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/uart/uart_wb.vhd -section_id TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/uart/uart_rx_sim.vhd -section_id TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/uart/uart_tx_sim.vhd -section_id TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/CPUs/MIPS/src/core/mips_types.vhd -section_id TestBench set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../lib/CPUs/MIPS/src/tb_mips_top.vhd -section_id TestBench set_global_assignment -name ALLOW_REGISTER_MERGING ON set_global_assignment -name ALLOW_REGISTER_DUPLICATION ON set_global_assignment -name ALLOW_REGISTER_RETIMING ON set_global_assignment -name OPTIMIZATION_MODE BALANCED set_global_assignment -name ENABLE_OCT_DONE OFF set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id eda_simulation set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 4 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk set_location_assignment PIN_E1 -to sys_nmi_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_nmi_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_rst_n set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE test.stp set_location_assignment PIN_L3 -to sys_leds[7] set_location_assignment PIN_B1 -to sys_leds[6] set_location_assignment PIN_F3 -to sys_leds[5] set_location_assignment PIN_D1 -to sys_leds[4] set_location_assignment PIN_A11 -to sys_leds[3] set_location_assignment PIN_B13 -to sys_leds[2] set_location_assignment PIN_A13 -to sys_leds[1] set_location_assignment PIN_A15 -to sys_leds[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_leds[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_leds[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_leds[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_leds[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_leds[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_leds[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_leds[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_leds[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to altera_reserved_tck set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to altera_reserved_tdi set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to altera_reserved_tdo set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to altera_reserved_tms set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[12] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[11] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[10] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[9] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[8] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_addr[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_ba[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_ba[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_cas_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_cke set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_clk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_cs_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[15] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[14] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[13] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[12] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[11] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[10] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[9] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[8] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_data[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_dqm[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_dqm[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_ras_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_sdram_we_n set_location_assignment PIN_P2 -to sys_sdram_addr[0] set_location_assignment PIN_N5 -to sys_sdram_addr[1] set_location_assignment PIN_N6 -to sys_sdram_addr[2] set_location_assignment PIN_M8 -to sys_sdram_addr[3] set_location_assignment PIN_P8 -to sys_sdram_addr[4] set_location_assignment PIN_T7 -to sys_sdram_addr[5] set_location_assignment PIN_N8 -to sys_sdram_addr[6] set_location_assignment PIN_T6 -to sys_sdram_addr[7] set_location_assignment PIN_R1 -to sys_sdram_addr[8] set_location_assignment PIN_P1 -to sys_sdram_addr[9] set_location_assignment PIN_N2 -to sys_sdram_addr[10] set_location_assignment PIN_N1 -to sys_sdram_addr[11] set_location_assignment PIN_L4 -to sys_sdram_addr[12] set_location_assignment PIN_G2 -to sys_sdram_data[0] set_location_assignment PIN_G1 -to sys_sdram_data[1] set_location_assignment PIN_L8 -to sys_sdram_data[2] set_location_assignment PIN_K5 -to sys_sdram_data[3] set_location_assignment PIN_K2 -to sys_sdram_data[4] set_location_assignment PIN_J2 -to sys_sdram_data[5] set_location_assignment PIN_J1 -to sys_sdram_data[6] set_location_assignment PIN_R7 -to sys_sdram_data[7] set_location_assignment PIN_T4 -to sys_sdram_data[8] set_location_assignment PIN_T2 -to sys_sdram_data[9] set_location_assignment PIN_T3 -to sys_sdram_data[10] set_location_assignment PIN_R3 -to sys_sdram_data[11] set_location_assignment PIN_R5 -to sys_sdram_data[12] set_location_assignment PIN_P3 -to sys_sdram_data[13] set_location_assignment PIN_N3 -to sys_sdram_data[14] set_location_assignment PIN_K1 -to sys_sdram_data[15] set_location_assignment PIN_M7 -to sys_sdram_ba[0] set_location_assignment PIN_M6 -to sys_sdram_ba[1] set_location_assignment PIN_L1 -to sys_sdram_cas_n set_location_assignment PIN_L7 -to sys_sdram_cke set_location_assignment PIN_R4 -to sys_sdram_clk set_location_assignment PIN_L2 -to sys_sdram_ras_n set_location_assignment PIN_R6 -to sys_sdram_dqm[0] set_location_assignment PIN_T5 -to sys_sdram_dqm[1] set_location_assignment PIN_C2 -to sys_sdram_we_n set_location_assignment PIN_P6 -to sys_sdram_cs_n set_location_assignment PIN_H1 -to spi_clk set_location_assignment PIN_H2 -to spi_miso set_location_assignment PIN_C1 -to spi_mosi set_location_assignment PIN_D2 -to spi_ss_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_clk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_miso set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_mosi set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_ss_n set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_rx set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_tx set_location_assignment PIN_D3 -to uart_rx[0] set_location_assignment PIN_A3 -to uart_rx[1] set_location_assignment PIN_C3 -to uart_tx[0] set_location_assignment PIN_B4 -to uart_tx[1] set_global_assignment -name VHDL_FILE bootloader/bootloader.elf.ROM.vhd set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_flash_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_types.vhd set_global_assignment -name VHDL_FILE ../../../../lib/spi/src/spi_master.vhd set_global_assignment -name SDC_FILE JMips.sdc set_global_assignment -name VHDL_FILE ../../../../lib/emac/src/sipo.vhd set_global_assignment -name VHDL_FILE ../../../../lib/emac/src/piso.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb16.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/phy/altera/sdr_phy_de0nano.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/clock/altera/sdr_clk_cycloneive.vhd set_global_assignment -name VHDL_FILE ../../../../lib/SDRAM/ddr_sdr_v1_5/src/ctrl_sdr_wb32.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/uart_types.vhd set_global_assignment -name VHDL_FILE ../../../../lib/misc/bbfifo/src/bbfifo.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/generic/uart_tx.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/generic/uart_rx.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/generic/uart.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/generic/juart/juart_tx.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/generic/juart/juart_rx.vhd set_global_assignment -name VHDL_FILE ../../../../lib/uart/src/uart_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/src/dpram_1w1r1c_ra.vhd set_global_assignment -name VHDL_FILE ../../../../lib/JBUS/gpio/src/gpio_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/misc/utils_pkg.vhd set_global_assignment -name VHDL_FILE ../../../../lib/JBUS/memory/src/rom_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/JBUS/memory/src/ram_wb.vhd set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/src/dpram_1w1r2c_ra.vhd set_global_assignment -name VHDL_FILE ../../../../lib/rams/altera/src/dpram_2w2r2c_ra.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync_ctrl.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/reg_stage.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync_stage.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_sync.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/gray_counter.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_async_ctrl.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_async_stage.vhd set_global_assignment -name VHDL_FILE ../../../../lib/FIFO/src/fifo_async.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_types.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_top.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_icache.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_cop.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_biu.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd set_global_assignment -name VHDL_FILE ../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd set_global_assignment -name VHDL_FILE mips_sys.vhd set_global_assignment -name VHDL_FILE ../../../../lib/misc/jtag_reg_alt.vhd set_location_assignment PIN_M1 -to dip_sw[0] set_location_assignment PIN_T8 -to dip_sw[1] set_location_assignment PIN_B9 -to dip_sw[2] set_location_assignment PIN_M15 -to dip_sw[3] set_location_assignment PIN_R8 -to clk_brd set_location_assignment PIN_J15 -to rst_brd_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_brd set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_brd_n set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top