-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: User SDRAM component adjustments
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

package sdram_config is

	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
	
	constant LMR_REG_BASE		: natural := 0;
	constant LMR_REG_EXTENDED	: natural := 1;
	constant LMR_OP_NORMAL		: natural := 0;
	constant LMR_OP_RES_DLL		: natural := 2;
	constant LMR_BT_SEQ			: natural := 0;
	constant LMR_BT_ILVD		: natural := 1;
	constant LMR_BL2			: natural := 1;
	constant LMR_BL4			: natural := 2;
	constant LMR_BL8			: natural := 3;
	constant LMR_CL2			: natural := 2;
	constant LMR_CL3			: natural := 3;
	constant LMR_CL2_5			: natural := 6;
	
	-- DDR SDRAM Hardware defined constants
	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
	constant ENABLE_PRE_ALL		: std_logic := '1';
	constant ENABLE_AUTO_PRE	: std_logic := '0';
	
	-- DDR-SDR TIMING constants ------------------------------------------------------------------
	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
	constant REFRESH_INTERVAL : real := 7.8125; -- us

	-- These values are for your SDRAM part (see datasheet) 
	constant TCAS : positive  := 2;   -- CAS latency [clocks]
	constant TRP  : positive  := 2;   -- precharge command period
	constant TRAS : positive  := 5;   -- active to precharge delay 
	constant TRFC : positive  := 8;   -- auto refresh command period
	constant TMRD : positive  := 2;   -- load mode register command cylce time
	constant TRCD : positive  := 2;   -- active to read or write delay !
	constant TWR  : positive  := 2;   -- write recovery time

	constant PWR_UP_WAIT : natural := 222; -- µs

	subtype user_tag_t is unsigned(3 downto 0);

	----------------------------------------------------------------------------------------------
	
end sdram_config;