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-- Company: 
-- Engineer:
--
-- Create Date:    18:09:51 10/22/05
-- Design Name:    
-- Module Name:    sipo - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sipo is
	 Generic (N    : integer := 8);
    Port ( rst    : in std_logic;
           clk    : in std_logic;
           ce     : in std_logic;
           d_in   : in std_logic;
           d_out  : out std_logic_vector(N-1 downto 0));
end sipo;

architecture Behavioral of sipo is

signal reg        : std_logic_vector(N-1 downto 0);

begin

process (rst, clk, ce, d_in, reg)
begin
   if rst ='1' then 
      reg <= (others => '0'); 
   elsif clk'event and clk='1' then  
      if ce = '1' then 
         reg <= d_in & reg((N-1) downto 1);
      end if; 
   end if;
   d_out <= reg;
end process;

end Behavioral;