/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1985 MIPS Computer Systems, Inc.
 * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
 * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
 */
#ifndef _ASM_REGDEF_H
#define _ASM_REGDEF_H

/*
 * Symbolic register names for 32 bit ABI
 */
#define zero			$0      /* wired zero */
#define AT				$1      /* assembler temp  - uppercase because of ".set at" */
#define v0				$2      /* return value */
#define v1				$3
#define a0				$4      /* argument registers */
#define a1				$5
#define a2				$6
#define a3				$7
#define t0				$8      /* caller saved */
#define t1				$9
#define t2				$10
#define t3				$11
#define t4				$12
#define t5				$13
#define t6				$14
#define t7				$15
#define s0				$16     /* callee saved */
#define s1				$17
#define s2				$18
#define s3				$19
#define s4				$20
#define s5				$21
#define s6				$22
#define s7				$23
#define t8				$24     /* caller saved */
#define t9				$25
#define jp				$25     /* PIC jump register */
#define k0				$26     /* kernel scratch */
#define k1				$27
#define gp				$28     /* global pointer */
#define sp				$29     /* stack pointer */
#define fp				$30     /* frame pointer */
#define s8				$30		/* same like fp! */
#define ra				$31     /* return address */

/* CP0 registers */
#define	CP0_INDEX		$0		/* R3000 available */
#define	CP0_RANDOM		$1		/* R3000 available */
#define	CP0_ENTRYLO		$2		/* R3000 available */
#define	CP0_CONTEXT		$4		/* R3000 available */
#define	CP0_BADDR		$8		/* R3000 available */
#define	CP0_ENTRYHI		$10		/* R3000 available */
#define	CP0_SR			$12		/* R3000 available */
#define	CP0_CR			$13		/* R3000 available */
#define	CP0_EPC			$14		/* R3000 available */
#define	CP0_PRID		$15		/* R3000 available */

/* Status register masks */
#define	SR_MASK_IEC		0x00000001
#define	SR_MASK_KUC		0x00000002
#define	SR_MASK_IEP		0x00000004
#define	SR_MASK_KUP		0x00000008
#define	SR_MASK_IEO		0x00000010
#define	SR_MASK_KUO		0x00000020
#define	SR_MASK_IM		0x0000FF00
#define	SR_MASK_DS		0x00FF0000
#define	SR_MASK_RE		0x01000000
#define	SR_MASK_CU		0xF0000000

/* Cause register masks */
#define	CR_MASK_EXC		0x0000007C
#define	CR_MASK_IP		0x0000FF00
#define	CR_MASK_CE		0x40000000
#define	CR_MASK_BD		0x80000000

#endif /* _ASM_REGDEF_H */