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-- Company: 
-- Engineer: 
-- 
-- Create Date:    00:28:57 07/10/2006 
-- Design Name: 
-- Module Name:    adder_registered - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use std.textio.all; --  Imports the standard textio package.

library work;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity eval_fixed_ja is
	Generic (
	        nbits : integer := 8;
	        nbits_int : integer := 0
			  );
	Port
	(
		srst			: in std_logic;
		clk			: in std_logic;
		di1			: in std_logic_vector(nbits-1 downto 0);
		di2			: in std_logic_vector(nbits-1 downto 0);
		in_valid		: in std_logic;
		do				: out std_logic_vector(nbits-1 downto 0);
		out_valid	: out std_logic
	);
			  
end eval_fixed_ja;

architecture Behavioral of eval_fixed_ja is
signal op1, op2 : sfixed(nbits_int downto -(nbits-1));
signal result : sfixed(2*nbits_int downto -(2*nbits-1));
begin

op1 <= to_sfixed(di1, op1);
op2 <= to_sfixed(di2, op2);

do <= to_slv(resize(result, op1, false, false));

---------------------------------------------------------------------
process(srst, clk, in_valid, di1, di2)
begin
	if rising_edge(clk) then
		if srst = '1' then
			result <= (others => '0');
		elsif in_valid = '1' then
			result <= op1 * op2;
		end if;
		out_valid <= in_valid;
	end if;	
end process;


---------------------------------------------------------------------
end Behavioral;