--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    11:25:45 10/15/05
-- Design Name:    
-- Module Name:    vga_ctrl_top - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.vga_types.all;
use work.cpu_pkg.all;

entity vga_ctrl_top is
	Generic
	(
		tsvga			: vga_timespec_t := ts_vga_1280_1024_72
	);
	Port
	(
		sys_rst_in		: in std_logic;
		sys_clk_in		: in std_logic;
		
		-- VGA signals
		sys_vga_clk_in	: in  std_logic;
		sys_vga_clk_out	: out std_logic;
		sys_vga_clk_ce	: in  std_logic;
		sys_vga_red		: out unsigned(7 downto 0);
		sys_vga_green	: out unsigned(7 downto 0);
		sys_vga_blue	: out unsigned(7 downto 0);
		sys_vga_blank_n	: out std_logic;
		sys_vga_sync_n	: out std_logic;
		sys_vga_hsync	: out std_logic;
		sys_vga_vsync	: out std_logic;
		
		-- Buttons and LEDs
		sys_btn			: in unsigned(4 downto 0);
		sys_dip			: in unsigned(7 downto 0);
		sys_led			: out unsigned(8 downto 0)
	);
end vga_ctrl_top;

architecture Behavioral of vga_ctrl_top is

	-- System signal
	signal rst                    : std_logic;
	signal clk                    : std_logic;
	signal vga_clk                : std_logic;

	--	Timing
	signal src_pos_x		   		: natural range 0 to tsvga.ts_h.ncyc_scan-1;
	signal src_pos_y		      	: natural range 0 to tsvga.ts_v.ncyc_scan-1;

	--	Backend signals
	signal scan_rdy				: std_logic;
	signal ctrl_scan_en			: std_logic;
	signal color_in				: color_array_t;
	signal color_op				: color_op_t;
	signal color_en				: unsigned (VGA_NUM_CH-1 downto 0);

	signal stat_vga_rdy			: std_logic;
	signal stat_hready			: std_logic;
	signal stat_vready			: std_logic;
	signal stat_scan			: std_logic;
	signal stat_hscan			: std_logic;
	signal stat_vscan			: std_logic;
	signal stat_hsync			: std_logic;
	signal stat_vsync			: std_logic;
	signal stat_hpos			: natural range 0 to tsvga.ts_h.ncyc_scan-1;
	signal stat_vpos			: natural range 0 to tsvga.ts_v.ncyc_scan-1;

	--	CG signals
	signal cg_en				: std_logic;
	signal cg_rdy				: std_logic;
	signal cg_draw				: std_logic;
	signal cg_clr_screen		: std_logic;
	signal cg_clr_line			: std_logic;
	signal cg_din				: unsigned(7 downto 0);
	signal cg_dout				: unsigned(7 downto 0);
	signal cg_ascii_we			: std_logic;
	signal cg_posy_we			: std_logic;
	signal cg_posx_we			: std_logic;
	signal cg_color				: color_t;
	signal cg_csr_pos_x			: natural range 0 to 80-1;
	signal cg_csr_pos_y			: natural range 0 to 32-1;

	-- CPU signals
	signal cpu_rst					: std_logic;
	signal cpu_ce					: std_logic;
	signal cpu_int_in				: std_logic;
	signal cpu_int_ack				: std_logic;
	signal cpu_we					: std_logic;
	signal cpu_re					: std_logic;
	signal cpu_io_sel				: std_logic;
	signal cpu_din 					: dmem_data_t;
	signal cpu_dout					: dmem_data_t;
	signal cpu_addr					: dmem_addr_t;
	signal cpu_xrom_data			: dmem_data_t;

	signal cpu_led					: dmem_data_t;
	signal cpu_red					: dmem_data_t;
	signal cpu_green				: dmem_data_t;
	signal cpu_blue					: dmem_data_t;
	signal cpu_color				: color_t;
	signal proc_color				: color_t;
	
begin

inst_vga_backend : entity work.vga_backend
	GENERIC MAP
	(
		tsvga						=> tsvga
	)
	PORT MAP
	(
		-- System signals
		sys_rst			=> rst,
		sys_clk			=> clk,
		
		-- Color channels
		color_in		=> color_in,
		color_op		=> color_op,
		color_en		=> color_en,

		-- Control signals
		ctrl_scan_en	=> ctrl_scan_en,

		-- Status signals
		stat_vga_rdy	=> stat_vga_rdy,
		stat_scan		=> stat_scan,
		stat_hsync		=> stat_hsync,
		stat_vsync		=> stat_vsync,
		stat_hready		=> stat_hready,
		stat_vready		=> stat_vready,
		stat_hscan		=> stat_hscan,
		stat_vscan		=> stat_vscan,
		stat_hpos		=> stat_hpos,
		stat_vpos		=> stat_vpos,
		
		-- VGA domain signals
		vga_clk_in		=> sys_vga_clk_in,
		vga_clk_ce		=> sys_vga_clk_ce,
		vga_red			=> sys_vga_red,
		vga_green		=> sys_vga_green,
		vga_blue		=> sys_vga_blue,
		vga_blank_n		=> sys_vga_blank_n,
		vga_sync_n		=> sys_vga_sync_n,
		vga_hsync		=> sys_vga_hsync,
		vga_vsync		=> sys_vga_vsync
	);

	vga_clk			<= sys_vga_clk_in;
	ctrl_scan_en	<= '1';
	color_en(0)		<= '1';
	color_en(1)		<= cg_draw;
	color_in(0)		<= cpu_color;
	color_in(1)		<= cg_color; --(X"FF", X"FF", X"FF", X"FF");	-- white opaque
	color_op		<= op_over;

	inst_char_gen : entity work.char_gen
	GENERIC MAP
	(
		tsvga				=> tsvga,
		CHARACTER_SCALE		=> 1,
		CHAR_ROM_SIZE_X		=> 8,	-- Pixels
		CHAR_ROM_SIZE_Y		=> 16,	-- Pixels
		CHAR_ROM_DEPTH		=> 256,	-- Chars
		MAX_CHAR_PER_LINE	=> 80,	-- Chars
		MAX_LINE_PER_FRAME	=> 32,	-- Chars
		CHAR_SPACING_X		=> 0, 	-- Pixels
		CHAR_SPACING_Y		=> 0,	-- Pixels
		SCREEN_OFFSET_X		=> 16,	-- Pixels
		SCREEN_OFFSET_Y		=> 16	-- Pixels
	)		
	PORT MAP
	(
	    rst				=> rst,
	    sys_clk			=> clk,
	    vga_clk			=> vga_clk,
	    ce				=> cg_en,
	    frame_pulse		=> scan_rdy,
	    clr_screen		=> cg_clr_screen,
	    clr_line		=> cg_clr_line,
	    din				=> cg_din,
	    dout			=> cg_dout,
	    ascii_we		=> cg_ascii_we,
	    posy_we			=> cg_posy_we,
	    posx_we			=> cg_posx_we,
	    ready			=> cg_rdy,
	    scan_pos_x_in	=> stat_hpos,
	    scan_pos_y_in	=> stat_vpos,
	   	csr_pos_x_out	=> cg_csr_pos_x,
	   	csr_pos_y_out	=> cg_csr_pos_y,
	    char_draw_en	=> cg_draw
    );

	inst_cpu_embedded: entity work.cpu_embedded
	PORT MAP
	(
		rst => cpu_rst,
		clk => clk,
		ce => cpu_ce,
		int_in => cpu_int_in,
		int_ack => cpu_int_ack,
		xmem_we => cpu_we,
		xmem_re => cpu_re,
		xmem_din => cpu_din,
		xmem_dout => cpu_dout,
		xmem_addr => cpu_addr,
		io_sel => cpu_io_sel
	);

	inst_xrom: entity work.xrom
	PORT MAP
	(
		clk			=> clk,
		ce			=> cpu_ce,
		addr		=> cpu_addr,
		dout 		=> cpu_xrom_data
	);

	---------------------------------------------------------------------------------------------
	rst             <= sys_rst_in;
	clk				<= sys_clk_in;

	scan_rdy		<= stat_hready and stat_vready;

	cg_en 			<= stat_scan;
	cpu_ce			<= '1';
	
	---------------------------------------------------------------------------------------------
led_out: process (clk)
	begin
		if rising_edge(clk) then
			sys_led	<= '0' & cpu_led;
		end if;
	end process;

	---------------------------------------------------------------------------------------------
cpu_reg_read:
	process(clk, cpu_io_sel, cpu_xrom_data)
	variable reg : dmem_data_t;
	begin
		
		if rising_edge(clk) then
			case cpu_addr is
			when X"00" =>	-- 00
				reg := "000" & unsigned(sys_btn(4 downto 0));
			when X"01" =>	-- 01 
				reg := cpu_led;
			when X"05" =>	-- 05 
				reg := unsigned(sys_dip);
			when X"0B" =>
				reg := "000000" & cg_rdy & '0';
			when others => null;
			end case;
		end if;	
		
		cpu_din <= cpu_xrom_data;
		if cpu_io_sel = '1' then
			cpu_din <= reg;
		end if;	

	end process;
	
------------------------------------------------------------------
cpu_reg_write:
	process(rst, clk)
	variable addr : unsigned(dmem_addr_t'length-1 downto 0);
	begin
		if (rst = '1') then
			cpu_led <= (others => '0');
			cg_din				<= (others => '0');
			cg_posy_we			<= '0';
			cg_posx_we			<= '0';
			cg_ascii_we			<= '0';
			cg_clr_line			<= '0';
			cg_clr_screen		<= '0';
			cpu_red				<= X"80";
			cpu_green			<= X"80";
			cpu_blue			<= X"80";
			
		elsif rising_edge(clk) then
			cg_posy_we	<= '0';
			cg_posx_we	<= '0';
			cg_ascii_we	<= '0';
			cg_clr_line			<= '0';
			cg_clr_screen		<= '0';
			addr := cpu_addr;
			if cpu_we = '1' then	
				if cpu_io_sel = '1' then
					case addr is
						when X"01" =>	-- 01
							cpu_led <= cpu_dout;
						when X"02" =>	-- 04
							cpu_red <= cpu_dout;
						when X"03" =>	-- 04
							cpu_green <= cpu_dout;
						when X"04" =>	-- 04
							cpu_blue <= cpu_dout;
						when X"08" =>	-- 08
							cg_din 		<= cpu_dout;
						    cg_posx_we	<= '1';
						when X"09" =>	-- 09
							cg_din 		<= cpu_dout;
						    cg_posy_we	<= '1';
						when X"0A" =>	-- 0A
							cg_din	 	<= cpu_dout;
							cg_ascii_we	<= '1';
						when X"0B" =>	-- 0B
							cg_clr_screen	<= cpu_dout(0);
							cg_clr_line		<= cpu_dout(1);
						when others => null;
					end case;
				end if;	
			end if;	
		end if;	
	end process;

	---------------------------------------------------------------------------------------------
	--- Test
	---------------------------------------------------------------------------------------------
	cpu_start: process (clk)
	begin
		if rising_edge(vga_clk) then
			if rst = '1' then
				cpu_rst <= '1';
			else	
				cpu_rst <= not stat_vga_rdy;
			end if;
		end if;	
	end process;

	color_sel: process (vga_clk)
	begin
		if rising_edge(vga_clk) and scan_rdy = '1' then
			cpu_color	<= (cpu_red, cpu_green, cpu_blue, X"00");
		end if;
	end process;

	color_ctrl: process (clk)
	variable enable : std_logic;
	begin
		if rising_edge(clk) then
			if (rst = '1') then
				src_pos_x	<= 0;
				src_pos_y	<= 0;
			elsif stat_scan = '1' then
				if src_pos_x < tsvga.ts_h.ncyc_scan-1 then
					src_pos_x	<= src_pos_x + 1;
				else	
					src_pos_x	<= 0;
					if src_pos_y < tsvga.ts_v.ncyc_scan-1 then
						src_pos_y	<= src_pos_y + 1;
					else	
						src_pos_y	<= 0;
					end if;	
				end if;	
			end if;
		end if;
	end process;

	color_proc: process (src_pos_x, src_pos_y)
	begin
		proc_color		<= (X"00", X"00", X"00", X"00");
		if src_pos_y = 0 then
			proc_color <= (X"00", X"FF", X"00", X"00");
		elsif src_pos_y = (tsvga.ts_v.ncyc_scan-1) then
			proc_color <= (X"00", X"FF", X"00", X"00");
		elsif src_pos_x = 0 then
			proc_color <= (X"FF", X"00", X"00", X"00");
		elsif src_pos_x = (tsvga.ts_h.ncyc_scan-1) then
			proc_color <= (X"00", X"00", X"FF", X"00");
		end if;	
	end process;
	
end Behavioral;