#
#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
#     FOR A PARTICULAR PURPOSE.
#     
#     (c) Copyright 2005 Xilinx, Inc.
#     All rights reserved.
#

CONFIG STEPPING = "ES";

# Bus clock nets
NET sys_clk_in TNM_NET = "sys_clk_in";
TIMESPEC "TS_sys_clk_in" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;

NET "inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
TIMESPEC TS_unrelate = FROM sys_clk_in TO vga_clk TIG;

NET sys_clk_in LOC = AE14;
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET sys_rstn_in LOC = D6;
NET sys_rstn_in PULLUP;
NET sys_rstn_in TIG;
NET sys_rstn_in IOSTANDARD = LVCMOS33;


////////////////////////////////////////////////////////////////////////////
// Buttons, LEDs, and DIP Switches
////////////////////////////////////////////////////////////////////////////
# GPLED 0-3
NET "sys_led<0>" LOC = "G5"; #GPLED0
NET "sys_led<1>" LOC = "G6"; #GPLED1
NET "sys_led<2>" LOC = "A11"; #GPLED2
NET "sys_led<3>" LOC = "A12"; #GPLED3
# North-East-South-West-Center LEDs
NET "sys_led<4>" LOC = "F9"; # W LED
NET "sys_led<5>" LOC = "E2"; # N LED
NET "sys_led<6>" LOC = "E10"; # E LED
NET "sys_led<7>" LOC = "A5"; # S LED
NET "sys_led<8>" LOC = "C6"; # C LED
NET "sys_led<*>" TIG;
NET "sys_led<*>" SLEW = SLOW;
NET "sys_led<*>" DRIVE = 2;
NET "sys_led<*>" IOSTANDARD = LVCMOS33;
# North-East-South-West-Center Buttons
NET "sys_btn<0>" LOC = "E9"; # W Button
NET "sys_btn<1>" LOC = "E7"; # N Button
NET "sys_btn<2>" LOC = "F10"; # E Button
NET "sys_btn<3>" LOC = "A6"; # S Button
NET "sys_btn<4>" LOC = "B6"; # C Button
NET "sys_btn<*>" TIG;
NET "sys_btn<*>" PULLDOWN;
NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
# Dip Switches 1-8
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
NET "sys_dip<*>" PULLDOWN;
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
NET "sys_dip<*>" TIG;

#------------------------------------------------------------------------------
# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
#------------------------------------------------------------------------------

NET sys_vga_blue<0> LOC = M21; # VGA_B0
NET sys_vga_blue<1> LOC = M26; # VGA_B1
NET sys_vga_blue<2> LOC = L26; # VGA_B2
NET sys_vga_blue<3> LOC = C5;  # VGA_B3
NET sys_vga_blue<4> LOC = C7;  # VGA_B4
NET sys_vga_blue<5> LOC = B7;  # VGA_B5
NET sys_vga_blue<6> LOC = G8;  # VGA_B6
NET sys_vga_blue<7> LOC = F8;  # VGA_B7
NET sys_vga_blue<*> IOSTANDARD = LVCMOS33;
NET sys_vga_blue<*> SLEW = FAST;
NET sys_vga_blue<*> DRIVE = 8;

NET sys_vga_clk  LOC = AF8;
NET sys_vga_clk  IOSTANDARD = LVDCI_33;
NET sys_vga_clk  SLEW = FAST;
NET sys_vga_clk  DRIVE = 8;

NET sys_vga_green<0> LOC = M22; # VGA_G0
NET sys_vga_green<1> LOC = M23; # VGA_G1
NET sys_vga_green<2> LOC = M20; # VGA_G2
NET sys_vga_green<3> LOC = E4;  # VGA_G3
NET sys_vga_green<4> LOC = D3;  # VGA_G4
NET sys_vga_green<5> LOC = H7;  # VGA_G5
NET sys_vga_green<6> LOC = H8;  # VGA_G6
NET sys_vga_green<7> LOC = C1;  # VGA_G7
NET sys_vga_green<*> IOSTANDARD = LVCMOS33;
NET sys_vga_green<*> SLEW = FAST;
NET sys_vga_green<*> DRIVE = 8;

NET sys_vga_hsync LOC = C10;
NET sys_vga_hsync SLEW = FAST;
NET sys_vga_hsync DRIVE = 8;
NET sys_vga_hsync IOSTANDARD = LVCMOS33;

NET sys_vga_red<0> LOC = N23; #VGA_R0
NET sys_vga_red<1> LOC = N24; #VGA_R1
NET sys_vga_red<2> LOC = N25; #VGA_R2
NET sys_vga_red<3> LOC = C2;  #VGA_R3
NET sys_vga_red<4> LOC = G7;  #VGA_R4
NET sys_vga_red<5> LOC = F7;  #VGA_R5
NET sys_vga_red<6> LOC = E5;  #VGA_R6
NET sys_vga_red<7> LOC = E6;  #VGA_R7
NET sys_vga_red<*> IOSTANDARD = LVCMOS33;
NET sys_vga_red<*> SLEW = FAST;
NET sys_vga_red<*> DRIVE = 8;

NET sys_vga_vsync LOC = A8;
NET sys_vga_vsync SLEW = FAST;
NET sys_vga_vsync DRIVE = 8;
NET sys_vga_vsync IOSTANDARD = LVCMOS33;

NET sys_vga_blank_n LOC = M24;
NET sys_vga_blank_n SLEW = FAST;
NET sys_vga_blank_n DRIVE = 8;
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;

NET sys_vga_sync_n LOC = L23;
NET sys_vga_sync_n SLEW = FAST;
NET sys_vga_sync_n DRIVE = 8;
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;