# -----------------------------------------------------------
include $(VHDL_HOME)/make/defs.mk
# -----------------------------------------------------------
include $(LIB_PATH)/CPUs/MIPS/ghdl/mips_core.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
include $(LIB_PATH)/emac/ghdl/emac_jbus.inc
include $(LIB_PATH)/VGA_ctrl/ghdl/vga_frontend_jb64.inc

# Configs
SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd
SRCS += $(LIB_PATH)/models/memory/sdram/mt46v16m16/mt46v16m16.vhd
SRCS += ../src/sdram_config_sim.vhd

# Clock Generator
SRCS += ../src/clockgen.vhd

# MIPS
SRCS += $(MIPS_CORE_SRCS)

# ROM
#vcom -explicit  -93 "Z:/work/repos/mips/src/bootloader/test.ROM.vhd"
SRCS += ../src/bootloader_flash.ROM.vhd
SRCS += $(LIB_PATH)/JBUS/memory/src/rom_wb.vhd

# RAMS 
SRCS += $(LIB_PATH)/rams/sim/src/dpram_1w1r2c_ro.vhd

# VGA
SRCS += $(VGA_FRONTEND_JB64_SRCS)

# UART
SRCS += $(LIB_PATH)/uart/src/uart_types.vhd
SRCS += $(LIB_PATH)/uart/src/sim/uart.vhd
SRCS += $(LIB_PATH)/uart/src/uart_wb.vhd

# PS2
SRCS += $(LIB_PATH)/ps2_port/src/debounce.vhd
SRCS += $(LIB_PATH)/ps2_port/src/ps2_core.vhd
SRCS += $(LIB_PATH)/ps2_port/src/ps2_phy_virtex.vhd
SRCS += $(LIB_PATH)/ps2_port/src/ps2_wb.vhd

# GPIO
SRCS += $(LIB_PATH)/JBUS/gpio/src/gpio_wb.vhd

# LCD
SRCS += $(LIB_PATH)/misc/lcd_port.vhd

# Async port
SRCS += $(LIB_PATH)/JBUS/async_port/src/async_types.vhd
SRCS += $(LIB_PATH)/JBUS/async_port/src/async_port_wb.vhd
SRCS += ../src/async_defs_sim.vhd

# Flash and USB
SRCS += $(LIB_PATH)/JBUS/flash_port/src/flash_port_wb.vhd

# Sync SRAM
SRCS += $(LIB_PATH)/SSRAM/src/package_utility.vhd
SRCS += $(LIB_PATH)/SSRAM/src/CY7C1354B.vhd
SRCS += $(LIB_PATH)/SSRAM/src/ssram_port_wb.vhd

# SDRAM
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb64.vhd

# AC-97
SRCS += $(LIB_PATH)/misc/singleshot.vhd
SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac_out.vhd
SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac_in.vhd
SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac_io.vhd
SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac97_wb.vhd

# Ethernet MAC
SRCS += $(EMAC_JBUS_SRCS)

# Top and TB
SRCS += ../src/mips_sys_sim.vhd
SRCS += ../src/tb_mips_sys.vhd

# Compile
TARGET := tb_mips_sys
ENTITY = tb_mips_sys
RUN_TIME := 10ms

GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit

include $(VHDL_HOME)/make/ghdl.mk