jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Compare commits

base: jens/vhdl:EMAC_R3
Branches Tags
jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
..
compare: jens/vhdl:EMAC_R2
Branches Tags
jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
1 Commits
EMAC_R3 .. EMAC_R2
Author SHA1 Message Date
jens 23afdea302 This commit was manufactured by cvs2svn to create tag 'EMAC_R2'. 
git-svn-id: http://moon:8086/svn/vhdl/tags/EMAC_R2@874 cc03376c-175c-47c8-b038-4cd826a8556b
 2010-04-07 18:44:43 +00:00
21 changed files with 1220 additions and 660 deletions
Expand all files Collapse all files
lib/emac/.directory_history
-2
View File
@@ -1,2 +0,0 @@
VHDL/lib/emac/emac_jb.vhd
lib/emac/emac_jb.vhd
+657
View File
@@ -0,0 +1,657 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use std.textio.all; -- Imports the standard textio package.
use work.utils_pkg.all;
ENTITY emac_jb IS
Generic
(
f_sysclk : real := 100.0;
TX_RAM_SIZE : natural := 2048
);
Port
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
INT_O : out STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
mii_rx_clk : in STD_LOGIC;
mii_rx_dv : in STD_LOGIC;
mii_rx_er : in STD_LOGIC;
mii_rx : in unsigned(7 downto 0);
mii_tx_clk : in STD_LOGIC;
mii_tx_en : out STD_LOGIC;
mii_tx_er : out STD_LOGIC;
mii_tx : out unsigned(7 downto 0);
mii_gtx_clk : out STD_LOGIC;
mii_crs : in STD_LOGIC;
mii_col : in STD_LOGIC
);
END emac_jb;
ARCHITECTURE behavior OF emac_jb IS
constant TX_RAM_ADDR_WIDTH : natural := NextExpBaseTwo(TX_RAM_SIZE);
subtype word_ptr_t is unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
-- Signals for EMAC connections
signal tx_fifo_din : unsigned(35 downto 0);
signal tx_fifo_dout : unsigned(35 downto 0);
signal tx_fifo_we : std_logic;
signal tx_fifo_re : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_full : std_logic;
signal rx_int_en : std_logic;
signal tx_int_en : std_logic;
signal irq_rx : std_logic;
signal irq_tx : std_logic;
signal tx_err : std_logic;
signal tx_flush_en : std_logic;
signal tx_flush_rdy : std_logic;
signal tx_flush_ptr_set : std_logic;
signal tx_commit_en : std_logic;
signal tx_flush_ptr : word_ptr_t;
signal host_data_we : std_logic;
signal host_data_reg : unsigned(31 downto 0);
signal host_tx_size : unsigned(15 downto 0);
signal tx_fill_size : word_ptr_t;
signal tx_fill_cnt : word_ptr_t;
signal tx_fill_ptr : word_ptr_t;
signal tx_fill_rdy : std_logic;
signal tx_fill_cnt_set : std_logic;
signal tx_fill_cnt_adv : std_logic;
signal tx_fill_ptr_set : std_logic;
signal tx_fill_ptr_adv : std_logic;
signal tx_alloc_OK : std_logic;
signal tx_alloc_req_en : std_logic;
signal tx_alloc_req : std_logic;
signal tx_alloc_ack : std_logic;
signal tx_nwords_free : word_ptr_t;
signal tx_alloc_base : word_ptr_t;
signal tx_alloc_size : word_ptr_t;
signal tx_alloc_en : std_logic;
signal tx_free_en : std_logic;
signal tx_uncommit_en : std_logic;
signal tx_fill_remain : unsigned(1 downto 0);
signal tx_xfer_size : word_ptr_t;
signal tx_xfer_ptr : word_ptr_t;
signal tx_xfer_cnt : word_ptr_t;
signal tx_xfer_en : std_logic;
signal tx_xfer_ptr_set : std_logic;
signal tx_xfer_ptr_adv : std_logic;
signal tx_xfer_cnt_set : std_logic;
signal tx_xfer_cnt_adv : std_logic;
signal tx_xfer_rdy : std_logic;
signal xfer_tag : unsigned(3 downto 0);
signal xfer_remain : unsigned(1 downto 0);
signal xfer_odd : std_logic;
signal xfer_remain_en : std_logic;
signal tx_ram_en_a : std_logic;
signal tx_ram_we_a : std_logic;
signal tx_ram_addr_a : unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
signal tx_ram_din_a : unsigned(35 downto 0);
signal tx_ram_dout_a : unsigned(35 downto 0);
signal tx_ram_en_b : std_logic;
signal tx_ram_we_b : std_logic;
signal tx_ram_addr_b : unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
signal tx_ram_din_b : unsigned(35 downto 0);
signal tx_ram_dout_b : unsigned(35 downto 0);
signal piso_din_be : unsigned(3 downto 0);
signal piso_din_rdy : std_logic;
signal tx_data_vld : std_logic;
subtype inter_frame_gap_cnt_t is natural range 0 to natural(1.0*f_sysclk)-1;
signal inter_frame_gap_cnt : inter_frame_gap_cnt_t;
signal inter_frame_gap_rdy : std_logic;
alias tx_ram_data_in_a is tx_ram_din_a(31 downto 0);
alias tx_ram_tag_in_a is tx_ram_din_a(35 downto 32);
alias tx_ram_data_out_a is tx_ram_dout_a(31 downto 0);
alias tx_ram_tag_out_a is tx_ram_dout_a(35 downto 32);
alias tx_ram_data_in_b is tx_ram_din_b(31 downto 0);
alias tx_ram_tag_in_b is tx_ram_din_b(35 downto 32);
alias tx_ram_data_out_b is tx_ram_dout_b(31 downto 0);
alias tx_ram_tag_out_b is tx_ram_dout_b(35 downto 32);
type host_tx_state_t is (host_tx_init, host_tx_flush, host_tx_idle, host_tx_alloc, host_tx_setup, host_tx_arm, host_tx_fill, host_tx_commit);
signal host_tx_s, host_tx_sn : host_tx_state_t;
type xfer_tx_state_t is (xfer_tx_init, xfer_tx_idle, xfer_tx_setup, xfer_wait, xfer_tx_active, xfer_tx_free);
signal xfer_tx_s, xfer_tx_sn : xfer_tx_state_t;
type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
constant piso_byte_mask_rom : piso_byte_mask_array_t :=
(
"1111",
"0001",
"0011",
"0111"
);
begin
SRDY_O <= CYC_I;
INT_O <= irq_rx or irq_tx;
mii_gtx_clk <= '0';
mii_tx_er <= tx_err;
tx_ram_tag_in_b <= "0000";
tx_ram_en_b <= '1';
tx_ram_we_b <= tx_uncommit_en or tx_flush_en;
tx_ram_addr_b <= tx_flush_ptr when (tx_flush_en = '1' or tx_uncommit_en = '1') else tx_xfer_ptr;
xfer_tag <= tx_ram_tag_out_b;
tx_ram_en_a <= '1';
tx_ram_we_a <= tx_commit_en or tx_fill_cnt_adv;
tx_ram_tag_in_a <= tx_fill_remain & "01" when tx_commit_en = '1' else "0000";
tx_ram_data_in_a <= resize(tx_fill_size, 16) & resize(tx_alloc_base, 16) when tx_commit_en = '1' else host_data_reg;
tx_ram_addr_a <= tx_alloc_base when tx_commit_en = '1' else tx_fill_ptr;
piso_din_be <= (others => '1');
tx_fifo_re <= piso_din_rdy;
tx_data_vld <= not tx_fifo_empty;
tx_fifo_din(35 downto 32) <= piso_byte_mask_rom(to_integer(xfer_remain)) when xfer_remain_en = '1' else "1111";
tx_fifo_din(31 downto 0) <= tx_ram_data_out_b;
------------------------------------------------------------------
host_tx_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
host_tx_s <= host_tx_init;
else
host_tx_s <= host_tx_sn;
end if;
end if;
end process;
host_tx_state:
process(host_tx_s, tx_flush_rdy, tx_alloc_req, tx_alloc_OK, tx_fill_rdy, host_data_we)
begin
tx_flush_en <= '0';
tx_flush_ptr_set <= '0';
tx_alloc_ack <= '0';
tx_fill_cnt_set <= '0';
tx_fill_cnt_adv <= '0';
tx_fill_ptr_set <= '0';
tx_fill_ptr_adv <= '0';
tx_commit_en <= '0';
tx_alloc_en <= '0';
host_tx_sn <= host_tx_s;
case host_tx_s is
when host_tx_init =>
tx_flush_ptr_set <= '1';
host_tx_sn <= host_tx_flush;
when host_tx_flush =>
tx_flush_en <= '1';
if tx_flush_rdy = '1' then
tx_flush_en <= '0';
host_tx_sn <= host_tx_idle;
end if;
when host_tx_idle =>
if tx_alloc_req = '1' then
host_tx_sn <= host_tx_alloc;
end if;
when host_tx_alloc =>
if tx_alloc_OK = '1' then
host_tx_sn <= host_tx_setup;
tx_alloc_ack <= '1';
end if;
when host_tx_setup =>
tx_fill_cnt_set <= '1';
tx_fill_ptr_set <= '1';
host_tx_sn <= host_tx_arm;
when host_tx_arm =>
tx_fill_ptr_adv <= '1';
tx_fill_cnt_adv <= '1';
host_tx_sn <= host_tx_fill;
when host_tx_fill =>
tx_fill_cnt_adv <= host_data_we;
tx_fill_ptr_adv <= not tx_fill_rdy and host_data_we;
if tx_alloc_req = '1' then
host_tx_sn <= host_tx_alloc;
elsif tx_fill_rdy = '1' then
host_tx_sn <= host_tx_commit;
end if;
when host_tx_commit =>
tx_commit_en <= '1';
tx_alloc_en <= '1';
host_tx_sn <= host_tx_idle;
when others =>
host_tx_sn <= host_tx_idle;
end case;
end process;
------------------------------------------------------------------
-- Allocation stuff
------------------------------------------------------------------
alloc_request_logic:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
tx_alloc_req <= '0';
elsif tx_alloc_req_en = '1' and tx_alloc_req = '0' then
tx_alloc_req <= '1';
tx_fill_remain <= host_tx_size(1 downto 0);
tx_fill_size <= host_tx_size(word_ptr_t'left+2 downto 2);
if host_tx_size(1 downto 0) /= "00" then
tx_fill_size <= host_tx_size(word_ptr_t'left+2 downto 2) + 1;
end if;
elsif tx_alloc_ack = '1' then
tx_alloc_req <= '0';
tx_alloc_size <= tx_fill_size;
end if;
end if;
end process;
------------------------------------------------------------------
alloc_base_logic:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_flush_en = '1' then
tx_alloc_base <= (others => '0');
elsif tx_commit_en = '1' then
tx_alloc_base <= tx_fill_ptr;
end if;
end if;
end process;
------------------------------------------------------------------
alloc_eval_logic:
process(CLK_I)
begin
if rising_edge(CLK_I) then
tx_alloc_OK <= '0';
if tx_alloc_req = '1' then
if tx_fill_size < tx_nwords_free then
tx_alloc_OK <= '1';
end if;
end if;
end if;
end process;
------------------------------------------------------------------
tx_nwords_free_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_flush_en = '1' then
tx_nwords_free <= (others => '1');
elsif tx_alloc_en = '1' then
tx_nwords_free <= tx_nwords_free - tx_fill_size;
elsif tx_free_en = '1' then
tx_nwords_free <= tx_nwords_free + tx_xfer_size;
end if;
end if;
end process;
------------------------------------------------------------------
tx_flush_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_flush_en = '0' then
tx_flush_rdy <= '0';
if tx_flush_ptr_set = '1' then
tx_flush_ptr <= (others => '1');
elsif tx_xfer_ptr_set = '1' then
tx_flush_ptr <= tx_ram_data_out_b(tx_flush_ptr'left downto 0);
end if;
elsif tx_flush_ptr /= 0 then
tx_flush_ptr <= tx_flush_ptr - 1;
else
tx_flush_rdy <= '1';
end if;
end if;
end process;
------------------------------------------------------------------
-- Fill stuff
------------------------------------------------------------------
tx_fill_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_fill_cnt_set = '1' then
tx_fill_rdy <= '0';
tx_fill_cnt <= tx_alloc_size;
elsif tx_fill_cnt_adv = '1' then
if tx_fill_cnt /= 0 then
tx_fill_cnt <= tx_fill_cnt - 1;
else
tx_fill_rdy <= '1';
end if;
end if;
end if;
end process;
tx_fill_pointer:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_fill_ptr_set = '1' then
tx_fill_ptr <= tx_alloc_base;
elsif tx_fill_ptr_adv = '1' then
tx_fill_ptr <= tx_fill_ptr + 1;
end if;
end if;
end process;
------------------------------------------------------------------
-- Transfer stuff
------------------------------------------------------------------
xfer_tx_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
xfer_tx_s <= xfer_tx_init;
else
xfer_tx_s <= xfer_tx_sn;
end if;
end if;
end process;
xfer_tx_state:
process(xfer_tx_s, xfer_tag, xfer_odd, tx_xfer_rdy, inter_frame_gap_rdy, tx_alloc_en, tx_fifo_full)
begin
tx_xfer_cnt_set <= '0';
tx_xfer_cnt_adv <= '0';
tx_xfer_ptr_set <= '0';
tx_xfer_ptr_adv <= '0';
tx_xfer_en <= '0';
xfer_remain_en <= '0';
tx_free_en <= '0';
tx_uncommit_en <= '0';
xfer_tx_sn <= xfer_tx_s;
case xfer_tx_s is
when xfer_tx_init =>
xfer_tx_sn <= xfer_tx_idle;
when xfer_tx_idle =>
if xfer_tag(0) = '1' then
tx_xfer_ptr_set <= '1';
tx_xfer_cnt_set <= '1';
xfer_tx_sn <= xfer_wait;
end if;
when xfer_wait =>
if inter_frame_gap_rdy = '1' then
xfer_tx_sn <= xfer_tx_setup;
end if;
when xfer_tx_setup =>
tx_uncommit_en <= '1';
tx_xfer_ptr_adv <= '1';
tx_xfer_cnt_adv <= '1';
xfer_tx_sn <= xfer_tx_active;
when xfer_tx_active =>
tx_xfer_en <= '1';
tx_xfer_cnt_adv <= not tx_fifo_full;
tx_xfer_ptr_adv <= not tx_fifo_full;
if tx_xfer_rdy = '1' then
xfer_remain_en <= xfer_odd;
tx_xfer_en <= '0';
tx_xfer_cnt_adv <= '0';
tx_xfer_ptr_adv <= '0';
xfer_tx_sn <= xfer_tx_free;
end if;
when xfer_tx_free =>
tx_free_en <= not tx_alloc_en;
if tx_alloc_en = '0' then
xfer_tx_sn <= xfer_tx_idle;
end if;
when others =>
xfer_tx_sn <= xfer_tx_idle;
end case;
end process;
------------------------------------------------------------------
interframe_gap_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_flush_en = '1' then
inter_frame_gap_rdy <= '1';
elsif tx_fifo_empty = '0' then
inter_frame_gap_rdy <= '0';
inter_frame_gap_cnt <= inter_frame_gap_cnt_t'high;
elsif inter_frame_gap_cnt /= 0 then
inter_frame_gap_cnt <= inter_frame_gap_cnt - 1;
else
inter_frame_gap_rdy <= '1';
end if;
end if;
end process;
------------------------------------------------------------------
tx_xfer_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if tx_xfer_cnt_set = '1' then
tx_xfer_size <= (others => '0');
tx_xfer_rdy <= '0';
tx_xfer_cnt <= tx_ram_data_out_b(tx_xfer_ptr'left+16 downto 16);
elsif tx_xfer_cnt_adv = '1' then
if tx_xfer_cnt /= 0 then
tx_xfer_cnt <= tx_xfer_cnt - 1;
tx_xfer_size <= tx_xfer_size + 1;
else
tx_xfer_rdy <= '1';
end if;
end if;
end if;
end process;
tx_xfer_pointer:
process(CLK_I)
begin
if rising_edge(CLK_I) then
tx_fifo_we <= tx_xfer_en;
if tx_xfer_ptr_set = '1' then
tx_xfer_ptr <= tx_ram_data_out_b(tx_xfer_ptr'left downto 0);
xfer_remain <= xfer_tag(3 downto 2);
xfer_odd <= '0';
if xfer_tag(3 downto 2) /= "00" then
xfer_odd <= '1';
end if;
elsif tx_xfer_ptr_adv = '1' then
tx_xfer_ptr <= tx_xfer_ptr + 1;
end if;
end if;
end process;
------------------------------------------------------------------
registers_write:
process(CLK_I)
begin
if rising_edge(CLK_I) then
host_data_we <= '0';
tx_alloc_req_en <= '0';
if RST_I = '1' then
rx_int_en <= '0';
tx_int_en <= '0';
tx_err <= '0';
elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(5 downto 2) is
when "0000" =>
tx_err <= DAT_I(31);
tx_alloc_req_en <= DAT_I(16);
tx_int_en <= DAT_I(5);
rx_int_en <= DAT_I(4);
when "0001" =>
if tx_alloc_req = '0' then
host_tx_size <= DAT_I(31 downto 16);
end if;
when "0010" =>
host_data_we <= '1';
host_data_reg <= DAT_I;
when others => null;
end case;
end if;
end if;
end process;
registers_read:
process(CLK_I)
begin
if rising_edge(CLK_I) then
ACK_O <= '0';
if (STB_I and CYC_I) = '1' then
ACK_O <= not WE_I;
DAT_O <= (others => '0');
case ADDR_I(5 downto 2) is
when "0000" =>
DAT_O(31) <= tx_err;
DAT_O(30) <= mii_rx_er;
DAT_O(29) <= mii_col;
DAT_O(28) <= mii_crs;
DAT_O(16) <= tx_alloc_req;
DAT_O(5) <= tx_int_en;
DAT_O(4) <= rx_int_en;
when "0001" =>
DAT_O(31 downto 16) <= host_tx_size;
when "0010" =>
when others => null;
end case;
end if;
end if;
end process;
inst_tx_ram : entity work.dpram_2w2r
GENERIC MAP
(
addr_width => TX_RAM_ADDR_WIDTH,
data_width => 36
)
PORT MAP
(
clk_a => CLK_I,
clk_b => CLK_I,
en_a => tx_ram_en_a,
en_b => tx_ram_en_b,
we_a => tx_ram_we_a,
we_b => tx_ram_we_b,
addr_a => tx_ram_addr_a,
addr_b => tx_ram_addr_b,
din_a => tx_ram_din_a,
din_b => tx_ram_din_b,
dout_a => tx_ram_dout_a,
dout_b => tx_ram_dout_b
);
-- Instantiate synchronous FIFO
inst_tx_fifo: entity work.fifo_async
GENERIC MAP
(
addr_width => 5,
data_width => 36,
do_last_read_update => true
)
PORT MAP
(
rst => RST_I,
clk_w => CLK_I,
clk_r => mii_tx_clk,
we => tx_fifo_we,
re => tx_fifo_re,
fifo_full => tx_fifo_full,
fifo_empty => tx_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => tx_fifo_din,
data_r => tx_fifo_dout
);
inst_piso : entity work.piso
GENERIC MAP
(
data_width_in => 32,
data_width_out => 8,
msb_first => false
)
PORT MAP
(
rst => RST_I,
clk => mii_tx_clk,
din_vld => tx_data_vld,
din_rdy => piso_din_rdy,
din_be => tx_fifo_dout(35 downto 32),
din => tx_fifo_dout(31 downto 0),
dout_en => mii_tx_en,
dout => mii_tx
);
irq_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
irq_tx <= tx_int_en;
irq_rx <= rx_int_en;
end if;
end process;
end behavior;
lib/emac/sim/.directory_history
-8
View File
@@ -1,8 +0,0 @@
VHDL/lib/emac/sim/tb_emac_jb.fdo
VHDL/lib/emac/sim/tb_serdes.fdo
VHDL/lib/emac/sim/tb_emac_jb.wdo
VHDL/lib/emac/sim/tb_serdes.wdo
VHDL/lib/emac/sim/tb_serdes.fdo
VHDL/lib/emac/sim/tb_serdes.wdo
lib/emac/sim/tb_crc32.fdo
-14
View File
@@ -1,14 +0,0 @@
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
##
vlib work
vcom -explicit -93 "../../misc/utils_pkg.vhd"
vcom -explicit -93 "../src/crc32.vhd"
vcom -explicit -93 "../src/tb_crc32.vhd"
vsim -t 1ps -lib work tb_crc32
view wave
do {tb_crc32.wdo}
view structure
view signals
run 1 us
lib/emac/sim/tb_crc32.wdo
-25
View File
@@ -1,25 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_crc32/clk
add wave -noupdate -format Logic /tb_crc32/rst
add wave -noupdate -format Logic /tb_crc32/din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/din
add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/crc32
add wave -noupdate -format Logic /tb_crc32/crc32_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_crc32/test_data
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {667016 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {1050 ns}
lib/emac/sim/tb_emac_jb.fdo
+11 -3
View File
@@ -3,12 +3,20 @@
## ##
vlib work vlib work
vcom -explicit -93 "../../misc/utils_pkg.vhd" vcom -explicit -93 "../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../misc/dpram_2w2r.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../src/piso.vhd" vcom -explicit -93 "../src/piso.vhd"
vcom -explicit -93 "../src/sipo.vhd" vcom -explicit -93 "../src/sipo.vhd"
vcom -explicit -93 "../src/tb_serdes.vhd" vcom -explicit -93 "../src/shifter.vhd"
vsim -t 1ps -lib work tb_serdes vcom -explicit -93 "../src/emac_jb.vhd"
vcom -explicit -93 "../src/tb_emac_jb.vhd"
vsim -t 1ps -lib work tb_emac_jb
view wave view wave
do {tb_serdes.wdo} do {tb_emac_jb.wdo}
view structure view structure
view signals view signals
lib/emac/sim/tb_emac_jb.wdo
+150 -39
View File
@@ -1,47 +1,158 @@
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_serdes/clk add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Logic /tb_serdes/rst add wave -noupdate -format Logic /tb_emac_jb/rst
add wave -noupdate -format Logic /tb_emac_jb/cyc_i
add wave -noupdate -format Logic /tb_emac_jb/stb_i
add wave -noupdate -format Logic /tb_emac_jb/we_i
add wave -noupdate -format Literal /tb_emac_jb/sel_i
add wave -noupdate -format Logic /tb_emac_jb/ack_o
add wave -noupdate -format Logic /tb_emac_jb/int_o
add wave -noupdate -format Logic /tb_emac_jb/mrdy_i
add wave -noupdate -format Logic /tb_emac_jb/srdy_o
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_o
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_clk
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_rx
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_dv
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_tx
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_en
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_er
add wave -noupdate -format Logic /tb_emac_jb/mii_crs
add wave -noupdate -format Logic /tb_emac_jb/mii_col
add wave -noupdate -format Logic /tb_emac_jb/mii_gtx_clk
add wave -noupdate -divider {Ethernet MAC}
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal /tb_emac_jb/emac_action
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_err
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_flush_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_flush_rdy
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_free_en
add wave -noupdate -format Literal -radix unsigned /tb_emac_jb/inst_emac_jb/tx_nwords_free
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_flush_ptr
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_cnt_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_cnt_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_cnt
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_ptr_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_ptr_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_ptr
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_alloc_base
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_alloc_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_ok
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_req_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_commit_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_req
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_ack
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_en_a
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_en_b
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/host_tx_s
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_out_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_out_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_in_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_in_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_addr_b
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_we_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_out_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_out_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_in_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_in_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_addr_a
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_we_a
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_free_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_ptr_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_ptr_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_ptr
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_cnt_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_cnt_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_cnt
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_rdy
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_data_vld
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_tag
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_remain
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/xfer_odd
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/xfer_remain_en
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_tx_s
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/piso_din_be
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/piso_din_rdy
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_we
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_full
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_din
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_empty
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_re
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_dout
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/host_tx_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/host_data_we
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/host_data_reg
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/inter_frame_gap_cnt
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/inter_frame_gap_rdy
add wave -noupdate -divider Shifter
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal /tb_emac_jb/shift_sa
add wave -noupdate -format Logic /tb_emac_jb/shift_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/shift_din
add wave -noupdate -format Logic /tb_emac_jb/shift_dout_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/shift_dout
add wave -noupdate -divider PiSo add wave -noupdate -divider PiSo
add wave -noupdate -format Logic /tb_serdes/clk add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Logic /tb_serdes/piso_din_vld add wave -noupdate -format Logic /tb_emac_jb/piso_din_vld
add wave -noupdate -format Logic /tb_serdes/piso_din_rdy add wave -noupdate -format Logic /tb_emac_jb/piso_din_rdy
add wave -noupdate -format Literal /tb_serdes/piso_din_be add wave -noupdate -format Literal /tb_emac_jb/piso_din_be
add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_din add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso_din
add wave -noupdate -format Logic /tb_serdes/piso_dout_vld add wave -noupdate -format Logic /tb_emac_jb/piso_dout_en
add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_dout add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso_dout
add wave -noupdate -format Logic /tb_serdes/piso_dout_en add wave -noupdate -format Logic /tb_emac_jb/inst_piso/pre_fin
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso/din_reg
add wave -noupdate -format Literal /tb_emac_jb/inst_piso/din_be_reg
add wave -noupdate -format Logic /tb_emac_jb/inst_piso/din_vld_reg
add wave -noupdate -format Literal /tb_emac_jb/inst_piso/shift_cnt_pipe
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso/shift_pipe
add wave -noupdate -format Literal /tb_emac_jb/inst_piso/vld_pipe
add wave -noupdate -format Logic /tb_emac_jb/piso2_din_vld
add wave -noupdate -format Logic /tb_emac_jb/piso2_din_rdy
add wave -noupdate -format Literal /tb_emac_jb/piso2_din_be
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso2_din
add wave -noupdate -format Logic /tb_emac_jb/piso2_dout_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso2_dout
add wave -noupdate -format Logic /tb_emac_jb/piso2_enable
add wave -noupdate -format Logic /tb_emac_jb/inst_piso2/pre_fin
add wave -noupdate -format Logic /tb_emac_jb/inst_piso2/rdy
add wave -noupdate -format Literal /tb_emac_jb/inst_piso2/shift_cnt_pipe
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso2/shift_pipe
add wave -noupdate -format Literal /tb_emac_jb/inst_piso2/vld_pipe
add wave -noupdate -divider SiPo add wave -noupdate -divider SiPo
add wave -noupdate -format Logic /tb_serdes/clk add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/clk
add wave -noupdate -format Logic /tb_serdes/sipo_enable add wave -noupdate -format Logic /tb_emac_jb/sipo_enable
add wave -noupdate -format Logic /tb_serdes/sipo_rst add wave -noupdate -format Logic /tb_emac_jb/sipo_din_vld
add wave -noupdate -format Logic /tb_serdes/sipo_din_vld add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_din add wave -noupdate -format Logic /tb_emac_jb/sipo_dout_en
add wave -noupdate -format Logic /tb_serdes/sipo_dout_vld add wave -noupdate -format Logic /tb_emac_jb/sipo_dout_vld
add wave -noupdate -format Logic /tb_serdes/sipo_dout_en add wave -noupdate -format Literal /tb_emac_jb/sipo_dout_be
add wave -noupdate -format Literal /tb_serdes/sipo_dout_be add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo_dout
add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_dout add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/pre_fin
add wave -noupdate -divider PiSo add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/abort
add wave -noupdate -format Logic /tb_serdes/clk add wave -noupdate -format Literal /tb_emac_jb/inst_sipo/shift_cnt_pipe
add wave -noupdate -format Logic /tb_serdes/piso2_din_vld add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_sipo/shift_pipe
add wave -noupdate -format Logic /tb_serdes/piso2_din_rdy add wave -noupdate -format Logic /tb_emac_jb/sipo2_enable
add wave -noupdate -format Literal /tb_serdes/piso2_din_be add wave -noupdate -format Logic /tb_emac_jb/sipo2_rst
add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_din add wave -noupdate -format Logic /tb_emac_jb/sipo2_din_vld
add wave -noupdate -format Logic /tb_serdes/piso2_dout_vld add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo2_din
add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_dout add wave -noupdate -format Logic /tb_emac_jb/sipo2_dout_en
add wave -noupdate -format Logic /tb_serdes/piso2_dout_en add wave -noupdate -format Logic /tb_emac_jb/sipo2_dout_vld
add wave -noupdate -divider SiPo add wave -noupdate -format Literal /tb_emac_jb/sipo2_dout_be
add wave -noupdate -format Logic /tb_serdes/clk add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo2_dout
add wave -noupdate -format Logic /tb_serdes/sipo2_enable add wave -noupdate -format Literal /tb_emac_jb/inst_sipo2/shift_cnt_pipe
add wave -noupdate -format Logic /tb_serdes/sipo2_rst add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_sipo2/shift_pipe
add wave -noupdate -format Logic /tb_serdes/sipo2_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_din
add wave -noupdate -format Logic /tb_serdes/sipo2_dout_vld
add wave -noupdate -format Logic /tb_serdes/sipo2_dout_en
add wave -noupdate -format Literal /tb_serdes/sipo2_dout_be
add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_dout
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {19757882 ps} 0} {{Cursor 2} {49999912163 ps} 0} {{Cursor 3} {49999529250 ps} 0} WaveRestoreCursors {{Cursor 1} {19622640 ps} 0} {{Cursor 2} {121551751 ps} 0}
configure wave -namecolwidth 150 configure wave -namecolwidth 150
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
lib/emac/sim/tb_emac_top_jb.fdo
+1 -1
View File
@@ -13,7 +13,7 @@ vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async.vhd" vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../src/piso.vhd" vcom -explicit -93 "../src/piso.vhd"
vcom -explicit -93 "../src/sipo.vhd" vcom -explicit -93 "../src/sipo.vhd"
vcom -explicit -93 "../src/crc32.vhd" vcom -explicit -93 "../src/shifter.vhd"
vcom -explicit -93 "../src/emac_types.vhd" vcom -explicit -93 "../src/emac_types.vhd"
vcom -explicit -93 "../src/emac_rx.vhd" vcom -explicit -93 "../src/emac_rx.vhd"
vcom -explicit -93 "../src/emac_tx.vhd" vcom -explicit -93 "../src/emac_tx.vhd"
lib/emac/sim/tb_emac_top_jb.wdo
+12 -18
View File
@@ -35,8 +35,10 @@ add wave -noupdate -format Literal /tb_emac_top_jb/pkt_count
add wave -noupdate -divider {Packet generator} add wave -noupdate -divider {Packet generator}
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/pkt_delay
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nbytes add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nbytes
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nwords add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nwords
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/pkt_delay
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/host_s add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/host_s
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_in add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_in
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_out add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_out
@@ -86,6 +88,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_a add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_b add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count_en
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din_vld add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din_vld
@@ -101,18 +104,16 @@ add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/s
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_en add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_en
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rst
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_ok add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_ok
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rdy add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rdy add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_ok add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_ok
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rst
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_num_ok add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_num_ok
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_addr add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_addr
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_cnt add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_cnt
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_vld
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fcs_chk_ok
add wave -noupdate -divider TX add wave -noupdate -divider TX
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst
@@ -120,6 +121,10 @@ add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/d
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_in add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_in
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_out add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_out
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_din add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_dout add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_we add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_we
@@ -168,26 +173,15 @@ add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/p
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_vld add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_vld
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_en add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_vld
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_rst
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_din_vld
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_req add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_req
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_ack add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_ack
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {11284359462 ps} 0} {{Cursor 2} {49999967706 ps} 0} {{Cursor 3} {49999529250 ps} 0} WaveRestoreCursors {{Cursor 1} {47057926829 ps} 0} {{Cursor 2} {50099085366 ps} 0} {{Cursor 3} {18156000484 ps} 0}
configure wave -namecolwidth 150 configure wave -namecolwidth 150
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
@@ -201,4 +195,4 @@ configure wave -gridperiod 100
configure wave -griddelta 40 configure wave -griddelta 40
configure wave -timeline 1 configure wave -timeline 1
update update
WaveRestoreZoom {11283753554 ps} {11286295500 ps} WaveRestoreZoom {0 ps} {24865002750 ps}
lib/emac/src/.directory_history
-8
View File
@@ -1,8 +0,0 @@
VHDL/lib/emac/emac_jb.vhd
VHDL/lib/emac/src/emac_jb.vhd
VHDL/lib/emac/src/emac_jb.vhd
VHDL/lib/emac/src/tb_emac_jb.vhd
VHDL/lib/emac/src/tb_serdes.vhd
VHDL/lib/emac/src/tb_serdes.vhd
lib/emac/src/crc32.vhd
-63
View File
@@ -1,63 +0,0 @@
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use std.textio.all; -- Imports the standard textio package.
use work.utils_pkg.all; -- Imports the standard textio package.
ENTITY crc32 IS
Generic
(
crc32_init : unsigned(31 downto 0) := X"00000000"
);
Port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
din_vld : in STD_LOGIC;
din : in unsigned(7 downto 0);
crc32_vld : out STD_LOGIC;
crc32_out : out unsigned(31 downto 0)
);
END crc32;
ARCHITECTURE behavior OF crc32 IS
type crc_table_t is array (0 to 15) of unsigned(31 downto 0);
constant crc_table : crc_table_t :=
(
X"4DBDF21C", X"500AE278", X"76D3D2D4", X"6B64C2B0",
X"3B61B38C", X"26D6A3E8", X"000F9344", X"1DB88320",
X"A005713C", X"BDB26158", X"9B6B51F4", X"86DC4190",
X"D6D930AC", X"CB6E20C8", X"EDB71064", X"F0000000"
);
signal crc0 : unsigned(31 downto 0);
signal crc1 : unsigned(31 downto 0);
signal crc2 : unsigned(31 downto 0);
--------------------------------------------------------------------------
begin
crc1 <= X"0" & crc0(31 downto 4) xor crc_table(to_integer(crc0(3 downto 0) xor din(3 downto 0)));
crc2 <= X"0" & crc1(31 downto 4) xor crc_table(to_integer(crc1(3 downto 0) xor din(7 downto 4)));
crc32_out <= crc0;
--------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
crc32_vld <= not rst and din_vld;
if rst = '1' then
crc0 <= crc32_init;
elsif din_vld = '1' then
crc0 <= crc2;
end if;
end if;
end process;
--------------------------------------------------------------------------
end behavior;
lib/emac/src/emac_rx.vhd
+3 -47
View File
@@ -104,15 +104,8 @@ ARCHITECTURE behavior OF emac_rx IS
signal mac_chk_addr : mac_addr_t; signal mac_chk_addr : mac_addr_t;
signal Gbps_en : std_logic; signal Gbps_en : std_logic;
signal fcs_chk_en : std_logic;
signal rx_en : std_logic; signal rx_en : std_logic;
signal fcs_vld : std_logic;
signal fcs_din_vld : std_logic;
signal fcs_din : unsigned(7 downto 0);
signal fcs : unsigned(31 downto 0);
signal fcs_chk_OK : std_logic;
type host_state_t is (host_init, host_flush, host_idle); type host_state_t is (host_init, host_flush, host_idle);
signal host_s, host_sn : host_state_t; signal host_s, host_sn : host_state_t;
@@ -150,11 +143,11 @@ begin
ram_addr_a <= xfer_ptr; ram_addr_a <= xfer_ptr;
ram_we_a <= xfer_en and sipo32_dout_vld; ram_we_a <= xfer_en and sipo32_dout_vld;
xfer_vld <= (mac_chk_OK or mac_chk_BC or xfer_promiscious) and (not fcs_chk_en or fcs_chk_OK); xfer_vld <= mac_chk_OK or mac_chk_BC or xfer_promiscious;
cmd_fifo_we <= commit_en and xfer_vld; cmd_fifo_we <= commit_en and xfer_vld;
cmd_fifo_re <= ctrl_in.pkt_free_en; cmd_fifo_re <= ctrl_in.pkt_free_en;
cmd_pkt_valid_in <= fcs_chk_OK; cmd_pkt_valid_in <= '1';
cmd_mac_ok_in <= mac_chk_OK; cmd_mac_ok_in <= mac_chk_OK;
cmd_bcast_in <= mac_chk_BC; cmd_bcast_in <= mac_chk_BC;
cmd_nbytes_in <= byte_count; cmd_nbytes_in <= byte_count;
@@ -201,7 +194,6 @@ host2xfer_sync_register:
if rising_edge(mii_rx_clk) then if rising_edge(mii_rx_clk) then
xfer_promiscious <= ctrl_in.promiscious; xfer_promiscious <= ctrl_in.promiscious;
Gbps_en <= ctrl_in.Gbps_en; Gbps_en <= ctrl_in.Gbps_en;
fcs_chk_en <= ctrl_in.fcs_chk_en;
mac_addr <= ctrl_in.mac_addr; mac_addr <= ctrl_in.mac_addr;
xfer_ram_limit <= host_ram_limit; xfer_ram_limit <= host_ram_limit;
end if; end if;
@@ -267,11 +259,7 @@ byte_counter:
begin begin
if rising_edge(mii_rx_clk) then if rising_edge(mii_rx_clk) then
if byte_count_rst = '1' then if byte_count_rst = '1' then
if fcs_chk_en = '0' then byte_count <= (others => '0');
byte_count <= to_unsigned(0, RAM_ADDR_WIDTH);
else
byte_count <= unsigned(to_signed(-4, RAM_ADDR_WIDTH));
end if;
elsif sipo32_en = '1' and sipo32_din_vld = '1' then elsif sipo32_en = '1' and sipo32_din_vld = '1' then
byte_count <= byte_count + 1; byte_count <= byte_count + 1;
end if; end if;
@@ -484,38 +472,6 @@ inst_sipo32 : entity work.sipo
); );
inst_fcs: entity work.crc32
GENERIC MAP
(
crc32_init => X"00000000"
)
PORT MAP
(
rst => byte_count_rst,
clk => mii_rx_clk,
din_vld => fcs_din_vld,
din => fcs_din,
crc32_vld => fcs_vld,
crc32_out => fcs
);
fcs_din <= sipo32_din;
fcs_din_vld <= sipo32_en and sipo32_din_vld;
fcs_chk_register:
process(mii_rx_clk)
begin
if rising_edge(mii_rx_clk) then
if fcs_vld = '1' then
fcs_chk_OK <= '0';
if fcs = X"2144DF1C" then
fcs_chk_OK <= '1';
end if;
end if;
end if;
end process;
mii_input_register: mii_input_register:
process(mii_rx_clk) process(mii_rx_clk)
begin begin
lib/emac/src/emac_top_jb.vhd
-6
View File
@@ -91,8 +91,6 @@ registers_write:
rx_ctrl_in.promiscious <= '0'; rx_ctrl_in.promiscious <= '0';
tx_ctrl_in.Gbps_en <= '0'; tx_ctrl_in.Gbps_en <= '0';
rx_ctrl_in.Gbps_en <= '0'; rx_ctrl_in.Gbps_en <= '0';
tx_ctrl_in.fcs_gen_en <= '0';
rx_ctrl_in.fcs_chk_en <= '0';
elsif (STB_I and CYC_I and WE_I) = '1' then elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(5 downto 2) is case ADDR_I(5 downto 2) is
@@ -100,7 +98,6 @@ registers_write:
when "0000" => when "0000" =>
rx_ctrl_in.reset <= DAT_I(31); rx_ctrl_in.reset <= DAT_I(31);
rx_ctrl_in.Gbps_en <= DAT_I(30); rx_ctrl_in.Gbps_en <= DAT_I(30);
rx_ctrl_in.fcs_chk_en <= DAT_I(29);
rx_ctrl_in.promiscious <= DAT_I(23); rx_ctrl_in.promiscious <= DAT_I(23);
rx_ctrl_in.pkt_req_en <= DAT_I(17); rx_ctrl_in.pkt_req_en <= DAT_I(17);
rx_ctrl_in.pkt_free_en <= DAT_I(16); rx_ctrl_in.pkt_free_en <= DAT_I(16);
@@ -113,7 +110,6 @@ registers_write:
when "0010" => when "0010" =>
tx_ctrl_in.reset <= DAT_I(31); tx_ctrl_in.reset <= DAT_I(31);
tx_ctrl_in.Gbps_en <= DAT_I(30); tx_ctrl_in.Gbps_en <= DAT_I(30);
tx_ctrl_in.fcs_gen_en <= DAT_I(29);
tx_ctrl_in.pkt_alloc_en <= DAT_I(17); tx_ctrl_in.pkt_alloc_en <= DAT_I(17);
tx_ctrl_in.pkt_commit_en <= DAT_I(16); tx_ctrl_in.pkt_commit_en <= DAT_I(16);
tx_int_en <= DAT_I(4); tx_int_en <= DAT_I(4);
@@ -164,7 +160,6 @@ registers_read:
DAT_O <= (others => '0'); DAT_O <= (others => '0');
DAT_O(31) <= rx_ctrl_out.reset_busy; DAT_O(31) <= rx_ctrl_out.reset_busy;
DAT_O(30) <= rx_ctrl_in.Gbps_en; DAT_O(30) <= rx_ctrl_in.Gbps_en;
DAT_O(29) <= rx_ctrl_in.fcs_chk_en;
DAT_O(23) <= rx_ctrl_in.promiscious; DAT_O(23) <= rx_ctrl_in.promiscious;
DAT_O(19) <= rx_ctrl_out.pkt_bcast; DAT_O(19) <= rx_ctrl_out.pkt_bcast;
DAT_O(18) <= rx_ctrl_out.pkt_mac_match; DAT_O(18) <= rx_ctrl_out.pkt_mac_match;
@@ -183,7 +178,6 @@ registers_read:
DAT_O <= (others => '0'); DAT_O <= (others => '0');
DAT_O(31) <= tx_ctrl_out.reset_busy; DAT_O(31) <= tx_ctrl_out.reset_busy;
DAT_O(30) <= tx_ctrl_in.Gbps_en; DAT_O(30) <= tx_ctrl_in.Gbps_en;
DAT_O(29) <= tx_ctrl_in.fcs_gen_en;
DAT_O(24) <= tx_ctrl_out.pkt_done; DAT_O(24) <= tx_ctrl_out.pkt_done;
DAT_O(17) <= tx_ctrl_out.pkt_alloc_req; DAT_O(17) <= tx_ctrl_out.pkt_alloc_req;
DAT_O(16) <= tx_ctrl_out.pkt_armed; DAT_O(16) <= tx_ctrl_out.pkt_armed;
lib/emac/src/emac_tx.vhd
+20 -112
View File
@@ -96,27 +96,10 @@ ARCHITECTURE behavior OF emac_tx IS
signal piso8_dout_vld : std_logic; signal piso8_dout_vld : std_logic;
signal piso8_din_rdy : std_logic; signal piso8_din_rdy : std_logic;
signal piso8_din_vld : std_logic;
signal piso8_dout : unsigned(3 downto 0); signal piso8_dout : unsigned(3 downto 0);
signal piso8_din : unsigned(7 downto 0);
signal reset_pipe : unsigned(31 downto 0); signal reset_pipe : unsigned(31 downto 0);
signal Gbps_en : std_logic; signal Gbps_en : std_logic;
signal fcs_gen_en : std_logic;
signal fcs_inject_en : std_logic;
signal fcs_rst : std_logic;
signal fcs_en : unsigned(7 downto 0);
signal fcs_vld : std_logic;
signal fcs_din_vld : std_logic;
signal fcs : unsigned(31 downto 0);
signal fcs_rev_endian : unsigned(31 downto 0);
signal mii_fifo_we : std_logic;
signal mii_fifo_re : std_logic;
signal mii_fifo_full : std_logic;
signal mii_fifo_empty : std_logic;
signal mii_fifo_re_dly : unsigned(7 downto 0);
subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
-- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps -- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
@@ -161,8 +144,8 @@ begin
ram_din_a(35 downto 32) <= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111"; ram_din_a(35 downto 32) <= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111";
ram_addr_a <= fill_ptr; ram_addr_a <= fill_ptr;
piso32_din <= preamble(preamble_addr) when preamble_en = '1' else fcs_rev_endian when fcs_inject_en = '1' else ram_dout_b(31 downto 0); piso32_din <= preamble(preamble_addr) when preamble_en = '1' else ram_dout_b(31 downto 0);
piso32_din_be <= "1111" when (preamble_en = '1' or fcs_inject_en = '1') else ram_dout_b(35 downto 32); piso32_din_be <= "1111" when preamble_en = '1' else ram_dout_b(35 downto 32);
cmd_fifo_we <= commit_en; cmd_fifo_we <= commit_en;
cmd_fifo_re <= uncommit_en; cmd_fifo_re <= uncommit_en;
@@ -176,8 +159,6 @@ begin
fill_cnt_en <= fill_bsy and din_vld; fill_cnt_en <= fill_bsy and din_vld;
mem_free_en <= not mem_free_ack(0) and mem_free_ack(1); mem_free_en <= not mem_free_ack(0) and mem_free_ack(1);
fcs_rev_endian <= fcs(7 downto 0) & fcs(15 downto 8) & fcs(23 downto 16) & fcs(31 downto 24);
------------------------------------------------------------------ ------------------------------------------------------------------
reset_gen: reset_gen:
process(clk) process(clk)
@@ -378,7 +359,6 @@ host2xfer_sync_register:
begin begin
if rising_edge(mii_tx_clk) then if rising_edge(mii_tx_clk) then
Gbps_en <= ctrl_in.Gbps_en; Gbps_en <= ctrl_in.Gbps_en;
fcs_gen_en <= ctrl_in.fcs_gen_en;
end if; end if;
end process; end process;
@@ -431,8 +411,9 @@ interframe_gap_counter:
begin begin
if rising_edge(mii_tx_clk) then if rising_edge(mii_tx_clk) then
ifg_idle <= '0'; ifg_idle <= '0';
if reset_en = '1' or mii_fifo_empty = '0' then if reset_en = '1' or piso32_dout_vld = '1' then
ifg_cnt <= ifg_cnt_t'high; ifg_cnt <= ifg_cnt_t'high;
ifg_idle <= '1';
elsif ifg_cnt /= 0 then elsif ifg_cnt /= 0 then
ifg_cnt <= ifg_cnt - 1; ifg_cnt <= ifg_cnt - 1;
else else
@@ -494,7 +475,7 @@ xfer_state_next:
end process; end process;
xfer_state: xfer_state:
process(xfer_s, ifg_idle, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en) process(xfer_s, ifg_idle, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy)
begin begin
piso32_din_vld <= '0'; piso32_din_vld <= '0';
@@ -503,8 +484,6 @@ xfer_state:
xfer_set <= '0'; xfer_set <= '0';
xfer_en <= '0'; xfer_en <= '0';
xfer_free_en <= '0'; xfer_free_en <= '0';
fcs_rst <= '0';
fcs_inject_en <= '0';
uncommit_en <= '0'; uncommit_en <= '0';
xfer_sn <= xfer_s; xfer_sn <= xfer_s;
@@ -515,18 +494,15 @@ xfer_state:
xfer_sn <= xfer_idle; xfer_sn <= xfer_idle;
when xfer_idle => when xfer_idle =>
if cmd_fifo_empty = '0' then if cmd_fifo_empty = '0' and piso32_din_rdy = '1' then
xfer_sn <= xfer_start; xfer_sn <= xfer_start;
end if; end if;
when xfer_start => when xfer_start =>
if cmd_fifo_empty = '0' and ifg_idle = '1' then xfer_set <= '1';
xfer_sn <= xfer_preamble0; xfer_sn <= xfer_preamble0;
end if;
when xfer_preamble0 => when xfer_preamble0 =>
xfer_set <= '1';
fcs_rst <= '1';
preamble_addr <= 0; preamble_addr <= 0;
preamble_en <= '1'; preamble_en <= '1';
piso32_din_vld <= '1'; piso32_din_vld <= '1';
@@ -547,28 +523,23 @@ xfer_state:
piso32_din_vld <= xfer_bsy; piso32_din_vld <= xfer_bsy;
xfer_en <= '1'; xfer_en <= '1';
if xfer_bsy = '0' then if xfer_bsy = '0' then
xfer_sn <= xfer_stop; uncommit_en <= '1';
xfer_free_en <= '1';
xfer_sn <= xfer_crc;
end if; end if;
when xfer_crc =>
xfer_sn <= xfer_stop;
when xfer_stop => when xfer_stop =>
if piso32_dout_vld = '0' then if piso32_dout_vld = '0' then
xfer_sn <= xfer_finish; xfer_sn <= xfer_finish;
if fcs_gen_en = '1' then
xfer_sn <= xfer_crc;
end if;
end if;
when xfer_crc =>
fcs_inject_en <= piso32_din_rdy;
piso32_din_vld <= '1';
if piso32_din_rdy = '1' then
xfer_sn <= xfer_finish;
end if; end if;
when xfer_finish => when xfer_finish =>
uncommit_en <= '1'; if ifg_idle = '0' then
xfer_free_en <= '1';
xfer_sn <= xfer_idle; xfer_sn <= xfer_idle;
end if;
when others => when others =>
xfer_sn <= xfer_idle; xfer_sn <= xfer_idle;
@@ -640,69 +611,7 @@ inst_piso32 : entity work.piso
); );
piso32_dout_en <= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_rdy; piso32_dout_en <= '1' when Gbps_en = '1' else piso8_din_rdy;
fcs_enable_gen:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
if fcs_rst = '1' then
fcs_en <= (others => '0');
elsif piso32_dout_vld = '1' then
fcs_en <= fcs_en(fcs_en'left-1 downto 0) & '1';
end if;
end if;
end process;
fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en;
inst_fcs: entity work.crc32
GENERIC MAP
(
crc32_init => X"00000000"
)
PORT MAP
(
rst => fcs_rst,
clk => mii_tx_clk,
din_vld => fcs_din_vld,
din => piso32_dout,
crc32_vld => fcs_vld,
crc32_out => fcs
);
mii_fifo_re_dly_gen:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
mii_fifo_re_dly <= mii_fifo_re_dly(mii_fifo_re_dly'left-1 downto 0) & not mii_fifo_empty;
end if;
end process;
mii_fifo_re <= mii_fifo_re_dly(mii_fifo_re_dly'left) when Gbps_en = '1' else (piso8_din_rdy and mii_fifo_re_dly(mii_fifo_re_dly'left));
mii_fifo_we <= piso32_dout_vld;
-- Instantiate synchronous FIFO
inst_mii_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => 4,
data_width => piso32_dout'length,
do_last_read_update => true
)
PORT MAP
(
rst => reset_en,
clk => mii_tx_clk,
we => mii_fifo_we,
re => mii_fifo_re,
fifo_full => mii_fifo_full,
fifo_empty => mii_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => piso32_dout,
data_r => piso8_din
);
inst_piso8 : entity work.piso inst_piso8 : entity work.piso
GENERIC MAP GENERIC MAP
@@ -715,16 +624,15 @@ inst_piso8 : entity work.piso
( (
rst => reset_en, rst => reset_en,
clk => mii_tx_clk, clk => mii_tx_clk,
din_vld => piso8_din_vld, din_vld => piso32_dout_vld,
din_rdy => piso8_din_rdy, din_rdy => piso8_din_rdy,
din_be => "11", din_be => "11",
din => piso8_din, din => piso32_dout,
dout_vld => piso8_dout_vld, dout_vld => piso8_dout_vld,
dout_en => '1', dout_en => '1',
dout => piso8_dout dout => piso8_dout
); );
piso8_din_vld <= not mii_fifo_empty and mii_fifo_re_dly(mii_fifo_re_dly'left);
mii_output_register: mii_output_register:
process(mii_tx_clk) process(mii_tx_clk)
@@ -732,8 +640,8 @@ mii_output_register:
if rising_edge(mii_tx_clk) then if rising_edge(mii_tx_clk) then
mii_tx_er <= '0'; mii_tx_er <= '0';
if Gbps_en = '1' then if Gbps_en = '1' then
mii_tx_en <= piso8_din_vld; mii_tx_en <= piso32_dout_vld;
mii_tx <= piso8_din; mii_tx <= piso32_dout;
else else
mii_tx_en <= piso8_dout_vld; mii_tx_en <= piso8_dout_vld;
mii_tx <= "0000" & piso8_dout; mii_tx <= "0000" & piso8_dout;
lib/emac/src/emac_types.vhd
-2
View File
@@ -18,7 +18,6 @@ package emac_types is
type tx_ctrl_in_t is record type tx_ctrl_in_t is record
Gbps_en : std_logic; Gbps_en : std_logic;
reset : std_logic; reset : std_logic;
fcs_gen_en : std_logic;
tx_size : unsigned(15 downto 0); tx_size : unsigned(15 downto 0);
pkt_commit_en : std_logic; pkt_commit_en : std_logic;
pkt_alloc_en : std_logic; pkt_alloc_en : std_logic;
@@ -35,7 +34,6 @@ package emac_types is
type rx_ctrl_in_t is record type rx_ctrl_in_t is record
Gbps_en : std_logic; Gbps_en : std_logic;
reset : std_logic; reset : std_logic;
fcs_chk_en : std_logic;
pkt_read_en : std_logic; pkt_read_en : std_logic;
pkt_req_en : std_logic; pkt_req_en : std_logic;
pkt_free_en : std_logic; pkt_free_en : std_logic;
lib/emac/src/piso.vhd
+33 -15
View File
@@ -31,18 +31,19 @@ ARCHITECTURE behavior OF piso IS
constant num_shifts : natural := data_width_in/data_width_out; constant num_shifts : natural := data_width_in/data_width_out;
signal pre_fin : STD_LOGIC; signal pre_fin : STD_LOGIC;
signal rdy : STD_LOGIC;
signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0); signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0);
signal shift_pipe : unsigned(data_width_in-1 downto 0); signal shift_pipe : unsigned(data_width_in-1 downto 0);
signal vld_pipe : unsigned(num_shifts-1 downto 0); signal vld_pipe : unsigned(num_shifts-1 downto 0);
signal din_reg : unsigned(data_width_in-1 downto 0); signal din_reg : unsigned(data_width_in-1 downto 0);
signal din_be_reg : unsigned(num_shifts-1 downto 0); signal din_be_reg : unsigned(num_shifts-1 downto 0);
signal din_reg_empty : STD_LOGIC; signal din_vld_reg : STD_LOGIC;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
begin begin
pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left-1); pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left-1);
din_rdy <= din_reg_empty; din_rdy <= rdy;
dout_vld <= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0); dout_vld <= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
dout <= shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first dout <= shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
else shift_pipe(data_width_out-1 downto 0); else shift_pipe(data_width_out-1 downto 0);
@@ -52,13 +53,11 @@ process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
din_reg_empty <= '1'; rdy <= '0';
elsif din_reg_empty = '1' then elsif pre_fin = '1' and rdy = '0' then
if din_vld = '1' then rdy <= '1';
din_reg_empty <= '0'; elsif din_vld = '1' then
end if; rdy <= '0';
elsif pre_fin = '1' and dout_en = '1' then
din_reg_empty <= '1';
end if; end if;
end if; end if;
end process; end process;
@@ -66,7 +65,18 @@ end process;
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if din_vld = '1' and din_reg_empty = '1' then if rst = '1' then
din_vld_reg <= '0';
elsif (pre_fin = '1' and dout_en = '1') or din_vld_reg = '0' then
din_vld_reg <= din_vld;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if din_vld = '1' and rdy = '1' then
din_reg <= din; din_reg <= din;
din_be_reg <= din_be; din_be_reg <= din_be;
end if; end if;
@@ -78,21 +88,26 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
shift_cnt_pipe <= (others => '1'); shift_cnt_pipe <= (others => '1');
elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then elsif (din_vld = '1' and din_vld_reg = '0') then
shift_cnt_pipe <= (others => '0'); shift_cnt_pipe <= (others => '0');
elsif dout_en = '1' then elsif dout_en = '1' then
if (pre_fin = '1' and din_vld_reg = '1') then
shift_cnt_pipe <= (others => '0');
else
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1'; shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1';
end if; end if;
end if; end if;
end if;
end process; end process;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then if dout_en = '1' then
if pre_fin = '1' and din_vld_reg = '1' then
shift_pipe <= din_reg; shift_pipe <= din_reg;
elsif dout_en = '1' then else
if (msb_first) then if (msb_first) then
shift_pipe <= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0'); shift_pipe <= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
else else
@@ -100,6 +115,7 @@ begin
end if; end if;
end if; end if;
end if; end if;
end if;
end process; end process;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
@@ -108,9 +124,10 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
vld_pipe <= (others => '0'); vld_pipe <= (others => '0');
elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
vld_pipe <= din_be_reg;
elsif dout_en = '1' then elsif dout_en = '1' then
if pre_fin = '1' and din_vld_reg = '1' then
vld_pipe <= din_be_reg;
else
if (msb_first) then if (msb_first) then
vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & '0'; vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & '0';
else else
@@ -118,6 +135,7 @@ begin
end if; end if;
end if; end if;
end if; end if;
end if;
end process; end process;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
lib/emac/src/pkt_gen.vhd
+9 -5
View File
@@ -12,6 +12,8 @@ ENTITY pkt_gen IS
( (
f_sysclk : real := 100.0; f_sysclk : real := 100.0;
TX_RAM_SIZE : natural := 2048; TX_RAM_SIZE : natural := 2048;
PKT_DLY_MIN : real := 1.0E-6;
PKT_DLY_MAX : real := 100.0E-6;
PKT_SIZE_MIN : natural := 64; PKT_SIZE_MIN : natural := 64;
PKT_SIZE_MAX : natural := 1518 PKT_SIZE_MAX : natural := 1518
@@ -21,8 +23,6 @@ ENTITY pkt_gen IS
clk : in STD_LOGIC; clk : in STD_LOGIC;
rst : in STD_LOGIC; rst : in STD_LOGIC;
en : in STD_LOGIC; en : in STD_LOGIC;
gigabit_en : in STD_LOGIC;
fcs_gen_en : in STD_LOGIC;
mii_tx_clk : in STD_LOGIC; mii_tx_clk : in STD_LOGIC;
mii_tx_en : out STD_LOGIC; mii_tx_en : out STD_LOGIC;
mii_tx_er : out STD_LOGIC; mii_tx_er : out STD_LOGIC;
@@ -38,6 +38,7 @@ ARCHITECTURE behavior OF pkt_gen IS
signal pkt_data : unsigned(31 downto 0); signal pkt_data : unsigned(31 downto 0);
signal pkt_nbytes : word_ptr_t := X"0040"; signal pkt_nbytes : word_ptr_t := X"0040";
signal pkt_nwords : word_ptr_t := X"0010"; signal pkt_nwords : word_ptr_t := X"0010";
signal pkt_delay : natural := natural(1.0*f_sysclk);
signal fill_size : word_ptr_t; signal fill_size : word_ptr_t;
signal fill_cnt : word_ptr_t; signal fill_cnt : word_ptr_t;
@@ -72,14 +73,13 @@ host_state_next:
end process; end process;
host_state: host_state:
process(host_s, tx_ctrl_out, pkt_nbytes, fill_rdy, en, gigabit_en, fcs_gen_en) process(host_s, tx_ctrl_out, pkt_nbytes, fill_rdy, en)
begin begin
tx_ctrl_in.pkt_alloc_en <= '0'; tx_ctrl_in.pkt_alloc_en <= '0';
tx_ctrl_in.pkt_commit_en <= '0'; tx_ctrl_in.pkt_commit_en <= '0';
tx_ctrl_in.reset <= '0'; tx_ctrl_in.reset <= '0';
tx_ctrl_in.Gbps_en <= gigabit_en; tx_ctrl_in.Gbps_en <= '0';
tx_ctrl_in.fcs_gen_en <= fcs_gen_en;
tx_ctrl_in.tx_size <= pkt_nbytes; tx_ctrl_in.tx_size <= pkt_nbytes;
fill_set <= '0'; fill_set <= '0';
fill_en <= '0'; fill_en <= '0';
@@ -132,6 +132,7 @@ host_state:
pkt_generator: pkt_generator:
process(clk) process(clk)
variable size : word_ptr_t; variable size : word_ptr_t;
variable delay : natural;
variable krand : real; variable krand : real;
variable seed1 : integer; variable seed1 : integer;
variable seed2 : integer; variable seed2 : integer;
@@ -140,6 +141,7 @@ pkt_generator:
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
size := to_unsigned(PKT_SIZE_MIN, word_ptr_t'length); size := to_unsigned(PKT_SIZE_MIN, word_ptr_t'length);
delay := natural(1.0E6*PKT_DLY_MIN*f_sysclk);
seed1 := 31101970; seed1 := 31101970;
seed2 := 12586901; seed2 := 12586901;
tx_packets <= 0; tx_packets <= 0;
@@ -147,9 +149,11 @@ pkt_generator:
elsif tx_ctrl_in.pkt_commit_en = '1' then elsif tx_ctrl_in.pkt_commit_en = '1' then
uniform(seed1, seed2, krand); uniform(seed1, seed2, krand);
size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length); size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length);
delay := natural(1.0E6*f_sysclk*(PKT_DLY_MIN + (PKT_DLY_MAX-PKT_DLY_MIN)*krand));
tx_packets <= tx_packets + 1; tx_packets <= tx_packets + 1;
tx_bytes <= tx_bytes + to_integer(pkt_nbytes); tx_bytes <= tx_bytes + to_integer(pkt_nbytes);
end if; end if;
pkt_delay <= delay;
pkt_nbytes <= size; pkt_nbytes <= size;
if size(1 downto 0) = 0 then if size(1 downto 0) = 0 then
pkt_nwords <= "00" & size(word_ptr_t'left downto 2); pkt_nwords <= "00" & size(word_ptr_t'left downto 2);
lib/emac/src/sipo.vhd
+1 -1
View File
@@ -104,7 +104,7 @@ end process;
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if din_vld = '1' or abort = '1' then if (din_en and din_vld) = '1' or abort = '1' then
if (msb_first) then if (msb_first) then
shift_pipe <= shift_pipe(shift_pipe'left-data_width_in downto 0) & din; shift_pipe <= shift_pipe(shift_pipe'left-data_width_in downto 0) & din;
else else
lib/emac/src/tb_crc32.vhd
-106
View File
@@ -1,106 +0,0 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_crc32 IS
END tb_crc32;
ARCHITECTURE behavior OF tb_crc32 IS
constant CLK_PERIOD : time := 10 ns;
signal CLK : std_logic := '1';
signal RST : std_logic := '1';
signal din_vld : std_logic := '0';
signal din : unsigned(7 downto 0) := (others => '-');
signal crc32 : unsigned(31 downto 0);
signal crc32_vld : std_logic;
type byte_array_t is array (0 to 61) of unsigned(7 downto 0);
signal test_data : byte_array_t :=
(
X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12",
X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11",
X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C",
X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D",
X"0E", X"0F", X"10", X"11", X"12", X"13"
);
BEGIN
inst_crc32: entity work.crc32
PORT MAP
(
rst => RST,
clk => CLK,
din_vld => din_vld,
din => din,
crc32_vld => crc32_vld,
crc32_out => crc32
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
CLK <= not CLK;
end process;
-- Master
STIMULUS: process
begin
wait for 6*CLK_PERIOD;
RST <= '0';
wait for 6*CLK_PERIOD;
wait until rising_edge(CLK);
for i in 0 to 61 loop
din_vld <= '1';
din <= test_data(i);
wait until rising_edge(CLK);
end loop;
din <= (others => '-');
din_vld <= '0';
wait;
end process;
END;
lib/emac/src/tb_emac_jb.vhd
+304 -100
View File
@@ -26,58 +26,130 @@ LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; USE ieee.numeric_std.ALL;
ENTITY tb_serdes IS ENTITY tb_emac_jb IS
END tb_serdes; END tb_emac_jb;
ARCHITECTURE behavior OF tb_serdes IS ARCHITECTURE behavior OF tb_emac_jb IS
constant CLK_PERIOD : time := 10 ns; constant CLK_PERIOD : time := 10 ns;
constant MII_CLK_PERIOD : time := 8 ns;
signal CLK : std_logic := '1'; signal CLK : std_logic := '1';
signal RST : std_logic := '1'; signal RST : std_logic := '1';
-- Slave
signal CYC_I : std_logic := '0';
signal STB_I : std_logic := '0';
signal WE_I : std_logic := '0';
signal SEL_I : unsigned(3 downto 0);
signal ACK_O : std_logic;
signal INT_O : std_logic;
signal MRDY_I : std_logic;
signal SRDY_O : std_logic;
signal ADDR_I : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0) := (others => '-');
signal DAT_O : unsigned(31 downto 0) := (others => '-');
signal DAT_O_reg : unsigned(31 downto 0) := (others => '-');
-- MII signals
signal mii_rx_clk_board : std_logic := '1';
signal mii_tx_clk_board : std_logic := '1';
signal mii_rx_clk : std_logic := '1';
signal mii_tx_clk : std_logic := '1';
signal mii_rx : unsigned(7 downto 0) := (others => '-');
signal mii_tx : unsigned(7 downto 0);
signal mii_rx_dv : std_logic := '0';
signal mii_rx_er : std_logic := '0';
signal mii_tx_en : std_logic;
signal mii_tx_er : std_logic;
signal mii_crs : std_logic := '0';
signal mii_col : std_logic := '0';
signal mii_gtx_clk : std_logic;
signal shift_sa : integer := 0;
signal shift_din_vld : std_logic := '0';
signal shift_din : unsigned(31 downto 0) := (others => '-');
signal shift_dout_vld : std_logic;
signal shift_dout : unsigned(31 downto 0);
signal piso_din_vld : std_logic := '0'; signal piso_din_vld : std_logic := '0';
signal piso_din_rdy : std_logic; signal piso_din_rdy : std_logic;
signal piso_din_be : unsigned(3 downto 0) := (others => '0'); signal piso_din_be : unsigned(7 downto 0) := (others => '0');
signal piso_din : unsigned(31 downto 0) := (others => '-'); signal piso_din : unsigned(31 downto 0) := (others => '-');
signal piso_dout_vld : std_logic;
signal piso_dout : unsigned(7 downto 0);
signal piso_dout_en : std_logic; signal piso_dout_en : std_logic;
signal piso_dout : unsigned(3 downto 0);
signal piso2_din_vld : std_logic := '0';
signal piso2_din_rdy : std_logic;
signal piso2_din_be : unsigned(1 downto 0) := (others => '1');
signal piso2_din : unsigned(7 downto 0) := (others => '-');
signal piso2_dout_vld : std_logic;
signal piso2_dout : unsigned(3 downto 0);
signal piso2_dout_en : std_logic;
signal sipo_enable : std_logic := '0'; signal sipo_enable : std_logic := '0';
signal sipo_rst : std_logic := '0'; signal sipo_din_en : std_logic := '0';
signal sipo_din_vld : std_logic := '0'; signal sipo_din : unsigned(3 downto 0) := (others => '-');
signal sipo_din : unsigned(7 downto 0) := (others => '-');
signal sipo_dout_vld : std_logic; signal sipo_dout_vld : std_logic;
signal sipo_dout_en : std_logic; signal sipo_dout_be : unsigned(7 downto 0);
signal sipo_dout_be : unsigned(3 downto 0);
signal sipo_dout : unsigned(31 downto 0); signal sipo_dout : unsigned(31 downto 0);
signal sipo2_enable : std_logic := '0'; type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_read);
signal sipo2_rst : std_logic := '0'; signal emac_action : emac_action_t;
signal sipo2_din_vld : std_logic := '0';
signal sipo2_din : unsigned(3 downto 0) := (others => '-');
signal sipo2_dout_vld : std_logic;
signal sipo2_dout_en : std_logic;
signal sipo2_dout_be : unsigned(1 downto 0);
signal sipo2_dout : unsigned(7 downto 0);
BEGIN BEGIN
inst_emac_jb : entity work.emac_jb
GENERIC MAP
(
f_sysclk => 100.0,
TX_RAM_SIZE => 2048
)
PORT MAP
(
CLK_I => CLK,
RST_I => RST,
INT_O => INT_O,
CYC_I => CYC_I,
STB_I => STB_I,
SEL_I => SEL_I,
WE_I => WE_I,
ACK_O => ACK_O,
SRDY_O => SRDY_O,
MRDY_I => MRDY_I,
ADDR_I => ADDR_I,
DAT_I => DAT_I,
DAT_O => DAT_O,
mii_rx_clk => mii_rx_clk_board,
mii_rx_dv => mii_rx_dv,
mii_rx_er => mii_rx_er,
mii_rx => mii_rx,
mii_tx_clk => mii_tx_clk_board,
mii_tx_en => mii_tx_en,
mii_tx_er => mii_tx_er,
mii_tx => mii_tx,
mii_gtx_clk => mii_gtx_clk,
mii_crs => mii_crs,
mii_col => mii_col
);
inst_shifter : entity work.shifter
GENERIC MAP
(
data_width => 32,
aggregate_size => 4,
do_pipelined => true
)
PORT MAP
(
rst => RST,
clk => CLK,
sa => shift_sa,
din_vld => shift_din_vld,
din => shift_din,
dout_vld => shift_dout_vld,
dout => shift_dout
);
inst_piso : entity work.piso inst_piso : entity work.piso
GENERIC MAP GENERIC MAP
( (
data_width_in => 32, data_width_in => 32,
data_width_out => 8, data_width_out => 4,
msb_first => true msb_first => true
) )
PORT MAP PORT MAP
@@ -88,43 +160,15 @@ inst_piso : entity work.piso
din_rdy => piso_din_rdy, din_rdy => piso_din_rdy,
din_be => piso_din_be, din_be => piso_din_be,
din => piso_din, din => piso_din,
dout_vld => piso_dout_vld,
dout_en => piso_dout_en, dout_en => piso_dout_en,
dout => piso_dout dout => piso_dout
); );
piso_dout_en <= piso2_din_rdy;
inst_piso2 : entity work.piso
GENERIC MAP
(
data_width_in => 8,
data_width_out => 4,
msb_first => true
)
PORT MAP
(
rst => RST,
clk => CLK,
din_vld => piso2_din_vld,
din_rdy => piso2_din_rdy,
din_be => piso2_din_be,
din => piso2_din,
dout_vld => piso2_dout_vld,
dout_en => piso2_dout_en,
dout => piso2_dout
);
piso2_din_vld <= piso_dout_vld;
piso2_dout_en <= '1';
piso2_din <= piso_dout;
inst_sipo : entity work.sipo inst_sipo : entity work.sipo
GENERIC MAP GENERIC MAP
( (
data_width_in => 8, data_width_in => 4,
data_width_out => 32, data_width_out => 32,
msb_first => true msb_first => true
) )
@@ -132,44 +176,16 @@ inst_sipo : entity work.sipo
( (
rst => RST, rst => RST,
clk => CLK, clk => CLK,
din_en => sipo_enable, enable => sipo_enable,
din_vld => sipo_din_vld, din_en => sipo_din_en,
din => sipo_din, din => sipo_din,
dout_be => sipo_dout_be, dout_be => sipo_dout_be,
dout_vld => sipo_dout_vld, dout_vld => sipo_dout_vld,
dout => sipo_dout, dout => sipo_dout
dout_en => sipo_dout_en
); );
sipo_din <= sipo2_dout; sipo_din <= piso_dout;
sipo_din_vld <= sipo2_dout_vld; sipo_din_en <= piso_dout_en;
sipo_enable <= sipo2_dout_en;
sipo_rst <= RST or not piso2_dout_vld;
inst_sipo2 : entity work.sipo
GENERIC MAP
(
data_width_in => 4,
data_width_out => 8,
msb_first => true
)
PORT MAP
(
rst => RST,
clk => CLK,
din_en => sipo2_enable,
din_vld => sipo2_din_vld,
din => sipo2_din,
dout_be => sipo2_dout_be,
dout_vld => sipo2_dout_vld,
dout => sipo2_dout,
dout_en => sipo2_dout_en
);
sipo2_din <= piso2_dout;
sipo2_din_vld <= piso2_dout_vld;
sipo2_enable <= sipo2_din_vld;
sipo_rst <= RST or not piso2_dout_vld;
CLK_GEN: process CLK_GEN: process
begin begin
@@ -177,42 +193,230 @@ CLK_GEN: process
CLK <= not CLK; CLK <= not CLK;
end process; end process;
MII_CLK_GEN: process
begin
wait for MII_CLK_PERIOD/2;
mii_rx_clk <= not mii_rx_clk;
mii_tx_clk <= not mii_tx_clk;
end process;
mii_rx_clk_board <= mii_rx_clk;
mii_tx_clk_board <= mii_tx_clk;
DAT_O_register:
process(CLK)
begin
if rising_edge(CLK) then
if ACK_O = '1' then
DAT_O_reg <= DAT_O;
end if;
end if;
end process;
-- Master -- Master
STIMULUS: process STIMULUS: process
procedure emac_alloc (size : natural) is
begin
-- TX-ALLOCATION
-- set TX-size
emac_action <= emac_alloc;
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= to_unsigned(size, 16) & X"55AA";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= X"0000_0004";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
-- set alloc request
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0001_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= X"0000_0000";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
-- check alloc busy
check_bsy:
while (true) loop
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '1';
ADDR_I <= X"0000_0000";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
wait until rising_edge(CLK);
if DAT_O_reg(16) = '0' then
exit check_bsy;
end if;
end loop;
emac_action <= emac_idle;
end procedure emac_alloc;
procedure emac_write (size : natural) is
variable data : unsigned (7 downto 0);
variable num_words : natural;
begin
-- FILL TX data
emac_action <= emac_write;
if (size mod 4) = 0 then
num_words := size/4;
else
num_words := size/4 + 1;
end if;
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
data := X"00";
ADDR_I <= X"0000_0008";
WE_I <= '1';
for i in 1 to num_words loop
STB_I <= '1';
DAT_I(7 downto 0) <= data;
data := data + 1;
DAT_I(15 downto 8) <= data;
data := data + 1;
DAT_I(23 downto 16) <= data;
data := data + 1;
DAT_I(31 downto 24) <= data;
data := data + 1;
wait until rising_edge(CLK) and SRDY_O = '1';
end loop;
STB_I <= '0';
wait until rising_edge(CLK) and SRDY_O = '1';
emac_action <= emac_idle;
end procedure emac_write;
begin begin
wait for 600*CLK_PERIOD; wait for 6*MII_CLK_PERIOD;
RST <= '0'; RST <= '0';
wait for 60*CLK_PERIOD; wait for 60*CLK_PERIOD;
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (64);
emac_write (64);
emac_alloc (512);
emac_write (512);
emac_alloc (1536);
emac_write (1536);
emac_alloc (65);
emac_write (65);
emac_alloc (66);
emac_write (66);
emac_alloc (67);
emac_write (67);
emac_alloc (512);
emac_write (512);
wait for 4000*CLK_PERIOD;
wait until rising_edge(CLK);
shift_din <= X"12345678";
shift_sa <= 0;
shift_din_vld <= '1';
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= 0;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_din_vld <= '0';
for i in 1 to 10 loop for i in 1 to 10 loop
wait until rising_edge(CLK); wait until rising_edge(CLK);
sipo_enable <= '1';
piso_din_vld <= '1'; piso_din_vld <= '1';
piso_din <= X"12345678"; piso_din <= X"12345678";
piso_din_be <= "1111"; piso_din_be <= "11111111";
wait until rising_edge(CLK) and piso_din_rdy = '1'; wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678"; piso_din <= piso_din + X"12345678";
piso_din_be <= "1111"; piso_din_be <= "11100111";
wait until rising_edge(CLK) and piso_din_rdy = '1'; wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678"; piso_din <= piso_din + X"12345678";
piso_din_be <= "1111"; piso_din_be <= "11111100";
wait until rising_edge(CLK) and piso_din_rdy = '1'; wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678"; piso_din <= piso_din + X"12345678";
piso_din_be <= "1100"; piso_din_be <= "00111111";
wait until rising_edge(CLK) and piso_din_rdy = '1'; wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= (others => '-'); piso_din <= (others => '-');
piso_din_vld <= '0'; piso_din_vld <= '0';
wait until rising_edge(CLK) and piso_dout_vld = '0'; wait until rising_edge(CLK) and sipo_dout_vld = '1';
wait until rising_edge(CLK);
wait until rising_edge(CLK) and sipo_dout_vld = '1';
sipo_enable <= '0';
-- wait until rising_edge(CLK);
-- wait until rising_edge(CLK) and sipo_dout_vld = '1';
--
wait for 33*CLK_PERIOD; wait for 33*CLK_PERIOD;
end loop; end loop;
lib/emac/src/tb_emac_top_jb.vhd
+5 -71
View File
@@ -32,7 +32,7 @@ END tb_emac_top_jb;
ARCHITECTURE behavior OF tb_emac_top_jb IS ARCHITECTURE behavior OF tb_emac_top_jb IS
constant CLK_PERIOD : time := 10 ns; constant CLK_PERIOD : time := 10 ns;
constant MII_CLK_PERIOD : time := 37.7 ns; constant MII_CLK_PERIOD : time := 38.7 ns;
signal CLK : std_logic := '1'; signal CLK : std_logic := '1';
signal RST : std_logic := '1'; signal RST : std_logic := '1';
@@ -74,8 +74,7 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
signal pktgen_tx_en : std_logic; signal pktgen_tx_en : std_logic;
signal pktgen_tx_er : std_logic; signal pktgen_tx_er : std_logic;
signal pktgen_en : std_logic := '0'; signal pktgen_en : std_logic := '0';
signal pktgen_gigabit : std_logic := '0';
signal pktgen_fcs_en : std_logic := '0';
signal dat_o_cnt_en : std_logic := '0'; signal dat_o_cnt_en : std_logic := '0';
signal dat_o_cnt_rst : std_logic := '1'; signal dat_o_cnt_rst : std_logic := '1';
signal dat_o_cnt : natural; signal dat_o_cnt : natural;
@@ -132,6 +131,8 @@ inst_pkt_gen : entity work.pkt_gen
GENERIC MAP GENERIC MAP
( (
f_sysclk => 100.0, f_sysclk => 100.0,
PKT_DLY_MIN => 1.0E-6,
PKT_DLY_MAX => 5.0E-6,
PKT_SIZE_MIN => 64, PKT_SIZE_MIN => 64,
PKT_SIZE_MAX => 1512 PKT_SIZE_MAX => 1512
@@ -141,8 +142,6 @@ inst_pkt_gen : entity work.pkt_gen
clk => CLK, clk => CLK,
rst => RST, rst => RST,
en => pktgen_en, en => pktgen_en,
gigabit_en => pktgen_gigabit,
fcs_gen_en => pktgen_fcs_en,
mii_tx_clk => mii_tx_clk_board, mii_tx_clk => mii_tx_clk_board,
mii_tx_en => pktgen_tx_en, mii_tx_en => pktgen_tx_en,
mii_tx_er => pktgen_tx_er, mii_tx_er => pktgen_tx_er,
@@ -198,66 +197,6 @@ DAT_O_count_register:
-- Master -- Master
STIMULUS: process STIMULUS: process
procedure emac_tx_reset_100mbps is
begin
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"A000_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
end procedure emac_tx_reset_100mbps;
procedure emac_rx_reset_100mbps is
begin
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"A000_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
end procedure emac_rx_reset_100mbps;
procedure emac_tx_reset_1000mbps is
begin
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"E000_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
end procedure emac_tx_reset_1000mbps;
procedure emac_rx_reset_1000mbps is
begin
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"E000_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
end procedure emac_rx_reset_1000mbps;
procedure emac_alloc (size : natural) is procedure emac_alloc (size : natural) is
begin begin
@@ -504,11 +443,6 @@ STIMULUS: process
wait for 6*MII_CLK_PERIOD; wait for 6*MII_CLK_PERIOD;
RST <= '0'; RST <= '0';
wait for 60*CLK_PERIOD; wait for 60*CLK_PERIOD;
emac_rx_reset_100mbps;
emac_tx_reset_100mbps;
pktgen_gigabit <= '0';
pktgen_fcs_en <= '1';
wait for 60*CLK_PERIOD;
emac_alloc (1004); emac_alloc (1004);
emac_alloc (1004); emac_alloc (1004);
@@ -638,7 +572,7 @@ STIMULUS: process
pktgen_en <= '1'; pktgen_en <= '1';
pkt_count <= 0; pkt_count <= 0;
for i in 1 to 500 loop for i in 1 to 500 loop
wait for 1 us; wait for 50 us;
emac_read (0); emac_read (0);
emac_free; emac_free;
pkt_count <= pkt_count + 1; pkt_count <= pkt_count + 1;