Compare commits
1
Commits
EMAC_BRANCH_DMA
...
R1
| Author | SHA1 | Date | |
|---|---|---|---|
 jens
|
d83a065b6b |
@@ -22,8 +22,7 @@
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
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||||
# ---------------------------------------------------------------------
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||||
# $Header: /tmp/cvsroot/VHDL/lib/CPUs/MIPS/tools/make,v 1.3 2008-08-23 07:37:52 Jens Exp $
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||||
# ----------------------------------------------------------------------
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||||
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TARGET=$2
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||||
DSTDIR=$1
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||||
|
||||
|
||||
@@ -1,15 +0,0 @@
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## NOTE: Do not edit this file.
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##
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vlib work
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vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
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||||
vcom -explicit -93 "../src/gray_counter.vhd"
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vcom -explicit -93 "../src/dpram.vhd"
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vcom -explicit -93 "../src/async_fifo_ctrl.vhd"
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vcom -explicit -93 "../src/tb_async_fifo_ctrl.vhd"
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vsim -t 1ps -lib work tb_async_fifo_ctrl
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view wave
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do {tb_async_fifo_ctrl.wdo}
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view structure
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view signals
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run 10us
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@@ -1,36 +0,0 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_async_fifo_ctrl/rst
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add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_w
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||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/we
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_w
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||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_r
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||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/re
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_r
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||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_empty
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||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_empty
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||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_full
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||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_full
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/din
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add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/dout
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||||
add wave -noupdate -format Logic /tb_async_fifo_ctrl/uut/inst_gray_counter_w/ce
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||||
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/uut/bnxt_w
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||||
add wave -noupdate -format Literal /tb_async_fifo_ctrl/uut/bcnt_r
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add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffw
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add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffr
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {250000 ps} 0}
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configure wave -namecolwidth 190
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configure wave -valuecolwidth 80
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {115874 ps} {612358 ps}
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@@ -1,13 +0,0 @@
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## NOTE: Do not edit this file.
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##
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vlib work
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vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../src/gray_counter.vhd"
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vcom -explicit -93 "../src/tb_gray_counter.vhd"
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vsim -t 1ps -lib work tb_gray_counter
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view wave
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do {tb_gray_counter.wdo}
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view structure
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view signals
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run 1us
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@@ -1,25 +0,0 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_gray_counter/rst
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add wave -noupdate -format Logic /tb_gray_counter/ce
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add wave -noupdate -format Logic /tb_gray_counter/clk
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add wave -noupdate -format Literal /tb_gray_counter/bcnt
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add wave -noupdate -format Literal /tb_gray_counter/bnxt
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add wave -noupdate -format Literal /tb_gray_counter/gcnt
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add wave -noupdate -format Literal /tb_gray_counter/gnxt
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {20898 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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update
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WaveRestoreZoom {0 ps} {134759 ps}
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@@ -1,15 +0,0 @@
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## NOTE: Do not edit this file.
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##
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vlib work
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vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../src/gray_counter.vhd"
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vcom -explicit -93 "../src/dpram.vhd"
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vcom -explicit -93 "../src/sync_fifo_ctrl.vhd"
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vcom -explicit -93 "../src/tb_sync_fifo_ctrl.vhd"
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vsim -t 1ps -lib work tb_sync_fifo_ctrl
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view wave
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do {tb_sync_fifo_ctrl.wdo}
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view structure
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view signals
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run 10us
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@@ -1,32 +0,0 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_sync_fifo_ctrl/rst
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add wave -noupdate -format Logic /tb_sync_fifo_ctrl/we
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add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_w
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add wave -noupdate -format Logic /tb_sync_fifo_ctrl/re
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add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_r
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add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_empty
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add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_empty
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add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_full
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add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_full
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add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/din
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add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/dout
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add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pw_next
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add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pr_next
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add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/diff
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TreeUpdate [SetDefaultTree]
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||||
WaveRestoreCursors {{Cursor 1} {290000 ps} 0}
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configure wave -namecolwidth 190
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configure wave -valuecolwidth 80
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {0 ps} {2166667 ps}
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||||
@@ -1,244 +0,0 @@
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-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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||||
-- This file: The call/return/data stack
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||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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LIBRARY WORK;
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USE WORK.FIFO_CTRL_PKG.ALL;
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entity async_fifo_ctrl is
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Generic (
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addr_width : integer := 3;
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almost_full_thresh : integer := 6;
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almost_empty_thresh : integer := 2
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);
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Port
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(
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rst : in STD_LOGIC;
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clk_w : in STD_LOGIC;
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clk_r : in STD_LOGIC;
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we : in STD_LOGIC;
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re : in STD_LOGIC;
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ptr_w : out unsigned (addr_width-1 downto 0);
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ptr_r : out unsigned (addr_width-1 downto 0);
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fifo_full : out STD_LOGIC;
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fifo_empty : out STD_LOGIC;
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fifo_afull : out STD_LOGIC;
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fifo_aempty : out STD_LOGIC
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);
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end async_fifo_ctrl;
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architecture Behavioral of async_fifo_ctrl is
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signal gcnt_w : unsigned (addr_width downto 0);
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signal gcnt2_w : unsigned (addr_width downto 0);
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signal bcnt2_aw : unsigned (addr_width downto 0);
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signal bcnt_w : unsigned (addr_width downto 0);
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signal gnxt_w : unsigned (addr_width downto 0);
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signal bnxt_w : unsigned (addr_width downto 0);
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signal gcnt_r : unsigned (addr_width downto 0);
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signal gcnt2_r : unsigned (addr_width downto 0);
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||||
signal bcnt2_ar : unsigned (addr_width downto 0);
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||||
signal bcnt_r : unsigned (addr_width downto 0);
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signal gnxt_r : unsigned (addr_width downto 0);
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signal bnxt_r : unsigned (addr_width downto 0);
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signal empty, full : std_logic;
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signal write_inhibit, read_inhibit : std_logic;
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signal winc, rinc : std_logic;
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||||
|
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-- synthesis translate_off
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||||
signal diffw : signed (addr_width downto 0);
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||||
signal diffr : signed (addr_width downto 0);
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||||
-- synthesis translate_on
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||||
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||||
begin
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||||
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||||
ptr_w <= bcnt_w(addr_width-1 downto 0);
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||||
ptr_r <= bcnt_r(addr_width-1 downto 0);
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||||
winc <= we and (not write_inhibit);
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||||
rinc <= re and (not read_inhibit);
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||||
fifo_full <= write_inhibit;
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||||
fifo_empty <= read_inhibit;
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||||
|
||||
proc_write_inhibit:
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||||
process(rst, clk_w)
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||||
begin
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||||
if rst = '1' then
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||||
write_inhibit <= '0';
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||||
elsif rising_edge(clk_w) then
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||||
write_inhibit <= full;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_read_inhibit:
|
||||
process(rst, clk_r)
|
||||
begin
|
||||
if rst = '1' then
|
||||
read_inhibit <= '1';
|
||||
elsif rising_edge(clk_r) then
|
||||
read_inhibit <= empty;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_sync_grptr:
|
||||
process(clk_w)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_w) then
|
||||
gcnt2_r <= p2;
|
||||
p2 := p1;
|
||||
p1 := gcnt_r;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_ptr_gwptr:
|
||||
process(clk_r)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_r) then
|
||||
gcnt2_w <= p2;
|
||||
p2 := p1;
|
||||
p1 := gcnt_w;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_full:
|
||||
process(gnxt_w, gcnt2_r)
|
||||
begin
|
||||
if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then
|
||||
full <= '1';
|
||||
else
|
||||
full <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_empty:
|
||||
process(gnxt_r, gcnt2_w)
|
||||
begin
|
||||
if (gnxt_r = gcnt2_w) then
|
||||
empty <= '1';
|
||||
else
|
||||
empty <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_sync_arptr:
|
||||
process(clk_w)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_w) then
|
||||
bcnt2_ar <= p2;
|
||||
p2 := p1;
|
||||
p1 := bcnt_r;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_ptr_awptr:
|
||||
process(clk_r)
|
||||
variable p1, p2 : unsigned (addr_width downto 0);
|
||||
begin
|
||||
if rising_edge(clk_r) then
|
||||
bcnt2_aw <= p2;
|
||||
p2 := p1;
|
||||
p1 := bcnt_w;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_full:
|
||||
process(rst, clk_w)
|
||||
variable diff : unsigned (addr_width downto 0);
|
||||
begin
|
||||
-- synthesis translate_off
|
||||
diffw <= signed(diff);
|
||||
-- synthesis translate_on
|
||||
if rst = '1' then
|
||||
fifo_afull <= '0';
|
||||
diff := (others => '0');
|
||||
elsif rising_edge(clk_w) then
|
||||
if diff >= almost_full_thresh-1 then
|
||||
fifo_afull <= '1';
|
||||
else
|
||||
fifo_afull <= '0';
|
||||
end if;
|
||||
diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_empty:
|
||||
process(rst, clk_r)
|
||||
variable diff : unsigned (addr_width downto 0);
|
||||
begin
|
||||
-- synthesis translate_off
|
||||
diffr <= signed(diff);
|
||||
-- synthesis translate_on
|
||||
if rst = '1' then
|
||||
fifo_aempty <= '1';
|
||||
diff := (others => '0');
|
||||
elsif rising_edge(clk_r) then
|
||||
if diff <= almost_empty_thresh+1 then
|
||||
fifo_aempty <= '1';
|
||||
else
|
||||
fifo_aempty <= '0';
|
||||
end if;
|
||||
diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_gray_counter_w : entity work.gray_counter
|
||||
generic map (
|
||||
width => addr_width+1,
|
||||
init_value => 0
|
||||
)
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk_w,
|
||||
ce => winc,
|
||||
bcnt => bcnt_w,
|
||||
bnxt => bnxt_w,
|
||||
gcnt => gcnt_w,
|
||||
gnxt => gnxt_w
|
||||
);
|
||||
|
||||
inst_gray_counter_r : entity work.gray_counter
|
||||
generic map (
|
||||
width => addr_width+1,
|
||||
init_value => 0
|
||||
)
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk_r,
|
||||
ce => rinc,
|
||||
bcnt => bcnt_r,
|
||||
bnxt => bnxt_r,
|
||||
gcnt => gcnt_r,
|
||||
gnxt => gnxt_r
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,79 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/dpram.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram;
|
||||
|
||||
architecture Behavioral of dpram is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clka)
|
||||
begin
|
||||
if clka'event and clka = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clkb)
|
||||
begin
|
||||
if clkb'event and clkb = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,46 +0,0 @@
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/fifo_ctrl_pkg.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package fifo_ctrl_pkg is
|
||||
|
||||
-- Constants
|
||||
-- Types
|
||||
|
||||
-- Functions
|
||||
function bin2gray(xb : unsigned) return unsigned;
|
||||
function gray2bin(xg : unsigned) return unsigned;
|
||||
|
||||
end fifo_ctrl_pkg;
|
||||
|
||||
package body fifo_ctrl_pkg is
|
||||
|
||||
function bin2gray(xb : unsigned) return unsigned is
|
||||
variable xg : unsigned(xb'left downto xb'right);
|
||||
begin
|
||||
|
||||
xg(xg'left) := xb(xb'left);
|
||||
for i in 1 to xb'left loop
|
||||
xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i);
|
||||
end loop;
|
||||
|
||||
return xg;
|
||||
end bin2gray;
|
||||
|
||||
function gray2bin(xg : unsigned) return unsigned is
|
||||
variable xb : unsigned(xg'left downto xg'right);
|
||||
begin
|
||||
|
||||
xb(xb'left) := xg(xg'left);
|
||||
for i in 1 to xg'left loop
|
||||
xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i);
|
||||
end loop;
|
||||
|
||||
return xb;
|
||||
end gray2bin;
|
||||
|
||||
end fifo_ctrl_pkg;
|
||||
|
||||
@@ -1,88 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The call/return/data stack
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
LIBRARY WORK;
|
||||
USE WORK.FIFO_CTRL_PKG.ALL;
|
||||
|
||||
entity gray_counter is
|
||||
Generic (
|
||||
width : natural := 3;
|
||||
init_value : natural := 0
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
bcnt : out unsigned (width-1 downto 0);
|
||||
bnxt : out unsigned (width-1 downto 0);
|
||||
gcnt : out unsigned (width-1 downto 0);
|
||||
gnxt : out unsigned (width-1 downto 0)
|
||||
);
|
||||
end gray_counter;
|
||||
|
||||
architecture Behavioral of gray_counter is
|
||||
|
||||
signal cntb : unsigned (width-1 downto 0);
|
||||
signal nxtb : unsigned (width-1 downto 0);
|
||||
signal cntg : unsigned (width-1 downto 0);
|
||||
signal nxtg : unsigned (width-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
bnxt <= nxtb;
|
||||
gnxt <= nxtg;
|
||||
|
||||
process(rst, clk, ce, cntb, nxtb)
|
||||
begin
|
||||
if rst = '1' then
|
||||
cntb <= to_unsigned(init_value, width);
|
||||
nxtb <= to_unsigned(init_value, width);
|
||||
cntg <= to_unsigned(init_value, width);
|
||||
nxtg <= to_unsigned(init_value, width);
|
||||
bcnt <= to_unsigned(init_value, width);
|
||||
gcnt <= to_unsigned(init_value, width);
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
bcnt <= nxtb;
|
||||
gcnt <= nxtg;
|
||||
cntb <= nxtb;
|
||||
cntg <= nxtg;
|
||||
end if;
|
||||
nxtg <= bin2gray(nxtb);
|
||||
nxtb <= cntb;
|
||||
if ce = '1' then
|
||||
nxtb <= cntb + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,199 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The call/return/data stack
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity sync_fifo_ctrl is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
almost_full_thresh : integer := 6;
|
||||
almost_empty_thresh : integer := 2
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
re : in STD_LOGIC;
|
||||
ptr_w : out unsigned (addr_width-1 downto 0);
|
||||
ptr_r : out unsigned (addr_width-1 downto 0);
|
||||
fifo_full : out STD_LOGIC;
|
||||
fifo_empty : out STD_LOGIC;
|
||||
fifo_afull : out STD_LOGIC;
|
||||
fifo_aempty : out STD_LOGIC
|
||||
);
|
||||
end sync_fifo_ctrl;
|
||||
|
||||
architecture Behavioral of sync_fifo_ctrl is
|
||||
|
||||
signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0);
|
||||
signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0);
|
||||
signal empty, full : std_logic;
|
||||
signal pre_empty, pre_full : std_logic;
|
||||
signal was_write : std_logic;
|
||||
signal write, read : std_logic;
|
||||
signal diff : unsigned (addr_width downto 0);
|
||||
|
||||
begin
|
||||
|
||||
read <= '1' when re = '1' and empty = '0' else '0';
|
||||
write <= '1' when we = '1' and full = '0' else '0';
|
||||
|
||||
fifo_full <= full;
|
||||
fifo_empty <= empty;
|
||||
|
||||
|
||||
proc_diff_gen:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
diff <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if write = '1' and read = '0' then
|
||||
diff <= diff + 1;
|
||||
elsif write = '0' and read = '1' then
|
||||
diff <= diff - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_full:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
fifo_afull <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if diff >= almost_full_thresh-1 then
|
||||
fifo_afull <= '1';
|
||||
else
|
||||
fifo_afull <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_almost_empty:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
fifo_aempty <= '1';
|
||||
elsif rising_edge(clk) then
|
||||
if diff <= almost_empty_thresh+1 then
|
||||
fifo_aempty <= '1';
|
||||
else
|
||||
fifo_aempty <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_full_reg:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
full <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
full <= pre_full;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_empty_reg:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
empty <= '1';
|
||||
elsif rising_edge(clk) then
|
||||
empty <= pre_empty;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_status_w:
|
||||
process(was_write, pW_next, pR_next, pW, pR, we, re)
|
||||
begin
|
||||
if (pW_next = pR) and (we = '1' or was_write = '1') then
|
||||
pre_full <= '1';
|
||||
else
|
||||
pre_full <= '0';
|
||||
end if;
|
||||
if (pR_next = pW) and (re = '1' or was_write = '0') then
|
||||
pre_empty <= '1';
|
||||
else
|
||||
pre_empty <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_flag_write:
|
||||
process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
was_write <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if write = '1' then
|
||||
was_write <= '1';
|
||||
elsif read = '1' then
|
||||
was_write <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_ptr_w:
|
||||
process(rst, clk, pW, we, full)
|
||||
begin
|
||||
if rst = '1' then
|
||||
pW <= to_unsigned(0, addr_width);
|
||||
pW_next <= to_unsigned(0, addr_width);
|
||||
elsif rising_edge(clk) then
|
||||
if we = '1' then
|
||||
pW <= pW_next;
|
||||
end if;
|
||||
end if;
|
||||
pW_next <= pW;
|
||||
if we = '1' and full = '0' then
|
||||
pW_next <= pW + 1;
|
||||
end if;
|
||||
ptr_w <= pW;
|
||||
end process;
|
||||
|
||||
proc_ptr_r:
|
||||
process(rst, clk, pR_next, pR, re, empty)
|
||||
begin
|
||||
if rst = '1' then
|
||||
pR <= to_unsigned(0, addr_width);
|
||||
pR_next <= to_unsigned(0, addr_width);
|
||||
elsif rising_edge(clk) then
|
||||
if re = '1' then
|
||||
pR <= pR_next;
|
||||
end if;
|
||||
end if;
|
||||
pR_next <= pR;
|
||||
if re = '1' and empty = '0' then
|
||||
pR_next <= pR + 1;
|
||||
end if;
|
||||
ptr_r <= pR_next;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,176 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_nco
|
||||
-- Module Name: tb_nco.vhd
|
||||
-- Project Name: nco
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
-- LIBRARY WORK;
|
||||
-- USE.YOURLIB.WHATELSE
|
||||
|
||||
ENTITY tb_async_fifo_ctrl IS
|
||||
END tb_async_fifo_ctrl;
|
||||
|
||||
ARCHITECTURE behavior OF tb_async_fifo_ctrl IS
|
||||
|
||||
--Constants
|
||||
constant PERIOD_W : time := 10 ns;
|
||||
constant PERIOD_R : time := 20 ns;
|
||||
constant ADDR_WIDTH : integer := 3;
|
||||
|
||||
--Inputs
|
||||
signal rst : STD_LOGIC := '1';
|
||||
signal clk_w : STD_LOGIC := '0';
|
||||
signal clk_r : STD_LOGIC := '0';
|
||||
signal we : STD_LOGIC := '0';
|
||||
signal re : STD_LOGIC := '0';
|
||||
signal din : unsigned (7 downto 0);
|
||||
--Outputs
|
||||
|
||||
signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0);
|
||||
signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0);
|
||||
signal dout : unsigned (7 downto 0);
|
||||
signal fifo_full : STD_LOGIC;
|
||||
signal fifo_empty : STD_LOGIC;
|
||||
signal fifo_almost_full : STD_LOGIC;
|
||||
signal fifo_almost_empty : STD_LOGIC;
|
||||
signal mem_we : STD_LOGIC;
|
||||
|
||||
signal write_en : STD_LOGIC := '0';
|
||||
signal read_en : STD_LOGIC := '0';
|
||||
|
||||
signal wdata : unsigned (7 downto 0) := (others => '0');
|
||||
signal rdata : unsigned (7 downto 0) := (others => '0');
|
||||
signal rdata2 : unsigned (7 downto 0) := (others => '0');
|
||||
|
||||
BEGIN
|
||||
|
||||
din <= wdata;
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: entity work.async_fifo_ctrl
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => ADDR_WIDTH,
|
||||
almost_full_thresh => 6,
|
||||
almost_empty_thresh => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_w => clk_w,
|
||||
clk_r => clk_r,
|
||||
we => we,
|
||||
re => re,
|
||||
ptr_w => ptr_w,
|
||||
ptr_r => ptr_r,
|
||||
fifo_full => fifo_full,
|
||||
fifo_empty => fifo_empty,
|
||||
fifo_afull => fifo_almost_full,
|
||||
fifo_aempty => fifo_almost_empty
|
||||
|
||||
);
|
||||
|
||||
inst_dpram: entity work.dpram
|
||||
GENERIC MAP (
|
||||
addr_width => ADDR_WIDTH,
|
||||
data_width => 8
|
||||
)
|
||||
PORT MAP(
|
||||
clka => clk_w,
|
||||
clkb => clk_r,
|
||||
en_a => '1',
|
||||
en_b => '1',
|
||||
we_a => mem_we,
|
||||
addr_a => ptr_w,
|
||||
addr_b => ptr_r,
|
||||
din_a => din,
|
||||
dout_b => dout
|
||||
);
|
||||
|
||||
tb_clk_w : PROCESS
|
||||
BEGIN
|
||||
clk_w <= not clk_w;
|
||||
wait for PERIOD_W/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_clk_r : PROCESS
|
||||
BEGIN
|
||||
clk_r <= not clk_r;
|
||||
wait for PERIOD_R/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_write : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 5*PERIOD_W;
|
||||
rst <= '0';
|
||||
wait for 5*PERIOD_W;
|
||||
write_en <= '1';
|
||||
wait for 15*PERIOD_W;
|
||||
write_en <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
tb_read : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 15*PERIOD_R;
|
||||
read_en <= '1';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
we <= write_en and not fifo_full;
|
||||
mem_we <= we;
|
||||
|
||||
tb_w : PROCESS(rst, clk_w)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
wdata <= (others => '0');
|
||||
elsif rising_edge(clk_w) then
|
||||
if we = '1' then
|
||||
wdata <= wdata + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
re <= read_en and not fifo_empty;
|
||||
|
||||
tb_r : PROCESS(rst, clk_r)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
rdata <= (others => '0');
|
||||
elsif rising_edge(clk_r) then
|
||||
rdata2 <= rdata;
|
||||
if re = '1' then
|
||||
assert rdata2 = dout report "FIFO read error!" severity failure;
|
||||
rdata <= rdata + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END behavior;
|
||||
@@ -1,83 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_gray_counter
|
||||
-- Module Name: tb_gray_counter.vhd
|
||||
-- Project Name: gray_counter package
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
LIBRARY WORK;
|
||||
USE WORK.FIFO_CTRL_PKG.ALL;
|
||||
|
||||
ENTITY tb_gray_counter IS
|
||||
END tb_gray_counter;
|
||||
|
||||
ARCHITECTURE behavior OF tb_gray_counter IS
|
||||
|
||||
constant PERIOD : time := 10 ns;
|
||||
constant WIDTH : integer := 3;
|
||||
|
||||
--Signals
|
||||
signal gcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal bcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal gnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal bnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
|
||||
signal rst : STD_LOGIC := '1';
|
||||
signal clk : STD_LOGIC := '0';
|
||||
signal ce : STD_LOGIC := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_gray_counter : entity work.gray_counter
|
||||
generic map (width => WIDTH)
|
||||
port map (
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
bcnt => bcnt,
|
||||
bnxt => bnxt,
|
||||
gcnt => gcnt,
|
||||
gnxt => gnxt
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_counter : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
wait for 4*PERIOD;
|
||||
rst <= '0';
|
||||
wait for 1*PERIOD;
|
||||
ce <= '1';
|
||||
wait for 3*PERIOD;
|
||||
ce <= '0';
|
||||
wait for 4*PERIOD;
|
||||
ce <= '1';
|
||||
wait for 1*PERIOD;
|
||||
ce <= '0';
|
||||
wait for 1*PERIOD;
|
||||
ce <= '1';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END behavior;
|
||||
@@ -1,221 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_nco
|
||||
-- Module Name: tb_nco.vhd
|
||||
-- Project Name: nco
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-----------------------------------------------------------------------
|
||||
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
-----------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.MATH_REAL.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
-- LIBRARY WORK;
|
||||
-- USE.YOURLIB.WHATELSE
|
||||
|
||||
ENTITY tb_sync_fifo_ctrl IS
|
||||
END tb_sync_fifo_ctrl;
|
||||
|
||||
ARCHITECTURE behavior OF tb_sync_fifo_ctrl IS
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
constant ADDR_WIDTH : integer := 3;
|
||||
|
||||
--Inputs
|
||||
signal rst : STD_LOGIC := '1';
|
||||
signal clk : STD_LOGIC := '0';
|
||||
signal we : STD_LOGIC := '0';
|
||||
signal re : STD_LOGIC := '0';
|
||||
signal din : unsigned (7 downto 0);
|
||||
--Outputs
|
||||
|
||||
signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0);
|
||||
signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0);
|
||||
signal dout : unsigned (7 downto 0);
|
||||
signal fifo_full : STD_LOGIC;
|
||||
signal fifo_empty : STD_LOGIC;
|
||||
signal fifo_almost_full : STD_LOGIC;
|
||||
signal fifo_almost_empty : STD_LOGIC;
|
||||
signal mem_we : STD_LOGIC;
|
||||
|
||||
signal write_en : STD_LOGIC := '0';
|
||||
signal read_en : STD_LOGIC := '0';
|
||||
|
||||
signal wdata : unsigned (7 downto 0) := (others => '0');
|
||||
signal rdata : unsigned (7 downto 0) := (others => '0');
|
||||
signal rdata2 : unsigned (7 downto 0) := (others => '0');
|
||||
|
||||
BEGIN
|
||||
|
||||
din <= wdata;
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: entity work.sync_fifo_ctrl
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => ADDR_WIDTH,
|
||||
almost_full_thresh => 6,
|
||||
almost_empty_thresh => 2
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => we,
|
||||
re => re,
|
||||
ptr_w => ptr_w,
|
||||
ptr_r => ptr_r,
|
||||
fifo_full => fifo_full,
|
||||
fifo_empty => fifo_empty,
|
||||
fifo_afull => fifo_almost_full,
|
||||
fifo_aempty => fifo_almost_empty
|
||||
|
||||
);
|
||||
|
||||
inst_dpram: entity work.dpram
|
||||
GENERIC MAP (
|
||||
addr_width => ADDR_WIDTH,
|
||||
data_width => 8
|
||||
)
|
||||
PORT MAP(
|
||||
clka => clk,
|
||||
clkb => clk,
|
||||
en_a => '1',
|
||||
en_b => '1',
|
||||
we_a => mem_we,
|
||||
addr_a => ptr_w,
|
||||
addr_b => ptr_r,
|
||||
din_a => din,
|
||||
dout_b => dout
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_write : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 5*PERIOD;
|
||||
rst <= '0';
|
||||
wait for 7*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 7*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 7*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 1*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 3*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 4*PERIOD;
|
||||
write_en <= '0';
|
||||
wait for 17*PERIOD;
|
||||
write_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
write_en <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
tb_read : PROCESS
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 25*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 25*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 25*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 5*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 1*PERIOD;
|
||||
read_en <= '0';
|
||||
wait for 7*PERIOD;
|
||||
read_en <= '1';
|
||||
wait for 15*PERIOD;
|
||||
read_en <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
we <= write_en and not fifo_full;
|
||||
mem_we <= we;
|
||||
|
||||
tb_w : PROCESS(rst, clk)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
wdata <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if we = '1' then
|
||||
wdata <= wdata + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
re <= read_en and not fifo_empty;
|
||||
|
||||
tb_r : PROCESS(rst, clk)
|
||||
BEGIN
|
||||
|
||||
if rst = '1' then
|
||||
rdata <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
rdata2 <= rdata;
|
||||
if re = '1' then
|
||||
assert rdata = dout report "FIFO read error!" severity failure;
|
||||
rdata <= rdata + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END behavior;
|
||||
@@ -1,297 +0,0 @@
|
||||
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
|
||||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<meta name="GENERATOR" content="Mozilla/4.5 [en] (X11; I; SunOS 5.7 sun4u) [Netscape]">
|
||||
<title>VHDL package for formatted file output</title>
|
||||
<!-- $Id: PCK_FIO.html,v 1.1 2008-08-23 08:20:28 Jens Exp $ -->
|
||||
</head>
|
||||
<body text="#000000" bgcolor="#FFFFFF" link="#0000EE" vlink="#551A8B" alink="#FF0000">
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_name_0"></a>Name</h1>
|
||||
<b>PCK_FIO</b> - VHDL package for formatted file output
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
Contents</h1>
|
||||
<a href="#PCK_FIO_usage_0">Usage</a>
|
||||
<br><a href="#PCK_FIO_file_0">The file output function 'fo'</a>
|
||||
<br><a href="#PCK_FIO_format_0">Format specifiers</a>
|
||||
<br><a href="#PCK_FIO_special_0">Special characters</a>
|
||||
<br><a href="#PCK_FIO_things_0">Things to watch out for</a>
|
||||
<br><a href="#PCK_FIO_methodology_0">Methodology notes</a>
|
||||
<br><a href="#PCK_FIO_parametrization_0">Parametrization</a>
|
||||
<br><a href="#PCK_FIO_test_0">Test bench</a>
|
||||
<br><a href="#PCK_FIO_limitations_0">Known limitations and problems</a>
|
||||
<br><a href="#PCK_FIO_author_0">Author</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_usage_0"></a>Usage</h1>
|
||||
PCK_FIO is a VHDL package that defines <tt>fprint, </tt>a function
|
||||
for formatted file output.
|
||||
<p>After installing the package you can call <tt>fprint</tt> as follows:
|
||||
<pre> fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));</pre>
|
||||
where F is the filehandle and L is the line variable.
|
||||
<p>The argument Format is the format string, which consists of ``normal''
|
||||
substrings which are copied verbatim, and format specifiers, starting with
|
||||
<tt>'%'</tt>.
|
||||
A typical format string looks as follows:
|
||||
<pre> "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"</pre>
|
||||
The remaining arguments are the expressions whose results you want to write
|
||||
to the file, embedded in <tt>fo</tt> function calls. There can be 0 to
|
||||
32 of such arguments. The expressions can be of any type for which an <tt>fo</tt>
|
||||
function exists. String expressions can also be called directly.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_file_0"></a>The file output function <tt>'fo'</tt></h1>
|
||||
The <tt>fo</tt> (<u>f</u>ile <u>o</u>utput) functions do the trick. They
|
||||
return a tagged string representation that is meaningful to format specifiers.
|
||||
Here are some examples:
|
||||
<pre> fo (signed'("1100")) returns "S:1100"
|
||||
fo (unsigned'("1100")) returns "U:1100"
|
||||
fo (TRUE) returns "L:T"
|
||||
fo (127) returns "I:127"</pre>
|
||||
The internal behavior of <tt>fo</tt> is irrelevant to the typical user.
|
||||
<p>The <tt>fo</tt> function is currently overloaded as follows:
|
||||
<pre> function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;</pre>
|
||||
|
||||
<pre>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%"></pre>
|
||||
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_format_0"></a>Format specifiers</h1>
|
||||
The general format of a format specifier is:
|
||||
<pre> %[-][n]c</pre>
|
||||
The optional <b>-</b> sign specifies left justified output; default is
|
||||
right justified.
|
||||
<p>The optional number <b>n</b> specifies a field-width. If it is not specified,
|
||||
<tt>fprint</tt>
|
||||
does something reasonable.
|
||||
<p><b>c</b> is the conversion specifier. Currently the following conversion
|
||||
specifiers are supported:
|
||||
<dl COMPACT>
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_r_0"></a><b>r</b></dt>
|
||||
|
||||
<dd>
|
||||
reasonable output format (inspired by Synopsys VSS)</dd>
|
||||
|
||||
<dl COMPACT>Prints the ``most reasonable'' representation e.g. hex for
|
||||
unsigned, signed and other bit-like vectors (not preferred for integers)</dl>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_b_0"></a><b>b</b></dt>
|
||||
|
||||
<dd>
|
||||
bit-oriented output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_d_0"></a><b>d</b></dt>
|
||||
|
||||
<dd>
|
||||
decimal output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_s_0"></a><b>s</b></dt>
|
||||
|
||||
<dd>
|
||||
string output (e.g. in combination with 'IMAGE for enum types)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_q_0"></a><b>q</b></dt>
|
||||
|
||||
<dd>
|
||||
``qualified'' string output (shows internal representation from <tt>fo</tt>)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO__0"></a><b>{}</b></dt>
|
||||
|
||||
<dd>
|
||||
Iteration operator, used as follows:</dd>
|
||||
|
||||
<dd>
|
||||
<tt>%n{<format-string>}</tt></dd>
|
||||
|
||||
<br>In this case, <b>n</b> is the iteration count and is mandatory. Iteration
|
||||
can be nested.</dl>
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_special_0"></a>Special characters</h1>
|
||||
To print a double-quote, use <tt>'""'</tt> in the format string (VHDL
|
||||
convention). To print the special characters, <tt>'\'</tt>, and <tt>'%'</tt>,
|
||||
escape them with <tt>'\'</tt>. To prevent <tt>'{'</tt> and <tt>'}'</tt>
|
||||
from being interpreted as opening and closing brackets in iteration strings,
|
||||
escape them with <tt>'\'</tt>.
|
||||
<p>A newline is specified in the format string by <tt>'\n'</tt>.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_things_0"></a>Things to notice</h1>
|
||||
The fprint function expands into VHDL <tt>write</tt> and <tt>writeline</tt>
|
||||
commands. As in plain VHDL, nothing will be written to the output file
|
||||
until a <tt>writeline</tt> is given. Therefore, don't forget to include
|
||||
<tt>'\n'</tt>
|
||||
commands in the format string, or it ``will not work''.
|
||||
<p>The preferred format specifier for integers is, naturally, <b>%d</b>.
|
||||
This calls the VHDL <tt>write</tt> for integers. If you specify a field
|
||||
width that is too small, the field will automatically be expanded. If you
|
||||
use <b>%r</b> for integers, the field is not expanded automatically, which
|
||||
means that some digits are simply thrown away. This may sometimes be useful
|
||||
but it is also dangerous. Look at the test bench output for differences
|
||||
between <b>%d</b> and <b>%r</b> output.
|
||||
<p>When using the <b>%d</b> format specifier, the VHDL constraints for
|
||||
the allowed integer range apply.
|
||||
<p>In VHDL, signed/unsigned types have been standardized only relatively
|
||||
recently, in the package <tt>IEEE.numeric_std</tt>. The lack of a standard
|
||||
has caused (and is causing) portability issues. The most popular non-standard
|
||||
package that defines signed/unsigned is <tt>IEEE.std_logic_arith</tt> from
|
||||
Synopsys. PCK_FIO has been developed with this latter package, and still
|
||||
refers to this package by default. However, PCK_FIO works with
|
||||
<tt>IEEE.numeric_std</tt>
|
||||
as well. To use <tt>IEEE.numeric_std</tt>, replace the reference to <tt>IEEE.std_logic_arith</tt>
|
||||
in the source code. This needs to be done consistently in a design
|
||||
database (e.g. in the PCK_FIO test bench as well).
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_methodology_0"></a>Methodology notes</h1>
|
||||
The obvious application for <tt>fprint</tt> is in test benches, to produce
|
||||
output files that trace the simulation behavior.
|
||||
<p>Another interesting application for <tt>fprint</tt> is to produce info,
|
||||
warning and error messages in your models. As it can take arguments, <tt>fprint</tt>
|
||||
is much better suited for this task than VHDL's <tt>assert</tt> or <tt>report</tt>
|
||||
statements. Actually <tt>fprint</tt> produces its own (few) warning messages.
|
||||
<p>An advanced usage is the generation of test vectors in a specific format.
|
||||
Instead of using the <tt>fo </tt>functions, you can write your own set
|
||||
of functions that return the symbols of a specific test format in a way
|
||||
that is understandable to the <tt>fprint</tt> format specifiers. As an
|
||||
example, when a high output value should be represented using the symbol
|
||||
'H' it suffices to write a conversion function that returns "B:H" and call
|
||||
it in combination with the <b>%b</b> format specifier.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_parametrization_0"></a>Parametrization</h1>
|
||||
Prefix and postfix strings for bit-oriented and hex-oriented output are
|
||||
parameterizable in the packages to accommodate different output styles.
|
||||
The settings in the distribution are such that hex output is indicated
|
||||
by the prefix '0x', while bit output prefix and postfix are empty
|
||||
strings.
|
||||
<p>You can adapt the output style by modifying the following constants
|
||||
in the package header:
|
||||
<p> <tt> -- prefix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: "X"""</tt>
|
||||
<br><tt> -- Verilog style: "h'"</tt>
|
||||
<br><tt> -- C style: "0x"</tt>
|
||||
<br><tt> constant FIO_h_PRE: string := "0x";</tt>
|
||||
<p><tt> -- postfix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_h_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: "B"""</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_bv_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_bv_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_b_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> constant FIO_b_POST: string := "";</tt>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_test_0"></a>Test bench</h1>
|
||||
Included in the distribution is a file <tt>TB_PCK_FIO.vhd</tt> with a test
|
||||
bench for the PCK_FIO package. The file <tt>PCK_FIO.out.gold </tt>contains
|
||||
the expected output. If you run the test bench it should produce the file
|
||||
<tt>PCK_FIO.out</tt>
|
||||
that should be identical to <tt>PCK_FIO.out.gold</tt>. The source files
|
||||
should be analyzed in a VHDL library <tt>EASICS_PACKAGES</tt>.
|
||||
<p>A good way to understand <tt>fprint</tt> is to inspect the test bench
|
||||
and what it produces.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_limitations_0"></a>Known limitations and problems</h1>
|
||||
This VHDL package is an implementation of a flexible concept. It is likely
|
||||
to be extended and modified in the future. Backward compatibility is not
|
||||
guaranteed. Therefore, it is not recommended to give this package the status
|
||||
of a company-wide standard package (or even worse, a VHDL standard package).
|
||||
Rather, it should be linked with a particular project (and it can be regarded
|
||||
as a standard package within that project).
|
||||
<p>PCK_FIO is written in standard VHDL Std1076-1987. Nevertheless, some
|
||||
simulators/versions have problems with the package. The following is an
|
||||
overview of currently known issues:
|
||||
<br>
|
||||
<center><table BORDER COLS=2 WIDTH="80%" >
|
||||
<tr>
|
||||
<th>Simulator</th>
|
||||
|
||||
<th>PCK_FIO handling</th>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 3.5 and earlier</td>
|
||||
|
||||
<td>Incorrect (all zero) output in compiled mode</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 97.01</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Mentor quickhdl</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Modeltech modelsim</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Cadence Leapfrog</td>
|
||||
|
||||
<td>Should work with 4.4.1
|
||||
<br>Mysterious problems have been reported - please run the test bench
|
||||
and report problems</td>
|
||||
</tr>
|
||||
|
||||
<caption ALIGN=BOTTOM>PCK_FIO and various simulators/versions</caption>
|
||||
</table></center>
|
||||
|
||||
<p>Although the package name suggests file IO, it only does file output.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_author_0"></a>Author</h1>
|
||||
<a href="mailto:jand@easics.be">Jan Decaluwe</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
</body>
|
||||
</html>
|
||||
@@ -1,206 +0,0 @@
|
||||
PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO
|
||||
-----------------------------------------
|
||||
|
||||
This is the result of running the PCK_FIO testbench.
|
||||
This file should be compared with PCK_FIO.out.gold, which is
|
||||
the reference output. Any difference indicates a portability
|
||||
issue or a simulator non-compliance or bug.
|
||||
|
||||
|
||||
--------------------
|
||||
-- Basic features --
|
||||
--------------------
|
||||
|
||||
-- First some auxiliary declarations
|
||||
> file RESULT: text is out "PCK_FIO.out";
|
||||
> variable L: line;
|
||||
> variable BoolTrue: boolean := TRUE;
|
||||
> variable BoolFalse: boolean := FALSE;
|
||||
> variable IntPos: integer := 5678;
|
||||
> variable BigIntPos: integer := 12345678;
|
||||
> variable IntNeg: integer := -8765;
|
||||
> variable BigIntNeg: integer := -87654321;
|
||||
> variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
|
||||
> variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
|
||||
> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
|
||||
> variable SigPos: signed(6 downto 0) := signed'("0010010");
|
||||
> variable SigNeg: signed(6 downto 0) := signed'("1010010");
|
||||
> variable BitX: std_logic := 'X';
|
||||
> variable Bit1: std_logic := '1';
|
||||
> variable Bit0: std_logic := '0';
|
||||
|
||||
|
||||
-- fprint call with no arguments
|
||||
> fprint(RESULT, L, "No arguments.\n);"
|
||||
No arguments.
|
||||
|
||||
-- Special characters need to be escaped
|
||||
> fprint(RESULT, L, "Special characters: \% \\ " \n");
|
||||
Special characters: % \ "
|
||||
|
||||
-- Various format specifiers interprete the same object differently
|
||||
> fprint(RESULT, L, "Format specifiers: %r %d %b %q\n);"
|
||||
> fo(Uns), fo(Uns), fo(Uns), fo(Uns)
|
||||
> );
|
||||
Format specifiers: 0x52 82 1010010 U:1010010
|
||||
|
||||
-- Format string can be shortened by using the iteration specifier
|
||||
> fprint(RESULT, L, "Iteration specifier: %4{%r }\n);"
|
||||
> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
|
||||
> );
|
||||
Iteration specifier: 0x52 0x12 0x52 0x12
|
||||
|
||||
------------------------------------
|
||||
-- Support for bit-oriented types --
|
||||
------------------------------------
|
||||
|
||||
-- Reasonable format
|
||||
> fprint(RESULT, L, "Reasonable format: %9{%r }\n",
|
||||
> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
> );
|
||||
Reasonable format: 0x12 0x52 0x12 0x52 0x?? 1 X T F
|
||||
|
||||
-- Decimal format
|
||||
> fprint(RESULT, L, "Decimal format: %7{%d }\n",
|
||||
> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
> );
|
||||
Decimal format: 18 82 18 -46 -1 1 -1 1 0
|
||||
|
||||
-- Bit format
|
||||
> fprint(RESULT, L, "Bit format: %7{%b }\n",
|
||||
> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
> );
|
||||
Bit format: 0010010 1010010 0010010 1010010 1X10Z10 1 X 1 0
|
||||
|
||||
|
||||
-- Alignment
|
||||
-- Template of the call: (<fs> stands for the format specifier)
|
||||
|
||||
> fprint(RESULT, L, "Bitvectors with <fs>: %4{<fs>|}\n",
|
||||
> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)
|
||||
> );
|
||||
|
||||
-- Results of the call with various format specifiers
|
||||
|
||||
Bitvectors with %1r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %2r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %3r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %4r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %5r: 0x52| 0x12| 0x12| 0x52|
|
||||
Bitvectors with %6r: 0x52| 0x12| 0x12| 0x52|
|
||||
Bitvectors with %7r: 0x52| 0x12| 0x12| 0x52|
|
||||
Bitvectors with %8r: 0x52| 0x12| 0x12| 0x52|
|
||||
Bitvectors with %9r: 0x52| 0x12| 0x12| 0x52|
|
||||
|
||||
Bitvectors with %-1r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %-2r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %-3r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %-4r: 0x52|0x12|0x12|0x52|
|
||||
Bitvectors with %-5r: 0x52 |0x12 |0x12 |0x52 |
|
||||
Bitvectors with %-6r: 0x52 |0x12 |0x12 |0x52 |
|
||||
Bitvectors with %-7r: 0x52 |0x12 |0x12 |0x52 |
|
||||
Bitvectors with %-8r: 0x52 |0x12 |0x12 |0x52 |
|
||||
Bitvectors with %-9r: 0x52 |0x12 |0x12 |0x52 |
|
||||
|
||||
Bitvectors with %1d: 82|18|18|-46|
|
||||
Bitvectors with %2d: 82|18|18|-46|
|
||||
Bitvectors with %3d: 82| 18| 18|-46|
|
||||
Bitvectors with %4d: 82| 18| 18| -46|
|
||||
Bitvectors with %5d: 82| 18| 18| -46|
|
||||
Bitvectors with %6d: 82| 18| 18| -46|
|
||||
Bitvectors with %7d: 82| 18| 18| -46|
|
||||
Bitvectors with %8d: 82| 18| 18| -46|
|
||||
Bitvectors with %9d: 82| 18| 18| -46|
|
||||
|
||||
Bitvectors with %-1d: 82|18|18|-46|
|
||||
Bitvectors with %-2d: 82|18|18|-46|
|
||||
Bitvectors with %-3d: 82 |18 |18 |-46|
|
||||
Bitvectors with %-4d: 82 |18 |18 |-46 |
|
||||
Bitvectors with %-5d: 82 |18 |18 |-46 |
|
||||
Bitvectors with %-6d: 82 |18 |18 |-46 |
|
||||
Bitvectors with %-7d: 82 |18 |18 |-46 |
|
||||
Bitvectors with %-8d: 82 |18 |18 |-46 |
|
||||
Bitvectors with %-9d: 82 |18 |18 |-46 |
|
||||
|
||||
|
||||
-------------------------------
|
||||
-- Support for integer types --
|
||||
-------------------------------
|
||||
|
||||
|
||||
-- Template of the call: (<fs> stands for the format specifier)
|
||||
|
||||
> fprint(RESULT, L, "Integers with <fs>: %4{<fs>|}\n",
|
||||
> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
> );
|
||||
|
||||
-- Results of the call with various format specifiers
|
||||
|
||||
Integers with %5d: 5678|-8765|12345678|-87654321|
|
||||
Integers with %6d: 5678| -8765|12345678|-87654321|
|
||||
Integers with %7d: 5678| -8765|12345678|-87654321|
|
||||
Integers with %8d: 5678| -8765|12345678|-87654321|
|
||||
Integers with %9d: 5678| -8765| 12345678|-87654321|
|
||||
Integers with %10d: 5678| -8765| 12345678| -87654321|
|
||||
|
||||
Integers with %-5d: 5678 |-8765|12345678|-87654321|
|
||||
Integers with %-6d: 5678 |-8765 |12345678|-87654321|
|
||||
Integers with %-7d: 5678 |-8765 |12345678|-87654321|
|
||||
Integers with %-8d: 5678 |-8765 |12345678|-87654321|
|
||||
Integers with %-9d: 5678 |-8765 |12345678 |-87654321|
|
||||
Integers with %-10d: 5678 |-8765 |12345678 |-87654321 |
|
||||
|
||||
Integers with %5r: 5678|-8765| 5678|-4321|
|
||||
Integers with %6r: 5678|- 8765| 45678|-54321|
|
||||
Integers with %7r: 5678|- 8765| 345678|-654321|
|
||||
Integers with %8r: 5678|- 8765| 2345678|-7654321|
|
||||
Integers with %9r: 5678|- 8765| 12345678|-87654321|
|
||||
Integers with %10r: 5678|- 8765| 12345678|- 87654321|
|
||||
|
||||
Integers with %-5r: 5678|-8765| 1234|-8765|
|
||||
Integers with %-6r: 5678 |-8765 | 12345|-87654|
|
||||
Integers with %-7r: 5678 |-8765 | 123456|-876543|
|
||||
Integers with %-8r: 5678 |-8765 | 1234567|-8765432|
|
||||
Integers with %-9r: 5678 |-8765 | 12345678|-87654321|
|
||||
Integers with %-10r: 5678 |-8765 | 12345678 |-87654321 |
|
||||
|
||||
|
||||
----------------------
|
||||
-- Support for time --
|
||||
----------------------
|
||||
-- For portability reasons, time is converted
|
||||
-- into an integer value (of nanoseconds)
|
||||
> wait for 648 ns
|
||||
> fprint (RESULT, L, "The time is now %d ns\n", fo(now));
|
||||
The time is now 648 ns
|
||||
|
||||
----------------------------------------
|
||||
-- Erroneous calls and error messages --
|
||||
----------------------------------------
|
||||
|
||||
-- Less arguments than formats specifiers
|
||||
> fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
|
||||
82 18
|
||||
** Warning: FIO_PrintLastValue: Format specifier beyond last argument
|
||||
** in format string: "%d %d %d %d \n"
|
||||
** ------^
|
||||
|
||||
-- Unsupported format specifier
|
||||
> fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
|
||||
0x52
|
||||
** Warning: FIO_PrintArg: Unexpected format specifier 'v'
|
||||
** in format string: "%r %v %r %r\n"
|
||||
** ----^
|
||||
** Assuming 'q' to proceed: V:0010010 0x52 0x12
|
||||
|
||||
|
||||
----------------------------------------
|
||||
-- Things you wouldn't expect to work --
|
||||
----------------------------------------
|
||||
|
||||
-- Nested iteration
|
||||
> fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
|
||||
<<_END__END__END_>><<_END__END__END_>><<_END__END__END_>>
|
||||
@@ -1,916 +0,0 @@
|
||||
---- File: PCK_FIO.vhd
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 1999 Easics NV
|
||||
----
|
||||
---- This program is free software; you can redistribute it and/or modify
|
||||
---- it under the terms of the GNU General Public License as published by
|
||||
---- the Free Software Foundation; either version 1, or (at your option)
|
||||
---- any later version.
|
||||
----
|
||||
---- This program is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
---- GNU General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU General Public License
|
||||
---- along with this program; if not, write to the Free Software
|
||||
---- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
----
|
||||
---- Revision history:
|
||||
----
|
||||
---- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/PCK_FIO.vhd,v $
|
||||
---- $Revision: 1.1 $
|
||||
---- $Log: not supported by cvs2svn $
|
||||
---- Revision 1.16 1999/04/21 08:28:46 jand
|
||||
---- Tested with IEEE.numeric_std
|
||||
---- Small patch for Leapfrog
|
||||
----
|
||||
---- Revision 1.14 1997/07/14 10:16:04 jand
|
||||
---- prefix/postfix for bits/bitvectors set to empty strings by default
|
||||
----
|
||||
---- Revision 1.13 1997/07/11 17:42:57 jand
|
||||
---- Corrected Easics address
|
||||
----
|
||||
---- Revision 1.12 1997/07/11 17:38:49 jand
|
||||
---- Improved prefix/postfix support
|
||||
----
|
||||
---- Revision 1.11 1995/11/15 13:46:02 jand
|
||||
---- Catched integer'low value in fo for integers
|
||||
----
|
||||
---- Revision 1.10 1995/08/11 16:42:26 jand
|
||||
---- Reimplemented FIO_FormatExpand as a procedure in an attempt to
|
||||
---- avoid memory leakage problems in VSS
|
||||
----
|
||||
---- Revision 1.9 1995/08/09 13:47:51 jand
|
||||
---- Removed array of line trick in fprint for less memory, less
|
||||
---- CPU time, and more conservatism in general
|
||||
---- Rearranged FIO_PrintValue call so that fprint remains concise
|
||||
----
|
||||
---- Revision 1.8 1995/08/09 10:32:27 jand
|
||||
---- Removed fprint_flat to have a single call level
|
||||
---- Added explicit deallocators of line variables (has strong influence
|
||||
---- on memory usage in VSS - and possibly CPU time)
|
||||
---- Redefined 'fo' for type time to make it more portable
|
||||
----
|
||||
---- Revision 1.7 1995/08/07 08:56:04 jand
|
||||
---- Improved conciseness of fprint argument handling through array of line type
|
||||
----
|
||||
---- Revision 1.6 1995/08/04 18:19:13 jand
|
||||
---- Increase # arguments from 16 to 32
|
||||
---- Corrected bug within fprint 's call to Arg16
|
||||
---- Added support for bit format specifier 'b'
|
||||
----
|
||||
---- Revision 1.5 1995/08/02 10:22:37 jand
|
||||
---- Release 1.1 under GNU
|
||||
----
|
||||
---- Revision 1.4 1995/08/01 11:15:52 jand
|
||||
---- Added escaping during iteration string read
|
||||
----
|
||||
---- Revision 1.3 1995/08/01 08:23:47 jand
|
||||
---- Many improvements in robustness, conciseness and coding style
|
||||
----
|
||||
---- Revision 1.2 1995/07/30 16:15:43 jand
|
||||
---- Improved robustness for release to the world
|
||||
----
|
||||
---- Revision 1.1 1995/07/30 14:21:30 jand
|
||||
---- Initial revision
|
||||
----
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
-- use IEEE.numeric_std.all;
|
||||
|
||||
package PCK_FIO is
|
||||
|
||||
-- prefix string for hex output
|
||||
-- VHDL style: "X"""
|
||||
-- Verilog style: "h'"
|
||||
-- C style: "0x"
|
||||
constant FIO_h_PRE: string := "0x";
|
||||
|
||||
-- postfix string for hex output
|
||||
-- VHDL style: """"
|
||||
constant FIO_h_POST: string := "";
|
||||
|
||||
-- prefix string for bit vector output
|
||||
-- VHDL style: "B"""
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_bv_PRE: string := "";
|
||||
|
||||
-- postfix string for bit vector output
|
||||
-- VHDL style: """"
|
||||
constant FIO_bv_POST: string := "";
|
||||
|
||||
-- prefix string for bit output
|
||||
-- VHDL style: "'"
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_b_PRE: string := "";
|
||||
|
||||
-- postfix string for bit output
|
||||
-- VHDL style: "'"
|
||||
constant FIO_b_POST: string := "";
|
||||
|
||||
-- digit width for the string representation of integers
|
||||
constant FIO_d_WIDTH: integer := 10;
|
||||
|
||||
-- bit width for the string representation of integers
|
||||
constant FIO_b_WIDTH: integer := 32;
|
||||
|
||||
-- definition of the NIL string (default value for fprint arguments)
|
||||
-- fprint stops consuming arguments at the first NIL argument
|
||||
constant FIO_NIL: string := "\";
|
||||
|
||||
procedure fprint
|
||||
(F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
);
|
||||
|
||||
function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive);
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
|
||||
package body PCK_FIO is
|
||||
|
||||
|
||||
--------------------------
|
||||
-- FIO Warnings support --
|
||||
--------------------------
|
||||
|
||||
procedure FIO_Warning_Fsbla (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
|
||||
"Format specifier beyond last argument\n");
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format);
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n");
|
||||
end FIO_Warning_Fsbla;
|
||||
|
||||
procedure FIO_Warning_Ufs (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive;
|
||||
Char: in character) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintArg: " &
|
||||
"Unexpected format specifier '%r'\n",
|
||||
fo(Char));
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format) ;
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n** Assuming 'q' to proceed: ");
|
||||
end FIO_Warning_Ufs;
|
||||
|
||||
|
||||
----------------------------------
|
||||
-- bit conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_bit_map is array(bit) of character;
|
||||
|
||||
constant C_BIT_MAP: T_bit_map
|
||||
:= ('0', '1');
|
||||
|
||||
----------------------------------
|
||||
-- std_logic conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_std_logic_map is array(std_ulogic) of character;
|
||||
|
||||
constant C_STD_LOGIC_MAP: T_std_logic_map
|
||||
:= ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
|
||||
|
||||
------------------------------
|
||||
-- Digit conversion support --
|
||||
------------------------------
|
||||
|
||||
-- types & constants
|
||||
|
||||
subtype S_digit_chars is character range '0' to '9';
|
||||
subtype S_digits is integer range 0 to 9 ;
|
||||
|
||||
type T_digit_chars_map is array(S_digit_chars) of S_digits;
|
||||
|
||||
constant C_DIGIT_CHARS_MAP: T_digit_chars_map
|
||||
:= (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
|
||||
|
||||
type T_digits_map is array(S_digits) of S_digit_chars;
|
||||
|
||||
constant C_DIGITS_MAP: T_digits_map
|
||||
:= ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
|
||||
|
||||
|
||||
--------------------------------
|
||||
-- Decimal conversion support --
|
||||
--------------------------------
|
||||
|
||||
function U_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end U_To_d;
|
||||
|
||||
function S_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
case Argument(Argument'left) is
|
||||
when '1' => Result := - 2**(Argument'left-1);
|
||||
when '0' => Result := 0;
|
||||
when others => return (integer'low);
|
||||
end case;
|
||||
for i in Argument'left-1 downto 1 loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(integer'low);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end S_To_d;
|
||||
|
||||
function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
|
||||
constant Sign: character := Arg(1);
|
||||
constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
|
||||
variable Char: character;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
Result := 0;
|
||||
for i in Value'range loop
|
||||
Result := Result * 10;
|
||||
Char := Value(i);
|
||||
if (Char /= ' ') then
|
||||
Result := Result + C_DIGIT_CHARS_MAP(Char);
|
||||
end if;
|
||||
end loop;
|
||||
case Sign is when '-' => return(-Result);
|
||||
when others => return(Result);
|
||||
end case;
|
||||
end I_To_d;
|
||||
|
||||
function B_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "1" => return(1);
|
||||
when "0" => return(0);
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end B_To_d;
|
||||
|
||||
function L_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "T" => return(1);
|
||||
when others => return(0);
|
||||
end case;
|
||||
end L_To_d;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Hex conversion support --
|
||||
----------------------------
|
||||
|
||||
-- Constants & types
|
||||
|
||||
constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
|
||||
|
||||
-- Function to return Hex index of a nibble
|
||||
|
||||
function U_To_h_Index(Arg: string(4 downto 1)) return integer is
|
||||
variable Index: integer := 0;
|
||||
begin
|
||||
for i in Arg'range loop
|
||||
case Arg(i) is when '1' => Index := 2**(i-1) + Index;
|
||||
when '0' => null;
|
||||
when others => return (17);
|
||||
end case;
|
||||
end loop;
|
||||
return (Index+1);
|
||||
end U_To_h_Index;
|
||||
|
||||
-- Hex conversion
|
||||
|
||||
function U_To_h (Arg: string) return string is
|
||||
variable Result: string((Arg'length-1)/4 +1 downto 1);
|
||||
variable ExtArg: string(Result'length*4 downto 1) := (others => '0');
|
||||
begin
|
||||
ExtArg(Arg'length downto 1) := Arg;
|
||||
for i in Result'range loop
|
||||
Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));
|
||||
end loop;
|
||||
return (FIO_h_PRE & Result & FIO_h_POST);
|
||||
end U_To_h;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Bit conversion support --
|
||||
----------------------------
|
||||
|
||||
function L_To_b (Arg: string(1 to 1)) return string is
|
||||
variable Result: string(1 to 1);
|
||||
begin
|
||||
case Arg is when "T" => Result := "1";
|
||||
when others => Result := "0";
|
||||
end case;
|
||||
return(FIO_b_PRE & Result & FIO_b_POST);
|
||||
end L_To_b;
|
||||
|
||||
|
||||
function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
|
||||
variable IntValue: integer := I_To_d(Arg);
|
||||
variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable BitWidth: integer range 0 to FIO_b_WIDTH;
|
||||
variable MsPos: integer range 1 to BitValue'length;
|
||||
variable BitValueExtended: string(1 to 2*FIO_b_WIDTH);
|
||||
|
||||
begin
|
||||
|
||||
if (IntValue < 0) then
|
||||
Sign := '-';
|
||||
IntValue := -IntValue;
|
||||
end if;
|
||||
|
||||
for i in BitValue'reverse_range loop
|
||||
BitValue(i) := C_DIGITS_MAP(IntValue mod 2);
|
||||
IntValue := IntValue / 2;
|
||||
exit when (IntValue = 0);
|
||||
end loop;
|
||||
|
||||
BitValueExtended := BitValue & Blanks;
|
||||
|
||||
if (Width = 0) or (Width > FIO_b_WIDTH+1) then
|
||||
BitWidth := FIO_b_WIDTH;
|
||||
else
|
||||
BitWidth := Width-1;
|
||||
end if;
|
||||
|
||||
if (Justified = RIGHT) then
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) &
|
||||
FIO_bv_POST);
|
||||
else
|
||||
for i in BitValue'range loop
|
||||
if BitValue(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) &
|
||||
FIO_bv_POST);
|
||||
end if;
|
||||
|
||||
end I_To_b;
|
||||
|
||||
|
||||
-----------------------------------
|
||||
-- Reasonable conversion support --
|
||||
-----------------------------------
|
||||
|
||||
function I_To_r (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
|
||||
constant Sign: character := Arg(1);
|
||||
constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable IntWidth: integer range 0 to FIO_d_WIDTH;
|
||||
variable MsPos: integer range 1 to Value'length;
|
||||
variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks;
|
||||
begin
|
||||
if (Width = 0) or (Width > FIO_d_WIDTH+1) then
|
||||
IntWidth := FIO_d_WIDTH;
|
||||
else
|
||||
IntWidth := Width-1;
|
||||
end if;
|
||||
if (Justified = RIGHT) then
|
||||
return (Sign & Value(Value'length-IntWidth+1 to Value'length));
|
||||
else
|
||||
for i in Value'range loop
|
||||
if Value(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
|
||||
end if;
|
||||
end I_To_r;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Reasonable output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function ReasonableOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return U_To_h(Value);
|
||||
when "I:" =>
|
||||
return I_To_r(Value, Justified, Width);
|
||||
when "B:" | "L:" | "C:" =>
|
||||
return Value;
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end ReasonableOutput;
|
||||
|
||||
|
||||
------------------------------------
|
||||
-- Bit output conversion function --
|
||||
------------------------------------
|
||||
|
||||
function BitOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return (FIO_bv_PRE & Value & FIO_bv_POST);
|
||||
when "B:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);
|
||||
when "I:" =>
|
||||
return I_To_b(Value, Justified, Width);
|
||||
when "L:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return L_To_b(Value(1 to 1));
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end BitOutput;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Decimal output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function DecimalOutput (Arg: string) return integer is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:"| "V:" =>
|
||||
return U_To_d(Value);
|
||||
when "S:" =>
|
||||
return S_To_d(Value);
|
||||
when "I:" =>
|
||||
return I_To_d(Value);
|
||||
when "B:" =>
|
||||
return B_To_d(Value);
|
||||
when "L:" =>
|
||||
return L_To_d(Value);
|
||||
when others =>
|
||||
return integer'low;
|
||||
end case;
|
||||
|
||||
end DecimalOutput;
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Atomic print functions --
|
||||
----------------------------
|
||||
|
||||
function FIO_EOS (Format: in string;
|
||||
Pointer: in integer)
|
||||
return boolean is
|
||||
begin
|
||||
return (Pointer > Format'length);
|
||||
end FIO_EOS;
|
||||
|
||||
|
||||
-- Atomic value print function
|
||||
|
||||
procedure FIO_PrintValue (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Last: in boolean := FALSE) is
|
||||
variable Char: character;
|
||||
begin
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '\' =>
|
||||
Pointer := Pointer + 1;
|
||||
exit when (FIO_EOS(Format, Pointer));
|
||||
Char := Format(Pointer);
|
||||
case Char is when 'n' => writeline(F, L);
|
||||
when others => write(L, Char);
|
||||
end case;
|
||||
when '%' =>
|
||||
if Last then
|
||||
FIO_Warning_Fsbla(F, L, Format, Pointer);
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
write(L, char);
|
||||
end case;
|
||||
Pointer := Pointer + 1;
|
||||
end loop;
|
||||
end FIO_PrintValue;
|
||||
|
||||
|
||||
---- Atomic argument print function
|
||||
|
||||
procedure FIO_PrintArg (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Arg: in string) is
|
||||
variable Char: character;
|
||||
variable Justified: side;
|
||||
variable Width: integer;
|
||||
begin
|
||||
|
||||
FIO_PrintValue(F, L, Format, Pointer);
|
||||
|
||||
Justified := RIGHT;
|
||||
Width := 0;
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '-' =>
|
||||
Justified := LEFT;
|
||||
Pointer := Pointer + 1;
|
||||
when '0' to '9' =>
|
||||
Width := Width*10 + C_DIGIT_CHARS_MAP(Char);
|
||||
Pointer := Pointer + 1;
|
||||
when 'r' =>
|
||||
write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'b' =>
|
||||
write(L, BitOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'd' =>
|
||||
write(L, DecimalOutput(Arg), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'q' | 's' =>
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
FIO_Warning_Ufs(F, L, Format, Pointer, Char);
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
end case;
|
||||
end loop;
|
||||
end FIO_PrintArg;
|
||||
|
||||
|
||||
-----------------------------------------------------
|
||||
-- The format string iteration expansion procedure --
|
||||
-----------------------------------------------------
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive) is
|
||||
|
||||
variable Pointer: positive := StartPointer;
|
||||
variable TokenStart: positive;
|
||||
variable IterStringStart: positive;
|
||||
variable IterStringEnd: positive;
|
||||
variable IterCount: natural;
|
||||
variable OpenBrackets: natural;
|
||||
variable L: line;
|
||||
|
||||
begin
|
||||
|
||||
FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- look for format specifier
|
||||
when '%' =>
|
||||
|
||||
-- initialize iteration token search
|
||||
TokenStart := Pointer;
|
||||
IterCount := 0;
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- start iteration token search
|
||||
TOKEN_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- read iteration counter
|
||||
when '0' to '9' =>
|
||||
IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer));
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- expect open bracket
|
||||
when '{' =>
|
||||
|
||||
-- initialize iteration string read
|
||||
OpenBrackets := 1;
|
||||
IterStringStart := Pointer + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- quit prematurely when iteration count is 0
|
||||
next FORMAT_SEARCH when (IterCount = 0);
|
||||
|
||||
-- start iteration string read
|
||||
ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
-- keep track of open brackets
|
||||
when '{' =>
|
||||
OpenBrackets := OpenBrackets + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- when closing bracket is found, process iteration string
|
||||
when '}' =>
|
||||
OpenBrackets := OpenBrackets - 1;
|
||||
if (OpenBrackets = 0) then
|
||||
IterStringEnd := Pointer-1;
|
||||
if (TokenStart /= 1) then
|
||||
write(L, Format(1 to TokenStart-1));
|
||||
end if;
|
||||
for i in 1 to IterCount loop
|
||||
write(L, Format(IterStringStart to IterStringEnd));
|
||||
end loop;
|
||||
if (IterStringEnd /= Format'length) then
|
||||
write(L, Format(IterStringEnd+2 to Format'length));
|
||||
end if;
|
||||
-- call expansion procedure recursively on expanded format
|
||||
FIO_FormatExpand(FMT, L.all, TokenStart);
|
||||
deallocate(L);
|
||||
return;
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
-- read iteration string
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop ITER_STRING_READ;
|
||||
|
||||
-- stop iteration token search when no opening bracket found
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
next FORMAT_SEARCH;
|
||||
|
||||
end case;
|
||||
|
||||
end loop TOKEN_READ;
|
||||
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
|
||||
-- read other characters
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop FORMAT_SEARCH;
|
||||
|
||||
write(FMT, Format);
|
||||
deallocate(L);
|
||||
|
||||
end FIO_FormatExpand;
|
||||
|
||||
|
||||
|
||||
--------------------------
|
||||
-- The fprint procedure --
|
||||
--------------------------
|
||||
|
||||
procedure fprint
|
||||
(F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
) is
|
||||
|
||||
variable Pointer: integer;
|
||||
variable FMT: line;
|
||||
|
||||
begin
|
||||
|
||||
Pointer := 1;
|
||||
|
||||
FIO_FormatExpand (FMT, Format, Format'low);
|
||||
|
||||
if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
|
||||
if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
|
||||
if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
|
||||
if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
|
||||
if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
|
||||
if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
|
||||
if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
|
||||
if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
|
||||
if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
|
||||
if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
|
||||
if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
|
||||
if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
|
||||
if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
|
||||
if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
|
||||
if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
|
||||
if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
|
||||
if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
|
||||
if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
|
||||
if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
|
||||
if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
|
||||
if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
|
||||
if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
|
||||
if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
|
||||
if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
|
||||
if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
|
||||
if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
|
||||
if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
|
||||
if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
|
||||
if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
|
||||
if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
|
||||
if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
|
||||
if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
|
||||
FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
|
||||
|
||||
deallocate(FMT);
|
||||
|
||||
end fprint;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Formatted output conversion functions --
|
||||
-------------------------------------------
|
||||
|
||||
function fo (Arg: unsigned) return string is
|
||||
constant Argument: unsigned(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("U:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: signed) return string is
|
||||
constant Argument: signed(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("S:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_logic_vector) return string is
|
||||
constant Argument: std_logic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic_vector) return string is
|
||||
constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit_vector) return string is
|
||||
constant Argument: bit_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_BIT_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: integer) return string is
|
||||
variable Argument: integer := Arg;
|
||||
variable Result: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
begin
|
||||
if (Argument < 0) and (Argument /= integer'low) then
|
||||
Sign := '-';
|
||||
Argument := -Argument;
|
||||
end if;
|
||||
for i in Result'reverse_range loop
|
||||
Result(i) := C_DIGITS_MAP(Argument mod 10);
|
||||
Argument := Argument / 10;
|
||||
exit when (Argument = 0);
|
||||
end loop;
|
||||
return ("I:" & Sign & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic) return string is
|
||||
begin
|
||||
return ("B:" & C_STD_LOGIC_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit) return string is
|
||||
begin
|
||||
return ("B:" & C_BIT_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: boolean) return string is
|
||||
begin
|
||||
if (ARG = TRUE) then
|
||||
return ("L:T");
|
||||
else
|
||||
return ("L:F");
|
||||
end if;
|
||||
end fo;
|
||||
|
||||
function fo (Arg: character) return string is
|
||||
begin
|
||||
return ("C:" & Arg);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: string) return string is
|
||||
begin
|
||||
return Arg;
|
||||
end fo;
|
||||
|
||||
function fo (Arg: time) return string is
|
||||
begin
|
||||
return fo (integer (Arg / 1 ns));
|
||||
end fo;
|
||||
|
||||
end PCK_FIO;
|
||||
@@ -1,72 +0,0 @@
|
||||
# $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
# $Log: not supported by cvs2svn $
|
||||
# Revision 1.3 1999/04/21 08:08:35 jand
|
||||
# Tested with IEEE.numeric_std
|
||||
# Small patch for Leapfrog
|
||||
#
|
||||
#
|
||||
|
||||
PCK_FIO, Version 1.16
|
||||
Copyright (C) 1995, 1999 Easics NV
|
||||
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 1999 Easics NV
|
||||
----
|
||||
---- This program is free software; you can redistribute it and/or modify
|
||||
---- it under the terms of the GNU General Public License as published by
|
||||
---- the Free Software Foundation; either version 1, or (at your option)
|
||||
---- any later version.
|
||||
----
|
||||
---- This program is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
---- GNU General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU General Public License
|
||||
---- along with this program; if not, write to the Free Software
|
||||
---- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
Contents
|
||||
--------
|
||||
|
||||
This distribution contains the following files:
|
||||
|
||||
PCK_FIO.vhd: VHDL source of the PCK_FIO package
|
||||
TB_PCK_FIO.vhd: VHDL source of the testbench for package PCK_FIO
|
||||
PCK_FIO.out.gold: Certified test bench output
|
||||
PCK_FIO.html: Manual for PCK_FIO in html format
|
||||
README: This file
|
||||
|
||||
|
||||
Installation
|
||||
------------
|
||||
|
||||
To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
|
||||
analyze the VHDL file PCK_FIO.vhd into this library.
|
||||
|
||||
To install the test bench, analyze TB_PCK_FIO.vhd into the same library.
|
||||
|
||||
If you want to use IEEE.numeric_std instead of IEEE.std_logic_arith, you need
|
||||
to edit the source code of the package and the test bench and replace the
|
||||
package use clause. PCK_FIO works with either of these packages.
|
||||
|
||||
To install the documentation, point your web browser to the file PCK_FIO.html
|
||||
and bookmark it.
|
||||
|
||||
|
||||
Installation check
|
||||
------------------
|
||||
|
||||
After installing the test bench, you should run it. The corresponding VHDL
|
||||
design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB).
|
||||
|
||||
Simulating the test bench should create a file called PCK_FIO.out. This file
|
||||
should be identical to PCK_FIO.out.gold. Any difference indicates a portability
|
||||
issue or a simulator non-compliance or bug.
|
||||
@@ -1,504 +0,0 @@
|
||||
---- File: TB_PCK_FIO.vhd
|
||||
----
|
||||
---- TBC_PCK_FIO: a test bench for the PCK_FIO package.
|
||||
---- Copyright (C) 1995, 1999 Easics NV
|
||||
----
|
||||
---- This program is free software; you can redistribute it and/or modify
|
||||
---- it under the terms of the GNU General Public License as published by
|
||||
---- the Free Software Foundation; either version 1, or (at your option)
|
||||
---- any later version.
|
||||
----
|
||||
---- This program is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
---- GNU General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU General Public License
|
||||
---- along with this program; if not, write to the Free Software
|
||||
---- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 396 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
----
|
||||
---- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd,v $
|
||||
---- $Revision: 1.1 $
|
||||
---- $Log: not supported by cvs2svn $
|
||||
---- Revision 1.7 1999/04/21 08:23:53 jand
|
||||
---- Tested with IEEE.numeric_std
|
||||
---- Small patch for Leapfrog
|
||||
----
|
||||
---- Revision 1.3 1998/09/29 10:09:44 vhdl
|
||||
---- to EASICS_PACKAGES
|
||||
----
|
||||
---- Revision 1.2 1998/09/29 09:17:51 vhdl
|
||||
---- library EASICS_PACKAGES;
|
||||
----
|
||||
---- Revision 1.1 1998/09/29 09:15:44 vhdl
|
||||
---- Initial revision
|
||||
----
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
-- use IEEE.numeric_std.all;
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library EASICS_PACKAGES;
|
||||
use EASICS_PACKAGES.PCK_FIO.all;
|
||||
|
||||
entity TBE_PCK_FIO is
|
||||
|
||||
end TBE_PCK_FIO;
|
||||
|
||||
architecture TB of TBE_PCK_FIO is
|
||||
|
||||
begin
|
||||
|
||||
USAGE: process
|
||||
|
||||
file RESULT: text is out "PCK_FIO.out";
|
||||
variable L: line;
|
||||
variable Pointer: integer;
|
||||
variable BoolTrue: boolean := TRUE;
|
||||
variable BoolFalse: boolean := FALSE;
|
||||
variable IntPos: integer := 5678;
|
||||
variable BigIntPos: integer := 12345678;
|
||||
variable IntNeg: integer := -8765;
|
||||
variable BigIntNeg: integer := -87654321;
|
||||
variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
|
||||
variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
|
||||
variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
|
||||
variable SigPos: signed(6 downto 0) := signed'("0010010");
|
||||
variable SigNeg: signed(6 downto 0) := signed'("1010010");
|
||||
variable BitX: std_logic := 'X';
|
||||
variable Bit1: std_logic := '1';
|
||||
variable Bit0: std_logic := '0';
|
||||
|
||||
variable parameter_1: integer := 1234;
|
||||
variable parameter_2: integer := 2345;
|
||||
variable parameter_3: integer := 4567;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
fprint(RESULT, L,
|
||||
"PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
|
||||
"-----------------------------------------\n\n" &
|
||||
"This is the result of running the PCK_FIO testbench.\n" &
|
||||
"This file should be compared with PCK_FIO.out.gold, which is\n" &
|
||||
"the reference output. Any difference indicates a portability\n" &
|
||||
"issue or a simulator non-compliance or bug.\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n--------------------\n" &
|
||||
"-- Basic features --\n" &
|
||||
"--------------------\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"-- First some auxiliary declarations\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"> file RESULT: text is out ""PCK_FIO.out"";\n" &
|
||||
"> variable L: line;\n" &
|
||||
"> variable BoolTrue: boolean := TRUE;\n" &
|
||||
"> variable BoolFalse: boolean := FALSE;\n" &
|
||||
"> variable IntPos: integer := 5678;\n" &
|
||||
"> variable BigIntPos: integer := 12345678;\n" &
|
||||
"> variable IntNeg: integer := -8765;\n" &
|
||||
"> variable BigIntNeg: integer := -87654321;\n" &
|
||||
"> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
|
||||
"> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
|
||||
"> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
|
||||
"> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" &
|
||||
"> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" &
|
||||
"> variable BitX: std_logic := 'X';\n" &
|
||||
"> variable Bit1: std_logic := '1';\n" &
|
||||
"> variable Bit0: std_logic := '0';\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n-- fprint call with no arguments\n" &
|
||||
"> fprint(RESULT, L, ""No arguments.\\n);""\n"
|
||||
);
|
||||
fprint(RESULT, L, "No arguments.\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Special characters need to be escaped\n" &
|
||||
"> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Special characters: \% \\ "" \n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Various format specifiers interprete the same object differently\n" &
|
||||
"> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n);""\n" &
|
||||
"> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
|
||||
fo(Uns), fo(Uns), fo(Uns), fo(Uns)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Format string can be shortened by using the iteration specifier\n" &
|
||||
"> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n);""\n" &
|
||||
"> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
|
||||
fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n------------------------------------\n" &
|
||||
"-- Support for bit-oriented types --\n" &
|
||||
"------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Reasonable format\n" &
|
||||
"> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Reasonable format: %9{%r }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Decimal format\n" &
|
||||
"> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Decimal format: %9{%d }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Bit format\n" &
|
||||
"> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Bit format: %9{%b }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Alignment\n-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Bitvectors with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
|
||||
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-------------------------------\n" &
|
||||
"-- Support for integer types --\n" &
|
||||
"-------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Integers with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
|
||||
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------\n" &
|
||||
"-- Support for time --\n" &
|
||||
"----------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
|
||||
"-- into an integer value (of nanoseconds)\n"
|
||||
);
|
||||
fprint (RESULT, L, "> wait for 648 ns\n");
|
||||
fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
|
||||
|
||||
wait for 648 ns;
|
||||
|
||||
fprint (RESULT, L, "The time is now %d ns\n", fo(now));
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Erroneous calls and error messages --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
|
||||
"> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L, "-- Unsupported format specifier\n" &
|
||||
"> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
|
||||
"fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Things you wouldn't expect to work --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Nested iteration\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
|
||||
fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
|
||||
|
||||
wait;
|
||||
|
||||
end process USAGE;
|
||||
|
||||
end TB;
|
||||
@@ -1,86 +0,0 @@
|
||||
---- $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
Changes from version 1.16 to version 2002.07
|
||||
============================================
|
||||
|
||||
PCK_FIO is now distributed under the GNU Lesser General Public Licencse
|
||||
instead of the ordinary GPL, to better reflect intended usage.
|
||||
|
||||
Cosmetic changes in source code to correct some typos in the testbench output.
|
||||
A new testbench is also supplied.
|
||||
|
||||
The package now uses IEEE.numeric_std as default.
|
||||
|
||||
URL http://www.easics.com has been made part of address.
|
||||
|
||||
Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993.
|
||||
Because of backwards-incompatibility, it has been necessary to supply
|
||||
different sets of files for 1987 and 1993.
|
||||
|
||||
Split the packages into a separate file for the header and a
|
||||
separate file for the body (in compliance with Easics' guidelines).
|
||||
|
||||
These changes resulted in the files:
|
||||
|
||||
Files for VHDL-1993:
|
||||
--------------------
|
||||
PCK_FIO_1993.vhd : the source code of the header file for the package
|
||||
PCK_FIO_1993_BODY.vhd: the source code of the body of the package
|
||||
TB_PCK_FIO_1993.vhd: the testbench for the package
|
||||
|
||||
Files for VHDL-1987:
|
||||
--------------------
|
||||
PCK_FIO_1987.vhd: the source code of the header file for the package
|
||||
PCK_FIO_1987_BODY.vhd: the source code of the body of the package
|
||||
TB_PCK_FIO_1987.vhd: the testbench for the package
|
||||
|
||||
Updated README and PCK_FIO.html to support these changes.
|
||||
|
||||
Adapted package files to support NUL termination of strings.
|
||||
fo(Arg: string) now prints the string until the first NUL.
|
||||
Several examples of its use are demonstrated in the supplied testbenches.
|
||||
|
||||
Made cosmetic changes to code to improve readability.
|
||||
|
||||
Acknowledgment
|
||||
--------------
|
||||
These changes have been implemented by Peter Geens.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,339 +0,0 @@
|
||||
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
|
||||
<html>
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
|
||||
<meta name="GENERATOR" content="Mozilla/4.76 [en] (X11; U; Linux 2.4.13 i686) [Netscape]">
|
||||
<title>VHDL package for formatted file output</title>
|
||||
<!-- $Id: PCK_FIO.html,v 1.1 2008-08-23 08:20:28 Jens Exp $ -->
|
||||
</head>
|
||||
<body text="#000000" bgcolor="#FFFFFF" link="#0000EE" vlink="#551A8B" alink="#FF0000">
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_name_0"></a>Name</h1>
|
||||
<b>PCK_FIO</b> - VHDL package for formatted file output
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
Contents</h1>
|
||||
<a href="#PCK_FIO_usage_0">Usage</a>
|
||||
<br><a href="#PCK_FIO_file_0">The file output function 'fo'</a>
|
||||
<br><a href="#PCK_FIO_format_0">Format specifiers</a>
|
||||
<br><a href="#PCK_FIO_special_0">Special characters</a>
|
||||
<br><a href="#PCK_FIO_things_0">Things to watch out for</a>
|
||||
<br><a href="#PCK_FIO_methodology_0">Methodology notes</a>
|
||||
<br><a href="#PCK_FIO_parametrization_0">Parametrization</a>
|
||||
<br><a href="#PCK_FIO_test_0">Test bench</a>
|
||||
<br><a href="#PCK_FIO_limitations_0">Known limitations and problems</a>
|
||||
<br><a href="#PCK_FIO_author_0">Author</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_usage_0"></a>Usage</h1>
|
||||
PCK_FIO is a VHDL package that defines <tt>fprint, </tt>a function
|
||||
for formatted file output.
|
||||
<p>After installing the package you can call <tt>fprint</tt> as follows:
|
||||
<pre> fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));</pre>
|
||||
where F is the filehandle and L is the line variable.
|
||||
<p>The argument Format is the format string, which consists of ``normal''
|
||||
substrings which are copied verbatim, and format specifiers, starting with
|
||||
<tt>'%'</tt>.
|
||||
A typical format string looks as follows:
|
||||
<pre> "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"</pre>
|
||||
The remaining arguments are the expressions whose results you want to write
|
||||
to the file, embedded in <tt>fo</tt> function calls. There can be 0 to
|
||||
32 of such arguments. The expressions can be of any type for which an <tt>fo</tt>
|
||||
function exists. String expressions can also be called directly.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_file_0"></a>The file output function <tt>'fo'</tt></h1>
|
||||
The <tt>fo</tt> (<u>f</u>ile <u>o</u>utput) functions do the trick. They
|
||||
return a tagged string representation that is meaningful to format specifiers.
|
||||
Here are some examples:
|
||||
<pre> fo (signed'("1100")) returns "S:1100"
|
||||
fo (unsigned'("1100")) returns "U:1100"
|
||||
fo (TRUE) returns "L:T"
|
||||
fo (127) returns "I:127"</pre>
|
||||
The internal behavior of <tt>fo</tt> is irrelevant to the typical user.
|
||||
<br>
|
||||
<pre>The <tt>fo</tt> function is currently overloaded as follows:</pre>
|
||||
|
||||
<pre> function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;</pre>
|
||||
|
||||
<p><br>To support null-terminated strings, the function <tt>fo</tt>(Arg:
|
||||
string) processes <tt>Arg</tt> up to the first <tt>NUL</tt> character,
|
||||
if any. If you want the whole string to be outputted you can just enter
|
||||
the string as a direct argument in <tt>fprint</tt>. See also the
|
||||
examples in the testbench.
|
||||
<pre>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%"></pre>
|
||||
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_format_0"></a>Format specifiers</h1>
|
||||
The general format of a format specifier is:
|
||||
<pre> %[-][n]c</pre>
|
||||
The optional <b>-</b> sign specifies left justified output; default is
|
||||
right justified.
|
||||
<p>The optional number <b>n</b> specifies a field-width. If it is not specified,
|
||||
<tt>fprint</tt>
|
||||
does something reasonable.
|
||||
<p><b>c</b> is the conversion specifier. Currently the following conversion
|
||||
specifiers are supported:
|
||||
<dl COMPACT>
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_r_0"></a><b>r</b></dt>
|
||||
|
||||
<dd>
|
||||
reasonable output format (inspired by Synopsys VSS)</dd>
|
||||
|
||||
<dl COMPACT>Prints the ``most reasonable'' representation e.g. hex for
|
||||
unsigned, signed and other bit-like vectors (not preferred for integers)</dl>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_b_0"></a><b>b</b></dt>
|
||||
|
||||
<dd>
|
||||
bit-oriented output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_d_0"></a><b>d</b></dt>
|
||||
|
||||
<dd>
|
||||
decimal output</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_s_0"></a><b>s</b></dt>
|
||||
|
||||
<dd>
|
||||
string output (e.g. in combination with 'IMAGE for enum types)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO_q_0"></a><b>q</b></dt>
|
||||
|
||||
<dd>
|
||||
``qualified'' string output (shows internal representation from <tt>fo</tt>)</dd>
|
||||
|
||||
<dt>
|
||||
<a NAME="PCK_FIO__0"></a><b>{}</b></dt>
|
||||
|
||||
<dd>
|
||||
Iteration operator, used as follows:</dd>
|
||||
|
||||
<dd>
|
||||
<tt>%n{<format-string>}</tt></dd>
|
||||
|
||||
<br>In this case, <b>n</b> is the iteration count and is mandatory. Iteration
|
||||
can be nested.</dl>
|
||||
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_special_0"></a>Special characters</h1>
|
||||
To print a double quote, use <tt>'""'</tt> in the format string (VHDL
|
||||
convention). To print the special characters, <tt>'\'</tt>, and <tt>'%'</tt>,
|
||||
escape them with <tt>'\'</tt>. To prevent <tt>'{'</tt> and <tt>'}'</tt>
|
||||
from being interpreted as opening and closing brackets in iteration strings,
|
||||
escape them with <tt>'\'</tt>.
|
||||
<p>A newline is specified in the format string by <tt>'\n'</tt>.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_things_0"></a>Things to notice</h1>
|
||||
The fprint function expands into VHDL <tt>write</tt> and <tt>writeline</tt>
|
||||
commands. As in plain VHDL, nothing will be written to the output file
|
||||
until a <tt>writeline</tt> is given. Therefore, don't forget to include
|
||||
<tt>'\n'</tt>
|
||||
commands in the format string, or it ``will not work''.
|
||||
<p>The preferred format specifier for integers is, naturally, <b>%d</b>.
|
||||
This calls the VHDL <tt>write</tt> for integers. If you specify a field
|
||||
width that is too small, the field will automatically be expanded. If you
|
||||
use <b>%r</b> for integers, the field is not expanded automatically, which
|
||||
means that some digits are simply thrown away. This may sometimes be useful
|
||||
but it is also dangerous. Look at the test bench output for differences
|
||||
between <b>%d</b> and <b>%r</b> output.
|
||||
<p>When using the <b>%d</b> format specifier, the VHDL constraints for
|
||||
the allowed integer range apply.
|
||||
<p>In VHDL, signed/unsigned types have been standardized only relatively
|
||||
recently, in the package <tt>IEEE.numeric_std</tt>. The lack of a standard
|
||||
has caused (and is causing) portability issues. The most popular non-standard
|
||||
package that defines signed/unsigned is <tt>IEEE.std_logic_arith</tt> from
|
||||
Synopsys. PCK_FIO works with both packages, but refers to the standard
|
||||
package <tt>IEEE.numeric_std</tt> by default. To use <tt>IEEE.std_logic_arith</tt>
|
||||
instead, replace the reference to <tt>IEEE.numeric_std</tt> in the source
|
||||
code. This needs to be done consistently in a design database (e.g.
|
||||
in the PCK_FIO test bench as well).
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_methodology_0"></a>Methodology notes</h1>
|
||||
The obvious application for <tt>fprint</tt> is in test benches, to produce
|
||||
output files that trace the simulation behavior.
|
||||
<p>Another interesting application for <tt>fprint</tt> is to produce info,
|
||||
warning and error messages in your models. As it can take arguments, <tt>fprint</tt>
|
||||
is much better suited for this task than VHDL's <tt>assert</tt> or <tt>report</tt>
|
||||
statements. Actually <tt>fprint</tt> produces its own (few) warning messages.
|
||||
<p>An advanced usage is the generation of test vectors in a specific format.
|
||||
Instead of using the <tt>fo </tt>functions, you can write your own set
|
||||
of functions that return the symbols of a specific test format in a way
|
||||
that is understandable to the <tt>fprint</tt> format specifiers. As an
|
||||
example, when a high output value should be represented using the symbol
|
||||
'H' it suffices to write a conversion function that returns "B:H" and call
|
||||
it in combination with the <b>%b</b> format specifier.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_parametrization_0"></a>Parametrization</h1>
|
||||
Prefix and postfix strings for bit-oriented and hex-oriented output are
|
||||
parameterizable in the packages to accommodate different output styles.
|
||||
The settings in the distribution are such that hex output is indicated
|
||||
by the prefix '0x', while bit output prefix and postfix are empty
|
||||
strings.
|
||||
<p>You can adapt the output style by modifying the following constants
|
||||
in the package header:
|
||||
<p> <tt> -- prefix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: "X"""</tt>
|
||||
<br><tt> -- Verilog style: "h'"</tt>
|
||||
<br><tt> -- C style: "0x"</tt>
|
||||
<br><tt> constant FIO_h_PRE: string := "0x";</tt>
|
||||
<p><tt> -- postfix string for hex output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_h_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: "B"""</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_bv_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit vector output</tt>
|
||||
<br><tt> -- VHDL style: """"</tt>
|
||||
<br><tt> constant FIO_bv_POST: string := "";</tt>
|
||||
<p><tt> -- prefix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> -- Verilog style: "b'"</tt>
|
||||
<br><tt> constant FIO_b_PRE: string := "";</tt>
|
||||
<p><tt> -- postfix string for bit output</tt>
|
||||
<br><tt> -- VHDL style: "'"</tt>
|
||||
<br><tt> constant FIO_b_POST: string := "";</tt>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_test_0"></a>Test bench</h1>
|
||||
Included in the distribution are the files <tt>TB_PCK_FIO_1987.vhd and
|
||||
TB_PCK_FIO_1993</tt> with a test bench,depending on the standard you're
|
||||
running, for the PCK_FIO package. The file <tt>PCK_FIO.out.gold </tt>contains
|
||||
the expected output. If you run the test bench it should produce the file
|
||||
<tt>PCK_FIO.out</tt>
|
||||
that should be identical to <tt>PCK_FIO.out.gold</tt>. The source files
|
||||
should be analyzed in a VHDL library <tt>EASICS_PACKAGES</tt>.
|
||||
<p>A good way to understand <tt>fprint</tt> is to inspect the test bench
|
||||
and what it produces.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_limitations_0"></a>Known limitations and problems</h1>
|
||||
This VHDL package is an implementation of a flexible concept. It is likely
|
||||
to be extended and modified in the future. Backward compatibility is not
|
||||
guaranteed. Therefore, it is not recommended to give this package the status
|
||||
of a company wide standard package (or even worse, a VHDL standard package).
|
||||
Rather, it should be linked with a particular project (and it can be regarded
|
||||
as a standard package within that project).
|
||||
<p>PCK_FIO is available in either standard VHDL Std1076-1987 or standard
|
||||
VHDL Std1076-1993. Nevertheless, some simulators/versions have problems
|
||||
with the package. The following is an overview of currently known issues:
|
||||
<br>
|
||||
<center><table BORDER COLS=2 WIDTH="80%" NOSAVE >
|
||||
<caption>PCK_FIO_1987 and various simulators/versions</caption>
|
||||
|
||||
<tr>
|
||||
<th>Simulator</th>
|
||||
|
||||
<th>PCK_FIO_1987</th>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 3.5 and earlier</td>
|
||||
|
||||
<td>Incorrect (all zero) output in compiled mode</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS 97.01</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.02</td>
|
||||
|
||||
<td>Incorrect output in compiled mode, interpreted mode works</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Mentor quickhdl</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr NOSAVE>
|
||||
<td NOSAVE>Modeltech modelsim</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Cadence Leapfrog</td>
|
||||
|
||||
<td>Should work with 4.4.1
|
||||
<br>Mysterious problems have been reported - please run the test bench
|
||||
and report problems</td>
|
||||
</tr>
|
||||
</table></center>
|
||||
|
||||
<br>
|
||||
<center><table BORDER COLS=2 WIDTH="80%" NOSAVE >
|
||||
<caption>PCK_FIO_1993 and various simulators/versions</caption>
|
||||
|
||||
<tr NOSAVE>
|
||||
<th NOSAVE>Simulator</th>
|
||||
|
||||
<th NOSAVE>PCK_FIO_1993</th>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.02</td>
|
||||
|
||||
<td>Compile errors due to improper handling of files by Synopsys</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Synopsys VSS/Scirocco 2000.06</td>
|
||||
|
||||
<td>works fine</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td>Modeltech modelsim 5.4c and higher</td>
|
||||
|
||||
<td>OK</td>
|
||||
</tr>
|
||||
</table></center>
|
||||
|
||||
<p>Although the package name suggests file IO, it only does file output.
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
<h1>
|
||||
<a NAME="PCK_FIO_author_0"></a>Author</h1>
|
||||
<a href="mailto:jand@easics.be">Jan Decaluwe</a>
|
||||
<p>
|
||||
<hr SIZE=1 NOSHADE WIDTH="100%">
|
||||
</body>
|
||||
</html>
|
||||
Binary file not shown.
@@ -1,105 +0,0 @@
|
||||
---- $Id: PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
package PCK_FIO is
|
||||
|
||||
-- prefix string for hex output
|
||||
-- VHDL style: "X"""
|
||||
-- Verilog style: "h'"
|
||||
-- C style: "0x"
|
||||
constant FIO_h_PRE: string := "0x";
|
||||
|
||||
-- postfix string for hex output
|
||||
-- VHDL style: """"
|
||||
constant FIO_h_POST: string := "";
|
||||
|
||||
-- prefix string for bit vector output
|
||||
-- VHDL style: "B"""
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_bv_PRE: string := "";
|
||||
|
||||
-- postfix string for bit vector output
|
||||
-- VHDL style: """"
|
||||
constant FIO_bv_POST: string := "";
|
||||
|
||||
-- prefix string for bit output
|
||||
-- VHDL style: "'"
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_b_PRE: string := "";
|
||||
|
||||
-- postfix string for bit output
|
||||
-- VHDL style: "'"
|
||||
constant FIO_b_POST: string := "";
|
||||
|
||||
-- digit width for the string representation of integers
|
||||
constant FIO_d_WIDTH: integer := 10;
|
||||
|
||||
-- bit width for the string representation of integers
|
||||
constant FIO_b_WIDTH: integer := 32;
|
||||
|
||||
-- definition of the NIL string (default value for fprint arguments)
|
||||
-- fprint stops consuming arguments at the first NIL argument
|
||||
constant FIO_NIL: string := "\";
|
||||
|
||||
|
||||
procedure fprint
|
||||
(F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
);
|
||||
|
||||
function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive);
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
@@ -1,821 +0,0 @@
|
||||
---- $Id: PCK_FIO_1987_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
package body PCK_FIO is
|
||||
|
||||
--------------------------
|
||||
-- FIO Warnings support --
|
||||
--------------------------
|
||||
|
||||
procedure FIO_Warning_Fsbla (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
|
||||
"Format specifier beyond last argument\n");
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format);
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n");
|
||||
end FIO_Warning_Fsbla;
|
||||
|
||||
procedure FIO_Warning_Ufs (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive;
|
||||
Char: in character) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintArg: " &
|
||||
"Unexpected format specifier '%r'\n",
|
||||
fo(Char));
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format) ;
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n** Assuming 'q' to proceed: ");
|
||||
end FIO_Warning_Ufs;
|
||||
|
||||
|
||||
----------------------------------
|
||||
-- bit conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_bit_map is array(bit) of character;
|
||||
|
||||
constant C_BIT_MAP: T_bit_map
|
||||
:= ('0', '1');
|
||||
|
||||
----------------------------------
|
||||
-- std_logic conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_std_logic_map is array(std_ulogic) of character;
|
||||
|
||||
constant C_STD_LOGIC_MAP: T_std_logic_map
|
||||
:= ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
|
||||
|
||||
------------------------------
|
||||
-- Digit conversion support --
|
||||
------------------------------
|
||||
|
||||
-- types & constants
|
||||
|
||||
subtype S_digit_chars is character range '0' to '9';
|
||||
subtype S_digits is integer range 0 to 9 ;
|
||||
|
||||
type T_digit_chars_map is array(S_digit_chars) of S_digits;
|
||||
|
||||
constant C_DIGIT_CHARS_MAP: T_digit_chars_map
|
||||
:= (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
|
||||
|
||||
type T_digits_map is array(S_digits) of S_digit_chars;
|
||||
|
||||
constant C_DIGITS_MAP: T_digits_map
|
||||
:= ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
|
||||
|
||||
|
||||
--------------------------------
|
||||
-- Decimal conversion support --
|
||||
--------------------------------
|
||||
|
||||
-- unsigned to decimal
|
||||
|
||||
function U_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end U_To_d;
|
||||
|
||||
-- signed to decimal
|
||||
|
||||
function S_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
case Argument(Argument'left) is
|
||||
when '1' => Result := - 2**(Argument'left-1);
|
||||
when '0' => Result := 0;
|
||||
when others => return (integer'low);
|
||||
end case;
|
||||
for i in Argument'left-1 downto 1 loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(integer'low);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end S_To_d;
|
||||
|
||||
-- string to decimal
|
||||
|
||||
function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
|
||||
constant Sign: character := Arg(1);
|
||||
constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
|
||||
variable Char: character;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
Result := 0;
|
||||
for i in Value'range loop
|
||||
Result := Result * 10;
|
||||
Char := Value(i);
|
||||
if (Char /= ' ') then
|
||||
Result := Result + C_DIGIT_CHARS_MAP(Char);
|
||||
end if;
|
||||
end loop;
|
||||
case Sign is when '-' => return(-Result);
|
||||
when others => return(Result);
|
||||
end case;
|
||||
end I_To_d;
|
||||
|
||||
-- boolean (0,1) to decimal
|
||||
|
||||
function B_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "1" => return(1);
|
||||
when "0" => return(0);
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end B_To_d;
|
||||
|
||||
-- boolean (T,F) to decimal
|
||||
|
||||
function L_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "T" => return(1);
|
||||
when others => return(0);
|
||||
end case;
|
||||
end L_To_d;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Hex conversion support --
|
||||
----------------------------
|
||||
|
||||
-- Constants & types
|
||||
|
||||
constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
|
||||
|
||||
-- Function to return Hex index of a nibble
|
||||
|
||||
function U_To_h_Index(Arg: string(4 downto 1)) return integer is
|
||||
variable Index: integer := 0;
|
||||
begin
|
||||
for i in Arg'range loop
|
||||
case Arg(i) is when '1' => Index := 2**(i-1) + Index;
|
||||
when '0' => null;
|
||||
when others => return (17);
|
||||
end case;
|
||||
end loop;
|
||||
return (Index+1);
|
||||
end U_To_h_Index;
|
||||
|
||||
-- Hex conversion
|
||||
|
||||
function U_To_h (Arg: string) return string is
|
||||
variable Result: string((Arg'length-1)/4 +1 downto 1);
|
||||
variable ExtArg: string(Result'length*4 downto 1) := (others => '0');
|
||||
begin
|
||||
ExtArg(Arg'length downto 1) := Arg;
|
||||
for i in Result'range loop
|
||||
Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));
|
||||
end loop;
|
||||
return (FIO_h_PRE & Result & FIO_h_POST);
|
||||
end U_To_h;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Bit conversion support --
|
||||
----------------------------
|
||||
|
||||
function L_To_b (Arg: string(1 to 1)) return string is
|
||||
variable Result: string(1 to 1);
|
||||
begin
|
||||
case Arg is when "T" => Result := "1";
|
||||
when others => Result := "0";
|
||||
end case;
|
||||
return(FIO_b_PRE & Result & FIO_b_POST);
|
||||
end L_To_b;
|
||||
|
||||
|
||||
function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
|
||||
variable IntValue: integer := I_To_d(Arg);
|
||||
variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable BitWidth: integer range 0 to FIO_b_WIDTH;
|
||||
variable MsPos: integer range 1 to BitValue'length;
|
||||
variable BitValueExtended: string(1 to 2*FIO_b_WIDTH);
|
||||
|
||||
begin
|
||||
|
||||
if (IntValue < 0) then
|
||||
Sign := '-';
|
||||
IntValue := -IntValue;
|
||||
end if;
|
||||
|
||||
for i in BitValue'reverse_range loop
|
||||
BitValue(i) := C_DIGITS_MAP(IntValue mod 2);
|
||||
IntValue := IntValue / 2;
|
||||
exit when (IntValue = 0);
|
||||
end loop;
|
||||
|
||||
BitValueExtended := BitValue & Blanks;
|
||||
|
||||
if (Width = 0) or (Width > FIO_b_WIDTH+1) then
|
||||
BitWidth := FIO_b_WIDTH;
|
||||
else
|
||||
BitWidth := Width-1;
|
||||
end if;
|
||||
|
||||
if (Justified = RIGHT) then
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) &
|
||||
FIO_bv_POST);
|
||||
else
|
||||
for i in BitValue'range loop
|
||||
if BitValue(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) &
|
||||
FIO_bv_POST);
|
||||
end if;
|
||||
|
||||
end I_To_b;
|
||||
|
||||
|
||||
-----------------------------------
|
||||
-- Reasonable conversion support --
|
||||
-----------------------------------
|
||||
|
||||
function I_To_r (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
|
||||
constant Sign: character := Arg(1);
|
||||
constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable IntWidth: integer range 0 to FIO_d_WIDTH;
|
||||
variable MsPos: integer range 1 to Value'length;
|
||||
variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks;
|
||||
begin
|
||||
if (Width = 0) or (Width > FIO_d_WIDTH+1) then
|
||||
IntWidth := FIO_d_WIDTH;
|
||||
else
|
||||
IntWidth := Width-1;
|
||||
end if;
|
||||
if (Justified = RIGHT) then
|
||||
return (Sign & Value(Value'length-IntWidth+1 to Value'length));
|
||||
else
|
||||
for i in Value'range loop
|
||||
if Value(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
|
||||
end if;
|
||||
end I_To_r;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Reasonable output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function ReasonableOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return U_To_h(Value);
|
||||
when "I:" =>
|
||||
return I_To_r(Value, Justified, Width);
|
||||
when "B:" | "L:" | "C:" =>
|
||||
return Value;
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end ReasonableOutput;
|
||||
|
||||
|
||||
------------------------------------
|
||||
-- Bit output conversion function --
|
||||
------------------------------------
|
||||
|
||||
function BitOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return (FIO_bv_PRE & Value & FIO_bv_POST);
|
||||
when "B:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);
|
||||
when "I:" =>
|
||||
return I_To_b(Value, Justified, Width);
|
||||
when "L:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return L_To_b(Value(1 to 1));
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end BitOutput;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Decimal output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function DecimalOutput (Arg: string) return integer is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:"| "V:" =>
|
||||
return U_To_d(Value);
|
||||
when "S:" =>
|
||||
return S_To_d(Value);
|
||||
when "I:" =>
|
||||
return I_To_d(Value);
|
||||
when "B:" =>
|
||||
return B_To_d(Value);
|
||||
when "L:" =>
|
||||
return L_To_d(Value);
|
||||
when others =>
|
||||
return integer'low;
|
||||
end case;
|
||||
|
||||
end DecimalOutput;
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Atomic print functions --
|
||||
----------------------------
|
||||
|
||||
-- test for end of format string
|
||||
|
||||
function FIO_EOS (Format: in string;
|
||||
Pointer: in integer)
|
||||
return boolean is
|
||||
begin
|
||||
return (Pointer > Format'length);
|
||||
end FIO_EOS;
|
||||
|
||||
|
||||
-- Atomic value print function
|
||||
|
||||
procedure FIO_PrintValue (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Last: in boolean := FALSE) is
|
||||
variable Char: character;
|
||||
begin
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '\' =>
|
||||
Pointer := Pointer + 1;
|
||||
exit when (FIO_EOS(Format, Pointer));
|
||||
Char := Format(Pointer);
|
||||
case Char is when 'n' => writeline(F, L);
|
||||
when others => write(L, Char);
|
||||
end case;
|
||||
when '%' =>
|
||||
if Last then
|
||||
FIO_Warning_Fsbla(F, L, Format, Pointer);
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
write(L, char);
|
||||
end case;
|
||||
Pointer := Pointer + 1;
|
||||
end loop;
|
||||
end FIO_PrintValue;
|
||||
|
||||
|
||||
---- Atomic argument print function
|
||||
|
||||
procedure FIO_PrintArg (F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Arg: in string) is
|
||||
variable Char: character;
|
||||
variable Justified: side;
|
||||
variable Width: integer;
|
||||
begin
|
||||
|
||||
FIO_PrintValue(F, L, Format, Pointer);
|
||||
|
||||
Justified := RIGHT;
|
||||
Width := 0;
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '-' =>
|
||||
Justified := LEFT;
|
||||
Pointer := Pointer + 1;
|
||||
when '0' to '9' =>
|
||||
Width := Width*10 + C_DIGIT_CHARS_MAP(Char);
|
||||
Pointer := Pointer + 1;
|
||||
when 'r' =>
|
||||
write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'b' =>
|
||||
write(L, BitOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'd' =>
|
||||
write(L, DecimalOutput(Arg), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'q' | 's' =>
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
FIO_Warning_Ufs(F, L, Format, Pointer, Char);
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
end case;
|
||||
end loop;
|
||||
end FIO_PrintArg;
|
||||
|
||||
|
||||
-----------------------------------------------------
|
||||
-- The format string iteration expansion procedure --
|
||||
-----------------------------------------------------
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive) is
|
||||
|
||||
variable Pointer: positive := StartPointer;
|
||||
variable TokenStart: positive;
|
||||
variable IterStringStart: positive;
|
||||
variable IterStringEnd: positive;
|
||||
variable IterCount: natural;
|
||||
variable OpenBrackets: natural;
|
||||
variable L: line;
|
||||
|
||||
begin
|
||||
|
||||
FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- look for format specifier
|
||||
when '%' =>
|
||||
|
||||
-- initialize iteration token search
|
||||
TokenStart := Pointer;
|
||||
IterCount := 0;
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- start iteration token search
|
||||
TOKEN_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- read iteration counter
|
||||
when '0' to '9' =>
|
||||
IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer));
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- expect open bracket
|
||||
when '{' =>
|
||||
|
||||
-- initialize iteration string read
|
||||
OpenBrackets := 1;
|
||||
IterStringStart := Pointer + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- quit prematurely when iteration count is 0
|
||||
next FORMAT_SEARCH when (IterCount = 0);
|
||||
|
||||
-- start iteration string read
|
||||
ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
-- keep track of open brackets
|
||||
when '{' =>
|
||||
OpenBrackets := OpenBrackets + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- when closing bracket is found, process iteration string
|
||||
when '}' =>
|
||||
OpenBrackets := OpenBrackets - 1;
|
||||
if (OpenBrackets = 0) then
|
||||
IterStringEnd := Pointer-1;
|
||||
if (TokenStart /= 1) then
|
||||
write(L, Format(1 to TokenStart-1));
|
||||
end if;
|
||||
for i in 1 to IterCount loop
|
||||
write(L, Format(IterStringStart to IterStringEnd));
|
||||
end loop;
|
||||
if (IterStringEnd /= Format'length) then
|
||||
write(L, Format(IterStringEnd+2 to Format'length));
|
||||
end if;
|
||||
-- call expansion procedure recursively on expanded format
|
||||
FIO_FormatExpand(FMT, L.all, TokenStart);
|
||||
deallocate(L);
|
||||
return;
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
-- read iteration string
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop ITER_STRING_READ;
|
||||
|
||||
-- stop iteration token search when no opening bracket found
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
next FORMAT_SEARCH;
|
||||
|
||||
end case;
|
||||
|
||||
end loop TOKEN_READ;
|
||||
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
|
||||
-- read other characters
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop FORMAT_SEARCH;
|
||||
|
||||
write(FMT, Format);
|
||||
deallocate(L);
|
||||
|
||||
end FIO_FormatExpand;
|
||||
|
||||
|
||||
|
||||
--------------------------
|
||||
-- The fprint procedure --
|
||||
--------------------------
|
||||
|
||||
procedure fprint
|
||||
(F: out text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
) is
|
||||
|
||||
variable Pointer: integer;
|
||||
variable FMT: line;
|
||||
|
||||
begin
|
||||
|
||||
Pointer := 1;
|
||||
|
||||
FIO_FormatExpand (FMT, Format, Format'low);
|
||||
|
||||
if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
|
||||
if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
|
||||
if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
|
||||
if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
|
||||
if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
|
||||
if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
|
||||
if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
|
||||
if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
|
||||
if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
|
||||
if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
|
||||
if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
|
||||
if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
|
||||
if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
|
||||
if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
|
||||
if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
|
||||
if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
|
||||
if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
|
||||
if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
|
||||
if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
|
||||
if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
|
||||
if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
|
||||
if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
|
||||
if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
|
||||
if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
|
||||
if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
|
||||
if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
|
||||
if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
|
||||
if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
|
||||
if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
|
||||
if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
|
||||
if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
|
||||
if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
|
||||
FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
|
||||
|
||||
deallocate(FMT);
|
||||
|
||||
end fprint;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Formatted output conversion functions --
|
||||
-------------------------------------------
|
||||
|
||||
function fo (Arg: unsigned) return string is
|
||||
constant Argument: unsigned(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("U:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: signed) return string is
|
||||
constant Argument: signed(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("S:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_logic_vector) return string is
|
||||
constant Argument: std_logic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic_vector) return string is
|
||||
constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit_vector) return string is
|
||||
constant Argument: bit_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_BIT_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: integer) return string is
|
||||
variable Argument: integer := Arg;
|
||||
variable Result: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
begin
|
||||
if (Argument < 0) and (Argument /= integer'low) then
|
||||
Sign := '-';
|
||||
Argument := -Argument;
|
||||
end if;
|
||||
for i in Result'reverse_range loop
|
||||
Result(i) := C_DIGITS_MAP(Argument mod 10);
|
||||
Argument := Argument / 10;
|
||||
exit when (Argument = 0);
|
||||
end loop;
|
||||
return ("I:" & Sign & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic) return string is
|
||||
begin
|
||||
return ("B:" & C_STD_LOGIC_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit) return string is
|
||||
begin
|
||||
return ("B:" & C_BIT_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: boolean) return string is
|
||||
begin
|
||||
if (ARG = TRUE) then
|
||||
return ("L:T");
|
||||
else
|
||||
return ("L:F");
|
||||
end if;
|
||||
end fo;
|
||||
|
||||
function fo (Arg: character) return string is
|
||||
begin
|
||||
return ("C:" & Arg);
|
||||
end fo;
|
||||
|
||||
-- auxilary function fgets(Arg: string)
|
||||
-- gives index until first NUL
|
||||
-- reads string from 1 to Arg'length
|
||||
function fgets (Arg: string) return integer is
|
||||
variable index: integer := Arg'length;
|
||||
begin
|
||||
for i in 1 to Arg'length loop
|
||||
if Arg(i) = NUL then
|
||||
index := i - 1;
|
||||
exit;
|
||||
else
|
||||
null;
|
||||
end if;
|
||||
end loop;
|
||||
return index;
|
||||
end fgets;
|
||||
|
||||
function fo (Arg: string) return string is
|
||||
begin
|
||||
return Arg(1 to fgets(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: time) return string is
|
||||
begin
|
||||
return fo (integer (Arg / 1 ns));
|
||||
end fo;
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,108 +0,0 @@
|
||||
---- $Id: PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
package PCK_FIO is
|
||||
|
||||
|
||||
-- prefix string for hex output
|
||||
-- VHDL style: "X"""
|
||||
-- Verilog style: "h'"
|
||||
-- C style: "0x"
|
||||
constant FIO_h_PRE: string := "0x";
|
||||
|
||||
-- postfix string for hex output
|
||||
-- VHDL style: """"
|
||||
constant FIO_h_POST: string := "";
|
||||
|
||||
-- prefix string for bit vector output
|
||||
-- VHDL style: "B"""
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_bv_PRE: string := "";
|
||||
|
||||
-- postfix string for bit vector output
|
||||
-- VHDL style: """"
|
||||
constant FIO_bv_POST: string := "";
|
||||
|
||||
-- prefix string for bit output
|
||||
-- VHDL style: "'"
|
||||
-- Verilog style: "b'"
|
||||
constant FIO_b_PRE: string := "";
|
||||
|
||||
-- postfix string for bit output
|
||||
-- VHDL style: "'"
|
||||
constant FIO_b_POST: string := "";
|
||||
|
||||
-- digit width for the string representation of integers
|
||||
constant FIO_d_WIDTH: integer := 10;
|
||||
|
||||
-- bit width for the string representation of integers
|
||||
constant FIO_b_WIDTH: integer := 32;
|
||||
|
||||
-- definition of the NIL string (default value for fprint arguments)
|
||||
-- fprint stops consuming arguments at the first NIL argument
|
||||
constant FIO_NIL: string := "\";
|
||||
|
||||
procedure fprint
|
||||
(file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
);
|
||||
|
||||
function fo (Arg: unsigned) return string;
|
||||
function fo (Arg: signed) return string;
|
||||
function fo (Arg: std_logic_vector) return string;
|
||||
function fo (Arg: std_ulogic_vector) return string;
|
||||
function fo (Arg: bit_vector) return string;
|
||||
function fo (Arg: integer) return string;
|
||||
function fo (Arg: std_ulogic) return string;
|
||||
function fo (Arg: bit) return string;
|
||||
function fo (Arg: boolean) return string;
|
||||
function fo (Arg: character) return string;
|
||||
function fo (Arg: string) return string;
|
||||
function fo (Arg: time) return string;
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive);
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
|
||||
|
||||
@@ -1,814 +0,0 @@
|
||||
---- $Id: PCK_FIO_1993_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
package body PCK_FIO is
|
||||
|
||||
--------------------------
|
||||
-- FIO Warnings support --
|
||||
--------------------------
|
||||
|
||||
procedure FIO_Warning_Fsbla (file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
|
||||
"Format specifier beyond last argument\n");
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format);
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n");
|
||||
end FIO_Warning_Fsbla;
|
||||
|
||||
procedure FIO_Warning_Ufs (file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: in positive;
|
||||
Char: in character) is
|
||||
begin
|
||||
fprint (F, L, "\n** Warning: FIO_PrintArg: " &
|
||||
"Unexpected format specifier '%r'\n",
|
||||
fo(Char));
|
||||
fprint (F, L, "** in format string: ""%s""\n", Format) ;
|
||||
fprint (F, L, "** ");
|
||||
for i in 1 to Pointer-1 loop
|
||||
fprint (F, L, "-");
|
||||
end loop;
|
||||
fprint (F, L, "^\n** Assuming 'q' to proceed: ");
|
||||
end FIO_Warning_Ufs;
|
||||
|
||||
|
||||
----------------------------------
|
||||
-- bit conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_bit_map is array(bit) of character;
|
||||
|
||||
constant C_BIT_MAP: T_bit_map
|
||||
:= ('0', '1');
|
||||
|
||||
----------------------------------
|
||||
-- std_logic conversion support --
|
||||
----------------------------------
|
||||
|
||||
type T_std_logic_map is array(std_ulogic) of character;
|
||||
|
||||
constant C_STD_LOGIC_MAP: T_std_logic_map
|
||||
:= ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
|
||||
|
||||
------------------------------
|
||||
-- Digit conversion support --
|
||||
------------------------------
|
||||
|
||||
-- types & constants
|
||||
|
||||
subtype S_digit_chars is character range '0' to '9';
|
||||
subtype S_digits is integer range 0 to 9 ;
|
||||
|
||||
type T_digit_chars_map is array(S_digit_chars) of S_digits;
|
||||
|
||||
constant C_DIGIT_CHARS_MAP: T_digit_chars_map
|
||||
:= (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
|
||||
|
||||
type T_digits_map is array(S_digits) of S_digit_chars;
|
||||
|
||||
constant C_DIGITS_MAP: T_digits_map
|
||||
:= ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
|
||||
|
||||
|
||||
--------------------------------
|
||||
-- Decimal conversion support --
|
||||
--------------------------------
|
||||
|
||||
-- unsigned to decimal
|
||||
|
||||
function U_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end U_To_d;
|
||||
|
||||
-- signed to decimal
|
||||
|
||||
function S_To_d (Arg: string) return integer is
|
||||
constant Argument: string(Arg'length downto 1) := Arg;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
case Argument(Argument'left) is
|
||||
when '1' => Result := - 2**(Argument'left-1);
|
||||
when '0' => Result := 0;
|
||||
when others => return (integer'low);
|
||||
end case;
|
||||
for i in Argument'left-1 downto 1 loop
|
||||
case Argument(i) is when '1' => Result := 2**(i-1) + Result;
|
||||
when '0' => null;
|
||||
when others => return(integer'low);
|
||||
end case;
|
||||
end loop;
|
||||
return (Result);
|
||||
end S_To_d;
|
||||
|
||||
-- string to decimal
|
||||
|
||||
function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
|
||||
constant Sign: character := Arg(1);
|
||||
constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
|
||||
variable Char: character;
|
||||
variable Result: integer := 0;
|
||||
begin
|
||||
Result := 0;
|
||||
for i in Value'range loop
|
||||
Result := Result * 10;
|
||||
Char := Value(i);
|
||||
if (Char /= ' ') then
|
||||
Result := Result + C_DIGIT_CHARS_MAP(Char);
|
||||
end if;
|
||||
end loop;
|
||||
case Sign is when '-' => return(-Result);
|
||||
when others => return(Result);
|
||||
end case;
|
||||
end I_To_d;
|
||||
|
||||
-- boolean (0,1) to decimal
|
||||
|
||||
function B_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "1" => return(1);
|
||||
when "0" => return(0);
|
||||
when others => return(-1);
|
||||
end case;
|
||||
end B_To_d;
|
||||
|
||||
-- boolean (T,F) to decimal
|
||||
|
||||
function L_To_d (Arg: string(1 to 1)) return integer is
|
||||
begin
|
||||
case Arg is when "T" => return(1);
|
||||
when others => return(0);
|
||||
end case;
|
||||
end L_To_d;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Hex conversion support --
|
||||
----------------------------
|
||||
|
||||
-- Constants & types
|
||||
|
||||
constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
|
||||
|
||||
-- Function to return Hex index of a nibble
|
||||
|
||||
function U_To_h_Index(Arg: string(4 downto 1)) return integer is
|
||||
variable Index: integer := 0;
|
||||
begin
|
||||
for i in Arg'range loop
|
||||
case Arg(i) is when '1' => Index := 2**(i-1) + Index;
|
||||
when '0' => null;
|
||||
when others => return (17);
|
||||
end case;
|
||||
end loop;
|
||||
return (Index+1);
|
||||
end U_To_h_Index;
|
||||
|
||||
-- Hex conversion
|
||||
|
||||
function U_To_h (Arg: string) return string is
|
||||
variable Result: string((Arg'length-1)/4 +1 downto 1);
|
||||
variable ExtArg: string(Result'length*4 downto 1) := (others => '0');
|
||||
begin
|
||||
ExtArg(Arg'length downto 1) := Arg;
|
||||
for i in Result'range loop
|
||||
Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));
|
||||
end loop;
|
||||
return (FIO_h_PRE & Result & FIO_h_POST);
|
||||
end U_To_h;
|
||||
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Bit conversion support --
|
||||
----------------------------
|
||||
|
||||
function L_To_b (Arg: string(1 to 1)) return string is
|
||||
variable Result: string(1 to 1);
|
||||
begin
|
||||
case Arg is when "T" => Result := "1";
|
||||
when others => Result := "0";
|
||||
end case;
|
||||
return(FIO_b_PRE & Result & FIO_b_POST);
|
||||
end L_To_b;
|
||||
|
||||
|
||||
function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
|
||||
variable IntValue: integer := I_To_d(Arg);
|
||||
variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
|
||||
variable BitWidth: integer range 0 to FIO_b_WIDTH;
|
||||
variable MsPos: integer range 1 to BitValue'length;
|
||||
variable BitValueExtended: string(1 to 2*FIO_b_WIDTH);
|
||||
|
||||
begin
|
||||
|
||||
if (IntValue < 0) then
|
||||
Sign := '-';
|
||||
IntValue := -IntValue;
|
||||
end if;
|
||||
|
||||
for i in BitValue'reverse_range loop
|
||||
BitValue(i) := C_DIGITS_MAP(IntValue mod 2);
|
||||
IntValue := IntValue / 2;
|
||||
exit when (IntValue = 0);
|
||||
end loop;
|
||||
|
||||
BitValueExtended := BitValue & Blanks;
|
||||
|
||||
if (Width = 0) or (Width > FIO_b_WIDTH+1) then
|
||||
BitWidth := FIO_b_WIDTH;
|
||||
else
|
||||
BitWidth := Width-1;
|
||||
end if;
|
||||
|
||||
if (Justified = RIGHT) then
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) &
|
||||
FIO_bv_POST);
|
||||
else
|
||||
for i in BitValue'range loop
|
||||
if BitValue(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (FIO_bv_PRE &
|
||||
Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) &
|
||||
FIO_bv_POST);
|
||||
end if;
|
||||
|
||||
end I_To_b;
|
||||
|
||||
|
||||
-----------------------------------
|
||||
-- Reasonable conversion support --
|
||||
-----------------------------------
|
||||
|
||||
function I_To_r (Arg: string(1 to FIO_d_WIDTH+1);
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
|
||||
constant Sign: character := Arg(1);
|
||||
constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable IntWidth: integer range 0 to FIO_d_WIDTH;
|
||||
variable MsPos: integer range 1 to Value'length;
|
||||
variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks;
|
||||
begin
|
||||
if (Width = 0) or (Width > FIO_d_WIDTH+1) then
|
||||
IntWidth := FIO_d_WIDTH;
|
||||
else
|
||||
IntWidth := Width-1;
|
||||
end if;
|
||||
if (Justified = RIGHT) then
|
||||
return (Sign & Value(Value'length-IntWidth+1 to Value'length));
|
||||
else
|
||||
for i in Value'range loop
|
||||
if Value(i) /= ' ' then
|
||||
MSPos := i;
|
||||
exit;
|
||||
end if;
|
||||
end loop;
|
||||
return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
|
||||
end if;
|
||||
end I_To_r;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Reasonable output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function ReasonableOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return U_To_h(Value);
|
||||
when "I:" =>
|
||||
return I_To_r(Value, Justified, Width);
|
||||
when "B:" | "L:" | "C:" =>
|
||||
return Value;
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end ReasonableOutput;
|
||||
|
||||
|
||||
------------------------------------
|
||||
-- Bit output conversion function --
|
||||
------------------------------------
|
||||
|
||||
function BitOutput (Arg: string;
|
||||
Justified: side;
|
||||
Width: integer) return string is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:" | "S:" | "V:" =>
|
||||
return (FIO_bv_PRE & Value & FIO_bv_POST);
|
||||
when "B:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);
|
||||
when "I:" =>
|
||||
return I_To_b(Value, Justified, Width);
|
||||
when "L:" =>
|
||||
-- Value(1 to 1) instead of Value for LeapFrog
|
||||
return L_To_b(Value(1 to 1));
|
||||
when others =>
|
||||
return Argument;
|
||||
end case;
|
||||
|
||||
end BitOutput;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Decimal output conversion function --
|
||||
-------------------------------------------
|
||||
|
||||
function DecimalOutput (Arg: string) return integer is
|
||||
constant Argument: string(1 to Arg'length) := Arg;
|
||||
constant TypeSpec: string (1 to 2) := Argument(1 to 2);
|
||||
constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
|
||||
begin
|
||||
case TypeSpec is
|
||||
when "U:"| "V:" =>
|
||||
return U_To_d(Value);
|
||||
when "S:" =>
|
||||
return S_To_d(Value);
|
||||
when "I:" =>
|
||||
return I_To_d(Value);
|
||||
when "B:" =>
|
||||
return B_To_d(Value);
|
||||
when "L:" =>
|
||||
return L_To_d(Value);
|
||||
when others =>
|
||||
return integer'low;
|
||||
end case;
|
||||
|
||||
end DecimalOutput;
|
||||
|
||||
|
||||
----------------------------
|
||||
-- Atomic print functions --
|
||||
----------------------------
|
||||
|
||||
-- test for end of format string
|
||||
|
||||
function FIO_EOS (Format: in string;
|
||||
Pointer: in integer)
|
||||
return boolean is
|
||||
begin
|
||||
return (Pointer > Format'length);
|
||||
end FIO_EOS;
|
||||
|
||||
|
||||
-- Atomic value print function
|
||||
|
||||
procedure FIO_PrintValue (file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Last: in boolean := FALSE) is
|
||||
variable Char: character;
|
||||
begin
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '\' =>
|
||||
Pointer := Pointer + 1;
|
||||
exit when (FIO_EOS(Format, Pointer));
|
||||
Char := Format(Pointer);
|
||||
case Char is when 'n' => writeline(F, L);
|
||||
when others => write(L, Char);
|
||||
end case;
|
||||
when '%' =>
|
||||
if Last then
|
||||
FIO_Warning_Fsbla(F, L, Format, Pointer);
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
write(L, char);
|
||||
end case;
|
||||
Pointer := Pointer + 1;
|
||||
end loop;
|
||||
end FIO_PrintValue;
|
||||
|
||||
|
||||
---- Atomic argument print function
|
||||
|
||||
procedure FIO_PrintArg (file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
Pointer: inout integer;
|
||||
Arg: in string) is
|
||||
variable Char: character;
|
||||
variable Justified: side;
|
||||
variable Width: integer;
|
||||
|
||||
begin
|
||||
|
||||
FIO_PrintValue(F, L, Format, Pointer);
|
||||
|
||||
Justified := RIGHT;
|
||||
Width := 0;
|
||||
while (not FIO_EOS(Format, Pointer)) loop
|
||||
Char := Format(Pointer);
|
||||
case Char is
|
||||
when '-' =>
|
||||
Justified := LEFT;
|
||||
Pointer := Pointer + 1;
|
||||
when '0' to '9' =>
|
||||
Width := Width*10 + C_DIGIT_CHARS_MAP(Char);
|
||||
Pointer := Pointer + 1;
|
||||
when 'r' =>
|
||||
write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'b' =>
|
||||
write(L, BitOutput(Arg, Justified, Width), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'd' =>
|
||||
write(L, DecimalOutput(Arg), Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when 'q' | 's' =>
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
when others =>
|
||||
FIO_Warning_Ufs(F, L, Format, Pointer, Char);
|
||||
write(L, Arg, Justified, Width);
|
||||
Pointer := Pointer + 1;
|
||||
exit;
|
||||
end case;
|
||||
end loop;
|
||||
end FIO_PrintArg;
|
||||
|
||||
|
||||
-----------------------------------------------------
|
||||
-- The format string iteration expansion procedure --
|
||||
-----------------------------------------------------
|
||||
|
||||
procedure FIO_FormatExpand (FMT: inout line;
|
||||
Format: in string;
|
||||
StartPointer: in positive) is
|
||||
|
||||
variable Pointer: positive := StartPointer;
|
||||
variable TokenStart: positive;
|
||||
variable IterStringStart: positive;
|
||||
variable IterStringEnd: positive;
|
||||
variable IterCount: natural;
|
||||
variable OpenBrackets: natural;
|
||||
variable L: line;
|
||||
|
||||
begin
|
||||
|
||||
FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- look for format specifier
|
||||
when '%' =>
|
||||
|
||||
-- initialize iteration token search
|
||||
TokenStart := Pointer;
|
||||
IterCount := 0;
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- start iteration token search
|
||||
TOKEN_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
|
||||
-- read iteration counter
|
||||
when '0' to '9' =>
|
||||
IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer));
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
-- expect open bracket
|
||||
when '{' =>
|
||||
|
||||
-- initialize iteration string read
|
||||
OpenBrackets := 1;
|
||||
IterStringStart := Pointer + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- quit prematurely when iteration count is 0
|
||||
next FORMAT_SEARCH when (IterCount = 0);
|
||||
|
||||
-- start iteration string read
|
||||
ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop
|
||||
|
||||
case Format(Pointer) is
|
||||
-- keep track of open brackets
|
||||
when '{' =>
|
||||
OpenBrackets := OpenBrackets + 1;
|
||||
Pointer := Pointer + 1;
|
||||
-- when closing bracket is found, process iteration string
|
||||
when '}' =>
|
||||
OpenBrackets := OpenBrackets - 1;
|
||||
if (OpenBrackets = 0) then
|
||||
IterStringEnd := Pointer-1;
|
||||
if (TokenStart /= 1) then
|
||||
write(L, Format(1 to TokenStart-1));
|
||||
end if;
|
||||
for i in 1 to IterCount loop
|
||||
write(L, Format(IterStringStart to IterStringEnd));
|
||||
end loop;
|
||||
if (IterStringEnd /= Format'length) then
|
||||
write(L, Format(IterStringEnd+2 to Format'length));
|
||||
end if;
|
||||
-- call expansion procedure recursively on expanded format
|
||||
FIO_FormatExpand(FMT, L.all, TokenStart);
|
||||
deallocate(L);
|
||||
return;
|
||||
end if;
|
||||
Pointer := Pointer + 1;
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
-- read iteration string
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop ITER_STRING_READ;
|
||||
|
||||
-- stop iteration token search when no opening bracket found
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
next FORMAT_SEARCH;
|
||||
|
||||
end case;
|
||||
|
||||
end loop TOKEN_READ;
|
||||
|
||||
-- skip escaped characters
|
||||
when '\' =>
|
||||
Pointer := Pointer + 2;
|
||||
|
||||
-- read other characters
|
||||
when others =>
|
||||
Pointer := Pointer + 1;
|
||||
|
||||
end case;
|
||||
|
||||
end loop FORMAT_SEARCH;
|
||||
|
||||
write(FMT, Format);
|
||||
deallocate(L);
|
||||
|
||||
end FIO_FormatExpand;
|
||||
|
||||
|
||||
|
||||
--------------------------
|
||||
-- The fprint procedure --
|
||||
--------------------------
|
||||
|
||||
procedure fprint
|
||||
(file F: text;
|
||||
L: inout line;
|
||||
Format: in string;
|
||||
A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
|
||||
A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
|
||||
A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
|
||||
A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
|
||||
) is
|
||||
|
||||
variable Pointer: integer;
|
||||
variable FMT: line;
|
||||
|
||||
begin
|
||||
|
||||
Pointer := 1;
|
||||
|
||||
FIO_FormatExpand (FMT, Format, Format'low);
|
||||
|
||||
if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
|
||||
if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
|
||||
if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
|
||||
if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
|
||||
if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
|
||||
if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
|
||||
if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
|
||||
if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
|
||||
if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
|
||||
if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
|
||||
if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
|
||||
if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
|
||||
if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
|
||||
if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
|
||||
if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
|
||||
if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
|
||||
if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
|
||||
if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
|
||||
if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
|
||||
if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
|
||||
if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
|
||||
if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
|
||||
if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
|
||||
if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
|
||||
if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
|
||||
if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
|
||||
if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
|
||||
if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
|
||||
if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
|
||||
if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
|
||||
if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
|
||||
if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
end if; end if; end if; end if; end if; end if; end if; end if;
|
||||
|
||||
FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
|
||||
|
||||
deallocate(FMT);
|
||||
|
||||
end fprint;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- Formatted output conversion functions --
|
||||
-------------------------------------------
|
||||
|
||||
function fo (Arg: unsigned) return string is
|
||||
constant Argument: unsigned(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("U:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: signed) return string is
|
||||
constant Argument: signed(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("S:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_logic_vector) return string is
|
||||
constant Argument: std_logic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic_vector) return string is
|
||||
constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_STD_LOGIC_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit_vector) return string is
|
||||
constant Argument: bit_vector(1 to Arg'length) := Arg;
|
||||
variable Result: string(1 to Arg'length);
|
||||
begin
|
||||
for i in Argument'range loop
|
||||
Result(i) := C_BIT_MAP(Argument(i));
|
||||
end loop;
|
||||
return ("V:" & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: integer) return string is
|
||||
variable Argument: integer := Arg;
|
||||
variable Result: string(1 to FIO_d_WIDTH) := (others => ' ');
|
||||
variable Sign: character := ' ';
|
||||
begin
|
||||
if (Argument < 0) and (Argument /= integer'low) then
|
||||
Sign := '-';
|
||||
Argument := -Argument;
|
||||
end if;
|
||||
for i in Result'reverse_range loop
|
||||
Result(i) := C_DIGITS_MAP(Argument mod 10);
|
||||
Argument := Argument / 10;
|
||||
exit when (Argument = 0);
|
||||
end loop;
|
||||
return ("I:" & Sign & Result);
|
||||
end fo;
|
||||
|
||||
function fo (Arg: std_ulogic) return string is
|
||||
begin
|
||||
return ("B:" & C_STD_LOGIC_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: bit) return string is
|
||||
begin
|
||||
return ("B:" & C_BIT_MAP(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: boolean) return string is
|
||||
begin
|
||||
if (ARG = TRUE) then
|
||||
return ("L:T");
|
||||
else
|
||||
return ("L:F");
|
||||
end if;
|
||||
end fo;
|
||||
|
||||
function fo (Arg: character) return string is
|
||||
begin
|
||||
return ("C:" & Arg);
|
||||
end fo;
|
||||
|
||||
-- auxilary function fgets(Arg :string)
|
||||
-- returns index of first NUL in Arg or if no NUL is present just Arg'length
|
||||
-- goes through Arg from 1 to Arg'length
|
||||
function fgets (Arg: string) return integer is
|
||||
variable index: integer := Arg'length;
|
||||
begin
|
||||
for i in 1 to Arg'length loop
|
||||
if Arg(i) = NUL then
|
||||
index := i - 1;
|
||||
exit;
|
||||
else
|
||||
null;
|
||||
end if;
|
||||
end loop;
|
||||
return index;
|
||||
end fgets;
|
||||
|
||||
-- returns the Arg string until the first NUL was encountered
|
||||
-- if fo is used on a string with NUL in it it will stop reading the rest
|
||||
-- of the string, even if a larger field width has been supplied. fo will
|
||||
-- then just pad the remaining characters with blanco's
|
||||
function fo (Arg: string) return string is
|
||||
begin
|
||||
return Arg(1 to fgets(Arg));
|
||||
end fo;
|
||||
|
||||
function fo (Arg: time) return string is
|
||||
begin
|
||||
return fo (integer (Arg / 1 ns));
|
||||
end fo;
|
||||
|
||||
end PCK_FIO;
|
||||
|
||||
@@ -1,88 +0,0 @@
|
||||
---- $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
Version 2002.07
|
||||
===============
|
||||
|
||||
Contents
|
||||
========
|
||||
|
||||
This distribution contains the following files:
|
||||
|
||||
PCK_FIO_1987.vhd: VHDL-87 source of the header of the PCK_FIO package
|
||||
PCK_FIO_1987_BODY.vhd: VHDL-87 source of the body of the PCK_FIO package
|
||||
PCK_FIO_1993.vhd: VHDL-93 source of the header of the PCK_FIO package
|
||||
PCK_FIO_1993_BODY.vhd: VHDL-93 source of the body of the PCK_FIO package
|
||||
TB_PCK_FIO_1987.vhd: VHDL-87 source of the testbench for package PCK_FIO
|
||||
TB_PCK_FIO_1993.vhd: VHDL-93 source of the testbench for package PCK_FIO
|
||||
PCK_FIO.out.gold: Certified test bench output
|
||||
PCK_FIO.html: Manual for PCK_FIO in html format
|
||||
README: This file
|
||||
|
||||
|
||||
Installation
|
||||
============
|
||||
|
||||
VHDL-1987
|
||||
---------
|
||||
To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
|
||||
analyze the VHDL file PCK_FIO_1987.vhd and PCK_FIO_1987_BODY.vhd into this library.
|
||||
|
||||
To install the test bench, analyze TB_PCK_FIO_1987.vhd into the same library.
|
||||
|
||||
VHDL-1993
|
||||
---------
|
||||
To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
|
||||
analyze the VHDL file PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd into this library.
|
||||
|
||||
To install the test bench, analyze TB_PCK_FIO_1993.vhd into the same library.
|
||||
|
||||
Numeric packages
|
||||
----------------
|
||||
If you want to use IEEE.std_logic_arith instead of IEEE.numeric_std, you need
|
||||
to edit the source code of the package, both header and body, and the test bench
|
||||
and replace the package use clause. PCK_FIO works with either of these packages.
|
||||
|
||||
Documentation
|
||||
-------------
|
||||
To install the documentation, put the file point PCK_FIO.html in a path of
|
||||
your choosing, point your web browser to it, and bookmark it.
|
||||
|
||||
|
||||
Installation check
|
||||
==================
|
||||
|
||||
After installing the test bench, you should run it. The corresponding VHDL
|
||||
design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB).
|
||||
|
||||
Simulating the test bench should create a file called PCK_FIO.out. This file
|
||||
should be identical to PCK_FIO.out.gold. Any difference indicates a portability
|
||||
issue or a simulator non-compliance or bug.
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,531 +0,0 @@
|
||||
---- $Id: TB_PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library EASICS_PACKAGES;
|
||||
use EASICS_PACKAGES.PCK_FIO.all;
|
||||
|
||||
entity TBE_PCK_FIO is
|
||||
|
||||
end TBE_PCK_FIO;
|
||||
|
||||
architecture TB of TBE_PCK_FIO is
|
||||
|
||||
begin
|
||||
|
||||
USAGE: process
|
||||
|
||||
file RESULT: text is out "PCK_FIO.out";
|
||||
variable L: line;
|
||||
variable Pointer: integer;
|
||||
variable BoolTrue: boolean := TRUE;
|
||||
variable BoolFalse: boolean := FALSE;
|
||||
variable IntPos: integer := 5678;
|
||||
variable BigIntPos: integer := 12345678;
|
||||
variable IntNeg: integer := -8765;
|
||||
variable BigIntNeg: integer := -87654321;
|
||||
variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
|
||||
variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
|
||||
variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
|
||||
variable SigPos: signed(6 downto 0) := signed'("0010010");
|
||||
variable SigNeg: signed(6 downto 0) := signed'("1010010");
|
||||
variable BitX: std_logic := 'X';
|
||||
variable Bit1: std_logic := '1';
|
||||
variable Bit0: std_logic := '0';
|
||||
|
||||
variable parameter_1: integer := 1234;
|
||||
variable parameter_2: integer := 2345;
|
||||
variable parameter_3: integer := 4567;
|
||||
|
||||
constant TempString: string :="ABC" & NUL & "DEF";
|
||||
begin
|
||||
|
||||
fprint(RESULT, L,
|
||||
"PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
|
||||
"-----------------------------------------\n\n" &
|
||||
"This is the result of running the PCK_FIO testbench.\n" &
|
||||
"This file should be compared with PCK_FIO.out.gold, which is\n" &
|
||||
"the reference output. Any difference indicates a portability\n" &
|
||||
"issue or a simulator non-compliance or bug.\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n--------------------\n" &
|
||||
"-- Basic features --\n" &
|
||||
"--------------------\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"-- First some auxiliary declarations\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"> file RESULT: text is out ""PCK_FIO.out"";\n" &
|
||||
"> variable L: line;\n" &
|
||||
"> variable BoolTrue: boolean := TRUE;\n" &
|
||||
"> variable BoolFalse: boolean := FALSE;\n" &
|
||||
"> variable IntPos: integer := 5678;\n" &
|
||||
"> variable BigIntPos: integer := 12345678;\n" &
|
||||
"> variable IntNeg: integer := -8765;\n" &
|
||||
"> variable BigIntNeg: integer := -87654321;\n" &
|
||||
"> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
|
||||
"> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
|
||||
"> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
|
||||
"> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" &
|
||||
"> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" &
|
||||
"> variable BitX: std_logic := 'X';\n" &
|
||||
"> variable Bit1: std_logic := '1';\n" &
|
||||
"> variable Bit0: std_logic := '0';\n" &
|
||||
"> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n-- fprint call with no arguments\n" &
|
||||
"> fprint(RESULT, L, ""No arguments.\\n"");\n"
|
||||
);
|
||||
fprint(RESULT, L, "No arguments.\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Special characters need to be escaped\n" &
|
||||
"> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Special characters: \% \\ "" \n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Various format specifiers interprete the same object differently\n" &
|
||||
"> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" &
|
||||
"> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
|
||||
fo(Uns), fo(Uns), fo(Uns), fo(Uns)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Format string can be shortened by using the iteration specifier\n" &
|
||||
"> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" &
|
||||
"> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
|
||||
fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
|
||||
);
|
||||
fprint(RESULT, L,
|
||||
"\n-------------------------------\n"&
|
||||
"--Testing string manipulation--\n"&
|
||||
"-------------------------------\n");
|
||||
fprint(RESULT, L, "--testing done using the string TempString : " & """ABC"""
|
||||
& " & NUL & ""DEF""\n");
|
||||
-- temp_string: string:="ABC"&NUL&"DEF"
|
||||
-- test for detecting NUL in string
|
||||
fprint(RESULT, L, "\n--test for NUL ending in strings\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n");
|
||||
fprint(RESULT, L, fo(TempString));
|
||||
|
||||
-- direct inclusion of string in fprint should give whole string
|
||||
fprint(RESULT, L, "\n--same without fo,so without NUL testing\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n");
|
||||
fprint(RESULT, L, TempString & "\n");
|
||||
|
||||
-- influence of given width
|
||||
|
||||
fprint(RESULT, L, "\n--if there are less characters in the given string then"
|
||||
& " in the width fo will\n"&
|
||||
"-- pad the remaining with blanco's according to the given justification\n");
|
||||
fprint(RESULT, L, "\n--with specified width, justified right,using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%5s", fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width, justified left, using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%-5s",fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width without fo\n");
|
||||
fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n");
|
||||
fprint(RESULT, L, "%9s", TempString);
|
||||
fprint(RESULT, L, "\n\n-- if the width is smaller then the number" &
|
||||
" of characters in the string fprint\n" &
|
||||
"-- will output the string with the minimum of characters needed\n");
|
||||
fprint(RESULT, L, "\n--with specified width,using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%2s",fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width without fo\n");
|
||||
fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n");
|
||||
fprint(RESULT, L, "%4s", TempString);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n------------------------------------\n" &
|
||||
"-- Support for bit-oriented types --\n" &
|
||||
"------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Reasonable format\n" &
|
||||
"> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Reasonable format: %9{%r }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Decimal format\n" &
|
||||
"> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Decimal format: %9{%d }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Bit format\n" &
|
||||
"> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Bit format: %9{%b }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Alignment\n-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Bitvectors with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
|
||||
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-------------------------------\n" &
|
||||
"-- Support for integer types --\n" &
|
||||
"-------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Integers with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
|
||||
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------\n" &
|
||||
"-- Support for time --\n" &
|
||||
"----------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
|
||||
"-- into an integer value (of nanoseconds)\n"
|
||||
);
|
||||
fprint (RESULT, L, "> wait for 648 ns\n");
|
||||
fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
|
||||
|
||||
wait for 648 ns;
|
||||
|
||||
fprint (RESULT, L, "The time is now %d ns\n", fo(now));
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Erroneous calls and error messages --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
|
||||
"> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L, "-- Unsupported format specifier\n" &
|
||||
"> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
|
||||
"fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Things you wouldn't expect to work --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Nested iteration\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
|
||||
fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
|
||||
|
||||
wait;
|
||||
|
||||
end process USAGE;
|
||||
|
||||
end TB;
|
||||
|
||||
|
||||
@@ -1,536 +0,0 @@
|
||||
---- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
|
||||
----
|
||||
---- PCK_FIO: a VHDL package for C-style formatted file output
|
||||
---- Copyright (C) 1995, 2001 Easics NV
|
||||
----
|
||||
---- This library is free software; you can redistribute it and/or
|
||||
---- modify it under the terms of the GNU Lesser General Public
|
||||
---- License as published by the Free Software Foundation; either
|
||||
---- version 2.1 of the License, or (at your option) any later version.
|
||||
----
|
||||
---- This library is distributed in the hope that it will be useful,
|
||||
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
---- Lesser General Public License for more details.
|
||||
----
|
||||
---- You should have received a copy of the GNU Lesser General Public
|
||||
---- License along with this library; if not, write to the Free Software
|
||||
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
----
|
||||
---- For suggestions, bug reports, enhancement requests, and info about
|
||||
---- our design services, you can contact us at the following address:
|
||||
---- http://www.easics.com
|
||||
---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
|
||||
---- tel.: +32 16 395 600 fax : +32 16 395 619
|
||||
---- e-mail: jand@easics.be (Jan Decaluwe)
|
||||
----
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- signed/unsigned definition: use either std_logic_arith or numeric_std
|
||||
-- use IEEE.std_logic_arith.all; -- the Synopsys one
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
use STD.TEXTIO.all;
|
||||
|
||||
library EASICS_PACKAGES;
|
||||
use EASICS_PACKAGES.PCK_FIO.all;
|
||||
|
||||
entity TBE_PCK_FIO is
|
||||
|
||||
end TBE_PCK_FIO;
|
||||
|
||||
architecture TB of TBE_PCK_FIO is
|
||||
|
||||
begin
|
||||
|
||||
USAGE: process
|
||||
|
||||
file RESULT: text open write_mode is "PCK_FIO.out";
|
||||
variable L: line;
|
||||
variable Pointer: integer;
|
||||
variable BoolTrue: boolean := TRUE;
|
||||
variable BoolFalse: boolean := FALSE;
|
||||
variable IntPos: integer := 5678;
|
||||
variable BigIntPos: integer := 12345678;
|
||||
variable IntNeg: integer := -8765;
|
||||
variable BigIntNeg: integer := -87654321;
|
||||
variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
|
||||
variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
|
||||
variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
|
||||
variable SigPos: signed(6 downto 0) := signed'("0010010");
|
||||
variable SigNeg: signed(6 downto 0) := signed'("1010010");
|
||||
variable BitX: std_logic := 'X';
|
||||
variable Bit1: std_logic := '1';
|
||||
variable Bit0: std_logic := '0';
|
||||
|
||||
variable parameter_1: integer := 1234;
|
||||
variable parameter_2: integer := 2345;
|
||||
variable parameter_3: integer := 4567;
|
||||
|
||||
constant TempString: string :="ABC" & NUL & "DEF";
|
||||
begin
|
||||
|
||||
fprint(RESULT, L,
|
||||
"PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
|
||||
"-----------------------------------------\n\n" &
|
||||
"This is the result of running the PCK_FIO testbench.\n" &
|
||||
"This file should be compared with PCK_FIO.out.gold, which is\n" &
|
||||
"the reference output. Any difference indicates a portability\n" &
|
||||
"issue or a simulator non-compliance or bug.\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n--------------------\n" &
|
||||
"-- Basic features --\n" &
|
||||
"--------------------\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"-- First some auxiliary declarations\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"> file RESULT: text is out ""PCK_FIO.out"";\n" &
|
||||
"> variable L: line;\n" &
|
||||
"> variable BoolTrue: boolean := TRUE;\n" &
|
||||
"> variable BoolFalse: boolean := FALSE;\n" &
|
||||
"> variable IntPos: integer := 5678;\n" &
|
||||
"> variable BigIntPos: integer := 12345678;\n" &
|
||||
"> variable IntNeg: integer := -8765;\n" &
|
||||
"> variable BigIntNeg: integer := -87654321;\n" &
|
||||
"> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
|
||||
"> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
|
||||
"> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
|
||||
"> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" &
|
||||
"> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" &
|
||||
"> variable BitX: std_logic := 'X';\n" &
|
||||
"> variable Bit1: std_logic := '1';\n" &
|
||||
"> variable Bit0: std_logic := '0';\n" &
|
||||
"> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n-- fprint call with no arguments\n" &
|
||||
"> fprint(RESULT, L, ""No arguments.\\n"");\n"
|
||||
);
|
||||
fprint(RESULT, L, "No arguments.\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Special characters need to be escaped\n" &
|
||||
"> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Special characters: \% \\ "" \n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Various format specifiers interprete the same object differently\n" &
|
||||
"> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" &
|
||||
"> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
|
||||
fo(Uns), fo(Uns), fo(Uns), fo(Uns)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-- Format string can be shortened by using the iteration specifier\n" &
|
||||
"> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" &
|
||||
"> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
|
||||
fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
|
||||
);
|
||||
fprint(RESULT, L,
|
||||
"\n-------------------------------\n"&
|
||||
"--Testing string manipulation--\n"&
|
||||
"-------------------------------\n");
|
||||
fprint(RESULT, L, "--testing done using the string TempString : " & """ABC"""
|
||||
& " & NUL & ""DEF""\n");
|
||||
-- TempString: string:="ABC" & NUL & "DEF"
|
||||
-- test for detecting NUL in string
|
||||
fprint(RESULT, L ,"\n--test for NUL ending in strings\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n");
|
||||
fprint(RESULT, L, fo(TempString));
|
||||
|
||||
-- direct inclusion of string in fprint should give whole string
|
||||
fprint(RESULT, L, "\n--same without fo,so without NUL testing\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n");
|
||||
fprint(RESULT, L, TempString & "\n");
|
||||
|
||||
-- influence of given width
|
||||
|
||||
fprint(RESULT, L, "\n--if there are less characters in the given string then in the width fo will\n"&
|
||||
"-- pad the remaining with blanco's according to the given justification\n");
|
||||
fprint(RESULT, L, "\n--with specified width, justified right,using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%5s", fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width, justified left, using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%-5s", fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width without fo\n");
|
||||
fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n");
|
||||
fprint(RESULT, L, "%9s", TempString);
|
||||
fprint(RESULT, L, "\n\n-- if the width is smaller then the number of characters in the string fprint\n"&
|
||||
"-- will output the string with the minimum of characters needed\n");
|
||||
fprint(RESULT, L, "\n--with specified width,using fo\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n");
|
||||
fprint(RESULT, L, "%2s", fo(TempString));
|
||||
fprint(RESULT, L, "\n--with specified width without fo\n");
|
||||
fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n");
|
||||
fprint(RESULT, L, "%4s", TempString);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n------------------------------------\n" &
|
||||
"-- Support for bit-oriented types --\n" &
|
||||
"------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Reasonable format\n" &
|
||||
"> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Reasonable format: %9{%r }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Decimal format\n" &
|
||||
"> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Decimal format: %9{%d }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "\n-- Bit format\n" &
|
||||
"> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
|
||||
"> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Bit format: %9{%b }\n",
|
||||
fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
|
||||
fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Alignment\n-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Bitvectors with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
|
||||
fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n-------------------------------\n" &
|
||||
"-- Support for integer types --\n" &
|
||||
"-------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n\n" &
|
||||
"-- Template of the call: (<fs> stands for the format specifier)\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "\n" &
|
||||
"> fprint(RESULT, L, ""Integers with <fs>: \%4{<fs>|}\\n"",\n" &
|
||||
"> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
|
||||
|
||||
"> );\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n" &
|
||||
"-- Results of the call with various format specifiers\n\n"
|
||||
);
|
||||
|
||||
|
||||
fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
|
||||
fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
|
||||
);
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------\n" &
|
||||
"-- Support for time --\n" &
|
||||
"----------------------\n"
|
||||
);
|
||||
|
||||
fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
|
||||
"-- into an integer value (of nanoseconds)\n"
|
||||
);
|
||||
fprint (RESULT, L, "> wait for 648 ns\n");
|
||||
fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
|
||||
|
||||
wait for 648 ns;
|
||||
|
||||
fprint (RESULT, L, "The time is now %d ns\n", fo(now));
|
||||
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Erroneous calls and error messages --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
|
||||
"> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L, "-- Unsupported format specifier\n" &
|
||||
"> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
|
||||
"fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
|
||||
|
||||
fprint(RESULT, L, "\n");
|
||||
|
||||
fprint(RESULT, L,
|
||||
"\n----------------------------------------\n" &
|
||||
"-- Things you wouldn't expect to work --\n" &
|
||||
"----------------------------------------\n"
|
||||
);
|
||||
|
||||
fprint(RESULT, L, "\n-- Nested iteration\n");
|
||||
fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
|
||||
fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
|
||||
|
||||
wait;
|
||||
|
||||
end process USAGE;
|
||||
|
||||
end TB;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,34 +0,0 @@
|
||||
### msMakefile generated by vma on Thu Oct 4 17:33:56 CEST 2001
|
||||
|
||||
ANALYZER = vcom -quiet -nologo
|
||||
ANALYZER_C = vcom -quiet -nologo
|
||||
all : \
|
||||
bin/tbe_pck_fio/tb.dat \
|
||||
bin/tbe_pck_fio/_primary.dat
|
||||
|
||||
# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB)
|
||||
# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO
|
||||
|
||||
bin/tbe_pck_fio/tb.dat \
|
||||
bin/tbe_pck_fio/_primary.dat : \
|
||||
bin/pck_fio/body.dat \
|
||||
bin/pck_fio/_primary.dat \
|
||||
TB_PCK_FIO_1987.vhd
|
||||
${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1987.vhd
|
||||
|
||||
|
||||
# Prerequisites for package body EASICS_PACKAGES.PCK_FIO(<body>)
|
||||
|
||||
bin/pck_fio/body.dat : \
|
||||
bin/pck_fio/_primary.dat \
|
||||
PCK_FIO_1987_BODY.vhd
|
||||
${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1987_BODY.vhd
|
||||
|
||||
|
||||
# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO
|
||||
|
||||
bin/pck_fio/_primary.dat : \
|
||||
PCK_FIO_1987.vhd
|
||||
${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1987.vhd
|
||||
|
||||
|
||||
@@ -1,34 +0,0 @@
|
||||
### msMakefile generated by vma on Thu Oct 4 17:32:23 CEST 2001
|
||||
|
||||
ANALYZER = vcom -quiet -nologo -93
|
||||
ANALYZER_C = vcom -quiet -nologo -93
|
||||
all : \
|
||||
bin/tbe_pck_fio/tb.dat \
|
||||
bin/tbe_pck_fio/_primary.dat
|
||||
|
||||
# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB)
|
||||
# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO
|
||||
|
||||
bin/tbe_pck_fio/tb.dat \
|
||||
bin/tbe_pck_fio/_primary.dat : \
|
||||
bin/pck_fio/body.dat \
|
||||
bin/pck_fio/_primary.dat \
|
||||
TB_PCK_FIO_1993.vhd
|
||||
${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1993.vhd
|
||||
|
||||
|
||||
# Prerequisites for package body EASICS_PACKAGES.PCK_FIO(<body>)
|
||||
|
||||
bin/pck_fio/body.dat : \
|
||||
bin/pck_fio/_primary.dat \
|
||||
PCK_FIO_1993_BODY.vhd
|
||||
${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1993_BODY.vhd
|
||||
|
||||
|
||||
# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO
|
||||
|
||||
bin/pck_fio/_primary.dat : \
|
||||
PCK_FIO_1993.vhd
|
||||
${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1993.vhd
|
||||
|
||||
|
||||
@@ -1,13 +0,0 @@
|
||||
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_config.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\dpram.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd"
|
||||
@@ -1,6 +0,0 @@
|
||||
vlib simprim
|
||||
|
||||
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
|
||||
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
|
||||
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
|
||||
vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd
|
||||
@@ -1,6 +0,0 @@
|
||||
vlib unisim
|
||||
|
||||
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
|
||||
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
|
||||
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
|
||||
vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd
|
||||
@@ -1,27 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../src/sdram_config.vhd"
|
||||
vcom -explicit -93 "../src/sdram_types.vhd"
|
||||
vcom -explicit -93 "../src/reset_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_cmd.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
|
||||
vcom -explicit -93 "../src/mt46v16m16.vhd"
|
||||
vcom -explicit -93 "../src/tb_sdr_ctrl.vhd"
|
||||
|
||||
#restart -force
|
||||
vsim -t 1ps -lib work tb_sdr_ctrl
|
||||
do {tb_sdr_ctrl.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 800us
|
||||
@@ -1,93 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_full
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_re
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_we
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rst
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
|
||||
add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
|
||||
add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
|
||||
add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {14963876 ps} 0}
|
||||
configure wave -namecolwidth 184
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {14733925 ps} {15711632 ps}
|
||||
@@ -1,27 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../src/sdram_config.vhd"
|
||||
vcom -explicit -93 "../src/sdram_types.vhd"
|
||||
vcom -explicit -93 "../src/reset_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_cmd.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
|
||||
vcom -explicit -93 "../src/mt46v16m16.vhd"
|
||||
vcom -explicit -93 "../src/tb_sdr_ctrl_fifo.vhd"
|
||||
|
||||
#restart -force
|
||||
vsim -t 1ps -lib work tb_sdr_ctrl_fifo
|
||||
do {tb_sdr_ctrl_fifo.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 20us
|
||||
@@ -1,68 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/clk_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/rst_out
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cas_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cs_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_ras_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_we_n
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_addr
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_busy
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/u_cmd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_cmd_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_r
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_data_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_w
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_wr
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_rd
|
||||
add wave -noupdate -divider {Read FIFO}
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_re
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/read_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/was_write
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr_next
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw_next
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_full
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_empty
|
||||
add wave -noupdate -divider {Write FIFO}
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_w
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/re
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_empty
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_full
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr_next
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw
|
||||
add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw_next
|
||||
add wave -noupdate -divider {Command FIFO}
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_w
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/re
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_empty
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_full
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {13893123 ps} 0}
|
||||
configure wave -namecolwidth 172
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {13879998 ps} {13928553 ps}
|
||||
@@ -1,27 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../src/sdram_config.vhd"
|
||||
vcom -explicit -93 "../src/sdram_types.vhd"
|
||||
vcom -explicit -93 "../src/reset_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_cmd.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
|
||||
vcom -explicit -93 "../src/mt46v16m16.vhd"
|
||||
vcom -explicit -93 "../src/tb_sdr_ctrl_lin_r_rand_w.vhd"
|
||||
|
||||
#restart -force
|
||||
vsim -t 1ps -lib work tb_sdr_ctrl
|
||||
do {tb_sdr_ctrl_lin_r_rand_w.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 1200us
|
||||
@@ -1,87 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rst
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
|
||||
add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
|
||||
add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
|
||||
add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {21813900 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {21725359 ps} {22204052 ps}
|
||||
@@ -1,27 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../src/sdram_config.vhd"
|
||||
vcom -explicit -93 "../src/sdram_types.vhd"
|
||||
vcom -explicit -93 "../src/reset_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_cmd.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
|
||||
vcom -explicit -93 "../src/mt46v16m16.vhd"
|
||||
vcom -explicit -93 "../src/tb_sdr_ctrl_lin_w_rand_r.vhd"
|
||||
|
||||
#restart -force
|
||||
vsim -t 1ps -lib work tb_sdr_ctrl
|
||||
do {tb_sdr_ctrl_lin_w_rand_r.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 1200us
|
||||
@@ -1,87 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rst
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
|
||||
add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
|
||||
add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
|
||||
add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {21813900 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {21725359 ps} {22204052 ps}
|
||||
@@ -1,27 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../src/sdram_config.vhd"
|
||||
vcom -explicit -93 "../src/sdram_types.vhd"
|
||||
vcom -explicit -93 "../src/reset_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_cmd.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
|
||||
vcom -explicit -93 "../src/mt46v16m16.vhd"
|
||||
vcom -explicit -93 "../src/tb_sdr_ctrl_rand_addr.vhd"
|
||||
|
||||
#restart -force
|
||||
vsim -t 1ps -lib work tb_sdr_ctrl
|
||||
do {tb_sdr_ctrl_rand_rw.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 1000us
|
||||
@@ -1,82 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rst
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
|
||||
add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
|
||||
add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
|
||||
add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {60573747 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {60552548 ps} {60600861 ps}
|
||||
@@ -1,27 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../src/sdram_config.vhd"
|
||||
vcom -explicit -93 "../src/sdram_types.vhd"
|
||||
vcom -explicit -93 "../src/reset_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_cmd.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
|
||||
vcom -explicit -93 "../src/mt46v16m16.vhd"
|
||||
vcom -explicit -93 "../src/tb_sdr_ctrl_rand_rw.vhd"
|
||||
|
||||
#restart -force
|
||||
vsim -t 1ps -lib work tb_sdr_ctrl
|
||||
do {tb_sdr_ctrl_rand_rw.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 10000us
|
||||
@@ -1,84 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rst
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
|
||||
add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
|
||||
add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
|
||||
add wave -noupdate -divider {Main controller}
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
|
||||
add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
|
||||
add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
|
||||
add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {16004147 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {15914249 ps} {16324366 ps}
|
||||
@@ -1,28 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
|
||||
vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../src/sdram_config.vhd"
|
||||
vcom -explicit -93 "../src/sdram_types.vhd"
|
||||
vcom -explicit -93 "../src/reset_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_cmd.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl.vhd"
|
||||
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
|
||||
vcom -explicit -93 "../src/sdram_ctrl_frontend.vhd"
|
||||
vcom -explicit -93 "../src/mt46v16m16.vhd"
|
||||
vcom -explicit -93 "../src/tb_sdram_ctrl_frontend.vhd"
|
||||
|
||||
#restart -force
|
||||
vsim -t 1ps -lib work tb_sdram_ctrl_frontend
|
||||
do {tb_sdram_ctrl_frontend.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 40us
|
||||
@@ -1,45 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/addr
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/busy
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/en
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/r_wn
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/din
|
||||
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/be
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/dout_vld
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout_reg
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/clk_out
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cs_n
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_we_n
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_ras_n
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cas_n
|
||||
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_ba
|
||||
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_dm
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_data
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_busy
|
||||
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we
|
||||
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
|
||||
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/sdr_cmd_busy
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/cat_fifo_full
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/write_fifo_full
|
||||
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/read_fifo_full
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {27951315 ps} 0}
|
||||
configure wave -namecolwidth 172
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {42 us}
|
||||
@@ -1,240 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: Clock generator (Virtex-4 specific)
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee, work;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
|
||||
Library UNISIM;
|
||||
use UNISIM.vcomponents.all;
|
||||
|
||||
entity clockgen is
|
||||
generic
|
||||
(
|
||||
read_phaseshift : integer := 0;
|
||||
frequency_hz : integer := 100E6
|
||||
);
|
||||
port
|
||||
(
|
||||
-- Clocks and Reset
|
||||
rst : in std_logic; -- external async reset, low active
|
||||
clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
|
||||
clk_fb_in : in std_logic; -- feedback clock
|
||||
read_clk0_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 0°
|
||||
read_clk270_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 270°
|
||||
sys_clk0_out : out std_logic; -- System clock, dcm#0 output 0°
|
||||
sys_clk270_out : out std_logic; -- System clock, dcm#0 output 270°
|
||||
locked_out : out std_logic; -- DCM locked status
|
||||
error_out : out std_logic -- indicates DCM Errors
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
architecture tech of clockgen is
|
||||
|
||||
constant CLKIN_PER : real := real(1000E6/frequency_hz);
|
||||
|
||||
signal locked : unsigned(1 downto 0);
|
||||
signal dcm_rst : unsigned(1 downto 0);
|
||||
signal read_clk0 : std_logic;
|
||||
signal read_clk270 : std_logic;
|
||||
signal read_clk0_bufg : std_logic;
|
||||
signal read_clk270_bufg : std_logic;
|
||||
signal sys_clk0 : std_logic;
|
||||
signal sys_clk270 : std_logic;
|
||||
signal sys_clk0_bufg : std_logic;
|
||||
signal sys_clk270_bufg : std_logic;
|
||||
signal dcm1_locked, dcm2_locked : unsigned(2 downto 0);
|
||||
signal cnt_q : unsigned(4 downto 0);
|
||||
|
||||
type STATE_TYPE is (s0, s1, s2, s3, s4);
|
||||
signal state_q : STATE_TYPE;
|
||||
|
||||
begin
|
||||
|
||||
read_clk0_out <= read_clk0_bufg;
|
||||
read_clk270_out <= read_clk270_bufg;
|
||||
sys_clk0_out <= sys_clk0_bufg;
|
||||
sys_clk270_out <= sys_clk270_bufg;
|
||||
|
||||
bufg11: bufg
|
||||
port map
|
||||
(
|
||||
o => sys_clk0_bufg,
|
||||
i => sys_clk0
|
||||
);
|
||||
|
||||
bufg12: bufg
|
||||
port map (
|
||||
o => sys_clk270_bufg,
|
||||
i => sys_clk270
|
||||
);
|
||||
|
||||
bufg13: bufg
|
||||
port map
|
||||
(
|
||||
o => read_clk0_bufg,
|
||||
i => read_clk0
|
||||
);
|
||||
|
||||
bufg14: bufg
|
||||
port map (
|
||||
o => read_clk270_bufg,
|
||||
i => read_clk270
|
||||
);
|
||||
|
||||
-------------------------------------------------------------------------------------------------------
|
||||
-- Clock generation
|
||||
-------------------------------------------------------------------------------------------------------
|
||||
|
||||
inst_DCM_BASE_0 : DCM_BASE
|
||||
generic map (
|
||||
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
||||
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
||||
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
|
||||
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
|
||||
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
|
||||
CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
|
||||
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
|
||||
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
|
||||
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
|
||||
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
|
||||
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
||||
-- an integer from 0 to 15
|
||||
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
|
||||
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
|
||||
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
|
||||
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
|
||||
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
|
||||
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
||||
port map (
|
||||
CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput
|
||||
CLK180 => open, -- 180 degree DCM CLK output
|
||||
CLK270 => sys_clk270, -- 270 degree DCM CLK output
|
||||
CLK2X => open, -- 2X DCM CLK output
|
||||
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
|
||||
CLK90 => open, -- 90 degree DCM CLK output
|
||||
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
|
||||
CLKFX => open, -- DCM CLK synthesis out (M/D)
|
||||
CLKFX180 => open, -- 180 degree CLK synthesis out
|
||||
LOCKED => locked(0), -- DCM LOCK status output
|
||||
CLKFB => clk_fb_in, -- DCM clock feedback
|
||||
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
|
||||
RST => dcm_rst(0) -- DCM asynchronous reset input
|
||||
);
|
||||
|
||||
inst_DCM_BASE_1 : DCM_BASE
|
||||
generic map (
|
||||
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
||||
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
||||
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
|
||||
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
|
||||
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
|
||||
CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
|
||||
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
|
||||
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
|
||||
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
|
||||
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
||||
-- an integer from 0 to 15
|
||||
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
|
||||
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
|
||||
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
|
||||
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
|
||||
PHASE_SHIFT => read_phaseshift, -- Amount of fixed phase shift from -255 to 1023
|
||||
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
||||
port map (
|
||||
CLK0 => read_clk0, -- 0 degree DCM CLK ouptput
|
||||
CLK180 => open, -- 180 degree DCM CLK output
|
||||
CLK270 => read_clk270, -- 270 degree DCM CLK output
|
||||
CLK2X => open, -- 2X DCM CLK output
|
||||
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
|
||||
CLK90 => open, -- 90 degree DCM CLK output
|
||||
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
|
||||
CLKFX => open, -- DCM CLK synthesis out (M/D)
|
||||
CLKFX180 => open, -- 180 degree CLK synthesis out
|
||||
LOCKED => locked(1), -- DCM LOCK status output
|
||||
CLKFB => read_clk0_bufg, -- DCM clock feedback
|
||||
CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
|
||||
RST => dcm_rst(1) -- DCM asynchronous reset input
|
||||
);
|
||||
|
||||
dcm_rst(1) <= not locked(0);
|
||||
|
||||
dcm_fsm:
|
||||
process(rst, clk_in)
|
||||
begin
|
||||
if rst = '1' then
|
||||
state_q <= s0;
|
||||
dcm_rst(0) <= '0';
|
||||
cnt_q <= "11111";
|
||||
error_out <= '0';
|
||||
locked_out <= '0';
|
||||
dcm1_locked <= (others => '0');
|
||||
dcm2_locked <= (others => '0');
|
||||
elsif rising_edge(clk_in) then
|
||||
case state_q is
|
||||
when s0 =>
|
||||
state_q <= s1;
|
||||
|
||||
when s1 =>
|
||||
cnt_q <= cnt_q - 1;
|
||||
if cnt_q = 0 then
|
||||
dcm_rst(0) <= '1';
|
||||
state_q <= s2;
|
||||
end if;
|
||||
|
||||
when s2 =>
|
||||
cnt_q <= cnt_q - 1;
|
||||
if cnt_q = 0 then
|
||||
dcm_rst(0) <= '0';
|
||||
state_q <= s3;
|
||||
end if;
|
||||
|
||||
when s3 =>
|
||||
if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
|
||||
state_q <= s4;
|
||||
error_out <= '0';
|
||||
end if;
|
||||
|
||||
when s4 =>
|
||||
if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
|
||||
locked_out <= '1';
|
||||
else
|
||||
error_out <= '1';
|
||||
end if;
|
||||
end case;
|
||||
|
||||
-- synchronize 'dcm1_locked'
|
||||
dcm1_locked <= dcm1_locked(1 downto 0) & locked(0);
|
||||
dcm2_locked <= dcm2_locked(1 downto 0) & locked(1);
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture tech;
|
||||
|
||||
|
||||
@@ -1,370 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: DDR physical layer (Virtex-4 specific)
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
|
||||
Library UNISIM;
|
||||
use UNISIM.vcomponents.all;
|
||||
|
||||
entity ddr_phy is
|
||||
Port (
|
||||
sys_rst : in STD_LOGIC;
|
||||
sys_clk0 : in STD_LOGIC;
|
||||
sys_clk270 : in STD_LOGIC;
|
||||
u_tag_in : in user_tag_t;
|
||||
u_tag_rd : out user_tag_t;
|
||||
u_tag_wr : out user_tag_t;
|
||||
read_clk : in STD_LOGIC;
|
||||
phy_ctrl : in phy_ctrl_t;
|
||||
part_ctrl : in part_ctrl_t;
|
||||
sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
sdr_dm : in unsigned(SDR_DM_WIDTH-1 downto 0);
|
||||
sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
sdr_data_vld : out STD_LOGIC;
|
||||
sdr_data_req_w : out STD_LOGIC;
|
||||
sdr_data_req_r : out STD_LOGIC;
|
||||
part_clk_p : out STD_LOGIC;
|
||||
part_clk_n : out STD_LOGIC;
|
||||
part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
|
||||
part_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
|
||||
part_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0);
|
||||
part_ba : out unsigned(DDR_BANK_WIDTH-1 downto 0);
|
||||
part_addr : out unsigned(DDR_ADDR_WIDTH-1 downto 0);
|
||||
part_cs_n : out STD_LOGIC;
|
||||
part_we_n : out STD_LOGIC;
|
||||
part_cas_n : out STD_LOGIC;
|
||||
part_ras_n : out STD_LOGIC;
|
||||
part_cke : out STD_LOGIC
|
||||
);
|
||||
end ddr_phy;
|
||||
|
||||
architecture tech of ddr_phy is
|
||||
|
||||
signal dqs_drive : std_logic;
|
||||
signal drive : std_logic;
|
||||
signal dqs : unsigned(DDR_DQS_WIDTH-1 downto 0);
|
||||
signal dqs_zen : unsigned(DDR_DQS_WIDTH-1 downto 0);
|
||||
signal dqs_rst : std_logic;
|
||||
signal ddr_data_w : unsigned(DDR_DATA_WIDTH-1 downto 0);
|
||||
signal data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
signal data_reg_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
signal drive270 : unsigned(DDR_DATA_WIDTH-1 downto 0);
|
||||
signal part_ctrl_reg : part_ctrl_t;
|
||||
signal we_reg : std_logic;
|
||||
signal read_en : std_logic;
|
||||
|
||||
type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
|
||||
signal u_tag_pipe : u_tag_array_t;
|
||||
|
||||
begin
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
utag_pipe:
|
||||
process(sys_rst, sys_clk0)
|
||||
begin
|
||||
if rising_edge(sys_clk0) then
|
||||
for i in u_tag_pipe'length-1 downto 1 loop
|
||||
u_tag_pipe(i) <= u_tag_pipe(i-1);
|
||||
end loop;
|
||||
if phy_ctrl.utag_we = '1' then
|
||||
u_tag_pipe(0) <= u_tag_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
WE_REGISTER:
|
||||
process(sys_rst, sys_clk0)
|
||||
begin
|
||||
if sys_rst = '1' then
|
||||
we_reg <= '0';
|
||||
elsif rising_edge(sys_clk0) then
|
||||
we_reg <= phy_ctrl.we;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DATA_DRIVE_GEN:
|
||||
process(sys_clk0)
|
||||
begin
|
||||
if falling_edge(sys_clk0) then
|
||||
dqs_rst <= not we_reg;
|
||||
drive <= we_reg;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DQS_DRIVE_GEN:
|
||||
process(sys_clk0)
|
||||
variable p : unsigned(1 downto 0);
|
||||
begin
|
||||
if rising_edge(sys_clk0) then
|
||||
if phy_ctrl.drive_en = '1' then
|
||||
p := (others => '1');
|
||||
else
|
||||
p := p(p'left-1 downto 0) & '0';
|
||||
end if;
|
||||
end if;
|
||||
dqs_drive <= p(p'left);
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
-- SDRAM Clock
|
||||
ODDR_clk_p : ODDR
|
||||
generic map
|
||||
(
|
||||
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
INIT => '0', -- Initial value for Q port ('1' or '0')
|
||||
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
|
||||
)
|
||||
port map (
|
||||
Q => part_clk_p, -- 1-bit DDR output
|
||||
C => sys_clk0, -- 1-bit clock input
|
||||
CE => '1', -- 1-bit clock enable input
|
||||
D1 => '1', -- 1-bit data input (positive edge)
|
||||
D2 => '0', -- 1-bit data input (negative edge)
|
||||
R => '0', -- 1-bit reset input
|
||||
S => '0' -- 1-bit set input
|
||||
);
|
||||
|
||||
ODDR_clk_n : ODDR
|
||||
generic map
|
||||
(
|
||||
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
INIT => '0', -- Initial value for Q port ('1' or '0')
|
||||
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
|
||||
)
|
||||
port map (
|
||||
Q => part_clk_n, -- 1-bit DDR output
|
||||
C => sys_clk0, -- 1-bit clock input
|
||||
CE => '1', -- 1-bit clock enable input
|
||||
D1 => '0', -- 1-bit data input (positive edge)
|
||||
D2 => '1', -- 1-bit data input (negative edge)
|
||||
R => '0', -- 1-bit reset input
|
||||
S => '0' -- 1-bit set input
|
||||
);
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
-- Data OUT DDR-FFs
|
||||
gen_ddr_data_out:
|
||||
for n in 0 to DDR_DATA_WIDTH-1 generate
|
||||
begin
|
||||
ODDR_data : ODDR
|
||||
generic map
|
||||
(
|
||||
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
INIT => '0', -- Initial value for Q port ('1' or '0')
|
||||
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
|
||||
)
|
||||
port map (
|
||||
Q => ddr_data_w(n), -- 1-bit DDR output
|
||||
C => sys_clk270, -- 1-bit clock input
|
||||
CE => '1', -- 1-bit clock enable input
|
||||
D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge)
|
||||
D2 => sdr_data_w(n), -- 1-bit data input (negative edge)
|
||||
R => '0', -- 1-bit reset input
|
||||
S => '0' -- 1-bit set input
|
||||
);
|
||||
end generate gen_ddr_data_out;
|
||||
|
||||
-- Sample tristate on clock90
|
||||
process (sys_clk270)
|
||||
begin
|
||||
if rising_edge(sys_clk270) then
|
||||
for n in 0 to DDR_DATA_WIDTH-1 loop
|
||||
drive270(n) <= drive;
|
||||
end loop;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Output mux
|
||||
out_mux_data:
|
||||
for n in 0 to DDR_DATA_WIDTH-1 generate
|
||||
part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z';
|
||||
end generate;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
-- Data-mask OUT DDR-FFs
|
||||
gen_ddr_dm_out:
|
||||
for n in 0 to DDR_DM_WIDTH-1 generate
|
||||
begin
|
||||
ODDR_dm : ODDR
|
||||
generic map
|
||||
(
|
||||
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
INIT => '0', -- Initial value for Q port ('1' or '0')
|
||||
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
|
||||
)
|
||||
port map (
|
||||
Q => part_dm(n), -- 1-bit DDR output
|
||||
C => sys_clk270, -- 1-bit clock input
|
||||
CE => '1', -- 1-bit clock enable input
|
||||
D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge)
|
||||
D2 => sdr_dm(n), -- 1-bit data input (negative edge)
|
||||
R => '0', -- 1-bit reset input
|
||||
S => '0' -- 1-bit set input
|
||||
);
|
||||
end generate gen_ddr_dm_out;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
-- DQS OUT DDR-FFs
|
||||
gen_dqs_out:
|
||||
for n in 0 to DDR_DQS_WIDTH-1 generate
|
||||
begin
|
||||
ODDR_dqs : ODDR
|
||||
generic map
|
||||
(
|
||||
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
INIT => '0', -- Initial value for Q port ('1' or '0')
|
||||
SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
|
||||
)
|
||||
port map (
|
||||
Q => dqs(n), -- 1-bit DDR output
|
||||
C => sys_clk0, -- 1-bit clock input
|
||||
CE => '1', -- 1-bit clock enable input
|
||||
D2 => '0', -- 1-bit data input (positive edge)
|
||||
D1 => '1', -- 1-bit data input (negative edge)
|
||||
R => dqs_rst, -- 1-bit reset input
|
||||
S => '0' -- 1-bit set input
|
||||
);
|
||||
end generate gen_dqs_out;
|
||||
|
||||
-- Tristate-Control fuer dqs
|
||||
process (sys_clk0) is
|
||||
variable zctrl : boolean;
|
||||
begin
|
||||
if rising_edge(sys_clk0) then
|
||||
if dqs_drive = '1' then
|
||||
zctrl := false;
|
||||
else
|
||||
zctrl := true;
|
||||
end if;
|
||||
if zctrl then
|
||||
dqs_zen <= (others => '1');
|
||||
else
|
||||
dqs_zen <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Tristate-Buffer fuer dqs
|
||||
gen_out_mux_dqs:
|
||||
for n in 0 to DDR_DQS_WIDTH-1 generate
|
||||
part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n);
|
||||
end generate gen_out_mux_dqs;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
process (sys_rst, sys_clk0) is
|
||||
begin
|
||||
if sys_rst = '1' then
|
||||
part_ctrl_reg.cmd <= COMMAND(SD_DESELECT);
|
||||
part_ctrl_reg.ba <= (others=>'0');
|
||||
part_ctrl_reg.addr <= (others=>'0');
|
||||
part_ctrl_reg.cke <= '0';
|
||||
elsif rising_edge(sys_clk0) then
|
||||
part_ctrl_reg <= part_ctrl;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (sys_clk0) is
|
||||
begin
|
||||
if falling_edge(sys_clk0) then
|
||||
part_ras_n <= part_ctrl_reg.cmd.ras_n;
|
||||
part_cas_n <= part_ctrl_reg.cmd.cas_n;
|
||||
part_we_n <= part_ctrl_reg.cmd.we_n;
|
||||
part_cs_n <= part_ctrl_reg.cmd.cs_n;
|
||||
part_ba <= part_ctrl_reg.ba;
|
||||
part_addr <= part_ctrl_reg.addr;
|
||||
part_cke <= part_ctrl_reg.cke;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- READ DATA Processing
|
||||
-----------------------------------------------------------------
|
||||
gen_ddr_data_in:
|
||||
for n in 0 to DDR_DATA_WIDTH-1 generate
|
||||
begin
|
||||
IDDR_data : IDDR
|
||||
generic map
|
||||
(
|
||||
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
|
||||
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
|
||||
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
|
||||
SRTYPE => "SYNC" -- Set/Reset type: "SYNC" or "ASYNC"
|
||||
)
|
||||
port map
|
||||
(
|
||||
Q1 => data_r(n), -- 1-bit output for positive edge of clock
|
||||
Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock
|
||||
C => read_clk, -- 1-bit clock input
|
||||
CE => read_en, -- 1-bit clock enable input
|
||||
D => part_data(n), -- 1-bit DDR data input
|
||||
R => '0', -- 1-bit reset
|
||||
S => '0' -- 1-bit set
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
data_sample_stage:
|
||||
process (sys_clk0)
|
||||
begin
|
||||
if falling_edge(sys_clk0) then
|
||||
data_reg_r <= data_r;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
misc_flags_and_data_out:
|
||||
process (sys_rst, sys_clk0)
|
||||
variable p : unsigned(3 downto 0);
|
||||
begin
|
||||
if sys_rst = '1' then
|
||||
p := (others => '0');
|
||||
read_en <= '0';
|
||||
sdr_data_vld <= '0';
|
||||
sdr_data_req_w <= '0';
|
||||
sdr_data_req_r <= '0';
|
||||
elsif rising_edge(sys_clk0) then
|
||||
sdr_data_r <= data_reg_r;
|
||||
if p(3) = '1' then
|
||||
u_tag_rd <= u_tag_pipe(4);
|
||||
end if;
|
||||
if phy_ctrl.we = '1' then
|
||||
u_tag_wr <= u_tag_pipe(0);
|
||||
end if;
|
||||
sdr_data_req_w <= phy_ctrl.we;
|
||||
sdr_data_req_r <= phy_ctrl.re;
|
||||
sdr_data_vld <= p(3);
|
||||
read_en <= p(1);
|
||||
if phy_ctrl.re = '1' then
|
||||
p := p(p'left-1 downto 0) & '1';
|
||||
else
|
||||
p := p(p'left-1 downto 0) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
end tech;
|
||||
@@ -1,111 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.fifo_ctrl_pkg.all;
|
||||
|
||||
entity fifo_sync is
|
||||
Generic (
|
||||
addr_width : natural := 4;
|
||||
data_width : natural := 8;
|
||||
almost_full_thresh : integer := 12;
|
||||
almost_empty_thresh : integer := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
re : in STD_LOGIC;
|
||||
fifo_full : out STD_LOGIC;
|
||||
fifo_empty : out STD_LOGIC;
|
||||
fifo_afull : out STD_LOGIC;
|
||||
fifo_aempty : out STD_LOGIC;
|
||||
data_w : in unsigned (data_width-1 downto 0);
|
||||
data_r : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end fifo_sync;
|
||||
|
||||
architecture Behavioral of fifo_sync is
|
||||
|
||||
signal mem_we : STD_LOGIC;
|
||||
signal ptr_w : unsigned (addr_width-1 downto 0);
|
||||
signal ptr_r : unsigned (addr_width-1 downto 0);
|
||||
signal full : STD_LOGIC;
|
||||
signal empty : STD_LOGIC;
|
||||
signal almost_full : STD_LOGIC;
|
||||
signal almost_empty : STD_LOGIC;
|
||||
|
||||
begin
|
||||
|
||||
mem_we <= we;
|
||||
fifo_full <= full;
|
||||
fifo_empty <= empty;
|
||||
fifo_afull <= almost_full;
|
||||
fifo_aempty <= almost_empty;
|
||||
|
||||
inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
almost_full_thresh => almost_full_thresh,
|
||||
almost_empty_thresh => almost_empty_thresh
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
we => we,
|
||||
re => re,
|
||||
ptr_w => ptr_w,
|
||||
ptr_r => ptr_r,
|
||||
fifo_full => full,
|
||||
fifo_empty => empty,
|
||||
fifo_afull => almost_full,
|
||||
fifo_aempty => almost_empty
|
||||
|
||||
);
|
||||
|
||||
inst_dpram_1w1r: entity work.dpram_1w1r_dist
|
||||
GENERIC MAP (
|
||||
addr_width => addr_width,
|
||||
data_width => data_width
|
||||
)
|
||||
PORT MAP(
|
||||
clka => clk,
|
||||
clkb => clk,
|
||||
en_a => '1',
|
||||
en_b => '1',
|
||||
we_a => mem_we,
|
||||
addr_a => ptr_w,
|
||||
addr_b => ptr_r,
|
||||
din_a => data_w,
|
||||
dout_b => data_r
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,111 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: Reset generator (Virtex-4 specific)
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
Library UNISIM;
|
||||
use UNISIM.vcomponents.all;
|
||||
|
||||
entity reset is
|
||||
port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
rst_out : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture tech of reset is
|
||||
|
||||
signal rst : std_logic;
|
||||
signal shift_pipe : std_logic_vector(3 downto 0);
|
||||
attribute KEEP : string;
|
||||
attribute KEEP of shift_pipe : signal is "TRUE";
|
||||
|
||||
begin
|
||||
|
||||
rst <= shift_pipe(0);
|
||||
|
||||
bufg_reset: bufg
|
||||
port map
|
||||
(
|
||||
o => rst_out,
|
||||
i => rst
|
||||
);
|
||||
|
||||
fdp0: fdp
|
||||
generic map
|
||||
(
|
||||
init => '1'
|
||||
)
|
||||
port map
|
||||
(
|
||||
d => rst_in,
|
||||
c => clk,
|
||||
pre => '0',
|
||||
q => shift_pipe(3)
|
||||
);
|
||||
|
||||
fdp1: fdp
|
||||
generic map
|
||||
(
|
||||
init => '1'
|
||||
)
|
||||
port map
|
||||
(
|
||||
|
||||
d => shift_pipe(3),
|
||||
c => clk,
|
||||
pre => '0',
|
||||
q => shift_pipe(2)
|
||||
);
|
||||
|
||||
fdp2: fdp
|
||||
generic map
|
||||
(
|
||||
init => '1'
|
||||
)
|
||||
port map
|
||||
(
|
||||
d => shift_pipe(2),
|
||||
c => clk,
|
||||
pre => '0',
|
||||
q => shift_pipe(1)
|
||||
);
|
||||
|
||||
fdp3: fdp
|
||||
generic map
|
||||
(
|
||||
init => '1'
|
||||
)
|
||||
port map
|
||||
(
|
||||
|
||||
d => shift_pipe(1),
|
||||
c => clk,
|
||||
pre => '0',
|
||||
q => shift_pipe(0)
|
||||
);
|
||||
|
||||
end tech;
|
||||
@@ -1,269 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: SDRAM command controller
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
|
||||
entity sdram_cmd is
|
||||
Generic (BL : natural := 2);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
enable : in STD_LOGIC;
|
||||
u_tag_in : in user_tag_t;
|
||||
u_tag_out : out user_tag_t;
|
||||
phy_ctrl : out phy_ctrl_t;
|
||||
cmd : in sdr_cmd_t;
|
||||
cmd_we : in STD_LOGIC;
|
||||
cmd_ack : out STD_LOGIC;
|
||||
col_addr : in col_addr_t;
|
||||
mode_word : in mode_word_t;
|
||||
sdr_cmd_ctrl : out sdr_cmd_lines_t;
|
||||
sdr_addr : out sdr_addr_t;
|
||||
sdr_ba : out sdr_ba_t
|
||||
);
|
||||
end sdram_cmd;
|
||||
|
||||
architecture behaviour of sdram_cmd is
|
||||
|
||||
signal st_sdr, st_sdr_next : sdr_state_t;
|
||||
|
||||
signal cc_preset : natural range 0 to 10;
|
||||
signal cc_load_en : std_logic;
|
||||
signal cycle_finished : std_logic;
|
||||
|
||||
signal burst_preset : natural range 0 to 3;
|
||||
signal burst_load_en : std_logic;
|
||||
signal burst_finished : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
u_tag_out <= u_tag_in;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
fsm_sdr_state:
|
||||
process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr)
|
||||
begin
|
||||
st_sdr_next <= st_sdr;
|
||||
sdr_cmd_ctrl <= COMMAND(SD_NOP);
|
||||
|
||||
cc_load_en <= '0';
|
||||
cc_preset <= TIMING(cmd);
|
||||
burst_load_en <= '0';
|
||||
cmd_ack <= '0';
|
||||
burst_preset <= BL/2-1;
|
||||
phy_ctrl.re <= '0';
|
||||
phy_ctrl.drive_en <= '0';
|
||||
phy_ctrl.we <= '0';
|
||||
phy_ctrl.utag_we <= '0';
|
||||
sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right);
|
||||
sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1);
|
||||
|
||||
case st_sdr is
|
||||
when PWR_DOWN =>
|
||||
sdr_cmd_ctrl <= COMMAND(SD_DESELECT);
|
||||
if enable = '1' then
|
||||
st_sdr_next <= IDLE;
|
||||
end if;
|
||||
|
||||
when PRECHARGE =>
|
||||
if cycle_finished = '1' then
|
||||
st_sdr_next <= IDLE;
|
||||
end if;
|
||||
|
||||
when MODE =>
|
||||
if cycle_finished = '1' then
|
||||
st_sdr_next <= IDLE;
|
||||
end if;
|
||||
|
||||
when IDLE =>
|
||||
if cmd_we = '1' then
|
||||
cmd_ack <= '1';
|
||||
cc_load_en <= '1';
|
||||
cc_preset <= TIMING(cmd);
|
||||
sdr_cmd_ctrl <= COMMAND(cmd);
|
||||
case cmd is
|
||||
when SD_PRE =>
|
||||
st_sdr_next <= PRECHARGE;
|
||||
sdr_addr(BIT_PRE_ALL) <= mode_word(BIT_PRE_ALL);
|
||||
when SD_LMR =>
|
||||
st_sdr_next <= MODE;
|
||||
when SD_ACT =>
|
||||
st_sdr_next <= ROW_ACT;
|
||||
when SD_AR =>
|
||||
st_sdr_next <= AUTO_REF;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
when ROW_ACT =>
|
||||
if cycle_finished = '1' then
|
||||
if cmd_we = '1' then
|
||||
cmd_ack <= '1';
|
||||
burst_load_en <= '1';
|
||||
cc_load_en <= '1';
|
||||
cc_preset <= TIMING(cmd);
|
||||
sdr_cmd_ctrl <= COMMAND(cmd);
|
||||
case cmd is
|
||||
when SD_PRE =>
|
||||
st_sdr_next <= PRECHARGE;
|
||||
when SD_READ =>
|
||||
phy_ctrl.utag_we <= '1';
|
||||
st_sdr_next <= READ;
|
||||
sdr_addr(col_addr_t'range) <= col_addr;
|
||||
when SD_WRITE =>
|
||||
phy_ctrl.utag_we <= '1';
|
||||
phy_ctrl.drive_en <= '1';
|
||||
st_sdr_next <= WRITE;
|
||||
sdr_addr(col_addr_t'range) <= col_addr;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when WRITE =>
|
||||
phy_ctrl.drive_en <= '1';
|
||||
phy_ctrl.we <= '1';
|
||||
if burst_finished = '1' then
|
||||
if cmd_we = '1' and cmd = SD_WRITE then
|
||||
sdr_addr(col_addr_t'range) <= col_addr;
|
||||
cmd_ack <= '1';
|
||||
burst_load_en <= '1';
|
||||
sdr_cmd_ctrl <= COMMAND(cmd);
|
||||
phy_ctrl.utag_we <= '1';
|
||||
else
|
||||
phy_ctrl.drive_en <= '0';
|
||||
cc_load_en <= '1';
|
||||
cc_preset <= TIMING(SD_WRITE)+1;
|
||||
st_sdr_next <= ROW_ACT;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when READ =>
|
||||
phy_ctrl.re <= '1';
|
||||
if burst_finished = '1' then
|
||||
if cmd_we = '1' and cmd = SD_READ then
|
||||
sdr_addr(col_addr_t'range) <= col_addr;
|
||||
cmd_ack <= '1';
|
||||
burst_load_en <= '1';
|
||||
sdr_cmd_ctrl <= COMMAND(cmd);
|
||||
phy_ctrl.utag_we <= '1';
|
||||
else
|
||||
cc_load_en <= '1';
|
||||
cc_preset <= TIMING(SD_READ);
|
||||
st_sdr_next <= ROW_ACT;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when WRITE_A => -- not implemented yet
|
||||
cmd_ack <= '1';
|
||||
st_sdr_next <= IDLE;
|
||||
|
||||
when READ_A => -- not implemented yet
|
||||
cmd_ack <= '1';
|
||||
st_sdr_next <= IDLE;
|
||||
|
||||
when BURST_STOP => -- not implemented yet
|
||||
cmd_ack <= '1';
|
||||
st_sdr_next <= IDLE;
|
||||
|
||||
when SELF_REF => -- not implemented yet
|
||||
cmd_ack <= '1';
|
||||
st_sdr_next <= IDLE;
|
||||
|
||||
when PRE_PWR_DOWN => -- not implemented yet
|
||||
cmd_ack <= '1';
|
||||
st_sdr_next <= IDLE;
|
||||
|
||||
when ACT_PWR_DOWN => -- not implemented yet
|
||||
cmd_ack <= '1';
|
||||
st_sdr_next <= IDLE;
|
||||
|
||||
when AUTO_REF =>
|
||||
if cycle_finished = '1' then
|
||||
st_sdr_next <= IDLE;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
st_sdr_next <= IDLE;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
fsm_sdr_state_next:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
st_sdr <= PWR_DOWN;
|
||||
elsif rising_edge(clk) then
|
||||
st_sdr <= st_sdr_next;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
cycle_counter:
|
||||
process (rst, clk)
|
||||
variable cycle_cnt : natural range 0 to 10;
|
||||
begin
|
||||
if rst = '1' then
|
||||
cycle_cnt := 0;
|
||||
cycle_finished <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
cycle_finished <= '0';
|
||||
if cc_load_en = '1' then
|
||||
cycle_cnt := cc_preset;
|
||||
elsif cycle_cnt /= 0 then
|
||||
cycle_cnt := cycle_cnt - 1;
|
||||
else
|
||||
cycle_finished <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
burst_counter:
|
||||
process (rst, clk)
|
||||
variable burst_cnt : natural range 0 to 3;
|
||||
begin
|
||||
if rst = '1' then
|
||||
burst_cnt := 0;
|
||||
elsif rising_edge(clk) then
|
||||
burst_finished <= '0';
|
||||
if burst_load_en = '1' then
|
||||
burst_cnt := burst_preset;
|
||||
elsif burst_cnt /= 0 then
|
||||
burst_cnt := burst_cnt - 1;
|
||||
end if;
|
||||
if burst_cnt = 0 then
|
||||
burst_finished <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
end behaviour;
|
||||
@@ -1,74 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: User SDRAM component adjustments
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package sdram_config is
|
||||
|
||||
constant DDR_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width
|
||||
constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
|
||||
constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
|
||||
constant DDR_ROW_ADDR_WIDTH : positive := 13; --
|
||||
constant DDR_COL_ADDR_WIDTH : positive := 9; --
|
||||
|
||||
constant LMR_REG_BASE : natural := 0;
|
||||
constant LMR_REG_EXTENDED : natural := 1;
|
||||
constant LMR_OP_NORMAL : natural := 0;
|
||||
constant LMR_OP_RES_DLL : natural := 2;
|
||||
constant LMR_BT_SEQ : natural := 0;
|
||||
constant LMR_BT_ILVD : natural := 1;
|
||||
constant LMR_BL2 : natural := 1;
|
||||
constant LMR_BL4 : natural := 2;
|
||||
constant LMR_BL8 : natural := 3;
|
||||
constant LMR_CL2 : natural := 2;
|
||||
constant LMR_CL3 : natural := 3;
|
||||
constant LMR_CL2_5 : natural := 6;
|
||||
|
||||
-- DDR SDRAM Hardware defined constants
|
||||
constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
|
||||
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
|
||||
constant ENABLE_PRE_ALL : std_logic := '1';
|
||||
constant ENABLE_AUTO_PRE : std_logic := '0';
|
||||
|
||||
-- DDR-SDR TIMING constants ------------------------------------------------------------------
|
||||
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
|
||||
constant REFRESH_INTERVAL : real := 7.8125; -- us
|
||||
|
||||
-- These values are for your SDRAM part (see datasheet)
|
||||
constant TCAS : positive := 2; -- CAS latency [clocks]
|
||||
constant TRP : positive := 2; -- precharge command period
|
||||
constant TRAS : positive := 4; -- active to precharge delay
|
||||
constant TRFC : positive := 8; -- auto refresh command period
|
||||
constant TMRD : positive := 2; -- load mode register command cylce time
|
||||
constant TRCD : positive := 2; -- active to read or write delay !
|
||||
constant TWR : positive := 2; -- write recovery time
|
||||
|
||||
constant PWR_UP_WAIT : natural := 1; -- µs
|
||||
|
||||
subtype user_tag_t is unsigned(3 downto 0);
|
||||
|
||||
----------------------------------------------------------------------------------------------
|
||||
|
||||
end sdram_config;
|
||||
@@ -1,487 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: SDRAM main controller and user I/F
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
use work.utils_pkg.all;
|
||||
|
||||
entity sdram_ctrl is
|
||||
Generic
|
||||
(
|
||||
f_sysclk : natural := 100E6;
|
||||
BL : natural := 2
|
||||
);
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
u_busy : out STD_LOGIC;
|
||||
u_tag_in : in user_tag_t;
|
||||
u_tag_out : out user_tag_t;
|
||||
u_addr : in user_addr_t;
|
||||
u_cmd : in user_cmd_t;
|
||||
u_cmd_we : in STD_LOGIC;
|
||||
col_addr : out col_addr_t;
|
||||
sdr_cmd_busy : in STD_LOGIC;
|
||||
sdr_cmd : out sdr_cmd_t;
|
||||
sdr_cmd_we : out STD_LOGIC;
|
||||
sdr_mode : out mode_word_t;
|
||||
sdr_cke : out STD_LOGIC
|
||||
);
|
||||
end sdram_ctrl;
|
||||
|
||||
architecture behaviour of sdram_ctrl is
|
||||
|
||||
constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL);
|
||||
|
||||
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH);
|
||||
signal st_ctrl, st_ctrl_next : ctrl_state_t;
|
||||
|
||||
constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
|
||||
signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
|
||||
signal pwr_up_cnt_rst : std_logic;
|
||||
signal pwr_up_finished : std_logic;
|
||||
|
||||
signal cycle_cnt : natural range 0 to 255;
|
||||
signal cc_preset : natural range 0 to 255;
|
||||
signal cc_load_en : std_logic;
|
||||
signal cycle_finished : std_logic;
|
||||
|
||||
signal seq_cnt : natural range 0 to 31;
|
||||
signal seq_rst_en : std_logic;
|
||||
signal seq_cnt_en : std_logic;
|
||||
|
||||
constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6);
|
||||
signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
|
||||
signal refresh_request : std_logic;
|
||||
signal refresh_cnt_rst : std_logic;
|
||||
|
||||
signal addr_reg_load_en : std_logic;
|
||||
|
||||
signal u_tag_reg : user_tag_t;
|
||||
signal bank_addr_reg : bank_addr_t;
|
||||
signal row_addr_reg : row_addr_t;
|
||||
signal col_addr_reg : col_addr_t;
|
||||
|
||||
signal u_bank_addr : bank_addr_t;
|
||||
signal u_row_addr : row_addr_t;
|
||||
signal u_col_addr : col_addr_t;
|
||||
|
||||
signal act_request : std_logic;
|
||||
signal act_request_set : std_logic;
|
||||
signal act_request_clr : std_logic;
|
||||
|
||||
type init_seq_rom_t is array (0 to 14) of init_seq_t;
|
||||
|
||||
constant init_seq_rom : init_seq_rom_t :=
|
||||
(
|
||||
(
|
||||
cmd => SD_NOP,
|
||||
mode_word => (others => '0'),
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_PRE,
|
||||
mode_word => "000010000000000",
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_NOP,
|
||||
mode_word => (others => '0'),
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_LMR,
|
||||
mode_word => to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010",
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_NOP,
|
||||
mode_word => (others => '0'),
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_LMR,
|
||||
mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
|
||||
wait_cycle => 200
|
||||
),
|
||||
(
|
||||
cmd => SD_NOP,
|
||||
mode_word => (others => '0'),
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_PRE,
|
||||
mode_word => "000010000000000",
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_NOP,
|
||||
mode_word => (others => '0'),
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_AR,
|
||||
mode_word => (others => '0'),
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_NOP,
|
||||
mode_word => (others => '0'),
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_AR,
|
||||
mode_word => (others => '0'),
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_NOP,
|
||||
mode_word => (others => '0'),
|
||||
wait_cycle => 0
|
||||
),
|
||||
(
|
||||
cmd => SD_LMR,
|
||||
mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
|
||||
wait_cycle => 200
|
||||
),
|
||||
(
|
||||
cmd => SD_NOP,
|
||||
mode_word => (others => '0'),
|
||||
wait_cycle => 0
|
||||
)
|
||||
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1);
|
||||
u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1);
|
||||
u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0);
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
fsm_ctrl_state:
|
||||
process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request)
|
||||
begin
|
||||
|
||||
u_busy <= '1';
|
||||
pwr_up_cnt_rst <= '0';
|
||||
cc_preset <= init_seq_rom(seq_cnt).wait_cycle;
|
||||
cc_load_en <= '0';
|
||||
sdr_cmd <= init_seq_rom(seq_cnt).cmd;
|
||||
sdr_cmd_we <= '0';
|
||||
sdr_mode <= bank_addr_reg & row_addr_reg;
|
||||
col_addr <= col_addr_reg;
|
||||
sdr_cke <= '1';
|
||||
seq_cnt_en <= '0';
|
||||
seq_rst_en <= '0';
|
||||
addr_reg_load_en <= '0';
|
||||
refresh_cnt_rst <= '0';
|
||||
act_request_set <= '0';
|
||||
act_request_clr <= '0';
|
||||
u_tag_out <= u_tag_reg;
|
||||
|
||||
st_ctrl_next <= st_ctrl;
|
||||
case st_ctrl is
|
||||
when RESET =>
|
||||
sdr_cke <= '0';
|
||||
pwr_up_cnt_rst <= '1';
|
||||
st_ctrl_next <= POWER_WAIT;
|
||||
|
||||
when POWER_WAIT =>
|
||||
sdr_cke <= '0';
|
||||
if pwr_up_finished = '1' then
|
||||
seq_rst_en <= '1';
|
||||
st_ctrl_next <= INIT;
|
||||
end if;
|
||||
|
||||
when INIT =>
|
||||
sdr_mode <= init_seq_rom(seq_cnt).mode_word;
|
||||
sdr_cmd <= init_seq_rom(seq_cnt).cmd;
|
||||
cc_preset <= init_seq_rom(seq_cnt).wait_cycle;
|
||||
if seq_cnt = init_seq_rom_t'high then
|
||||
act_request_set <= '1';
|
||||
refresh_cnt_rst <= '1';
|
||||
st_ctrl_next <= USER_READY;
|
||||
elsif sdr_cmd_busy = '0' then
|
||||
cc_load_en <= '1';
|
||||
sdr_cmd_we <= '1';
|
||||
st_ctrl_next <= INIT_WAIT;
|
||||
end if;
|
||||
|
||||
when INIT_WAIT =>
|
||||
if sdr_cmd_busy = '0' and cycle_finished = '1' then
|
||||
seq_cnt_en <= '1';
|
||||
st_ctrl_next <= INIT;
|
||||
end if;
|
||||
|
||||
when USER_READY =>
|
||||
if sdr_cmd_busy = '0' then
|
||||
if refresh_request = '1' then
|
||||
sdr_mode(BIT_PRE_ALL) <= '1';
|
||||
sdr_cmd_we <= '1';
|
||||
sdr_cmd <= SD_PRE;
|
||||
st_ctrl_next <= REFRESH;
|
||||
else
|
||||
u_busy <= '0';
|
||||
if u_cmd_we = '1' then
|
||||
case u_cmd is
|
||||
when UCMD_NOP =>
|
||||
sdr_cmd <= SD_NOP;
|
||||
when UCMD_LMR =>
|
||||
sdr_cmd <= SD_NOP;
|
||||
when UCMD_WRITE =>
|
||||
col_addr <= u_col_addr;
|
||||
u_tag_out <= u_tag_in;
|
||||
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
|
||||
addr_reg_load_en <= '1';
|
||||
act_request_clr <= '1';
|
||||
sdr_cmd <= SD_WRITE;
|
||||
if (u_row_addr /= row_addr_reg) or act_request = '1' then
|
||||
st_ctrl_next <= USER_WRITE_PRE;
|
||||
elsif (u_bank_addr /= bank_addr_reg) then
|
||||
if ENABLE_PRE_ALL = '1' then
|
||||
st_ctrl_next <= USER_WRITE_ACT;
|
||||
else
|
||||
st_ctrl_next <= USER_WRITE_PRE;
|
||||
end if;
|
||||
elsif sdr_cmd_busy = '0' then
|
||||
sdr_cmd_we <= '1';
|
||||
else
|
||||
st_ctrl_next <= USER_WRITE;
|
||||
end if;
|
||||
when UCMD_READ =>
|
||||
col_addr <= u_col_addr;
|
||||
u_tag_out <= u_tag_in;
|
||||
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
|
||||
addr_reg_load_en <= '1';
|
||||
act_request_clr <= '1';
|
||||
sdr_cmd <= SD_READ;
|
||||
if (u_row_addr /= row_addr_reg) or act_request = '1' then
|
||||
st_ctrl_next <= USER_READ_PRE;
|
||||
elsif (u_bank_addr /= bank_addr_reg) then
|
||||
if ENABLE_PRE_ALL = '1' then
|
||||
st_ctrl_next <= USER_READ_ACT;
|
||||
else
|
||||
st_ctrl_next <= USER_READ_PRE;
|
||||
end if;
|
||||
elsif sdr_cmd_busy = '0' then
|
||||
sdr_cmd_we <= '1';
|
||||
else
|
||||
st_ctrl_next <= USER_READ;
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when USER_WRITE_PRE =>
|
||||
sdr_cmd <= SD_PRE;
|
||||
sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
|
||||
if sdr_cmd_busy = '0' then
|
||||
sdr_cmd_we <= '1';
|
||||
st_ctrl_next <= USER_WRITE_ACT;
|
||||
end if;
|
||||
|
||||
when USER_WRITE_ACT =>
|
||||
sdr_cmd <= SD_ACT;
|
||||
if sdr_cmd_busy = '0' then
|
||||
sdr_cmd_we <= '1';
|
||||
st_ctrl_next <= USER_WRITE;
|
||||
end if;
|
||||
|
||||
when USER_WRITE =>
|
||||
sdr_cmd <= SD_WRITE;
|
||||
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
|
||||
if sdr_cmd_busy = '0' then
|
||||
sdr_cmd_we <= '1';
|
||||
st_ctrl_next <= USER_READY;
|
||||
end if;
|
||||
|
||||
when USER_READ_PRE =>
|
||||
sdr_cmd <= SD_PRE;
|
||||
sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
|
||||
if sdr_cmd_busy = '0' then
|
||||
sdr_cmd_we <= '1';
|
||||
st_ctrl_next <= USER_READ_ACT;
|
||||
end if;
|
||||
|
||||
when USER_READ_ACT =>
|
||||
sdr_cmd <= SD_ACT;
|
||||
if sdr_cmd_busy = '0' then
|
||||
sdr_cmd_we <= '1';
|
||||
st_ctrl_next <= USER_READ;
|
||||
end if;
|
||||
|
||||
when USER_READ =>
|
||||
sdr_cmd <= SD_READ;
|
||||
sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
|
||||
if sdr_cmd_busy = '0' then
|
||||
sdr_cmd_we <= '1';
|
||||
st_ctrl_next <= USER_READY;
|
||||
end if;
|
||||
|
||||
when REFRESH =>
|
||||
sdr_cmd <= SD_AR;
|
||||
if sdr_cmd_busy = '0' then
|
||||
sdr_cmd_we <= '1';
|
||||
st_ctrl_next <= USER_READY;
|
||||
refresh_cnt_rst <= '1';
|
||||
act_request_set <= '1';
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
st_ctrl_next <= RESET;
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
fsm_ctrl_state_next:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
st_ctrl <= RESET;
|
||||
elsif rising_edge(clk) then
|
||||
st_ctrl <= st_ctrl_next;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
act_request_register:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
act_request <= '1';
|
||||
elsif rising_edge(clk) then
|
||||
if act_request_set = '1' then
|
||||
act_request <= '1';
|
||||
elsif act_request_clr = '1' then
|
||||
act_request <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
user_addr_register:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
bank_addr_reg <= (others => '0');
|
||||
row_addr_reg <= (others => '0');
|
||||
col_addr_reg <= (others => '0');
|
||||
u_tag_reg <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if addr_reg_load_en = '1' then
|
||||
bank_addr_reg <= u_bank_addr;
|
||||
row_addr_reg <= u_row_addr;
|
||||
col_addr_reg <= u_col_addr;
|
||||
u_tag_reg <= u_tag_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
power_up_counter:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
pwr_up_cnt <= 0;
|
||||
pwr_up_finished <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
pwr_up_finished <= '0';
|
||||
if pwr_up_cnt_rst = '1' then
|
||||
pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1;
|
||||
else
|
||||
if pwr_up_cnt /= 0 then
|
||||
pwr_up_cnt <= pwr_up_cnt - 1;
|
||||
else
|
||||
pwr_up_finished <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
refresh_counter:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
refresh_cnt <= 0;
|
||||
refresh_request <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
refresh_request <= '0';
|
||||
if refresh_cnt_rst = '1' then
|
||||
refresh_cnt <= REFRESH_CLOCK_INTERVAL-1;
|
||||
else
|
||||
if refresh_cnt /= 0 then
|
||||
refresh_cnt <= refresh_cnt - 1;
|
||||
else
|
||||
refresh_request <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
cycle_counter:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
cycle_cnt <= 0;
|
||||
cycle_finished <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
cycle_finished <= '0';
|
||||
if cc_load_en = '1' then
|
||||
cycle_cnt <= cc_preset;
|
||||
elsif cycle_cnt /= 0 then
|
||||
cycle_cnt <= cycle_cnt - 1;
|
||||
else
|
||||
cycle_finished <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
seq_counter:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
seq_cnt <= 0;
|
||||
elsif rising_edge(clk) then
|
||||
if seq_rst_en = '1' then
|
||||
seq_cnt <= 0;
|
||||
elsif seq_cnt_en = '1' then
|
||||
if seq_cnt /= init_seq_rom_t'high then
|
||||
seq_cnt <= seq_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
end behaviour;
|
||||
@@ -1,277 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.fifo_ctrl_pkg.all;
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
|
||||
entity sdram_ctrl_frontend is
|
||||
Generic
|
||||
(
|
||||
BL : natural := 2;
|
||||
f_sysclk : natural := 100E6;
|
||||
read_phaseshift : integer := 0;
|
||||
fifo_depth : integer := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
sys_rst_in : in STD_LOGIC;
|
||||
sys_clk_in : in STD_LOGIC;
|
||||
sys_rst_out : out STD_LOGIC;
|
||||
sys_clk_out : out STD_LOGIC;
|
||||
sys_clk_fb : in STD_LOGIC;
|
||||
|
||||
-- User interface
|
||||
busy : out STD_LOGIC;
|
||||
en : in STD_LOGIC;
|
||||
r_wn : in STD_LOGIC;
|
||||
be : in unsigned(SDR_DM_WIDTH-1 downto 0);
|
||||
addr : in user_addr_t;
|
||||
din : in unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
dout : out unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
dout_re : in STD_LOGIC;
|
||||
dout_vld : out STD_LOGIC;
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p : out STD_LOGIC;
|
||||
sd_clk_n : out STD_LOGIC;
|
||||
sd_cke : out STD_LOGIC;
|
||||
sd_cs_n : out STD_LOGIC;
|
||||
sd_cas_n : out STD_LOGIC;
|
||||
sd_ras_n : out STD_LOGIC;
|
||||
sd_we_n : out STD_LOGIC;
|
||||
sd_addr : out sdr_addr_t;
|
||||
sd_ba : out sdr_ba_t;
|
||||
sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
|
||||
sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
|
||||
sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
|
||||
|
||||
);
|
||||
end sdram_ctrl_frontend;
|
||||
|
||||
architecture struct of sdram_ctrl_frontend is
|
||||
|
||||
-- Number of user data words for simulation
|
||||
signal rst_out : std_logic;
|
||||
signal clk_out : std_logic;
|
||||
|
||||
signal u_addr : user_addr_t;
|
||||
signal u_tag_in : user_tag_t;
|
||||
signal u_tag_rd : user_tag_t;
|
||||
signal u_tag_wr : user_tag_t;
|
||||
signal u_cmd : user_cmd_t;
|
||||
signal u_cmd_we : std_logic;
|
||||
signal u_busy : std_logic;
|
||||
signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
signal u_dm : unsigned(SDR_DM_WIDTH-1 downto 0);
|
||||
signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
signal u_data_vld : std_logic;
|
||||
signal u_req_wr : std_logic;
|
||||
|
||||
constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
|
||||
signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0);
|
||||
signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0);
|
||||
signal cat_fifo_re : std_logic;
|
||||
signal cat_fifo_we : std_logic;
|
||||
signal cat_fifo_full : std_logic;
|
||||
signal cat_fifo_empty : std_logic;
|
||||
-- signal cat_fifo_almost_full : std_logic;
|
||||
-- signal cat_fifo_almost_empty : std_logic;
|
||||
|
||||
signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
|
||||
signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
|
||||
signal write_fifo_re : std_logic;
|
||||
signal write_fifo_we : std_logic;
|
||||
signal write_fifo_full : std_logic;
|
||||
signal write_fifo_empty : std_logic;
|
||||
-- signal write_fifo_almost_full : std_logic;
|
||||
-- signal write_fifo_almost_empty : std_logic;
|
||||
|
||||
signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
signal read_fifo_re : std_logic;
|
||||
signal read_fifo_we : std_logic;
|
||||
signal read_fifo_full : std_logic;
|
||||
signal read_fifo_empty : std_logic;
|
||||
-- signal read_fifo_almost_full : std_logic;
|
||||
-- signal read_fifo_almost_empty : std_logic;
|
||||
|
||||
alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
|
||||
alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
|
||||
alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
|
||||
alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
|
||||
alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
|
||||
alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
|
||||
alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-SDR_DM_WIDTH);
|
||||
alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-SDR_DM_WIDTH-1 downto 0);
|
||||
alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-SDR_DM_WIDTH);
|
||||
alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-SDR_DM_WIDTH-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_cat_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => fifo_depth,
|
||||
data_width => CAT_FIFO_WIDTH
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst_out,
|
||||
clk => clk_out,
|
||||
we => cat_fifo_we,
|
||||
re => cat_fifo_re,
|
||||
fifo_full => cat_fifo_full,
|
||||
fifo_empty => cat_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => cat_fifo_din,
|
||||
data_r => cat_fifo_dout
|
||||
);
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_write_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => fifo_depth,
|
||||
data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst_out,
|
||||
clk => clk_out,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => write_fifo_din,
|
||||
data_r => write_fifo_dout
|
||||
);
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_read_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => fifo_depth,
|
||||
data_width => 2*DDR_DATA_WIDTH
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst_out,
|
||||
clk => clk_out,
|
||||
we => read_fifo_we,
|
||||
re => read_fifo_re,
|
||||
fifo_full => read_fifo_full,
|
||||
fifo_empty => read_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => read_fifo_din,
|
||||
data_r => read_fifo_dout
|
||||
);
|
||||
|
||||
-- DDR SDRAM Controller Core
|
||||
inst_sdram_ctrl : entity work.sdram_ctrl_top
|
||||
Generic map
|
||||
(
|
||||
BL => BL,
|
||||
read_phaseshift => read_phaseshift,
|
||||
f_sysclk => f_sysclk
|
||||
)
|
||||
Port map
|
||||
(
|
||||
|
||||
sys_rst_in => sys_rst_in,
|
||||
sys_clk_in => sys_clk_in,
|
||||
|
||||
sys_rst_out => rst_out,
|
||||
sys_clk_out => clk_out,
|
||||
sys_clk_fb => sys_clk_fb,
|
||||
|
||||
-- User interface
|
||||
u_data_vld => u_data_vld,
|
||||
u_data_req_w => u_req_wr,
|
||||
u_data_req_r => open,
|
||||
u_tag_in => u_tag_in,
|
||||
u_tag_rd => u_tag_rd,
|
||||
u_tag_wr => u_tag_wr,
|
||||
u_busy => u_busy,
|
||||
u_addr => u_addr,
|
||||
u_cmd => u_cmd,
|
||||
u_cmd_we => u_cmd_we,
|
||||
u_data_wr => u_data_w,
|
||||
u_data_rd => u_data_r,
|
||||
u_dm => u_dm,
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p => sd_clk_p,
|
||||
sd_clk_n => sd_clk_n,
|
||||
sd_cke => sd_cke,
|
||||
sd_cs_n => sd_cs_n,
|
||||
sd_cas_n => sd_cas_n,
|
||||
sd_ras_n => sd_ras_n,
|
||||
sd_we_n => sd_we_n,
|
||||
sd_addr => sd_addr,
|
||||
sd_ba => sd_ba,
|
||||
sd_dm => sd_dm,
|
||||
sd_dqs => sd_dqs,
|
||||
sd_data => sd_data
|
||||
|
||||
);
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
sys_rst_out <= rst_out;
|
||||
sys_clk_out <= clk_out;
|
||||
|
||||
busy <= cat_fifo_full or write_fifo_full or read_fifo_full;
|
||||
write_fifo_we <= en and not r_wn and not write_fifo_full and not cat_fifo_full and not read_fifo_full;
|
||||
write_fifo_data_in <= din;
|
||||
write_fifo_dm_in <= not be;
|
||||
cat_fifo_we <= en and not cat_fifo_full and not write_fifo_full and not read_fifo_full;
|
||||
cmd_fifo_in <= UCMD_WRITE when r_wn = '0' else UCMD_READ;
|
||||
addr_fifo_in <= addr;
|
||||
tag_fifo_in <= (others=>'0');
|
||||
dout <= read_fifo_dout;
|
||||
dout_vld <= not read_fifo_empty;
|
||||
|
||||
u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
|
||||
u_cmd <= cmd_fifo_out;
|
||||
u_addr <= addr_fifo_out;
|
||||
u_dm <= write_fifo_dm_out;
|
||||
u_tag_in <= tag_fifo_out;
|
||||
|
||||
write_fifo_re <= u_req_wr and (not write_fifo_empty);
|
||||
cat_fifo_re <= u_cmd_we;
|
||||
u_data_w <= write_fifo_data_out;
|
||||
read_fifo_re <= (not read_fifo_empty) and dout_re;
|
||||
read_fifo_we <= u_data_vld;
|
||||
read_fifo_din <= u_data_r;
|
||||
|
||||
|
||||
end architecture struct;
|
||||
@@ -1,285 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: Top-level put all together
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
|
||||
entity sdram_ctrl_top is
|
||||
Generic
|
||||
(
|
||||
BL : natural := 2;
|
||||
f_sysclk : natural := 100E6;
|
||||
read_phaseshift : integer := 0
|
||||
);
|
||||
Port
|
||||
(
|
||||
sys_rst_in : in STD_LOGIC;
|
||||
sys_clk_in : in STD_LOGIC;
|
||||
sys_rst_out : out STD_LOGIC;
|
||||
sys_clk_out : out STD_LOGIC;
|
||||
sys_clk_fb : in STD_LOGIC;
|
||||
|
||||
-- User interface
|
||||
u_data_vld : out STD_LOGIC;
|
||||
u_data_req_w : out STD_LOGIC;
|
||||
u_data_req_r : out STD_LOGIC;
|
||||
u_busy : out STD_LOGIC;
|
||||
u_tag_in : in user_tag_t;
|
||||
u_tag_rd : out user_tag_t;
|
||||
u_tag_wr : out user_tag_t;
|
||||
u_addr : in user_addr_t;
|
||||
u_cmd : in user_cmd_t;
|
||||
u_cmd_we : in STD_LOGIC;
|
||||
u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0);
|
||||
u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0);
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p : out STD_LOGIC;
|
||||
sd_clk_n : out STD_LOGIC;
|
||||
sd_cke : out STD_LOGIC;
|
||||
sd_cs_n : out STD_LOGIC;
|
||||
sd_cas_n : out STD_LOGIC;
|
||||
sd_ras_n : out STD_LOGIC;
|
||||
sd_we_n : out STD_LOGIC;
|
||||
sd_addr : out sdr_addr_t;
|
||||
sd_ba : out sdr_ba_t;
|
||||
sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
|
||||
sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
|
||||
sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
|
||||
|
||||
);
|
||||
end sdram_ctrl_top;
|
||||
|
||||
architecture rtl of sdram_ctrl_top is
|
||||
|
||||
signal clk0 : std_logic;
|
||||
signal clk270 : std_logic;
|
||||
signal read_clk270 : std_logic;
|
||||
|
||||
signal phy_ctrl : phy_ctrl_t;
|
||||
|
||||
signal u_tag : user_tag_t;
|
||||
signal sd_cmd_in : sdr_cmd_t;
|
||||
signal sd_cmd : sdr_cmd_t;
|
||||
signal sd_cmd_we : std_logic;
|
||||
signal cmd_ctrl : sdr_cmd_lines_t;
|
||||
signal cke : std_logic;
|
||||
signal ba : unsigned(DDR_BANK_WIDTH-1 downto 0);
|
||||
signal addr : unsigned(DDR_ADDR_WIDTH-1 downto 0);
|
||||
|
||||
-- Clock generator
|
||||
|
||||
signal cg_rst : std_logic;
|
||||
signal cg_read_clk0 : std_logic;
|
||||
signal cg_read_clk270 : std_logic;
|
||||
signal cg_sys_clk0 : std_logic;
|
||||
signal cg_sys_clk270 : std_logic;
|
||||
signal cg_locked : std_logic;
|
||||
signal cg_error : std_logic;
|
||||
signal ctrl_rst : std_logic;
|
||||
signal part_ctrl : part_ctrl_t;
|
||||
|
||||
-- SD command FIFO
|
||||
|
||||
constant CMD_FIFO_ADDR_WIDTH : positive := 2;
|
||||
constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length;
|
||||
signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
|
||||
signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
|
||||
signal cmd_fifo_re : std_logic;
|
||||
signal cmd_fifo_we : std_logic;
|
||||
signal cmd_fifo_full : std_logic;
|
||||
signal cmd_fifo_empty : std_logic;
|
||||
|
||||
alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
|
||||
alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
|
||||
alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
|
||||
alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
|
||||
|
||||
alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
|
||||
alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
|
||||
alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
|
||||
alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
---------------------------------
|
||||
clk0 <= cg_sys_clk0;
|
||||
clk270 <= cg_sys_clk270;
|
||||
read_clk270 <= cg_read_clk270;
|
||||
cg_rst <= not cg_locked;
|
||||
|
||||
---------------------------------
|
||||
sys_clk_out <= cg_sys_clk0;
|
||||
sys_rst_out <= ctrl_rst;
|
||||
|
||||
---------------------------------
|
||||
part_ctrl.cmd <= cmd_ctrl;
|
||||
part_ctrl.ba <= ba;
|
||||
part_ctrl.addr <= addr;
|
||||
part_ctrl.cke <= cke;
|
||||
|
||||
---------------------------------
|
||||
sd_cmd_we <= not cmd_fifo_empty;
|
||||
cmd_fifo_in <= to_unsigned(sd_cmd_in, 4);
|
||||
sd_cmd <= sdr_cmd_t(to_integer(cmd_fifo_out));
|
||||
|
||||
---------------------------------
|
||||
inst_reset: entity work.reset
|
||||
port map
|
||||
(
|
||||
clk => clk0,
|
||||
rst_in => cg_rst,
|
||||
rst_out => ctrl_rst
|
||||
);
|
||||
|
||||
inst_clockgen : entity work.clockgen
|
||||
generic map
|
||||
(
|
||||
read_phaseshift => read_phaseshift,
|
||||
frequency_hz => f_sysclk
|
||||
)
|
||||
port map
|
||||
(
|
||||
rst => sys_rst_in,
|
||||
clk_in => sys_clk_in,
|
||||
clk_fb_in => sys_clk_fb,
|
||||
read_clk0_out => cg_read_clk0,
|
||||
read_clk270_out => cg_read_clk270,
|
||||
sys_clk0_out => cg_sys_clk0,
|
||||
sys_clk270_out => cg_sys_clk270,
|
||||
locked_out => cg_locked,
|
||||
error_out => cg_error
|
||||
);
|
||||
|
||||
-- Main controller
|
||||
inst_sdram_ctrl : entity work.sdram_ctrl
|
||||
Generic map
|
||||
(
|
||||
f_sysclk => 100E6,
|
||||
BL => BL
|
||||
)
|
||||
Port map
|
||||
(
|
||||
rst => ctrl_rst,
|
||||
clk => clk0,
|
||||
u_busy => u_busy,
|
||||
u_tag_in => u_tag_in,
|
||||
u_tag_out => tag_fifo_in,
|
||||
u_cmd => u_cmd,
|
||||
u_cmd_we => u_cmd_we,
|
||||
u_addr => u_addr,
|
||||
sdr_cmd_busy => cmd_fifo_full,
|
||||
sdr_cmd => sd_cmd_in,
|
||||
sdr_cmd_we => cmd_fifo_we,
|
||||
col_addr => col_fifo_in,
|
||||
sdr_mode => mode_fifo_in,
|
||||
sdr_cke => cke
|
||||
);
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_sd_cmd_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => CMD_FIFO_ADDR_WIDTH,
|
||||
data_width => CMD_FIFO_DATA_WIDTH,
|
||||
almost_full_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1),
|
||||
almost_empty_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1)
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => ctrl_rst,
|
||||
clk => clk0,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => open,
|
||||
fifo_aempty => open,
|
||||
data_w => cmd_fifo_din,
|
||||
data_r => cmd_fifo_dout
|
||||
);
|
||||
|
||||
-- DDR SDRAM command fsm
|
||||
inst_sdram_cmd : entity work.sdram_cmd
|
||||
Generic map
|
||||
(
|
||||
BL => BL
|
||||
)
|
||||
Port map
|
||||
(
|
||||
rst => ctrl_rst,
|
||||
clk => clk0,
|
||||
u_tag_in => tag_fifo_out,
|
||||
u_tag_out => u_tag,
|
||||
phy_ctrl => phy_ctrl,
|
||||
enable => cke,
|
||||
cmd => sd_cmd,
|
||||
cmd_we => sd_cmd_we,
|
||||
cmd_ack => cmd_fifo_re,
|
||||
sdr_cmd_ctrl => cmd_ctrl,
|
||||
col_addr => col_fifo_out,
|
||||
mode_word => mode_fifo_out,
|
||||
sdr_ba => ba,
|
||||
sdr_addr => addr
|
||||
);
|
||||
|
||||
-- DDR phy
|
||||
inst_ddr_phy : entity work.ddr_phy
|
||||
Port map
|
||||
(
|
||||
sys_rst => ctrl_rst,
|
||||
sys_clk0 => clk0,
|
||||
sys_clk270 => clk270,
|
||||
u_tag_in => u_tag,
|
||||
u_tag_rd => u_tag_rd,
|
||||
u_tag_wr => u_tag_wr,
|
||||
read_clk => read_clk270,
|
||||
phy_ctrl => phy_ctrl,
|
||||
part_ctrl => part_ctrl,
|
||||
sdr_data_req_w => u_data_req_w,
|
||||
sdr_data_req_r => u_data_req_r,
|
||||
sdr_data_w => u_data_wr,
|
||||
sdr_dm => u_dm,
|
||||
sdr_data_r => u_data_rd,
|
||||
sdr_data_vld => u_data_vld,
|
||||
part_clk_p => sd_clk_p,
|
||||
part_clk_n => sd_clk_n,
|
||||
part_addr => sd_addr,
|
||||
part_ba => sd_ba,
|
||||
part_dm => sd_dm,
|
||||
part_dqs => sd_dqs,
|
||||
part_data => sd_data,
|
||||
part_cs_n => sd_cs_n,
|
||||
part_we_n => sd_we_n,
|
||||
part_cas_n => sd_cas_n,
|
||||
part_ras_n => sd_ras_n,
|
||||
part_cke => sd_cke
|
||||
);
|
||||
|
||||
end architecture rtl;
|
||||
|
||||
@@ -1,133 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: Type definitions
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.sdram_config.all;
|
||||
|
||||
package sdram_types is
|
||||
|
||||
-----------------------------------------------------------------------------------------
|
||||
-- Table of Timing Parameters as a function of operation
|
||||
|
||||
-- Derived constants from sdram_config
|
||||
|
||||
constant DDR_DQS_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines
|
||||
constant DDR_DM_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines
|
||||
constant SDR_DATA_WIDTH : positive := 2*DDR_DATA_WIDTH; --
|
||||
constant SDR_DM_WIDTH : positive := 2*DDR_DM_WIDTH; --
|
||||
|
||||
subtype user_cmd_t is unsigned(1 downto 0);
|
||||
constant UCMD_NOP : user_cmd_t := "00";
|
||||
constant UCMD_READ : user_cmd_t := "01";
|
||||
constant UCMD_WRITE : user_cmd_t := "10";
|
||||
constant UCMD_LMR : user_cmd_t := "11";
|
||||
|
||||
subtype sdr_cmd_t is natural range 0 to 9;
|
||||
constant SD_DESELECT : sdr_cmd_t := 0;
|
||||
constant SD_NOP : sdr_cmd_t := 1;
|
||||
constant SD_LMR : sdr_cmd_t := 2;
|
||||
constant SD_ACT : sdr_cmd_t := 3;
|
||||
constant SD_READ : sdr_cmd_t := 4;
|
||||
constant SD_WRITE : sdr_cmd_t := 5;
|
||||
constant SD_PRE : sdr_cmd_t := 6;
|
||||
constant SD_BST : sdr_cmd_t := 7;
|
||||
constant SD_AR : sdr_cmd_t := 8;
|
||||
constant SD_SR : sdr_cmd_t := 9;
|
||||
|
||||
type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
|
||||
subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0);
|
||||
subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
|
||||
subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
|
||||
subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0);
|
||||
|
||||
subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
|
||||
subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
|
||||
subtype col_addr_t is unsigned(8 downto 0);
|
||||
|
||||
subtype cycle_cnt_t is natural range 0 to 10;
|
||||
|
||||
type phy_ctrl_t is
|
||||
record
|
||||
drive_en : std_logic;
|
||||
re : std_logic;
|
||||
we : std_logic;
|
||||
utag_we : std_logic;
|
||||
end record phy_ctrl_t;
|
||||
|
||||
type sdr_cmd_lines_t is
|
||||
record
|
||||
cs_n : std_logic;
|
||||
ras_n : std_logic;
|
||||
cas_n : std_logic;
|
||||
we_n : std_logic;
|
||||
end record sdr_cmd_lines_t;
|
||||
|
||||
type part_ctrl_t is
|
||||
record
|
||||
cmd : sdr_cmd_lines_t;
|
||||
ba : unsigned(DDR_BANK_WIDTH-1 downto 0);
|
||||
addr : unsigned(DDR_ADDR_WIDTH-1 downto 0);
|
||||
cke : std_logic;
|
||||
end record part_ctrl_t;
|
||||
|
||||
type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t;
|
||||
constant COMMAND : part_cmd_array_t :=
|
||||
-- command cs_n ras_qn cas_qn we_qn
|
||||
( SD_DESELECT => ( '1', '1', '1', '1'),
|
||||
SD_NOP => ( '0', '1', '1', '1'),
|
||||
SD_LMR => ( '0', '0', '0', '0'),
|
||||
SD_ACT => ( '0', '0', '1', '1'),
|
||||
SD_READ => ( '0', '1', '0', '1'),
|
||||
SD_WRITE => ( '0', '1', '0', '0'),
|
||||
SD_PRE => ( '0', '0', '1', '0'),
|
||||
SD_BST => ( '0', '1', '1', '0'),
|
||||
SD_AR => ( '0', '0', '0', '1'),
|
||||
SD_SR => ( '0', '0', '0', '1')
|
||||
);
|
||||
|
||||
type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
|
||||
constant TIMING : part_timing_array_t :=
|
||||
-- command cycle_cnt
|
||||
( SD_DESELECT => ( 0 ),
|
||||
SD_NOP => ( 0 ),
|
||||
SD_LMR => ( TMRD-1 ),
|
||||
SD_ACT => ( TRCD-1 ),
|
||||
SD_READ => ( TCAS-1 ),
|
||||
SD_WRITE => ( TWR-1 ),
|
||||
SD_PRE => ( TRP-1 ),
|
||||
SD_BST => ( 0 ),
|
||||
SD_AR => ( TRFC-1 ),
|
||||
SD_SR => ( TRFC-1 )
|
||||
);
|
||||
|
||||
type init_seq_t is
|
||||
record
|
||||
cmd : sdr_cmd_t;
|
||||
mode_word : mode_word_t;
|
||||
wait_cycle : natural;
|
||||
end record init_seq_t;
|
||||
|
||||
end sdram_types;
|
||||
@@ -1,332 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
use work.utils_pkg.all;
|
||||
|
||||
entity tb_sdr_ctrl is
|
||||
end;
|
||||
|
||||
architecture struct of tb_sdr_ctrl is
|
||||
|
||||
-- Number of user data words for simulation
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant BURST_LEN : natural := 8;
|
||||
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '0';
|
||||
signal rst_out : std_logic;
|
||||
signal clk_out : std_logic;
|
||||
signal clk_fb : std_logic;
|
||||
signal part_clk_p : std_logic;
|
||||
signal part_clk_n : std_logic;
|
||||
signal part_cke : std_logic;
|
||||
signal part_cs_n : std_logic;
|
||||
signal part_we_n : std_logic;
|
||||
signal part_ras_n : std_logic;
|
||||
signal part_cas_n : std_logic;
|
||||
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal u_addr : user_addr_t := (others => '0');
|
||||
signal u_tag_in : user_tag_t := "0000";
|
||||
signal u_tag_rd : user_tag_t;
|
||||
signal u_tag_wr : user_tag_t;
|
||||
signal u_cmd : user_cmd_t := UCMD_NOP;
|
||||
signal u_cmd_we : std_logic := '0';
|
||||
signal u_busy : std_logic;
|
||||
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
|
||||
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_data_vld : std_logic;
|
||||
signal u_req_wr : std_logic;
|
||||
signal u_req_rd : std_logic;
|
||||
signal u_read_en : std_logic := '0';
|
||||
signal u_write_en : std_logic := '0';
|
||||
signal u_addr_cnt_en : std_logic := '0';
|
||||
signal u_addr_load : std_logic := '0';
|
||||
signal u_addr_preset : user_addr_t := (others => '0');
|
||||
signal u_addr_end : user_addr_t := (others => '0');
|
||||
signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
|
||||
signal test_phase : test_phase_t := IDLE;
|
||||
|
||||
type u_addr_mode_t is (MONOTONIC, RANDOM);
|
||||
signal u_addr_mode : u_addr_mode_t := MONOTONIC;
|
||||
signal cycle_cnt : natural := 1;
|
||||
signal data_cnt : natural := 0;
|
||||
signal efficiency : real := 0.0;
|
||||
|
||||
begin
|
||||
|
||||
clk_fb <= part_clk_p after 1 ns;
|
||||
|
||||
-- DDR SDRAM Controller Core
|
||||
inst_sdram_ctrl : entity work.sdram_ctrl_top
|
||||
Generic map
|
||||
(
|
||||
BL => BURST_LEN,
|
||||
read_phaseshift => 0,
|
||||
f_sysclk => 100E6
|
||||
)
|
||||
Port map
|
||||
(
|
||||
|
||||
sys_rst_in => rst,
|
||||
sys_clk_in => clk,
|
||||
|
||||
sys_rst_out => rst_out,
|
||||
sys_clk_out => clk_out,
|
||||
sys_clk_fb => clk_fb,
|
||||
|
||||
-- User interface
|
||||
u_data_vld => u_data_vld,
|
||||
u_data_req_w => u_req_wr,
|
||||
u_data_req_r => u_req_rd,
|
||||
u_tag_in => u_tag_in,
|
||||
u_tag_rd => u_tag_rd,
|
||||
u_tag_wr => u_tag_wr,
|
||||
u_busy => u_busy,
|
||||
u_addr => u_addr,
|
||||
u_cmd => u_cmd,
|
||||
u_cmd_we => u_cmd_we,
|
||||
u_data_wr => u_data_w,
|
||||
u_data_rd => u_data_r,
|
||||
u_dm => u_dm,
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p => part_clk_p,
|
||||
sd_clk_n => part_clk_n,
|
||||
sd_cke => part_cke,
|
||||
sd_cs_n => part_cs_n,
|
||||
sd_cas_n => part_cas_n,
|
||||
sd_ras_n => part_ras_n,
|
||||
sd_we_n => part_we_n,
|
||||
sd_addr => part_addr,
|
||||
sd_ba => part_ba,
|
||||
sd_dm => part_dm,
|
||||
sd_dqs => part_dqs,
|
||||
sd_data => part_data
|
||||
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(part_data),
|
||||
dqs => std_logic_vector(part_dqs),
|
||||
addr => std_logic_vector(part_addr),
|
||||
ba => std_logic_vector(part_ba),
|
||||
clk => part_clk_p,
|
||||
clk_n => part_clk_n,
|
||||
cke => part_cke,
|
||||
cs_n => part_cs_n,
|
||||
ras_n => part_ras_n,
|
||||
cas_n => part_cas_n,
|
||||
we_n => part_we_n,
|
||||
dm => std_logic_vector(part_dm)
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
R_DATA_COMPARE:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_data_vld='1' then
|
||||
if u_read_en = '1' then
|
||||
assert (ref_data = u_data_r) report "Error on read!" severity failure;
|
||||
end if;
|
||||
for i in 0 to DDR_DATA_WIDTH/4-1 loop
|
||||
ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
|
||||
end loop;
|
||||
last_data := last_data + DDR_DATA_WIDTH/4;
|
||||
elsif u_read_en = '0' then
|
||||
last_data := (others => '0');
|
||||
ref_data <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
W_DATA_GEN:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_req_wr = '1' then
|
||||
for i in 0 to DDR_DATA_WIDTH/4-1 loop
|
||||
u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
|
||||
end loop;
|
||||
last_data := last_data + DDR_DATA_WIDTH/4;
|
||||
elsif u_write_en = '0' then
|
||||
last_data := (others => '0');
|
||||
u_data_w <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ADDR_GEN:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_addr_load = '1' then
|
||||
u_addr <= u_addr_preset;
|
||||
elsif u_addr_cnt_en = '1' then
|
||||
if u_addr_mode = MONOTONIC then
|
||||
u_addr <= u_addr + BURST_LEN;
|
||||
else
|
||||
if u_addr(u_addr'left) = '1' then
|
||||
if BURST_LEN = 2 then
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
|
||||
elsif BURST_LEN = 4 then
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
|
||||
elsif BURST_LEN = 8 then
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
|
||||
end if;
|
||||
else
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
performance_count:
|
||||
process(clk_out)
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_write_en = '1' or u_read_en = '1' then
|
||||
cycle_cnt <= cycle_cnt + 1;
|
||||
if u_req_wr = '1' or u_req_rd = '1' then
|
||||
data_cnt <= data_cnt + 1;
|
||||
end if;
|
||||
else
|
||||
cycle_cnt <= 1;
|
||||
data_cnt <= 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
|
||||
|
||||
efficiency <= real(data_cnt)/real(cycle_cnt);
|
||||
u_cmd_we <= (u_write_en or u_read_en) and (not u_busy);
|
||||
u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
|
||||
|
||||
process
|
||||
begin
|
||||
|
||||
-- Write MAX_WORDS to DDR SDRAM Controller
|
||||
wait for 4*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
wait for 137*CLK_PERIOD;
|
||||
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- Bank 0
|
||||
u_addr_preset <= X"000000";
|
||||
u_addr_end <= X"008000"-BURST_LEN;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_cmd <= UCMD_WRITE;
|
||||
u_write_en <= '1';
|
||||
while u_addr /= u_addr_end loop
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_write_en <= '0';
|
||||
wait until rising_edge(clk_out) and u_req_wr='0';
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- Bank 1
|
||||
u_addr_preset <= X"400000";
|
||||
u_addr_end <= X"408000"-BURST_LEN;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_cmd <= UCMD_WRITE;
|
||||
u_write_en <= '1';
|
||||
while u_addr /= u_addr_end loop
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_write_en <= '0';
|
||||
wait until rising_edge(clk_out) and u_req_wr='0';
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- Bank 0
|
||||
u_addr_preset <= X"000000";
|
||||
u_addr_end <= X"008000"-BURST_LEN;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_cmd <= UCMD_READ;
|
||||
u_read_en <= '1';
|
||||
while u_addr /= u_addr_end loop
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_read_en <= '0';
|
||||
wait until rising_edge(clk_out) and u_data_vld='0';
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- Bank 1
|
||||
u_addr_preset <= X"400000";
|
||||
u_addr_end <= X"408000"-BURST_LEN;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_cmd <= UCMD_READ;
|
||||
u_read_en <= '1';
|
||||
while u_addr /= u_addr_end loop
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_read_en <= '0';
|
||||
wait until rising_edge(clk_out) and u_data_vld='0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture struct;
|
||||
@@ -1,416 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.fifo_ctrl_pkg.all;
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
|
||||
entity tb_sdr_ctrl_fifo is
|
||||
end;
|
||||
|
||||
architecture struct of tb_sdr_ctrl_fifo is
|
||||
|
||||
-- Number of user data words for simulation
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant BURST_LEN : natural := 2;
|
||||
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '0';
|
||||
signal rst_out : std_logic;
|
||||
signal clk_out : std_logic;
|
||||
signal clk_fb : std_logic;
|
||||
signal part_clk_p : std_logic;
|
||||
signal part_clk_n : std_logic;
|
||||
signal part_cke : std_logic;
|
||||
signal part_cs_n : std_logic;
|
||||
signal part_we_n : std_logic;
|
||||
signal part_ras_n : std_logic;
|
||||
signal part_cas_n : std_logic;
|
||||
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal u_addr : user_addr_t := (others => '0');
|
||||
signal u_tag_in : user_tag_t := "0000";
|
||||
signal u_tag_rd : user_tag_t;
|
||||
signal u_tag_wr : user_tag_t;
|
||||
signal u_cmd : user_cmd_t := UCMD_NOP;
|
||||
signal u_cmd_we : std_logic := '0';
|
||||
signal u_busy : std_logic;
|
||||
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
|
||||
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_data_vld : std_logic;
|
||||
signal u_req_wr : std_logic;
|
||||
signal u_req_rd : std_logic;
|
||||
signal u_read_en : std_logic := '0';
|
||||
signal u_write_en : std_logic := '0';
|
||||
|
||||
signal cmd_fifo_din : unsigned(25 downto 0) := (others => '0');
|
||||
signal cmd_fifo_dout : unsigned(25 downto 0) := (others => '0');
|
||||
signal cmd_fifo_re : std_logic := '0';
|
||||
signal cmd_fifo_we : std_logic := '0';
|
||||
signal cmd_fifo_full : std_logic := '0';
|
||||
signal cmd_fifo_empty : std_logic := '0';
|
||||
signal cmd_fifo_almost_full : std_logic := '0';
|
||||
signal cmd_fifo_almost_empty : std_logic := '0';
|
||||
|
||||
signal write_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal write_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal write_fifo_re : std_logic := '0';
|
||||
signal write_fifo_we : std_logic := '0';
|
||||
signal write_fifo_full : std_logic := '0';
|
||||
signal write_fifo_empty : std_logic := '0';
|
||||
signal write_fifo_almost_full : std_logic := '0';
|
||||
signal write_fifo_almost_empty : std_logic := '0';
|
||||
|
||||
signal read_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal read_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal read_fifo_re : std_logic := '0';
|
||||
signal read_fifo_we : std_logic := '0';
|
||||
signal read_fifo_full : std_logic := '0';
|
||||
signal read_fifo_empty : std_logic := '0';
|
||||
signal read_fifo_almost_full : std_logic := '0';
|
||||
signal read_fifo_almost_empty : std_logic := '0';
|
||||
|
||||
signal write_start : std_logic := '1';
|
||||
signal read_start : std_logic := '1';
|
||||
|
||||
alias cmd_fifo_in is cmd_fifo_din(25 downto 24);
|
||||
alias addr_fifo_in is cmd_fifo_din(23 downto 0);
|
||||
alias cmd_fifo_out is cmd_fifo_dout(25 downto 24);
|
||||
alias addr_fifo_out is cmd_fifo_dout(23 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
clk_fb <= part_clk_p after 1 ns;
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_command_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 8,
|
||||
data_width => 2+24
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst_out,
|
||||
clk => clk_out,
|
||||
we => cmd_fifo_we,
|
||||
re => cmd_fifo_re,
|
||||
fifo_full => cmd_fifo_full,
|
||||
fifo_empty => cmd_fifo_empty,
|
||||
fifo_afull => cmd_fifo_almost_full,
|
||||
fifo_aempty => cmd_fifo_almost_empty,
|
||||
data_w => cmd_fifo_din,
|
||||
data_r => cmd_fifo_dout
|
||||
);
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_write_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 8,
|
||||
data_width => 2*DDR_DATA_WIDTH
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst_out,
|
||||
clk => clk_out,
|
||||
we => write_fifo_we,
|
||||
re => write_fifo_re,
|
||||
fifo_full => write_fifo_full,
|
||||
fifo_empty => write_fifo_empty,
|
||||
fifo_afull => write_fifo_almost_full,
|
||||
fifo_aempty => write_fifo_almost_empty,
|
||||
data_w => write_fifo_din,
|
||||
data_r => write_fifo_dout
|
||||
);
|
||||
|
||||
-- Instantiate synchronous FIFO
|
||||
inst_read_fifo: entity work.fifo_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 8,
|
||||
data_width => 2*DDR_DATA_WIDTH
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst_out,
|
||||
clk => clk_out,
|
||||
we => read_fifo_we,
|
||||
re => read_fifo_re,
|
||||
fifo_full => read_fifo_full,
|
||||
fifo_empty => read_fifo_empty,
|
||||
fifo_afull => read_fifo_almost_full,
|
||||
fifo_aempty => read_fifo_almost_empty,
|
||||
data_w => read_fifo_din,
|
||||
data_r => read_fifo_dout
|
||||
);
|
||||
|
||||
-- DDR SDRAM Controller Core
|
||||
inst_sdram_ctrl : entity work.sdram_ctrl_top
|
||||
Generic map
|
||||
(
|
||||
BL => BURST_LEN,
|
||||
read_phaseshift => 0,
|
||||
f_sysclk => 100E6
|
||||
)
|
||||
Port map
|
||||
(
|
||||
|
||||
sys_rst_in => rst,
|
||||
sys_clk_in => clk,
|
||||
|
||||
sys_rst_out => rst_out,
|
||||
sys_clk_out => clk_out,
|
||||
sys_clk_fb => clk_fb,
|
||||
|
||||
-- User interface
|
||||
u_data_vld => u_data_vld,
|
||||
u_data_req_w => u_req_wr,
|
||||
u_data_req_r => u_req_rd,
|
||||
u_tag_in => u_tag_in,
|
||||
u_tag_rd => u_tag_rd,
|
||||
u_tag_wr => u_tag_wr,
|
||||
u_busy => u_busy,
|
||||
u_addr => u_addr,
|
||||
u_cmd => u_cmd,
|
||||
u_cmd_we => u_cmd_we,
|
||||
u_data_wr => u_data_w,
|
||||
u_data_rd => u_data_r,
|
||||
u_dm => u_dm,
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p => part_clk_p,
|
||||
sd_clk_n => part_clk_n,
|
||||
sd_cke => part_cke,
|
||||
sd_cs_n => part_cs_n,
|
||||
sd_cas_n => part_cas_n,
|
||||
sd_ras_n => part_ras_n,
|
||||
sd_we_n => part_we_n,
|
||||
sd_addr => part_addr,
|
||||
sd_ba => part_ba,
|
||||
sd_dm => part_dm,
|
||||
sd_dqs => part_dqs,
|
||||
sd_data => part_data
|
||||
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(part_data),
|
||||
dqs => std_logic_vector(part_dqs),
|
||||
addr => std_logic_vector(part_addr),
|
||||
ba => std_logic_vector(part_ba),
|
||||
clk => part_clk_p,
|
||||
clk_n => part_clk_n,
|
||||
cke => part_cke,
|
||||
cs_n => part_cs_n,
|
||||
ras_n => part_ras_n,
|
||||
cas_n => part_cas_n,
|
||||
we_n => part_we_n,
|
||||
dm => std_logic_vector(part_dm)
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
u_cmd_we <= (not cmd_fifo_empty) and write_start and (not u_busy);
|
||||
u_cmd <= cmd_fifo_out;
|
||||
u_addr <= addr_fifo_out;
|
||||
|
||||
write_fifo_re <= u_req_wr and (not write_fifo_empty);
|
||||
cmd_fifo_re <= u_cmd_we;
|
||||
u_data_w <= write_fifo_dout;
|
||||
read_fifo_re <= (not read_fifo_empty) and read_start;
|
||||
read_fifo_we <= u_data_vld;
|
||||
read_fifo_din <= u_data_r;
|
||||
|
||||
process
|
||||
begin
|
||||
|
||||
-- Write MAX_WORDS to DDR SDRAM Controller
|
||||
wait for 4*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
|
||||
wait for 4*CLK_PERIOD;
|
||||
wait until rising_edge(clk_out) and rst_out='0';
|
||||
|
||||
write_fifo_we <= '1';
|
||||
cmd_fifo_we <= '1';
|
||||
write_fifo_din <= X"01020304";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"000000";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"05060708";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"000002";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"00001111";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"000004";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"22223333";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"000006";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"44445555";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"000008";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"66667777";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"00000a";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"88889999";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"00000c";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"AAAABBBB";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"00000e";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"CCCCDDDD";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"000010";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"EEEEFFFF";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"000012";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '0';
|
||||
cmd_fifo_we <= '0';
|
||||
|
||||
-- wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- write_start <= '1';
|
||||
-- wait until rising_edge(clk_out) and write_fifo_empty='1';
|
||||
|
||||
write_fifo_we <= '1';
|
||||
cmd_fifo_we <= '1';
|
||||
write_fifo_din <= X"01234567";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '0';
|
||||
cmd_fifo_in <= UCMD_READ;
|
||||
addr_fifo_in <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"89ABCDEF";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"000016";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"11223344";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"000018";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '0';
|
||||
cmd_fifo_in <= UCMD_READ;
|
||||
addr_fifo_in <= X"000010";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"55667788";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"00001a";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"99990000";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"00001c";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '1';
|
||||
write_fifo_din <= X"AAAA5555";
|
||||
cmd_fifo_in <= UCMD_WRITE;
|
||||
addr_fifo_in <= X"000020";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '0';
|
||||
cmd_fifo_in <= UCMD_READ;
|
||||
addr_fifo_in <= X"000000";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
cmd_fifo_in <= UCMD_READ;
|
||||
addr_fifo_in <= X"000018";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
cmd_fifo_in <= UCMD_READ;
|
||||
addr_fifo_in <= X"00001A";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
cmd_fifo_in <= UCMD_READ;
|
||||
addr_fifo_in <= X"00001C";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
cmd_fifo_in <= UCMD_READ;
|
||||
addr_fifo_in <= X"000020";
|
||||
|
||||
wait until rising_edge(clk_out);
|
||||
write_fifo_we <= '0';
|
||||
cmd_fifo_we <= '0';
|
||||
|
||||
wait for 40*CLK_PERIOD;
|
||||
read_start <= '1';
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture struct;
|
||||
@@ -1,318 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
use work.utils_pkg.all;
|
||||
|
||||
entity tb_sdr_ctrl is
|
||||
end;
|
||||
|
||||
architecture struct of tb_sdr_ctrl is
|
||||
|
||||
-- Number of user data words for simulation
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant BURST_LEN : natural := 8;
|
||||
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '0';
|
||||
signal rst_out : std_logic;
|
||||
signal clk_out : std_logic;
|
||||
signal clk_fb : std_logic;
|
||||
signal part_clk_p : std_logic;
|
||||
signal part_clk_n : std_logic;
|
||||
signal part_cke : std_logic;
|
||||
signal part_cs_n : std_logic;
|
||||
signal part_we_n : std_logic;
|
||||
signal part_ras_n : std_logic;
|
||||
signal part_cas_n : std_logic;
|
||||
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal u_addr : user_addr_t := (others => '0');
|
||||
signal lin_addr : user_addr_t := (others => '0');
|
||||
signal rand_gen : unsigned(7 downto 0) := (others => '0');
|
||||
signal u_tag_in : user_tag_t := "0000";
|
||||
signal u_tag_rd : user_tag_t;
|
||||
signal u_tag_wr : user_tag_t;
|
||||
signal u_cmd : user_cmd_t := UCMD_NOP;
|
||||
signal u_cmd_we : std_logic := '0';
|
||||
signal u_busy : std_logic;
|
||||
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
|
||||
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_data_vld : std_logic;
|
||||
signal u_req_wr : std_logic;
|
||||
signal u_req_rd : std_logic;
|
||||
signal u_read_en : std_logic := '0';
|
||||
signal u_write_en : std_logic := '0';
|
||||
signal rw_null_en : std_logic := '0';
|
||||
signal u_addr_cnt_en : std_logic := '0';
|
||||
signal u_addr_load : std_logic := '0';
|
||||
signal u_addr_preset : user_addr_t := (others => '0');
|
||||
signal u_addr_end : user_addr_t := (others => '0');
|
||||
signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
|
||||
signal test_phase : test_phase_t := IDLE;
|
||||
|
||||
type u_addr_mode_t is (MONOTONIC, RANDOM);
|
||||
signal u_addr_mode : u_addr_mode_t := MONOTONIC;
|
||||
signal cycle_cnt : natural := 1;
|
||||
signal data_cnt : natural := 0;
|
||||
signal efficiency : real := 0.0;
|
||||
|
||||
begin
|
||||
|
||||
clk_fb <= part_clk_p after 1 ns;
|
||||
|
||||
-- DDR SDRAM Controller Core
|
||||
inst_sdram_ctrl : entity work.sdram_ctrl_top
|
||||
Generic map
|
||||
(
|
||||
BL => BURST_LEN,
|
||||
read_phaseshift => 0,
|
||||
f_sysclk => 100E6
|
||||
)
|
||||
Port map
|
||||
(
|
||||
|
||||
sys_rst_in => rst,
|
||||
sys_clk_in => clk,
|
||||
|
||||
sys_rst_out => rst_out,
|
||||
sys_clk_out => clk_out,
|
||||
sys_clk_fb => clk_fb,
|
||||
|
||||
-- User interface
|
||||
u_data_vld => u_data_vld,
|
||||
u_data_req_w => u_req_wr,
|
||||
u_data_req_r => u_req_rd,
|
||||
u_tag_in => u_tag_in,
|
||||
u_tag_rd => u_tag_rd,
|
||||
u_tag_wr => u_tag_wr,
|
||||
u_busy => u_busy,
|
||||
u_addr => u_addr,
|
||||
u_cmd => u_cmd,
|
||||
u_cmd_we => u_cmd_we,
|
||||
u_data_wr => u_data_w,
|
||||
u_data_rd => u_data_r,
|
||||
u_dm => u_dm,
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p => part_clk_p,
|
||||
sd_clk_n => part_clk_n,
|
||||
sd_cke => part_cke,
|
||||
sd_cs_n => part_cs_n,
|
||||
sd_cas_n => part_cas_n,
|
||||
sd_ras_n => part_ras_n,
|
||||
sd_we_n => part_we_n,
|
||||
sd_addr => part_addr,
|
||||
sd_ba => part_ba,
|
||||
sd_dm => part_dm,
|
||||
sd_dqs => part_dqs,
|
||||
sd_data => part_data
|
||||
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(part_data),
|
||||
dqs => std_logic_vector(part_dqs),
|
||||
addr => std_logic_vector(part_addr),
|
||||
ba => std_logic_vector(part_ba),
|
||||
clk => part_clk_p,
|
||||
clk_n => part_clk_n,
|
||||
cke => part_cke,
|
||||
cs_n => part_cs_n,
|
||||
ras_n => part_ras_n,
|
||||
cas_n => part_cas_n,
|
||||
we_n => part_we_n,
|
||||
dm => std_logic_vector(part_dm)
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
R_DATA_COMPARE:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_data_vld='1' then
|
||||
if u_read_en = '1' and u_tag_rd = "0000" then
|
||||
assert (ref_data = u_data_r) report "Error on read!" severity failure;
|
||||
for i in 0 to DDR_DATA_WIDTH/4-1 loop
|
||||
ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
|
||||
end loop;
|
||||
last_data := last_data + DDR_DATA_WIDTH/4;
|
||||
end if;
|
||||
elsif u_read_en = '0' and rw_null_en = '0' then
|
||||
last_data := (others => '0');
|
||||
ref_data <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
W_DATA_GEN:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_req_wr = '1' and u_tag_wr = "0000" then
|
||||
for i in 0 to DDR_DATA_WIDTH/4-1 loop
|
||||
u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
|
||||
end loop;
|
||||
last_data := last_data + DDR_DATA_WIDTH/4;
|
||||
elsif u_write_en = '0' and rw_null_en = '0' then
|
||||
last_data := (others => '0');
|
||||
u_data_w <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ADDR_GEN:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_addr_load = '1' then
|
||||
lin_addr <= u_addr_preset;
|
||||
rand_gen <= X"80";
|
||||
elsif u_addr_cnt_en = '1' then
|
||||
lin_addr <= lin_addr + BURST_LEN;
|
||||
if rand_gen(rand_gen'left) = '1' then
|
||||
rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010";
|
||||
else
|
||||
rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
performance_count:
|
||||
process(clk_out)
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_write_en = '1' or u_read_en = '1' then
|
||||
cycle_cnt <= cycle_cnt + 1;
|
||||
if u_req_wr = '1' or u_req_rd = '1' then
|
||||
data_cnt <= data_cnt + 1;
|
||||
end if;
|
||||
else
|
||||
cycle_cnt <= 1;
|
||||
data_cnt <= 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
u_tag_in <= "000" & rw_null_en;
|
||||
|
||||
efficiency <= real(data_cnt)/real(cycle_cnt);
|
||||
u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
|
||||
u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0';
|
||||
u_addr <= (rand_gen(7) and (not rw_null_en)) & lin_addr(lin_addr'left-1 downto 0);
|
||||
process
|
||||
begin
|
||||
|
||||
-- Write MAX_WORDS to DDR SDRAM Controller
|
||||
wait for 4*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
wait for 137*CLK_PERIOD;
|
||||
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- Bank 0
|
||||
test_phase <= WRITE_MULTI;
|
||||
u_addr_preset <= X"000000";
|
||||
u_addr_end <= X"010000"-BURST_LEN;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_cmd <= UCMD_READ;
|
||||
u_write_en <= '1';
|
||||
rw_null_en <= '1';
|
||||
while lin_addr /= u_addr_end loop
|
||||
u_cmd <= UCMD_READ;
|
||||
rw_null_en <= '1';
|
||||
if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
|
||||
if rand_gen(1) = '1' or rand_gen(7) = '1' then
|
||||
u_cmd <= UCMD_WRITE;
|
||||
end if;
|
||||
rw_null_en <= '0';
|
||||
end if;
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_write_en <= '0';
|
||||
rw_null_en <= '0';
|
||||
wait until rising_edge(clk_out) and u_req_wr='0';
|
||||
wait for 200*CLK_PERIOD;
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- Bank 0
|
||||
test_phase <= READ_MULTI;
|
||||
u_addr_preset <= X"000000";
|
||||
u_addr_end <= X"010000"-BURST_LEN;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_cmd <= UCMD_WRITE;
|
||||
u_read_en <= '1';
|
||||
rw_null_en <= '1';
|
||||
while lin_addr /= u_addr_end loop
|
||||
u_cmd <= UCMD_WRITE;
|
||||
rw_null_en <= '1';
|
||||
if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
|
||||
if rand_gen(1) = '1' or rand_gen(7) = '1' then
|
||||
u_cmd <= UCMD_READ;
|
||||
end if;
|
||||
rw_null_en <= '0';
|
||||
end if;
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_read_en <= '0';
|
||||
rw_null_en <= '0';
|
||||
wait until rising_edge(clk_out) and u_data_vld='0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture struct;
|
||||
@@ -1,316 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
use work.utils_pkg.all;
|
||||
|
||||
entity tb_sdr_ctrl is
|
||||
end;
|
||||
|
||||
architecture struct of tb_sdr_ctrl is
|
||||
|
||||
-- Number of user data words for simulation
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant BURST_LEN : natural := 8;
|
||||
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '0';
|
||||
signal rst_out : std_logic;
|
||||
signal clk_out : std_logic;
|
||||
signal clk_fb : std_logic;
|
||||
signal part_clk_p : std_logic;
|
||||
signal part_clk_n : std_logic;
|
||||
signal part_cke : std_logic;
|
||||
signal part_cs_n : std_logic;
|
||||
signal part_we_n : std_logic;
|
||||
signal part_ras_n : std_logic;
|
||||
signal part_cas_n : std_logic;
|
||||
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal u_addr : user_addr_t := (others => '0');
|
||||
signal lin_addr : user_addr_t := (others => '0');
|
||||
signal rand_gen : unsigned(7 downto 0) := (others => '0');
|
||||
signal u_tag_in : user_tag_t := "0000";
|
||||
signal u_tag_rd : user_tag_t;
|
||||
signal u_tag_wr : user_tag_t;
|
||||
signal u_cmd : user_cmd_t := UCMD_NOP;
|
||||
signal u_cmd_we : std_logic := '0';
|
||||
signal u_busy : std_logic;
|
||||
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
|
||||
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_data_vld : std_logic;
|
||||
signal u_req_wr : std_logic;
|
||||
signal u_req_rd : std_logic;
|
||||
signal u_read_en : std_logic := '0';
|
||||
signal u_write_en : std_logic := '0';
|
||||
signal rw_null_en : std_logic := '0';
|
||||
signal u_addr_cnt_en : std_logic := '0';
|
||||
signal u_addr_load : std_logic := '0';
|
||||
signal u_addr_preset : user_addr_t := (others => '0');
|
||||
signal u_addr_end : user_addr_t := (others => '0');
|
||||
signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
|
||||
signal test_phase : test_phase_t := IDLE;
|
||||
|
||||
type u_addr_mode_t is (MONOTONIC, RANDOM);
|
||||
signal u_addr_mode : u_addr_mode_t := MONOTONIC;
|
||||
signal cycle_cnt : natural := 1;
|
||||
signal data_cnt : natural := 0;
|
||||
signal efficiency : real := 0.0;
|
||||
|
||||
begin
|
||||
|
||||
clk_fb <= part_clk_p after 1 ns;
|
||||
|
||||
-- DDR SDRAM Controller Core
|
||||
inst_sdram_ctrl : entity work.sdram_ctrl_top
|
||||
Generic map
|
||||
(
|
||||
BL => BURST_LEN,
|
||||
read_phaseshift => 0,
|
||||
f_sysclk => 100E6
|
||||
)
|
||||
Port map
|
||||
(
|
||||
|
||||
sys_rst_in => rst,
|
||||
sys_clk_in => clk,
|
||||
|
||||
sys_rst_out => rst_out,
|
||||
sys_clk_out => clk_out,
|
||||
sys_clk_fb => clk_fb,
|
||||
|
||||
-- User interface
|
||||
u_data_vld => u_data_vld,
|
||||
u_data_req_w => u_req_wr,
|
||||
u_data_req_r => u_req_rd,
|
||||
u_tag_in => u_tag_in,
|
||||
u_tag_rd => u_tag_rd,
|
||||
u_tag_wr => u_tag_wr,
|
||||
u_busy => u_busy,
|
||||
u_addr => u_addr,
|
||||
u_cmd => u_cmd,
|
||||
u_cmd_we => u_cmd_we,
|
||||
u_data_wr => u_data_w,
|
||||
u_data_rd => u_data_r,
|
||||
u_dm => u_dm,
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p => part_clk_p,
|
||||
sd_clk_n => part_clk_n,
|
||||
sd_cke => part_cke,
|
||||
sd_cs_n => part_cs_n,
|
||||
sd_cas_n => part_cas_n,
|
||||
sd_ras_n => part_ras_n,
|
||||
sd_we_n => part_we_n,
|
||||
sd_addr => part_addr,
|
||||
sd_ba => part_ba,
|
||||
sd_dm => part_dm,
|
||||
sd_dqs => part_dqs,
|
||||
sd_data => part_data
|
||||
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(part_data),
|
||||
dqs => std_logic_vector(part_dqs),
|
||||
addr => std_logic_vector(part_addr),
|
||||
ba => std_logic_vector(part_ba),
|
||||
clk => part_clk_p,
|
||||
clk_n => part_clk_n,
|
||||
cke => part_cke,
|
||||
cs_n => part_cs_n,
|
||||
ras_n => part_ras_n,
|
||||
cas_n => part_cas_n,
|
||||
we_n => part_we_n,
|
||||
dm => std_logic_vector(part_dm)
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
R_DATA_COMPARE:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_data_vld='1' then
|
||||
if u_read_en = '1' and u_tag_rd = "0000" then
|
||||
assert (ref_data = u_data_r) report "Error on read!" severity failure;
|
||||
for i in 0 to DDR_DATA_WIDTH/4-1 loop
|
||||
ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
|
||||
end loop;
|
||||
last_data := last_data + DDR_DATA_WIDTH/4;
|
||||
end if;
|
||||
elsif u_read_en = '0' and rw_null_en = '0' then
|
||||
last_data := (others => '0');
|
||||
ref_data <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
W_DATA_GEN:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_req_wr = '1' and u_tag_wr = "0000" then
|
||||
for i in 0 to DDR_DATA_WIDTH/4-1 loop
|
||||
u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
|
||||
end loop;
|
||||
last_data := last_data + DDR_DATA_WIDTH/4;
|
||||
elsif u_write_en = '0' and rw_null_en = '0' then
|
||||
last_data := (others => '0');
|
||||
u_data_w <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ADDR_GEN:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_addr_load = '1' then
|
||||
lin_addr <= u_addr_preset;
|
||||
rand_gen <= X"80";
|
||||
elsif u_addr_cnt_en = '1' then
|
||||
lin_addr <= lin_addr + BURST_LEN;
|
||||
if rand_gen(rand_gen'left) = '1' then
|
||||
rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010";
|
||||
else
|
||||
rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
performance_count:
|
||||
process(clk_out)
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_write_en = '1' or u_read_en = '1' then
|
||||
cycle_cnt <= cycle_cnt + 1;
|
||||
if u_req_wr = '1' or u_req_rd = '1' then
|
||||
data_cnt <= data_cnt + 1;
|
||||
end if;
|
||||
else
|
||||
cycle_cnt <= 1;
|
||||
data_cnt <= 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
u_tag_in <= "000" & rw_null_en;
|
||||
|
||||
efficiency <= real(data_cnt)/real(cycle_cnt);
|
||||
u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
|
||||
u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0';
|
||||
u_addr <= (rand_gen(7) and (rw_null_en)) & lin_addr(lin_addr'left-1 downto 0);
|
||||
process
|
||||
begin
|
||||
|
||||
-- Write MAX_WORDS to DDR SDRAM Controller
|
||||
wait for 4*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
wait for 137*CLK_PERIOD;
|
||||
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- Bank 0
|
||||
test_phase <= WRITE_MULTI;
|
||||
u_addr_preset <= X"000000";
|
||||
u_addr_end <= X"010000"-BURST_LEN;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_cmd <= UCMD_WRITE;
|
||||
u_write_en <= '1';
|
||||
while lin_addr /= u_addr_end loop
|
||||
u_cmd <= UCMD_WRITE;
|
||||
rw_null_en <= '0';
|
||||
if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
|
||||
if rand_gen(1) = '1' or rand_gen(7) = '1' then
|
||||
u_cmd <= UCMD_READ;
|
||||
end if;
|
||||
rw_null_en <= '1';
|
||||
end if;
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_write_en <= '0';
|
||||
rw_null_en <= '0';
|
||||
wait until rising_edge(clk_out) and u_req_wr='0';
|
||||
wait for 200*CLK_PERIOD;
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- Bank 0
|
||||
test_phase <= READ_MULTI;
|
||||
u_addr_preset <= X"000000";
|
||||
u_addr_end <= X"010000"-BURST_LEN;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_cmd <= UCMD_READ;
|
||||
u_read_en <= '1';
|
||||
while lin_addr /= u_addr_end loop
|
||||
u_cmd <= UCMD_READ;
|
||||
rw_null_en <= '0';
|
||||
if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
|
||||
if rand_gen(1) = '1' or rand_gen(7) = '1' then
|
||||
u_cmd <= UCMD_WRITE;
|
||||
end if;
|
||||
rw_null_en <= '1';
|
||||
end if;
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_read_en <= '0';
|
||||
rw_null_en <= '0';
|
||||
wait until rising_edge(clk_out) and u_data_vld='0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture struct;
|
||||
@@ -1,315 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
use work.utils_pkg.all;
|
||||
|
||||
entity tb_sdr_ctrl is
|
||||
end;
|
||||
|
||||
architecture struct of tb_sdr_ctrl is
|
||||
|
||||
-- Number of user data words for simulation
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant BURST_LEN : natural := 8;
|
||||
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '0';
|
||||
signal rst_out : std_logic;
|
||||
signal clk_out : std_logic;
|
||||
signal clk_fb : std_logic;
|
||||
signal part_clk_p : std_logic;
|
||||
signal part_clk_n : std_logic;
|
||||
signal part_cke : std_logic;
|
||||
signal part_cs_n : std_logic;
|
||||
signal part_we_n : std_logic;
|
||||
signal part_ras_n : std_logic;
|
||||
signal part_cas_n : std_logic;
|
||||
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal u_addr : user_addr_t := (others => '0');
|
||||
signal u_tag_in : user_tag_t := "0000";
|
||||
signal u_tag_rd : user_tag_t;
|
||||
signal u_tag_wr : user_tag_t;
|
||||
signal u_cmd : user_cmd_t := UCMD_NOP;
|
||||
signal u_cmd_we : std_logic := '0';
|
||||
signal u_busy : std_logic;
|
||||
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
|
||||
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_data_vld : std_logic;
|
||||
signal u_req_wr : std_logic;
|
||||
signal u_req_rd : std_logic;
|
||||
signal u_read_en : std_logic := '0';
|
||||
signal u_write_en : std_logic := '0';
|
||||
signal u_addr_cnt_en : std_logic := '0';
|
||||
signal u_addr_load : std_logic := '0';
|
||||
signal u_addr_preset : user_addr_t := (others => '0');
|
||||
signal u_addr_end : user_addr_t := (others => '0');
|
||||
signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
|
||||
signal test_phase : test_phase_t := IDLE;
|
||||
|
||||
type u_addr_mode_t is (MONOTONIC, RANDOM);
|
||||
signal u_addr_mode : u_addr_mode_t := MONOTONIC;
|
||||
signal cycle_cnt : natural := 1;
|
||||
signal data_cnt : natural := 0;
|
||||
signal efficiency : real := 0.0;
|
||||
|
||||
begin
|
||||
|
||||
clk_fb <= part_clk_p after 1 ns;
|
||||
|
||||
-- DDR SDRAM Controller Core
|
||||
inst_sdram_ctrl : entity work.sdram_ctrl_top
|
||||
Generic map
|
||||
(
|
||||
BL => BURST_LEN,
|
||||
read_phaseshift => 0,
|
||||
f_sysclk => 100E6
|
||||
)
|
||||
Port map
|
||||
(
|
||||
|
||||
sys_rst_in => rst,
|
||||
sys_clk_in => clk,
|
||||
|
||||
sys_rst_out => rst_out,
|
||||
sys_clk_out => clk_out,
|
||||
sys_clk_fb => clk_fb,
|
||||
|
||||
-- User interface
|
||||
u_data_vld => u_data_vld,
|
||||
u_data_req_w => u_req_wr,
|
||||
u_data_req_r => u_req_rd,
|
||||
u_tag_in => u_tag_in,
|
||||
u_tag_rd => u_tag_rd,
|
||||
u_tag_wr => u_tag_wr,
|
||||
u_busy => u_busy,
|
||||
u_addr => u_addr,
|
||||
u_cmd => u_cmd,
|
||||
u_cmd_we => u_cmd_we,
|
||||
u_data_wr => u_data_w,
|
||||
u_data_rd => u_data_r,
|
||||
u_dm => u_dm,
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p => part_clk_p,
|
||||
sd_clk_n => part_clk_n,
|
||||
sd_cke => part_cke,
|
||||
sd_cs_n => part_cs_n,
|
||||
sd_cas_n => part_cas_n,
|
||||
sd_ras_n => part_ras_n,
|
||||
sd_we_n => part_we_n,
|
||||
sd_addr => part_addr,
|
||||
sd_ba => part_ba,
|
||||
sd_dm => part_dm,
|
||||
sd_dqs => part_dqs,
|
||||
sd_data => part_data
|
||||
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(part_data),
|
||||
dqs => std_logic_vector(part_dqs),
|
||||
addr => std_logic_vector(part_addr),
|
||||
ba => std_logic_vector(part_ba),
|
||||
clk => part_clk_p,
|
||||
clk_n => part_clk_n,
|
||||
cke => part_cke,
|
||||
cs_n => part_cs_n,
|
||||
ras_n => part_ras_n,
|
||||
cas_n => part_cas_n,
|
||||
we_n => part_we_n,
|
||||
dm => std_logic_vector(part_dm)
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
R_DATA_COMPARE:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_data_vld='1' then
|
||||
if u_read_en = '1' then
|
||||
assert (ref_data = u_data_r) report "Error on read!" severity failure;
|
||||
end if;
|
||||
for i in 0 to DDR_DATA_WIDTH/4-1 loop
|
||||
ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
|
||||
end loop;
|
||||
last_data := last_data + DDR_DATA_WIDTH/4;
|
||||
elsif u_read_en = '0' then
|
||||
last_data := (others => '0');
|
||||
ref_data <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
W_DATA_GEN:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_req_wr = '1' then
|
||||
for i in 0 to DDR_DATA_WIDTH/4-1 loop
|
||||
u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
|
||||
end loop;
|
||||
last_data := last_data + DDR_DATA_WIDTH/4;
|
||||
elsif u_write_en = '0' then
|
||||
last_data := (others => '0');
|
||||
u_data_w <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ADDR_GEN:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_addr_load = '1' then
|
||||
u_addr <= u_addr_preset;
|
||||
elsif u_addr_cnt_en = '1' then
|
||||
if u_addr_mode = MONOTONIC then
|
||||
u_addr <= u_addr + BURST_LEN;
|
||||
else
|
||||
if u_addr(u_addr'left) = '1' then
|
||||
if BURST_LEN = 2 then
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
|
||||
elsif BURST_LEN = 4 then
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
|
||||
elsif BURST_LEN = 8 then
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
|
||||
end if;
|
||||
else
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
performance_count:
|
||||
process(clk_out)
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_write_en = '1' or u_read_en = '1' then
|
||||
cycle_cnt <= cycle_cnt + 1;
|
||||
if u_req_wr = '1' or u_req_rd = '1' then
|
||||
data_cnt <= data_cnt + 1;
|
||||
end if;
|
||||
else
|
||||
cycle_cnt <= 1;
|
||||
data_cnt <= 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
|
||||
|
||||
efficiency <= real(data_cnt)/real(cycle_cnt);
|
||||
u_cmd_we <= (u_write_en or u_read_en) and (not u_busy);
|
||||
u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
|
||||
|
||||
process
|
||||
begin
|
||||
|
||||
-- Write MAX_WORDS to DDR SDRAM Controller
|
||||
wait for 4*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
wait for 137*CLK_PERIOD;
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- Bank 0
|
||||
test_phase <= WRITE_MULTI;
|
||||
u_addr_preset <= X"800000";
|
||||
if BURST_LEN = 2 then
|
||||
u_addr_end <= X"5E2330";
|
||||
elsif BURST_LEN = 4 then
|
||||
u_addr_end <= X"7DEDD0";
|
||||
elsif BURST_LEN = 8 then
|
||||
u_addr_end <= X"5666B0";
|
||||
end if;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_mode <= RANDOM;
|
||||
u_cmd <= UCMD_WRITE;
|
||||
u_write_en <= '1';
|
||||
while u_addr /= u_addr_end loop
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_write_en <= '0';
|
||||
wait until rising_edge(clk_out) and u_req_wr='0';
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- Bank 0
|
||||
test_phase <= READ_MULTI;
|
||||
u_addr_preset <= X"800000";
|
||||
if BURST_LEN = 2 then
|
||||
u_addr_end <= X"5E2330";
|
||||
elsif BURST_LEN = 4 then
|
||||
u_addr_end <= X"7DEDD0";
|
||||
elsif BURST_LEN = 8 then
|
||||
u_addr_end <= X"5666B0";
|
||||
end if;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_mode <= RANDOM;
|
||||
u_cmd <= UCMD_READ;
|
||||
u_read_en <= '1';
|
||||
while u_addr /= u_addr_end loop
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_read_en <= '0';
|
||||
wait until rising_edge(clk_out) and u_data_vld='0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture struct;
|
||||
@@ -1,329 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
use work.utils_pkg.all;
|
||||
|
||||
entity tb_sdr_ctrl is
|
||||
end;
|
||||
|
||||
architecture struct of tb_sdr_ctrl is
|
||||
|
||||
-- Number of user data words for simulation
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant BURST_LEN : natural := 2;
|
||||
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '0';
|
||||
signal rst_out : std_logic;
|
||||
signal clk_out : std_logic;
|
||||
signal clk_fb : std_logic;
|
||||
signal part_clk_p : std_logic;
|
||||
signal part_clk_n : std_logic;
|
||||
signal part_cke : std_logic;
|
||||
signal part_cs_n : std_logic;
|
||||
signal part_we_n : std_logic;
|
||||
signal part_ras_n : std_logic;
|
||||
signal part_cas_n : std_logic;
|
||||
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal u_addr : user_addr_t := (others => '0');
|
||||
signal u_tag_in : user_tag_t := "0000";
|
||||
signal u_tag_rd : user_tag_t;
|
||||
signal u_tag_wr : user_tag_t;
|
||||
signal u_cmd : user_cmd_t := UCMD_NOP;
|
||||
signal u_cmd_we : std_logic := '0';
|
||||
signal u_busy : std_logic;
|
||||
signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
|
||||
signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal u_data_vld : std_logic;
|
||||
signal u_req_wr : std_logic;
|
||||
signal u_req_rd : std_logic;
|
||||
signal u_read_en : std_logic := '0';
|
||||
signal u_write_en : std_logic := '0';
|
||||
signal rw_null_en : std_logic := '0';
|
||||
signal u_addr_cnt_en : std_logic := '0';
|
||||
signal u_addr_load : std_logic := '0';
|
||||
signal u_addr_preset : user_addr_t := (others => '0');
|
||||
signal u_addr_end : user_addr_t := (others => '0');
|
||||
signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
|
||||
signal test_phase : test_phase_t := IDLE;
|
||||
|
||||
type u_addr_mode_t is (MONOTONIC, RANDOM);
|
||||
signal u_addr_mode : u_addr_mode_t := MONOTONIC;
|
||||
signal cycle_cnt : natural := 1;
|
||||
signal data_cnt : natural := 0;
|
||||
signal efficiency : real := 0.0;
|
||||
|
||||
begin
|
||||
|
||||
clk_fb <= part_clk_p after 1 ns;
|
||||
|
||||
-- DDR SDRAM Controller Core
|
||||
inst_sdram_ctrl : entity work.sdram_ctrl_top
|
||||
Generic map
|
||||
(
|
||||
BL => BURST_LEN,
|
||||
read_phaseshift => 0,
|
||||
f_sysclk => 100E6
|
||||
)
|
||||
Port map
|
||||
(
|
||||
|
||||
sys_rst_in => rst,
|
||||
sys_clk_in => clk,
|
||||
|
||||
sys_rst_out => rst_out,
|
||||
sys_clk_out => clk_out,
|
||||
sys_clk_fb => clk_fb,
|
||||
|
||||
-- User interface
|
||||
u_data_vld => u_data_vld,
|
||||
u_data_req_w => u_req_wr,
|
||||
u_data_req_r => u_req_rd,
|
||||
u_tag_in => u_tag_in,
|
||||
u_tag_rd => u_tag_rd,
|
||||
u_tag_wr => u_tag_wr,
|
||||
u_busy => u_busy,
|
||||
u_addr => u_addr,
|
||||
u_cmd => u_cmd,
|
||||
u_cmd_we => u_cmd_we,
|
||||
u_data_wr => u_data_w,
|
||||
u_data_rd => u_data_r,
|
||||
u_dm => u_dm,
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p => part_clk_p,
|
||||
sd_clk_n => part_clk_n,
|
||||
sd_cke => part_cke,
|
||||
sd_cs_n => part_cs_n,
|
||||
sd_cas_n => part_cas_n,
|
||||
sd_ras_n => part_ras_n,
|
||||
sd_we_n => part_we_n,
|
||||
sd_addr => part_addr,
|
||||
sd_ba => part_ba,
|
||||
sd_dm => part_dm,
|
||||
sd_dqs => part_dqs,
|
||||
sd_data => part_data
|
||||
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(part_data),
|
||||
dqs => std_logic_vector(part_dqs),
|
||||
addr => std_logic_vector(part_addr),
|
||||
ba => std_logic_vector(part_ba),
|
||||
clk => part_clk_p,
|
||||
clk_n => part_clk_n,
|
||||
cke => part_cke,
|
||||
cs_n => part_cs_n,
|
||||
ras_n => part_ras_n,
|
||||
cas_n => part_cas_n,
|
||||
we_n => part_we_n,
|
||||
dm => std_logic_vector(part_dm)
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
R_DATA_COMPARE:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_data_vld='1' then
|
||||
if u_read_en = '1' then
|
||||
assert (ref_data = u_data_r) report "Error on read!" severity failure;
|
||||
end if;
|
||||
for i in 0 to DDR_DATA_WIDTH/4-1 loop
|
||||
ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
|
||||
end loop;
|
||||
last_data := last_data + DDR_DATA_WIDTH/4;
|
||||
elsif u_read_en = '0' and rw_null_en = '0' then
|
||||
last_data := (others => '0');
|
||||
ref_data <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
W_DATA_GEN:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_req_wr = '1' then
|
||||
for i in 0 to DDR_DATA_WIDTH/4-1 loop
|
||||
u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
|
||||
end loop;
|
||||
last_data := last_data + DDR_DATA_WIDTH/4;
|
||||
elsif u_write_en = '0' and rw_null_en = '0' then
|
||||
last_data := (others => '0');
|
||||
u_data_w <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ADDR_GEN:
|
||||
process(clk_out)
|
||||
variable last_data : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_addr_load = '1' then
|
||||
u_addr <= u_addr_preset;
|
||||
elsif u_addr_cnt_en = '1' then
|
||||
if u_addr_mode = MONOTONIC then
|
||||
u_addr <= u_addr + BURST_LEN;
|
||||
else
|
||||
if u_addr(u_addr'left) = '1' then
|
||||
if BURST_LEN = 2 then
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
|
||||
elsif BURST_LEN = 4 then
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
|
||||
elsif BURST_LEN = 8 then
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
|
||||
end if;
|
||||
else
|
||||
u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
performance_count:
|
||||
process(clk_out)
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if u_write_en = '1' or u_read_en = '1' then
|
||||
cycle_cnt <= cycle_cnt + 1;
|
||||
if u_req_wr = '1' or u_req_rd = '1' then
|
||||
data_cnt <= data_cnt + 1;
|
||||
end if;
|
||||
else
|
||||
cycle_cnt <= 1;
|
||||
data_cnt <= 0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
|
||||
|
||||
efficiency <= real(data_cnt)/real(cycle_cnt);
|
||||
u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
|
||||
u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
|
||||
|
||||
process
|
||||
begin
|
||||
|
||||
-- Write MAX_WORDS to DDR SDRAM Controller
|
||||
wait for 4*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
wait for 137*CLK_PERIOD;
|
||||
|
||||
-- Bank 0
|
||||
test_phase <= WRITE_MULTI;
|
||||
u_addr_preset <= X"800000";
|
||||
if BURST_LEN = 2 then
|
||||
u_addr_end <= X"646808";
|
||||
elsif BURST_LEN = 4 then
|
||||
u_addr_end <= X"7DEDD0";
|
||||
elsif BURST_LEN = 8 then
|
||||
u_addr_end <= X"5666B0";
|
||||
end if;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_mode <= RANDOM;
|
||||
while u_addr /= u_addr_end loop
|
||||
u_cmd <= UCMD_WRITE;
|
||||
u_write_en <= '1';
|
||||
rw_null_en <= '0';
|
||||
if u_addr(20) = '0' then
|
||||
u_cmd <= UCMD_READ;
|
||||
u_write_en <= '0';
|
||||
rw_null_en <= '1';
|
||||
end if;
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_write_en <= '0';
|
||||
rw_null_en <= '0';
|
||||
wait for 200*CLK_PERIOD;
|
||||
|
||||
wait until rising_edge(clk_out) and u_busy='0';
|
||||
-- Bank 0
|
||||
test_phase <= READ_MULTI;
|
||||
u_addr_preset <= X"800000";
|
||||
if BURST_LEN = 2 then
|
||||
u_addr_end <= X"646808";
|
||||
elsif BURST_LEN = 4 then
|
||||
u_addr_end <= X"7DEDD0";
|
||||
elsif BURST_LEN = 8 then
|
||||
u_addr_end <= X"5666B0";
|
||||
end if;
|
||||
u_addr_load <= '1';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_load <= '0';
|
||||
wait until rising_edge(clk_out);
|
||||
u_addr_mode <= RANDOM;
|
||||
while u_addr /= u_addr_end loop
|
||||
u_cmd <= UCMD_READ;
|
||||
u_read_en <= '1';
|
||||
rw_null_en <= '0';
|
||||
if u_addr(20) = '0' then
|
||||
u_cmd <= UCMD_WRITE;
|
||||
u_read_en <= '0';
|
||||
rw_null_en <= '1';
|
||||
end if;
|
||||
wait until rising_edge(clk_out);
|
||||
end loop;
|
||||
u_read_en <= '0';
|
||||
rw_null_en <= '0';
|
||||
wait until rising_edge(clk_out) and u_data_vld='0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture struct;
|
||||
@@ -1,385 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.fifo_ctrl_pkg.all;
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
|
||||
entity tb_sdram_ctrl_frontend is
|
||||
end;
|
||||
|
||||
architecture struct of tb_sdram_ctrl_frontend is
|
||||
|
||||
-- Number of user data words for simulation
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant BURST_LEN : natural := 2;
|
||||
|
||||
signal rst : std_logic := '1';
|
||||
signal clk : std_logic := '0';
|
||||
signal rst_out : std_logic;
|
||||
signal clk_out : std_logic;
|
||||
signal clk_fb : std_logic;
|
||||
signal part_clk_p : std_logic;
|
||||
signal part_clk_n : std_logic;
|
||||
signal part_cke : std_logic;
|
||||
signal part_cs_n : std_logic;
|
||||
signal part_we_n : std_logic;
|
||||
signal part_ras_n : std_logic;
|
||||
signal part_cas_n : std_logic;
|
||||
signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal addr : user_addr_t := (others => '0');
|
||||
signal r_wn : std_logic := '0';
|
||||
signal en : std_logic := '0';
|
||||
signal busy : std_logic;
|
||||
signal din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal be : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "1111";
|
||||
signal dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal dout_vld : std_logic;
|
||||
signal dout_re : std_logic;
|
||||
signal dout_reg : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
clk_fb <= part_clk_p after 1 ns;
|
||||
|
||||
-- DDR SDRAM Controller Core
|
||||
inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend
|
||||
Generic map
|
||||
(
|
||||
BL => BURST_LEN,
|
||||
read_phaseshift => 0,
|
||||
f_sysclk => 100E6,
|
||||
fifo_depth => 4
|
||||
)
|
||||
Port map
|
||||
(
|
||||
|
||||
sys_rst_in => rst,
|
||||
sys_clk_in => clk,
|
||||
|
||||
sys_rst_out => rst_out,
|
||||
sys_clk_out => clk_out,
|
||||
sys_clk_fb => clk_fb,
|
||||
|
||||
busy => busy,
|
||||
en => en,
|
||||
r_wn => r_wn,
|
||||
be => be,
|
||||
addr => addr,
|
||||
din => din,
|
||||
dout => dout,
|
||||
dout_re => dout_re,
|
||||
dout_vld => dout_vld,
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p => part_clk_p,
|
||||
sd_clk_n => part_clk_n,
|
||||
sd_cke => part_cke,
|
||||
sd_cs_n => part_cs_n,
|
||||
sd_cas_n => part_cas_n,
|
||||
sd_ras_n => part_ras_n,
|
||||
sd_we_n => part_we_n,
|
||||
sd_addr => part_addr,
|
||||
sd_ba => part_ba,
|
||||
sd_dm => part_dm,
|
||||
sd_dqs => part_dqs,
|
||||
sd_data => part_data
|
||||
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(part_data),
|
||||
dqs => std_logic_vector(part_dqs),
|
||||
addr => std_logic_vector(part_addr),
|
||||
ba => std_logic_vector(part_ba),
|
||||
clk => part_clk_p,
|
||||
clk_n => part_clk_n,
|
||||
cke => part_cke,
|
||||
cs_n => part_cs_n,
|
||||
ras_n => part_ras_n,
|
||||
cas_n => part_cas_n,
|
||||
we_n => part_we_n,
|
||||
dm => std_logic_vector(part_dm)
|
||||
);
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
clk <= not clk;
|
||||
end process;
|
||||
|
||||
read_register:
|
||||
process(clk_out)
|
||||
begin
|
||||
if rising_edge(clk_out) then
|
||||
if dout_vld = '1' then
|
||||
dout_reg <= dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------------------------------
|
||||
dout_re <= dout_vld;
|
||||
|
||||
process
|
||||
begin
|
||||
|
||||
-- Write MAX_WORDS to DDR SDRAM Controller
|
||||
wait for 4*CLK_PERIOD;
|
||||
rst <= '0';
|
||||
|
||||
wait for 4*CLK_PERIOD;
|
||||
wait until rising_edge(clk_out) and rst_out='0';
|
||||
|
||||
for i in 0 to 999 loop
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= to_unsigned(i, 32);
|
||||
addr <= to_unsigned(2*i, 24);
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
end loop;
|
||||
|
||||
for i in 0 to 999 loop
|
||||
en <= '1';
|
||||
r_wn <= '1';
|
||||
din <= to_unsigned(i, 32);
|
||||
addr <= to_unsigned(2*i, 24);
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
end loop;
|
||||
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"01020304";
|
||||
addr <= X"000000";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"05060708";
|
||||
addr <= X"000002";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"00001111";
|
||||
addr <= X"000004";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"22223333";
|
||||
addr <= X"000006";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"44445555";
|
||||
addr <= X"000008";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"66667777";
|
||||
addr <= X"00000a";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"88889999";
|
||||
addr <= X"00000c";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"AAAABBBB";
|
||||
addr <= X"00000e";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"CCCCDDDD";
|
||||
addr <= X"000010";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"EEEEFFFF";
|
||||
addr <= X"000012";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"FFFFFFFF";
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '1';
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"87CCCCCC";
|
||||
be <= "1000";
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '1';
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"CC65CCCC";
|
||||
be <= "0100";
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '1';
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"CCCC43CC";
|
||||
be <= "0010";
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '1';
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"89ABCDEF";
|
||||
addr <= X"000016";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"CCCCCC21";
|
||||
be <= "0001";
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '1';
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"55555555";
|
||||
be <= "1010";
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '1';
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"AAAAAAAA";
|
||||
be <= "0101";
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '1';
|
||||
addr <= X"000014";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
be <= "1111";
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"11223344";
|
||||
addr <= X"000018";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
r_wn <= '1';
|
||||
addr <= X"000010";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"55667788";
|
||||
addr <= X"00001a";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"99990000";
|
||||
addr <= X"00001c";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '1';
|
||||
r_wn <= '0';
|
||||
din <= X"AAAA5555";
|
||||
addr <= X"000020";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
r_wn <= '1';
|
||||
addr <= X"000000";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
r_wn <= '1';
|
||||
addr <= X"000018";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
r_wn <= '1';
|
||||
addr <= X"00001A";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
r_wn <= '1';
|
||||
addr <= X"00001C";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
r_wn <= '1';
|
||||
addr <= X"000020";
|
||||
|
||||
wait until rising_edge(clk_out) and busy = '0';
|
||||
en <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture struct;
|
||||
@@ -1,546 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11:25:45 10/15/05
|
||||
-- Design Name:
|
||||
-- Module Name: char_gen - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.vga_types.all;
|
||||
|
||||
entity char_gen is
|
||||
Generic
|
||||
(
|
||||
tsvga : vga_timespec_t := ts_vga_800_600_72;
|
||||
|
||||
-- User supplied parameters
|
||||
CHARACTER_SCALE : natural := 1;
|
||||
CHAR_ROM_SIZE_X : natural := 8; -- Pixels
|
||||
CHAR_ROM_SIZE_Y : natural := 16; -- Pixels
|
||||
CHAR_ROM_DEPTH : natural := 256; -- Chars
|
||||
MAX_CHAR_PER_LINE : natural := 32; -- Chars
|
||||
MAX_LINE_PER_FRAME : natural := 16; -- Chars
|
||||
CHAR_SPACING_X : natural := 0; -- Pixels
|
||||
CHAR_SPACING_Y : natural := 0; -- Pixels
|
||||
SCREEN_OFFSET_X : natural := 16; -- Pixels
|
||||
SCREEN_OFFSET_Y : natural := 16 -- Pixels
|
||||
);
|
||||
Port
|
||||
(
|
||||
-- System signals
|
||||
rst : in std_logic;
|
||||
vga_clk : in std_logic;
|
||||
sys_clk : in std_logic;
|
||||
ce : in std_logic;
|
||||
frame_pulse : in std_logic;
|
||||
|
||||
|
||||
-- Host Signals
|
||||
clr_screen : in std_logic;
|
||||
clr_line : in std_logic;
|
||||
ascii_data : in unsigned(7 downto 0);
|
||||
ascii_data_we : in std_logic;
|
||||
ascii_posy_we : in std_logic;
|
||||
ascii_posx_we : in std_logic;
|
||||
ready : out std_logic;
|
||||
|
||||
-- Control signals
|
||||
pos_x : in natural range 0 to tsvga.ts_h.ncyc_scan-1;
|
||||
pos_y : in natural range 0 to tsvga.ts_v.ncyc_scan-1;
|
||||
|
||||
-- Output
|
||||
char_draw_en : out std_logic
|
||||
|
||||
);
|
||||
end char_gen;
|
||||
|
||||
architecture Behavioral of char_gen is
|
||||
|
||||
constant A_RAM_ADDR_WIDTH : integer := 12;
|
||||
constant A_RAM_DATA_WIDTH : integer := 8;
|
||||
|
||||
type offset_rom_t is array (0 to MAX_LINE_PER_FRAME-1) of unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
|
||||
|
||||
|
||||
|
||||
function gen_offset_rom(num_char_per_line, num_lines : natural) return offset_rom_t is
|
||||
variable result : offset_rom_t;
|
||||
|
||||
variable offset : unsigned(A_RAM_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
begin
|
||||
for i in 0 to num_lines-1 loop
|
||||
result(i) := offset;
|
||||
offset := offset + to_unsigned(num_char_per_line, A_RAM_ADDR_WIDTH-1);
|
||||
end loop;
|
||||
return result;
|
||||
end gen_offset_rom;
|
||||
|
||||
constant offset_rom : offset_rom_t := gen_offset_rom(MAX_CHAR_PER_LINE, MAX_LINE_PER_FRAME);
|
||||
|
||||
-- Calculated parameters
|
||||
type cg_state_t is (cg_init, cg_ready, cg_clr_line, cg_clr_screen);
|
||||
signal s, sn : cg_state_t;
|
||||
|
||||
constant CELL_SIZE_X : natural := (CHAR_ROM_SIZE_X+CHAR_SPACING_X)*CHARACTER_SCALE;
|
||||
constant CELL_SIZE_Y : natural := (CHAR_ROM_SIZE_Y+CHAR_SPACING_Y)*CHARACTER_SCALE;
|
||||
constant CHAR_SIZE_X : natural := CHAR_ROM_SIZE_X*CHARACTER_SCALE;
|
||||
constant CHAR_SIZE_Y : natural := CHAR_ROM_SIZE_Y*CHARACTER_SCALE;
|
||||
|
||||
signal line_offset : natural range 0 to MAX_LINE_PER_FRAME-1;
|
||||
signal cell_x_cnt : natural range 0 to MAX_CHAR_PER_LINE-1;
|
||||
signal cell_y_cnt : natural range 0 to MAX_LINE_PER_FRAME-1;
|
||||
signal char_x_cnt : natural range 0 to CELL_SIZE_X-1;
|
||||
signal char_y_cnt : natural range 0 to CELL_SIZE_Y-1;
|
||||
signal char_rom_row : unsigned(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto 0);
|
||||
signal char_rom_addr : unsigned(NextExpBaseTwo(CHAR_ROM_DEPTH*CHAR_ROM_SIZE_Y)-1 downto 0);
|
||||
signal char_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0);
|
||||
signal char_reg : unsigned((CHARACTER_SCALE*CHAR_ROM_SIZE_X)-1 downto 0);
|
||||
|
||||
signal a_addr_rd : unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
|
||||
signal a_addr_wr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
|
||||
signal a_data_rd : unsigned(A_RAM_DATA_WIDTH-1 downto 0);
|
||||
signal a_data_wr : unsigned(A_RAM_DATA_WIDTH-1 downto 0);
|
||||
signal a_ram_we : std_logic;
|
||||
signal a_cnt : natural range 0 to 2**A_RAM_ADDR_WIDTH-1;
|
||||
signal a_cnt_rst : std_logic;
|
||||
signal a_cnt_en : std_logic;
|
||||
signal csr_posx_reg : natural range 0 to MAX_CHAR_PER_LINE-1;
|
||||
signal csr_posy_reg : natural range 0 to MAX_LINE_PER_FRAME-1;
|
||||
signal a_data_reg : unsigned(A_RAM_DATA_WIDTH-1 downto 0);
|
||||
signal a_data_we : std_logic;
|
||||
signal csr_posx_overflow : std_logic;
|
||||
signal csr_posx_cnt_din : natural range 0 to MAX_CHAR_PER_LINE-1;
|
||||
signal csr_posx_cnt_set : std_logic;
|
||||
signal csr_posx_cnt_en : std_logic;
|
||||
signal csr_posy_overflow : std_logic;
|
||||
signal csr_posy_cnt_din : natural range 0 to MAX_LINE_PER_FRAME-1;
|
||||
signal csr_posy_cnt_set : std_logic;
|
||||
signal csr_posy_cnt_en : std_logic;
|
||||
|
||||
signal line_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
|
||||
signal char_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
|
||||
|
||||
-- Visible Cursor
|
||||
constant CURSOR_BLINK_INTERVAL : natural := tsvga.nfps/2;
|
||||
|
||||
type cursor_rom_t is array (0 to 2*CHAR_ROM_SIZE_Y-1) of unsigned (CHAR_ROM_SIZE_X-1 downto 0);
|
||||
constant cursor_rom : cursor_rom_t :=
|
||||
(
|
||||
-- Cursor off
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"11111111",
|
||||
"11111111",
|
||||
"11111111",
|
||||
|
||||
-- Cursor on
|
||||
"00000000",
|
||||
"00000000",
|
||||
"11111111",
|
||||
"11111111",
|
||||
"11111111",
|
||||
"11111111",
|
||||
"11111111",
|
||||
"11111111",
|
||||
"11111111",
|
||||
"11111111",
|
||||
"11111111",
|
||||
"11111111",
|
||||
"11111111",
|
||||
"00000000",
|
||||
"00000000",
|
||||
"00000000"
|
||||
|
||||
);
|
||||
signal cursor_rom_addr : unsigned(NextExpBaseTwo(2*CHAR_ROM_SIZE_Y)-1 downto 0);
|
||||
signal cursor_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0);
|
||||
signal cursor_visible : std_logic;
|
||||
signal cursor_cnt : natural range 0 to CURSOR_BLINK_INTERVAL-1;
|
||||
signal csr_posx_synced : natural range 0 to MAX_CHAR_PER_LINE-1;
|
||||
signal csr_posy_synced : natural range 0 to MAX_LINE_PER_FRAME-1;
|
||||
|
||||
-- Scrolling
|
||||
signal scroll_offset : natural range 0 to MAX_CHAR_PER_LINE-1;
|
||||
signal scroll_active : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
a_addr_rd <= to_unsigned(cell_x_cnt, a_addr_rd'length) + offset_rom(line_offset);
|
||||
line_addr <= offset_rom(csr_posy_reg);
|
||||
char_addr <= to_unsigned(csr_posx_reg, char_addr'length);
|
||||
char_rom_addr <= a_data_rd & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1));
|
||||
cursor_rom_addr <= cursor_visible & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1));
|
||||
|
||||
inst_char_rom : entity work.char_rom
|
||||
PORT MAP
|
||||
(
|
||||
CLK => vga_clk,
|
||||
ADDR => char_rom_addr,
|
||||
DATA => char_rom_data
|
||||
);
|
||||
|
||||
inst_ascii_ram: entity work.dpram
|
||||
GENERIC MAP (
|
||||
addr_width => A_RAM_ADDR_WIDTH,
|
||||
data_width => A_RAM_DATA_WIDTH
|
||||
)
|
||||
PORT MAP(
|
||||
clka => sys_clk,
|
||||
clkb => vga_clk,
|
||||
en_a => '1',
|
||||
en_b => '1',
|
||||
we_a => a_ram_we,
|
||||
addr_a => a_addr_wr,
|
||||
addr_b => a_addr_rd,
|
||||
din_a => a_data_wr,
|
||||
dout_b => a_data_rd
|
||||
);
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
--- ASCII RAM control
|
||||
---------------------------------------------------------------------------------------------
|
||||
asci_ram_fsm:
|
||||
process (s, a_cnt, clr_line, clr_screen, a_data_we, a_data_reg, char_addr, line_addr)
|
||||
begin
|
||||
sn <= s;
|
||||
a_cnt_rst <= '0';
|
||||
a_cnt_en <= '0';
|
||||
a_ram_we <= '0';
|
||||
a_data_wr <= a_data_reg;
|
||||
a_addr_wr <= char_addr + line_addr;
|
||||
ready <= '0';
|
||||
|
||||
case s is
|
||||
|
||||
when cg_init =>
|
||||
sn <= cg_clr_screen;
|
||||
a_cnt_rst <= '1';
|
||||
when cg_ready =>
|
||||
ready <= '1';
|
||||
a_ram_we <= a_data_we;
|
||||
if clr_screen = '1' then
|
||||
a_cnt_rst <= '1';
|
||||
sn <= cg_clr_screen;
|
||||
elsif clr_line = '1' then
|
||||
a_cnt_rst <= '1';
|
||||
sn <= cg_clr_line;
|
||||
end if;
|
||||
when cg_clr_line =>
|
||||
a_ram_we <= '1';
|
||||
a_cnt_en <= '1';
|
||||
a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH);
|
||||
a_addr_wr <= to_unsigned(a_cnt + to_integer(line_addr), A_RAM_ADDR_WIDTH);
|
||||
if a_cnt = MAX_CHAR_PER_LINE-1 then
|
||||
sn <= cg_ready;
|
||||
end if;
|
||||
when cg_clr_screen =>
|
||||
a_ram_we <= '1';
|
||||
a_cnt_en <= '1';
|
||||
a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH);
|
||||
a_addr_wr <= to_unsigned(a_cnt, A_RAM_ADDR_WIDTH);
|
||||
if a_cnt = (2**A_RAM_ADDR_WIDTH-1) then
|
||||
sn <= cg_ready;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
sn <= cg_ready;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
asci_ram_fsm_next: process (rst, sys_clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
s <= cg_init;
|
||||
elsif rising_edge(sys_clk) then
|
||||
s <= sn;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
asci_ram_cnt: process (rst, sys_clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
a_cnt <= 0;
|
||||
elsif rising_edge(sys_clk) then
|
||||
if a_cnt_rst = '1' then
|
||||
a_cnt <= 0;
|
||||
elsif a_cnt_en = '1' then
|
||||
if a_cnt < (2**A_RAM_ADDR_WIDTH-1) then
|
||||
a_cnt <= a_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
asci_addr_reg: process (rst, sys_clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
csr_posx_cnt_en <= '0';
|
||||
csr_posx_cnt_set <= '0';
|
||||
csr_posy_cnt_en <= '0';
|
||||
csr_posy_cnt_set <= '0';
|
||||
a_data_reg <= (others => '0');
|
||||
a_data_we <= '0';
|
||||
elsif rising_edge(sys_clk) then
|
||||
a_data_we <= '0';
|
||||
csr_posx_cnt_en <= '0';
|
||||
csr_posx_cnt_set <= '0';
|
||||
csr_posy_cnt_en <= '0';
|
||||
csr_posy_cnt_set <= '0';
|
||||
if ascii_posy_we = '1' then
|
||||
csr_posy_cnt_din <= to_integer(ascii_data);
|
||||
csr_posy_cnt_set <= '1';
|
||||
elsif ascii_posx_we = '1' then
|
||||
csr_posx_cnt_din <= to_integer(ascii_data);
|
||||
csr_posx_cnt_set <= '1';
|
||||
elsif ascii_data_we = '1' then
|
||||
if ascii_data < X"20" then
|
||||
if ascii_data = X"0D" then
|
||||
csr_posx_cnt_din <= 0;
|
||||
csr_posx_cnt_set <= '1';
|
||||
elsif ascii_data = X"0A" then
|
||||
csr_posy_cnt_en <= '1';
|
||||
end if;
|
||||
else
|
||||
a_data_reg <= ascii_data - X"20";
|
||||
a_data_we <= '1';
|
||||
csr_posx_cnt_en <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
asci_csr_posx_counter:
|
||||
process (rst, sys_clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
csr_posx_reg <= 0;
|
||||
csr_posx_overflow <= '0';
|
||||
elsif rising_edge(sys_clk) then
|
||||
csr_posx_overflow <= '0';
|
||||
if csr_posx_cnt_set = '1' then
|
||||
csr_posx_reg <= csr_posx_cnt_din;
|
||||
elsif csr_posx_cnt_en = '1' then
|
||||
if csr_posx_reg < MAX_CHAR_PER_LINE-1 then
|
||||
csr_posx_reg <= csr_posx_reg + 1;
|
||||
else
|
||||
csr_posx_reg <= 0;
|
||||
csr_posx_overflow <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
asci_csr_posy_counter:
|
||||
process (rst, sys_clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
csr_posy_reg <= 0;
|
||||
csr_posy_overflow <= '0';
|
||||
elsif rising_edge(sys_clk) then
|
||||
csr_posy_overflow <= '0';
|
||||
if csr_posy_cnt_set = '1' then
|
||||
csr_posy_reg <= csr_posy_cnt_din;
|
||||
elsif csr_posy_cnt_en = '1' or csr_posx_overflow = '1' then
|
||||
if csr_posy_reg < MAX_LINE_PER_FRAME-1 then
|
||||
csr_posy_reg <= csr_posy_reg + 1;
|
||||
else
|
||||
csr_posy_reg <= 0;
|
||||
csr_posy_overflow <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
scroll_gen: process (rst, sys_clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
scroll_offset <= 0;
|
||||
scroll_active <= '0';
|
||||
elsif rising_edge(sys_clk) then
|
||||
if clr_screen = '1' then
|
||||
scroll_offset <= 0;
|
||||
scroll_active <= '0';
|
||||
elsif csr_posy_overflow = '1' then
|
||||
scroll_active <= '1';
|
||||
scroll_offset <= 1;
|
||||
end if;
|
||||
if (csr_posy_cnt_en = '1' or csr_posx_overflow = '1') and scroll_active = '1' then
|
||||
scroll_offset <= scroll_offset + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
--- Cursor generator
|
||||
---------------------------------------------------------------------------------------------
|
||||
proc_sync_csr_posx:
|
||||
process(vga_clk)
|
||||
variable p1, p2 : natural range 0 to MAX_CHAR_PER_LINE-1;
|
||||
begin
|
||||
if rising_edge(vga_clk) then
|
||||
csr_posx_synced <= p2;
|
||||
p2 := p1;
|
||||
p1 := csr_posx_reg;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_sync_csr_posy:
|
||||
process(vga_clk)
|
||||
variable p1, p2 : natural range 0 to MAX_LINE_PER_FRAME-1;
|
||||
begin
|
||||
if rising_edge(vga_clk) then
|
||||
csr_posy_synced <= p2;
|
||||
p2 := p1;
|
||||
p1 := csr_posy_reg;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
csr_blink_cnt: process (rst, vga_clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
cursor_cnt <= 0;
|
||||
cursor_visible <= '0';
|
||||
elsif rising_edge(vga_clk) then
|
||||
if frame_pulse = '1' then
|
||||
if cursor_cnt < CURSOR_BLINK_INTERVAL-1 then
|
||||
cursor_cnt <= cursor_cnt + 1;
|
||||
else
|
||||
cursor_cnt <= 0;
|
||||
cursor_visible <= not cursor_visible;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cursor_rom_read: process (vga_clk)
|
||||
begin
|
||||
if rising_edge(vga_clk) then
|
||||
cursor_rom_data <= (others => '0');
|
||||
if (cell_x_cnt = csr_posx_synced) and (line_offset = csr_posy_synced) then
|
||||
cursor_rom_data <= cursor_rom(to_integer(cursor_rom_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
--- Character generator
|
||||
---------------------------------------------------------------------------------------------
|
||||
char_rom_ctrl: process (vga_clk)
|
||||
begin
|
||||
if rising_edge(vga_clk) then
|
||||
char_rom_row <= to_unsigned(char_y_cnt, char_rom_row'length);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
char_reg_ctrl: process (vga_clk)
|
||||
begin
|
||||
if rising_edge(vga_clk) and ce = '1' then
|
||||
if char_x_cnt = 2 then -- +2 delay for ASCII-RAM access and CHAR-ROM access
|
||||
for i in 0 to CHAR_ROM_SIZE_X-1 loop
|
||||
for j in 0 to CHARACTER_SCALE-1 loop
|
||||
char_reg(i*CHARACTER_SCALE + j) <= char_rom_data(i) xor cursor_rom_data(i);
|
||||
end loop;
|
||||
end loop;
|
||||
else
|
||||
char_reg <= char_reg(char_reg'left-1 downto 0) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
cg_ctrl: process (rst, vga_clk)
|
||||
variable enable_x : std_logic;
|
||||
variable enable_y : std_logic;
|
||||
variable char_en : std_logic;
|
||||
variable char_en2 : std_logic;
|
||||
begin
|
||||
|
||||
if (rst = '1') then
|
||||
enable_x := '0';
|
||||
enable_y := '0';
|
||||
line_offset <= 0;
|
||||
cell_x_cnt <= 0;
|
||||
cell_y_cnt <= 0;
|
||||
char_x_cnt <= 0;
|
||||
char_y_cnt <= 0;
|
||||
char_en := '0';
|
||||
elsif rising_edge(vga_clk) and ce = '1' then
|
||||
char_draw_en <= char_en2 and char_reg(char_reg'left);
|
||||
char_en2 := char_en;
|
||||
char_en := '0';
|
||||
if pos_y = SCREEN_OFFSET_Y then
|
||||
enable_y := '1';
|
||||
cell_y_cnt <= 0;
|
||||
char_x_cnt <= 0;
|
||||
line_offset <= scroll_offset;
|
||||
end if;
|
||||
if pos_x = SCREEN_OFFSET_X and enable_y = '1' then
|
||||
enable_x := '1';
|
||||
cell_x_cnt <= 0;
|
||||
char_x_cnt <= 0;
|
||||
elsif enable_x = '1' and enable_y = '1' then
|
||||
if char_x_cnt < CELL_SIZE_X-1 then
|
||||
char_x_cnt <= char_x_cnt + 1;
|
||||
else
|
||||
char_x_cnt <= 0;
|
||||
if cell_x_cnt < MAX_CHAR_PER_LINE-1 then
|
||||
cell_x_cnt <= cell_x_cnt + 1;
|
||||
else
|
||||
enable_x := '0';
|
||||
if char_y_cnt < CELL_SIZE_Y-1 then
|
||||
char_y_cnt <= char_y_cnt + 1;
|
||||
else
|
||||
char_y_cnt <= 0;
|
||||
if cell_y_cnt < MAX_LINE_PER_FRAME-1 then
|
||||
cell_y_cnt <= cell_y_cnt + 1;
|
||||
else
|
||||
enable_y := '0';
|
||||
end if;
|
||||
if line_offset < MAX_LINE_PER_FRAME-1 then
|
||||
line_offset <= line_offset + 1;
|
||||
else
|
||||
line_offset <= 0;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if (char_x_cnt < CHAR_SIZE_X) and (char_y_cnt < CHAR_SIZE_Y) then
|
||||
char_en := '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
end Behavioral;
|
||||
@@ -1,105 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11:25:45 10/15/05
|
||||
-- Design Name:
|
||||
-- Module Name: vga_ctrl_core - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.vga_types.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
Library UNISIM;
|
||||
use UNISIM.vcomponents.all;
|
||||
|
||||
entity clkgen is
|
||||
Generic
|
||||
(
|
||||
sys_freq : integer := 100E6;
|
||||
tsvga : vga_timespec_t := ts_vga_800_600_72
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
vga_clk : out std_logic;
|
||||
dcm_locked : out std_logic
|
||||
);
|
||||
end clkgen;
|
||||
|
||||
architecture tech of clkgen is
|
||||
|
||||
signal vga_clk0 : std_logic;
|
||||
signal dcm_clk0 : std_logic;
|
||||
signal dcm_clk_fb : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Compnent instantiation
|
||||
DCM_VGA_CLK_inst : DCM_BASE
|
||||
generic map (
|
||||
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
||||
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
||||
CLKFX_DIVIDE => DCM_FREQ_D(sys_freq, tsvga.f_pxl_clk), -- Can be any interger from 1 to 32
|
||||
CLKFX_MULTIPLY => DCM_FREQ_M(sys_freq, tsvga.f_pxl_clk), -- Can be any integer from 2 to 32
|
||||
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
|
||||
CLKIN_PERIOD => DCM_PERIOD(sys_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
|
||||
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
|
||||
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
|
||||
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
||||
-- an integer from 0 to 15
|
||||
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
|
||||
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
|
||||
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
|
||||
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
|
||||
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
|
||||
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
||||
port map (
|
||||
CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput
|
||||
CLK180 => open, -- 180 degree DCM CLK output
|
||||
CLK270 => open, -- 270 degree DCM CLK output
|
||||
CLK2X => open, -- 2X DCM CLK output
|
||||
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
|
||||
CLK90 => open, -- 90 degree DCM CLK output
|
||||
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
|
||||
CLKFX => vga_clk0, -- DCM CLK synthesis out (M/D)
|
||||
CLKFX180 => open, -- 180 degree CLK synthesis out
|
||||
LOCKED => dcm_locked, -- DCM LOCK status output
|
||||
CLKFB => dcm_clk_fb, -- DCM clock feedback
|
||||
CLKIN => clk, -- Clock input (from IBUFG, BUFG or DCM)
|
||||
RST => rst -- DCM asynchronous reset input
|
||||
);
|
||||
|
||||
BUFG_dcm_clk_fb : BUFG
|
||||
port map
|
||||
(
|
||||
O => dcm_clk_fb, -- Clock buffer output
|
||||
I => dcm_clk0 -- Clock buffer input
|
||||
);
|
||||
|
||||
BUFG_vga_clk : BUFG
|
||||
port map
|
||||
(
|
||||
O => vga_clk, -- Clock buffer output
|
||||
I => vga_clk0 -- Clock buffer input
|
||||
);
|
||||
|
||||
|
||||
end tech;
|
||||
@@ -1,79 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dpram is
|
||||
Generic
|
||||
(
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port
|
||||
(
|
||||
clka : in STD_LOGIC;
|
||||
clkb : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end dpram;
|
||||
|
||||
architecture Behavioral of dpram is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clka)
|
||||
begin
|
||||
if clka'event and clka = '1' then
|
||||
if en_a = '1' then
|
||||
if we_a = '1' then
|
||||
RAM(to_integer(addr_a)) <= din_a;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clkb)
|
||||
begin
|
||||
if clkb'event and clkb = '1' then
|
||||
if en_b = '1' then
|
||||
dout_b <= RAM(to_integer(addr_b));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,540 +0,0 @@
|
||||
-- generated with romgen v3.0 by MikeJ
|
||||
library ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity char_rom is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
ADDR : in unsigned(11 downto 0);
|
||||
DATA : out unsigned(7 downto 0)
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of char_rom is
|
||||
|
||||
|
||||
type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
|
||||
constant ROM : ROM_ARRAY := (
|
||||
x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0000
|
||||
x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0008
|
||||
x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0010
|
||||
x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0018
|
||||
x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0020
|
||||
x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0028
|
||||
x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0030
|
||||
x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0038
|
||||
x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0040
|
||||
x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0048
|
||||
x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0050
|
||||
x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0058
|
||||
x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0060
|
||||
x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0068
|
||||
x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0070
|
||||
x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0078
|
||||
x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0080
|
||||
x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0088
|
||||
x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0090
|
||||
x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0098
|
||||
x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x00A0
|
||||
x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x00A8
|
||||
x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0
|
||||
x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x00B8
|
||||
x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x00C0
|
||||
x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8
|
||||
x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x00D0
|
||||
x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8
|
||||
x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x00E0
|
||||
x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8
|
||||
x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0
|
||||
x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
|
||||
x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0108
|
||||
x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0110
|
||||
x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0118
|
||||
x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0120
|
||||
x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0128
|
||||
x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130
|
||||
x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0138
|
||||
x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140
|
||||
x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148
|
||||
x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0150
|
||||
x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158
|
||||
x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160
|
||||
x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168
|
||||
x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
|
||||
x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178
|
||||
x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0180
|
||||
x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0188
|
||||
x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0190
|
||||
x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198
|
||||
x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x01A0
|
||||
x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8
|
||||
x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0
|
||||
x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x01B8
|
||||
x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0
|
||||
x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x01C8
|
||||
x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0
|
||||
x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8
|
||||
x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0
|
||||
x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8
|
||||
x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0
|
||||
x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x01F8
|
||||
x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200
|
||||
x"08",x"1C",x"3E",x"7F",x"7F",x"1C",x"3E",x"00", -- 0x0208
|
||||
x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0210
|
||||
x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0218
|
||||
x"00",x"00",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0220
|
||||
x"00",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0228
|
||||
x"00",x"00",x"00",x"00",x"FF",x"FF",x"00",x"00", -- 0x0230
|
||||
x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0238
|
||||
x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C", -- 0x0240
|
||||
x"00",x"00",x"00",x"E0",x"F0",x"38",x"18",x"18", -- 0x0248
|
||||
x"18",x"18",x"1C",x"0F",x"07",x"00",x"00",x"00", -- 0x0250
|
||||
x"18",x"18",x"38",x"F0",x"E0",x"00",x"00",x"00", -- 0x0258
|
||||
x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FF",x"FF", -- 0x0260
|
||||
x"C0",x"E0",x"70",x"38",x"1C",x"0E",x"07",x"03", -- 0x0268
|
||||
x"03",x"07",x"0E",x"1C",x"38",x"70",x"E0",x"C0", -- 0x0270
|
||||
x"FF",x"FF",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0278
|
||||
x"FF",x"FF",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0280
|
||||
x"00",x"3C",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288
|
||||
x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"00", -- 0x0290
|
||||
x"36",x"7F",x"7F",x"7F",x"3E",x"1C",x"08",x"00", -- 0x0298
|
||||
x"60",x"60",x"60",x"60",x"60",x"60",x"60",x"60", -- 0x02A0
|
||||
x"00",x"00",x"00",x"07",x"0F",x"1C",x"18",x"18", -- 0x02A8
|
||||
x"C3",x"E7",x"7E",x"3C",x"3C",x"7E",x"E7",x"C3", -- 0x02B0
|
||||
x"00",x"3C",x"7E",x"66",x"66",x"7E",x"3C",x"00", -- 0x02B8
|
||||
x"18",x"18",x"66",x"66",x"18",x"18",x"3C",x"00", -- 0x02C0
|
||||
x"06",x"06",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x02C8
|
||||
x"08",x"1C",x"3E",x"7F",x"3E",x"1C",x"08",x"00", -- 0x02D0
|
||||
x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x02D8
|
||||
x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x02E0
|
||||
x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02E8
|
||||
x"00",x"00",x"03",x"3E",x"76",x"36",x"36",x"00", -- 0x02F0
|
||||
x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
|
||||
x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308
|
||||
x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310
|
||||
x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320
|
||||
x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0328
|
||||
x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0330
|
||||
x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0338
|
||||
x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0340
|
||||
x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348
|
||||
x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350
|
||||
x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0358
|
||||
x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360
|
||||
x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0368
|
||||
x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0370
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378
|
||||
x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0380
|
||||
x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0388
|
||||
x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0390
|
||||
x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0398
|
||||
x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0
|
||||
x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0
|
||||
x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
|
||||
x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8
|
||||
x"03",x"03",x"03",x"03",x"03",x"03",x"FF",x"FF", -- 0x03D0
|
||||
x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8
|
||||
x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0
|
||||
x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x03E8
|
||||
x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0
|
||||
x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8
|
||||
x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0400
|
||||
x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0408
|
||||
x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0410
|
||||
x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0418
|
||||
x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0420
|
||||
x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428
|
||||
x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430
|
||||
x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0438
|
||||
x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0440
|
||||
x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0448
|
||||
x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0450
|
||||
x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0458
|
||||
x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460
|
||||
x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0468
|
||||
x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0470
|
||||
x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0478
|
||||
x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0480
|
||||
x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0488
|
||||
x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0490
|
||||
x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0498
|
||||
x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0
|
||||
x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x04A8
|
||||
x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x04B0
|
||||
x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x04B8
|
||||
x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x04C0
|
||||
x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8
|
||||
x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x04D0
|
||||
x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8
|
||||
x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x04E0
|
||||
x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8
|
||||
x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x04F0
|
||||
x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x04F8
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500
|
||||
x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0508
|
||||
x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0510
|
||||
x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0518
|
||||
x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0520
|
||||
x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0528
|
||||
x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0530
|
||||
x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0538
|
||||
x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0540
|
||||
x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0548
|
||||
x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0550
|
||||
x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0558
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0560
|
||||
x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0568
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570
|
||||
x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0578
|
||||
x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0580
|
||||
x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0588
|
||||
x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0590
|
||||
x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0598
|
||||
x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x05A0
|
||||
x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x05A8
|
||||
x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x05B0
|
||||
x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8
|
||||
x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x05C0
|
||||
x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x05C8
|
||||
x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x05D0
|
||||
x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x05D8
|
||||
x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0
|
||||
x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x05E8
|
||||
x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0
|
||||
x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x05F8
|
||||
x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0600
|
||||
x"F7",x"E3",x"C1",x"80",x"80",x"E3",x"C1",x"FF", -- 0x0608
|
||||
x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0610
|
||||
x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0618
|
||||
x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0620
|
||||
x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628
|
||||
x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF", -- 0x0630
|
||||
x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF", -- 0x0638
|
||||
x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0640
|
||||
x"FF",x"FF",x"FF",x"1F",x"0F",x"C7",x"E7",x"E7", -- 0x0648
|
||||
x"E7",x"E7",x"E3",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0650
|
||||
x"E7",x"E7",x"C7",x"0F",x"1F",x"FF",x"FF",x"FF", -- 0x0658
|
||||
x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"00",x"00", -- 0x0660
|
||||
x"3F",x"1F",x"8F",x"C7",x"E3",x"F1",x"F8",x"FC", -- 0x0668
|
||||
x"FC",x"F8",x"F1",x"E3",x"C7",x"8F",x"1F",x"3F", -- 0x0670
|
||||
x"00",x"00",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0678
|
||||
x"00",x"00",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0680
|
||||
x"FF",x"C3",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF", -- 0x0690
|
||||
x"C9",x"80",x"80",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x0698
|
||||
x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F", -- 0x06A0
|
||||
x"FF",x"FF",x"FF",x"F8",x"F0",x"E3",x"E7",x"E7", -- 0x06A8
|
||||
x"3C",x"18",x"81",x"C3",x"C3",x"81",x"18",x"3C", -- 0x06B0
|
||||
x"FF",x"C3",x"81",x"99",x"99",x"81",x"C3",x"FF", -- 0x06B8
|
||||
x"E7",x"E7",x"99",x"99",x"E7",x"E7",x"C3",x"FF", -- 0x06C0
|
||||
x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x06C8
|
||||
x"F7",x"E3",x"C1",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x06D0
|
||||
x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x06D8
|
||||
x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x06E0
|
||||
x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x06E8
|
||||
x"FF",x"FF",x"FC",x"C1",x"89",x"C9",x"C9",x"FF", -- 0x06F0
|
||||
x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700
|
||||
x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708
|
||||
x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710
|
||||
x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720
|
||||
x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0728
|
||||
x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0730
|
||||
x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0738
|
||||
x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0740
|
||||
x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748
|
||||
x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750
|
||||
x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0758
|
||||
x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760
|
||||
x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0768
|
||||
x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0770
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778
|
||||
x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0780
|
||||
x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0788
|
||||
x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0790
|
||||
x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0798
|
||||
x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0
|
||||
x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8
|
||||
x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0
|
||||
x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8
|
||||
x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8
|
||||
x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"00",x"00", -- 0x07D0
|
||||
x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8
|
||||
x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0
|
||||
x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x07E8
|
||||
x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0
|
||||
x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0", -- 0x07F8
|
||||
x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0800
|
||||
x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0808
|
||||
x"00",x"60",x"60",x"7C",x"66",x"66",x"7C",x"00", -- 0x0810
|
||||
x"00",x"00",x"3C",x"60",x"60",x"60",x"3C",x"00", -- 0x0818
|
||||
x"00",x"06",x"06",x"3E",x"66",x"66",x"3E",x"00", -- 0x0820
|
||||
x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0828
|
||||
x"00",x"0E",x"18",x"3E",x"18",x"18",x"18",x"00", -- 0x0830
|
||||
x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"7C", -- 0x0838
|
||||
x"00",x"60",x"60",x"7C",x"66",x"66",x"66",x"00", -- 0x0840
|
||||
x"00",x"18",x"00",x"38",x"18",x"18",x"3C",x"00", -- 0x0848
|
||||
x"00",x"06",x"00",x"06",x"06",x"06",x"06",x"3C", -- 0x0850
|
||||
x"00",x"60",x"60",x"6C",x"78",x"6C",x"66",x"00", -- 0x0858
|
||||
x"00",x"38",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0860
|
||||
x"00",x"00",x"66",x"7F",x"7F",x"6B",x"63",x"00", -- 0x0868
|
||||
x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0870
|
||||
x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0878
|
||||
x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0880
|
||||
x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"06", -- 0x0888
|
||||
x"00",x"00",x"7C",x"66",x"60",x"60",x"60",x"00", -- 0x0890
|
||||
x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0898
|
||||
x"00",x"18",x"7E",x"18",x"18",x"18",x"0E",x"00", -- 0x08A0
|
||||
x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x08A8
|
||||
x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x08B0
|
||||
x"00",x"00",x"63",x"6B",x"7F",x"3E",x"36",x"00", -- 0x08B8
|
||||
x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x08C0
|
||||
x"00",x"00",x"66",x"66",x"66",x"3E",x"0C",x"78", -- 0x08C8
|
||||
x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x08D0
|
||||
x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x08D8
|
||||
x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x08E0
|
||||
x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x08E8
|
||||
x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x08F0
|
||||
x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x08F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
|
||||
x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0908
|
||||
x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0910
|
||||
x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0918
|
||||
x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0920
|
||||
x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0928
|
||||
x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0930
|
||||
x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0938
|
||||
x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0940
|
||||
x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0948
|
||||
x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0950
|
||||
x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0958
|
||||
x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0960
|
||||
x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0968
|
||||
x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0970
|
||||
x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0978
|
||||
x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0980
|
||||
x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0988
|
||||
x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0990
|
||||
x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0998
|
||||
x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x09A0
|
||||
x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x09A8
|
||||
x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x09B0
|
||||
x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x09B8
|
||||
x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x09C0
|
||||
x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x09C8
|
||||
x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x09D0
|
||||
x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x09D8
|
||||
x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x09E0
|
||||
x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x09E8
|
||||
x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x09F0
|
||||
x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x09F8
|
||||
x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0A00
|
||||
x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A08
|
||||
x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0A10
|
||||
x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0A18
|
||||
x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0A20
|
||||
x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0A28
|
||||
x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0A30
|
||||
x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0A38
|
||||
x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A40
|
||||
x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0A48
|
||||
x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0A50
|
||||
x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0A58
|
||||
x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0A60
|
||||
x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0A68
|
||||
x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0A70
|
||||
x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0A78
|
||||
x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0A80
|
||||
x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0A88
|
||||
x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0A90
|
||||
x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0A98
|
||||
x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x0AA0
|
||||
x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0AA8
|
||||
x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x0AB0
|
||||
x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x0AB8
|
||||
x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x0AC0
|
||||
x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x0AC8
|
||||
x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x0AD0
|
||||
x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x0AD8
|
||||
x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x0AE0
|
||||
x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0AE8
|
||||
x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0AF0
|
||||
x"33",x"99",x"CC",x"66",x"33",x"99",x"CC",x"66", -- 0x0AF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
|
||||
x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0B08
|
||||
x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0B10
|
||||
x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0B20
|
||||
x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0B28
|
||||
x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0B30
|
||||
x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B38
|
||||
x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0B40
|
||||
x"CC",x"99",x"33",x"66",x"CC",x"99",x"33",x"66", -- 0x0B48
|
||||
x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B50
|
||||
x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B58
|
||||
x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0B60
|
||||
x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0B68
|
||||
x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0B78
|
||||
x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B80
|
||||
x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0B88
|
||||
x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0B90
|
||||
x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B98
|
||||
x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0BA0
|
||||
x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0BA8
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0BB0
|
||||
x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
|
||||
x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0BC8
|
||||
x"01",x"03",x"06",x"6C",x"78",x"70",x"60",x"00", -- 0x0BD0
|
||||
x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x0BD8
|
||||
x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x0BE0
|
||||
x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x0BE8
|
||||
x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x0BF0
|
||||
x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x0BF8
|
||||
x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0C00
|
||||
x"FF",x"FF",x"C3",x"F9",x"C1",x"99",x"C1",x"FF", -- 0x0C08
|
||||
x"FF",x"9F",x"9F",x"83",x"99",x"99",x"83",x"FF", -- 0x0C10
|
||||
x"FF",x"FF",x"C3",x"9F",x"9F",x"9F",x"C3",x"FF", -- 0x0C18
|
||||
x"FF",x"F9",x"F9",x"C1",x"99",x"99",x"C1",x"FF", -- 0x0C20
|
||||
x"FF",x"FF",x"C3",x"99",x"81",x"9F",x"C3",x"FF", -- 0x0C28
|
||||
x"FF",x"F1",x"E7",x"C1",x"E7",x"E7",x"E7",x"FF", -- 0x0C30
|
||||
x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"83", -- 0x0C38
|
||||
x"FF",x"9F",x"9F",x"83",x"99",x"99",x"99",x"FF", -- 0x0C40
|
||||
x"FF",x"E7",x"FF",x"C7",x"E7",x"E7",x"C3",x"FF", -- 0x0C48
|
||||
x"FF",x"F9",x"FF",x"F9",x"F9",x"F9",x"F9",x"C3", -- 0x0C50
|
||||
x"FF",x"9F",x"9F",x"93",x"87",x"93",x"99",x"FF", -- 0x0C58
|
||||
x"FF",x"C7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0C60
|
||||
x"FF",x"FF",x"99",x"80",x"80",x"94",x"9C",x"FF", -- 0x0C68
|
||||
x"FF",x"FF",x"83",x"99",x"99",x"99",x"99",x"FF", -- 0x0C70
|
||||
x"FF",x"FF",x"C3",x"99",x"99",x"99",x"C3",x"FF", -- 0x0C78
|
||||
x"FF",x"FF",x"83",x"99",x"99",x"83",x"9F",x"9F", -- 0x0C80
|
||||
x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"F9", -- 0x0C88
|
||||
x"FF",x"FF",x"83",x"99",x"9F",x"9F",x"9F",x"FF", -- 0x0C90
|
||||
x"FF",x"FF",x"C1",x"9F",x"C3",x"F9",x"83",x"FF", -- 0x0C98
|
||||
x"FF",x"E7",x"81",x"E7",x"E7",x"E7",x"F1",x"FF", -- 0x0CA0
|
||||
x"FF",x"FF",x"99",x"99",x"99",x"99",x"C1",x"FF", -- 0x0CA8
|
||||
x"FF",x"FF",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0CB0
|
||||
x"FF",x"FF",x"9C",x"94",x"80",x"C1",x"C9",x"FF", -- 0x0CB8
|
||||
x"FF",x"FF",x"99",x"C3",x"E7",x"C3",x"99",x"FF", -- 0x0CC0
|
||||
x"FF",x"FF",x"99",x"99",x"99",x"C1",x"F3",x"87", -- 0x0CC8
|
||||
x"FF",x"FF",x"81",x"F3",x"E7",x"CF",x"81",x"FF", -- 0x0CD0
|
||||
x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x0CD8
|
||||
x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x0CE0
|
||||
x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x0CE8
|
||||
x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x0CF0
|
||||
x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x0CF8
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D00
|
||||
x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0D08
|
||||
x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D10
|
||||
x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0D18
|
||||
x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0D20
|
||||
x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0D28
|
||||
x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0D30
|
||||
x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D38
|
||||
x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0D40
|
||||
x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0D48
|
||||
x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0D50
|
||||
x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0D58
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0D60
|
||||
x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0D68
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0D70
|
||||
x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0D78
|
||||
x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0D80
|
||||
x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0D88
|
||||
x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0D90
|
||||
x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0D98
|
||||
x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x0DA0
|
||||
x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x0DA8
|
||||
x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x0DB0
|
||||
x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0DB8
|
||||
x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x0DC0
|
||||
x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x0DC8
|
||||
x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x0DD0
|
||||
x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0DD8
|
||||
x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x0DE0
|
||||
x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x0DE8
|
||||
x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x0DF0
|
||||
x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x0DF8
|
||||
x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0E00
|
||||
x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E08
|
||||
x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0E10
|
||||
x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0E18
|
||||
x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0E20
|
||||
x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0E28
|
||||
x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0E30
|
||||
x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0E38
|
||||
x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E40
|
||||
x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0E48
|
||||
x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0E50
|
||||
x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0E58
|
||||
x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0E60
|
||||
x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0E68
|
||||
x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0E70
|
||||
x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0E78
|
||||
x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0E80
|
||||
x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0E88
|
||||
x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0E90
|
||||
x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0E98
|
||||
x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0EA0
|
||||
x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0EA8
|
||||
x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0EB0
|
||||
x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x0EB8
|
||||
x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x0EC0
|
||||
x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x0EC8
|
||||
x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x0ED0
|
||||
x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0ED8
|
||||
x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x0EE0
|
||||
x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0EE8
|
||||
x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0EF0
|
||||
x"CC",x"66",x"33",x"99",x"CC",x"66",x"33",x"99", -- 0x0EF8
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F00
|
||||
x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0F08
|
||||
x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0F10
|
||||
x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F18
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0F20
|
||||
x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0F28
|
||||
x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0F30
|
||||
x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F38
|
||||
x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0F40
|
||||
x"33",x"66",x"CC",x"99",x"33",x"66",x"CC",x"99", -- 0x0F48
|
||||
x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F50
|
||||
x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F58
|
||||
x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0F60
|
||||
x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0F68
|
||||
x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F70
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0F78
|
||||
x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F80
|
||||
x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0F88
|
||||
x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0F90
|
||||
x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F98
|
||||
x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0FA0
|
||||
x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x0FA8
|
||||
x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0FB0
|
||||
x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FB8
|
||||
x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FC0
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x0FC8
|
||||
x"FE",x"FC",x"F9",x"93",x"87",x"8F",x"9F",x"FF", -- 0x0FD0
|
||||
x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x0FD8
|
||||
x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0FE0
|
||||
x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x0FE8
|
||||
x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x0FF0
|
||||
x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0" -- 0x0FF8
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
p_rom : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
DATA <= ROM(to_integer(unsigned(ADDR)));
|
||||
end process;
|
||||
end RTL;
|
||||
@@ -1,539 +0,0 @@
|
||||
library ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity char_rom is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
ADDR : in unsigned(11 downto 0);
|
||||
DATA : out unsigned(7 downto 0)
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of char_rom is
|
||||
|
||||
|
||||
type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
|
||||
constant ROM : ROM_ARRAY := (
|
||||
x"7C",x"40",x"7C",x"44",x"7C",x"0C",x"0C",x"7C", -- 0x0000
|
||||
x"3C",x"24",x"7E",x"62",x"62",x"62",x"62",x"00", -- 0x0008
|
||||
x"7C",x"24",x"3E",x"32",x"32",x"32",x"7E",x"00", -- 0x0010
|
||||
x"7E",x"42",x"40",x"60",x"60",x"62",x"7E",x"00", -- 0x0018
|
||||
x"7E",x"22",x"22",x"32",x"32",x"32",x"7E",x"00", -- 0x0020
|
||||
x"7E",x"40",x"40",x"78",x"60",x"60",x"7E",x"00", -- 0x0028
|
||||
x"7E",x"40",x"40",x"78",x"60",x"60",x"60",x"00", -- 0x0030
|
||||
x"7E",x"42",x"40",x"6E",x"62",x"62",x"7E",x"00", -- 0x0038
|
||||
x"42",x"42",x"42",x"7E",x"62",x"62",x"62",x"00", -- 0x0040
|
||||
x"10",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x0048
|
||||
x"02",x"02",x"02",x"06",x"06",x"46",x"3C",x"00", -- 0x0050
|
||||
x"42",x"44",x"48",x"7E",x"62",x"62",x"62",x"00", -- 0x0058
|
||||
x"40",x"40",x"40",x"60",x"60",x"60",x"7E",x"00", -- 0x0060
|
||||
x"66",x"5A",x"42",x"62",x"62",x"62",x"62",x"00", -- 0x0068
|
||||
x"72",x"4A",x"4A",x"6A",x"6A",x"6A",x"66",x"00", -- 0x0070
|
||||
x"7E",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x0078
|
||||
x"7E",x"42",x"42",x"7E",x"60",x"60",x"60",x"00", -- 0x0080
|
||||
x"7E",x"42",x"42",x"62",x"6A",x"64",x"7A",x"00", -- 0x0088
|
||||
x"7E",x"42",x"42",x"7E",x"64",x"62",x"62",x"00", -- 0x0090
|
||||
x"7E",x"42",x"40",x"7E",x"06",x"46",x"7E",x"00", -- 0x0098
|
||||
x"7C",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x00A0
|
||||
x"42",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x00A8
|
||||
x"42",x"42",x"42",x"24",x"24",x"18",x"18",x"00", -- 0x00B0
|
||||
x"62",x"62",x"62",x"62",x"42",x"5A",x"66",x"00", -- 0x00B8
|
||||
x"42",x"24",x"18",x"7C",x"62",x"62",x"62",x"00", -- 0x00C0
|
||||
x"42",x"42",x"42",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8
|
||||
x"7E",x"02",x"1C",x"60",x"60",x"60",x"7E",x"00", -- 0x00D0
|
||||
x"3C",x"20",x"20",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8
|
||||
x"18",x"20",x"20",x"78",x"60",x"60",x"7C",x"00", -- 0x00E0
|
||||
x"3C",x"04",x"04",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8
|
||||
x"08",x"1C",x"2A",x"08",x"08",x"08",x"08",x"00", -- 0x00F0
|
||||
x"00",x"20",x"40",x"FE",x"40",x"20",x"00",x"00", -- 0x00F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
|
||||
x"18",x"18",x"1C",x"1C",x"1C",x"00",x"1C",x"00", -- 0x0108
|
||||
x"36",x"36",x"12",x"12",x"00",x"00",x"00",x"00", -- 0x0110
|
||||
x"24",x"24",x"7E",x"34",x"7E",x"34",x"34",x"00", -- 0x0118
|
||||
x"08",x"3E",x"28",x"3E",x"1A",x"3E",x"18",x"00", -- 0x0120
|
||||
x"70",x"52",x"74",x"08",x"1E",x"2A",x"4E",x"00", -- 0x0128
|
||||
x"78",x"48",x"30",x"70",x"6A",x"64",x"7A",x"00", -- 0x0130
|
||||
x"38",x"38",x"08",x"08",x"00",x"00",x"00",x"00", -- 0x0138
|
||||
x"0C",x"10",x"20",x"30",x"30",x"10",x"0C",x"00", -- 0x0140
|
||||
x"30",x"08",x"04",x"0C",x"0C",x"08",x"30",x"00", -- 0x0148
|
||||
x"08",x"2A",x"1C",x"3E",x"1C",x"2A",x"08",x"00", -- 0x0150
|
||||
x"00",x"08",x"08",x"3E",x"3E",x"0C",x"0C",x"00", -- 0x0158
|
||||
x"00",x"00",x"00",x"00",x"1C",x"1C",x"04",x"04", -- 0x0160
|
||||
x"00",x"00",x"00",x"7E",x"7E",x"00",x"00",x"00", -- 0x0168
|
||||
x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
|
||||
x"00",x"02",x"04",x"08",x"10",x"20",x"40",x"00", -- 0x0178
|
||||
x"7E",x"42",x"46",x"6A",x"72",x"62",x"7E",x"00", -- 0x0180
|
||||
x"38",x"08",x"08",x"18",x"18",x"18",x"3C",x"00", -- 0x0188
|
||||
x"7E",x"42",x"02",x"7E",x"60",x"60",x"7E",x"00", -- 0x0190
|
||||
x"3E",x"02",x"02",x"1E",x"06",x"06",x"7E",x"00", -- 0x0198
|
||||
x"40",x"40",x"44",x"44",x"7E",x"0C",x"0C",x"00", -- 0x01A0
|
||||
x"3E",x"20",x"20",x"3E",x"06",x"46",x"7E",x"00", -- 0x01A8
|
||||
x"7E",x"40",x"40",x"7E",x"62",x"62",x"7E",x"00", -- 0x01B0
|
||||
x"7E",x"42",x"04",x"08",x"18",x"18",x"18",x"00", -- 0x01B8
|
||||
x"3C",x"24",x"24",x"7E",x"62",x"62",x"7E",x"00", -- 0x01C0
|
||||
x"7E",x"42",x"42",x"7E",x"06",x"06",x"7E",x"00", -- 0x01C8
|
||||
x"00",x"00",x"18",x"00",x"18",x"18",x"00",x"00", -- 0x01D0
|
||||
x"00",x"00",x"1C",x"00",x"1C",x"1C",x"04",x"04", -- 0x01D8
|
||||
x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0
|
||||
x"00",x"00",x"7E",x"00",x"7E",x"7E",x"00",x"00", -- 0x01E8
|
||||
x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0
|
||||
x"7E",x"42",x"02",x"3E",x"30",x"00",x"30",x"00", -- 0x01F8
|
||||
x"00",x"00",x"00",x"00",x"FF",x"00",x"00",x"00", -- 0x0200
|
||||
x"18",x"3C",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x0208
|
||||
x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"10", -- 0x0210
|
||||
x"00",x"00",x"00",x"FF",x"00",x"00",x"00",x"00", -- 0x0218
|
||||
x"00",x"00",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0220
|
||||
x"00",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0228
|
||||
x"00",x"00",x"00",x"00",x"00",x"FF",x"00",x"00", -- 0x0230
|
||||
x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x0238
|
||||
x"04",x"04",x"04",x"04",x"04",x"04",x"04",x"04", -- 0x0240
|
||||
x"00",x"00",x"00",x"C0",x"30",x"10",x"08",x"08", -- 0x0248
|
||||
x"10",x"10",x"08",x"0C",x"03",x"00",x"00",x"00", -- 0x0250
|
||||
x"08",x"08",x"10",x"30",x"C0",x"00",x"00",x"00", -- 0x0258
|
||||
x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"FF", -- 0x0260
|
||||
x"80",x"40",x"20",x"10",x"08",x"04",x"02",x"01", -- 0x0268
|
||||
x"01",x"02",x"04",x"08",x"10",x"20",x"40",x"80", -- 0x0270
|
||||
x"FF",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0278
|
||||
x"FF",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0280
|
||||
x"3C",x"7E",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"00", -- 0x0290
|
||||
x"24",x"7E",x"7E",x"7E",x"3C",x"18",x"18",x"00", -- 0x0298
|
||||
x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x02A0
|
||||
x"00",x"00",x"00",x"03",x"0C",x"08",x"10",x"10", -- 0x02A8
|
||||
x"81",x"42",x"24",x"18",x"18",x"24",x"42",x"81", -- 0x02B0
|
||||
x"3C",x"7E",x"66",x"42",x"66",x"7E",x"3C",x"00", -- 0x02B8
|
||||
x"18",x"18",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x02C0
|
||||
x"02",x"02",x"02",x"02",x"02",x"02",x"02",x"02", -- 0x02C8
|
||||
x"00",x"18",x"3C",x"7E",x"7E",x"3C",x"18",x"00", -- 0x02D0
|
||||
x"08",x"08",x"08",x"FF",x"08",x"08",x"08",x"08", -- 0x02D8
|
||||
x"C0",x"30",x"C0",x"30",x"C0",x"30",x"C0",x"30", -- 0x02E0
|
||||
x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x02E8
|
||||
x"00",x"00",x"7C",x"24",x"64",x"64",x"66",x"00", -- 0x02F0
|
||||
x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
|
||||
x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308
|
||||
x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310
|
||||
x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320
|
||||
x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0328
|
||||
x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33", -- 0x0330
|
||||
x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0338
|
||||
x"00",x"00",x"00",x"00",x"CC",x"33",x"CC",x"33", -- 0x0340
|
||||
x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348
|
||||
x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350
|
||||
x"08",x"08",x"08",x"0F",x"08",x"08",x"08",x"08", -- 0x0358
|
||||
x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360
|
||||
x"08",x"08",x"08",x"0F",x"00",x"00",x"00",x"00", -- 0x0368
|
||||
x"00",x"00",x"00",x"F8",x"08",x"08",x"08",x"08", -- 0x0370
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378
|
||||
x"00",x"00",x"00",x"0F",x"08",x"08",x"08",x"08", -- 0x0380
|
||||
x"08",x"08",x"08",x"FF",x"00",x"00",x"00",x"00", -- 0x0388
|
||||
x"00",x"00",x"00",x"FF",x"08",x"08",x"08",x"08", -- 0x0390
|
||||
x"08",x"08",x"08",x"F8",x"08",x"08",x"08",x"08", -- 0x0398
|
||||
x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0
|
||||
x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0
|
||||
x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
|
||||
x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8
|
||||
x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"FF", -- 0x03D0
|
||||
x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8
|
||||
x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0
|
||||
x"08",x"08",x"08",x"F8",x"00",x"00",x"00",x"00", -- 0x03E8
|
||||
x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0
|
||||
x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8
|
||||
x"83",x"BF",x"83",x"BB",x"83",x"F3",x"F3",x"83", -- 0x0400
|
||||
x"C3",x"DB",x"81",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0408
|
||||
x"83",x"DB",x"C1",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0410
|
||||
x"81",x"BD",x"BF",x"9F",x"9F",x"9D",x"81",x"FF", -- 0x0418
|
||||
x"81",x"DD",x"DD",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0420
|
||||
x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428
|
||||
x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430
|
||||
x"81",x"BD",x"BF",x"91",x"9D",x"9D",x"81",x"FF", -- 0x0438
|
||||
x"BD",x"BD",x"BD",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0440
|
||||
x"EF",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0448
|
||||
x"FD",x"FD",x"FD",x"F9",x"F9",x"B9",x"C3",x"FF", -- 0x0450
|
||||
x"BD",x"BB",x"B7",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0458
|
||||
x"BF",x"BF",x"BF",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460
|
||||
x"99",x"A5",x"BD",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0468
|
||||
x"8D",x"B5",x"B5",x"95",x"95",x"95",x"99",x"FF", -- 0x0470
|
||||
x"81",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x0478
|
||||
x"81",x"BD",x"BD",x"81",x"9F",x"9F",x"9F",x"FF", -- 0x0480
|
||||
x"81",x"BD",x"BD",x"9D",x"95",x"9B",x"85",x"FF", -- 0x0488
|
||||
x"81",x"BD",x"BD",x"81",x"9B",x"9D",x"9D",x"FF", -- 0x0490
|
||||
x"81",x"BD",x"BF",x"81",x"F9",x"B9",x"81",x"FF", -- 0x0498
|
||||
x"83",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0
|
||||
x"BD",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x04A8
|
||||
x"BD",x"BD",x"BD",x"DB",x"DB",x"E7",x"E7",x"FF", -- 0x04B0
|
||||
x"9D",x"9D",x"9D",x"9D",x"BD",x"A5",x"99",x"FF", -- 0x04B8
|
||||
x"BD",x"DB",x"E7",x"83",x"9D",x"9D",x"9D",x"FF", -- 0x04C0
|
||||
x"BD",x"BD",x"BD",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8
|
||||
x"81",x"FD",x"E3",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x04D0
|
||||
x"C3",x"DF",x"DF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8
|
||||
x"E7",x"DF",x"DF",x"87",x"9F",x"9F",x"83",x"FF", -- 0x04E0
|
||||
x"C3",x"FB",x"FB",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8
|
||||
x"F7",x"E3",x"D5",x"F7",x"F7",x"F7",x"F7",x"FF", -- 0x04F0
|
||||
x"FF",x"DF",x"BF",x"01",x"BF",x"DF",x"FF",x"FF", -- 0x04F8
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500
|
||||
x"E7",x"E7",x"E3",x"E3",x"E3",x"FF",x"E3",x"FF", -- 0x0508
|
||||
x"C9",x"C9",x"ED",x"ED",x"FF",x"FF",x"FF",x"FF", -- 0x0510
|
||||
x"DB",x"DB",x"81",x"CB",x"81",x"CB",x"CB",x"FF", -- 0x0518
|
||||
x"F7",x"C1",x"D7",x"C1",x"E5",x"C1",x"E7",x"FF", -- 0x0520
|
||||
x"8F",x"AD",x"8B",x"F7",x"E1",x"D5",x"B1",x"FF", -- 0x0528
|
||||
x"87",x"B7",x"CF",x"8F",x"95",x"9B",x"85",x"FF", -- 0x0530
|
||||
x"C7",x"C7",x"F7",x"F7",x"FF",x"FF",x"FF",x"FF", -- 0x0538
|
||||
x"F3",x"EF",x"DF",x"CF",x"CF",x"EF",x"F3",x"FF", -- 0x0540
|
||||
x"CF",x"F7",x"FB",x"F3",x"F3",x"F7",x"CF",x"FF", -- 0x0548
|
||||
x"F7",x"D5",x"E3",x"C1",x"E3",x"D5",x"F7",x"FF", -- 0x0550
|
||||
x"FF",x"F7",x"F7",x"C1",x"C1",x"F3",x"F3",x"FF", -- 0x0558
|
||||
x"FF",x"FF",x"FF",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x0560
|
||||
x"FF",x"FF",x"FF",x"81",x"81",x"FF",x"FF",x"FF", -- 0x0568
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570
|
||||
x"FF",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"FF", -- 0x0578
|
||||
x"81",x"BD",x"B9",x"95",x"8D",x"9D",x"81",x"FF", -- 0x0580
|
||||
x"C7",x"F7",x"F7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0588
|
||||
x"81",x"BD",x"FD",x"81",x"9F",x"9F",x"81",x"FF", -- 0x0590
|
||||
x"C1",x"FD",x"FD",x"E1",x"F9",x"F9",x"81",x"FF", -- 0x0598
|
||||
x"BF",x"BF",x"BB",x"BB",x"81",x"F3",x"F3",x"FF", -- 0x05A0
|
||||
x"C1",x"DF",x"DF",x"C1",x"F9",x"B9",x"81",x"FF", -- 0x05A8
|
||||
x"81",x"BF",x"BF",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05B0
|
||||
x"81",x"BD",x"FB",x"F7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8
|
||||
x"C3",x"DB",x"DB",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05C0
|
||||
x"81",x"BD",x"BD",x"81",x"F9",x"F9",x"81",x"FF", -- 0x05C8
|
||||
x"FF",x"FF",x"E7",x"FF",x"E7",x"E7",x"FF",x"FF", -- 0x05D0
|
||||
x"FF",x"FF",x"E3",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x05D8
|
||||
x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0
|
||||
x"FF",x"FF",x"81",x"FF",x"81",x"81",x"FF",x"FF", -- 0x05E8
|
||||
x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0
|
||||
x"81",x"BD",x"FD",x"C1",x"CF",x"FF",x"CF",x"FF", -- 0x05F8
|
||||
x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF", -- 0x0600
|
||||
x"E7",x"C3",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x0608
|
||||
x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF", -- 0x0610
|
||||
x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0618
|
||||
x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0620
|
||||
x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF", -- 0x0630
|
||||
x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF", -- 0x0638
|
||||
x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB", -- 0x0640
|
||||
x"FF",x"FF",x"FF",x"3F",x"CF",x"EF",x"F7",x"F7", -- 0x0648
|
||||
x"EF",x"EF",x"F7",x"F3",x"FC",x"FF",x"FF",x"FF", -- 0x0650
|
||||
x"F7",x"F7",x"EF",x"CF",x"3F",x"FF",x"FF",x"FF", -- 0x0658
|
||||
x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"00", -- 0x0660
|
||||
x"7F",x"BF",x"DF",x"EF",x"F7",x"FB",x"FD",x"FE", -- 0x0668
|
||||
x"FE",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"7F", -- 0x0670
|
||||
x"00",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0678
|
||||
x"00",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0680
|
||||
x"C3",x"81",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x0690
|
||||
x"DB",x"81",x"81",x"81",x"C3",x"E7",x"E7",x"FF", -- 0x0698
|
||||
x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF", -- 0x06A0
|
||||
x"FF",x"FF",x"FF",x"FC",x"F3",x"F7",x"EF",x"EF", -- 0x06A8
|
||||
x"7E",x"BD",x"DB",x"E7",x"E7",x"DB",x"BD",x"7E", -- 0x06B0
|
||||
x"C3",x"81",x"99",x"BD",x"99",x"81",x"C3",x"FF", -- 0x06B8
|
||||
x"E7",x"E7",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x06C0
|
||||
x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD", -- 0x06C8
|
||||
x"FF",x"E7",x"C3",x"81",x"81",x"C3",x"E7",x"FF", -- 0x06D0
|
||||
x"F7",x"F7",x"F7",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x06D8
|
||||
x"3F",x"CF",x"3F",x"CF",x"3F",x"CF",x"3F",x"CF", -- 0x06E0
|
||||
x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7", -- 0x06E8
|
||||
x"FF",x"FF",x"83",x"DB",x"9B",x"9B",x"99",x"FF", -- 0x06F0
|
||||
x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700
|
||||
x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708
|
||||
x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710
|
||||
x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720
|
||||
x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0728
|
||||
x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC", -- 0x0730
|
||||
x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0738
|
||||
x"FF",x"FF",x"FF",x"FF",x"33",x"CC",x"33",x"CC", -- 0x0740
|
||||
x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748
|
||||
x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750
|
||||
x"F7",x"F7",x"F7",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0758
|
||||
x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760
|
||||
x"F7",x"F7",x"F7",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0768
|
||||
x"FF",x"FF",x"FF",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0770
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778
|
||||
x"FF",x"FF",x"FF",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0780
|
||||
x"F7",x"F7",x"F7",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0788
|
||||
x"FF",x"FF",x"FF",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x0790
|
||||
x"F7",x"F7",x"F7",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0798
|
||||
x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0
|
||||
x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8
|
||||
x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0
|
||||
x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8
|
||||
x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8
|
||||
x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"00", -- 0x07D0
|
||||
x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8
|
||||
x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0
|
||||
x"F7",x"F7",x"F7",x"07",x"FF",x"FF",x"FF",x"FF", -- 0x07E8
|
||||
x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0
|
||||
x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"00", -- 0x07F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
p_rom : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
DATA <= ROM(to_integer(unsigned(ADDR)));
|
||||
end process;
|
||||
end RTL;
|
||||
@@ -1,539 +0,0 @@
|
||||
library ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity char_rom is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
ADDR : in unsigned(11 downto 0);
|
||||
DATA : out unsigned(7 downto 0)
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of char_rom is
|
||||
|
||||
|
||||
type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
|
||||
constant ROM : ROM_ARRAY := (
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0000
|
||||
x"08",x"14",x"14",x"22",x"3E",x"41",x"41",x"80", -- 0x0008
|
||||
x"FC",x"42",x"42",x"7C",x"42",x"42",x"42",x"FC", -- 0x0010
|
||||
x"3C",x"46",x"40",x"40",x"40",x"40",x"46",x"3C", -- 0x0018
|
||||
x"FC",x"42",x"42",x"42",x"42",x"42",x"42",x"FC", -- 0x0020
|
||||
x"FC",x"46",x"50",x"70",x"50",x"40",x"46",x"FC", -- 0x0028
|
||||
x"FC",x"46",x"50",x"70",x"50",x"40",x"40",x"E0", -- 0x0030
|
||||
x"3C",x"46",x"40",x"4E",x"44",x"44",x"44",x"3C", -- 0x0038
|
||||
x"EE",x"44",x"44",x"7C",x"44",x"44",x"44",x"EE", -- 0x0040
|
||||
x"1C",x"08",x"08",x"08",x"08",x"08",x"08",x"1C", -- 0x0048
|
||||
x"1C",x"08",x"08",x"08",x"08",x"08",x"C8",x"70", -- 0x0050
|
||||
x"E6",x"48",x"50",x"60",x"50",x"48",x"44",x"EE", -- 0x0058
|
||||
x"E0",x"40",x"40",x"40",x"40",x"40",x"46",x"FC", -- 0x0060
|
||||
x"C6",x"6C",x"6C",x"54",x"54",x"44",x"44",x"EE", -- 0x0068
|
||||
x"CE",x"64",x"64",x"54",x"54",x"4C",x"4C",x"E6", -- 0x0070
|
||||
x"3C",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x0078
|
||||
x"FC",x"42",x"42",x"7C",x"40",x"40",x"40",x"E0", -- 0x0080
|
||||
x"3C",x"42",x"42",x"42",x"42",x"4A",x"46",x"3D", -- 0x0088
|
||||
x"FC",x"42",x"42",x"7C",x"50",x"48",x"44",x"EE", -- 0x0090
|
||||
x"3C",x"42",x"40",x"20",x"1C",x"02",x"C2",x"7C", -- 0x0098
|
||||
x"FE",x"92",x"10",x"10",x"10",x"10",x"10",x"38", -- 0x00A0
|
||||
x"E7",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x00A8
|
||||
x"E7",x"42",x"42",x"42",x"42",x"42",x"24",x"18", -- 0x00B0
|
||||
x"C3",x"41",x"5D",x"49",x"49",x"55",x"63",x"41", -- 0x00B8
|
||||
x"EE",x"44",x"28",x"10",x"10",x"28",x"44",x"EE", -- 0x00C0
|
||||
x"EE",x"44",x"44",x"28",x"10",x"10",x"10",x"38", -- 0x00C8
|
||||
x"FE",x"84",x"08",x"7C",x"24",x"40",x"82",x"FE", -- 0x00D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
|
||||
x"10",x"10",x"10",x"10",x"10",x"00",x"10",x"10", -- 0x0108
|
||||
x"CC",x"44",x"44",x"22",x"00",x"00",x"00",x"00", -- 0x0110
|
||||
x"77",x"22",x"FF",x"22",x"22",x"FF",x"22",x"77", -- 0x0118
|
||||
x"10",x"3E",x"50",x"3C",x"12",x"12",x"7C",x"10", -- 0x0120
|
||||
x"87",x"42",x"04",x"08",x"10",x"20",x"44",x"E2", -- 0x0128
|
||||
x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130
|
||||
x"1E",x"08",x"3C",x"00",x"00",x"00",x"00",x"00", -- 0x0138
|
||||
x"0E",x"12",x"60",x"40",x"40",x"60",x"12",x"0E", -- 0x0140
|
||||
x"70",x"48",x"06",x"02",x"02",x"06",x"48",x"70", -- 0x0148
|
||||
x"42",x"24",x"99",x"7E",x"99",x"24",x"42",x"00", -- 0x0150
|
||||
x"08",x"08",x"08",x"7F",x"08",x"08",x"08",x"00", -- 0x0158
|
||||
x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160
|
||||
x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168
|
||||
x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
|
||||
x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178
|
||||
x"7C",x"82",x"82",x"82",x"82",x"82",x"82",x"7C", -- 0x0180
|
||||
x"10",x"30",x"50",x"10",x"10",x"10",x"10",x"7C", -- 0x0188
|
||||
x"7C",x"C2",x"02",x"1C",x"60",x"80",x"86",x"FC", -- 0x0190
|
||||
x"7C",x"C2",x"02",x"1C",x"02",x"02",x"C2",x"7C", -- 0x0198
|
||||
x"08",x"18",x"28",x"48",x"FE",x"08",x"08",x"3E", -- 0x01A0
|
||||
x"FE",x"80",x"80",x"FC",x"02",x"02",x"C2",x"7C", -- 0x01A8
|
||||
x"7C",x"86",x"80",x"FC",x"82",x"82",x"82",x"7C", -- 0x01B0
|
||||
x"7E",x"C2",x"04",x"08",x"10",x"10",x"10",x"7C", -- 0x01B8
|
||||
x"7C",x"82",x"82",x"7C",x"82",x"82",x"82",x"7C", -- 0x01C0
|
||||
x"7C",x"82",x"82",x"7E",x"02",x"02",x"C2",x"7C", -- 0x01C8
|
||||
x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0
|
||||
x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8
|
||||
x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0
|
||||
x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8
|
||||
x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0
|
||||
x"3C",x"62",x"02",x"04",x"08",x"08",x"00",x"08", -- 0x01F8
|
||||
x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0200
|
||||
x"FE",x"FE",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0208
|
||||
x"FE",x"FE",x"C6",x"FC",x"C6",x"C6",x"FE",x"FE", -- 0x0210
|
||||
x"FE",x"FE",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0218
|
||||
x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0220
|
||||
x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"FE",x"FE", -- 0x0228
|
||||
x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0230
|
||||
x"FE",x"FE",x"C0",x"DE",x"C6",x"C6",x"FE",x"FE", -- 0x0238
|
||||
x"C6",x"C6",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0240
|
||||
x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0248
|
||||
x"18",x"18",x"18",x"18",x"18",x"18",x"78",x"78", -- 0x0250
|
||||
x"C6",x"C6",x"DC",x"F0",x"D8",x"CC",x"C6",x"C6", -- 0x0258
|
||||
x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0260
|
||||
x"FE",x"FE",x"D6",x"D6",x"D6",x"D6",x"D6",x"D6", -- 0x0268
|
||||
x"E6",x"E6",x"F6",x"D6",x"D6",x"DE",x"CE",x"CE", -- 0x0270
|
||||
x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0278
|
||||
x"FE",x"FE",x"C6",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0280
|
||||
x"FE",x"FE",x"C6",x"C6",x"C6",x"CE",x"FE",x"FF", -- 0x0288
|
||||
x"FE",x"FE",x"C6",x"FE",x"D8",x"D8",x"C6",x"C6", -- 0x0290
|
||||
x"FE",x"FE",x"C0",x"FE",x"06",x"06",x"FE",x"FE", -- 0x0298
|
||||
x"FE",x"FE",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02A0
|
||||
x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x02A8
|
||||
x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"7C", -- 0x02B0
|
||||
x"D6",x"D6",x"D6",x"D6",x"D6",x"D6",x"FE",x"FE", -- 0x02B8
|
||||
x"C6",x"C6",x"6C",x"38",x"38",x"6C",x"C6",x"C6", -- 0x02C0
|
||||
x"C6",x"C6",x"C6",x"FE",x"06",x"06",x"FE",x"FE", -- 0x02C8
|
||||
x"FE",x"FE",x"0E",x"18",x"30",x"E0",x"FE",x"FE", -- 0x02D0
|
||||
x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x02D8
|
||||
x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x02E0
|
||||
x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x02E8
|
||||
x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x02F0
|
||||
x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x02F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368
|
||||
x"00",x"00",x"00",x"07",x"1F",x"3F",x"3F",x"7F", -- 0x0370
|
||||
x"00",x"00",x"00",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0378
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400
|
||||
x"03",x"1F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0408
|
||||
x"FC",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"0F", -- 0x0410
|
||||
x"00",x"80",x"E0",x"F8",x"F8",x"FE",x"FE",x"FE", -- 0x0418
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"07", -- 0x0420
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"F8",x"FE", -- 0x0428
|
||||
x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0430
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x0438
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"7F", -- 0x0440
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x0448
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x0450
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"C0", -- 0x0458
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"1F",x"7F", -- 0x0460
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"E0",x"F8", -- 0x0468
|
||||
x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7F",x"7F", -- 0x0470
|
||||
x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"FF",x"FF", -- 0x0478
|
||||
x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC", -- 0x0480
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0488
|
||||
x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F1", -- 0x0490
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"FF", -- 0x0498
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x04A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x04A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x04B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500
|
||||
x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0508
|
||||
x"03",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0510
|
||||
x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0518
|
||||
x"07",x"07",x"07",x"00",x"00",x"07",x"0F",x"3F", -- 0x0520
|
||||
x"FE",x"FF",x"FF",x"7F",x"3F",x"FF",x"FF",x"FF", -- 0x0528
|
||||
x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0530
|
||||
x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"03", -- 0x0538
|
||||
x"7F",x"7F",x"7F",x"07",x"03",x"7F",x"FF",x"FF", -- 0x0540
|
||||
x"E0",x"F0",x"F1",x"F1",x"F3",x"F3",x"F3",x"F1", -- 0x0548
|
||||
x"7F",x"FF",x"FF",x"FC",x"F0",x"F0",x"F0",x"F8", -- 0x0550
|
||||
x"C0",x"C1",x"C1",x"03",x"03",x"03",x"03",x"03", -- 0x0558
|
||||
x"FF",x"FF",x"FF",x"FF",x"F8",x"F0",x"F0",x"F0", -- 0x0560
|
||||
x"FC",x"FE",x"FE",x"FF",x"7F",x"3F",x"3F",x"3F", -- 0x0568
|
||||
x"7F",x"7F",x"7F",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0570
|
||||
x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0578
|
||||
x"FC",x"FC",x"FC",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0580
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0588
|
||||
x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0590
|
||||
x"FF",x"FF",x"FF",x"F3",x"F1",x"F1",x"F1",x"F1", -- 0x0598
|
||||
x"F0",x"F0",x"F8",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x05A0
|
||||
x"7F",x"FF",x"FF",x"FC",x"F8",x"F8",x"F8",x"F8", -- 0x05A8
|
||||
x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x05B0
|
||||
x"3C",x"42",x"B9",x"A5",x"B9",x"A9",x"A5",x"42", -- 0x05B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600
|
||||
x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0608
|
||||
x"01",x"01",x"03",x"0F",x"7F",x"7F",x"7F",x"7F", -- 0x0610
|
||||
x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FC",x"FC", -- 0x0618
|
||||
x"3F",x"7F",x"7E",x"7C",x"7E",x"7F",x"3F",x"3F", -- 0x0620
|
||||
x"FF",x"FF",x"3F",x"3F",x"3F",x"BF",x"BF",x"BF", -- 0x0628
|
||||
x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"1F", -- 0x0630
|
||||
x"03",x"07",x"07",x"07",x"07",x"F7",x"F3",x"F3", -- 0x0638
|
||||
x"FF",x"FF",x"E3",x"C3",x"E3",x"FB",x"FB",x"FB", -- 0x0640
|
||||
x"F1",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0648
|
||||
x"FC",x"FE",x"7F",x"3F",x"1F",x"0F",x"07",x"03", -- 0x0650
|
||||
x"03",x"03",x"83",x"C3",x"E3",x"F1",x"F1",x"F0", -- 0x0658
|
||||
x"F0",x"F0",x"F0",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0660
|
||||
x"3F",x"3F",x"3F",x"3F",x"7F",x"FE",x"FE",x"FC", -- 0x0668
|
||||
x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0670
|
||||
x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"07", -- 0x0678
|
||||
x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC",x"FC", -- 0x0680
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0688
|
||||
x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0690
|
||||
x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0698
|
||||
x"F9",x"F9",x"F9",x"F9",x"F9",x"F8",x"F8",x"F8", -- 0x06A0
|
||||
x"F8",x"F8",x"F8",x"F8",x"FC",x"FF",x"FF",x"7F", -- 0x06A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"FC",x"FC",x"FC", -- 0x06B0
|
||||
x"3C",x"00",x"00",x"00",x"78",x"FC",x"FC",x"FC", -- 0x06B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700
|
||||
x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0708
|
||||
x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0710
|
||||
x"F0",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718
|
||||
x"0F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720
|
||||
x"BF",x"BF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728
|
||||
x"1F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730
|
||||
x"F0",x"F0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738
|
||||
x"FB",x"7B",x"03",x"01",x"00",x"00",x"00",x"00", -- 0x0740
|
||||
x"F0",x"F8",x"FE",x"FF",x"FF",x"FF",x"3F",x"07", -- 0x0748
|
||||
x"03",x"07",x"1F",x"FF",x"FF",x"FF",x"FE",x"F0", -- 0x0750
|
||||
x"F0",x"F0",x"E0",x"E0",x"C0",x"80",x"00",x"00", -- 0x0758
|
||||
x"7F",x"1F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760
|
||||
x"F8",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768
|
||||
x"7E",x"7E",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770
|
||||
x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778
|
||||
x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780
|
||||
x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788
|
||||
x"F3",x"F3",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790
|
||||
x"F1",x"F1",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798
|
||||
x"F8",x"F8",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0
|
||||
x"3F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8
|
||||
x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0
|
||||
x"FC",x"78",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
p_rom : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
DATA <= ROM(to_integer(unsigned(ADDR)));
|
||||
end process;
|
||||
end RTL;
|
||||
@@ -1,539 +0,0 @@
|
||||
library ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity char_rom is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
ADDR : in unsigned(11 downto 0);
|
||||
DATA : out unsigned(7 downto 0)
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of char_rom is
|
||||
|
||||
|
||||
type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
|
||||
constant ROM : ROM_ARRAY := (
|
||||
x"3C",x"66",x"6E",x"6A",x"6E",x"60",x"3C",x"00", -- 0x0000
|
||||
x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0008
|
||||
x"60",x"60",x"7C",x"66",x"66",x"66",x"7C",x"00", -- 0x0010
|
||||
x"00",x"00",x"3C",x"66",x"60",x"66",x"3C",x"00", -- 0x0018
|
||||
x"06",x"06",x"3E",x"66",x"66",x"66",x"3E",x"00", -- 0x0020
|
||||
x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0028
|
||||
x"1C",x"30",x"30",x"7C",x"30",x"30",x"30",x"00", -- 0x0030
|
||||
x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"3C", -- 0x0038
|
||||
x"60",x"60",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0040
|
||||
x"18",x"00",x"38",x"18",x"18",x"18",x"3C",x"00", -- 0x0048
|
||||
x"18",x"00",x"38",x"18",x"18",x"18",x"18",x"70", -- 0x0050
|
||||
x"60",x"60",x"66",x"6C",x"78",x"6C",x"66",x"00", -- 0x0058
|
||||
x"38",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0060
|
||||
x"00",x"00",x"36",x"7F",x"6B",x"6B",x"63",x"00", -- 0x0068
|
||||
x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0070
|
||||
x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0078
|
||||
x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0080
|
||||
x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"07", -- 0x0088
|
||||
x"00",x"00",x"6C",x"76",x"60",x"60",x"60",x"00", -- 0x0090
|
||||
x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0098
|
||||
x"30",x"30",x"7C",x"30",x"30",x"30",x"1C",x"00", -- 0x00A0
|
||||
x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x00A8
|
||||
x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0
|
||||
x"00",x"00",x"63",x"6B",x"6B",x"7F",x"36",x"00", -- 0x00B8
|
||||
x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x00C0
|
||||
x"00",x"00",x"66",x"66",x"66",x"3E",x"06",x"3C", -- 0x00C8
|
||||
x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x00D0
|
||||
x"7C",x"60",x"60",x"60",x"60",x"60",x"7C",x"00", -- 0x00D8
|
||||
x"1C",x"36",x"30",x"7C",x"30",x"30",x"7E",x"00", -- 0x00E0
|
||||
x"3E",x"06",x"06",x"06",x"06",x"06",x"3E",x"00", -- 0x00E8
|
||||
x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0
|
||||
x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
|
||||
x"18",x"18",x"18",x"18",x"18",x"00",x"18",x"00", -- 0x0108
|
||||
x"6C",x"6C",x"6C",x"00",x"00",x"00",x"00",x"00", -- 0x0110
|
||||
x"36",x"36",x"7F",x"36",x"7F",x"36",x"36",x"00", -- 0x0118
|
||||
x"0C",x"3F",x"68",x"3E",x"0B",x"7E",x"18",x"00", -- 0x0120
|
||||
x"60",x"66",x"0C",x"18",x"30",x"66",x"06",x"00", -- 0x0128
|
||||
x"38",x"6C",x"6C",x"38",x"6D",x"66",x"3B",x"00", -- 0x0130
|
||||
x"0C",x"18",x"30",x"00",x"00",x"00",x"00",x"00", -- 0x0138
|
||||
x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140
|
||||
x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148
|
||||
x"00",x"18",x"7E",x"3C",x"7E",x"18",x"00",x"00", -- 0x0150
|
||||
x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158
|
||||
x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160
|
||||
x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168
|
||||
x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
|
||||
x"00",x"06",x"0C",x"18",x"30",x"60",x"00",x"00", -- 0x0178
|
||||
x"3C",x"66",x"6E",x"7E",x"76",x"66",x"3C",x"00", -- 0x0180
|
||||
x"18",x"38",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0188
|
||||
x"3C",x"66",x"06",x"0C",x"18",x"30",x"7E",x"00", -- 0x0190
|
||||
x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198
|
||||
x"0C",x"1C",x"3C",x"6C",x"7E",x"0C",x"0C",x"00", -- 0x01A0
|
||||
x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8
|
||||
x"1C",x"30",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0
|
||||
x"7E",x"06",x"0C",x"18",x"30",x"30",x"30",x"00", -- 0x01B8
|
||||
x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0
|
||||
x"3C",x"66",x"66",x"3E",x"06",x"0C",x"38",x"00", -- 0x01C8
|
||||
x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"00", -- 0x01D0
|
||||
x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"30", -- 0x01D8
|
||||
x"0C",x"18",x"30",x"60",x"30",x"18",x"0C",x"00", -- 0x01E0
|
||||
x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8
|
||||
x"30",x"18",x"0C",x"06",x"0C",x"18",x"30",x"00", -- 0x01F0
|
||||
x"3C",x"66",x"0C",x"18",x"18",x"00",x"18",x"00", -- 0x01F8
|
||||
x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200
|
||||
x"3C",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0208
|
||||
x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0210
|
||||
x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0218
|
||||
x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0220
|
||||
x"7E",x"60",x"60",x"7C",x"60",x"60",x"7E",x"00", -- 0x0228
|
||||
x"7E",x"60",x"60",x"7C",x"60",x"60",x"60",x"00", -- 0x0230
|
||||
x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0238
|
||||
x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0240
|
||||
x"7E",x"18",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0248
|
||||
x"3E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0250
|
||||
x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0258
|
||||
x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0260
|
||||
x"63",x"77",x"7F",x"6B",x"6B",x"63",x"63",x"00", -- 0x0268
|
||||
x"66",x"66",x"76",x"7E",x"6E",x"66",x"66",x"00", -- 0x0270
|
||||
x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0278
|
||||
x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0280
|
||||
x"3C",x"66",x"66",x"66",x"6A",x"6C",x"36",x"00", -- 0x0288
|
||||
x"7C",x"66",x"66",x"7C",x"6C",x"66",x"66",x"00", -- 0x0290
|
||||
x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0298
|
||||
x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x02A0
|
||||
x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x02A8
|
||||
x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x02B0
|
||||
x"63",x"63",x"6B",x"00",x"00",x"00",x"00",x"00", -- 0x02B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0370
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
p_rom : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
DATA <= ROM(to_integer(unsigned(ADDR)));
|
||||
end process;
|
||||
end RTL;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,539 +0,0 @@
|
||||
library ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity char_rom is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
ADDR : in unsigned(11 downto 0);
|
||||
DATA : out unsigned(7 downto 0)
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of char_rom is
|
||||
|
||||
|
||||
type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
|
||||
constant ROM : ROM_ARRAY := (
|
||||
x"00",x"00",x"01",x"03",x"07",x"0F",x"0F",x"0F", -- 0x0000
|
||||
x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0008
|
||||
x"00",x"00",x"E0",x"F0",x"F8",x"FC",x"FC",x"FC", -- 0x0010
|
||||
x"00",x"00",x"01",x"07",x"1F",x"3F",x"7F",x"7F", -- 0x0018
|
||||
x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0020
|
||||
x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0028
|
||||
x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0030
|
||||
x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"8F", -- 0x0038
|
||||
x"00",x"00",x"C3",x"E3",x"F1",x"F1",x"F1",x"F1", -- 0x0040
|
||||
x"00",x"00",x"F8",x"FC",x"FE",x"FE",x"FE",x"FE", -- 0x0048
|
||||
x"00",x"00",x"1F",x"1F",x"0F",x"0F",x"0F",x"0F", -- 0x0050
|
||||
x"00",x"00",x"81",x"C3",x"E2",x"E2",x"E2",x"E2", -- 0x0058
|
||||
x"00",x"00",x"FC",x"06",x"FA",x"72",x"DA",x"FA", -- 0x0060
|
||||
x"00",x"00",x"03",x"0F",x"3F",x"7F",x"7F",x"7F", -- 0x0068
|
||||
x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"C7", -- 0x0070
|
||||
x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0078
|
||||
x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0080
|
||||
x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0088
|
||||
x"00",x"00",x"80",x"C0",x"C0",x"E0",x"E0",x"F0", -- 0x0090
|
||||
x"00",x"00",x"3F",x"3F",x"06",x"06",x"06",x"06", -- 0x0098
|
||||
x"00",x"00",x"D8",x"D8",x"18",x"1F",x"1F",x"18", -- 0x00A0
|
||||
x"00",x"00",x"DF",x"DF",x"D8",x"DE",x"DE",x"D8", -- 0x00A8
|
||||
x"00",x"00",x"80",x"80",x"00",x"00",x"00",x"00", -- 0x00B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8
|
||||
x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"3F", -- 0x0100
|
||||
x"C1",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"80", -- 0x0108
|
||||
x"FC",x"F8",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x0110
|
||||
x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0118
|
||||
x"FF",x"C3",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0120
|
||||
x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0128
|
||||
x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0130
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0138
|
||||
x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0140
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0148
|
||||
x"0F",x"0F",x"0F",x"8F",x"8F",x"8F",x"DF",x"FF", -- 0x0150
|
||||
x"E3",x"E3",x"E1",x"E0",x"E1",x"E1",x"E1",x"E3", -- 0x0158
|
||||
x"56",x"8E",x"FC",x"00",x"FF",x"FE",x"FE",x"FC", -- 0x0160
|
||||
x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0168
|
||||
x"83",x"03",x"03",x"0F",x"3F",x"FF",x"FF",x"FC", -- 0x0170
|
||||
x"F8",x"F8",x"F8",x"F8",x"F0",x"C0",x"00",x"00", -- 0x0178
|
||||
x"FF",x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0180
|
||||
x"E7",x"87",x"07",x"07",x"07",x"00",x"00",x"FF", -- 0x0188
|
||||
x"F0",x"F0",x"F0",x"E0",x"80",x"00",x"00",x"80", -- 0x0190
|
||||
x"06",x"06",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0198
|
||||
x"18",x"18",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A0
|
||||
x"DF",x"DF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A8
|
||||
x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8
|
||||
x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"7F",x"7F", -- 0x0200
|
||||
x"80",x"80",x"80",x"83",x"87",x"87",x"07",x"06", -- 0x0208
|
||||
x"00",x"1C",x"7C",x"FC",x"FC",x"FC",x"F0",x"F0", -- 0x0210
|
||||
x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0218
|
||||
x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0220
|
||||
x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0228
|
||||
x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0230
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"0F", -- 0x0238
|
||||
x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0240
|
||||
x"FF",x"FF",x"FF",x"FF",x"FE",x"FC",x"FC",x"FC", -- 0x0248
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"7F",x"7F", -- 0x0250
|
||||
x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3", -- 0x0258
|
||||
x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0260
|
||||
x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0268
|
||||
x"F0",x"C0",x"03",x"07",x"07",x"07",x"03",x"01", -- 0x0270
|
||||
x"18",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0278
|
||||
x"FF",x"FF",x"FF",x"FC",x"E0",x"06",x"1E",x"FE", -- 0x0280
|
||||
x"FF",x"FF",x"FF",x"0F",x"07",x"07",x"07",x"07", -- 0x0288
|
||||
x"C0",x"C0",x"E0",x"E0",x"F0",x"F0",x"F0",x"F0", -- 0x0290
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8
|
||||
x"7F",x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F", -- 0x0300
|
||||
x"00",x"00",x"00",x"80",x"FF",x"FF",x"FF",x"FF", -- 0x0308
|
||||
x"F0",x"78",x"7C",x"FC",x"FC",x"F8",x"F0",x"E0", -- 0x0310
|
||||
x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F",x"07", -- 0x0318
|
||||
x"8F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0320
|
||||
x"F8",x"F8",x"F8",x"F8",x"F8",x"F0",x"E0",x"C0", -- 0x0328
|
||||
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"3F", -- 0x0330
|
||||
x"1F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0338
|
||||
x"F1",x"F1",x"F1",x"F1",x"E1",x"C1",x"81",x"03", -- 0x0340
|
||||
x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FE",x"FF", -- 0x0348
|
||||
x"7F",x"3F",x"3F",x"3F",x"3F",x"1F",x"1F",x"1F", -- 0x0350
|
||||
x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"C7", -- 0x0358
|
||||
x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"F8",x"F0", -- 0x0360
|
||||
x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0368
|
||||
x"01",x"03",x"07",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0370
|
||||
x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0378
|
||||
x"FE",x"FE",x"FE",x"FF",x"FF",x"7F",x"1F",x"07", -- 0x0380
|
||||
x"07",x"07",x"0F",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0388
|
||||
x"F0",x"F0",x"F0",x"F0",x"FF",x"EF",x"C3",x"83", -- 0x0390
|
||||
x"00",x"00",x"00",x"00",x"DB",x"DF",x"1F",x"1B", -- 0x0398
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
p_rom : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
DATA <= ROM(to_integer(unsigned(ADDR)));
|
||||
end process;
|
||||
end RTL;
|
||||
@@ -1,6 +0,0 @@
|
||||
@echo off
|
||||
|
||||
bff2rom fixedsys_8x15.bff y >char_rom_fixedsys_8x15.vhd
|
||||
bff2rom fixedsys_8x16.bff y >char_rom_fixedsys_8x16.vhd
|
||||
bff2rom fixedsys_9x16.bff y >char_rom_fixedsys_9x16.vhd
|
||||
bff2rom System_16x16.bff y >char_rom_system_16x16.vhd
|
||||
@@ -1,121 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.vga_types.all;
|
||||
|
||||
entity linefifo is
|
||||
Generic
|
||||
(
|
||||
depth : natural := 64;
|
||||
almost_full_thresh : natural := 60;
|
||||
almost_empty_thresh : natural := 4
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in STD_LOGIC;
|
||||
clk_w : in STD_LOGIC;
|
||||
clk_r : in STD_LOGIC;
|
||||
we_w : in STD_LOGIC;
|
||||
re_r : in STD_LOGIC;
|
||||
fifo_full : out STD_LOGIC;
|
||||
fifo_empty : out STD_LOGIC;
|
||||
fifo_afull : out STD_LOGIC;
|
||||
fifo_aempty : out STD_LOGIC;
|
||||
color_w : in color_t;
|
||||
color_r : out color_t
|
||||
);
|
||||
end linefifo;
|
||||
|
||||
architecture Behavioral of linefifo is
|
||||
|
||||
constant data_width : integer := 8;
|
||||
constant addr_width : integer := NextExpBaseTwo(depth);
|
||||
|
||||
signal buf_we_w : STD_LOGIC;
|
||||
signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0);
|
||||
signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0);
|
||||
signal full : STD_LOGIC;
|
||||
signal empty : STD_LOGIC;
|
||||
signal almost_full : STD_LOGIC;
|
||||
signal almost_empty : STD_LOGIC;
|
||||
|
||||
begin
|
||||
|
||||
buf_we_w <= we_w;
|
||||
fifo_full <= full;
|
||||
fifo_empty <= empty;
|
||||
fifo_afull <= almost_full;
|
||||
fifo_aempty <= almost_empty;
|
||||
|
||||
gen_line:
|
||||
for c in color_range_t generate
|
||||
begin
|
||||
inst_dpram: entity work.dpram
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
data_width => data_width
|
||||
)
|
||||
PORT MAP(
|
||||
clka => clk_w,
|
||||
clkb => clk_r,
|
||||
en_a => '1',
|
||||
en_b => '1',
|
||||
we_a => buf_we_w,
|
||||
addr_a => ptr_w,
|
||||
addr_b => ptr_r,
|
||||
din_a => color_w(c),
|
||||
dout_b => color_r(c)
|
||||
);
|
||||
end generate;
|
||||
|
||||
inst_fifo_ctrl: entity work.async_fifo_ctrl
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => ADDR_WIDTH,
|
||||
almost_full_thresh => almost_full_thresh,
|
||||
almost_empty_thresh => almost_empty_thresh
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => rst,
|
||||
clk_w => clk_w,
|
||||
clk_r => clk_r,
|
||||
we => we_w,
|
||||
re => re_r,
|
||||
ptr_w => ptr_w,
|
||||
ptr_r => ptr_r,
|
||||
fifo_full => full,
|
||||
fifo_empty => empty,
|
||||
fifo_afull => almost_full,
|
||||
fifo_aempty => almost_empty
|
||||
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,223 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11:25:45 10/15/05
|
||||
-- Design Name:
|
||||
-- Module Name: vga_backend - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.vga_types.all;
|
||||
|
||||
entity vga_backend is
|
||||
Generic
|
||||
(
|
||||
sys_freq : integer := 100E6;
|
||||
fifo_depth : integer := 2048;
|
||||
fifo_almost_full_thresh : natural := 2000;
|
||||
fifo_almost_empty_thresh : natural := 48;
|
||||
tsvga : vga_timespec_t := ts_vga_800_600_72
|
||||
);
|
||||
Port
|
||||
(
|
||||
-- System signals
|
||||
sys_rst : in std_logic;
|
||||
sys_clk : in std_logic;
|
||||
vga_ready : out std_logic;
|
||||
|
||||
-- Buffered channel (Graphics plane)
|
||||
color_in : in color_t;
|
||||
color_fifo_we : in std_logic;
|
||||
color_fifo_full : out std_logic;
|
||||
color_fifo_afull : out std_logic;
|
||||
|
||||
-- Direct channel (Character plane)
|
||||
direct_color_in : in color_t;
|
||||
direct_draw_en : in std_logic;
|
||||
|
||||
-- Status signals
|
||||
stat_hsync : out std_logic;
|
||||
stat_vsync : out std_logic;
|
||||
stat_hready : out std_logic;
|
||||
stat_vready : out std_logic;
|
||||
stat_hscan : out std_logic;
|
||||
stat_vscan : out std_logic;
|
||||
stat_hpos : out natural range 0 to tsvga.ts_h.ncyc_scan-1;
|
||||
stat_vpos : out natural range 0 to tsvga.ts_v.ncyc_scan-1;
|
||||
|
||||
-- VGA domain signals
|
||||
vga_clk_out : out std_logic;
|
||||
vga_color_out : out color_t;
|
||||
vga_blank_n : out std_logic;
|
||||
vga_sync_n : out std_logic;
|
||||
vga_hsync : out std_logic;
|
||||
vga_vsync : out std_logic
|
||||
);
|
||||
end vga_backend;
|
||||
|
||||
architecture Behavioral of vga_backend is
|
||||
|
||||
signal scan_enable : std_logic;
|
||||
signal fifo_full : std_logic;
|
||||
signal fifo_empty : std_logic;
|
||||
signal fifo_almost_empty : std_logic;
|
||||
signal fifo_almost_full : std_logic;
|
||||
signal is_scan : std_logic;
|
||||
signal is_hscan : std_logic;
|
||||
signal is_vscan : std_logic;
|
||||
signal hsync : std_logic;
|
||||
signal vsync : std_logic;
|
||||
signal hready : std_logic;
|
||||
signal vready : std_logic;
|
||||
signal color : color_t;
|
||||
signal vga_clk : std_logic;
|
||||
signal dcm_locked : std_logic;
|
||||
signal rst : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
vga_clk_out <= vga_clk;
|
||||
vga_ready <= dcm_locked;
|
||||
|
||||
inst_clkgen: entity work.clkgen
|
||||
GENERIC MAP
|
||||
(
|
||||
sys_freq => sys_freq,
|
||||
tsvga => tsvga
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => sys_rst,
|
||||
clk => sys_clk,
|
||||
vga_clk => vga_clk,
|
||||
dcm_locked => dcm_locked
|
||||
);
|
||||
|
||||
inst_vga_timing: entity work.vga_timing
|
||||
GENERIC MAP
|
||||
(
|
||||
tsvga => tsvga
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
sys_rst => sys_rst,
|
||||
vga_clk => vga_clk,
|
||||
vga_ce => dcm_locked,
|
||||
sync_h => hsync,
|
||||
sync_v => vsync,
|
||||
scan_pos_h => stat_hpos,
|
||||
scan_pos_v => stat_vpos,
|
||||
is_scan_h => is_hscan,
|
||||
is_scan_v => is_vscan,
|
||||
scan_rdy_h => hready,
|
||||
scan_rdy_v => vready
|
||||
);
|
||||
|
||||
inst_linefifo: entity work.linefifo
|
||||
GENERIC MAP
|
||||
(
|
||||
depth => fifo_depth,
|
||||
almost_full_thresh => fifo_almost_full_thresh,
|
||||
almost_empty_thresh => fifo_almost_empty_thresh
|
||||
)
|
||||
PORT MAP(
|
||||
rst => sys_rst,
|
||||
clk_w => sys_clk,
|
||||
clk_r => vga_clk,
|
||||
we_w => color_fifo_we,
|
||||
re_r => is_scan,
|
||||
color_w => color_in,
|
||||
color_r => color,
|
||||
fifo_full => fifo_full,
|
||||
fifo_empty => fifo_empty,
|
||||
fifo_afull => fifo_almost_full,
|
||||
fifo_aempty => fifo_almost_empty
|
||||
|
||||
);
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
rst <= not dcm_locked;
|
||||
stat_hsync <= hsync;
|
||||
stat_vsync <= vsync;
|
||||
stat_hscan <= is_hscan;
|
||||
stat_vscan <= is_vscan;
|
||||
stat_hready <= hready;
|
||||
stat_vready <= vready;
|
||||
|
||||
vga_blank_n <= '1';
|
||||
vga_sync_n <= '0';
|
||||
is_scan <= is_hscan and is_vscan and scan_enable;
|
||||
|
||||
color_fifo_full <= fifo_full;
|
||||
color_fifo_afull <= fifo_almost_full;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
proc_vga_start:
|
||||
process (rst, vga_clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
scan_enable <= '0';
|
||||
elsif rising_edge(vga_clk) then
|
||||
if vsync = '1' then
|
||||
if fifo_empty = '0' then
|
||||
scan_enable <= '1';
|
||||
else
|
||||
scan_enable <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_vga_color_out:
|
||||
process (rst, vga_clk)
|
||||
variable do_scan : std_logic;
|
||||
begin
|
||||
if rst = '1' then
|
||||
do_scan := '0';
|
||||
elsif rising_edge(vga_clk) then
|
||||
vga_color_out <= (X"00", X"00", X"00");
|
||||
if do_scan = '1' then
|
||||
if direct_draw_en = '1' then
|
||||
vga_color_out <= direct_color_in;
|
||||
else
|
||||
vga_color_out <= color;
|
||||
end if;
|
||||
end if;
|
||||
do_scan := is_scan;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
proc_vga_sync_out:
|
||||
process (rst, vga_clk)
|
||||
variable hsync_r : std_logic;
|
||||
variable vsync_r : std_logic;
|
||||
begin
|
||||
if rst = '1' then
|
||||
vga_hsync <= tsvga.ts_h.sync_polarity;
|
||||
vga_vsync <= tsvga.ts_v.sync_polarity;
|
||||
hsync_r := tsvga.ts_h.sync_polarity;
|
||||
vsync_r := tsvga.ts_v.sync_polarity;
|
||||
elsif rising_edge(vga_clk) then
|
||||
vga_hsync <= hsync_r;
|
||||
vga_vsync <= vsync_r;
|
||||
hsync_r := hsync xor (not tsvga.ts_h.sync_polarity);
|
||||
vsync_r := vsync xor (not tsvga.ts_v.sync_polarity);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,127 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11:15:39 10/21/05
|
||||
-- Design Name:
|
||||
-- Module Name: fsm_scan - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.vga_types.all;
|
||||
|
||||
entity vga_sync is
|
||||
Generic
|
||||
(
|
||||
ts : scan_timespec_t := (4,2,1,3,'0')
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
ce : in std_logic;
|
||||
pos : out natural range 0 to ts.ncyc_scan-1;
|
||||
sync : out std_logic;
|
||||
is_scan : out std_logic;
|
||||
rdy_scan : out std_logic
|
||||
);
|
||||
end vga_sync;
|
||||
|
||||
architecture Behavioral of vga_sync is
|
||||
|
||||
type timing_state_t is (st_init, st_scan, st_front, st_sync, st_back);
|
||||
|
||||
-- Counter
|
||||
signal state, next_state : timing_state_t;
|
||||
signal count_srst : std_logic;
|
||||
signal count : natural range 0 to ts.ncyc_scan-1;
|
||||
|
||||
begin
|
||||
|
||||
pos <= count;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
counter:
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if ce = '1' then
|
||||
if count_srst = '1' then
|
||||
count <= 0;
|
||||
else
|
||||
count <= count + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
SYNC_TIMING:
|
||||
process (state, count)
|
||||
begin
|
||||
count_srst <= '0';
|
||||
rdy_scan <= '0';
|
||||
is_scan <= '0';
|
||||
sync <= '0';
|
||||
|
||||
next_state <= state; --default is to stay in current state
|
||||
|
||||
case (state) is
|
||||
|
||||
when st_init =>
|
||||
count_srst <= '1';
|
||||
next_state <= st_front;
|
||||
when st_front =>
|
||||
if count = ts.ncyc_porch_front - 1 then
|
||||
count_srst <= '1';
|
||||
next_state <= st_sync;
|
||||
end if;
|
||||
when st_sync =>
|
||||
sync <= '1';
|
||||
if count = ts.ncyc_sync_pulse - 1 then
|
||||
count_srst <= '1';
|
||||
next_state <= st_back;
|
||||
end if;
|
||||
when st_back =>
|
||||
if count = ts.ncyc_porch_back - 1 then
|
||||
count_srst <= '1';
|
||||
next_state <= st_scan;
|
||||
end if;
|
||||
when st_scan =>
|
||||
is_scan <= '1';
|
||||
if count = ts.ncyc_scan - 1 then
|
||||
count_srst <= '1';
|
||||
rdy_scan <= '1';
|
||||
next_state <= st_front;
|
||||
end if;
|
||||
when others =>
|
||||
next_state <= st_init;
|
||||
|
||||
end case;
|
||||
end process;
|
||||
|
||||
SYNC_TIMING_NEXT:
|
||||
process (rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
state <= st_init;
|
||||
elsif rising_edge(clk) and ce = '1' then
|
||||
state <= next_state;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
end Behavioral;
|
||||
@@ -1,102 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 11:25:45 10/15/05
|
||||
-- Design Name:
|
||||
-- Module Name: vga_ctrl_core - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.vga_types.all;
|
||||
|
||||
entity vga_timing is
|
||||
Generic
|
||||
(
|
||||
tsvga : vga_timespec_t := ts_vga_800_600_72
|
||||
);
|
||||
Port
|
||||
(
|
||||
sys_rst : in std_logic;
|
||||
vga_clk : in std_logic;
|
||||
vga_ce : in std_logic;
|
||||
sync_h : out std_logic;
|
||||
sync_v : out std_logic;
|
||||
scan_pos_h : out natural range 0 to tsvga.ts_h.ncyc_scan-1;
|
||||
scan_pos_v : out natural range 0 to tsvga.ts_v.ncyc_scan-1;
|
||||
is_scan_h : out std_logic;
|
||||
is_scan_v : out std_logic;
|
||||
scan_rdy_h : out std_logic;
|
||||
scan_rdy_v : out std_logic
|
||||
);
|
||||
end vga_timing;
|
||||
|
||||
architecture Behavioral of vga_timing is
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
signal is_scan_h_i : std_logic;
|
||||
signal is_scan_v_i : std_logic;
|
||||
signal scan_rdy_h_i : std_logic;
|
||||
signal scan_rdy_v_i : std_logic;
|
||||
signal sync_h_i : std_logic;
|
||||
signal sync_v_i : std_logic;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
is_scan_h <= is_scan_h_i;
|
||||
is_scan_v <= is_scan_v_i;
|
||||
scan_rdy_h <= scan_rdy_h_i;
|
||||
scan_rdy_v <= scan_rdy_v_i;
|
||||
sync_h <= sync_h_i;
|
||||
sync_v <= sync_v_i;
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
inst_vga_sync_h: entity work.vga_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
ts => tsvga.ts_h
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => sys_rst,
|
||||
clk => vga_clk,
|
||||
ce => vga_ce,
|
||||
pos => scan_pos_h,
|
||||
sync => sync_h_i,
|
||||
is_scan => is_scan_h_i,
|
||||
rdy_scan => scan_rdy_h_i
|
||||
);
|
||||
|
||||
inst_vga_sync_v: entity work.vga_sync
|
||||
GENERIC MAP
|
||||
(
|
||||
ts => tsvga.ts_v
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => sys_rst,
|
||||
clk => vga_clk,
|
||||
ce => scan_rdy_h_i,
|
||||
pos => scan_pos_v,
|
||||
sync => sync_v_i,
|
||||
is_scan => is_scan_v_i,
|
||||
rdy_scan => scan_rdy_v_i
|
||||
);
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,213 +0,0 @@
|
||||
-- Package File Template
|
||||
--
|
||||
-- Purpose: This package defines supplemental types, subtypes,
|
||||
-- constants, and functions
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
package vga_types is
|
||||
|
||||
-- Constants
|
||||
|
||||
-- Types
|
||||
type color_range_t is (r, g, b);
|
||||
type color_t is array (color_range_t) of unsigned(7 downto 0);
|
||||
|
||||
type scan_timespec_t is
|
||||
record
|
||||
ncyc_scan : integer;
|
||||
ncyc_porch_front : integer;
|
||||
ncyc_sync_pulse : integer;
|
||||
ncyc_porch_back : integer;
|
||||
sync_polarity : std_logic;
|
||||
end record;
|
||||
|
||||
type vga_timespec_t is
|
||||
record
|
||||
f_pxl_clk : integer;
|
||||
nfps : integer;
|
||||
ts_h : scan_timespec_t;
|
||||
ts_v : scan_timespec_t;
|
||||
end record;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Common timimg specifications
|
||||
-----------------------------------------------------------------------
|
||||
-- For test bench (not for H/W use)
|
||||
constant ts_vga_testbench : vga_timespec_t :=
|
||||
(
|
||||
f_pxl_clk => 100E6,
|
||||
nfps => 6,
|
||||
ts_h => (8,5,2,3,'0'),
|
||||
ts_v => (6,4,2,3,'0')
|
||||
);
|
||||
|
||||
-- 640 x 480 @ 60 Hz (not recommended)
|
||||
constant ts_vga_640_480_60 : vga_timespec_t :=
|
||||
(
|
||||
f_pxl_clk => 25175000,
|
||||
nfps => 60,
|
||||
ts_h => (640,16,96,48,'0'),
|
||||
ts_v => (480,11,2,31,'0')
|
||||
);
|
||||
|
||||
-- 640 x 480 @ 72 Hz (not recommended)
|
||||
constant ts_vga_640_480_72 : vga_timespec_t :=
|
||||
(
|
||||
f_pxl_clk => 31500000,
|
||||
nfps => 72,
|
||||
ts_h => (640,24,40,128,'0'),
|
||||
ts_v => (480,9,3,28,'0')
|
||||
);
|
||||
|
||||
-- 800 x 600 @ 60 Hz (OK)
|
||||
constant ts_vga_800_600_60 : vga_timespec_t :=
|
||||
(
|
||||
f_pxl_clk => 40000000,
|
||||
nfps => 60,
|
||||
ts_h => (800,40,128,88,'0'),
|
||||
ts_v => (600,1,4,23,'0')
|
||||
);
|
||||
|
||||
-- 800 x 600 @ 72 Hz (OK)
|
||||
constant ts_vga_800_600_72 : vga_timespec_t :=
|
||||
(
|
||||
f_pxl_clk => 50000000,
|
||||
nfps => 72,
|
||||
ts_h => (800,56,120,64,'0'),
|
||||
ts_v => (600,37,6,23,'0')
|
||||
);
|
||||
|
||||
-- 1024 x 768 @ 60 Hz (Noisy)
|
||||
constant ts_vga_1024_768_60 : vga_timespec_t :=
|
||||
(
|
||||
f_pxl_clk => 65000000,
|
||||
nfps => 60,
|
||||
ts_h => (1024,24,136,160,'0'),
|
||||
ts_v => (768,3,6,29,'0')
|
||||
);
|
||||
|
||||
-- 1024 x 768 @ 70 Hz (OK)
|
||||
constant ts_vga_1024_768_70 : vga_timespec_t :=
|
||||
(
|
||||
f_pxl_clk => 75000000,
|
||||
nfps => 70,
|
||||
ts_h => (1024,24,136,144,'0'),
|
||||
ts_v => (768,3,6,29,'0')
|
||||
);
|
||||
|
||||
-- 1280 x 1024 @ 70 Hz (Noisy)
|
||||
constant ts_vga_1280_1024_70 : vga_timespec_t :=
|
||||
(
|
||||
f_pxl_clk => 125000000,
|
||||
nfps => 70,
|
||||
ts_h => (1280,16,176,192,'0'),
|
||||
ts_v => (1024,3,3,42,'0')
|
||||
);
|
||||
|
||||
-- 1280 x 1024 @ 72 Hz (OK)
|
||||
constant ts_vga_1280_1024_72 : vga_timespec_t :=
|
||||
(
|
||||
f_pxl_clk => 130000000,
|
||||
nfps => 72,
|
||||
ts_h => (1280,32,160,224,'0'),
|
||||
ts_v => (1024,2,2,33,'0')
|
||||
);
|
||||
|
||||
-- Functions
|
||||
function NextPowerOfTwo(x : natural) return natural;
|
||||
function NextExpBaseTwo(x : natural) return natural;
|
||||
function GCD(a, b : natural) return natural;
|
||||
function LCM(a, b : natural) return natural;
|
||||
function DCM_PERIOD(f_sys_hz : natural) return real;
|
||||
function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural;
|
||||
function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural;
|
||||
|
||||
end vga_types;
|
||||
|
||||
|
||||
package body vga_types is
|
||||
|
||||
function NextExpBaseTwo(x : natural) return natural is
|
||||
begin
|
||||
return natural(ceil(log2(real(x))));
|
||||
end NextExpBaseTwo;
|
||||
|
||||
function NextPowerOfTwo(x : natural) return natural is
|
||||
begin
|
||||
|
||||
return 2**NextExpBaseTwo(x);
|
||||
end NextPowerOfTwo;
|
||||
|
||||
function GCD(a, b : natural) return natural is
|
||||
variable aa : natural;
|
||||
variable bb : natural;
|
||||
begin
|
||||
aa := a;
|
||||
bb := b;
|
||||
while bb /= 0 loop
|
||||
if aa > bb then
|
||||
aa := aa - bb;
|
||||
else
|
||||
bb := bb - aa;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
return aa;
|
||||
|
||||
end GCD;
|
||||
|
||||
function LCM(a, b : natural) return natural is
|
||||
begin
|
||||
|
||||
return (a * b)/GCD(a, b);
|
||||
|
||||
end LCM;
|
||||
|
||||
function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural is
|
||||
variable f_sys_mhz : natural;
|
||||
variable f_vga_mhz : natural;
|
||||
variable m : natural;
|
||||
begin
|
||||
f_sys_mhz := f_sys_hz/1E6;
|
||||
f_vga_mhz := f_vga_hz/1E6;
|
||||
m := f_vga_mhz/GCD(f_sys_mhz, f_vga_mhz);
|
||||
|
||||
if m = 1 then
|
||||
m := 2;
|
||||
end if;
|
||||
|
||||
return m;
|
||||
|
||||
end DCM_FREQ_M;
|
||||
|
||||
function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural is
|
||||
variable f_sys_mhz : natural;
|
||||
variable f_vga_mhz : natural;
|
||||
variable m : natural;
|
||||
variable d : natural;
|
||||
begin
|
||||
m := DCM_FREQ_M(f_sys_hz, f_vga_hz);
|
||||
f_sys_mhz := f_sys_hz/1E6;
|
||||
f_vga_mhz := f_vga_hz/1E6;
|
||||
d := m*f_sys_mhz/f_vga_mhz;
|
||||
|
||||
return d;
|
||||
|
||||
end DCM_FREQ_D;
|
||||
|
||||
function DCM_PERIOD(f_sys_hz : natural) return real is
|
||||
begin
|
||||
|
||||
return 1.0E9/real(f_sys_hz);
|
||||
|
||||
end DCM_PERIOD;
|
||||
|
||||
|
||||
end vga_types;
|
||||
|
||||
|
||||
@@ -1,37 +0,0 @@
|
||||
function eval_filter(N)
|
||||
omega_lp = 0.15
|
||||
omega_hp = 0.05
|
||||
|
||||
omega_bp_m = 0.02;
|
||||
bw2_bp = 0.02;
|
||||
|
||||
lp = lowpass(N, omega_lp, 1.0);
|
||||
coef_lp = hann(N)'.*lp./sum(lp.^2);
|
||||
|
||||
hp = lowpass(N, 0.5-omega_hp, 1.0).*cos(pi*(0:N-1));
|
||||
coef_hp = hp./sum(hp.^2).*hann(N)';
|
||||
|
||||
bp = lowpass(N, bw2_bp/2, 1.0).*cos(2*pi*omega_bp_m*(0:N-1));
|
||||
coef_bp = bp./sum(bp.^2).*hann(N)';
|
||||
|
||||
abs_lp = 20*log10(abs(fft(coef_lp)));
|
||||
abs_hp = 20*log10(abs(fft(coef_hp)));
|
||||
abs_bp = 20*log10(abs(fft(coef_bp)));
|
||||
|
||||
close all;
|
||||
plot((0:N/2)/N, abs_lp(1:N/2+1));grid;
|
||||
figure
|
||||
plot((0:N/2)/N, abs_hp(1:N/2+1));grid;
|
||||
figure
|
||||
plot((0:N/2)/N, abs_bp(1:N/2+1));grid;
|
||||
|
||||
figure
|
||||
plot((0:N-1), coef_lp);grid;
|
||||
figure
|
||||
plot((0:N-1), coef_hp);grid;
|
||||
figure
|
||||
plot((0:N-1), coef_bp);grid;
|
||||
|
||||
mean_lp = mean(coef_lp-mean(coef_lp))
|
||||
mean_hp = mean(coef_hp)
|
||||
mean_bp = mean(coef_bp)
|
||||
@@ -1,20 +0,0 @@
|
||||
function coef = lowpass(N, omega, scale)
|
||||
|
||||
phi = 0;
|
||||
dphi = 2*omega;
|
||||
if (mod(N, 2) == 0)
|
||||
M = N/2;
|
||||
for i=0:M-1,
|
||||
phi = phi + dphi;
|
||||
coef(M+i+1) = scale*sinc(phi);
|
||||
coef(M-i-1+1) = coef(M+i+1);
|
||||
end;
|
||||
else
|
||||
M = (N-1)/2;
|
||||
for i=1:M,
|
||||
phi = phi + dphi;
|
||||
coef(M+i+1) = scale*sinc(phi);
|
||||
coef(M-i+1) = coef(M+i+1);
|
||||
end;
|
||||
coef(M+1) = scale*Sinc(0.0);
|
||||
end;
|
||||
@@ -1,16 +0,0 @@
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd"
|
||||
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
|
||||
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
|
||||
vcom -explicit -93 "../src/filter_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fir_stage_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fir_stage.vhd"
|
||||
vcom -explicit -93 "../src/fir_iterative_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fir_iterative.vhd"
|
||||
vcom -explicit -93 "../src/tb_fir_iterative.vhd"
|
||||
vsim -t 1ps -lib work tb_fir_iterative
|
||||
do {tb_fir_iterative.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 20us
|
||||
@@ -1,86 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/coeffs
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/xi
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/yo
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem
|
||||
add wave -noupdate -divider {Xmem Dual}
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/coeffs
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
|
||||
add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi
|
||||
add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/y_valid
|
||||
add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
|
||||
add wave -noupdate -divider {FIR Stage}
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/in_valid
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out_clr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/valid
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/p_valid
|
||||
add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
|
||||
add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/out_valid
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {1892287 ps} 0}
|
||||
configure wave -namecolwidth 140
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {1750644 ps} {2771198 ps}
|
||||
Binary file not shown.
@@ -1,16 +0,0 @@
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd"
|
||||
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
|
||||
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
|
||||
vcom -explicit -93 "../src/filter_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fir_stage_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fir_stage.vhd"
|
||||
vcom -explicit -93 "../src/fir_parallel_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fir_parallel.vhd"
|
||||
vcom -explicit -93 "../src/tb_fir_parallel.vhd"
|
||||
vsim -t 1ps -lib work tb_fir_parallel
|
||||
do {tb_fir_parallel.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 1000us
|
||||
@@ -1,29 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_fir_parallel/clk
|
||||
add wave -noupdate -format Logic /tb_fir_parallel/srst
|
||||
add wave -noupdate -format Logic /tb_fir_parallel/in_valid
|
||||
add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/x_in
|
||||
add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/y_out
|
||||
add wave -noupdate -format Logic /tb_fir_parallel/out_valid
|
||||
add wave -noupdate -format Logic /tb_fir_parallel/fileout_enable
|
||||
add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/xi
|
||||
add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/yo
|
||||
add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/coeff_in
|
||||
add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/uut_fir_parallel/h
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {19450000 ps} 0}
|
||||
configure wave -namecolwidth 140
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {25152750 ps}
|
||||
@@ -1,10 +0,0 @@
|
||||
% Read data
|
||||
function tb_fir_results()
|
||||
fir = TEXTREAD('fir.txt')';
|
||||
|
||||
N= length(fir);
|
||||
|
||||
% Output
|
||||
close all;
|
||||
plot(0:N-1, fir); grid;
|
||||
|
||||
@@ -1,14 +0,0 @@
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd"
|
||||
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
|
||||
vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
|
||||
vcom -explicit -93 "../src/filter_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fir_stage_pkg.vhd"
|
||||
vcom -explicit -93 "../src/fir_stage.vhd"
|
||||
vcom -explicit -93 "../src/tb_fir_stage.vhd"
|
||||
vsim -t 1ps -lib work tb_fir_stage
|
||||
do {tb_fir_stage.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 2us
|
||||
@@ -1,31 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_fir_stage/clk
|
||||
add wave -noupdate -format Logic /tb_fir_stage/srst
|
||||
add wave -noupdate -divider Input
|
||||
add wave -noupdate -format Logic /tb_fir_stage/in_valid
|
||||
add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x_in
|
||||
add wave -noupdate -format Literal /tb_fir_stage/xi
|
||||
add wave -noupdate -divider Output
|
||||
add wave -noupdate -format Logic /tb_fir_stage/out_valid
|
||||
add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y_out
|
||||
add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_stage/yo
|
||||
add wave -noupdate -divider {Stage signals}
|
||||
add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x
|
||||
add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {1655000 ps} 0}
|
||||
configure wave -namecolwidth 140
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {2100 ns}
|
||||
@@ -1,227 +0,0 @@
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
package filter_pkg is
|
||||
|
||||
constant pi : real := 3.141592653589793e+000;
|
||||
type real_array_t is array (natural range <>) of real;
|
||||
|
||||
function FilterCoef_Lowpass (N : positive; omega, amp : real) return real_array_t;
|
||||
function FilterCoef_Highpass (N : positive; omega, amp : real) return real_array_t;
|
||||
function FilterCoef_Bandpass (N : positive; bw2, omega_m, amp : real) return real_array_t;
|
||||
function FilterCoef_Delta (N:positive; delay:natural; amp:real) return real_array_t;
|
||||
function Window_Hamming (x : real_array_t) return real_array_t;
|
||||
function Window_VonHann (x : real_array_t) return real_array_t;
|
||||
function Window_Blackman (x : real_array_t) return real_array_t;
|
||||
function Sinc (x : real) return real;
|
||||
function FilterEnergy (x : real_array_t) return real;
|
||||
function FilterMean (x : real_array_t) return real;
|
||||
function FilterScale (x : real_array_t; scale : real) return real_array_t;
|
||||
function FilterTestCoef (N : positive) return real_array_t;
|
||||
function NextPowerOfTwo(x : real) return natural;
|
||||
|
||||
end; -- package filter_pkg;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
package body filter_pkg is
|
||||
|
||||
function Prototype_Lowpass (N : positive; omega : real) return real_array_t is
|
||||
variable res : real_array_t(0 to N-1);
|
||||
variable M : positive;
|
||||
variable phi : real := 0.0;
|
||||
variable dphi : real := 2.0*pi*omega;
|
||||
begin
|
||||
if (N mod 2) = 0 then
|
||||
M := N/2;
|
||||
for i in 0 to M-1 loop
|
||||
phi := phi + dphi;
|
||||
res(M+i) := Sinc(phi);
|
||||
res(M-i-1) := res(M+i);
|
||||
end loop;
|
||||
else
|
||||
M := (N-1)/2;
|
||||
for i in 1 to M loop
|
||||
phi := phi + dphi;
|
||||
res(M+i) := Sinc(phi);
|
||||
res(M-i) := res(M+i);
|
||||
end loop;
|
||||
res(M) := Sinc(0.0);
|
||||
end if;
|
||||
return res;
|
||||
|
||||
end Prototype_Lowpass;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function FilterCoef_Lowpass (N : positive; omega, amp : real) return real_array_t is
|
||||
variable lp : real_array_t(0 to N-1);
|
||||
begin
|
||||
lp := Prototype_Lowpass(N, omega);
|
||||
|
||||
return Window_VonHann(FilterScale(lp, amp/FilterEnergy(lp)));
|
||||
|
||||
end FilterCoef_Lowpass;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function FilterCoef_Highpass (N : positive; omega, amp : real) return real_array_t is
|
||||
variable lp, res : real_array_t(0 to N-1);
|
||||
variable phi : real := 0.0;
|
||||
variable dphi : real := pi;
|
||||
begin
|
||||
lp := Prototype_Lowpass(N, 0.5-omega);
|
||||
|
||||
for i in 0 to N-1 loop
|
||||
res(i) := lp(i) * cos(phi);
|
||||
phi := phi + dphi;
|
||||
end loop;
|
||||
|
||||
return Window_VonHann(FilterScale(res, amp/FilterEnergy(lp)));
|
||||
|
||||
end FilterCoef_Highpass;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function FilterCoef_Bandpass (N : positive; bw2, omega_m, amp : real) return real_array_t is
|
||||
variable lp, res, mean, sum : real_array_t(0 to N-1);
|
||||
variable phi : real := 0.0;
|
||||
variable dphi : real := 2.0*pi*omega_m;
|
||||
begin
|
||||
lp := Prototype_Lowpass(N, bw2/2.0);
|
||||
|
||||
for i in 0 to N-1 loop
|
||||
res(i) := lp(i) * cos(phi);
|
||||
phi := phi + dphi;
|
||||
end loop;
|
||||
|
||||
return Window_VonHann(FilterScale(res, amp/FilterEnergy(lp)));
|
||||
|
||||
end FilterCoef_Bandpass;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function FilterCoef_Delta (N:positive; delay:natural; amp:real) return real_array_t is
|
||||
variable res : real_array_t(0 to N-1);
|
||||
begin
|
||||
for i in 0 to N-1 loop
|
||||
res(i) := 0.0;
|
||||
end loop;
|
||||
res(delay) := amp;
|
||||
|
||||
return res;
|
||||
|
||||
end FilterCoef_Delta;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function FilterTestCoef (N : positive) return real_array_t is
|
||||
variable phi : real := 0.0;
|
||||
variable dphi : real := 1.0/real(N);
|
||||
variable res : real_array_t(0 to N-1);
|
||||
begin
|
||||
for i in 0 to N-1 loop
|
||||
res(i) := phi;
|
||||
phi := phi + dphi;
|
||||
end loop;
|
||||
return res;
|
||||
|
||||
end FilterTestCoef;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function Window_Hamming (x : real_array_t) return real_array_t is
|
||||
variable res : real_array_t(x'range);
|
||||
variable phi : real := 0.0;
|
||||
variable dphi : real := 2.0*pi/real(x'length-1);
|
||||
begin
|
||||
for i in x'range loop
|
||||
res(i) := x(i) * (0.54 - 0.46*(cos(phi)));
|
||||
phi := phi + dphi;
|
||||
end loop;
|
||||
return res;
|
||||
|
||||
end Window_Hamming;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function Window_VonHann (x : real_array_t) return real_array_t is
|
||||
variable res : real_array_t(x'range);
|
||||
variable phi : real := 0.0;
|
||||
variable dphi : real := 2.0*pi/real(x'length-1);
|
||||
begin
|
||||
for i in x'range loop
|
||||
res(i) := 0.5 * x(i) * (1.0 - (cos(phi)));
|
||||
phi := phi + dphi;
|
||||
end loop;
|
||||
return res;
|
||||
|
||||
end Window_VonHann;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function Window_Blackman (x : real_array_t) return real_array_t is
|
||||
variable res : real_array_t(0 to x'length-1);
|
||||
variable phi : real := 0.0;
|
||||
variable dphi : real := 2.0*pi/real(x'length-1);
|
||||
begin
|
||||
for i in x'range loop
|
||||
res(i) := x(i) * (0.42 - 0.5*cos(phi) + 0.08*cos(2.0*phi));
|
||||
phi := phi + dphi;
|
||||
end loop;
|
||||
return res;
|
||||
|
||||
end Window_Blackman;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function Sinc (x : real) return real is
|
||||
variable res : real := 1.0;
|
||||
begin
|
||||
if x /= 0.0 then
|
||||
res := sin(x)/x;
|
||||
end if;
|
||||
|
||||
return res;
|
||||
|
||||
end Sinc;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function FilterScale (x : real_array_t; scale : real) return real_array_t is
|
||||
variable res : real_array_t(x'range);
|
||||
begin
|
||||
for i in x'range loop
|
||||
res(i) := scale * x(i);
|
||||
end loop;
|
||||
|
||||
return res;
|
||||
|
||||
end FilterScale;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function FilterEnergy (x : real_array_t) return real is
|
||||
variable res : real := 0.0;
|
||||
begin
|
||||
for i in x'range loop
|
||||
res := res + x(i)*x(i);
|
||||
end loop;
|
||||
|
||||
return res;
|
||||
|
||||
end FilterEnergy;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function FilterMean (x : real_array_t) return real is
|
||||
variable res : real := 0.0;
|
||||
begin
|
||||
for i in x'range loop
|
||||
res := res + x(i);
|
||||
end loop;
|
||||
|
||||
return res/real(x'length);
|
||||
|
||||
end FilterMean;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function NextPowerOfTwo(x : real) return natural is
|
||||
begin
|
||||
return integer(ceil(log2(x)));
|
||||
|
||||
end NextPowerOfTwo;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
end; -- package filter_pkg;
|
||||
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Reference in New Issue
Block a user