- added POR for CPU
- UART set to 460800 baud and added more FIFO depth
git-svn-id: http://moon:8086/svn/vhdl/trunk@1367 cc03376c-175c-47c8-b038-4cd826a8556b
- reduce uart buffer to introduce more delay (work around for bus timeout)
git-svn-id: http://moon:8086/svn/vhdl/trunk@1361 cc03376c-175c-47c8-b038-4cd826a8556b