jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[TB]

Browse Source 
- use correct hello.elf.flash.bin

git-svn-id: http://moon:8086/svn/vhdl/trunk@1080 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-14 11:00:20 +00:00
parent db9e21023c
commit ff20480866
3 changed files with 2 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/sim/hello.flash.bin
BIN
View File
Binary file not shown.
lib/CPUs/MIPS/sim/tb_mips_top.fdo
+2 -8
View File
@@ -5,9 +5,6 @@ vlib work
# RAMS # RAMS
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd" vcom -explicit -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd" vcom -explicit -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
vcom -explicit -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
vcom -explicit -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
# FIFOS # FIFOS
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
@@ -18,11 +15,8 @@ vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd" vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
# UART # UART
#vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd" vcom -explicit -93 "../../../uart/uart_rx_sim.vhd"
#vcom -explicit -93 "../../../uart/kcuart_rx.vhd" vcom -explicit -93 "../../../uart/uart_tx_sim.vhd"
#vcom -explicit -93 "../../../uart/kcuart_tx.vhd"
#vcom -explicit -93 "../../../uart/uart_rx.vhd"
#vcom -explicit -93 "../../../uart/uart_tx.vhd"
vcom -explicit -93 "../../../uart/uart_wb.vhd" vcom -explicit -93 "../../../uart/uart_wb.vhd"
# GPIO # GPIO
lib/CPUs/MIPS/src/tb_mips_top.vhd
-6
View File
@@ -328,10 +328,6 @@ inst_sram_port : entity work.async_port_wb
); );
inst_uart : entity work.uart_wb inst_uart : entity work.uart_wb
GENERIC MAP
(
simulate_tx => true
)
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
@@ -399,8 +395,6 @@ SRAM_WRITE:
FLASH_READ: FLASH_READ:
process(rst, flash_cs_n, flash_oe_n, flash_a) process(rst, flash_cs_n, flash_oe_n, flash_a)
type file_t is file of integer; type file_t is file of integer;
-- file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
-- file load_flash : file_t open read_mode is "test_timer.elf.flash.bin";
file load_flash : file_t open read_mode is "hello.elf.flash.bin"; file load_flash : file_t open read_mode is "hello.elf.flash.bin";
variable instr : integer; variable instr : integer;
variable index : natural; variable index : natural;