diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd index 4388ed5..6dc0c01 100644 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd @@ -210,7 +210,7 @@ begin ctrl_out.exc_ack <= '1'; cop_ir <= ID_stage.IR; cop_ir_en <= ID_stage.ctrl.cop_instr_en; - cop_dout <= EX_stage.reg_b_in; -- dmem_din when MEM_stage.ctrl.dmem_en = '1' else MEM_stage.ex_result; + cop_dout <= EX_stage.reg_b; -- dmem_din when MEM_stage.ctrl.dmem_en = '1' else MEM_stage.ex_result; -------------------------------------------------------------------------- -- Muldiv @@ -222,7 +222,7 @@ inst_muldiv: muldiv clk => clk, hilo_we => EX_stage.ctrl.mul_hilo_we, din_hi => EX_stage.reg_a, - din_lo => EX_stage.reg_b_in, + din_lo => EX_stage.reg_b, mul_divn => EX_stage.ctrl.mul_mul_divn, start => EX_stage.ctrl.mul_start, s_un => EX_stage.ctrl.mul_s_un, @@ -512,11 +512,11 @@ proc_stage_fwd_a: begin data := reg_a; if hdu.alu_fwd_a_ex then - data := EX_stage.reg_b; + data := EX_stage.result; elsif hdu.alu_fwd_a_mem then - data := MEM_stage.reg_b; + data := MEM_stage.result; elsif hdu.alu_fwd_a_wb then - data := WB_stage.reg_b; + data := WB_stage.result; end if; ID_stage.reg_a <= to_mips_01(data) after 1 ns; @@ -529,11 +529,11 @@ proc_stage_fwd_b: begin data := reg_b; if hdu.alu_fwd_b_ex then - data := EX_stage.reg_b; + data := EX_stage.result; elsif hdu.alu_fwd_b_mem then - data := MEM_stage.reg_b; + data := MEM_stage.result; elsif hdu.alu_fwd_b_wb then - data := WB_stage.reg_b; + data := WB_stage.result; end if; ID_stage.reg_b <= to_mips_01(data) after 1 ns; @@ -578,7 +578,7 @@ inst_reg_dual: reg_dual we => WB_stage.reg_we, en => '1', wptr => WB_stage.reg_wptr, - din => WB_stage.reg_b, + din => WB_stage.result, rptr_a => ID_stage.reg_a_rptr, rptr_b => ID_stage.reg_b_rptr, dout_a => reg_a, @@ -590,7 +590,7 @@ inst_reg_dual: reg_dual -------------------------------------------------------------------------- EX_stage.reg_a_rptr <= extract_rs(EX_stage.IR); EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR); - EX_stage.reg_b <= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result; + EX_stage.result <= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result; proc_stage_ID_EX_1: process(clk_1) @@ -611,7 +611,7 @@ proc_stage_ID_EX_1: EX_stage.va <= ID_stage.va; EX_stage.reg_a <= ID_stage.reg_a; - EX_stage.reg_b_in <= ID_stage.reg_b; + EX_stage.reg_b <= ID_stage.reg_b; EX_stage.events_in <= ID_stage.events; EX_stage.ctrl <= ID_stage.ctrl; EX_stage.reg_write <= ID_stage.reg_write; @@ -700,7 +700,7 @@ proc_stage_DMEM_ADDR: end if; end if; end process; - dmem_src <= cop_din when EX_stage.ctrl.cop_instr_en = '1' else EX_stage.reg_b_in; + dmem_src <= cop_din when EX_stage.ctrl.cop_instr_en = '1' else EX_stage.reg_b; dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp) after 1 ns; dmem_en <= EX_stage.dmem_en; dmem_we <= EX_stage.ctrl.dmem_we; @@ -821,7 +821,7 @@ inst_shifter: shifter PORT MAP ( shift_ctrl => EX_stage.shift_ctrl, - din => EX_stage.reg_b_in, + din => EX_stage.reg_b, dout => EX_stage.alu_op2_s ); @@ -868,7 +868,8 @@ proc_stage_MEM_n: elsif sdu.MEM_stall = '0' then MEM_stage.nop <= sdu.MEM_nop; MEM_stage.reg_a <= EX_stage.reg_a; - MEM_stage.reg_b_in <= EX_stage.reg_b; + MEM_stage.reg_b <= EX_stage.reg_b; + MEM_stage.result_in <= EX_stage.result; MEM_stage.op <= EX_stage.op; MEM_stage.epc <= EX_stage.epc; MEM_stage.pcn <= EX_stage.pcn; @@ -882,17 +883,17 @@ proc_stage_MEM_n: MEM_stage.reg_wptr <= EX_stage.reg_wptr; if MEM_stage.reg_wptr = EX_stage.reg_wptr then if (EX_stage.ctrl.dmem_en and MEM_stage.ctrl.dmem_en) = '1' then - MEM_stage.reg_b_in <= MEM_stage.reg_b; + MEM_stage.result_in <= MEM_stage.result; end if; else - MEM_stage.reg_b_in <= EX_stage.reg_b_in; + MEM_stage.result_in <= EX_stage.reg_b; end if; if EX_stage.ctrl.cop_instr_en = '1' then if EX_stage.ctrl.cop_read = '1' then - MEM_stage.reg_b_in <= cop_din; + MEM_stage.result_in <= cop_din; end if; elsif EX_stage.ctrl.dmem_en = '0' then - MEM_stage.reg_b_in <= EX_stage.reg_b; + MEM_stage.result_in <= EX_stage.result; end if; if sdu.MEM_nop = '1' then MEM_stage.reg_we <= '0'; @@ -909,7 +910,7 @@ proc_stage_MEM_mux: variable data : word_t; variable be : unsigned(3 downto 0); begin - data := MEM_stage.reg_b_in; + data := MEM_stage.result_in; if MEM_stage.ctrl.reg_link = '1' then data := MEM_stage.epc + 8; elsif MEM_stage.ctrl.dmem_en = '1' then @@ -929,7 +930,7 @@ proc_stage_MEM_mux: data(31 downto 24) := temp2(31 downto 24); end if; end if; - MEM_stage.reg_b <= data after 1 ns; + MEM_stage.result <= data after 1 ns; end process; @@ -966,6 +967,7 @@ proc_stage_WB_p: WB_stage.nop <= sdu.WB_nop; WB_stage.reg_a <= MEM_stage.reg_a; WB_stage.reg_b <= MEM_stage.reg_b; + WB_stage.result <= MEM_stage.result; WB_stage.op <= MEM_stage.op; WB_stage.epc <= MEM_stage.epc; branch_delay := MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works diff --git a/lib/CPUs/MIPS/src/core/mips_types.vhd b/lib/CPUs/MIPS/src/core/mips_types.vhd index df30cad..3e096fd 100644 --- a/lib/CPUs/MIPS/src/core/mips_types.vhd +++ b/lib/CPUs/MIPS/src/core/mips_types.vhd @@ -485,7 +485,7 @@ package mips_types is pcn : word_t; reg_a : word_t; reg_b : word_t; - reg_b_in : word_t; + result : word_t; ctrl : ctrl_lines_t; shift_ctrl : shift_ctrl_t; alu_op1 : word_t; @@ -513,7 +513,8 @@ package mips_types is pcn : word_t; reg_a : word_t; reg_b : word_t; - reg_b_in : word_t; + result : word_t; + result_in : word_t; ctrl : ctrl_lines_t; reg_wptr : reg_ptr_t; reg_we : STD_LOGIC; @@ -529,6 +530,7 @@ package mips_types is epc : word_t; reg_a : word_t; reg_b : word_t; + result : word_t; bd : STD_LOGIC; exc : std_logic; exc_last : std_logic;