diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd
index b75299d..f8ad262 100644
--- a/lib/CPUs/MIPS/src/core/mips_bui.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd
@@ -189,29 +189,21 @@ begin
 
 	MRDY_O			<= '1';
 
-cyc_registered_out:
+read_cyc_register:
 	process(CLK_I)
-	variable cyc	: std_logic;
 	begin
 		if rising_edge(CLK_I) then
 			if RST_I = '1' then
-				cyc		:= '0';
-				CYC_O	<= '0';
+				read_cycle		<= '0';
 			else
-				CYC_O	<= cyc or not bout_fifo_empty;
-				if cyc = '0' then
-					if (bout_fifo_we and bout_rdy) = '1' then
-						cyc		:= '1';
-					end if;
-				elsif SRDY_I = '1' then
-					cyc		:= read_cycle;
-				end if;
+				read_cycle 		<= (dmem_mem_rd_gnt and CYC_O_dmem_rd) 
+								or (dcache_mem_gnt and CYC_O_dcache) 
+								or (icache_mem_gnt and CYC_O_icache);
 			end if;
 		end if;
 	end process;	
-
-	read_cycle 		<= (dmem_mem_rd_gnt and CYC_O_dmem_rd) or (dcache_mem_gnt and CYC_O_dcache) or (icache_mem_gnt and CYC_O_icache);
-	
+					
+	CYC_O			<= not bout_fifo_empty or read_cycle;
 	STB_O			<= not bout_fifo_empty;
 	ADDR_O			<= bout_fifo_addr_out;
 	DAT_O			<= bout_fifo_data_out;
@@ -300,9 +292,14 @@ inst_bout_fifo: entity work.fifo_sync_dist
 		data_r		=>  bout_fifo_dout
 	);
 	bout_rdy			<= not bout_fifo_full;
-	bout_fifo_re		<= SRDY_I;
+	bout_fifo_re		<= not bout_fifo_empty and SRDY_I;
 	
 	bout_fifo_we		<= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
+-- 	bout_fifo_we		<= STB_O_dmem_wr when dmem_mem_wr_gnt = '1' else
+-- 						   STB_O_dmem_rd when dmem_mem_rd_gnt = '1' else
+-- 						   STB_O_dcache when dcache_mem_gnt = '1' else
+-- 						   STB_O_icache when icache_mem_gnt = '1' else '0';
+						   
 
 	bout_fifo_data_in	<= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');