diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys.prj b/projects/mips_sys/ise92/mips_sys/mips_sys.prj
index 0399c87..0f38437 100644
--- a/projects/mips_sys/ise92/mips_sys/mips_sys.prj
+++ b/projects/mips_sys/ise92/mips_sys/mips_sys.prj
@@ -31,10 +31,9 @@ vhdl work "../../../../lib/VGA_ctrl/src/linefifo.vhd"
 vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
 vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
-vhdl work "../../src/rom_wb.vhd"
-vhdl work "../../src/ram_wb.vhd"
-vhdl work "../../src/gpio_wb.vhd"
 vhdl work "../../../../lib/uart/uart_wb.vhd"
+vhdl work "../../../../lib/misc/rom_wb.vhd"
+vhdl work "../../../../lib/misc/ram_wb.vhd"
 vhdl work "../../../../lib/misc/lcd_port.vhd"
 vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
 vhdl work "../../../../lib/misc/async_port_wb.vhd"
diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
index 9eeca44..c5a55bd 100644
--- a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
+++ b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
@@ -31,10 +31,9 @@ vhdl work "W:\vhdl\lib\VGA_ctrl\src\linefifo.vhd"
 vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\rom_wb.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\ram_wb.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\gpio_wb.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
+vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
 vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
 vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
 vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
diff --git a/projects/mips_sys/sim/tb_mips_sys.wdo b/projects/mips_sys/sim/tb_mips_sys.wdo
index 0d3990c..dbea432 100644
--- a/projects/mips_sys/sim/tb_mips_sys.wdo
+++ b/projects/mips_sys/sim/tb_mips_sys.wdo
@@ -151,18 +151,16 @@ add wave -noupdate -divider Flash
 add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
 add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
-add wave -noupdate -format Logic /tb_mips_sys/sys_flash_wrn
-add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rdn
 add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rstn
 add wave -noupdate -divider {Sync SRAM}
 add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_clk
 add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_cke_n
 add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_ce_n
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_we_n
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_oe_n
 add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_dp
 add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_adv
 add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_bw_n
@@ -170,6 +168,8 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_mode
 add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_zz
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
+add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
 add wave -noupdate -divider {MIPS TOP}
 add wave -noupdate -format Logic /tb_mips_sys/uut/clk
 add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
@@ -315,7 +315,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_re
 add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_we
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {115147600 ps} 0}
+WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {973266423 ps} 0}
 configure wave -namecolwidth 218
 configure wave -valuecolwidth 130
 configure wave -justifyvalue left
@@ -329,4 +329,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {2390724794 ps} {3001528274 ps}
+WaveRestoreZoom {973174006 ps} {973377973 ps}