From fda12e53c3c7e8173dc57210516e7f8d7f0d0336 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 14 Oct 2008 17:09:30 +0000 Subject: [PATCH] - Uses now full capacity of SDRAM (64-Bit interface on ML-402) - Removed read data mask git-svn-id: http://moon:8086/svn/vhdl/trunk@57 cc03376c-175c-47c8-b038-4cd826a8556b --- .../src/sdram_ctrl_frontend_wb.vhd | 42 ++++++++----------- 1 file changed, 18 insertions(+), 24 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd index e078ede..3ae2ab3 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd @@ -83,8 +83,6 @@ architecture struct of sdram_ctrl_frontend_wb is signal u_busy : std_logic; signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_dm_rd_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_dm_rd_out : unsigned(SDR_DM_WIDTH-1 downto 0); signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); signal u_data_vld : std_logic; signal u_req_wr : std_logic; @@ -100,8 +98,8 @@ architecture struct of sdram_ctrl_frontend_wb is -- signal cat_fifo_almost_full : std_logic; -- signal cat_fifo_almost_empty : std_logic; - signal write_fifo_din : unsigned(35 downto 0); - signal write_fifo_dout : unsigned(35 downto 0); + signal write_fifo_din : unsigned(36 downto 0); + signal write_fifo_dout : unsigned(36 downto 0); signal write_fifo_re : std_logic; signal write_fifo_we : std_logic; signal write_fifo_full : std_logic; @@ -109,8 +107,8 @@ architecture struct of sdram_ctrl_frontend_wb is -- signal write_fifo_almost_full : std_logic; -- signal write_fifo_almost_empty : std_logic; - signal read_fifo_din : unsigned(35 downto 0); - signal read_fifo_dout : unsigned(35 downto 0); + signal read_fifo_din : unsigned(31 downto 0); + signal read_fifo_dout : unsigned(31 downto 0); signal read_fifo_re : std_logic; signal read_fifo_we : std_logic; signal read_fifo_full : std_logic; @@ -128,14 +126,14 @@ architecture struct of sdram_ctrl_frontend_wb is alias dm_rd_fifo_out is cat_fifo_dout(4-1 downto 0); alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-4); - alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-4-1 downto 0); + alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-4-1 downto 1); + alias write_fifo_a25_in is write_fifo_din(0); alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-4); - alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-4-1 downto 0); + alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-4-1 downto 1); + alias write_fifo_a25_out is write_fifo_dout(0); - alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-4); - alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-4-1 downto 0); - alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-4); - alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-4-1 downto 0); + alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-1 downto 0); + alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-1 downto 0); begin @@ -165,7 +163,7 @@ begin GENERIC MAP ( addr_width => fifo_depth, - data_width => 36 + data_width => write_fifo_din'length ) PORT MAP ( @@ -186,7 +184,7 @@ begin GENERIC MAP ( addr_width => fifo_depth, - data_width => 36 + data_width => read_fifo_din'length ) PORT MAP ( @@ -231,9 +229,7 @@ begin u_cmd_we => u_cmd_we, u_data_wr => u_data_w, u_data_rd => u_data_r, - u_dm_wr_in => u_dm_wr_in, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, + u_dm => u_dm_wr_in, -- SDRAM signals sd_clk_p => sd_clk_p, @@ -259,25 +255,23 @@ begin write_fifo_we <= STB_I and WE_I and rdy; write_fifo_data_in <= DAT_I; write_fifo_dm_in <= not SEL_I; + write_fifo_a25_in <= ADDR_I(25); cat_fifo_we <= STB_I and rdy; cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ; addr_fifo_in <= ADDR_I(24 downto 2) & "0"; - dm_rd_fifo_in <= not SEL_I; - tag_fifo_in <= (others=>'0'); + tag_fifo_in <= "000" & ADDR_I(25); u_cmd_we <= (not cat_fifo_empty) and (not u_busy); u_cmd <= cmd_fifo_out; u_addr <= addr_fifo_out; - u_dm_rd_in <= dm_rd_fifo_out & dm_rd_fifo_out; - u_dm_wr_in <= write_fifo_dm_out & write_fifo_dm_out; + u_dm_wr_in <= ("1111" & write_fifo_dm_out) when write_fifo_a25_out = '0' else (write_fifo_dm_out & "1111"); u_tag_in <= tag_fifo_out; + u_data_w <= write_fifo_data_out & write_fifo_data_out; write_fifo_re <= u_req_wr and (not write_fifo_empty); cat_fifo_re <= u_cmd_we; - u_data_w <= write_fifo_data_out & write_fifo_data_out; read_fifo_re <= (not read_fifo_empty) and MRDY_I; read_fifo_we <= u_data_vld; - read_fifo_data_in <= u_data_r(31 downto 0); - read_fifo_dm_in <= u_dm_rd_out(3 downto 0); + read_fifo_data_in <= u_data_r(31 downto 0) when u_tag_rd(0) = '0' else u_data_r(63 downto 32); end architecture struct;