From fd682df811c5cdbb5f392d348f95fc6467e0753a Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 16 May 2015 17:52:06 +0000 Subject: [PATCH] - added git-svn-id: http://moon:8086/svn/vhdl/trunk@1098 cc03376c-175c-47c8-b038-4cd826a8556b --- .../altera_lnsim/altera_lnsim_components.vhd | 794 ++++++++++++++++++ 1 file changed, 794 insertions(+) create mode 100644 Common/sim/altera/libsrc/altera_lnsim/altera_lnsim_components.vhd diff --git a/Common/sim/altera/libsrc/altera_lnsim/altera_lnsim_components.vhd b/Common/sim/altera/libsrc/altera_lnsim/altera_lnsim_components.vhd new file mode 100644 index 0000000..50b087a --- /dev/null +++ b/Common/sim/altera/libsrc/altera_lnsim/altera_lnsim_components.vhd @@ -0,0 +1,794 @@ +-- Copyright (C) 1991-2010 Altera Corporation +-- This simulation model contains highly confidential and +-- proprietary information of Altera and is being provided +-- in accordance with and subject to the protections of the +-- applicable Altera Program License Subscription Agreement +-- which governs its use and disclosure. Your use of Altera +-- Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, +-- and any output files any of the foregoing (including device +-- programming or simulation files), and any associated +-- documentation or information are expressly subject to the +-- terms and conditions of the Altera Program License Subscription +-- Agreement, Altera MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of simulating designs for +-- use exclusively in logic devices manufactured by Altera and sold +-- by Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. Altera products and +-- services are protected under numerous U.S. and foreign patents, +-- maskwork rights, copyrights and other intellectual property laws. +-- Altera assumes no responsibility or liability arising out of the +-- application or use of this simulation model. + +library ieee; +use ieee.std_logic_1164.all; + +package altera_lnsim_components is + +component altera_mult_add + GENERIC ( + extra_latency : INTEGER := 0; + dedicated_multiplier_circuitry : STRING := "AUTO"; + dsp_block_balancing : STRING := "AUTO"; + selected_device_family : STRING := "Stratix V"; + lpm_type : STRING := "altera_mult_add"; + lpm_hint : STRING := "UNUSED"; + width_a : INTEGER := 1; + input_register_a0 : STRING := "UNREGISTERED"; + input_aclr_a0 : STRING := "NONE"; + input_source_a0 : STRING := "DATAA"; + input_register_a1 : STRING := "UNREGISTERED"; + input_aclr_a1 : STRING := "NONE"; + input_source_a1 : STRING := "DATAA"; + input_register_a2 : STRING := "UNREGISTERED"; + input_aclr_a2 : STRING := "NONE"; + input_source_a2 : STRING := "DATAA"; + input_register_a3 : STRING := "UNREGISTERED"; + input_aclr_a3 : STRING := "NONE"; + input_source_a3 : STRING := "DATAA"; + width_b : INTEGER := 1; + input_register_b0 : STRING := "UNREGISTERED"; + input_aclr_b0 : STRING := "NONE"; + input_source_b0 : STRING := "DATAB"; + input_register_b1 : STRING := "UNREGISTERED"; + input_aclr_b1 : STRING := "NONE"; + input_source_b1 : STRING := "DATAB"; + input_register_b2 : STRING := "UNREGISTERED"; + input_aclr_b2 : STRING := "NONE"; + input_source_b2 : STRING := "DATAB"; + input_register_b3 : STRING := "UNREGISTERED"; + input_aclr_b3 : STRING := "NONE"; + input_source_b3 : STRING := "DATAB"; + width_c : INTEGER := 1; + input_register_c0 : STRING := "UNREGISTERED"; + input_aclr_c0 : STRING := "NONE"; + input_register_c1 : STRING := "UNREGISTERED"; + input_aclr_c1 : STRING := "NONE"; + input_register_c2 : STRING := "UNREGISTERED"; + input_aclr_c2 : STRING := "NONE"; + input_register_c3 : STRING := "UNREGISTERED"; + input_aclr_c3 : STRING := "NONE"; + width_result : INTEGER := 34; + output_register : STRING := "UNREGISTERED"; + output_aclr : STRING := "NONE"; + port_signa : STRING := "PORT_UNUSED"; + representation_a : STRING := "UNSIGNED"; + signed_register_a : STRING := "UNREGISTERED"; + signed_aclr_a : STRING := "NONE"; + signed_pipeline_register_a : STRING := "UNREGISTERED"; + signed_pipeline_aclr_a : STRING := "NONE"; + port_signb : STRING := "PORT_UNUSED"; + representation_b : STRING := "UNSIGNED"; + signed_register_b : STRING := "UNREGISTERED"; + signed_aclr_b : STRING := "NONE"; + signed_pipeline_register_b : STRING := "UNREGISTERED"; + signed_pipeline_aclr_b : STRING := "NONE"; + number_of_multipliers : INTEGER := 1; + multiplier1_direction : STRING := "UNUSED"; + multiplier3_direction : STRING := "UNUSED"; + multiplier_register0 : STRING := "UNREGISTERED"; + multiplier_aclr0 : STRING := "NONE"; + multiplier_register1 : STRING := "UNREGISTERED"; + multiplier_aclr1 : STRING := "NONE"; + multiplier_register2 : STRING := "UNREGISTERED"; + multiplier_aclr2 : STRING := "NONE"; + multiplier_register3 : STRING := "UNREGISTERED"; + multiplier_aclr3 : STRING := "NONE"; + port_addnsub1 : STRING := "PORT_UNUSED"; + addnsub_multiplier_register1 : STRING := "UNREGISTERED"; + addnsub_multiplier_aclr1 : STRING := "NONE"; + addnsub_multiplier_pipeline_register1 : STRING := "UNREGISTERED"; + addnsub_multiplier_pipeline_aclr1 : STRING := "NONE"; + port_addnsub3 : STRING := "PORT_UNUSED"; + use_subnadd : STRING := "NO"; + addnsub_multiplier_register3 : STRING := "UNREGISTERED"; + addnsub_multiplier_aclr3 : STRING := "NONE"; + addnsub_multiplier_pipeline_register3 : STRING := "UNREGISTERED"; + addnsub_multiplier_pipeline_aclr3 : STRING := "NONE"; + adder1_rounding : STRING := "NO"; + addnsub1_round_register : STRING := "UNREGISTERED"; + addnsub1_round_aclr : STRING := "NONE"; + addnsub1_round_pipeline_register : STRING := "UNREGISTERED"; + addnsub1_round_pipeline_aclr : STRING := "NONE"; + adder3_rounding : STRING := "NO"; + addnsub3_round_register : STRING := "UNREGISTERED"; + addnsub3_round_aclr : STRING := "NONE"; + addnsub3_round_pipeline_register : STRING := "UNREGISTERED"; + addnsub3_round_pipeline_aclr : STRING := "NONE"; + multiplier01_rounding : STRING := "NO"; + mult01_round_register : STRING := "UNREGISTERED"; + mult01_round_aclr : STRING := "NONE"; + multiplier23_rounding : STRING := "NO"; + mult23_round_register : STRING := "UNREGISTERED"; + mult23_round_aclr : STRING := "NONE"; + width_msb : INTEGER := 17; + output_rounding : STRING := "NO"; + output_round_type : STRING := "NEAREST_INTEGER"; + output_round_register : STRING := "UNREGISTERED"; + output_round_aclr : STRING := "NONE"; + output_round_pipeline_register : STRING := "UNREGISTERED"; + output_round_pipeline_aclr : STRING := "NONE"; + chainout_rounding : STRING := "NO"; + chainout_round_register : STRING := "UNREGISTERED"; + chainout_round_aclr : STRING := "NONE"; + chainout_round_pipeline_register : STRING := "UNREGISTERED"; + chainout_round_pipeline_aclr : STRING := "NONE"; + chainout_round_output_register : STRING := "UNREGISTERED"; + chainout_round_output_aclr : STRING := "NONE"; + multiplier01_saturation : STRING := "NO"; + mult01_saturation_register : STRING := "UNREGISTERED"; + mult01_saturation_aclr : STRING := "NONE"; + multiplier23_saturation : STRING := "NO"; + mult23_saturation_register : STRING := "UNREGISTERED"; + mult23_saturation_aclr : STRING := "NONE"; + port_mult0_is_saturated : STRING := "UNUSED"; + port_mult1_is_saturated : STRING := "UNUSED"; + port_mult2_is_saturated : STRING := "UNUSED"; + port_mult3_is_saturated : STRING := "UNUSED"; + width_saturate_sign : INTEGER := 1; + output_saturation : STRING := "NO"; + port_output_is_overflow : STRING := "PORT_UNUSED"; + output_saturate_type : STRING := "ASYMMETRIC"; + output_saturate_register : STRING := "UNREGISTERED"; + output_saturate_aclr : STRING := "NONE"; + output_saturate_pipeline_register : STRING := "UNREGISTERED"; + output_saturate_pipeline_aclr : STRING := "NONE"; + chainout_saturation : STRING := "NO"; + port_chainout_sat_is_overflow : STRING := "PORT_UNUSED"; + chainout_saturate_register : STRING := "UNREGISTERED"; + chainout_saturate_aclr : STRING := "NONE"; + chainout_saturate_pipeline_register : STRING := "UNREGISTERED"; + chainout_saturate_pipeline_aclr : STRING := "NONE"; + chainout_saturate_output_register : STRING := "UNREGISTERED"; + chainout_saturate_output_aclr : STRING := "NONE"; + scanouta_register : STRING := "UNREGISTERED"; + scanouta_aclr : STRING := "NONE"; + width_chainin : INTEGER := 1; + chainout_adder : STRING := "NO"; + chainout_adder_direction : STRING := "ADD"; + chainout_register : STRING := "UNREGISTERED"; + chainout_aclr : STRING := "NONE"; + port_negate : STRING := "PORT_UNUSED"; + negate_register : STRING := "UNREGISTERED"; + negate_aclr : STRING := "NONE"; + negate_latency_clock : STRING := "UNREGISTERED"; + negate_latency_aclr : STRING := "NONE"; + zero_chainout_output_register : STRING := "UNREGISTERED"; + zero_chainout_output_aclr : STRING := "NONE"; + shift_mode : STRING := "NO"; + rotate_register : STRING := "UNREGISTERED"; + rotate_aclr : STRING := "NONE"; + rotate_pipeline_register : STRING := "UNREGISTERED"; + rotate_pipeline_aclr : STRING := "NONE"; + rotate_output_register : STRING := "UNREGISTERED"; + rotate_output_aclr : STRING := "NONE"; + shift_right_register : STRING := "UNREGISTERED"; + shift_right_aclr : STRING := "NONE"; + shift_right_pipeline_register : STRING := "UNREGISTERED"; + shift_right_pipeline_aclr : STRING := "NONE"; + shift_right_output_register : STRING := "UNREGISTERED"; + shift_right_output_aclr : STRING := "NONE"; + zero_loopback_register : STRING := "UNREGISTERED"; + zero_loopback_aclr : STRING := "NONE"; + zero_loopback_pipeline_register : STRING := "UNREGISTERED"; + zero_loopback_pipeline_aclr : STRING := "NONE"; + zero_loopback_output_register : STRING := "UNREGISTERED"; + zero_loopback_output_aclr : STRING := "NONE"; + accumulator : STRING := "NO"; + accum_direction : STRING := "ADD"; + double_accum : STRING := "NO"; + loadconst_value : INTEGER := 0; + use_sload_accum_port : STRING := "NO"; + accum_sload_register : STRING := "UNREGISTERED"; + accum_sload_aclr : STRING := "NONE"; + accum_sload_pipeline_register : STRING := "UNREGISTERED"; + accum_sload_pipeline_aclr : STRING := "NONE"; + loadconst_control_register : STRING := "UNREGISTERED"; + loadconst_control_aclr : STRING := "NONE"; + systolic_delay1 : STRING := "UNREGISTERED"; + systolic_delay3 : STRING := "UNREGISTERED"; + systolic_aclr1 : STRING := "NONE"; + systolic_aclr3 : STRING := "NONE"; + preadder_mode : STRING := "SIMPLE"; + preadder_direction_0 : STRING := "ADD"; + preadder_direction_1 : STRING := "ADD"; + preadder_direction_2 : STRING := "ADD"; + preadder_direction_3 : STRING := "ADD"; + width_coef : INTEGER := 1; + coefsel0_register : STRING := "UNREGISTERED"; + coefsel0_aclr : STRING := "NONE"; + coefsel1_register : STRING := "UNREGISTERED"; + coefsel1_aclr : STRING := "NONE"; + coefsel2_register : STRING := "UNREGISTERED"; + coefsel2_aclr : STRING := "NONE"; + coefsel3_register : STRING := "UNREGISTERED"; + coefsel3_aclr : STRING := "NONE"; + coef0_0 : INTEGER := 0; + coef0_1 : INTEGER := 0; + coef0_2 : INTEGER := 0; + coef0_3 : INTEGER := 0; + coef0_4 : INTEGER := 0; + coef0_5 : INTEGER := 0; + coef0_6 : INTEGER := 0; + coef0_7 : INTEGER := 0; + coef1_0 : INTEGER := 0; + coef1_1 : INTEGER := 0; + coef1_2 : INTEGER := 0; + coef1_3 : INTEGER := 0; + coef1_4 : INTEGER := 0; + coef1_5 : INTEGER := 0; + coef1_6 : INTEGER := 0; + coef1_7 : INTEGER := 0; + coef2_0 : INTEGER := 0; + coef2_1 : INTEGER := 0; + coef2_2 : INTEGER := 0; + coef2_3 : INTEGER := 0; + coef2_4 : INTEGER := 0; + coef2_5 : INTEGER := 0; + coef2_6 : INTEGER := 0; + coef2_7 : INTEGER := 0; + coef3_0 : INTEGER := 0; + coef3_1 : INTEGER := 0; + coef3_2 : INTEGER := 0; + coef3_3 : INTEGER := 0; + coef3_4 : INTEGER := 0; + coef3_5 : INTEGER := 0; + coef3_6 : INTEGER := 0; + coef3_7 : INTEGER := 0; + latency : INTEGER := 0; + input_a0_latency_clock : STRING := "UNREGISTERED"; + input_a0_latency_aclr : STRING := "NONE"; + input_a1_latency_clock : STRING := "UNREGISTERED"; + input_a1_latency_aclr : STRING := "NONE"; + input_a2_latency_clock : STRING := "UNREGISTERED"; + input_a2_latency_aclr : STRING := "NONE"; + input_a3_latency_clock : STRING := "UNREGISTERED"; + input_a3_latency_aclr : STRING := "NONE"; + input_b0_latency_clock : STRING := "UNREGISTERED"; + input_b0_latency_aclr : STRING := "NONE"; + input_b1_latency_clock : STRING := "UNREGISTERED"; + input_b1_latency_aclr : STRING := "NONE"; + input_b2_latency_clock : STRING := "UNREGISTERED"; + input_b2_latency_aclr : STRING := "NONE"; + input_b3_latency_clock : STRING := "UNREGISTERED"; + input_b3_latency_aclr : STRING := "NONE"; + input_c0_latency_clock : STRING := "UNREGISTERED"; + input_c0_latency_aclr : STRING := "NONE"; + input_c1_latency_clock : STRING := "UNREGISTERED"; + input_c1_latency_aclr : STRING := "NONE"; + input_c2_latency_clock : STRING := "UNREGISTERED"; + input_c2_latency_aclr : STRING := "NONE"; + input_c3_latency_clock : STRING := "UNREGISTERED"; + input_c3_latency_aclr : STRING := "NONE"; + coefsel0_latency_clock : STRING := "UNREGISTERED"; + coefsel0_latency_aclr : STRING := "NONE"; + coefsel1_latency_clock : STRING := "UNREGISTERED"; + coefsel1_latency_aclr : STRING := "NONE"; + coefsel2_latency_clock : STRING := "UNREGISTERED"; + coefsel2_latency_aclr : STRING := "NONE"; + coefsel3_latency_clock : STRING := "UNREGISTERED"; + coefsel3_latency_aclr : STRING := "NONE"; + signed_latency_clock_a : STRING := "UNREGISTERED"; + signed_latency_aclr_a : STRING := "NONE"; + signed_latency_clock_b : STRING := "UNREGISTERED"; + signed_latency_aclr_b : STRING := "NONE"; + addnsub_multiplier_latency_clock1 : STRING := "UNREGISTERED"; + addnsub_multiplier_latency_aclr1 : STRING := "NONE"; + addnsub_multiplier_latency_clock3 : STRING := "UNREGISTERED"; + addnsub_multiplier_latency_aclr3 : STRING := "NONE"; + accum_sload_latency_clock : STRING := "UNREGISTERED"; + accum_sload_latency_aclr : STRING := "NONE" + ); + PORT ( + dataa : IN STD_LOGIC_VECTOR(width_a * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + datab : IN STD_LOGIC_VECTOR(width_b * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + datac : IN STD_LOGIC_VECTOR(width_c * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + scanina : IN STD_LOGIC_VECTOR(width_a - 1 downto 0) := (OTHERS => '0'); + scaninb : IN STD_LOGIC_VECTOR(width_b - 1 downto 0) := (OTHERS => '0'); + sourcea : IN STD_LOGIC_VECTOR(number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + sourceb : IN STD_LOGIC_VECTOR(number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + clock3 : IN STD_LOGIC := '0'; + clock2 : IN STD_LOGIC := '0'; + clock1 : IN STD_LOGIC := '0'; + clock0 : IN STD_LOGIC := '0'; + aclr3 : IN STD_LOGIC := '0'; + aclr2 : IN STD_LOGIC := '0'; + aclr1 : IN STD_LOGIC := '0'; + aclr0 : IN STD_LOGIC := '0'; + ena3 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena0 : IN STD_LOGIC := '1'; + signa : IN STD_LOGIC := '0'; + signb : IN STD_LOGIC := '0'; + addnsub1 : IN STD_LOGIC := '0'; + addnsub3 : IN STD_LOGIC := '0'; + result : OUT STD_LOGIC_VECTOR(width_result - 1 downto 0); + scanouta : OUT STD_LOGIC_VECTOR(width_a - 1 downto 0); + scanoutb : OUT STD_LOGIC_VECTOR(width_b - 1 downto 0); + mult01_round : IN STD_LOGIC := '0'; + mult23_round : IN STD_LOGIC := '0'; + mult01_saturation : IN STD_LOGIC := '0'; + mult23_saturation : IN STD_LOGIC := '0'; + addnsub1_round : IN STD_LOGIC := '0'; + addnsub3_round : IN STD_LOGIC := '0'; + mult0_is_saturated : OUT STD_LOGIC; + mult1_is_saturated : OUT STD_LOGIC; + mult2_is_saturated : OUT STD_LOGIC; + mult3_is_saturated : OUT STD_LOGIC; + output_round : IN STD_LOGIC := '0'; + chainout_round : IN STD_LOGIC := '0'; + output_saturate : IN STD_LOGIC := '0'; + chainout_saturate : IN STD_LOGIC := '0'; + overflow : OUT STD_LOGIC; + chainout_sat_overflow : OUT STD_LOGIC; + chainin : IN STD_LOGIC_VECTOR(width_chainin - 1 downto 0) := (OTHERS => '0'); + zero_chainout : IN STD_LOGIC := '0'; + rotate : IN STD_LOGIC := '0'; + shift_right : IN STD_LOGIC := '0'; + zero_loopback : IN STD_LOGIC := '0'; + accum_sload : IN STD_LOGIC := '0'; + sload_accum : IN STD_LOGIC := '0'; + negate : IN STD_LOGIC := '0'; + coefsel0 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel1 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel2 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel3 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0') + ); +end component; + +component altera_mult_add_rtl + GENERIC ( + extra_latency : INTEGER := 0; + dedicated_multiplier_circuitry : STRING := "AUTO"; + dsp_block_balancing : STRING := "AUTO"; + selected_device_family : STRING := "Stratix V"; + lpm_type : STRING := "altera_mult_add"; + lpm_hint : STRING := "UNUSED"; + width_a : INTEGER := 1; + input_register_a0 : STRING := "UNREGISTERED"; + input_aclr_a0 : STRING := "NONE"; + input_source_a0 : STRING := "DATAA"; + input_register_a1 : STRING := "UNREGISTERED"; + input_aclr_a1 : STRING := "NONE"; + input_source_a1 : STRING := "DATAA"; + input_register_a2 : STRING := "UNREGISTERED"; + input_aclr_a2 : STRING := "NONE"; + input_source_a2 : STRING := "DATAA"; + input_register_a3 : STRING := "UNREGISTERED"; + input_aclr_a3 : STRING := "NONE"; + input_source_a3 : STRING := "DATAA"; + width_b : INTEGER := 1; + input_register_b0 : STRING := "UNREGISTERED"; + input_aclr_b0 : STRING := "NONE"; + input_source_b0 : STRING := "DATAB"; + input_register_b1 : STRING := "UNREGISTERED"; + input_aclr_b1 : STRING := "NONE"; + input_source_b1 : STRING := "DATAB"; + input_register_b2 : STRING := "UNREGISTERED"; + input_aclr_b2 : STRING := "NONE"; + input_source_b2 : STRING := "DATAB"; + input_register_b3 : STRING := "UNREGISTERED"; + input_aclr_b3 : STRING := "NONE"; + input_source_b3 : STRING := "DATAB"; + width_c : INTEGER := 1; + input_register_c0 : STRING := "UNREGISTERED"; + input_aclr_c0 : STRING := "NONE"; + input_register_c1 : STRING := "UNREGISTERED"; + input_aclr_c1 : STRING := "NONE"; + input_register_c2 : STRING := "UNREGISTERED"; + input_aclr_c2 : STRING := "NONE"; + input_register_c3 : STRING := "UNREGISTERED"; + input_aclr_c3 : STRING := "NONE"; + width_result : INTEGER := 34; + output_register : STRING := "UNREGISTERED"; + output_aclr : STRING := "NONE"; + port_signa : STRING := "PORT_UNUSED"; + representation_a : STRING := "UNSIGNED"; + signed_register_a : STRING := "UNREGISTERED"; + signed_aclr_a : STRING := "NONE"; + signed_pipeline_register_a : STRING := "UNREGISTERED"; + signed_pipeline_aclr_a : STRING := "NONE"; + port_signb : STRING := "PORT_UNUSED"; + representation_b : STRING := "UNSIGNED"; + signed_register_b : STRING := "UNREGISTERED"; + signed_aclr_b : STRING := "NONE"; + signed_pipeline_register_b : STRING := "UNREGISTERED"; + signed_pipeline_aclr_b : STRING := "NONE"; + number_of_multipliers : INTEGER := 1; + multiplier1_direction : STRING := "UNUSED"; + multiplier3_direction : STRING := "UNUSED"; + multiplier_register0 : STRING := "UNREGISTERED"; + multiplier_aclr0 : STRING := "NONE"; + multiplier_register1 : STRING := "UNREGISTERED"; + multiplier_aclr1 : STRING := "NONE"; + multiplier_register2 : STRING := "UNREGISTERED"; + multiplier_aclr2 : STRING := "NONE"; + multiplier_register3 : STRING := "UNREGISTERED"; + multiplier_aclr3 : STRING := "NONE"; + port_addnsub1 : STRING := "PORT_UNUSED"; + addnsub_multiplier_register1 : STRING := "UNREGISTERED"; + addnsub_multiplier_aclr1 : STRING := "NONE"; + addnsub_multiplier_pipeline_register1 : STRING := "UNREGISTERED"; + addnsub_multiplier_pipeline_aclr1 : STRING := "NONE"; + port_addnsub3 : STRING := "PORT_UNUSED"; + use_subnadd : STRING := "NO"; + addnsub_multiplier_register3 : STRING := "UNREGISTERED"; + addnsub_multiplier_aclr3 : STRING := "NONE"; + addnsub_multiplier_pipeline_register3 : STRING := "UNREGISTERED"; + addnsub_multiplier_pipeline_aclr3 : STRING := "NONE"; + adder1_rounding : STRING := "NO"; + addnsub1_round_register : STRING := "UNREGISTERED"; + addnsub1_round_aclr : STRING := "NONE"; + addnsub1_round_pipeline_register : STRING := "UNREGISTERED"; + addnsub1_round_pipeline_aclr : STRING := "NONE"; + adder3_rounding : STRING := "NO"; + addnsub3_round_register : STRING := "UNREGISTERED"; + addnsub3_round_aclr : STRING := "NONE"; + addnsub3_round_pipeline_register : STRING := "UNREGISTERED"; + addnsub3_round_pipeline_aclr : STRING := "NONE"; + multiplier01_rounding : STRING := "NO"; + mult01_round_register : STRING := "UNREGISTERED"; + mult01_round_aclr : STRING := "NONE"; + multiplier23_rounding : STRING := "NO"; + mult23_round_register : STRING := "UNREGISTERED"; + mult23_round_aclr : STRING := "NONE"; + width_msb : INTEGER := 17; + output_rounding : STRING := "NO"; + output_round_type : STRING := "NEAREST_INTEGER"; + output_round_register : STRING := "UNREGISTERED"; + output_round_aclr : STRING := "NONE"; + output_round_pipeline_register : STRING := "UNREGISTERED"; + output_round_pipeline_aclr : STRING := "NONE"; + chainout_rounding : STRING := "NO"; + chainout_round_register : STRING := "UNREGISTERED"; + chainout_round_aclr : STRING := "NONE"; + chainout_round_pipeline_register : STRING := "UNREGISTERED"; + chainout_round_pipeline_aclr : STRING := "NONE"; + chainout_round_output_register : STRING := "UNREGISTERED"; + chainout_round_output_aclr : STRING := "NONE"; + multiplier01_saturation : STRING := "NO"; + mult01_saturation_register : STRING := "UNREGISTERED"; + mult01_saturation_aclr : STRING := "NONE"; + multiplier23_saturation : STRING := "NO"; + mult23_saturation_register : STRING := "UNREGISTERED"; + mult23_saturation_aclr : STRING := "NONE"; + port_mult0_is_saturated : STRING := "UNUSED"; + port_mult1_is_saturated : STRING := "UNUSED"; + port_mult2_is_saturated : STRING := "UNUSED"; + port_mult3_is_saturated : STRING := "UNUSED"; + width_saturate_sign : INTEGER := 1; + output_saturation : STRING := "NO"; + port_output_is_overflow : STRING := "PORT_UNUSED"; + output_saturate_type : STRING := "ASYMMETRIC"; + output_saturate_register : STRING := "UNREGISTERED"; + output_saturate_aclr : STRING := "NONE"; + output_saturate_pipeline_register : STRING := "UNREGISTERED"; + output_saturate_pipeline_aclr : STRING := "NONE"; + chainout_saturation : STRING := "NO"; + port_chainout_sat_is_overflow : STRING := "PORT_UNUSED"; + chainout_saturate_register : STRING := "UNREGISTERED"; + chainout_saturate_aclr : STRING := "NONE"; + chainout_saturate_pipeline_register : STRING := "UNREGISTERED"; + chainout_saturate_pipeline_aclr : STRING := "NONE"; + chainout_saturate_output_register : STRING := "UNREGISTERED"; + chainout_saturate_output_aclr : STRING := "NONE"; + scanouta_register : STRING := "UNREGISTERED"; + scanouta_aclr : STRING := "NONE"; + width_chainin : INTEGER := 1; + chainout_adder : STRING := "NO"; + chainout_adder_direction : STRING := "ADD"; + chainout_register : STRING := "UNREGISTERED"; + chainout_aclr : STRING := "NONE"; + port_negate : STRING := "PORT_UNUSED"; + negate_register : STRING := "UNREGISTERED"; + negate_aclr : STRING := "NONE"; + negate_latency_clock : STRING := "UNREGISTERED"; + negate_latency_aclr : STRING := "NONE"; + zero_chainout_output_register : STRING := "UNREGISTERED"; + zero_chainout_output_aclr : STRING := "NONE"; + shift_mode : STRING := "NO"; + rotate_register : STRING := "UNREGISTERED"; + rotate_aclr : STRING := "NONE"; + rotate_pipeline_register : STRING := "UNREGISTERED"; + rotate_pipeline_aclr : STRING := "NONE"; + rotate_output_register : STRING := "UNREGISTERED"; + rotate_output_aclr : STRING := "NONE"; + shift_right_register : STRING := "UNREGISTERED"; + shift_right_aclr : STRING := "NONE"; + shift_right_pipeline_register : STRING := "UNREGISTERED"; + shift_right_pipeline_aclr : STRING := "NONE"; + shift_right_output_register : STRING := "UNREGISTERED"; + shift_right_output_aclr : STRING := "NONE"; + zero_loopback_register : STRING := "UNREGISTERED"; + zero_loopback_aclr : STRING := "NONE"; + zero_loopback_pipeline_register : STRING := "UNREGISTERED"; + zero_loopback_pipeline_aclr : STRING := "NONE"; + zero_loopback_output_register : STRING := "UNREGISTERED"; + zero_loopback_output_aclr : STRING := "NONE"; + accumulator : STRING := "NO"; + accum_direction : STRING := "ADD"; + double_accum : STRING := "NO"; + loadconst_value : INTEGER := 0; + use_sload_accum_port : STRING := "NO"; + accum_sload_register : STRING := "UNREGISTERED"; + accum_sload_aclr : STRING := "NONE"; + accum_sload_pipeline_register : STRING := "UNREGISTERED"; + accum_sload_pipeline_aclr : STRING := "NONE"; + loadconst_control_register : STRING := "UNREGISTERED"; + loadconst_control_aclr : STRING := "NONE"; + systolic_delay1 : STRING := "UNREGISTERED"; + systolic_delay3 : STRING := "UNREGISTERED"; + systolic_aclr1 : STRING := "NONE"; + systolic_aclr3 : STRING := "NONE"; + preadder_mode : STRING := "SIMPLE"; + preadder_direction_0 : STRING := "ADD"; + preadder_direction_1 : STRING := "ADD"; + preadder_direction_2 : STRING := "ADD"; + preadder_direction_3 : STRING := "ADD"; + width_coef : INTEGER := 1; + coefsel0_register : STRING := "UNREGISTERED"; + coefsel0_aclr : STRING := "NONE"; + coefsel1_register : STRING := "UNREGISTERED"; + coefsel1_aclr : STRING := "NONE"; + coefsel2_register : STRING := "UNREGISTERED"; + coefsel2_aclr : STRING := "NONE"; + coefsel3_register : STRING := "UNREGISTERED"; + coefsel3_aclr : STRING := "NONE"; + coef0_0 : INTEGER := 0; + coef0_1 : INTEGER := 0; + coef0_2 : INTEGER := 0; + coef0_3 : INTEGER := 0; + coef0_4 : INTEGER := 0; + coef0_5 : INTEGER := 0; + coef0_6 : INTEGER := 0; + coef0_7 : INTEGER := 0; + coef1_0 : INTEGER := 0; + coef1_1 : INTEGER := 0; + coef1_2 : INTEGER := 0; + coef1_3 : INTEGER := 0; + coef1_4 : INTEGER := 0; + coef1_5 : INTEGER := 0; + coef1_6 : INTEGER := 0; + coef1_7 : INTEGER := 0; + coef2_0 : INTEGER := 0; + coef2_1 : INTEGER := 0; + coef2_2 : INTEGER := 0; + coef2_3 : INTEGER := 0; + coef2_4 : INTEGER := 0; + coef2_5 : INTEGER := 0; + coef2_6 : INTEGER := 0; + coef2_7 : INTEGER := 0; + coef3_0 : INTEGER := 0; + coef3_1 : INTEGER := 0; + coef3_2 : INTEGER := 0; + coef3_3 : INTEGER := 0; + coef3_4 : INTEGER := 0; + coef3_5 : INTEGER := 0; + coef3_6 : INTEGER := 0; + coef3_7 : INTEGER := 0; + latency : INTEGER := 0; + input_a0_latency_clock : STRING := "UNREGISTERED"; + input_a0_latency_aclr : STRING := "NONE"; + input_a1_latency_clock : STRING := "UNREGISTERED"; + input_a1_latency_aclr : STRING := "NONE"; + input_a2_latency_clock : STRING := "UNREGISTERED"; + input_a2_latency_aclr : STRING := "NONE"; + input_a3_latency_clock : STRING := "UNREGISTERED"; + input_a3_latency_aclr : STRING := "NONE"; + input_b0_latency_clock : STRING := "UNREGISTERED"; + input_b0_latency_aclr : STRING := "NONE"; + input_b1_latency_clock : STRING := "UNREGISTERED"; + input_b1_latency_aclr : STRING := "NONE"; + input_b2_latency_clock : STRING := "UNREGISTERED"; + input_b2_latency_aclr : STRING := "NONE"; + input_b3_latency_clock : STRING := "UNREGISTERED"; + input_b3_latency_aclr : STRING := "NONE"; + input_c0_latency_clock : STRING := "UNREGISTERED"; + input_c0_latency_aclr : STRING := "NONE"; + input_c1_latency_clock : STRING := "UNREGISTERED"; + input_c1_latency_aclr : STRING := "NONE"; + input_c2_latency_clock : STRING := "UNREGISTERED"; + input_c2_latency_aclr : STRING := "NONE"; + input_c3_latency_clock : STRING := "UNREGISTERED"; + input_c3_latency_aclr : STRING := "NONE"; + coefsel0_latency_clock : STRING := "UNREGISTERED"; + coefsel0_latency_aclr : STRING := "NONE"; + coefsel1_latency_clock : STRING := "UNREGISTERED"; + coefsel1_latency_aclr : STRING := "NONE"; + coefsel2_latency_clock : STRING := "UNREGISTERED"; + coefsel2_latency_aclr : STRING := "NONE"; + coefsel3_latency_clock : STRING := "UNREGISTERED"; + coefsel3_latency_aclr : STRING := "NONE"; + signed_latency_clock_a : STRING := "UNREGISTERED"; + signed_latency_aclr_a : STRING := "NONE"; + signed_latency_clock_b : STRING := "UNREGISTERED"; + signed_latency_aclr_b : STRING := "NONE"; + addnsub_multiplier_latency_clock1 : STRING := "UNREGISTERED"; + addnsub_multiplier_latency_aclr1 : STRING := "NONE"; + addnsub_multiplier_latency_clock3 : STRING := "UNREGISTERED"; + addnsub_multiplier_latency_aclr3 : STRING := "NONE"; + accum_sload_latency_clock : STRING := "UNREGISTERED"; + accum_sload_latency_aclr : STRING := "NONE" + ); + PORT ( + dataa : IN STD_LOGIC_VECTOR(width_a * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + datab : IN STD_LOGIC_VECTOR(width_b * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + datac : IN STD_LOGIC_VECTOR(width_c * number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + scanina : IN STD_LOGIC_VECTOR(width_a - 1 downto 0) := (OTHERS => '0'); + scaninb : IN STD_LOGIC_VECTOR(width_b - 1 downto 0) := (OTHERS => '0'); + sourcea : IN STD_LOGIC_VECTOR(number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + sourceb : IN STD_LOGIC_VECTOR(number_of_multipliers - 1 downto 0) := (OTHERS => '0'); + clock3 : IN STD_LOGIC := '0'; + clock2 : IN STD_LOGIC := '0'; + clock1 : IN STD_LOGIC := '0'; + clock0 : IN STD_LOGIC := '0'; + aclr3 : IN STD_LOGIC := '0'; + aclr2 : IN STD_LOGIC := '0'; + aclr1 : IN STD_LOGIC := '0'; + aclr0 : IN STD_LOGIC := '0'; + ena3 : IN STD_LOGIC := '1'; + ena2 : IN STD_LOGIC := '1'; + ena1 : IN STD_LOGIC := '1'; + ena0 : IN STD_LOGIC := '1'; + signa : IN STD_LOGIC := '0'; + signb : IN STD_LOGIC := '0'; + addnsub1 : IN STD_LOGIC := '0'; + addnsub3 : IN STD_LOGIC := '0'; + result : OUT STD_LOGIC_VECTOR(width_result - 1 downto 0); + scanouta : OUT STD_LOGIC_VECTOR(width_a - 1 downto 0); + scanoutb : OUT STD_LOGIC_VECTOR(width_b - 1 downto 0); + mult01_round : IN STD_LOGIC := '0'; + mult23_round : IN STD_LOGIC := '0'; + mult01_saturation : IN STD_LOGIC := '0'; + mult23_saturation : IN STD_LOGIC := '0'; + addnsub1_round : IN STD_LOGIC := '0'; + addnsub3_round : IN STD_LOGIC := '0'; + mult0_is_saturated : OUT STD_LOGIC; + mult1_is_saturated : OUT STD_LOGIC; + mult2_is_saturated : OUT STD_LOGIC; + mult3_is_saturated : OUT STD_LOGIC; + output_round : IN STD_LOGIC := '0'; + chainout_round : IN STD_LOGIC := '0'; + output_saturate : IN STD_LOGIC := '0'; + chainout_saturate : IN STD_LOGIC := '0'; + overflow : OUT STD_LOGIC; + chainout_sat_overflow : OUT STD_LOGIC; + chainin : IN STD_LOGIC_VECTOR(width_chainin - 1 downto 0) := (OTHERS => '0'); + zero_chainout : IN STD_LOGIC := '0'; + rotate : IN STD_LOGIC := '0'; + shift_right : IN STD_LOGIC := '0'; + zero_loopback : IN STD_LOGIC := '0'; + accum_sload : IN STD_LOGIC := '0'; + sload_accum : IN STD_LOGIC := '0'; + negate : IN STD_LOGIC := '0'; + coefsel0 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel1 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel2 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0'); + coefsel3 : IN STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0') + ); +end component; + +component altera_syncram + generic ( + operation_mode : string := "BIDIR_DUAL_PORT"; + -- port a parameters + width_a : integer := 1; + widthad_a : integer := 1; + numwords_a : integer := 0; + -- registering parameters + -- port a read parameters + outdata_reg_a : string := "UNREGISTERED"; + -- clearing parameters + address_aclr_a : string := "NONE"; + outdata_aclr_a : string := "NONE"; + -- clear for the byte enable port reigsters which are clocked by clk0 + -- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9 + width_byteena_a : integer := 1; + -- port b parameters + width_b : integer := 1; + widthad_b : integer := 1; + numwords_b : integer := 0; + -- registering parameters + -- port b read parameters + rdcontrol_reg_b : string := "CLOCK1"; + address_reg_b : string := "CLOCK1"; + outdata_reg_b : string := "UNREGISTERED"; + -- clearing parameters + outdata_aclr_b : string := "NONE"; + -- registering parameters + -- port b write parameters + indata_reg_b : string := "CLOCK1"; + -- registering parameter for the byte enable reister for port b + byteena_reg_b : string := "CLOCK1"; + address_aclr_b : string := "NONE"; + -- StratixII only : to bypass clock enable or using clock enable + clock_enable_input_a : string := "NORMAL"; + clock_enable_output_a : string := "NORMAL"; + clock_enable_input_b : string := "NORMAL"; + clock_enable_output_b : string := "NORMAL"; + -- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9 + width_byteena_b : integer := 1; + -- clock enable setting for the core + clock_enable_core_a : string := "USE_INPUT_CLKEN"; + clock_enable_core_b : string := "USE_INPUT_CLKEN"; + -- read-during-write-same-port setting + read_during_write_mode_port_a : string := "NEW_DATA_NO_NBE_READ"; + read_during_write_mode_port_b : string := "NEW_DATA_NO_NBE_READ"; + -- ECC status ports setting + enable_ecc : string := "FALSE"; + ecc_pipeline_stage_enabled : string := "FALSE"; + + width_eccstatus : integer := 3; + -- global parameters + -- width of a byte for byte enables + byte_size : integer := 0; + read_during_write_mode_mixed_ports: string := "DONT_CARE"; + -- ram block type choices are "AUTO", "M512", "M4K" and "MEGARAM" + ram_block_type : string := "AUTO"; + -- determine whether LE support is turned on or off for altsyncram + implement_in_les : string := "OFF"; + -- determine whether RAM would be power up to uninitialized or not + power_up_uninitialized : string := "FALSE"; + + sim_show_memory_data_in_port_b_layout : string := "OFF"; + + -- general operation parameters + init_file : string := "UNUSED"; + init_file_layout : string := "UNUSED"; + maximum_depth : integer := 0; + intended_device_family : string := "Stratix"; + lpm_hint : string := "UNUSED"; + lpm_type : string := "altera_syncram" ); + port ( + wren_a : in std_logic := '0'; + wren_b : in std_logic := '0'; + rden_a : in std_logic := '1'; + rden_b : in std_logic := '1'; + data_a : in std_logic_vector(width_a - 1 downto 0):= (others => '1'); + data_b : in std_logic_vector(width_b - 1 downto 0):= (others => '1'); + address_a : in std_logic_vector(widthad_a - 1 downto 0); + address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1'); + + clock0 : in std_logic := '1'; + clock1 : in std_logic := 'Z'; + clocken0 : in std_logic := '1'; + clocken1 : in std_logic := '1'; + clocken2 : in std_logic := '1'; + clocken3 : in std_logic := '1'; + aclr0 : in std_logic := '0'; + aclr1 : in std_logic := '0'; + byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1'); + byteena_b : in std_logic_vector( (width_byteena_b - 1) downto 0) := (others => 'Z'); + + addressstall_a : in std_logic := '0'; + addressstall_b : in std_logic := '0'; + + q_a : out std_logic_vector(width_a - 1 downto 0); + q_b : out std_logic_vector(width_b - 1 downto 0); + + eccstatus : out std_logic_vector(width_eccstatus-1 downto 0) := (others => '0') ); +end component; + +end altera_lnsim_components;