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- added INT_O line for VGA

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- mapped VGA-Int to IRQ5
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git-svn-id: http://moon:8086/svn/vhdl/trunk@645 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-08 21:51:06 +00:00
parent f0ad8cc351
commit fd0896f374
1 changed files with 4 additions and 1 deletions
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projects/mips_sys/src/mips_sys.vhd
+4 -1
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@@ -295,6 +295,7 @@ ARCHITECTURE behavior OF mips_sys IS
MDAT_O : out unsigned(63 downto 0); MDAT_O : out unsigned(63 downto 0);
-- JBUS Slave signals -- JBUS Slave signals
INT_O : out STD_LOGIC;
CYC_I : in STD_LOGIC; CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC; STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC; WE_I : in STD_LOGIC;
@@ -428,6 +429,7 @@ ARCHITECTURE behavior OF mips_sys IS
signal SRDY_O_uart1 : std_logic; signal SRDY_O_uart1 : std_logic;
signal SDAT_O_uart1 : unsigned(31 downto 0); signal SDAT_O_uart1 : unsigned(31 downto 0);
signal INT_O_vga : std_logic;
signal CYC_I_vga : std_logic; signal CYC_I_vga : std_logic;
signal ACK_O_vga : std_logic; signal ACK_O_vga : std_logic;
signal SRDY_O_vga : std_logic; signal SRDY_O_vga : std_logic;
@@ -552,7 +554,7 @@ int_sample:
process(CLK_O) process(CLK_O)
begin begin
if rising_edge(CLK_O) then if rising_edge(CLK_O) then
INT <= int_timer & (INT_O_ps2_0 or INT_O_ps2_1) & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4); INT <= int_timer & (INT_O_ps2_0 or INT_O_ps2_1) & (INT_O_vga or (gpo1(2) and INT_O_ac97)) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4);
end if; end if;
end process; end process;
@@ -940,6 +942,7 @@ inst_vga_frontend : vga_frontend64
MDAT_O => MDAT_O_vga, MDAT_O => MDAT_O_vga,
-- JBUS Slave signals -- JBUS Slave signals
INT_O => INT_O_vga,
CYC_I => CYC_I_vga, CYC_I => CYC_I_vga,
STB_I => STB_O, STB_I => STB_O,
WE_I => WE_O, WE_I => WE_O,