- fixed A0
git-svn-id: http://moon:8086/svn/vhdl/trunk@1271 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -198,8 +198,11 @@ part_clk <= clk0 after TPD_BOARD_SIM;
|
||||
part_ctrl_reg.addr <= (others=>'0');
|
||||
part_ctrl_reg.cke <= '0';
|
||||
else
|
||||
part_ctrl_reg <= phy_ctrl.part;
|
||||
data_reg_w <= phy_in.wr_data;
|
||||
part_ctrl_reg <= phy_ctrl.part;
|
||||
dm_reg_w <= (others=>'0');
|
||||
if (phy_ctrl.we = '1') then
|
||||
data_reg_w <= phy_in.wr_data;
|
||||
dm_reg_w <= phy_in.wr_dm;
|
||||
end if;
|
||||
we_reg <= phy_ctrl.we;
|
||||
end if;
|
||||
|
||||
@@ -96,8 +96,6 @@ architecture struct of sdram_ctrl_frontend_wb16 is
|
||||
|
||||
signal write_fifo_data_avail : std_logic;
|
||||
signal read_fifo_rdy : std_logic;
|
||||
signal write_piso_data_dout : unsigned(PART_DATA_WIDTH-1 downto 0);
|
||||
signal write_piso_dm_dout : unsigned(PART_DM_WIDTH-1 downto 0);
|
||||
|
||||
alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
|
||||
alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
|
||||
@@ -177,7 +175,7 @@ begin
|
||||
din => write_fifo_data_out,
|
||||
dout_vld => open,
|
||||
shift_en => phy_out.wr_data_re,
|
||||
dout => write_piso_data_dout
|
||||
dout => phy_in.wr_data
|
||||
|
||||
);
|
||||
|
||||
@@ -197,7 +195,7 @@ begin
|
||||
din => write_fifo_dm_out,
|
||||
dout_vld => open,
|
||||
shift_en => phy_out.wr_data_re,
|
||||
dout => write_piso_dm_dout
|
||||
dout => phy_in.wr_dm
|
||||
|
||||
);
|
||||
|
||||
@@ -283,22 +281,15 @@ begin
|
||||
write_fifo_dm_in <= not SEL_I;
|
||||
cat_fifo_we <= STB_I and rdy;
|
||||
cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ;
|
||||
addr_fifo_in <= "00" & ADDR_I(22 downto 1);
|
||||
tag_fifo_in <= "000" & ADDR_I(0);
|
||||
addr_fifo_in <= "00" & ADDR_I(22 downto 2) & '0';
|
||||
tag_fifo_in <= "000" & ADDR_I(1);
|
||||
|
||||
cat_fifo_re <= u_cmd_we and (not u_busy);
|
||||
u_cmd_we <= (not cat_fifo_empty);
|
||||
u_cmd <= cmd_fifo_out;
|
||||
u_addr <= addr_fifo_out;
|
||||
u_tag_in <= tag_fifo_out;
|
||||
-- phy_in.wr_dm <= write_fifo_dm_out;
|
||||
-- phy_in.wr_data <= write_fifo_data_out;
|
||||
phy_in.wr_data <= write_piso_data_dout when phy_out.tag_wr(0) = '0' else (write_piso_data_dout(PART_DATA_WIDTH/2-1 downto 0) & write_piso_data_dout(PART_DATA_WIDTH-1 downto PART_DATA_WIDTH/2));
|
||||
phy_in.wr_dm <= write_piso_dm_dout when phy_out.tag_wr(0) = '0' else (write_piso_dm_dout(PART_DM_WIDTH/2-1 downto 0) & write_piso_dm_dout(PART_DM_WIDTH-1 downto PART_DM_WIDTH/2));
|
||||
|
||||
-- write_fifo_re <= phy_out.wr_data_re and (not write_fifo_empty);
|
||||
read_fifo_re <= (not read_fifo_empty) and MRDY_I;
|
||||
-- read_fifo_we <= phy_out.rd_data_we;
|
||||
-- read_fifo_data_in <= phy_out.rd_data & phy_out.rd_data;
|
||||
|
||||
end architecture struct;
|
||||
|
||||
@@ -241,6 +241,51 @@ STIMULUS: process
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 300*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
wait until rising_edge(CLK_O);
|
||||
-- 1-word burst cycle
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
|
||||
SEL_O <= "1000";
|
||||
ADDR_O <= X"0000_0080";
|
||||
DAT_O <= X"1100_0000";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
SEL_O <= "0100";
|
||||
ADDR_O <= X"0000_0081";
|
||||
DAT_O <= X"0022_0000";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
SEL_O <= "0010";
|
||||
ADDR_O <= X"0000_0082";
|
||||
DAT_O <= X"0000_3300";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
SEL_O <= "0001";
|
||||
ADDR_O <= X"0000_0083";
|
||||
DAT_O <= X"0000_0044";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
-- 1-word burst cycle
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
|
||||
SEL_O <= "1111";
|
||||
ADDR_O <= X"0000_0080";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
CYC_O <= '0';
|
||||
wait until rising_edge(CLK_O) and ACK_I = '1';
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
------------------------------------------------------------
|
||||
wait for 3*CLK_PERIOD;
|
||||
------------------------------------------------------------
|
||||
|
||||
Reference in New Issue
Block a user